2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
62 #include "libiberty.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
73 char* pr_addr
PARAMS ((SIM_ADDR addr
));
74 char* pr_uword64
PARAMS ((uword64 addr
));
77 /* Get the simulator engine description, without including the code: */
82 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
87 /* The following reserved instruction value is used when a simulator
88 trap is required. NOTE: Care must be taken, since this value may be
89 used in later revisions of the MIPS ISA. */
90 #define RSVD_INSTRUCTION (0x00000005)
91 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
93 #define RSVD_INSTRUCTION_ARG_SHIFT 6
94 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
97 /* Bits in the Debug register */
98 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
99 #define Debug_DM 0x40000000 /* Debug Mode */
100 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
106 /*---------------------------------------------------------------------------*/
107 /*-- GDB simulator interface ------------------------------------------------*/
108 /*---------------------------------------------------------------------------*/
110 static void ColdReset
PARAMS((SIM_DESC sd
));
112 /*---------------------------------------------------------------------------*/
116 #define DELAYSLOT() {\
117 if (STATE & simDELAYSLOT)\
118 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
119 STATE |= simDELAYSLOT;\
122 #define JALDELAYSLOT() {\
124 STATE |= simJALDELAYSLOT;\
128 STATE &= ~simDELAYSLOT;\
129 STATE |= simSKIPNEXT;\
132 #define CANCELDELAYSLOT() {\
134 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
137 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
138 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
140 #define K0BASE (0x80000000)
141 #define K0SIZE (0x20000000)
142 #define K1BASE (0xA0000000)
143 #define K1SIZE (0x20000000)
144 #define MONITOR_BASE (0xBFC00000)
145 #define MONITOR_SIZE (1 << 11)
146 #define MEM_SIZE (2 << 20)
149 static char *tracefile
= "trace.din"; /* default filename for trace log */
150 FILE *tracefh
= NULL
;
151 static void open_trace
PARAMS((SIM_DESC sd
));
154 #define OPTION_DINERO_TRACE 200
155 #define OPTION_DINERO_FILE 201
158 mips_option_handler (sd
, opt
, arg
)
166 case OPTION_DINERO_TRACE
: /* ??? */
168 /* Eventually the simTRACE flag could be treated as a toggle, to
169 allow external control of the program points being traced
170 (i.e. only from main onwards, excluding the run-time setup,
172 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
174 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
177 else if (strcmp (arg
, "yes") == 0)
179 else if (strcmp (arg
, "no") == 0)
181 else if (strcmp (arg
, "on") == 0)
183 else if (strcmp (arg
, "off") == 0)
187 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
194 Simulator constructed without dinero tracing support (for performance).\n\
195 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
199 case OPTION_DINERO_FILE
:
201 if (optarg
!= NULL
) {
203 tmp
= (char *)malloc(strlen(optarg
) + 1);
206 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
212 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
223 static const OPTION mips_options
[] =
225 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
226 '\0', "on|off", "Enable dinero tracing",
227 mips_option_handler
},
228 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
229 '\0', "FILE", "Write dinero trace to FILE",
230 mips_option_handler
},
231 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
235 int interrupt_pending
;
238 interrupt_event (SIM_DESC sd
, void *data
)
240 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
243 interrupt_pending
= 0;
244 SignalExceptionInterrupt ();
246 else if (!interrupt_pending
)
247 sim_events_schedule (sd
, 1, interrupt_event
, data
);
252 /*---------------------------------------------------------------------------*/
253 /*-- GDB simulator interface ------------------------------------------------*/
254 /*---------------------------------------------------------------------------*/
257 sim_open (kind
, cb
, abfd
, argv
)
263 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
264 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
266 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
268 /* FIXME: watchpoints code shouldn't need this */
269 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
270 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
271 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
275 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
277 sim_add_option_table (sd
, mips_options
);
279 /* Allocate core managed memory */
282 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
283 /* For compatibility with the old code - under this (at level one)
284 are the kernel spaces K0 & K1. Both of these map to a single
285 smaller sub region */
286 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
288 MEM_SIZE
, /* actual size */
291 /* getopt will print the error message so we just have to exit if this fails.
292 FIXME: Hmmm... in the case of gdb we need getopt to call
294 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
296 /* Uninstall the modules to avoid memory leaks,
297 file descriptor leaks, etc. */
298 sim_module_uninstall (sd
);
302 /* check for/establish the a reference program image */
303 if (sim_analyze_program (sd
,
304 (STATE_PROG_ARGV (sd
) != NULL
305 ? *STATE_PROG_ARGV (sd
)
309 sim_module_uninstall (sd
);
313 /* Configure/verify the target byte order and other runtime
314 configuration options */
315 if (sim_config (sd
) != SIM_RC_OK
)
317 sim_module_uninstall (sd
);
321 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
323 /* Uninstall the modules to avoid memory leaks,
324 file descriptor leaks, etc. */
325 sim_module_uninstall (sd
);
329 /* verify assumptions the simulator made about the host type system.
330 This macro does not return if there is a problem */
331 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
332 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
335 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
336 and DOUBLE binary formats. This is a bit nasty, requiring that we
337 trust the explicit manifests held in the source: */
338 /* TODO: We need to cope with the simulated target and the host not
339 having the same endianness. This will require the high and low
340 words of a (double) to be swapped when converting between the
341 host and the simulated target. */
349 s
.d
= (double)523.2939453125;
351 if ((s
.i
[0] == 0 && (s
.f
[1] != (float)4.01102924346923828125
352 || s
.i
[1] != 0x40805A5A))
353 || (s
.i
[1] == 0 && (s
.f
[0] != (float)4.01102924346923828125
354 || s
.i
[0] != 0x40805A5A)))
356 fprintf(stderr
,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
362 /* This is NASTY, in that we are assuming the size of specific
366 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
368 cpu
->register_widths
[rn
] = GPRLEN
;
369 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
370 cpu
->register_widths
[rn
] = GPRLEN
;
371 else if ((rn
>= 33) && (rn
<= 37))
372 cpu
->register_widths
[rn
] = GPRLEN
;
373 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
374 cpu
->register_widths
[rn
] = 32;
376 cpu
->register_widths
[rn
] = 0;
378 /* start-sanitize-r5900 */
380 /* set the 5900 "upper" registers to 64 bits */
381 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
382 cpu
->register_widths
[rn
] = 64;
383 /* end-sanitize-r5900 */
387 if (STATE
& simTRACE
)
391 /* Write the monitor trap address handlers into the monitor (eeprom)
392 address space. This can only be done once the target endianness
393 has been determined. */
396 /* Entry into the IDT monitor is via fixed address vectors, and
397 not using machine instructions. To avoid clashing with use of
398 the MIPS TRAP system, we place our own (simulator specific)
399 "undefined" instructions into the relevant vector slots. */
400 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
402 address_word vaddr
= (MONITOR_BASE
+ loop
);
403 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
405 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
407 /* The PMON monitor uses the same address space, but rather than
408 branching into it the address of a routine is loaded. We can
409 cheat for the moment, and direct the PMON routine to IDT style
410 instructions within the monitor space. This relies on the IDT
411 monitor not using the locations from 0xBFC00500 onwards as its
413 for (loop
= 0; (loop
< 24); loop
++)
415 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
416 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
432 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
434 case 8: /* cliexit */
437 case 11: /* flush_cache */
441 /* FIXME - should monitor_base be SIM_ADDR?? */
442 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
444 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
446 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
448 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
460 tracefh
= fopen(tracefile
,"wb+");
463 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
470 sim_close (sd
, quitting
)
475 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
478 /* "quitting" is non-zero if we cannot hang on errors */
480 /* Ensure that any resources allocated through the callback
481 mechanism are released: */
482 sim_io_shutdown (sd
);
485 if (tracefh
!= NULL
&& tracefh
!= stderr
)
490 /* FIXME - free SD */
497 sim_write (sd
,addr
,buffer
,size
)
500 unsigned char *buffer
;
504 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
506 /* Return the number of bytes written, or zero if error. */
508 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
511 /* We use raw read and write routines, since we do not want to count
512 the GDB memory accesses in our statistics gathering. */
514 for (index
= 0; index
< size
; index
++)
516 address_word vaddr
= (address_word
)addr
+ index
;
519 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
521 if (sim_core_write_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
529 sim_read (sd
,addr
,buffer
,size
)
532 unsigned char *buffer
;
536 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
538 /* Return the number of bytes read, or zero if error. */
540 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
543 for (index
= 0; (index
< size
); index
++)
545 address_word vaddr
= (address_word
)addr
+ index
;
548 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
550 if (sim_core_read_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
558 sim_store_register (sd
,rn
,memory
)
561 unsigned char *memory
;
563 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
564 /* NOTE: gdb (the client) stores registers in target byte order
565 while the simulator uses host byte order */
567 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
570 /* Unfortunately this suffers from the same problem as the register
571 numbering one. We need to know what the width of each logical
572 register number is for the architecture being simulated. */
574 if (cpu
->register_widths
[rn
] == 0)
575 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
576 /* start-sanitize-r5900 */
577 else if (rn
== REGISTER_SA
)
578 SA
= T2H_8(*(uword64
*)memory
);
579 else if (rn
> LAST_EMBED_REGNUM
)
580 cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1] = T2H_8(*(uword64
*)memory
);
581 /* end-sanitize-r5900 */
582 else if (cpu
->register_widths
[rn
] == 32)
583 cpu
->registers
[rn
] = T2H_4 (*(unsigned int*)memory
);
585 cpu
->registers
[rn
] = T2H_8 (*(uword64
*)memory
);
591 sim_fetch_register (sd
,rn
,memory
)
594 unsigned char *memory
;
596 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
597 /* NOTE: gdb (the client) stores registers in target byte order
598 while the simulator uses host byte order */
600 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
603 if (cpu
->register_widths
[rn
] == 0)
604 sim_io_eprintf(sd
,"Invalid register width for %d (register fetch ignored)\n",rn
);
605 /* start-sanitize-r5900 */
606 else if (rn
== REGISTER_SA
)
607 *((uword64
*)memory
) = H2T_8(SA
);
608 else if (rn
> LAST_EMBED_REGNUM
)
609 *((uword64
*)memory
) = H2T_8(cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1]);
610 /* end-sanitize-r5900 */
611 else if (cpu
->register_widths
[rn
] == 32)
612 *((unsigned int *)memory
) = H2T_4 ((unsigned int)(cpu
->registers
[rn
] & 0xFFFFFFFF));
613 else /* 64bit register */
614 *((uword64
*)memory
) = H2T_8 (cpu
->registers
[rn
]);
621 sim_info (sd
,verbose
)
625 /* Accessed from the GDB "info files" command: */
626 if (STATE_VERBOSE_P (sd
) || verbose
)
629 sim_io_printf (sd
, "MIPS %d-bit %s endian simulator\n",
630 (PROCESSOR_64BIT
? 64 : 32),
631 (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
? "Big" : "Little"));
633 #if !defined(FASTSIM)
634 /* It would be a useful feature, if when performing multi-cycle
635 simulations (rather than single-stepping) we keep the start and
636 end times of the execution, so that we can give a performance
637 figure for the simulator. */
638 #endif /* !FASTSIM */
639 sim_io_printf (sd
, "Number of execution cycles = %ld\n",
640 (long) sim_events_time (sd
));
642 /* print information pertaining to MIPS ISA and architecture being simulated */
643 /* things that may be interesting */
644 /* instructions executed - if available */
645 /* cycles executed - if available */
646 /* pipeline stalls - if available */
647 /* virtual time taken */
649 /* profiling frequency */
653 profile_print (sd
, STATE_VERBOSE_P (sd
), NULL
, NULL
);
658 sim_create_inferior (sd
, abfd
, argv
,env
)
666 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
674 /* override PC value set by ColdReset () */
676 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
678 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
679 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
683 #if 0 /* def DEBUG */
686 /* We should really place the argv slot values into the argument
687 registers, and onto the stack as required. However, this
688 assumes that we have a stack defined, which is not
689 necessarily true at the moment. */
691 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
692 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
693 printf("DBG: arg \"%s\"\n",*cptr
);
701 sim_do_command (sd
,cmd
)
705 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
706 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
710 /*---------------------------------------------------------------------------*/
711 /*-- Private simulator support interface ------------------------------------*/
712 /*---------------------------------------------------------------------------*/
714 /* Read a null terminated string from memory, return in a buffer */
723 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
725 buf
= NZALLOC (char, nr
+ 1);
726 sim_read (sd
, addr
, buf
, nr
);
730 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
732 sim_monitor (SIM_DESC sd
,
738 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
741 /* The IDT monitor actually allows two instructions per vector
742 slot. However, the simulator currently causes a trap on each
743 individual instruction. We cheat, and lose the bottom bit. */
746 /* The following callback functions are available, however the
747 monitor we are simulating does not make use of them: get_errno,
748 isatty, lseek, rename, system, time and unlink */
752 case 6: /* int open(char *path,int flags) */
754 char *path
= fetch_str (sd
, A0
);
755 V0
= sim_io_open (sd
, path
, (int)A1
);
760 case 7: /* int read(int file,char *ptr,int len) */
764 char *buf
= zalloc (nr
);
765 V0
= sim_io_read (sd
, fd
, buf
, nr
);
766 sim_write (sd
, A1
, buf
, nr
);
771 case 8: /* int write(int file,char *ptr,int len) */
775 char *buf
= zalloc (nr
);
776 sim_read (sd
, A1
, buf
, nr
);
777 V0
= sim_io_write (sd
, fd
, buf
, nr
);
782 case 10: /* int close(int file) */
784 V0
= sim_io_close (sd
, (int)A0
);
788 case 2: /* Densan monitor: char inbyte(int waitflag) */
790 if (A0
== 0) /* waitflag == NOWAIT */
793 /* Drop through to case 11 */
795 case 11: /* char inbyte(void) */
798 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
800 sim_io_error(sd
,"Invalid return from character read");
808 case 3: /* Densan monitor: void co(char chr) */
809 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
811 char tmp
= (char)(A0
& 0xFF);
812 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
816 case 17: /* void _exit() */
818 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
819 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
820 (unsigned int)(A0
& 0xFFFFFFFF));
824 case 28 : /* PMON flush_cache */
827 case 55: /* void get_mem_info(unsigned int *ptr) */
828 /* in: A0 = pointer to three word memory location */
829 /* out: [A0 + 0] = size */
830 /* [A0 + 4] = instruction cache size */
831 /* [A0 + 8] = data cache size */
833 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
835 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
836 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
840 case 158 : /* PMON printf */
841 /* in: A0 = pointer to format string */
842 /* A1 = optional argument 1 */
843 /* A2 = optional argument 2 */
844 /* A3 = optional argument 3 */
846 /* The following is based on the PMON printf source */
850 signed_word
*ap
= &A1
; /* 1st argument */
851 /* This isn't the quickest way, since we call the host print
852 routine for every character almost. But it does avoid
853 having to allocate and manage a temporary string buffer. */
854 /* TODO: Include check that we only use three arguments (A1,
856 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
861 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
862 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
863 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
865 if (strchr ("dobxXulscefg%", s
))
880 else if (c
>= '1' && c
<= '9')
884 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
887 n
= (unsigned int)strtol(tmp
,NULL
,10);
900 sim_io_printf (sd
, "%%");
905 address_word p
= *ap
++;
907 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
908 sim_io_printf(sd
, "%c", ch
);
911 sim_io_printf(sd
,"(null)");
914 sim_io_printf (sd
, "%c", (int)*ap
++);
919 sim_read (sd
, s
++, &c
, 1);
923 sim_read (sd
, s
++, &c
, 1);
926 if (strchr ("dobxXu", c
))
928 word64 lv
= (word64
) *ap
++;
930 sim_io_printf(sd
,"<binary not supported>");
933 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
935 sim_io_printf(sd
, tmp
, lv
);
937 sim_io_printf(sd
, tmp
, (int)lv
);
940 else if (strchr ("eEfgG", c
))
942 double dbl
= *(double*)(ap
++);
943 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
944 sim_io_printf (sd
, tmp
, dbl
);
950 sim_io_printf(sd
, "%c", c
);
956 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
957 reason
, pr_addr(cia
));
963 /* Store a word into memory. */
966 store_word (SIM_DESC sd
,
975 if ((vaddr
& 3) != 0)
976 SignalExceptionAddressStore ();
979 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
982 const uword64 mask
= 7;
986 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
987 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
988 memval
= ((uword64
) val
) << (8 * byte
);
989 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
995 /* Load a word from memory. */
998 load_word (SIM_DESC sd
,
1003 if ((vaddr
& 3) != 0)
1004 SignalExceptionAddressLoad ();
1010 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1013 const uword64 mask
= 0x7;
1014 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1015 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1019 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1020 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1022 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1023 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1030 /* Simulate the mips16 entry and exit pseudo-instructions. These
1031 would normally be handled by the reserved instruction exception
1032 code, but for ease of simulation we just handle them directly. */
1035 mips16_entry (SIM_DESC sd
,
1040 int aregs
, sregs
, rreg
;
1043 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1046 aregs
= (insn
& 0x700) >> 8;
1047 sregs
= (insn
& 0x0c0) >> 6;
1048 rreg
= (insn
& 0x020) >> 5;
1050 /* This should be checked by the caller. */
1059 /* This is the entry pseudo-instruction. */
1061 for (i
= 0; i
< aregs
; i
++)
1062 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1070 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1073 for (i
= 0; i
< sregs
; i
++)
1076 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1084 /* This is the exit pseudo-instruction. */
1091 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1094 for (i
= 0; i
< sregs
; i
++)
1097 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1105 FGR
[0] = WORD64LO (GPR
[4]);
1106 FPR_STATE
[0] = fmt_uninterpreted
;
1108 else if (aregs
== 6)
1110 FGR
[0] = WORD64LO (GPR
[5]);
1111 FGR
[1] = WORD64LO (GPR
[4]);
1112 FPR_STATE
[0] = fmt_uninterpreted
;
1113 FPR_STATE
[1] = fmt_uninterpreted
;
1115 #endif /* defined(HASFPU) */
1121 /*-- trace support ----------------------------------------------------------*/
1123 /* The TRACE support is provided (if required) in the memory accessing
1124 routines. Since we are also providing the architecture specific
1125 features, the architecture simulation code can also deal with
1126 notifying the TRACE world of cache flushes, etc. Similarly we do
1127 not need to provide profiling support in the simulator engine,
1128 since we can sample in the instruction fetch control loop. By
1129 defining the TRACE manifest, we add tracing as a run-time
1133 /* Tracing by default produces "din" format (as required by
1134 dineroIII). Each line of such a trace file *MUST* have a din label
1135 and address field. The rest of the line is ignored, so comments can
1136 be included if desired. The first field is the label which must be
1137 one of the following values:
1142 3 escape record (treated as unknown access type)
1143 4 escape record (causes cache flush)
1145 The address field is a 32bit (lower-case) hexadecimal address
1146 value. The address should *NOT* be preceded by "0x".
1148 The size of the memory transfer is not important when dealing with
1149 cache lines (as long as no more than a cache line can be
1150 transferred in a single operation :-), however more information
1151 could be given following the dineroIII requirement to allow more
1152 complete memory and cache simulators to provide better
1153 results. i.e. the University of Pisa has a cache simulator that can
1154 also take bus size and speed as (variable) inputs to calculate
1155 complete system performance (a much more useful ability when trying
1156 to construct an end product, rather than a processor). They
1157 currently have an ARM version of their tool called ChARM. */
1161 dotrace (SIM_DESC sd
,
1169 if (STATE
& simTRACE
) {
1171 fprintf(tracefh
,"%d %s ; width %d ; ",
1175 va_start(ap
,comment
);
1176 vfprintf(tracefh
,comment
,ap
);
1178 fprintf(tracefh
,"\n");
1180 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1181 we may be generating 64bit ones, we should put the hi-32bits of the
1182 address into the comment field. */
1184 /* TODO: Provide a buffer for the trace lines. We can then avoid
1185 performing writes until the buffer is filled, or the file is
1188 /* NOTE: We could consider adding a comment field to the "din" file
1189 produced using type 3 markers (unknown access). This would then
1190 allow information about the program that the "din" is for, and
1191 the MIPs world that was being simulated, to be placed into the
1198 /*---------------------------------------------------------------------------*/
1199 /*-- simulator engine -------------------------------------------------------*/
1200 /*---------------------------------------------------------------------------*/
1203 ColdReset (SIM_DESC sd
)
1206 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1208 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1209 /* RESET: Fixed PC address: */
1210 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1211 /* The reset vector address is in the unmapped, uncached memory space. */
1213 SR
&= ~(status_SR
| status_TS
| status_RP
);
1214 SR
|= (status_ERL
| status_BEV
);
1216 /* Cheat and allow access to the complete register set immediately */
1217 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1218 && WITH_TARGET_WORD_BITSIZE
== 64)
1219 SR
|= status_FR
; /* 64bit registers */
1221 /* Ensure that any instructions with pending register updates are
1225 for (loop
= 0; (loop
< PSLOTS
); loop
++)
1226 PENDING_SLOT_REG
[loop
] = (LAST_EMBED_REGNUM
+ 1);
1227 PENDING_IN
= PENDING_OUT
= PENDING_TOTAL
= 0;
1230 /* Initialise the FPU registers to the unknown state */
1231 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1234 for (rn
= 0; (rn
< 32); rn
++)
1235 FPR_STATE
[rn
] = fmt_uninterpreted
;
1241 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1243 /* Translate a virtual address to a physical address and cache
1244 coherence algorithm describing the mechanism used to resolve the
1245 memory reference. Given the virtual address vAddr, and whether the
1246 reference is to Instructions ot Data (IorD), find the corresponding
1247 physical address (pAddr) and the cache coherence algorithm (CCA)
1248 used to resolve the reference. If the virtual address is in one of
1249 the unmapped address spaces the physical address and the CCA are
1250 determined directly by the virtual address. If the virtual address
1251 is in one of the mapped address spaces then the TLB is used to
1252 determine the physical address and access type; if the required
1253 translation is not present in the TLB or the desired access is not
1254 permitted the function fails and an exception is taken.
1256 NOTE: Normally (RAW == 0), when address translation fails, this
1257 function raises an exception and does not return. */
1260 address_translation (SIM_DESC sd
,
1266 address_word
*pAddr
,
1270 int res
= -1; /* TRUE : Assume good return */
1273 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1276 /* Check that the address is valid for this memory model */
1278 /* For a simple (flat) memory model, we simply pass virtual
1279 addressess through (mostly) unchanged. */
1280 vAddr
&= 0xFFFFFFFF;
1282 *pAddr
= vAddr
; /* default for isTARGET */
1283 *CCA
= Uncached
; /* not used for isHOST */
1288 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1290 /* Prefetch data from memory. Prefetch is an advisory instruction for
1291 which an implementation specific action is taken. The action taken
1292 may increase performance, but must not change the meaning of the
1293 program, or alter architecturally-visible state. */
1296 prefetch (SIM_DESC sd
,
1306 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1309 /* For our simple memory model we do nothing */
1313 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1315 /* Load a value from memory. Use the cache and main memory as
1316 specified in the Cache Coherence Algorithm (CCA) and the sort of
1317 access (IorD) to find the contents of AccessLength memory bytes
1318 starting at physical location pAddr. The data is returned in the
1319 fixed width naturally-aligned memory element (MemElem). The
1320 low-order two (or three) bits of the address and the AccessLength
1321 indicate which of the bytes within MemElem needs to be given to the
1322 processor. If the memory access type of the reference is uncached
1323 then only the referenced bytes are read from memory and valid
1324 within the memory element. If the access type is cached, and the
1325 data is not present in cache, an implementation specific size and
1326 alignment block of memory is read and loaded into the cache to
1327 satisfy a load reference. At a minimum, the block is the entire
1330 load_memory (SIM_DESC sd
,
1345 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1348 #if defined(WARN_MEM)
1349 if (CCA
!= uncached
)
1350 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1351 #endif /* WARN_MEM */
1353 /* If instruction fetch then we need to check that the two lo-order
1354 bits are zero, otherwise raise a InstructionFetch exception: */
1355 if ((IorD
== isINSTRUCTION
)
1356 && ((pAddr
& 0x3) != 0)
1357 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1358 SignalExceptionInstructionFetch ();
1360 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1362 /* In reality this should be a Bus Error */
1363 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1365 (LOADDRMASK
+ 1) << 2,
1370 dotrace (SD
, CPU
, tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1373 /* Read the specified number of bytes from memory. Adjust for
1374 host/target byte ordering/ Align the least significant byte
1377 switch (AccessLength
)
1379 case AccessLength_QUADWORD
:
1381 unsigned_16 val
= sim_core_read_aligned_16 (cpu
, NULL_CIA
,
1382 sim_core_read_map
, pAddr
);
1383 value1
= VH8_16 (val
);
1384 value
= VL8_16 (val
);
1387 case AccessLength_DOUBLEWORD
:
1388 value
= sim_core_read_aligned_8 (cpu
, NULL_CIA
,
1389 sim_core_read_map
, pAddr
);
1391 case AccessLength_SEPTIBYTE
:
1392 value
= sim_core_read_misaligned_7 (cpu
, NULL_CIA
,
1393 sim_core_read_map
, pAddr
);
1394 case AccessLength_SEXTIBYTE
:
1395 value
= sim_core_read_misaligned_6 (cpu
, NULL_CIA
,
1396 sim_core_read_map
, pAddr
);
1397 case AccessLength_QUINTIBYTE
:
1398 value
= sim_core_read_misaligned_5 (cpu
, NULL_CIA
,
1399 sim_core_read_map
, pAddr
);
1400 case AccessLength_WORD
:
1401 value
= sim_core_read_aligned_4 (cpu
, NULL_CIA
,
1402 sim_core_read_map
, pAddr
);
1404 case AccessLength_TRIPLEBYTE
:
1405 value
= sim_core_read_misaligned_3 (cpu
, NULL_CIA
,
1406 sim_core_read_map
, pAddr
);
1407 case AccessLength_HALFWORD
:
1408 value
= sim_core_read_aligned_2 (cpu
, NULL_CIA
,
1409 sim_core_read_map
, pAddr
);
1411 case AccessLength_BYTE
:
1412 value
= sim_core_read_aligned_1 (cpu
, NULL_CIA
,
1413 sim_core_read_map
, pAddr
);
1420 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1421 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1424 /* See also store_memory. */
1425 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1428 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1429 shifted to the most significant byte position. */
1430 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1432 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1433 is already in the correct postition. */
1434 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1438 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1439 pr_uword64(value1
),pr_uword64(value
));
1443 if (memval1p
) *memval1p
= value1
;
1447 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1449 /* Store a value to memory. The specified data is stored into the
1450 physical location pAddr using the memory hierarchy (data caches and
1451 main memory) as specified by the Cache Coherence Algorithm
1452 (CCA). The MemElem contains the data for an aligned, fixed-width
1453 memory element (word for 32-bit processors, doubleword for 64-bit
1454 processors), though only the bytes that will actually be stored to
1455 memory need to be valid. The low-order two (or three) bits of pAddr
1456 and the AccessLength field indicates which of the bytes within the
1457 MemElem data should actually be stored; only these bytes in memory
1461 store_memory (SIM_DESC sd
,
1467 uword64 MemElem1
, /* High order 64 bits */
1472 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1475 #if defined(WARN_MEM)
1476 if (CCA
!= uncached
)
1477 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1478 #endif /* WARN_MEM */
1480 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1481 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1484 dotrace (SD
, CPU
, tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1488 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1491 /* See also load_memory */
1492 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1495 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1496 shifted to the most significant byte position. */
1497 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1499 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1500 is already in the correct postition. */
1501 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1505 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1508 switch (AccessLength
)
1510 case AccessLength_QUADWORD
:
1512 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1513 sim_core_write_aligned_16 (cpu
, NULL_CIA
,
1514 sim_core_write_map
, pAddr
, val
);
1517 case AccessLength_DOUBLEWORD
:
1518 sim_core_write_aligned_8 (cpu
, NULL_CIA
,
1519 sim_core_write_map
, pAddr
, MemElem
);
1521 case AccessLength_SEPTIBYTE
:
1522 sim_core_write_misaligned_7 (cpu
, NULL_CIA
,
1523 sim_core_write_map
, pAddr
, MemElem
);
1525 case AccessLength_SEXTIBYTE
:
1526 sim_core_write_misaligned_6 (cpu
, NULL_CIA
,
1527 sim_core_write_map
, pAddr
, MemElem
);
1529 case AccessLength_QUINTIBYTE
:
1530 sim_core_write_misaligned_5 (cpu
, NULL_CIA
,
1531 sim_core_write_map
, pAddr
, MemElem
);
1533 case AccessLength_WORD
:
1534 sim_core_write_aligned_4 (cpu
, NULL_CIA
,
1535 sim_core_write_map
, pAddr
, MemElem
);
1537 case AccessLength_TRIPLEBYTE
:
1538 sim_core_write_misaligned_3 (cpu
, NULL_CIA
,
1539 sim_core_write_map
, pAddr
, MemElem
);
1541 case AccessLength_HALFWORD
:
1542 sim_core_write_aligned_2 (cpu
, NULL_CIA
,
1543 sim_core_write_map
, pAddr
, MemElem
);
1545 case AccessLength_BYTE
:
1546 sim_core_write_aligned_1 (cpu
, NULL_CIA
,
1547 sim_core_write_map
, pAddr
, MemElem
);
1558 ifetch32 (SIM_DESC sd
,
1563 /* Copy the action of the LW instruction */
1564 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1565 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1568 unsigned32 instruction
;
1571 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1572 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1573 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1574 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1575 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1580 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1581 /* Order loads and stores to synchronise shared memory. Perform the
1582 action necessary to make the effects of groups of synchronizable
1583 loads and stores indicated by stype occur in the same order for all
1586 sync_operation (SIM_DESC sd
,
1592 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1597 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1598 /* Signal an exception condition. This will result in an exception
1599 that aborts the instruction. The instruction operation pseudocode
1600 will never see a return from this function call. */
1603 signal_exception (SIM_DESC sd
,
1611 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1614 /* Ensure that any active atomic read/modify/write operation will fail: */
1617 switch (exception
) {
1618 /* TODO: For testing purposes I have been ignoring TRAPs. In
1619 reality we should either simulate them, or allow the user to
1620 ignore them at run-time.
1623 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1629 unsigned int instruction
;
1632 va_start(ap
,exception
);
1633 instruction
= va_arg(ap
,unsigned int);
1636 code
= (instruction
>> 6) & 0xFFFFF;
1638 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1639 code
, pr_addr(cia
));
1643 case DebugBreakPoint
:
1644 if (! (Debug
& Debug_DM
))
1650 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1651 DEPC
= cia
- 4; /* reference the branch instruction */
1655 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1659 Debug
|= Debug_DM
; /* in debugging mode */
1660 Debug
|= Debug_DBp
; /* raising a DBp exception */
1662 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1666 case ReservedInstruction
:
1669 unsigned int instruction
;
1670 va_start(ap
,exception
);
1671 instruction
= va_arg(ap
,unsigned int);
1673 /* Provide simple monitor support using ReservedInstruction
1674 exceptions. The following code simulates the fixed vector
1675 entry points into the IDT monitor by causing a simulator
1676 trap, performing the monitor operation, and returning to
1677 the address held in the $ra register (standard PCS return
1678 address). This means we only need to pre-load the vector
1679 space with suitable instruction values. For systems were
1680 actual trap instructions are used, we would not need to
1681 perform this magic. */
1682 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1684 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1685 /* NOTE: This assumes that a branch-and-link style
1686 instruction was used to enter the vector (which is the
1687 case with the current IDT monitor). */
1688 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1690 /* Look for the mips16 entry and exit instructions, and
1691 simulate a handler for them. */
1692 else if ((cia
& 1) != 0
1693 && (instruction
& 0xf81f) == 0xe809
1694 && (instruction
& 0x0c0) != 0x0c0)
1696 mips16_entry (SD
, CPU
, cia
, instruction
);
1697 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1699 /* else fall through to normal exception processing */
1700 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1705 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1707 /* Keep a copy of the current A0 in-case this is the program exit
1711 unsigned int instruction
;
1712 va_start(ap
,exception
);
1713 instruction
= va_arg(ap
,unsigned int);
1715 /* Check for our special terminating BREAK: */
1716 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1717 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1718 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1721 if (STATE
& simDELAYSLOT
)
1722 PC
= cia
- 4; /* reference the branch instruction */
1725 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1726 sim_stopped
, SIM_SIGTRAP
);
1729 /* Store exception code into current exception id variable (used
1732 /* TODO: If not simulating exceptions then stop the simulator
1733 execution. At the moment we always stop the simulation. */
1735 /* See figure 5-17 for an outline of the code below */
1736 if (! (SR
& status_EXL
))
1738 CAUSE
= (exception
<< 2);
1739 if (STATE
& simDELAYSLOT
)
1741 STATE
&= ~simDELAYSLOT
;
1743 EPC
= (cia
- 4); /* reference the branch instruction */
1747 /* FIXME: TLB et.al. */
1752 CAUSE
= (exception
<< 2);
1756 /* Store exception code into current exception id variable (used
1758 if (SR
& status_BEV
)
1759 PC
= (signed)0xBFC00200 + 0x180;
1761 PC
= (signed)0x80000000 + 0x180;
1763 switch ((CAUSE
>> 2) & 0x1F)
1766 /* Interrupts arrive during event processing, no need to
1770 case TLBModification
:
1775 case InstructionFetch
:
1777 /* The following is so that the simulator will continue from the
1778 exception address on breakpoint operations. */
1780 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1781 sim_stopped
, SIM_SIGBUS
);
1783 case ReservedInstruction
:
1784 case CoProcessorUnusable
:
1786 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1787 sim_stopped
, SIM_SIGILL
);
1789 case IntegerOverflow
:
1791 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1792 sim_stopped
, SIM_SIGFPE
);
1798 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1799 sim_stopped
, SIM_SIGTRAP
);
1803 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1804 "FATAL: Should not encounter a breakpoint\n");
1806 default : /* Unknown internal exception */
1808 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1809 sim_stopped
, SIM_SIGABRT
);
1813 case SimulatorFault
:
1817 va_start(ap
,exception
);
1818 msg
= va_arg(ap
,char *);
1820 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1821 "FATAL: Simulator error \"%s\"\n",msg
);
1828 #if defined(WARN_RESULT)
1829 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1830 /* This function indicates that the result of the operation is
1831 undefined. However, this should not affect the instruction
1832 stream. All that is meant to happen is that the destination
1833 register is set to an undefined result. To keep the simulator
1834 simple, we just don't bother updating the destination register, so
1835 the overall result will be undefined. If desired we can stop the
1836 simulator by raising a pseudo-exception. */
1837 #define UndefinedResult() undefined_result (sd,cia)
1839 undefined_result(sd
,cia
)
1843 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1844 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1849 #endif /* WARN_RESULT */
1852 cache_op (SIM_DESC sd
,
1858 unsigned int instruction
)
1860 #if 1 /* stop warning message being displayed (we should really just remove the code) */
1861 static int icache_warning
= 1;
1862 static int dcache_warning
= 1;
1864 static int icache_warning
= 0;
1865 static int dcache_warning
= 0;
1868 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1869 enable bit in the Status Register is clear - a coprocessor
1870 unusable exception is taken. */
1872 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
1876 case 0: /* instruction cache */
1878 case 0: /* Index Invalidate */
1879 case 1: /* Index Load Tag */
1880 case 2: /* Index Store Tag */
1881 case 4: /* Hit Invalidate */
1883 case 6: /* Hit Writeback */
1884 if (!icache_warning
)
1886 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
1892 SignalException(ReservedInstruction
,instruction
);
1897 case 1: /* data cache */
1899 case 0: /* Index Writeback Invalidate */
1900 case 1: /* Index Load Tag */
1901 case 2: /* Index Store Tag */
1902 case 3: /* Create Dirty */
1903 case 4: /* Hit Invalidate */
1904 case 5: /* Hit Writeback Invalidate */
1905 case 6: /* Hit Writeback */
1906 if (!dcache_warning
)
1908 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
1914 SignalException(ReservedInstruction
,instruction
);
1919 default: /* unrecognised cache ID */
1920 SignalException(ReservedInstruction
,instruction
);
1927 /*-- FPU support routines ---------------------------------------------------*/
1929 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
1931 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1932 formats conform to ANSI/IEEE Std 754-1985. */
1933 /* SINGLE precision floating:
1934 * seeeeeeeefffffffffffffffffffffff
1936 * e = 8bits = exponent
1937 * f = 23bits = fraction
1939 /* SINGLE precision fixed:
1940 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1942 * i = 31bits = integer
1944 /* DOUBLE precision floating:
1945 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1947 * e = 11bits = exponent
1948 * f = 52bits = fraction
1950 /* DOUBLE precision fixed:
1951 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1953 * i = 63bits = integer
1956 /* Extract sign-bit: */
1957 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1958 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1959 /* Extract biased exponent: */
1960 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1961 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1962 /* Extract unbiased Exponent: */
1963 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1964 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1965 /* Extract complete fraction field: */
1966 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1967 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1968 /* Extract numbered fraction bit: */
1969 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1970 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1972 /* Explicit QNaN values used when value required: */
1973 #define FPQNaN_SINGLE (0x7FBFFFFF)
1974 #define FPQNaN_WORD (0x7FFFFFFF)
1975 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1976 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1978 /* Explicit Infinity values used when required: */
1979 #define FPINF_SINGLE (0x7F800000)
1980 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1982 #if 1 /* def DEBUG */
1983 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1984 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1988 value_fpr (SIM_DESC sd
,
1997 /* Treat unused register values, as fixed-point 64bit values: */
1998 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2000 /* If request to read data as "uninterpreted", then use the current
2002 fmt
= FPR_STATE
[fpr
];
2007 /* For values not yet accessed, set to the desired format: */
2008 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2009 FPR_STATE
[fpr
] = fmt
;
2011 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2014 if (fmt
!= FPR_STATE
[fpr
]) {
2015 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
2016 FPR_STATE
[fpr
] = fmt_unknown
;
2019 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2020 /* Set QNaN value: */
2023 value
= FPQNaN_SINGLE
;
2027 value
= FPQNaN_DOUBLE
;
2031 value
= FPQNaN_WORD
;
2035 value
= FPQNaN_LONG
;
2042 } else if (SizeFGR() == 64) {
2046 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2049 case fmt_uninterpreted
:
2063 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2066 case fmt_uninterpreted
:
2069 if ((fpr
& 1) == 0) { /* even registers only */
2070 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2072 SignalException(ReservedInstruction
,0);
2083 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2086 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2093 store_fpr (SIM_DESC sd
,
2103 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2106 if (SizeFGR() == 64) {
2108 case fmt_uninterpreted_32
:
2109 fmt
= fmt_uninterpreted
;
2112 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2113 FPR_STATE
[fpr
] = fmt
;
2116 case fmt_uninterpreted_64
:
2117 fmt
= fmt_uninterpreted
;
2118 case fmt_uninterpreted
:
2122 FPR_STATE
[fpr
] = fmt
;
2126 FPR_STATE
[fpr
] = fmt_unknown
;
2132 case fmt_uninterpreted_32
:
2133 fmt
= fmt_uninterpreted
;
2136 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2137 FPR_STATE
[fpr
] = fmt
;
2140 case fmt_uninterpreted_64
:
2141 fmt
= fmt_uninterpreted
;
2142 case fmt_uninterpreted
:
2145 if ((fpr
& 1) == 0) { /* even register number only */
2146 FGR
[fpr
+1] = (value
>> 32);
2147 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2148 FPR_STATE
[fpr
+ 1] = fmt
;
2149 FPR_STATE
[fpr
] = fmt
;
2151 FPR_STATE
[fpr
] = fmt_unknown
;
2152 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2153 SignalException(ReservedInstruction
,0);
2158 FPR_STATE
[fpr
] = fmt_unknown
;
2163 #if defined(WARN_RESULT)
2166 #endif /* WARN_RESULT */
2169 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2172 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2189 sim_fpu_32to (&wop
, op
);
2190 boolean
= sim_fpu_is_nan (&wop
);
2197 sim_fpu_64to (&wop
, op
);
2198 boolean
= sim_fpu_is_nan (&wop
);
2202 fprintf (stderr
, "Bad switch\n");
2207 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2221 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2228 sim_fpu_32to (&wop
, op
);
2229 boolean
= sim_fpu_is_infinity (&wop
);
2235 sim_fpu_64to (&wop
, op
);
2236 boolean
= sim_fpu_is_infinity (&wop
);
2240 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2245 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2259 /* Argument checking already performed by the FPCOMPARE code */
2262 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2265 /* The format type should already have been checked: */
2271 sim_fpu_32to (&wop1
, op1
);
2272 sim_fpu_32to (&wop2
, op2
);
2273 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2280 sim_fpu_64to (&wop1
, op1
);
2281 sim_fpu_64to (&wop2
, op2
);
2282 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2286 fprintf (stderr
, "Bad switch\n");
2291 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2305 /* Argument checking already performed by the FPCOMPARE code */
2308 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2311 /* The format type should already have been checked: */
2317 sim_fpu_32to (&wop1
, op1
);
2318 sim_fpu_32to (&wop2
, op2
);
2319 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2326 sim_fpu_64to (&wop1
, op1
);
2327 sim_fpu_64to (&wop2
, op2
);
2328 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2332 fprintf (stderr
, "Bad switch\n");
2337 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2344 AbsoluteValue(op
,fmt
)
2351 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2354 /* The format type should already have been checked: */
2360 sim_fpu_32to (&wop
, op
);
2361 sim_fpu_abs (&wop
, &wop
);
2362 sim_fpu_to32 (&ans
, &wop
);
2370 sim_fpu_64to (&wop
, op
);
2371 sim_fpu_abs (&wop
, &wop
);
2372 sim_fpu_to64 (&ans
, &wop
);
2377 fprintf (stderr
, "Bad switch\n");
2392 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2395 /* The format type should already have been checked: */
2401 sim_fpu_32to (&wop
, op
);
2402 sim_fpu_neg (&wop
, &wop
);
2403 sim_fpu_to32 (&ans
, &wop
);
2411 sim_fpu_64to (&wop
, op
);
2412 sim_fpu_neg (&wop
, &wop
);
2413 sim_fpu_to64 (&ans
, &wop
);
2418 fprintf (stderr
, "Bad switch\n");
2434 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2437 /* The registers must specify FPRs valid for operands of type
2438 "fmt". If they are not valid, the result is undefined. */
2440 /* The format type should already have been checked: */
2448 sim_fpu_32to (&wop1
, op1
);
2449 sim_fpu_32to (&wop2
, op2
);
2450 sim_fpu_add (&ans
, &wop1
, &wop2
);
2451 sim_fpu_to32 (&res
, &ans
);
2461 sim_fpu_64to (&wop1
, op1
);
2462 sim_fpu_64to (&wop2
, op2
);
2463 sim_fpu_add (&ans
, &wop1
, &wop2
);
2464 sim_fpu_to64 (&res
, &ans
);
2469 fprintf (stderr
, "Bad switch\n");
2474 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2489 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2492 /* The registers must specify FPRs valid for operands of type
2493 "fmt". If they are not valid, the result is undefined. */
2495 /* The format type should already have been checked: */
2503 sim_fpu_32to (&wop1
, op1
);
2504 sim_fpu_32to (&wop2
, op2
);
2505 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2506 sim_fpu_to32 (&res
, &ans
);
2516 sim_fpu_64to (&wop1
, op1
);
2517 sim_fpu_64to (&wop2
, op2
);
2518 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2519 sim_fpu_to64 (&res
, &ans
);
2524 fprintf (stderr
, "Bad switch\n");
2529 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2536 Multiply(op1
,op2
,fmt
)
2544 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2547 /* The registers must specify FPRs valid for operands of type
2548 "fmt". If they are not valid, the result is undefined. */
2550 /* The format type should already have been checked: */
2558 sim_fpu_32to (&wop1
, op1
);
2559 sim_fpu_32to (&wop2
, op2
);
2560 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2561 sim_fpu_to32 (&res
, &ans
);
2571 sim_fpu_64to (&wop1
, op1
);
2572 sim_fpu_64to (&wop2
, op2
);
2573 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2574 sim_fpu_to64 (&res
, &ans
);
2579 fprintf (stderr
, "Bad switch\n");
2584 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2599 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2602 /* The registers must specify FPRs valid for operands of type
2603 "fmt". If they are not valid, the result is undefined. */
2605 /* The format type should already have been checked: */
2613 sim_fpu_32to (&wop1
, op1
);
2614 sim_fpu_32to (&wop2
, op2
);
2615 sim_fpu_div (&ans
, &wop1
, &wop2
);
2616 sim_fpu_to32 (&res
, &ans
);
2626 sim_fpu_64to (&wop1
, op1
);
2627 sim_fpu_64to (&wop2
, op2
);
2628 sim_fpu_div (&ans
, &wop1
, &wop2
);
2629 sim_fpu_to64 (&res
, &ans
);
2634 fprintf (stderr
, "Bad switch\n");
2639 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2653 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2656 /* The registers must specify FPRs valid for operands of type
2657 "fmt". If they are not valid, the result is undefined. */
2659 /* The format type should already have been checked: */
2666 sim_fpu_32to (&wop
, op
);
2667 sim_fpu_inv (&ans
, &wop
);
2668 sim_fpu_to32 (&res
, &ans
);
2677 sim_fpu_64to (&wop
, op
);
2678 sim_fpu_inv (&ans
, &wop
);
2679 sim_fpu_to64 (&res
, &ans
);
2684 fprintf (stderr
, "Bad switch\n");
2689 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2703 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2706 /* The registers must specify FPRs valid for operands of type
2707 "fmt". If they are not valid, the result is undefined. */
2709 /* The format type should already have been checked: */
2716 sim_fpu_32to (&wop
, op
);
2717 sim_fpu_sqrt (&ans
, &wop
);
2718 sim_fpu_to32 (&res
, &ans
);
2727 sim_fpu_64to (&wop
, op
);
2728 sim_fpu_sqrt (&ans
, &wop
);
2729 sim_fpu_to64 (&res
, &ans
);
2734 fprintf (stderr
, "Bad switch\n");
2739 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2746 convert (SIM_DESC sd
,
2755 sim_fpu_round round
;
2756 unsigned32 result32
;
2757 unsigned64 result64
;
2760 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2766 /* Round result to nearest representable value. When two
2767 representable values are equally near, round to the value
2768 that has a least significant bit of zero (i.e. is even). */
2769 round
= sim_fpu_round_near
;
2772 /* Round result to the value closest to, and not greater in
2773 magnitude than, the result. */
2774 round
= sim_fpu_round_zero
;
2777 /* Round result to the value closest to, and not less than,
2779 round
= sim_fpu_round_up
;
2783 /* Round result to the value closest to, and not greater than,
2785 round
= sim_fpu_round_down
;
2789 fprintf (stderr
, "Bad switch\n");
2793 /* Convert the input to sim_fpu internal format */
2797 sim_fpu_64to (&wop
, op
);
2800 sim_fpu_32to (&wop
, op
);
2803 sim_fpu_i32to (&wop
, op
, round
);
2806 sim_fpu_i64to (&wop
, op
, round
);
2809 fprintf (stderr
, "Bad switch\n");
2813 /* Convert sim_fpu format into the output */
2814 /* The value WOP is converted to the destination format, rounding
2815 using mode RM. When the destination is a fixed-point format, then
2816 a source value of Infinity, NaN or one which would round to an
2817 integer outside the fixed point range then an IEEE Invalid
2818 Operation condition is raised. */
2822 sim_fpu_round_32 (&wop
, round
, 0);
2823 sim_fpu_to32 (&result32
, &wop
);
2824 result64
= result32
;
2827 sim_fpu_round_64 (&wop
, round
, 0);
2828 sim_fpu_to64 (&result64
, &wop
);
2831 sim_fpu_to32i (&result32
, &wop
, round
);
2832 result64
= result32
;
2835 sim_fpu_to64i (&result64
, &wop
, round
);
2839 fprintf (stderr
, "Bad switch\n");
2844 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2852 /*-- co-processor support routines ------------------------------------------*/
2855 CoProcPresent(coproc_number
)
2856 unsigned int coproc_number
;
2858 /* Return TRUE if simulator provides a model for the given co-processor number */
2863 cop_lw (SIM_DESC sd
,
2868 unsigned int memword
)
2870 switch (coproc_num
) {
2874 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2876 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2877 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2882 #if 0 /* this should be controlled by a configuration option */
2883 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2892 cop_ld (SIM_DESC sd
,
2899 switch (coproc_num
) {
2902 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
2907 #if 0 /* this message should be controlled by a configuration option */
2908 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2917 cop_sw (SIM_DESC sd
,
2923 unsigned int value
= 0;
2925 switch (coproc_num
) {
2931 hold
= FPR_STATE
[coproc_reg
];
2932 FPR_STATE
[coproc_reg
] = fmt_word
;
2933 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
2934 FPR_STATE
[coproc_reg
] = hold
;
2938 value
= (unsigned int)ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
2941 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE
[coproc_reg
]));
2943 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_single
);
2950 #if 0 /* should be controlled by configuration option */
2951 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2960 cop_sd (SIM_DESC sd
,
2967 switch (coproc_num
) {
2971 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
2974 value
= ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
2977 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE
[coproc_reg
]));
2979 value
= ValueFPR(coproc_reg
,fmt_double
);
2986 #if 0 /* should be controlled by configuration option */
2987 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2996 decode_coproc (SIM_DESC sd
,
2999 unsigned int instruction
)
3001 int coprocnum
= ((instruction
>> 26) & 3);
3005 case 0: /* standard CPU control and cache registers */
3007 int code
= ((instruction
>> 21) & 0x1F);
3008 /* R4000 Users Manual (second edition) lists the following CP0
3010 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3011 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3012 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3013 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3014 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3015 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3016 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3017 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3018 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3019 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3021 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3023 int rt
= ((instruction
>> 16) & 0x1F);
3024 int rd
= ((instruction
>> 11) & 0x1F);
3026 switch (rd
) /* NOTEs: Standard CP0 registers */
3028 /* 0 = Index R4000 VR4100 VR4300 */
3029 /* 1 = Random R4000 VR4100 VR4300 */
3030 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3031 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3032 /* 4 = Context R4000 VR4100 VR4300 */
3033 /* 5 = PageMask R4000 VR4100 VR4300 */
3034 /* 6 = Wired R4000 VR4100 VR4300 */
3035 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3036 /* 9 = Count R4000 VR4100 VR4300 */
3037 /* 10 = EntryHi R4000 VR4100 VR4300 */
3038 /* 11 = Compare R4000 VR4100 VR4300 */
3039 /* 12 = SR R4000 VR4100 VR4300 */
3046 /* 13 = Cause R4000 VR4100 VR4300 */
3053 /* 14 = EPC R4000 VR4100 VR4300 */
3054 /* 15 = PRId R4000 VR4100 VR4300 */
3055 #ifdef SUBTARGET_R3900
3064 /* 16 = Config R4000 VR4100 VR4300 */
3067 GPR
[rt
] = C0_CONFIG
;
3069 C0_CONFIG
= GPR
[rt
];
3072 #ifdef SUBTARGET_R3900
3081 /* 17 = LLAddr R4000 VR4100 VR4300 */
3083 /* 18 = WatchLo R4000 VR4100 VR4300 */
3084 /* 19 = WatchHi R4000 VR4100 VR4300 */
3085 /* 20 = XContext R4000 VR4100 VR4300 */
3086 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3087 /* 27 = CacheErr R4000 VR4100 */
3088 /* 28 = TagLo R4000 VR4100 VR4300 */
3089 /* 29 = TagHi R4000 VR4100 VR4300 */
3090 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3091 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3092 /* CPR[0,rd] = GPR[rt]; */
3095 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3097 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3100 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3103 if (SR
& status_ERL
)
3105 /* Oops, not yet available */
3106 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3116 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3120 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3128 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3129 /* TODO: When executing an ERET or RFE instruction we should
3130 clear LLBIT, to ensure that any out-standing atomic
3131 read/modify/write sequence fails. */
3135 case 2: /* undefined co-processor */
3136 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3139 case 1: /* should not occur (FPU co-processor) */
3140 case 3: /* should not occur (FPU co-processor) */
3141 SignalException(ReservedInstruction
,instruction
);
3148 /*-- instruction simulation -------------------------------------------------*/
3150 /* When the IGEN simulator is being built, the function below is be
3151 replaced by a generated version. However, WITH_IGEN == 2 indicates
3152 that the fubction below should be compiled but under a different
3153 name (to allow backward compatibility) */
3155 #if (WITH_IGEN != 1)
3157 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3159 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3162 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3165 int next_cpu_nr
; /* ignore */
3166 int nr_cpus
; /* ignore */
3167 int siggnal
; /* ignore */
3169 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3170 #if !defined(FASTSIM)
3171 unsigned int pipeline_count
= 1;
3175 if (STATE_MEMORY (sd
) == NULL
) {
3176 printf("DBG: simulate() entered with no memory\n");
3181 #if 0 /* Disabled to check that everything works OK */
3182 /* The VR4300 seems to sign-extend the PC on its first
3183 access. However, this may just be because it is currently
3184 configured in 32bit mode. However... */
3185 PC
= SIGNEXTEND(PC
,32);
3188 /* main controlling loop */
3190 /* vaddr is slowly being replaced with cia - current instruction
3192 address_word cia
= (uword64
)PC
;
3193 address_word vaddr
= cia
;
3196 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3200 printf("DBG: state = 0x%08X :",state
);
3201 if (state
& simHALTEX
) printf(" simHALTEX");
3202 if (state
& simHALTIN
) printf(" simHALTIN");
3207 DSSTATE
= (STATE
& simDELAYSLOT
);
3210 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3213 /* Fetch the next instruction from the simulator memory: */
3214 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3215 if ((vaddr
& 1) == 0) {
3216 /* Copy the action of the LW instruction */
3217 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3218 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3221 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3222 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3223 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3224 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3226 /* Copy the action of the LH instruction */
3227 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3228 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3231 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3232 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3233 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3234 paddr
& ~ (uword64
) 1,
3235 vaddr
, isINSTRUCTION
, isREAL
);
3236 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3237 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3240 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3245 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3248 /* This is required by exception processing, to ensure that we can
3249 cope with exceptions in the delay slots of branches that may
3250 already have changed the PC. */
3251 if ((vaddr
& 1) == 0)
3252 PC
+= 4; /* increment ready for the next fetch */
3255 /* NOTE: If we perform a delay slot change to the PC, this
3256 increment is not requuired. However, it would make the
3257 simulator more complicated to try and avoid this small hit. */
3259 /* Currently this code provides a simple model. For more
3260 complicated models we could perform exception status checks at
3261 this point, and set the simSTOP state as required. This could
3262 also include processing any hardware interrupts raised by any
3263 I/O model attached to the simulator context.
3265 Support for "asynchronous" I/O events within the simulated world
3266 could be providing by managing a counter, and calling a I/O
3267 specific handler when a particular threshold is reached. On most
3268 architectures a decrement and check for zero operation is
3269 usually quicker than an increment and compare. However, the
3270 process of managing a known value decrement to zero, is higher
3271 than the cost of using an explicit value UINT_MAX into the
3272 future. Which system is used will depend on how complicated the
3273 I/O model is, and how much it is likely to affect the simulator
3276 If events need to be scheduled further in the future than
3277 UINT_MAX event ticks, then the I/O model should just provide its
3278 own counter, triggered from the event system. */
3280 /* MIPS pipeline ticks. To allow for future support where the
3281 pipeline hit of individual instructions is known, this control
3282 loop manages a "pipeline_count" variable. It is initialised to
3283 1 (one), and will only be changed by the simulator engine when
3284 executing an instruction. If the engine does not have access to
3285 pipeline cycle count information then all instructions will be
3286 treated as using a single cycle. NOTE: A standard system is not
3287 provided by the default simulator because different MIPS
3288 architectures have different cycle counts for the same
3291 [NOTE: pipeline_count has been replaced the event queue] */
3293 /* shuffle the floating point status pipeline state */
3294 ENGINE_ISSUE_PREFIX_HOOK();
3296 /* NOTE: For multi-context simulation environments the "instruction"
3297 variable should be local to this routine. */
3299 /* Shorthand accesses for engine. Note: If we wanted to use global
3300 variables (and a single-threaded simulator engine), then we can
3301 create the actual variables with these names. */
3303 if (!(STATE
& simSKIPNEXT
)) {
3304 /* Include the simulator engine */
3305 #include "oengine.c"
3306 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3307 #error "Mismatch between run-time simulator code and simulation engine"
3309 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3310 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3312 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3313 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3316 #if defined(WARN_LOHI)
3317 /* Decrement the HI/LO validity ticks */
3322 /* start-sanitize-r5900 */
3327 /* end-sanitize-r5900 */
3328 #endif /* WARN_LOHI */
3330 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3331 should check for it being changed. It is better doing it here,
3332 than within the simulator, since it will help keep the simulator
3335 #if defined(WARN_ZERO)
3336 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3337 #endif /* WARN_ZERO */
3338 ZERO
= 0; /* reset back to zero before next instruction */
3340 } else /* simSKIPNEXT check */
3341 STATE
&= ~simSKIPNEXT
;
3343 /* If the delay slot was active before the instruction is
3344 executed, then update the PC to its new value: */
3347 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3353 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
3354 /* Deal with pending register updates: */
3356 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3358 if (PENDING_OUT
!= PENDING_IN
) {
3360 int index
= PENDING_OUT
;
3361 int total
= PENDING_TOTAL
;
3362 if (PENDING_TOTAL
== 0) {
3363 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
3366 for (loop
= 0; (loop
< total
); loop
++) {
3368 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
3370 if (PENDING_SLOT_REG
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
3372 printf("pending_slot_count[%d] = %d\n",index
,PENDING_SLOT_COUNT
[index
]);
3374 if (--(PENDING_SLOT_COUNT
[index
]) == 0) {
3376 printf("pending_slot_reg[%d] = %d\n",index
,PENDING_SLOT_REG
[index
]);
3377 printf("pending_slot_value[%d] = 0x%s\n",index
,pr_addr(PENDING_SLOT_VALUE
[index
]));
3379 if (PENDING_SLOT_REG
[index
] == COCIDX
) {
3381 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
3386 REGISTERS
[PENDING_SLOT_REG
[index
]] = PENDING_SLOT_VALUE
[index
];
3388 /* The only time we have PENDING updates to FPU
3389 registers, is when performing binary transfers. This
3390 means we should update the register type field. */
3391 if ((PENDING_SLOT_REG
[index
] >= FGRIDX
) && (PENDING_SLOT_REG
[index
] < (FGRIDX
+ 32)))
3392 FPR_STATE
[PENDING_SLOT_REG
[index
] - FGRIDX
] = fmt_uninterpreted
;
3396 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG
[index
],pr_addr(REGISTERS
[PENDING_SLOT_REG
[index
]]));
3398 PENDING_SLOT_REG
[index
] = (LAST_EMBED_REGNUM
+ 1);
3400 if (PENDING_OUT
== PSLOTS
)
3406 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
3409 if (index
== PSLOTS
)
3414 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN
,PENDING_OUT
,PENDING_TOTAL
);
3418 #if !defined(FASTSIM)
3419 if (sim_events_tickn (sd
, pipeline_count
))
3421 /* cpu->cia = cia; */
3422 sim_events_process (sd
);
3425 if (sim_events_tick (sd
))
3427 /* cpu->cia = cia; */
3428 sim_events_process (sd
);
3430 #endif /* FASTSIM */
3436 /* This code copied from gdb's utils.c. Would like to share this code,
3437 but don't know of a common place where both could get to it. */
3439 /* Temporary storage using circular buffer */
3445 static char buf
[NUMCELLS
][CELLSIZE
];
3447 if (++cell
>=NUMCELLS
) cell
=0;
3451 /* Print routines to handle variable size regs, etc */
3453 /* Eliminate warning from compiler on 32-bit systems */
3454 static int thirty_two
= 32;
3460 char *paddr_str
=get_cell();
3461 switch (sizeof(addr
))
3464 sprintf(paddr_str
,"%08lx%08lx",
3465 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3468 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3471 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3474 sprintf(paddr_str
,"%x",addr
);
3483 char *paddr_str
=get_cell();
3484 sprintf(paddr_str
,"%08lx%08lx",
3485 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3490 /*---------------------------------------------------------------------------*/
3491 /*> EOF interp.c <*/