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* Numerous changes & small bug fixes in PKE sim code and test suite.
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Author$
18 $Date$
19
20 NOTEs:
21
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
25 code on the hardware.
26
27 */
28
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
33 #define TRACE (1)
34 #endif
35
36 #include "bfd.h"
37 #include "sim-main.h"
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
41
42 #include "config.h"
43
44 #include <stdio.h>
45 #include <stdarg.h>
46 #include <ansidecl.h>
47 #include <ctype.h>
48 #include <limits.h>
49 #include <math.h>
50 #ifdef HAVE_STDLIB_H
51 #include <stdlib.h>
52 #endif
53 #ifdef HAVE_STRING_H
54 #include <string.h>
55 #else
56 #ifdef HAVE_STRINGS_H
57 #include <strings.h>
58 #endif
59 #endif
60
61 #include "getopt.h"
62 #include "libiberty.h"
63 #include "bfd.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
66
67 #include "sysdep.h"
68
69 #ifndef PARAMS
70 #define PARAMS(x)
71 #endif
72
73 char* pr_addr PARAMS ((SIM_ADDR addr));
74 char* pr_uword64 PARAMS ((uword64 addr));
75
76
77 /* Get the simulator engine description, without including the code: */
78 #if (WITH_IGEN)
79 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
80 #else
81 #define SIM_MANIFESTS
82 #include "oengine.c"
83 #undef SIM_MANIFESTS
84 #endif
85
86 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
87 #define SD sd
88 #define CPU cpu
89
90
91 /* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
94 #define RSVD_INSTRUCTION (0x00000005)
95 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
96
97 #define RSVD_INSTRUCTION_ARG_SHIFT 6
98 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
99
100
101 /* Bits in the Debug register */
102 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
103 #define Debug_DM 0x40000000 /* Debug Mode */
104 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
105
106
107
108
109
110 /*---------------------------------------------------------------------------*/
111 /*-- GDB simulator interface ------------------------------------------------*/
112 /*---------------------------------------------------------------------------*/
113
114 static void ColdReset PARAMS((SIM_DESC sd));
115
116 /*---------------------------------------------------------------------------*/
117
118
119
120 #define DELAYSLOT() {\
121 if (STATE & simDELAYSLOT)\
122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
123 STATE |= simDELAYSLOT;\
124 }
125
126 #define JALDELAYSLOT() {\
127 DELAYSLOT ();\
128 STATE |= simJALDELAYSLOT;\
129 }
130
131 #define NULLIFY() {\
132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
134 }
135
136 #define CANCELDELAYSLOT() {\
137 DSSTATE = 0;\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
139 }
140
141 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
143
144 #define K0BASE (0x80000000)
145 #define K0SIZE (0x20000000)
146 #define K1BASE (0xA0000000)
147 #define K1SIZE (0x20000000)
148 #define MONITOR_BASE (0xBFC00000)
149 #define MONITOR_SIZE (1 << 11)
150 #define MEM_SIZE (2 << 20)
151
152 #if defined(TRACE)
153 static char *tracefile = "trace.din"; /* default filename for trace log */
154 FILE *tracefh = NULL;
155 static void open_trace PARAMS((SIM_DESC sd));
156 #endif /* TRACE */
157
158 static DECLARE_OPTION_HANDLER (mips_option_handler);
159
160 #define OPTION_DINERO_TRACE 200
161 #define OPTION_DINERO_FILE 201
162
163 static SIM_RC
164 mips_option_handler (sd, cpu, opt, arg, is_command)
165 SIM_DESC sd;
166 sim_cpu *cpu;
167 int opt;
168 char *arg;
169 int is_command;
170 {
171 int cpu_nr;
172 switch (opt)
173 {
174 case OPTION_DINERO_TRACE: /* ??? */
175 #if defined(TRACE)
176 /* Eventually the simTRACE flag could be treated as a toggle, to
177 allow external control of the program points being traced
178 (i.e. only from main onwards, excluding the run-time setup,
179 etc.). */
180 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
181 {
182 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
183 if (arg == NULL)
184 STATE |= simTRACE;
185 else if (strcmp (arg, "yes") == 0)
186 STATE |= simTRACE;
187 else if (strcmp (arg, "no") == 0)
188 STATE &= ~simTRACE;
189 else if (strcmp (arg, "on") == 0)
190 STATE |= simTRACE;
191 else if (strcmp (arg, "off") == 0)
192 STATE &= ~simTRACE;
193 else
194 {
195 fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
196 return SIM_RC_FAIL;
197 }
198 }
199 return SIM_RC_OK;
200 #else /* !TRACE */
201 fprintf(stderr,"\
202 Simulator constructed without dinero tracing support (for performance).\n\
203 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
204 return SIM_RC_FAIL;
205 #endif /* !TRACE */
206
207 case OPTION_DINERO_FILE:
208 #if defined(TRACE)
209 if (optarg != NULL) {
210 char *tmp;
211 tmp = (char *)malloc(strlen(optarg) + 1);
212 if (tmp == NULL)
213 {
214 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
215 return SIM_RC_FAIL;
216 }
217 else {
218 strcpy(tmp,optarg);
219 tracefile = tmp;
220 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
221 }
222 }
223 #endif /* TRACE */
224 return SIM_RC_OK;
225
226 }
227
228 return SIM_RC_OK;
229 }
230
231 static const OPTION mips_options[] =
232 {
233 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
234 '\0', "on|off", "Enable dinero tracing",
235 mips_option_handler },
236 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
237 '\0', "FILE", "Write dinero trace to FILE",
238 mips_option_handler },
239 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
240 };
241
242
243 int interrupt_pending;
244
245 static void
246 interrupt_event (SIM_DESC sd, void *data)
247 {
248 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
249 if (SR & status_IE)
250 {
251 interrupt_pending = 0;
252 SignalExceptionInterrupt ();
253 }
254 else if (!interrupt_pending)
255 sim_events_schedule (sd, 1, interrupt_event, data);
256 }
257
258
259 /*---------------------------------------------------------------------------*/
260 /*-- Device registration hook -----------------------------------------------*/
261 /*---------------------------------------------------------------------------*/
262 static void device_init(SIM_DESC sd) {
263 #ifdef DEVICE_INIT
264 extern void register_devices(SIM_DESC);
265 register_devices(sd);
266 #endif
267 }
268
269 /* start-sanitize-sky */
270 #ifdef TARGET_SKY
271 static struct {
272 short i[NUM_VU_INTEGER_REGS];
273 int f[NUM_VU_REGS - NUM_VU_INTEGER_REGS];
274 } vu_regs[2];
275 #endif
276 /* end-sanitize-sky */
277
278 /*---------------------------------------------------------------------------*/
279 /*-- GDB simulator interface ------------------------------------------------*/
280 /*---------------------------------------------------------------------------*/
281
282 SIM_DESC
283 sim_open (kind, cb, abfd, argv)
284 SIM_OPEN_KIND kind;
285 host_callback *cb;
286 struct _bfd *abfd;
287 char **argv;
288 {
289 SIM_DESC sd = sim_state_alloc (kind, cb);
290 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
291
292 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
293
294 /* FIXME: watchpoints code shouldn't need this */
295 STATE_WATCHPOINTS (sd)->pc = &(PC);
296 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
297 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
298
299 STATE = 0;
300
301 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
302 return 0;
303 sim_add_option_table (sd, NULL, mips_options);
304
305 /* Allocate core managed memory */
306
307 /* the monitor */
308 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
309 /* For compatibility with the old code - under this (at level one)
310 are the kernel spaces K0 & K1. Both of these map to a single
311 smaller sub region */
312 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
313 /* start-sanitize-sky */
314 #ifndef TARGET_SKY
315 /* end-sanitize-sky */
316 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
317 K1BASE, K0SIZE,
318 MEM_SIZE, /* actual size */
319 K0BASE);
320 /* start-sanitize-sky */
321 #else
322 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
323 K1BASE, K0SIZE,
324 MEM_SIZE, /* actual size */
325 K0BASE,
326 0); /* add alias at 0x0000 */
327 #endif
328 /* end-sanitize-sky */
329
330 device_init(sd);
331
332 /* getopt will print the error message so we just have to exit if this fails.
333 FIXME: Hmmm... in the case of gdb we need getopt to call
334 print_filtered. */
335 if (sim_parse_args (sd, argv) != SIM_RC_OK)
336 {
337 /* Uninstall the modules to avoid memory leaks,
338 file descriptor leaks, etc. */
339 sim_module_uninstall (sd);
340 return 0;
341 }
342
343 /* check for/establish the a reference program image */
344 if (sim_analyze_program (sd,
345 (STATE_PROG_ARGV (sd) != NULL
346 ? *STATE_PROG_ARGV (sd)
347 : NULL),
348 abfd) != SIM_RC_OK)
349 {
350 sim_module_uninstall (sd);
351 return 0;
352 }
353
354 /* Configure/verify the target byte order and other runtime
355 configuration options */
356 if (sim_config (sd) != SIM_RC_OK)
357 {
358 sim_module_uninstall (sd);
359 return 0;
360 }
361
362 if (sim_post_argv_init (sd) != SIM_RC_OK)
363 {
364 /* Uninstall the modules to avoid memory leaks,
365 file descriptor leaks, etc. */
366 sim_module_uninstall (sd);
367 return 0;
368 }
369
370 /* verify assumptions the simulator made about the host type system.
371 This macro does not return if there is a problem */
372 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
373 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
374
375 /* This is NASTY, in that we are assuming the size of specific
376 registers: */
377 {
378 int rn;
379 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
380 {
381 if (rn < 32)
382 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
383 else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
384 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
385 else if ((rn >= 33) && (rn <= 37))
386 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
387 else if ((rn == SRIDX)
388 || (rn == FCR0IDX)
389 || (rn == FCR31IDX)
390 || ((rn >= 72) && (rn <= 89)))
391 cpu->register_widths[rn] = 32;
392 else
393 cpu->register_widths[rn] = 0;
394 }
395 /* start-sanitize-r5900 */
396
397 /* set the 5900 "upper" registers to 64 bits */
398 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
399 cpu->register_widths[rn] = 64;
400 /* end-sanitize-r5900 */
401
402 /* start-sanitize-sky */
403 #ifdef TARGET_SKY
404 /* Now the VU registers */
405 for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
406 cpu->register_widths[rn + NUM_R5900_REGS] = 16;
407 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
408
409 /* Hack for now - to test gdb interface */
410 vu_regs[0].i[rn] = rn + 0x100;
411 vu_regs[1].i[rn] = rn + 0x200;
412 }
413
414 for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
415 float f;
416 int first_vec_reg = NUM_VU_INTEGER_REGS + 8;
417
418 cpu->register_widths[rn + NUM_R5900_REGS] = 32;
419 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
420
421 /* Hack for now - to test gdb interface */
422 if( rn < first_vec_reg ) {
423 f = rn - NUM_VU_INTEGER_REGS + 100.0;
424 vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f);
425 f = rn - NUM_VU_INTEGER_REGS + 200.0;
426 vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f);
427 }
428 else {
429 f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 1000.0;
430 vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f);
431 f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 2000.0;
432 vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f);
433 }
434 }
435 #endif
436 /* end-sanitize-sky */
437 }
438
439 #if defined(TRACE)
440 if (STATE & simTRACE)
441 open_trace(sd);
442 #endif /* TRACE */
443
444 /* Write the monitor trap address handlers into the monitor (eeprom)
445 address space. This can only be done once the target endianness
446 has been determined. */
447 {
448 unsigned loop;
449 /* Entry into the IDT monitor is via fixed address vectors, and
450 not using machine instructions. To avoid clashing with use of
451 the MIPS TRAP system, we place our own (simulator specific)
452 "undefined" instructions into the relevant vector slots. */
453 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
454 {
455 address_word vaddr = (MONITOR_BASE + loop);
456 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
457 H2T (insn);
458 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
459 }
460 /* The PMON monitor uses the same address space, but rather than
461 branching into it the address of a routine is loaded. We can
462 cheat for the moment, and direct the PMON routine to IDT style
463 instructions within the monitor space. This relies on the IDT
464 monitor not using the locations from 0xBFC00500 onwards as its
465 entry points.*/
466 for (loop = 0; (loop < 24); loop++)
467 {
468 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
469 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
470 switch (loop)
471 {
472 case 0: /* read */
473 value = 7;
474 break;
475 case 1: /* write */
476 value = 8;
477 break;
478 case 2: /* open */
479 value = 6;
480 break;
481 case 3: /* close */
482 value = 10;
483 break;
484 case 5: /* printf */
485 value = ((0x500 - 16) / 8); /* not an IDT reason code */
486 break;
487 case 8: /* cliexit */
488 value = 17;
489 break;
490 case 11: /* flush_cache */
491 value = 28;
492 break;
493 }
494 /* FIXME - should monitor_base be SIM_ADDR?? */
495 value = ((unsigned int)MONITOR_BASE + (value * 8));
496 H2T (value);
497 sim_write (sd, vaddr, (char *)&value, sizeof (value));
498
499 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
500 vaddr -= 0x300;
501 sim_write (sd, vaddr, (char *)&value, sizeof (value));
502 }
503 }
504
505 return sd;
506 }
507
508 #if defined(TRACE)
509 static void
510 open_trace(sd)
511 SIM_DESC sd;
512 {
513 tracefh = fopen(tracefile,"wb+");
514 if (tracefh == NULL)
515 {
516 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
517 tracefh = stderr;
518 }
519 }
520 #endif /* TRACE */
521
522 void
523 sim_close (sd, quitting)
524 SIM_DESC sd;
525 int quitting;
526 {
527 #ifdef DEBUG
528 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
529 #endif
530
531 /* "quitting" is non-zero if we cannot hang on errors */
532
533 /* Ensure that any resources allocated through the callback
534 mechanism are released: */
535 sim_io_shutdown (sd);
536
537 #if defined(TRACE)
538 if (tracefh != NULL && tracefh != stderr)
539 fclose(tracefh);
540 tracefh = NULL;
541 #endif /* TRACE */
542
543 /* FIXME - free SD */
544
545 return;
546 }
547
548
549 int
550 sim_write (sd,addr,buffer,size)
551 SIM_DESC sd;
552 SIM_ADDR addr;
553 unsigned char *buffer;
554 int size;
555 {
556 int index;
557 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
558
559 /* Return the number of bytes written, or zero if error. */
560 #ifdef DEBUG
561 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
562 #endif
563
564 /* We use raw read and write routines, since we do not want to count
565 the GDB memory accesses in our statistics gathering. */
566
567 for (index = 0; index < size; index++)
568 {
569 address_word vaddr = (address_word)addr + index;
570 address_word paddr;
571 int cca;
572 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
573 break;
574 if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
575 break;
576 }
577
578 return(index);
579 }
580
581 int
582 sim_read (sd,addr,buffer,size)
583 SIM_DESC sd;
584 SIM_ADDR addr;
585 unsigned char *buffer;
586 int size;
587 {
588 int index;
589 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
590
591 /* Return the number of bytes read, or zero if error. */
592 #ifdef DEBUG
593 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
594 #endif /* DEBUG */
595
596 for (index = 0; (index < size); index++)
597 {
598 address_word vaddr = (address_word)addr + index;
599 address_word paddr;
600 int cca;
601 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
602 break;
603 if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1)
604 break;
605 }
606
607 return(index);
608 }
609
610 int
611 sim_store_register (sd,rn,memory,length)
612 SIM_DESC sd;
613 int rn;
614 unsigned char *memory;
615 int length;
616 {
617 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
618 /* NOTE: gdb (the client) stores registers in target byte order
619 while the simulator uses host byte order */
620 #ifdef DEBUG
621 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
622 #endif /* DEBUG */
623
624 /* Unfortunately this suffers from the same problem as the register
625 numbering one. We need to know what the width of each logical
626 register number is for the architecture being simulated. */
627
628 if (cpu->register_widths[rn] == 0)
629 {
630 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
631 return 0;
632 }
633
634 /* start-sanitize-r5900 */
635 if (rn >= 90 && rn < 90 + 32)
636 {
637 GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
638 return 8;
639 }
640 switch (rn)
641 {
642 case REGISTER_SA:
643 SA = T2H_8(*(unsigned64*)memory);
644 return 8;
645 case 122: /* FIXME */
646 LO1 = T2H_8(*(unsigned64*)memory);
647 return 8;
648 case 123: /* FIXME */
649 HI1 = T2H_8(*(unsigned64*)memory);
650 return 8;
651 }
652 /* end-sanitize-r5900 */
653
654 /* start-sanitize-sky */
655 #ifdef TARGET_SKY
656 if (rn >= NUM_R5900_REGS)
657 {
658 int size = 4; /* Default register size */
659
660 rn = rn - NUM_R5900_REGS;
661
662 if (rn < NUM_VU_INTEGER_REGS)
663 {
664 vu_regs[0].i[rn] = T2H_2( *(unsigned short *) memory );
665 size = 2;
666 }
667 else if( rn < NUM_VU_REGS )
668 vu_regs[0].f[rn - NUM_VU_INTEGER_REGS]
669 = T2H_4( *(unsigned int *) memory );
670 else {
671 rn = rn - NUM_VU_REGS;
672
673 if( rn < NUM_VU_INTEGER_REGS )
674 {
675 vu_regs[1].i[rn] = T2H_2( *(unsigned short *) memory );
676 size = 2;
677 }
678 else if( rn < NUM_VU_REGS )
679 vu_regs[1].f[rn - NUM_VU_INTEGER_REGS]
680 = T2H_4( *(unsigned int *) memory );
681 else
682 sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
683 }
684
685 return size;
686 }
687 #endif
688 /* end-sanitize-sky */
689
690 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
691 {
692 if (cpu->register_widths[rn] == 32)
693 {
694 cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
695 return 4;
696 }
697 else
698 {
699 cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
700 return 8;
701 }
702 }
703
704 if (cpu->register_widths[rn] == 32)
705 {
706 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
707 return 4;
708 }
709 else
710 {
711 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
712 return 8;
713 }
714 }
715
716 int
717 sim_fetch_register (sd,rn,memory,length)
718 SIM_DESC sd;
719 int rn;
720 unsigned char *memory;
721 int length;
722 {
723 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
724 /* NOTE: gdb (the client) stores registers in target byte order
725 while the simulator uses host byte order */
726 #ifdef DEBUG
727 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
728 #endif /* DEBUG */
729
730 if (cpu->register_widths[rn] == 0)
731 {
732 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
733 return 0;
734 }
735
736 /* start-sanitize-r5900 */
737 if (rn >= 90 && rn < 90 + 32)
738 {
739 *(unsigned64*)memory = GPR1[rn - 90];
740 return 8;
741 }
742 switch (rn)
743 {
744 case REGISTER_SA:
745 *((unsigned64*)memory) = H2T_8(SA);
746 return 8;
747 case 122: /* FIXME */
748 *((unsigned64*)memory) = H2T_8(LO1);
749 return 8;
750 case 123: /* FIXME */
751 *((unsigned64*)memory) = H2T_8(HI1);
752 return 8;
753 }
754 /* end-sanitize-r5900 */
755
756 /* start-sanitize-sky */
757 #ifdef TARGET_SKY
758 if (rn >= NUM_R5900_REGS)
759 {
760 int size = 4; /* default register width */
761
762 rn = rn - NUM_R5900_REGS;
763
764 if (rn < NUM_VU_INTEGER_REGS)
765 {
766 *((unsigned short *) memory) = H2T_2( vu_regs[0].i[rn] );
767 size = 2;
768 }
769 else if (rn < NUM_VU_REGS)
770 *((unsigned int *) memory)
771 = H2T_4( vu_regs[0].f[rn - NUM_VU_INTEGER_REGS] );
772 else
773 {
774 rn = rn - NUM_VU_REGS;
775
776 if (rn < NUM_VU_INTEGER_REGS)
777 {
778 (*(unsigned short *) memory) = H2T_2( vu_regs[1].i[rn] );
779 size = 2;
780 }
781 else if (rn < NUM_VU_REGS)
782 (*(unsigned int *) memory)
783 = H2T_4( vu_regs[1].f[rn - NUM_VU_INTEGER_REGS] );
784 else
785 sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
786 }
787
788 return size;
789 }
790 #endif
791 /* end-sanitize-sky */
792
793 /* Any floating point register */
794 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
795 {
796 if (cpu->register_widths[rn] == 32)
797 {
798 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
799 return 4;
800 }
801 else
802 {
803 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
804 return 8;
805 }
806 }
807
808 if (cpu->register_widths[rn] == 32)
809 {
810 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
811 return 4;
812 }
813 else
814 {
815 *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
816 return 8;
817 }
818 }
819
820
821 SIM_RC
822 sim_create_inferior (sd, abfd, argv,env)
823 SIM_DESC sd;
824 struct _bfd *abfd;
825 char **argv;
826 char **env;
827 {
828
829 #ifdef DEBUG
830 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
831 pr_addr(PC));
832 #endif /* DEBUG */
833
834 ColdReset(sd);
835
836 if (abfd != NULL)
837 {
838 /* override PC value set by ColdReset () */
839 int cpu_nr;
840 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
841 {
842 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
843 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
844 }
845 }
846
847 #if 0 /* def DEBUG */
848 if (argv || env)
849 {
850 /* We should really place the argv slot values into the argument
851 registers, and onto the stack as required. However, this
852 assumes that we have a stack defined, which is not
853 necessarily true at the moment. */
854 char **cptr;
855 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
856 for (cptr = argv; (cptr && *cptr); cptr++)
857 printf("DBG: arg \"%s\"\n",*cptr);
858 }
859 #endif /* DEBUG */
860
861 return SIM_RC_OK;
862 }
863
864 void
865 sim_do_command (sd,cmd)
866 SIM_DESC sd;
867 char *cmd;
868 {
869 if (sim_args_command (sd, cmd) != SIM_RC_OK)
870 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
871 cmd);
872 }
873
874 /*---------------------------------------------------------------------------*/
875 /*-- Private simulator support interface ------------------------------------*/
876 /*---------------------------------------------------------------------------*/
877
878 /* Read a null terminated string from memory, return in a buffer */
879 static char *
880 fetch_str (sd, addr)
881 SIM_DESC sd;
882 address_word addr;
883 {
884 char *buf;
885 int nr = 0;
886 char null;
887 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
888 nr++;
889 buf = NZALLOC (char, nr + 1);
890 sim_read (sd, addr, buf, nr);
891 return buf;
892 }
893
894 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
895 static void
896 sim_monitor (SIM_DESC sd,
897 sim_cpu *cpu,
898 address_word cia,
899 unsigned int reason)
900 {
901 #ifdef DEBUG
902 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
903 #endif /* DEBUG */
904
905 /* The IDT monitor actually allows two instructions per vector
906 slot. However, the simulator currently causes a trap on each
907 individual instruction. We cheat, and lose the bottom bit. */
908 reason >>= 1;
909
910 /* The following callback functions are available, however the
911 monitor we are simulating does not make use of them: get_errno,
912 isatty, lseek, rename, system, time and unlink */
913 switch (reason)
914 {
915
916 case 6: /* int open(char *path,int flags) */
917 {
918 char *path = fetch_str (sd, A0);
919 V0 = sim_io_open (sd, path, (int)A1);
920 zfree (path);
921 break;
922 }
923
924 case 7: /* int read(int file,char *ptr,int len) */
925 {
926 int fd = A0;
927 int nr = A2;
928 char *buf = zalloc (nr);
929 V0 = sim_io_read (sd, fd, buf, nr);
930 sim_write (sd, A1, buf, nr);
931 zfree (buf);
932 }
933 break;
934
935 case 8: /* int write(int file,char *ptr,int len) */
936 {
937 int fd = A0;
938 int nr = A2;
939 char *buf = zalloc (nr);
940 sim_read (sd, A1, buf, nr);
941 V0 = sim_io_write (sd, fd, buf, nr);
942 zfree (buf);
943 break;
944 }
945
946 case 10: /* int close(int file) */
947 {
948 V0 = sim_io_close (sd, (int)A0);
949 break;
950 }
951
952 case 2: /* Densan monitor: char inbyte(int waitflag) */
953 {
954 if (A0 == 0) /* waitflag == NOWAIT */
955 V0 = (unsigned_word)-1;
956 }
957 /* Drop through to case 11 */
958
959 case 11: /* char inbyte(void) */
960 {
961 char tmp;
962 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
963 {
964 sim_io_error(sd,"Invalid return from character read");
965 V0 = (unsigned_word)-1;
966 }
967 else
968 V0 = (unsigned_word)tmp;
969 break;
970 }
971
972 case 3: /* Densan monitor: void co(char chr) */
973 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
974 {
975 char tmp = (char)(A0 & 0xFF);
976 sim_io_write_stdout (sd, &tmp, sizeof(char));
977 break;
978 }
979
980 case 17: /* void _exit() */
981 {
982 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
983 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
984 (unsigned int)(A0 & 0xFFFFFFFF));
985 break;
986 }
987
988 case 28 : /* PMON flush_cache */
989 break;
990
991 case 55: /* void get_mem_info(unsigned int *ptr) */
992 /* in: A0 = pointer to three word memory location */
993 /* out: [A0 + 0] = size */
994 /* [A0 + 4] = instruction cache size */
995 /* [A0 + 8] = data cache size */
996 {
997 address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
998 H2T (value);
999 sim_write (sd, A0, (char *)&value, sizeof (value));
1000 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1001 break;
1002 }
1003
1004 case 158 : /* PMON printf */
1005 /* in: A0 = pointer to format string */
1006 /* A1 = optional argument 1 */
1007 /* A2 = optional argument 2 */
1008 /* A3 = optional argument 3 */
1009 /* out: void */
1010 /* The following is based on the PMON printf source */
1011 {
1012 address_word s = A0;
1013 char c;
1014 signed_word *ap = &A1; /* 1st argument */
1015 /* This isn't the quickest way, since we call the host print
1016 routine for every character almost. But it does avoid
1017 having to allocate and manage a temporary string buffer. */
1018 /* TODO: Include check that we only use three arguments (A1,
1019 A2 and A3) */
1020 while (sim_read (sd, s++, &c, 1) && c != '\0')
1021 {
1022 if (c == '%')
1023 {
1024 char tmp[40];
1025 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1026 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1027 while (sim_read (sd, s++, &c, 1) && c != '\0')
1028 {
1029 if (strchr ("dobxXulscefg%", s))
1030 break;
1031 else if (c == '-')
1032 fmt = FMT_LJUST;
1033 else if (c == '0')
1034 fmt = FMT_RJUST0;
1035 else if (c == '~')
1036 fmt = FMT_CENTER;
1037 else if (c == '*')
1038 {
1039 if (haddot)
1040 trunc = (int)*ap++;
1041 else
1042 width = (int)*ap++;
1043 }
1044 else if (c >= '1' && c <= '9')
1045 {
1046 address_word t = s;
1047 unsigned int n;
1048 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1049 tmp[s - t] = c;
1050 tmp[s - t] = '\0';
1051 n = (unsigned int)strtol(tmp,NULL,10);
1052 if (haddot)
1053 trunc = n;
1054 else
1055 width = n;
1056 s--;
1057 }
1058 else if (c == '.')
1059 haddot = 1;
1060 }
1061 switch (c)
1062 {
1063 case '%':
1064 sim_io_printf (sd, "%%");
1065 break;
1066 case 's':
1067 if ((int)*ap != 0)
1068 {
1069 address_word p = *ap++;
1070 char ch;
1071 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1072 sim_io_printf(sd, "%c", ch);
1073 }
1074 else
1075 sim_io_printf(sd,"(null)");
1076 break;
1077 case 'c':
1078 sim_io_printf (sd, "%c", (int)*ap++);
1079 break;
1080 default:
1081 if (c == 'l')
1082 {
1083 sim_read (sd, s++, &c, 1);
1084 if (c == 'l')
1085 {
1086 longlong = 1;
1087 sim_read (sd, s++, &c, 1);
1088 }
1089 }
1090 if (strchr ("dobxXu", c))
1091 {
1092 word64 lv = (word64) *ap++;
1093 if (c == 'b')
1094 sim_io_printf(sd,"<binary not supported>");
1095 else
1096 {
1097 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1098 if (longlong)
1099 sim_io_printf(sd, tmp, lv);
1100 else
1101 sim_io_printf(sd, tmp, (int)lv);
1102 }
1103 }
1104 else if (strchr ("eEfgG", c))
1105 {
1106 double dbl = *(double*)(ap++);
1107 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1108 sim_io_printf (sd, tmp, dbl);
1109 trunc = 0;
1110 }
1111 }
1112 }
1113 else
1114 sim_io_printf(sd, "%c", c);
1115 }
1116 break;
1117 }
1118
1119 default:
1120 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1121 reason, pr_addr(cia));
1122 break;
1123 }
1124 return;
1125 }
1126
1127 /* Store a word into memory. */
1128
1129 static void
1130 store_word (SIM_DESC sd,
1131 sim_cpu *cpu,
1132 address_word cia,
1133 uword64 vaddr,
1134 signed_word val)
1135 {
1136 address_word paddr;
1137 int uncached;
1138
1139 if ((vaddr & 3) != 0)
1140 SignalExceptionAddressStore ();
1141 else
1142 {
1143 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1144 isTARGET, isREAL))
1145 {
1146 const uword64 mask = 7;
1147 uword64 memval;
1148 unsigned int byte;
1149
1150 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1151 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1152 memval = ((uword64) val) << (8 * byte);
1153 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1154 isREAL);
1155 }
1156 }
1157 }
1158
1159 /* Load a word from memory. */
1160
1161 static signed_word
1162 load_word (SIM_DESC sd,
1163 sim_cpu *cpu,
1164 address_word cia,
1165 uword64 vaddr)
1166 {
1167 if ((vaddr & 3) != 0)
1168 SignalExceptionAddressLoad ();
1169 else
1170 {
1171 address_word paddr;
1172 int uncached;
1173
1174 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1175 isTARGET, isREAL))
1176 {
1177 const uword64 mask = 0x7;
1178 const unsigned int reverse = ReverseEndian ? 1 : 0;
1179 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1180 uword64 memval;
1181 unsigned int byte;
1182
1183 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1184 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1185 isDATA, isREAL);
1186 byte = (vaddr & mask) ^ (bigend << 2);
1187 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1188 }
1189 }
1190
1191 return 0;
1192 }
1193
1194 /* Simulate the mips16 entry and exit pseudo-instructions. These
1195 would normally be handled by the reserved instruction exception
1196 code, but for ease of simulation we just handle them directly. */
1197
1198 static void
1199 mips16_entry (SIM_DESC sd,
1200 sim_cpu *cpu,
1201 address_word cia,
1202 unsigned int insn)
1203 {
1204 int aregs, sregs, rreg;
1205
1206 #ifdef DEBUG
1207 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1208 #endif /* DEBUG */
1209
1210 aregs = (insn & 0x700) >> 8;
1211 sregs = (insn & 0x0c0) >> 6;
1212 rreg = (insn & 0x020) >> 5;
1213
1214 /* This should be checked by the caller. */
1215 if (sregs == 3)
1216 abort ();
1217
1218 if (aregs < 5)
1219 {
1220 int i;
1221 signed_word tsp;
1222
1223 /* This is the entry pseudo-instruction. */
1224
1225 for (i = 0; i < aregs; i++)
1226 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1227
1228 tsp = SP;
1229 SP -= 32;
1230
1231 if (rreg)
1232 {
1233 tsp -= 4;
1234 store_word (SD, CPU, cia, (uword64) tsp, RA);
1235 }
1236
1237 for (i = 0; i < sregs; i++)
1238 {
1239 tsp -= 4;
1240 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1241 }
1242 }
1243 else
1244 {
1245 int i;
1246 signed_word tsp;
1247
1248 /* This is the exit pseudo-instruction. */
1249
1250 tsp = SP + 32;
1251
1252 if (rreg)
1253 {
1254 tsp -= 4;
1255 RA = load_word (SD, CPU, cia, (uword64) tsp);
1256 }
1257
1258 for (i = 0; i < sregs; i++)
1259 {
1260 tsp -= 4;
1261 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1262 }
1263
1264 SP += 32;
1265
1266 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1267 {
1268 if (aregs == 5)
1269 {
1270 FGR[0] = WORD64LO (GPR[4]);
1271 FPR_STATE[0] = fmt_uninterpreted;
1272 }
1273 else if (aregs == 6)
1274 {
1275 FGR[0] = WORD64LO (GPR[5]);
1276 FGR[1] = WORD64LO (GPR[4]);
1277 FPR_STATE[0] = fmt_uninterpreted;
1278 FPR_STATE[1] = fmt_uninterpreted;
1279 }
1280 }
1281
1282 PC = RA;
1283 }
1284
1285 }
1286
1287 /*-- trace support ----------------------------------------------------------*/
1288
1289 /* The TRACE support is provided (if required) in the memory accessing
1290 routines. Since we are also providing the architecture specific
1291 features, the architecture simulation code can also deal with
1292 notifying the TRACE world of cache flushes, etc. Similarly we do
1293 not need to provide profiling support in the simulator engine,
1294 since we can sample in the instruction fetch control loop. By
1295 defining the TRACE manifest, we add tracing as a run-time
1296 option. */
1297
1298 #if defined(TRACE)
1299 /* Tracing by default produces "din" format (as required by
1300 dineroIII). Each line of such a trace file *MUST* have a din label
1301 and address field. The rest of the line is ignored, so comments can
1302 be included if desired. The first field is the label which must be
1303 one of the following values:
1304
1305 0 read data
1306 1 write data
1307 2 instruction fetch
1308 3 escape record (treated as unknown access type)
1309 4 escape record (causes cache flush)
1310
1311 The address field is a 32bit (lower-case) hexadecimal address
1312 value. The address should *NOT* be preceded by "0x".
1313
1314 The size of the memory transfer is not important when dealing with
1315 cache lines (as long as no more than a cache line can be
1316 transferred in a single operation :-), however more information
1317 could be given following the dineroIII requirement to allow more
1318 complete memory and cache simulators to provide better
1319 results. i.e. the University of Pisa has a cache simulator that can
1320 also take bus size and speed as (variable) inputs to calculate
1321 complete system performance (a much more useful ability when trying
1322 to construct an end product, rather than a processor). They
1323 currently have an ARM version of their tool called ChARM. */
1324
1325
1326 void
1327 dotrace (SIM_DESC sd,
1328 sim_cpu *cpu,
1329 FILE *tracefh,
1330 int type,
1331 SIM_ADDR address,
1332 int width,
1333 char *comment,...)
1334 {
1335 if (STATE & simTRACE) {
1336 va_list ap;
1337 fprintf(tracefh,"%d %s ; width %d ; ",
1338 type,
1339 pr_addr(address),
1340 width);
1341 va_start(ap,comment);
1342 vfprintf(tracefh,comment,ap);
1343 va_end(ap);
1344 fprintf(tracefh,"\n");
1345 }
1346 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1347 we may be generating 64bit ones, we should put the hi-32bits of the
1348 address into the comment field. */
1349
1350 /* TODO: Provide a buffer for the trace lines. We can then avoid
1351 performing writes until the buffer is filled, or the file is
1352 being closed. */
1353
1354 /* NOTE: We could consider adding a comment field to the "din" file
1355 produced using type 3 markers (unknown access). This would then
1356 allow information about the program that the "din" is for, and
1357 the MIPs world that was being simulated, to be placed into the
1358 trace file. */
1359
1360 return;
1361 }
1362 #endif /* TRACE */
1363
1364 /*---------------------------------------------------------------------------*/
1365 /*-- simulator engine -------------------------------------------------------*/
1366 /*---------------------------------------------------------------------------*/
1367
1368 static void
1369 ColdReset (SIM_DESC sd)
1370 {
1371 int cpu_nr;
1372 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1373 {
1374 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1375 /* RESET: Fixed PC address: */
1376 PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
1377 /* The reset vector address is in the unmapped, uncached memory space. */
1378
1379 SR &= ~(status_SR | status_TS | status_RP);
1380 SR |= (status_ERL | status_BEV);
1381
1382 /* Cheat and allow access to the complete register set immediately */
1383 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1384 && WITH_TARGET_WORD_BITSIZE == 64)
1385 SR |= status_FR; /* 64bit registers */
1386
1387 /* Ensure that any instructions with pending register updates are
1388 cleared: */
1389 PENDING_INVALIDATE();
1390
1391 /* Initialise the FPU registers to the unknown state */
1392 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1393 {
1394 int rn;
1395 for (rn = 0; (rn < 32); rn++)
1396 FPR_STATE[rn] = fmt_uninterpreted;
1397 }
1398
1399 }
1400 }
1401
1402 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1403 (revision 3.1) */
1404 /* Translate a virtual address to a physical address and cache
1405 coherence algorithm describing the mechanism used to resolve the
1406 memory reference. Given the virtual address vAddr, and whether the
1407 reference is to Instructions ot Data (IorD), find the corresponding
1408 physical address (pAddr) and the cache coherence algorithm (CCA)
1409 used to resolve the reference. If the virtual address is in one of
1410 the unmapped address spaces the physical address and the CCA are
1411 determined directly by the virtual address. If the virtual address
1412 is in one of the mapped address spaces then the TLB is used to
1413 determine the physical address and access type; if the required
1414 translation is not present in the TLB or the desired access is not
1415 permitted the function fails and an exception is taken.
1416
1417 NOTE: Normally (RAW == 0), when address translation fails, this
1418 function raises an exception and does not return. */
1419
1420 int
1421 address_translation (SIM_DESC sd,
1422 sim_cpu *cpu,
1423 address_word cia,
1424 address_word vAddr,
1425 int IorD,
1426 int LorS,
1427 address_word *pAddr,
1428 int *CCA,
1429 int raw)
1430 {
1431 int res = -1; /* TRUE : Assume good return */
1432
1433 #ifdef DEBUG
1434 sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
1435 #endif
1436
1437 /* Check that the address is valid for this memory model */
1438
1439 /* For a simple (flat) memory model, we simply pass virtual
1440 addressess through (mostly) unchanged. */
1441 vAddr &= 0xFFFFFFFF;
1442
1443 *pAddr = vAddr; /* default for isTARGET */
1444 *CCA = Uncached; /* not used for isHOST */
1445
1446 return(res);
1447 }
1448
1449 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1450 (revision 3.1) */
1451 /* Prefetch data from memory. Prefetch is an advisory instruction for
1452 which an implementation specific action is taken. The action taken
1453 may increase performance, but must not change the meaning of the
1454 program, or alter architecturally-visible state. */
1455
1456 void
1457 prefetch (SIM_DESC sd,
1458 sim_cpu *cpu,
1459 address_word cia,
1460 int CCA,
1461 address_word pAddr,
1462 address_word vAddr,
1463 int DATA,
1464 int hint)
1465 {
1466 #ifdef DEBUG
1467 sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
1468 #endif /* DEBUG */
1469
1470 /* For our simple memory model we do nothing */
1471 return;
1472 }
1473
1474 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1475 (revision 3.1) */
1476 /* Load a value from memory. Use the cache and main memory as
1477 specified in the Cache Coherence Algorithm (CCA) and the sort of
1478 access (IorD) to find the contents of AccessLength memory bytes
1479 starting at physical location pAddr. The data is returned in the
1480 fixed width naturally-aligned memory element (MemElem). The
1481 low-order two (or three) bits of the address and the AccessLength
1482 indicate which of the bytes within MemElem needs to be given to the
1483 processor. If the memory access type of the reference is uncached
1484 then only the referenced bytes are read from memory and valid
1485 within the memory element. If the access type is cached, and the
1486 data is not present in cache, an implementation specific size and
1487 alignment block of memory is read and loaded into the cache to
1488 satisfy a load reference. At a minimum, the block is the entire
1489 memory element. */
1490 void
1491 load_memory (SIM_DESC sd,
1492 sim_cpu *cpu,
1493 address_word cia,
1494 uword64* memvalp,
1495 uword64* memval1p,
1496 int CCA,
1497 int AccessLength,
1498 address_word pAddr,
1499 address_word vAddr,
1500 int IorD)
1501 {
1502 uword64 value = 0;
1503 uword64 value1 = 0;
1504
1505 #ifdef DEBUG
1506 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
1507 #endif /* DEBUG */
1508
1509 #if defined(WARN_MEM)
1510 if (CCA != uncached)
1511 sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1512 #endif /* WARN_MEM */
1513
1514 /* If instruction fetch then we need to check that the two lo-order
1515 bits are zero, otherwise raise a InstructionFetch exception: */
1516 if ((IorD == isINSTRUCTION)
1517 && ((pAddr & 0x3) != 0)
1518 && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
1519 SignalExceptionInstructionFetch ();
1520
1521 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1522 {
1523 /* In reality this should be a Bus Error */
1524 sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1525 AccessLength,
1526 (LOADDRMASK + 1) << 2,
1527 pr_addr (pAddr));
1528 }
1529
1530 #if defined(TRACE)
1531 dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
1532 #endif /* TRACE */
1533
1534 /* Read the specified number of bytes from memory. Adjust for
1535 host/target byte ordering/ Align the least significant byte
1536 read. */
1537
1538 switch (AccessLength)
1539 {
1540 case AccessLength_QUADWORD :
1541 {
1542 unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA,
1543 sim_core_read_map, pAddr);
1544 value1 = VH8_16 (val);
1545 value = VL8_16 (val);
1546 break;
1547 }
1548 case AccessLength_DOUBLEWORD :
1549 value = sim_core_read_aligned_8 (cpu, NULL_CIA,
1550 sim_core_read_map, pAddr);
1551 break;
1552 case AccessLength_SEPTIBYTE :
1553 value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
1554 sim_core_read_map, pAddr);
1555 break;
1556 case AccessLength_SEXTIBYTE :
1557 value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
1558 sim_core_read_map, pAddr);
1559 break;
1560 case AccessLength_QUINTIBYTE :
1561 value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
1562 sim_core_read_map, pAddr);
1563 break;
1564 case AccessLength_WORD :
1565 value = sim_core_read_aligned_4 (cpu, NULL_CIA,
1566 sim_core_read_map, pAddr);
1567 break;
1568 case AccessLength_TRIPLEBYTE :
1569 value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
1570 sim_core_read_map, pAddr);
1571 break;
1572 case AccessLength_HALFWORD :
1573 value = sim_core_read_aligned_2 (cpu, NULL_CIA,
1574 sim_core_read_map, pAddr);
1575 break;
1576 case AccessLength_BYTE :
1577 value = sim_core_read_aligned_1 (cpu, NULL_CIA,
1578 sim_core_read_map, pAddr);
1579 break;
1580 default:
1581 abort ();
1582 }
1583
1584 #ifdef DEBUG
1585 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1586 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
1587 #endif /* DEBUG */
1588
1589 /* See also store_memory. */
1590 if (AccessLength <= AccessLength_DOUBLEWORD)
1591 {
1592 if (BigEndianMem)
1593 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1594 shifted to the most significant byte position. */
1595 value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1596 else
1597 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1598 is already in the correct postition. */
1599 value <<= ((pAddr & LOADDRMASK) * 8);
1600 }
1601
1602 #ifdef DEBUG
1603 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1604 pr_uword64(value1),pr_uword64(value));
1605 #endif /* DEBUG */
1606
1607 *memvalp = value;
1608 if (memval1p) *memval1p = value1;
1609 }
1610
1611
1612 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1613 (revision 3.1) */
1614 /* Store a value to memory. The specified data is stored into the
1615 physical location pAddr using the memory hierarchy (data caches and
1616 main memory) as specified by the Cache Coherence Algorithm
1617 (CCA). The MemElem contains the data for an aligned, fixed-width
1618 memory element (word for 32-bit processors, doubleword for 64-bit
1619 processors), though only the bytes that will actually be stored to
1620 memory need to be valid. The low-order two (or three) bits of pAddr
1621 and the AccessLength field indicates which of the bytes within the
1622 MemElem data should actually be stored; only these bytes in memory
1623 will be changed. */
1624
1625 void
1626 store_memory (SIM_DESC sd,
1627 sim_cpu *cpu,
1628 address_word cia,
1629 int CCA,
1630 int AccessLength,
1631 uword64 MemElem,
1632 uword64 MemElem1, /* High order 64 bits */
1633 address_word pAddr,
1634 address_word vAddr)
1635 {
1636 #ifdef DEBUG
1637 sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
1638 #endif /* DEBUG */
1639
1640 #if defined(WARN_MEM)
1641 if (CCA != uncached)
1642 sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1643 #endif /* WARN_MEM */
1644
1645 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1646 sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
1647
1648 #if defined(TRACE)
1649 dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
1650 #endif /* TRACE */
1651
1652 #ifdef DEBUG
1653 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
1654 #endif /* DEBUG */
1655
1656 /* See also load_memory */
1657 if (AccessLength <= AccessLength_DOUBLEWORD)
1658 {
1659 if (BigEndianMem)
1660 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1661 shifted to the most significant byte position. */
1662 MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1663 else
1664 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1665 is already in the correct postition. */
1666 MemElem >>= ((pAddr & LOADDRMASK) * 8);
1667 }
1668
1669 #ifdef DEBUG
1670 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
1671 #endif /* DEBUG */
1672
1673 switch (AccessLength)
1674 {
1675 case AccessLength_QUADWORD :
1676 {
1677 unsigned_16 val = U16_8 (MemElem1, MemElem);
1678 sim_core_write_aligned_16 (cpu, NULL_CIA,
1679 sim_core_write_map, pAddr, val);
1680 break;
1681 }
1682 case AccessLength_DOUBLEWORD :
1683 sim_core_write_aligned_8 (cpu, NULL_CIA,
1684 sim_core_write_map, pAddr, MemElem);
1685 break;
1686 case AccessLength_SEPTIBYTE :
1687 sim_core_write_misaligned_7 (cpu, NULL_CIA,
1688 sim_core_write_map, pAddr, MemElem);
1689 break;
1690 case AccessLength_SEXTIBYTE :
1691 sim_core_write_misaligned_6 (cpu, NULL_CIA,
1692 sim_core_write_map, pAddr, MemElem);
1693 break;
1694 case AccessLength_QUINTIBYTE :
1695 sim_core_write_misaligned_5 (cpu, NULL_CIA,
1696 sim_core_write_map, pAddr, MemElem);
1697 break;
1698 case AccessLength_WORD :
1699 sim_core_write_aligned_4 (cpu, NULL_CIA,
1700 sim_core_write_map, pAddr, MemElem);
1701 break;
1702 case AccessLength_TRIPLEBYTE :
1703 sim_core_write_misaligned_3 (cpu, NULL_CIA,
1704 sim_core_write_map, pAddr, MemElem);
1705 break;
1706 case AccessLength_HALFWORD :
1707 sim_core_write_aligned_2 (cpu, NULL_CIA,
1708 sim_core_write_map, pAddr, MemElem);
1709 break;
1710 case AccessLength_BYTE :
1711 sim_core_write_aligned_1 (cpu, NULL_CIA,
1712 sim_core_write_map, pAddr, MemElem);
1713 break;
1714 default:
1715 abort ();
1716 }
1717
1718 return;
1719 }
1720
1721
1722 unsigned32
1723 ifetch32 (SIM_DESC sd,
1724 sim_cpu *cpu,
1725 address_word cia,
1726 address_word vaddr)
1727 {
1728 /* Copy the action of the LW instruction */
1729 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1730 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1731 unsigned64 value;
1732 address_word paddr;
1733 unsigned32 instruction;
1734 unsigned byte;
1735 int cca;
1736 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1737 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1738 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1739 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1740 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1741 return instruction;
1742 }
1743
1744
1745 unsigned16
1746 ifetch16 (SIM_DESC sd,
1747 sim_cpu *cpu,
1748 address_word cia,
1749 address_word vaddr)
1750 {
1751 /* Copy the action of the LW instruction */
1752 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1753 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1754 unsigned64 value;
1755 address_word paddr;
1756 unsigned16 instruction;
1757 unsigned byte;
1758 int cca;
1759 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1760 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1761 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1762 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1763 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1764 return instruction;
1765 }
1766
1767
1768 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1769 /* Order loads and stores to synchronise shared memory. Perform the
1770 action necessary to make the effects of groups of synchronizable
1771 loads and stores indicated by stype occur in the same order for all
1772 processors. */
1773 void
1774 sync_operation (SIM_DESC sd,
1775 sim_cpu *cpu,
1776 address_word cia,
1777 int stype)
1778 {
1779 #ifdef DEBUG
1780 sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
1781 #endif /* DEBUG */
1782 return;
1783 }
1784
1785 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1786 /* Signal an exception condition. This will result in an exception
1787 that aborts the instruction. The instruction operation pseudocode
1788 will never see a return from this function call. */
1789
1790 void
1791 signal_exception (SIM_DESC sd,
1792 sim_cpu *cpu,
1793 address_word cia,
1794 int exception,...)
1795 {
1796 int vector;
1797
1798 #ifdef DEBUG
1799 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1800 #endif /* DEBUG */
1801
1802 /* Ensure that any active atomic read/modify/write operation will fail: */
1803 LLBIT = 0;
1804
1805 switch (exception) {
1806 /* TODO: For testing purposes I have been ignoring TRAPs. In
1807 reality we should either simulate them, or allow the user to
1808 ignore them at run-time.
1809 Same for SYSCALL */
1810 case Trap :
1811 sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
1812 break;
1813
1814 case SystemCall :
1815 {
1816 va_list ap;
1817 unsigned int instruction;
1818 unsigned int code;
1819
1820 va_start(ap,exception);
1821 instruction = va_arg(ap,unsigned int);
1822 va_end(ap);
1823
1824 code = (instruction >> 6) & 0xFFFFF;
1825
1826 sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1827 code, pr_addr(cia));
1828 }
1829 break;
1830
1831 case DebugBreakPoint :
1832 if (! (Debug & Debug_DM))
1833 {
1834 if (INDELAYSLOT())
1835 {
1836 CANCELDELAYSLOT();
1837
1838 Debug |= Debug_DBD; /* signaled from within in delay slot */
1839 DEPC = cia - 4; /* reference the branch instruction */
1840 }
1841 else
1842 {
1843 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1844 DEPC = cia;
1845 }
1846
1847 Debug |= Debug_DM; /* in debugging mode */
1848 Debug |= Debug_DBp; /* raising a DBp exception */
1849 PC = 0xBFC00200;
1850 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1851 }
1852 break;
1853
1854 case ReservedInstruction :
1855 {
1856 va_list ap;
1857 unsigned int instruction;
1858 va_start(ap,exception);
1859 instruction = va_arg(ap,unsigned int);
1860 va_end(ap);
1861 /* Provide simple monitor support using ReservedInstruction
1862 exceptions. The following code simulates the fixed vector
1863 entry points into the IDT monitor by causing a simulator
1864 trap, performing the monitor operation, and returning to
1865 the address held in the $ra register (standard PCS return
1866 address). This means we only need to pre-load the vector
1867 space with suitable instruction values. For systems were
1868 actual trap instructions are used, we would not need to
1869 perform this magic. */
1870 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1871 {
1872 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
1873 /* NOTE: This assumes that a branch-and-link style
1874 instruction was used to enter the vector (which is the
1875 case with the current IDT monitor). */
1876 sim_engine_restart (SD, CPU, NULL, RA);
1877 }
1878 /* Look for the mips16 entry and exit instructions, and
1879 simulate a handler for them. */
1880 else if ((cia & 1) != 0
1881 && (instruction & 0xf81f) == 0xe809
1882 && (instruction & 0x0c0) != 0x0c0)
1883 {
1884 mips16_entry (SD, CPU, cia, instruction);
1885 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1886 }
1887 /* else fall through to normal exception processing */
1888 sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
1889 }
1890
1891 case BreakPoint:
1892 #ifdef DEBUG
1893 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1894 #endif /* DEBUG */
1895 /* Keep a copy of the current A0 in-case this is the program exit
1896 breakpoint: */
1897 {
1898 va_list ap;
1899 unsigned int instruction;
1900 va_start(ap,exception);
1901 instruction = va_arg(ap,unsigned int);
1902 va_end(ap);
1903 /* Check for our special terminating BREAK: */
1904 if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
1905 sim_engine_halt (SD, CPU, NULL, cia,
1906 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1907 }
1908 }
1909 if (STATE & simDELAYSLOT)
1910 PC = cia - 4; /* reference the branch instruction */
1911 else
1912 PC = cia;
1913 sim_engine_halt (SD, CPU, NULL, cia,
1914 sim_stopped, SIM_SIGTRAP);
1915
1916 default:
1917 /* Store exception code into current exception id variable (used
1918 by exit code): */
1919
1920 /* TODO: If not simulating exceptions then stop the simulator
1921 execution. At the moment we always stop the simulation. */
1922
1923 /* See figure 5-17 for an outline of the code below */
1924 if (! (SR & status_EXL))
1925 {
1926 CAUSE = (exception << 2);
1927 if (STATE & simDELAYSLOT)
1928 {
1929 STATE &= ~simDELAYSLOT;
1930 CAUSE |= cause_BD;
1931 EPC = (cia - 4); /* reference the branch instruction */
1932 }
1933 else
1934 EPC = cia;
1935 /* FIXME: TLB et.al. */
1936 vector = 0x180;
1937 }
1938 else
1939 {
1940 CAUSE = (exception << 2);
1941 vector = 0x180;
1942 }
1943 SR |= status_EXL;
1944 /* Store exception code into current exception id variable (used
1945 by exit code): */
1946 if (SR & status_BEV)
1947 PC = (signed)0xBFC00200 + 0x180;
1948 else
1949 PC = (signed)0x80000000 + 0x180;
1950
1951 switch ((CAUSE >> 2) & 0x1F)
1952 {
1953 case Interrupt:
1954 /* Interrupts arrive during event processing, no need to
1955 restart */
1956 return;
1957
1958 case TLBModification:
1959 case TLBLoad:
1960 case TLBStore:
1961 case AddressLoad:
1962 case AddressStore:
1963 case InstructionFetch:
1964 case DataReference:
1965 /* The following is so that the simulator will continue from the
1966 exception address on breakpoint operations. */
1967 PC = EPC;
1968 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1969 sim_stopped, SIM_SIGBUS);
1970
1971 case ReservedInstruction:
1972 case CoProcessorUnusable:
1973 PC = EPC;
1974 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1975 sim_stopped, SIM_SIGILL);
1976
1977 case IntegerOverflow:
1978 case FPE:
1979 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1980 sim_stopped, SIM_SIGFPE);
1981
1982 case Trap:
1983 case Watch:
1984 case SystemCall:
1985 PC = EPC;
1986 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1987 sim_stopped, SIM_SIGTRAP);
1988
1989 case BreakPoint:
1990 PC = EPC;
1991 sim_engine_abort (SD, CPU, NULL_CIA,
1992 "FATAL: Should not encounter a breakpoint\n");
1993
1994 default : /* Unknown internal exception */
1995 PC = EPC;
1996 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1997 sim_stopped, SIM_SIGABRT);
1998
1999 }
2000
2001 case SimulatorFault:
2002 {
2003 va_list ap;
2004 char *msg;
2005 va_start(ap,exception);
2006 msg = va_arg(ap,char *);
2007 va_end(ap);
2008 sim_engine_abort (SD, CPU, NULL_CIA,
2009 "FATAL: Simulator error \"%s\"\n",msg);
2010 }
2011 }
2012
2013 return;
2014 }
2015
2016 #if defined(WARN_RESULT)
2017 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2018 /* This function indicates that the result of the operation is
2019 undefined. However, this should not affect the instruction
2020 stream. All that is meant to happen is that the destination
2021 register is set to an undefined result. To keep the simulator
2022 simple, we just don't bother updating the destination register, so
2023 the overall result will be undefined. If desired we can stop the
2024 simulator by raising a pseudo-exception. */
2025 #define UndefinedResult() undefined_result (sd,cia)
2026 static void
2027 undefined_result(sd,cia)
2028 SIM_DESC sd;
2029 address_word cia;
2030 {
2031 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
2032 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2033 state |= simSTOP;
2034 #endif
2035 return;
2036 }
2037 #endif /* WARN_RESULT */
2038
2039 void
2040 cache_op (SIM_DESC sd,
2041 sim_cpu *cpu,
2042 address_word cia,
2043 int op,
2044 address_word pAddr,
2045 address_word vAddr,
2046 unsigned int instruction)
2047 {
2048 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2049 static int icache_warning = 1;
2050 static int dcache_warning = 1;
2051 #else
2052 static int icache_warning = 0;
2053 static int dcache_warning = 0;
2054 #endif
2055
2056 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2057 enable bit in the Status Register is clear - a coprocessor
2058 unusable exception is taken. */
2059 #if 0
2060 sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
2061 #endif
2062
2063 switch (op & 0x3) {
2064 case 0: /* instruction cache */
2065 switch (op >> 2) {
2066 case 0: /* Index Invalidate */
2067 case 1: /* Index Load Tag */
2068 case 2: /* Index Store Tag */
2069 case 4: /* Hit Invalidate */
2070 case 5: /* Fill */
2071 case 6: /* Hit Writeback */
2072 if (!icache_warning)
2073 {
2074 sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
2075 icache_warning = 1;
2076 }
2077 break;
2078
2079 default:
2080 SignalException(ReservedInstruction,instruction);
2081 break;
2082 }
2083 break;
2084
2085 case 1: /* data cache */
2086 switch (op >> 2) {
2087 case 0: /* Index Writeback Invalidate */
2088 case 1: /* Index Load Tag */
2089 case 2: /* Index Store Tag */
2090 case 3: /* Create Dirty */
2091 case 4: /* Hit Invalidate */
2092 case 5: /* Hit Writeback Invalidate */
2093 case 6: /* Hit Writeback */
2094 if (!dcache_warning)
2095 {
2096 sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
2097 dcache_warning = 1;
2098 }
2099 break;
2100
2101 default:
2102 SignalException(ReservedInstruction,instruction);
2103 break;
2104 }
2105 break;
2106
2107 default: /* unrecognised cache ID */
2108 SignalException(ReservedInstruction,instruction);
2109 break;
2110 }
2111
2112 return;
2113 }
2114
2115 /*-- FPU support routines ---------------------------------------------------*/
2116
2117 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2118 formats conform to ANSI/IEEE Std 754-1985. */
2119 /* SINGLE precision floating:
2120 * seeeeeeeefffffffffffffffffffffff
2121 * s = 1bit = sign
2122 * e = 8bits = exponent
2123 * f = 23bits = fraction
2124 */
2125 /* SINGLE precision fixed:
2126 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2127 * s = 1bit = sign
2128 * i = 31bits = integer
2129 */
2130 /* DOUBLE precision floating:
2131 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2132 * s = 1bit = sign
2133 * e = 11bits = exponent
2134 * f = 52bits = fraction
2135 */
2136 /* DOUBLE precision fixed:
2137 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2138 * s = 1bit = sign
2139 * i = 63bits = integer
2140 */
2141
2142 /* Extract sign-bit: */
2143 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2144 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2145 /* Extract biased exponent: */
2146 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2147 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2148 /* Extract unbiased Exponent: */
2149 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2150 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2151 /* Extract complete fraction field: */
2152 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2153 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2154 /* Extract numbered fraction bit: */
2155 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2156 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2157
2158 /* Explicit QNaN values used when value required: */
2159 #define FPQNaN_SINGLE (0x7FBFFFFF)
2160 #define FPQNaN_WORD (0x7FFFFFFF)
2161 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2162 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2163
2164 /* Explicit Infinity values used when required: */
2165 #define FPINF_SINGLE (0x7F800000)
2166 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2167
2168 #if 1 /* def DEBUG */
2169 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2170 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2171 #endif /* DEBUG */
2172
2173 uword64
2174 value_fpr (SIM_DESC sd,
2175 sim_cpu *cpu,
2176 address_word cia,
2177 int fpr,
2178 FP_formats fmt)
2179 {
2180 uword64 value = 0;
2181 int err = 0;
2182
2183 /* Treat unused register values, as fixed-point 64bit values: */
2184 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
2185 #if 1
2186 /* If request to read data as "uninterpreted", then use the current
2187 encoding: */
2188 fmt = FPR_STATE[fpr];
2189 #else
2190 fmt = fmt_long;
2191 #endif
2192
2193 /* For values not yet accessed, set to the desired format: */
2194 if (FPR_STATE[fpr] == fmt_uninterpreted) {
2195 FPR_STATE[fpr] = fmt;
2196 #ifdef DEBUG
2197 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
2198 #endif /* DEBUG */
2199 }
2200 if (fmt != FPR_STATE[fpr]) {
2201 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
2202 FPR_STATE[fpr] = fmt_unknown;
2203 }
2204
2205 if (FPR_STATE[fpr] == fmt_unknown) {
2206 /* Set QNaN value: */
2207 switch (fmt) {
2208 case fmt_single:
2209 value = FPQNaN_SINGLE;
2210 break;
2211
2212 case fmt_double:
2213 value = FPQNaN_DOUBLE;
2214 break;
2215
2216 case fmt_word:
2217 value = FPQNaN_WORD;
2218 break;
2219
2220 case fmt_long:
2221 value = FPQNaN_LONG;
2222 break;
2223
2224 default:
2225 err = -1;
2226 break;
2227 }
2228 } else if (SizeFGR() == 64) {
2229 switch (fmt) {
2230 case fmt_single:
2231 case fmt_word:
2232 value = (FGR[fpr] & 0xFFFFFFFF);
2233 break;
2234
2235 case fmt_uninterpreted:
2236 case fmt_double:
2237 case fmt_long:
2238 value = FGR[fpr];
2239 break;
2240
2241 default :
2242 err = -1;
2243 break;
2244 }
2245 } else {
2246 switch (fmt) {
2247 case fmt_single:
2248 case fmt_word:
2249 value = (FGR[fpr] & 0xFFFFFFFF);
2250 break;
2251
2252 case fmt_uninterpreted:
2253 case fmt_double:
2254 case fmt_long:
2255 if ((fpr & 1) == 0) { /* even registers only */
2256 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2257 } else {
2258 SignalException(ReservedInstruction,0);
2259 }
2260 break;
2261
2262 default :
2263 err = -1;
2264 break;
2265 }
2266 }
2267
2268 if (err)
2269 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2270
2271 #ifdef DEBUG
2272 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2273 #endif /* DEBUG */
2274
2275 return(value);
2276 }
2277
2278 void
2279 store_fpr (SIM_DESC sd,
2280 sim_cpu *cpu,
2281 address_word cia,
2282 int fpr,
2283 FP_formats fmt,
2284 uword64 value)
2285 {
2286 int err = 0;
2287
2288 #ifdef DEBUG
2289 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2290 #endif /* DEBUG */
2291
2292 if (SizeFGR() == 64) {
2293 switch (fmt) {
2294 case fmt_uninterpreted_32:
2295 fmt = fmt_uninterpreted;
2296 case fmt_single :
2297 case fmt_word :
2298 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2299 FPR_STATE[fpr] = fmt;
2300 break;
2301
2302 case fmt_uninterpreted_64:
2303 fmt = fmt_uninterpreted;
2304 case fmt_uninterpreted:
2305 case fmt_double :
2306 case fmt_long :
2307 FGR[fpr] = value;
2308 FPR_STATE[fpr] = fmt;
2309 break;
2310
2311 default :
2312 FPR_STATE[fpr] = fmt_unknown;
2313 err = -1;
2314 break;
2315 }
2316 } else {
2317 switch (fmt) {
2318 case fmt_uninterpreted_32:
2319 fmt = fmt_uninterpreted;
2320 case fmt_single :
2321 case fmt_word :
2322 FGR[fpr] = (value & 0xFFFFFFFF);
2323 FPR_STATE[fpr] = fmt;
2324 break;
2325
2326 case fmt_uninterpreted_64:
2327 fmt = fmt_uninterpreted;
2328 case fmt_uninterpreted:
2329 case fmt_double :
2330 case fmt_long :
2331 if ((fpr & 1) == 0) { /* even register number only */
2332 FGR[fpr+1] = (value >> 32);
2333 FGR[fpr] = (value & 0xFFFFFFFF);
2334 FPR_STATE[fpr + 1] = fmt;
2335 FPR_STATE[fpr] = fmt;
2336 } else {
2337 FPR_STATE[fpr] = fmt_unknown;
2338 FPR_STATE[fpr + 1] = fmt_unknown;
2339 SignalException(ReservedInstruction,0);
2340 }
2341 break;
2342
2343 default :
2344 FPR_STATE[fpr] = fmt_unknown;
2345 err = -1;
2346 break;
2347 }
2348 }
2349 #if defined(WARN_RESULT)
2350 else
2351 UndefinedResult();
2352 #endif /* WARN_RESULT */
2353
2354 if (err)
2355 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2356
2357 #ifdef DEBUG
2358 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2359 #endif /* DEBUG */
2360
2361 return;
2362 }
2363
2364 int
2365 NaN(op,fmt)
2366 uword64 op;
2367 FP_formats fmt;
2368 {
2369 int boolean = 0;
2370 switch (fmt) {
2371 case fmt_single:
2372 case fmt_word:
2373 {
2374 sim_fpu wop;
2375 sim_fpu_32to (&wop, op);
2376 boolean = sim_fpu_is_nan (&wop);
2377 break;
2378 }
2379 case fmt_double:
2380 case fmt_long:
2381 {
2382 sim_fpu wop;
2383 sim_fpu_64to (&wop, op);
2384 boolean = sim_fpu_is_nan (&wop);
2385 break;
2386 }
2387 default:
2388 fprintf (stderr, "Bad switch\n");
2389 abort ();
2390 }
2391
2392 #ifdef DEBUG
2393 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2394 #endif /* DEBUG */
2395
2396 return(boolean);
2397 }
2398
2399 int
2400 Infinity(op,fmt)
2401 uword64 op;
2402 FP_formats fmt;
2403 {
2404 int boolean = 0;
2405
2406 #ifdef DEBUG
2407 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
2408 #endif /* DEBUG */
2409
2410 switch (fmt) {
2411 case fmt_single:
2412 {
2413 sim_fpu wop;
2414 sim_fpu_32to (&wop, op);
2415 boolean = sim_fpu_is_infinity (&wop);
2416 break;
2417 }
2418 case fmt_double:
2419 {
2420 sim_fpu wop;
2421 sim_fpu_64to (&wop, op);
2422 boolean = sim_fpu_is_infinity (&wop);
2423 break;
2424 }
2425 default:
2426 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2427 break;
2428 }
2429
2430 #ifdef DEBUG
2431 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2432 #endif /* DEBUG */
2433
2434 return(boolean);
2435 }
2436
2437 int
2438 Less(op1,op2,fmt)
2439 uword64 op1;
2440 uword64 op2;
2441 FP_formats fmt;
2442 {
2443 int boolean = 0;
2444
2445 /* Argument checking already performed by the FPCOMPARE code */
2446
2447 #ifdef DEBUG
2448 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2449 #endif /* DEBUG */
2450
2451 /* The format type should already have been checked: */
2452 switch (fmt) {
2453 case fmt_single:
2454 {
2455 sim_fpu wop1;
2456 sim_fpu wop2;
2457 sim_fpu_32to (&wop1, op1);
2458 sim_fpu_32to (&wop2, op2);
2459 boolean = sim_fpu_is_lt (&wop1, &wop2);
2460 break;
2461 }
2462 case fmt_double:
2463 {
2464 sim_fpu wop1;
2465 sim_fpu wop2;
2466 sim_fpu_64to (&wop1, op1);
2467 sim_fpu_64to (&wop2, op2);
2468 boolean = sim_fpu_is_lt (&wop1, &wop2);
2469 break;
2470 }
2471 default:
2472 fprintf (stderr, "Bad switch\n");
2473 abort ();
2474 }
2475
2476 #ifdef DEBUG
2477 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2478 #endif /* DEBUG */
2479
2480 return(boolean);
2481 }
2482
2483 int
2484 Equal(op1,op2,fmt)
2485 uword64 op1;
2486 uword64 op2;
2487 FP_formats fmt;
2488 {
2489 int boolean = 0;
2490
2491 /* Argument checking already performed by the FPCOMPARE code */
2492
2493 #ifdef DEBUG
2494 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2495 #endif /* DEBUG */
2496
2497 /* The format type should already have been checked: */
2498 switch (fmt) {
2499 case fmt_single:
2500 {
2501 sim_fpu wop1;
2502 sim_fpu wop2;
2503 sim_fpu_32to (&wop1, op1);
2504 sim_fpu_32to (&wop2, op2);
2505 boolean = sim_fpu_is_eq (&wop1, &wop2);
2506 break;
2507 }
2508 case fmt_double:
2509 {
2510 sim_fpu wop1;
2511 sim_fpu wop2;
2512 sim_fpu_64to (&wop1, op1);
2513 sim_fpu_64to (&wop2, op2);
2514 boolean = sim_fpu_is_eq (&wop1, &wop2);
2515 break;
2516 }
2517 default:
2518 fprintf (stderr, "Bad switch\n");
2519 abort ();
2520 }
2521
2522 #ifdef DEBUG
2523 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2524 #endif /* DEBUG */
2525
2526 return(boolean);
2527 }
2528
2529 uword64
2530 AbsoluteValue(op,fmt)
2531 uword64 op;
2532 FP_formats fmt;
2533 {
2534 uword64 result = 0;
2535
2536 #ifdef DEBUG
2537 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2538 #endif /* DEBUG */
2539
2540 /* The format type should already have been checked: */
2541 switch (fmt) {
2542 case fmt_single:
2543 {
2544 sim_fpu wop;
2545 unsigned32 ans;
2546 sim_fpu_32to (&wop, op);
2547 sim_fpu_abs (&wop, &wop);
2548 sim_fpu_to32 (&ans, &wop);
2549 result = ans;
2550 break;
2551 }
2552 case fmt_double:
2553 {
2554 sim_fpu wop;
2555 unsigned64 ans;
2556 sim_fpu_64to (&wop, op);
2557 sim_fpu_abs (&wop, &wop);
2558 sim_fpu_to64 (&ans, &wop);
2559 result = ans;
2560 break;
2561 }
2562 default:
2563 fprintf (stderr, "Bad switch\n");
2564 abort ();
2565 }
2566
2567 return(result);
2568 }
2569
2570 uword64
2571 Negate(op,fmt)
2572 uword64 op;
2573 FP_formats fmt;
2574 {
2575 uword64 result = 0;
2576
2577 #ifdef DEBUG
2578 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2579 #endif /* DEBUG */
2580
2581 /* The format type should already have been checked: */
2582 switch (fmt) {
2583 case fmt_single:
2584 {
2585 sim_fpu wop;
2586 unsigned32 ans;
2587 sim_fpu_32to (&wop, op);
2588 sim_fpu_neg (&wop, &wop);
2589 sim_fpu_to32 (&ans, &wop);
2590 result = ans;
2591 break;
2592 }
2593 case fmt_double:
2594 {
2595 sim_fpu wop;
2596 unsigned64 ans;
2597 sim_fpu_64to (&wop, op);
2598 sim_fpu_neg (&wop, &wop);
2599 sim_fpu_to64 (&ans, &wop);
2600 result = ans;
2601 break;
2602 }
2603 default:
2604 fprintf (stderr, "Bad switch\n");
2605 abort ();
2606 }
2607
2608 return(result);
2609 }
2610
2611 uword64
2612 Add(op1,op2,fmt)
2613 uword64 op1;
2614 uword64 op2;
2615 FP_formats fmt;
2616 {
2617 uword64 result = 0;
2618
2619 #ifdef DEBUG
2620 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2621 #endif /* DEBUG */
2622
2623 /* The registers must specify FPRs valid for operands of type
2624 "fmt". If they are not valid, the result is undefined. */
2625
2626 /* The format type should already have been checked: */
2627 switch (fmt) {
2628 case fmt_single:
2629 {
2630 sim_fpu wop1;
2631 sim_fpu wop2;
2632 sim_fpu ans;
2633 unsigned32 res;
2634 sim_fpu_32to (&wop1, op1);
2635 sim_fpu_32to (&wop2, op2);
2636 sim_fpu_add (&ans, &wop1, &wop2);
2637 sim_fpu_to32 (&res, &ans);
2638 result = res;
2639 break;
2640 }
2641 case fmt_double:
2642 {
2643 sim_fpu wop1;
2644 sim_fpu wop2;
2645 sim_fpu ans;
2646 unsigned64 res;
2647 sim_fpu_64to (&wop1, op1);
2648 sim_fpu_64to (&wop2, op2);
2649 sim_fpu_add (&ans, &wop1, &wop2);
2650 sim_fpu_to64 (&res, &ans);
2651 result = res;
2652 break;
2653 }
2654 default:
2655 fprintf (stderr, "Bad switch\n");
2656 abort ();
2657 }
2658
2659 #ifdef DEBUG
2660 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2661 #endif /* DEBUG */
2662
2663 return(result);
2664 }
2665
2666 uword64
2667 Sub(op1,op2,fmt)
2668 uword64 op1;
2669 uword64 op2;
2670 FP_formats fmt;
2671 {
2672 uword64 result = 0;
2673
2674 #ifdef DEBUG
2675 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2676 #endif /* DEBUG */
2677
2678 /* The registers must specify FPRs valid for operands of type
2679 "fmt". If they are not valid, the result is undefined. */
2680
2681 /* The format type should already have been checked: */
2682 switch (fmt) {
2683 case fmt_single:
2684 {
2685 sim_fpu wop1;
2686 sim_fpu wop2;
2687 sim_fpu ans;
2688 unsigned32 res;
2689 sim_fpu_32to (&wop1, op1);
2690 sim_fpu_32to (&wop2, op2);
2691 sim_fpu_sub (&ans, &wop1, &wop2);
2692 sim_fpu_to32 (&res, &ans);
2693 result = res;
2694 }
2695 break;
2696 case fmt_double:
2697 {
2698 sim_fpu wop1;
2699 sim_fpu wop2;
2700 sim_fpu ans;
2701 unsigned64 res;
2702 sim_fpu_64to (&wop1, op1);
2703 sim_fpu_64to (&wop2, op2);
2704 sim_fpu_sub (&ans, &wop1, &wop2);
2705 sim_fpu_to64 (&res, &ans);
2706 result = res;
2707 }
2708 break;
2709 default:
2710 fprintf (stderr, "Bad switch\n");
2711 abort ();
2712 }
2713
2714 #ifdef DEBUG
2715 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2716 #endif /* DEBUG */
2717
2718 return(result);
2719 }
2720
2721 uword64
2722 Multiply(op1,op2,fmt)
2723 uword64 op1;
2724 uword64 op2;
2725 FP_formats fmt;
2726 {
2727 uword64 result = 0;
2728
2729 #ifdef DEBUG
2730 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2731 #endif /* DEBUG */
2732
2733 /* The registers must specify FPRs valid for operands of type
2734 "fmt". If they are not valid, the result is undefined. */
2735
2736 /* The format type should already have been checked: */
2737 switch (fmt) {
2738 case fmt_single:
2739 {
2740 sim_fpu wop1;
2741 sim_fpu wop2;
2742 sim_fpu ans;
2743 unsigned32 res;
2744 sim_fpu_32to (&wop1, op1);
2745 sim_fpu_32to (&wop2, op2);
2746 sim_fpu_mul (&ans, &wop1, &wop2);
2747 sim_fpu_to32 (&res, &ans);
2748 result = res;
2749 break;
2750 }
2751 case fmt_double:
2752 {
2753 sim_fpu wop1;
2754 sim_fpu wop2;
2755 sim_fpu ans;
2756 unsigned64 res;
2757 sim_fpu_64to (&wop1, op1);
2758 sim_fpu_64to (&wop2, op2);
2759 sim_fpu_mul (&ans, &wop1, &wop2);
2760 sim_fpu_to64 (&res, &ans);
2761 result = res;
2762 break;
2763 }
2764 default:
2765 fprintf (stderr, "Bad switch\n");
2766 abort ();
2767 }
2768
2769 #ifdef DEBUG
2770 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2771 #endif /* DEBUG */
2772
2773 return(result);
2774 }
2775
2776 uword64
2777 Divide(op1,op2,fmt)
2778 uword64 op1;
2779 uword64 op2;
2780 FP_formats fmt;
2781 {
2782 uword64 result = 0;
2783
2784 #ifdef DEBUG
2785 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2786 #endif /* DEBUG */
2787
2788 /* The registers must specify FPRs valid for operands of type
2789 "fmt". If they are not valid, the result is undefined. */
2790
2791 /* The format type should already have been checked: */
2792 switch (fmt) {
2793 case fmt_single:
2794 {
2795 sim_fpu wop1;
2796 sim_fpu wop2;
2797 sim_fpu ans;
2798 unsigned32 res;
2799 sim_fpu_32to (&wop1, op1);
2800 sim_fpu_32to (&wop2, op2);
2801 sim_fpu_div (&ans, &wop1, &wop2);
2802 sim_fpu_to32 (&res, &ans);
2803 result = res;
2804 break;
2805 }
2806 case fmt_double:
2807 {
2808 sim_fpu wop1;
2809 sim_fpu wop2;
2810 sim_fpu ans;
2811 unsigned64 res;
2812 sim_fpu_64to (&wop1, op1);
2813 sim_fpu_64to (&wop2, op2);
2814 sim_fpu_div (&ans, &wop1, &wop2);
2815 sim_fpu_to64 (&res, &ans);
2816 result = res;
2817 break;
2818 }
2819 default:
2820 fprintf (stderr, "Bad switch\n");
2821 abort ();
2822 }
2823
2824 #ifdef DEBUG
2825 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2826 #endif /* DEBUG */
2827
2828 return(result);
2829 }
2830
2831 uword64 UNUSED
2832 Recip(op,fmt)
2833 uword64 op;
2834 FP_formats fmt;
2835 {
2836 uword64 result = 0;
2837
2838 #ifdef DEBUG
2839 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2840 #endif /* DEBUG */
2841
2842 /* The registers must specify FPRs valid for operands of type
2843 "fmt". If they are not valid, the result is undefined. */
2844
2845 /* The format type should already have been checked: */
2846 switch (fmt) {
2847 case fmt_single:
2848 {
2849 sim_fpu wop;
2850 sim_fpu ans;
2851 unsigned32 res;
2852 sim_fpu_32to (&wop, op);
2853 sim_fpu_inv (&ans, &wop);
2854 sim_fpu_to32 (&res, &ans);
2855 result = res;
2856 break;
2857 }
2858 case fmt_double:
2859 {
2860 sim_fpu wop;
2861 sim_fpu ans;
2862 unsigned64 res;
2863 sim_fpu_64to (&wop, op);
2864 sim_fpu_inv (&ans, &wop);
2865 sim_fpu_to64 (&res, &ans);
2866 result = res;
2867 break;
2868 }
2869 default:
2870 fprintf (stderr, "Bad switch\n");
2871 abort ();
2872 }
2873
2874 #ifdef DEBUG
2875 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2876 #endif /* DEBUG */
2877
2878 return(result);
2879 }
2880
2881 uword64
2882 SquareRoot(op,fmt)
2883 uword64 op;
2884 FP_formats fmt;
2885 {
2886 uword64 result = 0;
2887
2888 #ifdef DEBUG
2889 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2890 #endif /* DEBUG */
2891
2892 /* The registers must specify FPRs valid for operands of type
2893 "fmt". If they are not valid, the result is undefined. */
2894
2895 /* The format type should already have been checked: */
2896 switch (fmt) {
2897 case fmt_single:
2898 {
2899 sim_fpu wop;
2900 sim_fpu ans;
2901 unsigned32 res;
2902 sim_fpu_32to (&wop, op);
2903 sim_fpu_sqrt (&ans, &wop);
2904 sim_fpu_to32 (&res, &ans);
2905 result = res;
2906 break;
2907 }
2908 case fmt_double:
2909 {
2910 sim_fpu wop;
2911 sim_fpu ans;
2912 unsigned64 res;
2913 sim_fpu_64to (&wop, op);
2914 sim_fpu_sqrt (&ans, &wop);
2915 sim_fpu_to64 (&res, &ans);
2916 result = res;
2917 break;
2918 }
2919 default:
2920 fprintf (stderr, "Bad switch\n");
2921 abort ();
2922 }
2923
2924 #ifdef DEBUG
2925 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2926 #endif /* DEBUG */
2927
2928 return(result);
2929 }
2930
2931 uword64
2932 Max (uword64 op1,
2933 uword64 op2,
2934 FP_formats fmt)
2935 {
2936 int cmp;
2937 unsigned64 result;
2938
2939 #ifdef DEBUG
2940 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2941 #endif /* DEBUG */
2942
2943 /* The registers must specify FPRs valid for operands of type
2944 "fmt". If they are not valid, the result is undefined. */
2945
2946 /* The format type should already have been checked: */
2947 switch (fmt)
2948 {
2949 case fmt_single:
2950 {
2951 sim_fpu wop1;
2952 sim_fpu wop2;
2953 sim_fpu_32to (&wop1, op1);
2954 sim_fpu_32to (&wop2, op2);
2955 cmp = sim_fpu_cmp (&wop1, &wop2);
2956 break;
2957 }
2958 case fmt_double:
2959 {
2960 sim_fpu wop1;
2961 sim_fpu wop2;
2962 sim_fpu_64to (&wop1, op1);
2963 sim_fpu_64to (&wop2, op2);
2964 cmp = sim_fpu_cmp (&wop1, &wop2);
2965 break;
2966 }
2967 default:
2968 fprintf (stderr, "Bad switch\n");
2969 abort ();
2970 }
2971
2972 switch (cmp)
2973 {
2974 case SIM_FPU_IS_SNAN:
2975 case SIM_FPU_IS_QNAN:
2976 result = op1;
2977 case SIM_FPU_IS_NINF:
2978 case SIM_FPU_IS_NNUMBER:
2979 case SIM_FPU_IS_NDENORM:
2980 case SIM_FPU_IS_NZERO:
2981 result = op2; /* op1 - op2 < 0 */
2982 case SIM_FPU_IS_PINF:
2983 case SIM_FPU_IS_PNUMBER:
2984 case SIM_FPU_IS_PDENORM:
2985 case SIM_FPU_IS_PZERO:
2986 result = op1; /* op1 - op2 > 0 */
2987 default:
2988 fprintf (stderr, "Bad switch\n");
2989 abort ();
2990 }
2991
2992 #ifdef DEBUG
2993 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2994 #endif /* DEBUG */
2995
2996 return(result);
2997 }
2998
2999 uword64
3000 Min (uword64 op1,
3001 uword64 op2,
3002 FP_formats fmt)
3003 {
3004 int cmp;
3005 unsigned64 result;
3006
3007 #ifdef DEBUG
3008 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
3009 #endif /* DEBUG */
3010
3011 /* The registers must specify FPRs valid for operands of type
3012 "fmt". If they are not valid, the result is undefined. */
3013
3014 /* The format type should already have been checked: */
3015 switch (fmt)
3016 {
3017 case fmt_single:
3018 {
3019 sim_fpu wop1;
3020 sim_fpu wop2;
3021 sim_fpu_32to (&wop1, op1);
3022 sim_fpu_32to (&wop2, op2);
3023 cmp = sim_fpu_cmp (&wop1, &wop2);
3024 break;
3025 }
3026 case fmt_double:
3027 {
3028 sim_fpu wop1;
3029 sim_fpu wop2;
3030 sim_fpu_64to (&wop1, op1);
3031 sim_fpu_64to (&wop2, op2);
3032 cmp = sim_fpu_cmp (&wop1, &wop2);
3033 break;
3034 }
3035 default:
3036 fprintf (stderr, "Bad switch\n");
3037 abort ();
3038 }
3039
3040 switch (cmp)
3041 {
3042 case SIM_FPU_IS_SNAN:
3043 case SIM_FPU_IS_QNAN:
3044 result = op1;
3045 case SIM_FPU_IS_NINF:
3046 case SIM_FPU_IS_NNUMBER:
3047 case SIM_FPU_IS_NDENORM:
3048 case SIM_FPU_IS_NZERO:
3049 result = op1; /* op1 - op2 < 0 */
3050 case SIM_FPU_IS_PINF:
3051 case SIM_FPU_IS_PNUMBER:
3052 case SIM_FPU_IS_PDENORM:
3053 case SIM_FPU_IS_PZERO:
3054 result = op2; /* op1 - op2 > 0 */
3055 default:
3056 fprintf (stderr, "Bad switch\n");
3057 abort ();
3058 }
3059
3060 #ifdef DEBUG
3061 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
3062 #endif /* DEBUG */
3063
3064 return(result);
3065 }
3066
3067 uword64
3068 convert (SIM_DESC sd,
3069 sim_cpu *cpu,
3070 address_word cia,
3071 int rm,
3072 uword64 op,
3073 FP_formats from,
3074 FP_formats to)
3075 {
3076 sim_fpu wop;
3077 sim_fpu_round round;
3078 unsigned32 result32;
3079 unsigned64 result64;
3080
3081 #ifdef DEBUG
3082 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
3083 #endif /* DEBUG */
3084
3085 switch (rm)
3086 {
3087 case FP_RM_NEAREST:
3088 /* Round result to nearest representable value. When two
3089 representable values are equally near, round to the value
3090 that has a least significant bit of zero (i.e. is even). */
3091 round = sim_fpu_round_near;
3092 break;
3093 case FP_RM_TOZERO:
3094 /* Round result to the value closest to, and not greater in
3095 magnitude than, the result. */
3096 round = sim_fpu_round_zero;
3097 break;
3098 case FP_RM_TOPINF:
3099 /* Round result to the value closest to, and not less than,
3100 the result. */
3101 round = sim_fpu_round_up;
3102 break;
3103
3104 case FP_RM_TOMINF:
3105 /* Round result to the value closest to, and not greater than,
3106 the result. */
3107 round = sim_fpu_round_down;
3108 break;
3109 default:
3110 round = 0;
3111 fprintf (stderr, "Bad switch\n");
3112 abort ();
3113 }
3114
3115 /* Convert the input to sim_fpu internal format */
3116 switch (from)
3117 {
3118 case fmt_double:
3119 sim_fpu_64to (&wop, op);
3120 break;
3121 case fmt_single:
3122 sim_fpu_32to (&wop, op);
3123 break;
3124 case fmt_word:
3125 sim_fpu_i32to (&wop, op, round);
3126 break;
3127 case fmt_long:
3128 sim_fpu_i64to (&wop, op, round);
3129 break;
3130 default:
3131 fprintf (stderr, "Bad switch\n");
3132 abort ();
3133 }
3134
3135 /* Convert sim_fpu format into the output */
3136 /* The value WOP is converted to the destination format, rounding
3137 using mode RM. When the destination is a fixed-point format, then
3138 a source value of Infinity, NaN or one which would round to an
3139 integer outside the fixed point range then an IEEE Invalid
3140 Operation condition is raised. */
3141 switch (to)
3142 {
3143 case fmt_single:
3144 sim_fpu_round_32 (&wop, round, 0);
3145 sim_fpu_to32 (&result32, &wop);
3146 result64 = result32;
3147 break;
3148 case fmt_double:
3149 sim_fpu_round_64 (&wop, round, 0);
3150 sim_fpu_to64 (&result64, &wop);
3151 break;
3152 case fmt_word:
3153 sim_fpu_to32i (&result32, &wop, round);
3154 result64 = result32;
3155 break;
3156 case fmt_long:
3157 sim_fpu_to64i (&result64, &wop, round);
3158 break;
3159 default:
3160 result64 = 0;
3161 fprintf (stderr, "Bad switch\n");
3162 abort ();
3163 }
3164
3165 #ifdef DEBUG
3166 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
3167 #endif /* DEBUG */
3168
3169 return(result64);
3170 }
3171
3172
3173 /*-- co-processor support routines ------------------------------------------*/
3174
3175 static int UNUSED
3176 CoProcPresent(coproc_number)
3177 unsigned int coproc_number;
3178 {
3179 /* Return TRUE if simulator provides a model for the given co-processor number */
3180 return(0);
3181 }
3182
3183 void
3184 cop_lw (SIM_DESC sd,
3185 sim_cpu *cpu,
3186 address_word cia,
3187 int coproc_num,
3188 int coproc_reg,
3189 unsigned int memword)
3190 {
3191 switch (coproc_num)
3192 {
3193 case 1:
3194 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3195 {
3196 #ifdef DEBUG
3197 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
3198 #endif
3199 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
3200 FPR_STATE[coproc_reg] = fmt_uninterpreted;
3201 break;
3202 }
3203
3204 default:
3205 #if 0 /* this should be controlled by a configuration option */
3206 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
3207 #endif
3208 break;
3209 }
3210
3211 return;
3212 }
3213
3214 void
3215 cop_ld (SIM_DESC sd,
3216 sim_cpu *cpu,
3217 address_word cia,
3218 int coproc_num,
3219 int coproc_reg,
3220 uword64 memword)
3221 {
3222 switch (coproc_num) {
3223 case 1:
3224 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3225 {
3226 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
3227 break;
3228 }
3229
3230 default:
3231 #if 0 /* this message should be controlled by a configuration option */
3232 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
3233 #endif
3234 break;
3235 }
3236
3237 return;
3238 }
3239
3240 unsigned int
3241 cop_sw (SIM_DESC sd,
3242 sim_cpu *cpu,
3243 address_word cia,
3244 int coproc_num,
3245 int coproc_reg)
3246 {
3247 unsigned int value = 0;
3248
3249 switch (coproc_num)
3250 {
3251 case 1:
3252 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3253 {
3254 FP_formats hold;
3255 hold = FPR_STATE[coproc_reg];
3256 FPR_STATE[coproc_reg] = fmt_word;
3257 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
3258 FPR_STATE[coproc_reg] = hold;
3259 break;
3260 }
3261
3262 default:
3263 #if 0 /* should be controlled by configuration option */
3264 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3265 #endif
3266 break;
3267 }
3268
3269 return(value);
3270 }
3271
3272 uword64
3273 cop_sd (SIM_DESC sd,
3274 sim_cpu *cpu,
3275 address_word cia,
3276 int coproc_num,
3277 int coproc_reg)
3278 {
3279 uword64 value = 0;
3280 switch (coproc_num)
3281 {
3282 case 1:
3283 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3284 {
3285 value = ValueFPR(coproc_reg,fmt_uninterpreted);
3286 break;
3287 }
3288
3289 default:
3290 #if 0 /* should be controlled by configuration option */
3291 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3292 #endif
3293 break;
3294 }
3295
3296 return(value);
3297 }
3298
3299 void
3300 decode_coproc (SIM_DESC sd,
3301 sim_cpu *cpu,
3302 address_word cia,
3303 unsigned int instruction)
3304 {
3305 int coprocnum = ((instruction >> 26) & 3);
3306
3307 switch (coprocnum)
3308 {
3309 case 0: /* standard CPU control and cache registers */
3310 {
3311 int code = ((instruction >> 21) & 0x1F);
3312 /* R4000 Users Manual (second edition) lists the following CP0
3313 instructions:
3314 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3315 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3316 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3317 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3318 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3319 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3320 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3321 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3322 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3323 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3324 */
3325 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
3326 {
3327 int rt = ((instruction >> 16) & 0x1F);
3328 int rd = ((instruction >> 11) & 0x1F);
3329
3330 switch (rd) /* NOTEs: Standard CP0 registers */
3331 {
3332 /* 0 = Index R4000 VR4100 VR4300 */
3333 /* 1 = Random R4000 VR4100 VR4300 */
3334 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3335 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3336 /* 4 = Context R4000 VR4100 VR4300 */
3337 /* 5 = PageMask R4000 VR4100 VR4300 */
3338 /* 6 = Wired R4000 VR4100 VR4300 */
3339 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3340 /* 9 = Count R4000 VR4100 VR4300 */
3341 /* 10 = EntryHi R4000 VR4100 VR4300 */
3342 /* 11 = Compare R4000 VR4100 VR4300 */
3343 /* 12 = SR R4000 VR4100 VR4300 */
3344 case 12:
3345 if (code == 0x00)
3346 GPR[rt] = SR;
3347 else
3348 SR = GPR[rt];
3349 break;
3350 /* 13 = Cause R4000 VR4100 VR4300 */
3351 case 13:
3352 if (code == 0x00)
3353 GPR[rt] = CAUSE;
3354 else
3355 CAUSE = GPR[rt];
3356 break;
3357 /* 14 = EPC R4000 VR4100 VR4300 */
3358 /* 15 = PRId R4000 VR4100 VR4300 */
3359 #ifdef SUBTARGET_R3900
3360 /* 16 = Debug */
3361 case 16:
3362 if (code == 0x00)
3363 GPR[rt] = Debug;
3364 else
3365 Debug = GPR[rt];
3366 break;
3367 #else
3368 /* 16 = Config R4000 VR4100 VR4300 */
3369 case 16:
3370 if (code == 0x00)
3371 GPR[rt] = C0_CONFIG;
3372 else
3373 C0_CONFIG = GPR[rt];
3374 break;
3375 #endif
3376 #ifdef SUBTARGET_R3900
3377 /* 17 = Debug */
3378 case 17:
3379 if (code == 0x00)
3380 GPR[rt] = DEPC;
3381 else
3382 DEPC = GPR[rt];
3383 break;
3384 #else
3385 /* 17 = LLAddr R4000 VR4100 VR4300 */
3386 #endif
3387 /* 18 = WatchLo R4000 VR4100 VR4300 */
3388 /* 19 = WatchHi R4000 VR4100 VR4300 */
3389 /* 20 = XContext R4000 VR4100 VR4300 */
3390 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3391 /* 27 = CacheErr R4000 VR4100 */
3392 /* 28 = TagLo R4000 VR4100 VR4300 */
3393 /* 29 = TagHi R4000 VR4100 VR4300 */
3394 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3395 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3396 /* CPR[0,rd] = GPR[rt]; */
3397 default:
3398 if (code == 0x00)
3399 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3400 else
3401 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3402 }
3403 }
3404 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3405 {
3406 /* ERET */
3407 if (SR & status_ERL)
3408 {
3409 /* Oops, not yet available */
3410 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3411 PC = EPC;
3412 SR &= ~status_ERL;
3413 }
3414 else
3415 {
3416 PC = EPC;
3417 SR &= ~status_EXL;
3418 }
3419 }
3420 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3421 {
3422 /* RFE */
3423 }
3424 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3425 {
3426 /* DERET */
3427 Debug &= ~Debug_DM;
3428 DELAYSLOT();
3429 DSPC = DEPC;
3430 }
3431 else
3432 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3433 /* TODO: When executing an ERET or RFE instruction we should
3434 clear LLBIT, to ensure that any out-standing atomic
3435 read/modify/write sequence fails. */
3436 }
3437 break;
3438
3439 case 2: /* undefined co-processor */
3440 sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3441 break;
3442
3443 case 1: /* should not occur (FPU co-processor) */
3444 case 3: /* should not occur (FPU co-processor) */
3445 SignalException(ReservedInstruction,instruction);
3446 break;
3447 }
3448
3449 return;
3450 }
3451
3452 /*-- instruction simulation -------------------------------------------------*/
3453
3454 /* When the IGEN simulator is being built, the function below is be
3455 replaced by a generated version. However, WITH_IGEN == 2 indicates
3456 that the fubction below should be compiled but under a different
3457 name (to allow backward compatibility) */
3458
3459 #if (WITH_IGEN != 1)
3460 #if (WITH_IGEN > 1)
3461 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3462 void
3463 old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3464 #else
3465 void
3466 sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3467 #endif
3468 SIM_DESC sd;
3469 int next_cpu_nr; /* ignore */
3470 int nr_cpus; /* ignore */
3471 int siggnal; /* ignore */
3472 {
3473 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
3474 #if !defined(FASTSIM)
3475 unsigned int pipeline_count = 1;
3476 #endif
3477
3478 #ifdef DEBUG
3479 if (STATE_MEMORY (sd) == NULL) {
3480 printf("DBG: simulate() entered with no memory\n");
3481 exit(1);
3482 }
3483 #endif /* DEBUG */
3484
3485 #if 0 /* Disabled to check that everything works OK */
3486 /* The VR4300 seems to sign-extend the PC on its first
3487 access. However, this may just be because it is currently
3488 configured in 32bit mode. However... */
3489 PC = SIGNEXTEND(PC,32);
3490 #endif
3491
3492 /* main controlling loop */
3493 while (1) {
3494 /* vaddr is slowly being replaced with cia - current instruction
3495 address */
3496 address_word cia = (uword64)PC;
3497 address_word vaddr = cia;
3498 address_word paddr;
3499 int cca;
3500 unsigned int instruction; /* uword64? what's this used for? FIXME! */
3501
3502 #ifdef DEBUG
3503 {
3504 printf("DBG: state = 0x%08X :",state);
3505 if (state & simHALTEX) printf(" simHALTEX");
3506 if (state & simHALTIN) printf(" simHALTIN");
3507 printf("\n");
3508 }
3509 #endif /* DEBUG */
3510
3511 DSSTATE = (STATE & simDELAYSLOT);
3512 #ifdef DEBUG
3513 if (dsstate)
3514 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
3515 #endif /* DEBUG */
3516
3517 /* Fetch the next instruction from the simulator memory: */
3518 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
3519 if ((vaddr & 1) == 0) {
3520 /* Copy the action of the LW instruction */
3521 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3522 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3523 uword64 value;
3524 unsigned int byte;
3525 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
3526 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
3527 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3528 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3529 } else {
3530 /* Copy the action of the LH instruction */
3531 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3532 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3533 uword64 value;
3534 unsigned int byte;
3535 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3536 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
3537 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
3538 paddr & ~ (uword64) 1,
3539 vaddr, isINSTRUCTION, isREAL);
3540 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3541 instruction = ((value >> (8 * byte)) & 0xFFFF);
3542 }
3543 } else {
3544 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
3545 exit(1);
3546 }
3547
3548 #ifdef DEBUG
3549 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
3550 #endif /* DEBUG */
3551
3552 /* This is required by exception processing, to ensure that we can
3553 cope with exceptions in the delay slots of branches that may
3554 already have changed the PC. */
3555 if ((vaddr & 1) == 0)
3556 PC += 4; /* increment ready for the next fetch */
3557 else
3558 PC += 2;
3559 /* NOTE: If we perform a delay slot change to the PC, this
3560 increment is not requuired. However, it would make the
3561 simulator more complicated to try and avoid this small hit. */
3562
3563 /* Currently this code provides a simple model. For more
3564 complicated models we could perform exception status checks at
3565 this point, and set the simSTOP state as required. This could
3566 also include processing any hardware interrupts raised by any
3567 I/O model attached to the simulator context.
3568
3569 Support for "asynchronous" I/O events within the simulated world
3570 could be providing by managing a counter, and calling a I/O
3571 specific handler when a particular threshold is reached. On most
3572 architectures a decrement and check for zero operation is
3573 usually quicker than an increment and compare. However, the
3574 process of managing a known value decrement to zero, is higher
3575 than the cost of using an explicit value UINT_MAX into the
3576 future. Which system is used will depend on how complicated the
3577 I/O model is, and how much it is likely to affect the simulator
3578 bandwidth.
3579
3580 If events need to be scheduled further in the future than
3581 UINT_MAX event ticks, then the I/O model should just provide its
3582 own counter, triggered from the event system. */
3583
3584 /* MIPS pipeline ticks. To allow for future support where the
3585 pipeline hit of individual instructions is known, this control
3586 loop manages a "pipeline_count" variable. It is initialised to
3587 1 (one), and will only be changed by the simulator engine when
3588 executing an instruction. If the engine does not have access to
3589 pipeline cycle count information then all instructions will be
3590 treated as using a single cycle. NOTE: A standard system is not
3591 provided by the default simulator because different MIPS
3592 architectures have different cycle counts for the same
3593 instructions.
3594
3595 [NOTE: pipeline_count has been replaced the event queue] */
3596
3597 /* shuffle the floating point status pipeline state */
3598 ENGINE_ISSUE_PREFIX_HOOK();
3599
3600 /* NOTE: For multi-context simulation environments the "instruction"
3601 variable should be local to this routine. */
3602
3603 /* Shorthand accesses for engine. Note: If we wanted to use global
3604 variables (and a single-threaded simulator engine), then we can
3605 create the actual variables with these names. */
3606
3607 if (!(STATE & simSKIPNEXT)) {
3608 /* Include the simulator engine */
3609 #include "oengine.c"
3610 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3611 #error "Mismatch between run-time simulator code and simulation engine"
3612 #endif
3613 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3614 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3615 #endif
3616 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3617 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3618 #endif
3619
3620 #if defined(WARN_LOHI)
3621 /* Decrement the HI/LO validity ticks */
3622 if (HIACCESS > 0)
3623 HIACCESS--;
3624 if (LOACCESS > 0)
3625 LOACCESS--;
3626 /* start-sanitize-r5900 */
3627 if (HI1ACCESS > 0)
3628 HI1ACCESS--;
3629 if (LO1ACCESS > 0)
3630 LO1ACCESS--;
3631 /* end-sanitize-r5900 */
3632 #endif /* WARN_LOHI */
3633
3634 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3635 should check for it being changed. It is better doing it here,
3636 than within the simulator, since it will help keep the simulator
3637 small. */
3638 if (ZERO != 0) {
3639 #if defined(WARN_ZERO)
3640 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
3641 #endif /* WARN_ZERO */
3642 ZERO = 0; /* reset back to zero before next instruction */
3643 }
3644 } else /* simSKIPNEXT check */
3645 STATE &= ~simSKIPNEXT;
3646
3647 /* If the delay slot was active before the instruction is
3648 executed, then update the PC to its new value: */
3649 if (DSSTATE) {
3650 #ifdef DEBUG
3651 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
3652 #endif /* DEBUG */
3653 PC = DSPC;
3654 CANCELDELAYSLOT();
3655 }
3656
3657 if (MIPSISA < 4)
3658 PENDING_TICK();
3659
3660 #if !defined(FASTSIM)
3661 if (sim_events_tickn (sd, pipeline_count))
3662 {
3663 /* cpu->cia = cia; */
3664 sim_events_process (sd);
3665 }
3666 #else
3667 if (sim_events_tick (sd))
3668 {
3669 /* cpu->cia = cia; */
3670 sim_events_process (sd);
3671 }
3672 #endif /* FASTSIM */
3673 }
3674 }
3675 #endif
3676
3677
3678 /* This code copied from gdb's utils.c. Would like to share this code,
3679 but don't know of a common place where both could get to it. */
3680
3681 /* Temporary storage using circular buffer */
3682 #define NUMCELLS 16
3683 #define CELLSIZE 32
3684 static char*
3685 get_cell()
3686 {
3687 static char buf[NUMCELLS][CELLSIZE];
3688 static int cell=0;
3689 if (++cell>=NUMCELLS) cell=0;
3690 return buf[cell];
3691 }
3692
3693 /* Print routines to handle variable size regs, etc */
3694
3695 /* Eliminate warning from compiler on 32-bit systems */
3696 static int thirty_two = 32;
3697
3698 char*
3699 pr_addr(addr)
3700 SIM_ADDR addr;
3701 {
3702 char *paddr_str=get_cell();
3703 switch (sizeof(addr))
3704 {
3705 case 8:
3706 sprintf(paddr_str,"%08lx%08lx",
3707 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3708 break;
3709 case 4:
3710 sprintf(paddr_str,"%08lx",(unsigned long)addr);
3711 break;
3712 case 2:
3713 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3714 break;
3715 default:
3716 sprintf(paddr_str,"%x",addr);
3717 }
3718 return paddr_str;
3719 }
3720
3721 char*
3722 pr_uword64(addr)
3723 uword64 addr;
3724 {
3725 char *paddr_str=get_cell();
3726 sprintf(paddr_str,"%08lx%08lx",
3727 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3728 return paddr_str;
3729 }
3730
3731
3732 void
3733 pending_tick (SIM_DESC sd,
3734 sim_cpu *cpu,
3735 address_word cia)
3736 {
3737 if (PENDING_TRACE)
3738 sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
3739 if (PENDING_OUT != PENDING_IN)
3740 {
3741 int loop;
3742 int index = PENDING_OUT;
3743 int total = PENDING_TOTAL;
3744 if (PENDING_TOTAL == 0)
3745 sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3746 for (loop = 0; (loop < total); loop++)
3747 {
3748 if (PENDING_SLOT_DEST[index] != NULL)
3749 {
3750 PENDING_SLOT_DELAY[index] -= 1;
3751 if (PENDING_SLOT_DELAY[index] == 0)
3752 {
3753 if (PENDING_SLOT_BIT[index] >= 0)
3754 switch (PENDING_SLOT_SIZE[index])
3755 {
3756 case 32:
3757 if (PENDING_SLOT_VALUE[index])
3758 *(unsigned32*)PENDING_SLOT_DEST[index] |=
3759 BIT32 (PENDING_SLOT_BIT[index]);
3760 else
3761 *(unsigned32*)PENDING_SLOT_DEST[index] &=
3762 BIT32 (PENDING_SLOT_BIT[index]);
3763 break;
3764 case 64:
3765 if (PENDING_SLOT_VALUE[index])
3766 *(unsigned64*)PENDING_SLOT_DEST[index] |=
3767 BIT64 (PENDING_SLOT_BIT[index]);
3768 else
3769 *(unsigned64*)PENDING_SLOT_DEST[index] &=
3770 BIT64 (PENDING_SLOT_BIT[index]);
3771 break;
3772 break;
3773 }
3774 else
3775 switch (PENDING_SLOT_SIZE[index])
3776 {
3777 case 32:
3778 *(unsigned32*)PENDING_SLOT_DEST[index] =
3779 PENDING_SLOT_VALUE[index];
3780 break;
3781 case 64:
3782 *(unsigned64*)PENDING_SLOT_DEST[index] =
3783 PENDING_SLOT_VALUE[index];
3784 break;
3785 }
3786 }
3787 if (PENDING_OUT == index)
3788 {
3789 PENDING_SLOT_DEST[index] = NULL;
3790 PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
3791 PENDING_TOTAL--;
3792 }
3793 }
3794 }
3795 index = (index + 1) % PSLOTS;
3796 }
3797 }
3798
3799 /*---------------------------------------------------------------------------*/
3800 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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