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* MONSTER sky -> devo merge
[deliverable/binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Date$
18
19 NOTEs:
20
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
24 code on the hardware.
25
26 */
27
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
32 #define TRACE (1)
33 #endif
34
35 #include "bfd.h"
36 #include "sim-main.h"
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
40 #include "sim-hw.h"
41
42 #if WITH_IGEN
43 #include "itable.h"
44 #endif
45
46 /* start-sanitize-sky */
47 #ifdef TARGET_SKY
48 #include "sky-vu.h"
49 #include "sky-vpe.h"
50 #include "sky-libvpe.h"
51 #include "sky-vif.h"
52 #include "idecode.h"
53 #include "sky-gdb.h"
54 #endif
55 /* end-sanitize-sky */
56
57 #include "config.h"
58
59 #include <stdio.h>
60 #include <stdarg.h>
61 #include <ansidecl.h>
62 #include <ctype.h>
63 #include <limits.h>
64 #include <math.h>
65 #ifdef HAVE_STDLIB_H
66 #include <stdlib.h>
67 #endif
68 #ifdef HAVE_STRING_H
69 #include <string.h>
70 #else
71 #ifdef HAVE_STRINGS_H
72 #include <strings.h>
73 #endif
74 #endif
75
76 #include "getopt.h"
77 #include "libiberty.h"
78 #include "bfd.h"
79 #include "callback.h" /* GDB simulator callback interface */
80 #include "remote-sim.h" /* GDB simulator interface */
81
82 #include "sysdep.h"
83
84 #ifndef PARAMS
85 #define PARAMS(x)
86 #endif
87
88 char* pr_addr PARAMS ((SIM_ADDR addr));
89 char* pr_uword64 PARAMS ((uword64 addr));
90
91
92 /* Get the simulator engine description, without including the code: */
93 #if !(WITH_IGEN)
94 #define SIM_MANIFESTS
95 #include "oengine.c"
96 #undef SIM_MANIFESTS
97 #endif
98
99 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
100 #define CPU cpu
101 #define SD sd
102
103
104 /* The following reserved instruction value is used when a simulator
105 trap is required. NOTE: Care must be taken, since this value may be
106 used in later revisions of the MIPS ISA. */
107
108 #define RSVD_INSTRUCTION (0x00000005)
109 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
110
111 #define RSVD_INSTRUCTION_ARG_SHIFT 6
112 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
113
114
115 /* Bits in the Debug register */
116 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
117 #define Debug_DM 0x40000000 /* Debug Mode */
118 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
119
120 /*---------------------------------------------------------------------------*/
121 /*-- GDB simulator interface ------------------------------------------------*/
122 /*---------------------------------------------------------------------------*/
123
124 static void ColdReset PARAMS((SIM_DESC sd));
125
126 /*---------------------------------------------------------------------------*/
127
128
129
130 #define DELAYSLOT() {\
131 if (STATE & simDELAYSLOT)\
132 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
133 STATE |= simDELAYSLOT;\
134 }
135
136 #define JALDELAYSLOT() {\
137 DELAYSLOT ();\
138 STATE |= simJALDELAYSLOT;\
139 }
140
141 #define NULLIFY() {\
142 STATE &= ~simDELAYSLOT;\
143 STATE |= simSKIPNEXT;\
144 }
145
146 #define CANCELDELAYSLOT() {\
147 DSSTATE = 0;\
148 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
149 }
150
151 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
152 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
153
154 #define K0BASE (0x80000000)
155 #define K0SIZE (0x20000000)
156 #define K1BASE (0xA0000000)
157 #define K1SIZE (0x20000000)
158 #define MONITOR_BASE (0xBFC00000)
159 #define MONITOR_SIZE (1 << 11)
160 #define MEM_SIZE (2 << 20)
161
162 /* start-sanitize-sky */
163 #ifdef TARGET_SKY
164 #undef MEM_SIZE
165 #define MEM_SIZE (16 << 20) /* 16 MB */
166 #undef MONITOR_SIZE
167 #define MONITOR_SIZE 0x100000 /* 1MB */
168 #endif
169 /* end-sanitize-sky */
170
171 #if defined(TRACE)
172 static char *tracefile = "trace.din"; /* default filename for trace log */
173 FILE *tracefh = NULL;
174 static void open_trace PARAMS((SIM_DESC sd));
175 #endif /* TRACE */
176
177 #if WITH_IGEN
178 static const char * get_insn_name (sim_cpu *, int);
179 #endif
180
181 /* simulation target board. NULL=canonical */
182 static char* board = NULL;
183
184
185 static DECLARE_OPTION_HANDLER (mips_option_handler);
186
187 enum {
188 OPTION_DINERO_TRACE = OPTION_START,
189 OPTION_DINERO_FILE,
190 /* start-stanitize-branchbug4011 */
191 OPTION_BRANCH_BUG_4011,
192 /* end-stanitize-branchbug4011 */
193 OPTION_BOARD
194 };
195
196
197 static SIM_RC
198 mips_option_handler (sd, cpu, opt, arg, is_command)
199 SIM_DESC sd;
200 sim_cpu *cpu;
201 int opt;
202 char *arg;
203 int is_command;
204 {
205 int cpu_nr;
206 switch (opt)
207 {
208 /* start-sanitize-branchbug4011 */
209 case OPTION_BRANCH_BUG_4011:
210 {
211 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
212 {
213 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
214 if (arg == NULL)
215 BRANCHBUG4011_OPTION = 1;
216 else if (strcmp (arg, "yes") == 0)
217 BRANCHBUG4011_OPTION = 1;
218 else if (strcmp (arg, "no") == 0)
219 BRANCHBUG4011_OPTION = 0;
220 else if (strcmp (arg, "on") == 0)
221 BRANCHBUG4011_OPTION = 1;
222 else if (strcmp (arg, "off") == 0)
223 BRANCHBUG4011_OPTION = 0;
224 else
225 {
226 fprintf (stderr, "Unrecognized check-4011-branch-bug option `%s'\n", arg);
227 return SIM_RC_FAIL;
228 }
229 }
230 return SIM_RC_OK;
231 }
232
233 /* end-sanitize-branchbug4011 */
234 case OPTION_DINERO_TRACE: /* ??? */
235 #if defined(TRACE)
236 /* Eventually the simTRACE flag could be treated as a toggle, to
237 allow external control of the program points being traced
238 (i.e. only from main onwards, excluding the run-time setup,
239 etc.). */
240 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
241 {
242 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
243 if (arg == NULL)
244 STATE |= simTRACE;
245 else if (strcmp (arg, "yes") == 0)
246 STATE |= simTRACE;
247 else if (strcmp (arg, "no") == 0)
248 STATE &= ~simTRACE;
249 else if (strcmp (arg, "on") == 0)
250 STATE |= simTRACE;
251 else if (strcmp (arg, "off") == 0)
252 STATE &= ~simTRACE;
253 else
254 {
255 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
256 return SIM_RC_FAIL;
257 }
258 }
259 return SIM_RC_OK;
260 #else /* !TRACE */
261 fprintf(stderr,"\
262 Simulator constructed without dinero tracing support (for performance).\n\
263 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
264 return SIM_RC_FAIL;
265 #endif /* !TRACE */
266
267 case OPTION_DINERO_FILE:
268 #if defined(TRACE)
269 if (optarg != NULL) {
270 char *tmp;
271 tmp = (char *)malloc(strlen(optarg) + 1);
272 if (tmp == NULL)
273 {
274 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
275 return SIM_RC_FAIL;
276 }
277 else {
278 strcpy(tmp,optarg);
279 tracefile = tmp;
280 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
281 }
282 }
283 #endif /* TRACE */
284 return SIM_RC_OK;
285
286 case OPTION_BOARD:
287 {
288 if (arg)
289 {
290 board = zalloc(strlen(arg) + 1);
291 strcpy(board, arg);
292 }
293 return SIM_RC_OK;
294 }
295 }
296
297 return SIM_RC_OK;
298 }
299
300
301 static const OPTION mips_options[] =
302 {
303 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
304 '\0', "on|off", "Enable dinero tracing",
305 mips_option_handler },
306 /* start-sanitize-branchbug4011 */
307 { {"check-4011-branch-bug", optional_argument, NULL, OPTION_BRANCH_BUG_4011},
308 '\0', "on|off", "Enable checking for 4011 branch bug",
309 mips_option_handler },
310 /* end-sanitize-branchbug4011 */
311 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
312 '\0', "FILE", "Write dinero trace to FILE",
313 mips_option_handler },
314 { {"board", required_argument, NULL, OPTION_BOARD},
315 '\0', "none" /* rely on compile-time string concatenation for other options */
316
317 /* start-sanitize-tx3904 */
318 #define BOARD_JMR3904 "jmr3904"
319 "|" BOARD_JMR3904
320 #define BOARD_JMR3904_PAL "jmr3904pal"
321 "|" BOARD_JMR3904_PAL
322 #define BOARD_JMR3904_DEBUG "jmr3904debug"
323 "|" BOARD_JMR3904_DEBUG
324 /* end-sanitize-tx3904 */
325
326 , "Customize simulation for a particular board.", mips_option_handler },
327
328 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
329 };
330
331
332 int interrupt_pending;
333
334 void
335 interrupt_event (SIM_DESC sd, void *data)
336 {
337 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
338 address_word cia = CIA_GET (cpu);
339 if (SR & status_IE)
340 {
341 interrupt_pending = 0;
342 SignalExceptionInterrupt (1); /* interrupt "1" */
343 }
344 else if (!interrupt_pending)
345 sim_events_schedule (sd, 1, interrupt_event, data);
346 }
347
348
349 /*---------------------------------------------------------------------------*/
350 /*-- Device registration hook -----------------------------------------------*/
351 /*---------------------------------------------------------------------------*/
352 static void device_init(SIM_DESC sd) {
353 #ifdef DEVICE_INIT
354 extern void register_devices(SIM_DESC);
355 register_devices(sd);
356 #endif
357 }
358
359 /*---------------------------------------------------------------------------*/
360 /*-- GDB simulator interface ------------------------------------------------*/
361 /*---------------------------------------------------------------------------*/
362
363 SIM_DESC
364 sim_open (kind, cb, abfd, argv)
365 SIM_OPEN_KIND kind;
366 host_callback *cb;
367 struct _bfd *abfd;
368 char **argv;
369 {
370 SIM_DESC sd = sim_state_alloc (kind, cb);
371 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
372
373 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
374
375 /* FIXME: watchpoints code shouldn't need this */
376 STATE_WATCHPOINTS (sd)->pc = &(PC);
377 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
378 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
379
380 #if WITH_IGEN
381 /* Initialize the mechanism for doing insn profiling. */
382 CPU_INSN_NAME (cpu) = get_insn_name;
383 CPU_MAX_INSNS (cpu) = nr_itable_entries;
384 #endif
385
386 STATE = 0;
387
388 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
389 return 0;
390 sim_add_option_table (sd, NULL, mips_options);
391
392 /* start-sanitize-sky */
393 #ifdef TARGET_SKY
394 sky_command_options_open (sd);
395 #endif
396 /* end-sanitize-sky */
397
398 /* getopt will print the error message so we just have to exit if this fails.
399 FIXME: Hmmm... in the case of gdb we need getopt to call
400 print_filtered. */
401 if (sim_parse_args (sd, argv) != SIM_RC_OK)
402 {
403 /* Uninstall the modules to avoid memory leaks,
404 file descriptor leaks, etc. */
405 sim_module_uninstall (sd);
406 return 0;
407 }
408
409 /* handle board-specific memory maps */
410 if (board == NULL)
411 {
412 /* Allocate core managed memory */
413
414 /* start-sanitize-sky */
415 #ifndef TARGET_SKY
416 /* end-sanitize-sky */
417 /* the monitor */
418 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
419 /* For compatibility with the old code - under this (at level one)
420 are the kernel spaces K0 & K1. Both of these map to a single
421 smaller sub region */
422 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
423 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
424 K1BASE, K0SIZE,
425 MEM_SIZE, /* actual size */
426 K0BASE);
427 /* start-sanitize-sky */
428 #else
429 /* the monitor */
430 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE - K1BASE, MONITOR_SIZE);
431 sim_do_command (sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
432 /* 16M @ 0x0. Aliases at 0x80000000 and 0xA0000000 are handled by
433 address_translation() */
434 sim_do_commandf (sd, "memory size 0x%lx", MEM_SIZE);
435 #endif
436 /* end-sanitize-sky */
437
438 device_init(sd);
439 }
440
441 /* start-sanitize-tx3904 */
442 #if (WITH_HW)
443 if (board != NULL
444 && (strcmp(board, BOARD_JMR3904) == 0 ||
445 strcmp(board, BOARD_JMR3904_PAL) == 0 ||
446 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
447 {
448 /* match VIRTUAL memory layout of JMR-TX3904 board */
449
450 /* --- environment --- */
451
452 STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
453
454 /* --- memory --- */
455
456 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
457 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
458 0x9FC00000,
459 4 * 1024 * 1024, /* 4 MB */
460 0xBFC00000);
461
462 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
463 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
464 0x80000000,
465 4 * 1024 * 1024, /* 4 MB */
466 0xA0000000);
467
468 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
469 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
470 0x88000000,
471 32 * 1024 * 1024, /* 32 MB */
472 0xA8000000);
473
474 /* Dummy memory regions for unsimulated devices */
475
476 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE010, 0x00c); /* EBIF */
477 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
478 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
479
480 /* --- simulated devices --- */
481 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
482 sim_hw_parse (sd, "/tx3904cpu");
483 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
484 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
485 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
486 sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
487 {
488 /* FIXME: poking at dv-sockser internals, use tcp backend if
489 --sockser_addr option was given.*/
490 extern char* sockser_addr;
491 if(sockser_addr == NULL)
492 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
493 else
494 sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
495 }
496 sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
497 sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
498
499 /* -- device connections --- */
500 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
501 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
502 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
503 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
504 sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
505 sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
506
507 /* add PAL timer & I/O module */
508 if(! strcmp(board, BOARD_JMR3904_PAL))
509 {
510 /* the device */
511 sim_hw_parse (sd, "/pal@0xffff0000");
512 sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
513
514 /* wire up interrupt ports to irc */
515 sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
516 sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
517 sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
518 }
519
520 if(! strcmp(board, BOARD_JMR3904_DEBUG))
521 {
522 /* -- DEBUG: glue interrupt generators --- */
523 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
524 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
525 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
526 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
527 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
528 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
529 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
530 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
531 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
532 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
533 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
534 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
535 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
536 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
537 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
538 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
539 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
540 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
541 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
542 }
543
544 device_init(sd);
545 }
546 #endif
547 /* end-sanitize-tx3904 */
548
549
550 /* check for/establish the a reference program image */
551 if (sim_analyze_program (sd,
552 (STATE_PROG_ARGV (sd) != NULL
553 ? *STATE_PROG_ARGV (sd)
554 : NULL),
555 abfd) != SIM_RC_OK)
556 {
557 sim_module_uninstall (sd);
558 return 0;
559 }
560
561 /* Configure/verify the target byte order and other runtime
562 configuration options */
563 if (sim_config (sd) != SIM_RC_OK)
564 {
565 sim_module_uninstall (sd);
566 return 0;
567 }
568
569 if (sim_post_argv_init (sd) != SIM_RC_OK)
570 {
571 /* Uninstall the modules to avoid memory leaks,
572 file descriptor leaks, etc. */
573 sim_module_uninstall (sd);
574 return 0;
575 }
576
577 /* verify assumptions the simulator made about the host type system.
578 This macro does not return if there is a problem */
579 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
580 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
581
582 /* This is NASTY, in that we are assuming the size of specific
583 registers: */
584 {
585 int rn;
586 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
587 {
588 if (rn < 32)
589 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
590 else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
591 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
592 else if ((rn >= 33) && (rn <= 37))
593 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
594 else if ((rn == SRIDX)
595 || (rn == FCR0IDX)
596 || (rn == FCR31IDX)
597 || ((rn >= 72) && (rn <= 89)))
598 cpu->register_widths[rn] = 32;
599 else
600 cpu->register_widths[rn] = 0;
601 }
602
603 /* start-sanitize-r5900 */
604 /* set the 5900 "upper" registers to 64 bits */
605 for( rn = LAST_EMBED_REGNUM+1; rn < FIRST_COP0_REG; rn++)
606 cpu->register_widths[rn] = 64;
607
608 for( rn = FIRST_COP0_REG; rn < NUM_REGS; rn++)
609 cpu->register_widths[rn] = 32;
610 /* end-sanitize-r5900 */
611
612 /* start-sanitize-sky */
613 #ifdef TARGET_SKY
614 /* Now the VU registers */
615 for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
616 cpu->register_widths[rn + NUM_CORE_REGS] = 16;
617 cpu->register_widths[rn + NUM_CORE_REGS + NUM_VU_REGS] = 16;
618 }
619
620 for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
621 cpu->register_widths[rn + NUM_CORE_REGS] = 32;
622 cpu->register_widths[rn + NUM_CORE_REGS + NUM_VU_REGS] = 32;
623 }
624
625 /* Finally the VIF registers */
626 for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
627 cpu->register_widths[rn + NUM_CORE_REGS] = 32;
628
629 cpu->cur_device = 0;
630 #endif
631 /* end-sanitize-sky */
632 }
633
634 #if defined(TRACE)
635 if (STATE & simTRACE)
636 open_trace(sd);
637 #endif /* TRACE */
638
639 /* Write an abort sequence into the TRAP (common) exception vector
640 addresses. This is to catch code executing a TRAP (et.al.)
641 instruction without installing a trap handler. */
642 {
643 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
644 HALT_INSTRUCTION /* BREAK */ };
645 H2T (halt[0]);
646 H2T (halt[1]);
647 sim_write (sd, 0x80000000, (char *) halt, sizeof (halt));
648 sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
649 sim_write (sd, 0x80000200, (char *) halt, sizeof (halt));
650 sim_write (sd, 0xBFC00200, (char *) halt, sizeof (halt));
651 sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
652 sim_write (sd, 0xBFC00400, (char *) halt, sizeof (halt));
653 }
654
655
656 /* Write the monitor trap address handlers into the monitor (eeprom)
657 address space. This can only be done once the target endianness
658 has been determined. */
659 {
660 unsigned loop;
661 /* Entry into the IDT monitor is via fixed address vectors, and
662 not using machine instructions. To avoid clashing with use of
663 the MIPS TRAP system, we place our own (simulator specific)
664 "undefined" instructions into the relevant vector slots. */
665 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
666 {
667 address_word vaddr = (MONITOR_BASE + loop);
668 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
669 H2T (insn);
670 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
671 }
672 /* The PMON monitor uses the same address space, but rather than
673 branching into it the address of a routine is loaded. We can
674 cheat for the moment, and direct the PMON routine to IDT style
675 instructions within the monitor space. This relies on the IDT
676 monitor not using the locations from 0xBFC00500 onwards as its
677 entry points.*/
678 for (loop = 0; (loop < 24); loop++)
679 {
680 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
681 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
682 switch (loop)
683 {
684 case 0: /* read */
685 value = 7;
686 break;
687 case 1: /* write */
688 value = 8;
689 break;
690 case 2: /* open */
691 value = 6;
692 break;
693 case 3: /* close */
694 value = 10;
695 break;
696 case 5: /* printf */
697 value = ((0x500 - 16) / 8); /* not an IDT reason code */
698 break;
699 case 8: /* cliexit */
700 value = 17;
701 break;
702 case 11: /* flush_cache */
703 value = 28;
704 break;
705 }
706 /* FIXME - should monitor_base be SIM_ADDR?? */
707 value = ((unsigned int)MONITOR_BASE + (value * 8));
708 H2T (value);
709 sim_write (sd, vaddr, (char *)&value, sizeof (value));
710
711 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
712 vaddr -= 0x300;
713 sim_write (sd, vaddr, (char *)&value, sizeof (value));
714 }
715 }
716
717
718 /* start-sanitize-sky */
719 #ifdef TARGET_SKY
720 /* Default TLB initialization... */
721
722 #define KPAGEMASK 0x001fe000
723 #define PAGE_MASK_4K 0x00000000
724 #define PAGE_MASK_16K 0x00006000
725 #define PAGE_MASK_64K 0x0001e000
726 #define PAGE_MASK_256K 0x0007e000
727 #define PAGE_MASK_1M 0x001fe000
728 #define PAGE_MASK_4M 0x007fe000
729 #define PAGE_MASK_16M 0x01ffe000
730
731 #define SET_TLB(index, page_mask, entry_hi, entry_lo0, entry_lo1) \
732 TLB[index].mask = page_mask; \
733 TLB[index].hi = entry_hi; \
734 TLB[index].lo0 = entry_lo0; \
735 TLB[index].lo1 = entry_lo1
736
737 SET_TLB(0, PAGE_MASK_16M, 0x00000000, 0x0000001e, 0x0004001e);/*0-32M*/
738
739 #endif /* TARGET_SKY */
740 /* end-sanitize-sky */
741
742 return sd;
743 }
744
745 #if defined(TRACE)
746 static void
747 open_trace(sd)
748 SIM_DESC sd;
749 {
750 tracefh = fopen(tracefile,"wb+");
751 if (tracefh == NULL)
752 {
753 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
754 tracefh = stderr;
755 }
756 }
757 #endif /* TRACE */
758
759 #if WITH_IGEN
760 /* Return name of an insn, used by insn profiling. */
761 static const char *
762 get_insn_name (sim_cpu *cpu, int i)
763 {
764 return itable[i].name;
765 }
766 #endif
767
768 void
769 sim_close (sd, quitting)
770 SIM_DESC sd;
771 int quitting;
772 {
773 #ifdef DEBUG
774 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
775 #endif
776
777 /* start-sanitize-sky */
778 #ifdef TARGET_SKY
779 sky_command_options_close (sd);
780 #endif
781 /* end-sanitize-sky */
782
783
784 /* "quitting" is non-zero if we cannot hang on errors */
785
786 /* Ensure that any resources allocated through the callback
787 mechanism are released: */
788 sim_io_shutdown (sd);
789
790 #if defined(TRACE)
791 if (tracefh != NULL && tracefh != stderr)
792 fclose(tracefh);
793 tracefh = NULL;
794 #endif /* TRACE */
795
796 /* FIXME - free SD */
797
798 return;
799 }
800
801
802 int
803 sim_write (sd,addr,buffer,size)
804 SIM_DESC sd;
805 SIM_ADDR addr;
806 unsigned char *buffer;
807 int size;
808 {
809 int index;
810 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
811
812 /* Return the number of bytes written, or zero if error. */
813 #ifdef DEBUG
814 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
815 #endif
816
817 /* We use raw read and write routines, since we do not want to count
818 the GDB memory accesses in our statistics gathering. */
819
820 for (index = 0; index < size; index++)
821 {
822 address_word vaddr = (address_word)addr + index;
823 address_word paddr;
824 int cca;
825 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
826 break;
827 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
828 break;
829 }
830
831 return(index);
832 }
833
834 int
835 sim_read (sd,addr,buffer,size)
836 SIM_DESC sd;
837 SIM_ADDR addr;
838 unsigned char *buffer;
839 int size;
840 {
841 int index;
842 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
843
844 /* Return the number of bytes read, or zero if error. */
845 #ifdef DEBUG
846 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
847 #endif /* DEBUG */
848
849 for (index = 0; (index < size); index++)
850 {
851 address_word vaddr = (address_word)addr + index;
852 address_word paddr;
853 int cca;
854 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
855 break;
856 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
857 break;
858 }
859
860 return(index);
861 }
862
863 int
864 sim_store_register (sd,rn,memory,length)
865 SIM_DESC sd;
866 int rn;
867 unsigned char *memory;
868 int length;
869 {
870 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
871 /* NOTE: gdb (the client) stores registers in target byte order
872 while the simulator uses host byte order */
873 #ifdef DEBUG
874 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
875 #endif /* DEBUG */
876
877 /* Unfortunately this suffers from the same problem as the register
878 numbering one. We need to know what the width of each logical
879 register number is for the architecture being simulated. */
880
881 if (cpu->register_widths[rn] == 0)
882 {
883 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
884 return 0;
885 }
886
887 /* start-sanitize-r5900 */
888 if (rn >= 90 && rn < 90 + 32)
889 {
890 GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
891 return 8;
892 }
893 switch (rn)
894 {
895 case REGISTER_SA:
896 SA = T2H_8(*(unsigned64*)memory);
897 return 8;
898 case 122: /* FIXME */
899 LO1 = T2H_8(*(unsigned64*)memory);
900 return 8;
901 case 123: /* FIXME */
902 HI1 = T2H_8(*(unsigned64*)memory);
903 return 8;
904 }
905
906 if (rn >= FIRST_COP0_REG && rn < (FIRST_COP0_REG+NUM_COP0_REGS))
907 {
908 switch (rn - FIRST_COP0_REG)
909 {
910 case 12: /* Status */
911 case 13: /* Cause */
912 return -1; /* Already done in regular register set */
913 case 14:
914 EPC = T2H_4(*((unsigned32*) memory));
915 break;
916 case 16:
917 C0_CONFIG = T2H_4(*((unsigned32*) memory));
918 break;
919 case 17: /* Debug */
920 Debug = T2H_4(*((unsigned32*) memory));
921 break;
922 case 18: /* Perf */
923 COP0_GPR[rn - FIRST_COP0_REG + 7] = T2H_4(*((unsigned32*) memory));
924 break;
925 case 19: /* TagLo */
926 case 20: /* TagHi */
927 case 21: /* ErrorEPC */
928 COP0_GPR[rn - FIRST_COP0_REG + 9] = T2H_4(*((unsigned32*) memory));
929 break;
930 default:
931 COP0_GPR[rn - FIRST_COP0_REG] = T2H_4(*((unsigned32*) memory));
932 break;
933 }
934
935 return 4;
936 }
937 /* end-sanitize-r5900 */
938
939 /* start-sanitize-sky */
940 #ifdef TARGET_SKY
941 if (rn >= NUM_CORE_REGS)
942 {
943 rn = rn - NUM_CORE_REGS;
944
945 if( rn < NUM_VU_REGS )
946 {
947 #ifdef TARGET_SKY_B
948 sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
949 return 0;
950 #else
951 if (rn < NUM_VU_INTEGER_REGS)
952 return write_vu_int_reg (&(vu0_device.regs), rn, memory);
953 else if (rn >= FIRST_VEC_REG)
954 {
955 rn -= FIRST_VEC_REG;
956 return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
957 memory);
958 }
959 else switch (rn - NUM_VU_INTEGER_REGS)
960 {
961 case 0:
962 return write_vu_special_reg (&vu0_device, VU_REG_CIA, memory);
963
964 case 1: /* Can't write TPC register */
965 case 2: /* or VPU_STAT */
966 case 4: /* or MAC */
967 case 9: /* VU0 has no P register */
968 return 4;
969
970 case 3:
971 return write_vu_misc_reg(&(vu0_device.regs), VU_REG_MST, memory);
972 case 5:
973 return write_vu_misc_reg(&(vu0_device.regs), VU_REG_MCP, memory);
974 case 6:
975 return write_vu_special_reg (&vu0_device, VU_REG_CMSAR0, memory);
976 case 7:
977 return write_vu_special_reg (&vu0_device, VU_REG_FBRST, memory);
978 case 8:
979 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR, memory);
980 case 10:
981 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI, memory);
982 case 11:
983 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ, memory);
984 default:
985 return write_vu_acc_reg (&(vu0_device.regs),
986 rn - (NUM_VU_INTEGER_REGS + 12),
987 memory);
988 }
989 #endif /* ! TARGET_SKY_B */
990 }
991
992 rn = rn - NUM_VU_REGS;
993
994 if (rn < NUM_VU_REGS)
995 {
996 if (rn < NUM_VU_INTEGER_REGS)
997 return write_vu_int_reg (&(vu1_device.regs), rn, memory);
998 else if (rn >= FIRST_VEC_REG)
999 {
1000 rn -= FIRST_VEC_REG;
1001 return write_vu_vec_reg (&(vu1_device.regs),
1002 rn >> 2, rn & 3, memory);
1003 }
1004 else switch (rn - NUM_VU_INTEGER_REGS)
1005 {
1006 case 0:
1007 return write_vu_special_reg (&vu1_device, VU_REG_CIA, memory);
1008
1009 case 1: /* Can't write TPC register */
1010 case 2: /* or VPU_STAT */
1011 case 4: /* or MAC */
1012 case 7: /* VU1 has no FBRST register */
1013 return 4;
1014
1015 case 3:
1016 return write_vu_misc_reg(&(vu1_device.regs), VU_REG_MST, memory);
1017 case 5:
1018 return write_vu_misc_reg(&(vu1_device.regs), VU_REG_MCP, memory);
1019 case 6: /* CMSAR1 is actually part of VU0 */
1020 #ifdef TARGET_SKY_B
1021 return 0;
1022 #else
1023 return write_vu_special_reg (&vu0_device, VU_REG_CMSAR1, memory);
1024 #endif /* ! TARGET_SKY_B */
1025 case 8:
1026 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR, memory);
1027 case 9:
1028 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP, memory);
1029 case 10:
1030 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI, memory);
1031 case 11:
1032 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ, memory);
1033 default:
1034 return write_vu_acc_reg (&(vu1_device.regs),
1035 rn - (NUM_VU_INTEGER_REGS + 12),
1036 memory);
1037 }
1038 }
1039
1040 rn -= NUM_VU_REGS; /* VIF0 registers are next */
1041
1042 if (rn < NUM_VIF_REGS)
1043 {
1044 #ifdef TARGET_SKY_B
1045 sim_io_eprintf( sd, "Invalid VIF register (register store ignored)\n" );
1046 return 0;
1047 #else
1048 if (rn < NUM_VIF_REGS-1)
1049 return write_vif_reg (&vif0_device, rn, memory);
1050 else
1051 {
1052 sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
1053 return 0;
1054 }
1055 #endif /* ! TARGET_SKY_B */
1056 }
1057
1058 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
1059
1060 if (rn < NUM_VIF_REGS)
1061 {
1062 if (rn < NUM_VIF_REGS-1)
1063 return write_vif_reg (&vif1_device, rn, memory);
1064 else
1065 {
1066 sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
1067 return 0;
1068 }
1069 }
1070
1071 sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
1072 return 0;
1073 }
1074 #endif
1075 /* end-sanitize-sky */
1076
1077 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
1078 {
1079 if (cpu->register_widths[rn] == 32)
1080 {
1081 cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
1082 return 4;
1083 }
1084 else
1085 {
1086 cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
1087 return 8;
1088 }
1089 }
1090
1091 if (cpu->register_widths[rn] == 32)
1092 {
1093 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
1094 return 4;
1095 }
1096 else
1097 {
1098 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
1099 return 8;
1100 }
1101
1102 return 0;
1103 }
1104
1105 int
1106 sim_fetch_register (sd,rn,memory,length)
1107 SIM_DESC sd;
1108 int rn;
1109 unsigned char *memory;
1110 int length;
1111 {
1112 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
1113 /* NOTE: gdb (the client) stores registers in target byte order
1114 while the simulator uses host byte order */
1115 #ifdef DEBUG
1116 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
1117 #endif /* DEBUG */
1118
1119 if (cpu->register_widths[rn] == 0)
1120 {
1121 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
1122 return 0;
1123 }
1124
1125 /* start-sanitize-r5900 */
1126 if (rn >= 90 && rn < 90 + 32)
1127 {
1128 *((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]);
1129 return 8;
1130 }
1131 switch (rn)
1132 {
1133 case REGISTER_SA:
1134 *((unsigned64*)memory) = H2T_8(SA);
1135 return 8;
1136 case 122: /* FIXME */
1137 *((unsigned64*)memory) = H2T_8(LO1);
1138 return 8;
1139 case 123: /* FIXME */
1140 *((unsigned64*)memory) = H2T_8(HI1);
1141 return 8;
1142 }
1143
1144 if (rn >= FIRST_COP0_REG && rn < (FIRST_COP0_REG+NUM_COP0_REGS))
1145 {
1146 switch (rn - FIRST_COP0_REG)
1147 {
1148 case 12: /* Status */
1149 case 13: /* Cause */
1150 return -1; /* Already done in regular register set */
1151 case 14:
1152 *((unsigned32*) memory) = H2T_4(EPC);
1153 break;
1154 case 16:
1155 *((unsigned32*) memory) = H2T_4(C0_CONFIG);
1156 break;
1157 case 17: /* Debug */
1158 *((unsigned32*) memory) = H2T_4(Debug);
1159 break;
1160 case 18: /* Perf */
1161 *((unsigned32*) memory) = H2T_4(COP0_GPR[rn - FIRST_COP0_REG + 7]);
1162 break;
1163 case 19: /* TagLo */
1164 case 20: /* TagHi */
1165 case 21: /* ErrorEPC */
1166 *((unsigned32*) memory) = H2T_4(COP0_GPR[rn - FIRST_COP0_REG + 9]);
1167 break;
1168 default:
1169 *((unsigned32*) memory) = H2T_4(COP0_GPR[rn - FIRST_COP0_REG]);
1170 break;
1171 }
1172
1173 return 4;
1174 }
1175 /* end-sanitize-r5900 */
1176
1177 /* start-sanitize-sky */
1178 #ifdef TARGET_SKY
1179 if (rn >= NUM_CORE_REGS)
1180 {
1181 rn = rn - NUM_CORE_REGS;
1182
1183 if (rn < NUM_VU_REGS)
1184 {
1185 #ifdef TARGET_SKY_B
1186 sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
1187 return 0;
1188 #else
1189 if (rn < NUM_VU_INTEGER_REGS)
1190 return read_vu_int_reg (&(vu0_device.regs), rn, memory);
1191 else if (rn >= FIRST_VEC_REG)
1192 {
1193 rn -= FIRST_VEC_REG;
1194 return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
1195 memory);
1196 }
1197 else switch (rn - NUM_VU_INTEGER_REGS)
1198 {
1199 case 0:
1200 return read_vu_special_reg (&vu0_device, VU_REG_CIA, memory);
1201 case 1:
1202 return read_vu_misc_reg(&(vu0_device.regs), VU_REG_MTPC, memory);
1203 case 2:
1204 return read_vu_special_reg (&vu0_device, VU_REG_STAT, memory);
1205 case 3:
1206 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MST, memory);
1207 case 4:
1208 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MMC, memory);
1209 case 5:
1210 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MCP, memory);
1211 case 6:
1212 return read_vu_special_reg (&vu0_device, VU_REG_CMSAR0, memory);
1213 case 7:
1214 return read_vu_special_reg (&vu0_device, VU_REG_FBRST, memory);
1215 case 8:
1216 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR, memory);
1217 case 9: /* VU0 has no P register */
1218 *((int *) memory) = 0;
1219 return 4;
1220 case 10:
1221 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI, memory);
1222 case 11:
1223 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ, memory);
1224 default:
1225 return read_vu_acc_reg (&(vu0_device.regs),
1226 rn - (NUM_VU_INTEGER_REGS + 12),
1227 memory);
1228 }
1229 #endif /* ! TARGET_SKY_B */
1230 }
1231
1232 rn -= NUM_VU_REGS; /* VU1 registers are next */
1233
1234 if (rn < NUM_VU_REGS)
1235 {
1236 if (rn < NUM_VU_INTEGER_REGS)
1237 return read_vu_int_reg (&(vu1_device.regs), rn, memory);
1238 else if (rn >= FIRST_VEC_REG)
1239 {
1240 rn -= FIRST_VEC_REG;
1241 return read_vu_vec_reg (&(vu1_device.regs),
1242 rn >> 2, rn & 3, memory);
1243 }
1244 else switch (rn - NUM_VU_INTEGER_REGS)
1245 {
1246 case 0:
1247 return read_vu_special_reg (&vu1_device, VU_REG_CIA, memory);
1248 case 1:
1249 return read_vu_misc_reg(&(vu1_device.regs), VU_REG_MTPC, memory);
1250 case 2:
1251 return read_vu_special_reg (&vu1_device, VU_REG_STAT, memory);
1252 case 3:
1253 return read_vu_misc_reg (&(vu1_device.regs), VU_REG_MST, memory);
1254 case 4:
1255 return read_vu_misc_reg (&(vu1_device.regs), VU_REG_MMC, memory);
1256 case 5:
1257 return read_vu_misc_reg (&(vu1_device.regs), VU_REG_MCP, memory);
1258 case 6: /* CMSAR1 is actually from VU0 */
1259 #ifdef TARGET_SKY_B
1260 return 0;
1261 #else
1262 return read_vu_special_reg (&vu0_device, VU_REG_CMSAR1, memory);
1263 #endif /* ! TARGET_SKY_B */
1264 case 7: /* VU1 has no FBRST register */
1265 *((int *) memory) = 0;
1266 return 4;
1267 case 8:
1268 return read_vu_misc_reg (&(vu1_device.regs), VU_REG_MR, memory);
1269 case 9:
1270 return read_vu_misc_reg (&(vu1_device.regs), VU_REG_MP, memory);
1271 case 10:
1272 return read_vu_misc_reg (&(vu1_device.regs), VU_REG_MI, memory);
1273 case 11:
1274 return read_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ, memory);
1275 default:
1276 return read_vu_acc_reg (&(vu1_device.regs),
1277 rn - (NUM_VU_INTEGER_REGS + 12),
1278 memory);
1279 }
1280 }
1281
1282 rn -= NUM_VU_REGS; /* VIF0 registers are next */
1283
1284 if (rn < NUM_VIF_REGS)
1285 {
1286 #ifdef TARGET_SKY_B
1287 sim_io_eprintf( sd, "Invalid VIF register (register fetch ignored)\n" );
1288 return 0;
1289 #else
1290 if (rn < NUM_VIF_REGS-2)
1291 return read_vif_reg (&vif0_device, rn, memory);
1292 else if (rn == NUM_VIF_REGS-2)
1293 return read_vif_pc (&vif0_device, memory);
1294 else
1295 return read_vif_pcx (&vif0_device, memory);
1296 #endif /* ! TARGET_SKY_B */
1297 }
1298
1299 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
1300
1301 if (rn < NUM_VIF_REGS)
1302 {
1303 if (rn < NUM_VIF_REGS-2)
1304 return read_vif_reg (&vif1_device, rn, memory);
1305 else if (rn == NUM_VIF_REGS-2)
1306 return read_vif_pc (&vif1_device, memory);
1307 else
1308 return read_vif_pcx (&vif1_device, memory);
1309 }
1310
1311 sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
1312 }
1313 #endif
1314 /* end-sanitize-sky */
1315
1316 /* Any floating point register */
1317 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
1318 {
1319 if (cpu->register_widths[rn] == 32)
1320 {
1321 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
1322 return 4;
1323 }
1324 else
1325 {
1326 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
1327 return 8;
1328 }
1329 }
1330
1331 if (cpu->register_widths[rn] == 32)
1332 {
1333 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1334 return 4;
1335 }
1336 else
1337 {
1338 *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
1339 return 8;
1340 }
1341
1342 return 0;
1343 }
1344
1345
1346 SIM_RC
1347 sim_create_inferior (sd, abfd, argv,env)
1348 SIM_DESC sd;
1349 struct _bfd *abfd;
1350 char **argv;
1351 char **env;
1352 {
1353
1354 #ifdef DEBUG
1355 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1356 pr_addr(PC));
1357 #endif /* DEBUG */
1358
1359 ColdReset(sd);
1360
1361 if (abfd != NULL)
1362 {
1363 /* override PC value set by ColdReset () */
1364 int cpu_nr;
1365 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1366 {
1367 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1368 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1369 }
1370 }
1371
1372 #if 0 /* def DEBUG */
1373 if (argv || env)
1374 {
1375 /* We should really place the argv slot values into the argument
1376 registers, and onto the stack as required. However, this
1377 assumes that we have a stack defined, which is not
1378 necessarily true at the moment. */
1379 char **cptr;
1380 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1381 for (cptr = argv; (cptr && *cptr); cptr++)
1382 printf("DBG: arg \"%s\"\n",*cptr);
1383 }
1384 #endif /* DEBUG */
1385
1386 return SIM_RC_OK;
1387 }
1388
1389 void
1390 sim_do_command (sd,cmd)
1391 SIM_DESC sd;
1392 char *cmd;
1393 {
1394 if (sim_args_command (sd, cmd) != SIM_RC_OK)
1395 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1396 cmd);
1397 }
1398
1399 /*---------------------------------------------------------------------------*/
1400 /*-- Private simulator support interface ------------------------------------*/
1401 /*---------------------------------------------------------------------------*/
1402
1403 /* Read a null terminated string from memory, return in a buffer */
1404 static char *
1405 fetch_str (sd, addr)
1406 SIM_DESC sd;
1407 address_word addr;
1408 {
1409 char *buf;
1410 int nr = 0;
1411 char null;
1412 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1413 nr++;
1414 buf = NZALLOC (char, nr + 1);
1415 sim_read (sd, addr, buf, nr);
1416 return buf;
1417 }
1418
1419 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1420 void
1421 sim_monitor (SIM_DESC sd,
1422 sim_cpu *cpu,
1423 address_word cia,
1424 unsigned int reason)
1425 {
1426 #ifdef DEBUG
1427 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1428 #endif /* DEBUG */
1429
1430 /* The IDT monitor actually allows two instructions per vector
1431 slot. However, the simulator currently causes a trap on each
1432 individual instruction. We cheat, and lose the bottom bit. */
1433 reason >>= 1;
1434
1435 /* The following callback functions are available, however the
1436 monitor we are simulating does not make use of them: get_errno,
1437 isatty, lseek, rename, system, time and unlink */
1438 switch (reason)
1439 {
1440
1441 case 6: /* int open(char *path,int flags) */
1442 {
1443 char *path = fetch_str (sd, A0);
1444 V0 = sim_io_open (sd, path, (int)A1);
1445 zfree (path);
1446 break;
1447 }
1448
1449 case 7: /* int read(int file,char *ptr,int len) */
1450 {
1451 int fd = A0;
1452 int nr = A2;
1453 char *buf = zalloc (nr);
1454 V0 = sim_io_read (sd, fd, buf, nr);
1455 sim_write (sd, A1, buf, nr);
1456 zfree (buf);
1457 }
1458 break;
1459
1460 case 8: /* int write(int file,char *ptr,int len) */
1461 {
1462 int fd = A0;
1463 int nr = A2;
1464 char *buf = zalloc (nr);
1465 sim_read (sd, A1, buf, nr);
1466 V0 = sim_io_write (sd, fd, buf, nr);
1467 zfree (buf);
1468 break;
1469 }
1470
1471 case 10: /* int close(int file) */
1472 {
1473 V0 = sim_io_close (sd, (int)A0);
1474 break;
1475 }
1476
1477 case 2: /* Densan monitor: char inbyte(int waitflag) */
1478 {
1479 if (A0 == 0) /* waitflag == NOWAIT */
1480 V0 = (unsigned_word)-1;
1481 }
1482 /* Drop through to case 11 */
1483
1484 case 11: /* char inbyte(void) */
1485 {
1486 char tmp;
1487 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1488 {
1489 sim_io_error(sd,"Invalid return from character read");
1490 V0 = (unsigned_word)-1;
1491 }
1492 else
1493 V0 = (unsigned_word)tmp;
1494 break;
1495 }
1496
1497 case 3: /* Densan monitor: void co(char chr) */
1498 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1499 {
1500 char tmp = (char)(A0 & 0xFF);
1501 sim_io_write_stdout (sd, &tmp, sizeof(char));
1502 break;
1503 }
1504
1505 case 17: /* void _exit() */
1506 {
1507 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1508 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1509 (unsigned int)(A0 & 0xFFFFFFFF));
1510 break;
1511 }
1512
1513 case 28 : /* PMON flush_cache */
1514 break;
1515
1516 case 55: /* void get_mem_info(unsigned int *ptr) */
1517 /* in: A0 = pointer to three word memory location */
1518 /* out: [A0 + 0] = size */
1519 /* [A0 + 4] = instruction cache size */
1520 /* [A0 + 8] = data cache size */
1521 {
1522 unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
1523 unsigned_4 zero = 0;
1524 H2T (value);
1525 sim_write (sd, A0 + 0, (char *)&value, 4);
1526 sim_write (sd, A0 + 4, (char *)&zero, 4);
1527 sim_write (sd, A0 + 8, (char *)&zero, 4);
1528 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1529 break;
1530 }
1531
1532 case 158 : /* PMON printf */
1533 /* in: A0 = pointer to format string */
1534 /* A1 = optional argument 1 */
1535 /* A2 = optional argument 2 */
1536 /* A3 = optional argument 3 */
1537 /* out: void */
1538 /* The following is based on the PMON printf source */
1539 {
1540 address_word s = A0;
1541 char c;
1542 signed_word *ap = &A1; /* 1st argument */
1543 /* This isn't the quickest way, since we call the host print
1544 routine for every character almost. But it does avoid
1545 having to allocate and manage a temporary string buffer. */
1546 /* TODO: Include check that we only use three arguments (A1,
1547 A2 and A3) */
1548 while (sim_read (sd, s++, &c, 1) && c != '\0')
1549 {
1550 if (c == '%')
1551 {
1552 char tmp[40];
1553 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1554 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1555 while (sim_read (sd, s++, &c, 1) && c != '\0')
1556 {
1557 if (strchr ("dobxXulscefg%", c))
1558 break;
1559 else if (c == '-')
1560 fmt = FMT_LJUST;
1561 else if (c == '0')
1562 fmt = FMT_RJUST0;
1563 else if (c == '~')
1564 fmt = FMT_CENTER;
1565 else if (c == '*')
1566 {
1567 if (haddot)
1568 trunc = (int)*ap++;
1569 else
1570 width = (int)*ap++;
1571 }
1572 else if (c >= '1' && c <= '9')
1573 {
1574 address_word t = s;
1575 unsigned int n;
1576 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1577 tmp[s - t] = c;
1578 tmp[s - t] = '\0';
1579 n = (unsigned int)strtol(tmp,NULL,10);
1580 if (haddot)
1581 trunc = n;
1582 else
1583 width = n;
1584 s--;
1585 }
1586 else if (c == '.')
1587 haddot = 1;
1588 }
1589 switch (c)
1590 {
1591 case '%':
1592 sim_io_printf (sd, "%%");
1593 break;
1594 case 's':
1595 if ((int)*ap != 0)
1596 {
1597 address_word p = *ap++;
1598 char ch;
1599 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1600 sim_io_printf(sd, "%c", ch);
1601 }
1602 else
1603 sim_io_printf(sd,"(null)");
1604 break;
1605 case 'c':
1606 sim_io_printf (sd, "%c", (int)*ap++);
1607 break;
1608 default:
1609 if (c == 'l')
1610 {
1611 sim_read (sd, s++, &c, 1);
1612 if (c == 'l')
1613 {
1614 longlong = 1;
1615 sim_read (sd, s++, &c, 1);
1616 }
1617 }
1618 if (strchr ("dobxXu", c))
1619 {
1620 word64 lv = (word64) *ap++;
1621 if (c == 'b')
1622 sim_io_printf(sd,"<binary not supported>");
1623 else
1624 {
1625 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1626 if (longlong)
1627 sim_io_printf(sd, tmp, lv);
1628 else
1629 sim_io_printf(sd, tmp, (int)lv);
1630 }
1631 }
1632 else if (strchr ("eEfgG", c))
1633 {
1634 double dbl = *(double*)(ap++);
1635 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1636 sim_io_printf (sd, tmp, dbl);
1637 trunc = 0;
1638 }
1639 }
1640 }
1641 else
1642 sim_io_printf(sd, "%c", c);
1643 }
1644 break;
1645 }
1646
1647 default:
1648 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1649 reason, pr_addr(cia));
1650 break;
1651 }
1652 return;
1653 }
1654
1655 /* Store a word into memory. */
1656
1657 static void
1658 store_word (SIM_DESC sd,
1659 sim_cpu *cpu,
1660 address_word cia,
1661 uword64 vaddr,
1662 signed_word val)
1663 {
1664 address_word paddr;
1665 int uncached;
1666
1667 if ((vaddr & 3) != 0)
1668 SignalExceptionAddressStore ();
1669 else
1670 {
1671 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1672 isTARGET, isREAL))
1673 {
1674 const uword64 mask = 7;
1675 uword64 memval;
1676 unsigned int byte;
1677
1678 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1679 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1680 memval = ((uword64) val) << (8 * byte);
1681 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1682 isREAL);
1683 }
1684 }
1685 }
1686
1687 /* Load a word from memory. */
1688
1689 static signed_word
1690 load_word (SIM_DESC sd,
1691 sim_cpu *cpu,
1692 address_word cia,
1693 uword64 vaddr)
1694 {
1695 if ((vaddr & 3) != 0)
1696 SignalExceptionAddressLoad ();
1697 else
1698 {
1699 address_word paddr;
1700 int uncached;
1701
1702 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1703 isTARGET, isREAL))
1704 {
1705 const uword64 mask = 0x7;
1706 const unsigned int reverse = ReverseEndian ? 1 : 0;
1707 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1708 uword64 memval;
1709 unsigned int byte;
1710
1711 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1712 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1713 isDATA, isREAL);
1714 byte = (vaddr & mask) ^ (bigend << 2);
1715 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1716 }
1717 }
1718
1719 return 0;
1720 }
1721
1722 /* Simulate the mips16 entry and exit pseudo-instructions. These
1723 would normally be handled by the reserved instruction exception
1724 code, but for ease of simulation we just handle them directly. */
1725
1726 static void
1727 mips16_entry (SIM_DESC sd,
1728 sim_cpu *cpu,
1729 address_word cia,
1730 unsigned int insn)
1731 {
1732 int aregs, sregs, rreg;
1733
1734 #ifdef DEBUG
1735 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1736 #endif /* DEBUG */
1737
1738 aregs = (insn & 0x700) >> 8;
1739 sregs = (insn & 0x0c0) >> 6;
1740 rreg = (insn & 0x020) >> 5;
1741
1742 /* This should be checked by the caller. */
1743 if (sregs == 3)
1744 abort ();
1745
1746 if (aregs < 5)
1747 {
1748 int i;
1749 signed_word tsp;
1750
1751 /* This is the entry pseudo-instruction. */
1752
1753 for (i = 0; i < aregs; i++)
1754 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1755
1756 tsp = SP;
1757 SP -= 32;
1758
1759 if (rreg)
1760 {
1761 tsp -= 4;
1762 store_word (SD, CPU, cia, (uword64) tsp, RA);
1763 }
1764
1765 for (i = 0; i < sregs; i++)
1766 {
1767 tsp -= 4;
1768 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1769 }
1770 }
1771 else
1772 {
1773 int i;
1774 signed_word tsp;
1775
1776 /* This is the exit pseudo-instruction. */
1777
1778 tsp = SP + 32;
1779
1780 if (rreg)
1781 {
1782 tsp -= 4;
1783 RA = load_word (SD, CPU, cia, (uword64) tsp);
1784 }
1785
1786 for (i = 0; i < sregs; i++)
1787 {
1788 tsp -= 4;
1789 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1790 }
1791
1792 SP += 32;
1793
1794 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1795 {
1796 if (aregs == 5)
1797 {
1798 FGR[0] = WORD64LO (GPR[4]);
1799 FPR_STATE[0] = fmt_uninterpreted;
1800 }
1801 else if (aregs == 6)
1802 {
1803 FGR[0] = WORD64LO (GPR[5]);
1804 FGR[1] = WORD64LO (GPR[4]);
1805 FPR_STATE[0] = fmt_uninterpreted;
1806 FPR_STATE[1] = fmt_uninterpreted;
1807 }
1808 }
1809
1810 PC = RA;
1811 }
1812
1813 }
1814
1815 /*-- trace support ----------------------------------------------------------*/
1816
1817 /* The TRACE support is provided (if required) in the memory accessing
1818 routines. Since we are also providing the architecture specific
1819 features, the architecture simulation code can also deal with
1820 notifying the TRACE world of cache flushes, etc. Similarly we do
1821 not need to provide profiling support in the simulator engine,
1822 since we can sample in the instruction fetch control loop. By
1823 defining the TRACE manifest, we add tracing as a run-time
1824 option. */
1825
1826 #if defined(TRACE)
1827 /* Tracing by default produces "din" format (as required by
1828 dineroIII). Each line of such a trace file *MUST* have a din label
1829 and address field. The rest of the line is ignored, so comments can
1830 be included if desired. The first field is the label which must be
1831 one of the following values:
1832
1833 0 read data
1834 1 write data
1835 2 instruction fetch
1836 3 escape record (treated as unknown access type)
1837 4 escape record (causes cache flush)
1838
1839 The address field is a 32bit (lower-case) hexadecimal address
1840 value. The address should *NOT* be preceded by "0x".
1841
1842 The size of the memory transfer is not important when dealing with
1843 cache lines (as long as no more than a cache line can be
1844 transferred in a single operation :-), however more information
1845 could be given following the dineroIII requirement to allow more
1846 complete memory and cache simulators to provide better
1847 results. i.e. the University of Pisa has a cache simulator that can
1848 also take bus size and speed as (variable) inputs to calculate
1849 complete system performance (a much more useful ability when trying
1850 to construct an end product, rather than a processor). They
1851 currently have an ARM version of their tool called ChARM. */
1852
1853
1854 void
1855 dotrace (SIM_DESC sd,
1856 sim_cpu *cpu,
1857 FILE *tracefh,
1858 int type,
1859 SIM_ADDR address,
1860 int width,
1861 char *comment,...)
1862 {
1863 if (STATE & simTRACE) {
1864 va_list ap;
1865 fprintf(tracefh,"%d %s ; width %d ; ",
1866 type,
1867 pr_addr(address),
1868 width);
1869 va_start(ap,comment);
1870 vfprintf(tracefh,comment,ap);
1871 va_end(ap);
1872 fprintf(tracefh,"\n");
1873 }
1874 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1875 we may be generating 64bit ones, we should put the hi-32bits of the
1876 address into the comment field. */
1877
1878 /* TODO: Provide a buffer for the trace lines. We can then avoid
1879 performing writes until the buffer is filled, or the file is
1880 being closed. */
1881
1882 /* NOTE: We could consider adding a comment field to the "din" file
1883 produced using type 3 markers (unknown access). This would then
1884 allow information about the program that the "din" is for, and
1885 the MIPs world that was being simulated, to be placed into the
1886 trace file. */
1887
1888 return;
1889 }
1890 #endif /* TRACE */
1891
1892 /*---------------------------------------------------------------------------*/
1893 /*-- simulator engine -------------------------------------------------------*/
1894 /*---------------------------------------------------------------------------*/
1895
1896 static void
1897 ColdReset (SIM_DESC sd)
1898 {
1899 int cpu_nr;
1900 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1901 {
1902 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1903 /* RESET: Fixed PC address: */
1904 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1905 /* The reset vector address is in the unmapped, uncached memory space. */
1906
1907 SR &= ~(status_SR | status_TS | status_RP);
1908 SR |= (status_ERL | status_BEV);
1909
1910 /* Cheat and allow access to the complete register set immediately */
1911 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1912 && WITH_TARGET_WORD_BITSIZE == 64)
1913 SR |= status_FR; /* 64bit registers */
1914
1915 /* Ensure that any instructions with pending register updates are
1916 cleared: */
1917 PENDING_INVALIDATE();
1918
1919 /* Initialise the FPU registers to the unknown state */
1920 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1921 {
1922 int rn;
1923 for (rn = 0; (rn < 32); rn++)
1924 FPR_STATE[rn] = fmt_uninterpreted;
1925 }
1926
1927 }
1928 }
1929
1930
1931
1932 /* start-sanitize-sky */
1933 #ifdef TARGET_SKY
1934
1935 /* See ch. 5 of the 5900 Users' Guide. */
1936 void
1937 signal_exception (SIM_DESC sd,
1938 sim_cpu *cpu,
1939 address_word cia,
1940 int cause, ...)
1941 {
1942 /* int vector; */
1943
1944 #ifdef DEBUG
1945 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",cause,pr_addr(cia));
1946 #endif /* DEBUG */
1947
1948 /* Ensure that any active atomic read/modify/write operation will fail: */
1949 LLBIT = 0;
1950
1951 /* First, handle any simulator specific magic exceptions. These are not "real" exceptions, but
1952 are exceptions which the simulator uses to implement different features. */
1953
1954 switch (cause) {
1955
1956 case SimulatorFault:
1957 {
1958 va_list ap;
1959 char *msg;
1960 va_start(ap,cause);
1961 msg = va_arg(ap,char *);
1962 va_end(ap);
1963 sim_engine_abort (SD, CPU, NULL_CIA,
1964 "FATAL: Simulator error \"%s\"\n",msg);
1965 }
1966
1967 case DebugBreakPoint :
1968 if (! (Debug & Debug_DM))
1969 {
1970 if (INDELAYSLOT())
1971 {
1972 CANCELDELAYSLOT();
1973
1974 Debug |= Debug_DBD; /* signaled from within in delay slot */
1975 DEPC = cia - 4; /* reference the branch instruction */
1976 }
1977 else
1978 {
1979 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1980 DEPC = cia;
1981 }
1982
1983 Debug |= Debug_DM; /* in debugging mode */
1984 Debug |= Debug_DBp; /* raising a DBp exception */
1985 PC = 0xBFC00200;
1986 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1987 }
1988 break;
1989
1990 case ReservedInstruction :
1991 {
1992 va_list ap;
1993 unsigned int instruction;
1994 va_start(ap,cause);
1995 instruction = va_arg(ap,unsigned int);
1996 va_end(ap);
1997 /* Provide simple monitor support using ReservedInstruction
1998 exceptions. The following code simulates the fixed vector
1999 entry points into the IDT monitor by causing a simulator
2000 trap, performing the monitor operation, and returning to
2001 the address held in the $ra register (standard PCS return
2002 address). This means we only need to pre-load the vector
2003 space with suitable instruction values. For systems were
2004 actual trap instructions are used, we would not need to
2005 perform this magic. */
2006 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
2007 {
2008 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
2009 /* NOTE: This assumes that a branch-and-link style
2010 instruction was used to enter the vector (which is the
2011 case with the current IDT monitor). */
2012 sim_engine_restart (SD, CPU, NULL, RA);
2013 }
2014 /* Look for the mips16 entry and exit instructions, and
2015 simulate a handler for them. */
2016 else if ((cia & 1) != 0
2017 && (instruction & 0xf81f) == 0xe809
2018 && (instruction & 0x0c0) != 0x0c0)
2019 {
2020 mips16_entry (SD, CPU, cia, instruction);
2021 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
2022 }
2023 /* else fall through to normal exception processing */
2024 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
2025 }
2026 }
2027
2028 /* Now we have the code for processing "real" exceptions. */
2029
2030 if (is5900Level2Exception(cause)) {
2031 switch(cause) {
2032 case NMIReset:
2033 cause_set_EXC2(1);
2034 break;
2035 default:
2036 sim_engine_abort (SD, CPU, NULL_CIA,
2037 "FATAL: Unexpected level 2 exception %d\n", cause);
2038 }
2039 if (STATE & simDELAYSLOT)
2040 {
2041 STATE &= ~simDELAYSLOT;
2042 COP0_ERROREPC = (cia - 4); /* reference the branch instruction */
2043 CAUSE |= cause_BD2;
2044 }
2045 else
2046 {
2047 COP0_ERROREPC = cia;
2048 CAUSE &= ~cause_BD2;
2049 }
2050
2051 SR |= status_ERL;
2052
2053 if (cause == NMIReset)
2054 PC = 0xBFC0000;
2055 else
2056 {
2057 ASSERT(0); /* At the moment, COUNTER, DEBUG never generated. */
2058 }
2059 sim_engine_restart (SD, CPU, NULL, PC);
2060 } else {
2061 /* A level 1 exception. */
2062 int refill, vector_offset;
2063
2064 cause_set_EXC(cause);
2065 if (SR & status_EXL)
2066 vector_offset = 0x180;
2067 else
2068 {
2069 if (cause == TLBLoad || cause == TLBStore) {
2070 va_list ap;
2071 va_start(ap, cause);
2072 refill = va_arg(ap,int);
2073 va_end(ap);
2074 }
2075
2076 if (STATE & simDELAYSLOT)
2077 {
2078 STATE &= ~simDELAYSLOT;
2079 CAUSE |= cause_BD;
2080 COP0_EPC = (cia - 4); /* reference the branch instruction */
2081 }
2082 else
2083 {
2084 COP0_EPC = cia;
2085 CAUSE &= ~cause_BD;
2086 }
2087
2088 SR |= status_EXL;
2089
2090 if ((cause == TLBLoad || cause == TLBStore) && refill == TLB_REFILL)
2091 vector_offset = 0x000;
2092 else if (cause == Interrupt)
2093 vector_offset = 0x200;
2094 else
2095 vector_offset = 0x180;
2096
2097 if (SR & status_BEV)
2098 PC = (signed)0xBFC00200 + vector_offset;
2099 else
2100 PC = (signed)0x80000000 + vector_offset;
2101 }
2102
2103 /* Now, handle the exception. */
2104 switch (cause)
2105 {
2106 case Interrupt:
2107 {
2108 va_list ap;
2109 unsigned int level;
2110 va_start(ap, cause);
2111 level = va_arg(ap,unsigned int);
2112 va_end(ap);
2113 /* Interrupts arrive during event processing, no need to restart.
2114 Hardware interrupts on sky target are INT1 and INT2. */
2115 if ( level == 1 )
2116 CAUSE |= cause_IP3; /* bit 11 */
2117 else if ( level == 2 )
2118 CAUSE |= cause_IP7; /* bit 15 */
2119 else
2120 sim_engine_abort (SD, CPU, NULL_CIA,
2121 "FATAL: Unexpected interrupt level %d\n", level);
2122 return;
2123 }
2124
2125 case NMIReset:
2126 ASSERT(0); /* NMIReset is a level 0 exception. */
2127 return;
2128
2129 case AddressLoad:
2130 case AddressStore:
2131 case InstructionFetch:
2132 case DataReference:
2133 /* The following is so that the simulator will continue from the
2134 exception address on breakpoint operations. */
2135 PC = COP0_EPC;
2136 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2137 sim_stopped, SIM_SIGBUS);
2138 break;
2139
2140 case ReservedInstruction:
2141 case CoProcessorUnusable:
2142 PC = COP0_EPC;
2143 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2144 sim_stopped, SIM_SIGILL);
2145 break;
2146
2147 case IntegerOverflow:
2148 case FPE:
2149 PC = COP0_EPC;
2150 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2151 sim_stopped, SIM_SIGFPE);
2152 break;
2153
2154 case TLBModification:
2155 case TLBLoad:
2156 case TLBStore:
2157 case BreakPoint:
2158 case SystemCall:
2159 case Trap:
2160 sim_engine_restart (SD, CPU, NULL, PC);
2161 break;
2162
2163 case Watch:
2164 PC = COP0_EPC;
2165 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2166 sim_stopped, SIM_SIGTRAP);
2167 break;
2168
2169 default : /* Unknown internal exception */
2170 PC = COP0_EPC;
2171 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2172 sim_stopped, SIM_SIGABRT);
2173 break;
2174
2175 }
2176 }
2177 return;
2178 }
2179
2180 #else /* TARGET_SKY */
2181 /* end-sanitize-sky */
2182
2183 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2184 /* Signal an exception condition. This will result in an exception
2185 that aborts the instruction. The instruction operation pseudocode
2186 will never see a return from this function call. */
2187
2188 void
2189 signal_exception (SIM_DESC sd,
2190 sim_cpu *cpu,
2191 address_word cia,
2192 int exception,...)
2193 {
2194 /* int vector; */
2195
2196 #ifdef DEBUG
2197 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
2198 #endif /* DEBUG */
2199
2200 /* Ensure that any active atomic read/modify/write operation will fail: */
2201 LLBIT = 0;
2202
2203 switch (exception) {
2204
2205 case DebugBreakPoint :
2206 if (! (Debug & Debug_DM))
2207 {
2208 if (INDELAYSLOT())
2209 {
2210 CANCELDELAYSLOT();
2211
2212 Debug |= Debug_DBD; /* signaled from within in delay slot */
2213 DEPC = cia - 4; /* reference the branch instruction */
2214 }
2215 else
2216 {
2217 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
2218 DEPC = cia;
2219 }
2220
2221 Debug |= Debug_DM; /* in debugging mode */
2222 Debug |= Debug_DBp; /* raising a DBp exception */
2223 PC = 0xBFC00200;
2224 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
2225 }
2226 break;
2227
2228 case ReservedInstruction :
2229 {
2230 va_list ap;
2231 unsigned int instruction;
2232 va_start(ap,exception);
2233 instruction = va_arg(ap,unsigned int);
2234 va_end(ap);
2235 /* Provide simple monitor support using ReservedInstruction
2236 exceptions. The following code simulates the fixed vector
2237 entry points into the IDT monitor by causing a simulator
2238 trap, performing the monitor operation, and returning to
2239 the address held in the $ra register (standard PCS return
2240 address). This means we only need to pre-load the vector
2241 space with suitable instruction values. For systems were
2242 actual trap instructions are used, we would not need to
2243 perform this magic. */
2244 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
2245 {
2246 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
2247 /* NOTE: This assumes that a branch-and-link style
2248 instruction was used to enter the vector (which is the
2249 case with the current IDT monitor). */
2250 sim_engine_restart (SD, CPU, NULL, RA);
2251 }
2252 /* Look for the mips16 entry and exit instructions, and
2253 simulate a handler for them. */
2254 else if ((cia & 1) != 0
2255 && (instruction & 0xf81f) == 0xe809
2256 && (instruction & 0x0c0) != 0x0c0)
2257 {
2258 mips16_entry (SD, CPU, cia, instruction);
2259 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
2260 }
2261 /* else fall through to normal exception processing */
2262 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
2263 }
2264
2265 default:
2266 /* Store exception code into current exception id variable (used
2267 by exit code): */
2268
2269 /* TODO: If not simulating exceptions then stop the simulator
2270 execution. At the moment we always stop the simulation. */
2271
2272 #ifdef SUBTARGET_R3900
2273 /* update interrupt-related registers */
2274
2275 /* insert exception code in bits 6:2 */
2276 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
2277 /* shift IE/KU history bits left */
2278 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
2279
2280 if (STATE & simDELAYSLOT)
2281 {
2282 STATE &= ~simDELAYSLOT;
2283 CAUSE |= cause_BD;
2284 EPC = (cia - 4); /* reference the branch instruction */
2285 }
2286 else
2287 EPC = cia;
2288
2289 if (SR & status_BEV)
2290 PC = (signed)0xBFC00000 + 0x180;
2291 else
2292 PC = (signed)0x80000000 + 0x080;
2293 #else
2294 /* See figure 5-17 for an outline of the code below */
2295 if (! (SR & status_EXL))
2296 {
2297 CAUSE = (exception << 2);
2298 if (STATE & simDELAYSLOT)
2299 {
2300 STATE &= ~simDELAYSLOT;
2301 CAUSE |= cause_BD;
2302 EPC = (cia - 4); /* reference the branch instruction */
2303 }
2304 else
2305 EPC = cia;
2306 /* FIXME: TLB et.al. */
2307 /* vector = 0x180; */
2308 }
2309 else
2310 {
2311 CAUSE = (exception << 2);
2312 /* vector = 0x180; */
2313 }
2314 SR |= status_EXL;
2315 /* Store exception code into current exception id variable (used
2316 by exit code): */
2317
2318 if (SR & status_BEV)
2319 PC = (signed)0xBFC00200 + 0x180;
2320 else
2321 PC = (signed)0x80000000 + 0x180;
2322 #endif
2323
2324 switch ((CAUSE >> 2) & 0x1F)
2325 {
2326 case Interrupt:
2327 /* Interrupts arrive during event processing, no need to
2328 restart */
2329 return;
2330
2331 case NMIReset:
2332 /* Ditto */
2333 #ifdef SUBTARGET_3900
2334 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
2335 PC = (signed)0xBFC00000;
2336 #endif SUBTARGET_3900
2337 return;
2338
2339 case TLBModification:
2340 case TLBLoad:
2341 case TLBStore:
2342 case AddressLoad:
2343 case AddressStore:
2344 case InstructionFetch:
2345 case DataReference:
2346 /* The following is so that the simulator will continue from the
2347 exception address on breakpoint operations. */
2348 PC = EPC;
2349 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2350 sim_stopped, SIM_SIGBUS);
2351
2352 case ReservedInstruction:
2353 case CoProcessorUnusable:
2354 PC = EPC;
2355 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2356 sim_stopped, SIM_SIGILL);
2357
2358 case IntegerOverflow:
2359 case FPE:
2360 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2361 sim_stopped, SIM_SIGFPE);
2362
2363 case BreakPoint:
2364 case SystemCall:
2365 case Trap:
2366 sim_engine_restart (SD, CPU, NULL, PC);
2367 break;
2368
2369 case Watch:
2370 PC = EPC;
2371 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2372 sim_stopped, SIM_SIGTRAP);
2373
2374 default : /* Unknown internal exception */
2375 PC = EPC;
2376 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2377 sim_stopped, SIM_SIGABRT);
2378
2379 }
2380
2381 case SimulatorFault:
2382 {
2383 va_list ap;
2384 char *msg;
2385 va_start(ap,exception);
2386 msg = va_arg(ap,char *);
2387 va_end(ap);
2388 sim_engine_abort (SD, CPU, NULL_CIA,
2389 "FATAL: Simulator error \"%s\"\n",msg);
2390 }
2391 }
2392
2393 return;
2394 }
2395
2396 /* start-sanitize-sky */
2397 #endif /* ! TARGET_SKY */
2398 /* end-sanitize-sky */
2399
2400
2401 #if defined(WARN_RESULT)
2402 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2403 /* This function indicates that the result of the operation is
2404 undefined. However, this should not affect the instruction
2405 stream. All that is meant to happen is that the destination
2406 register is set to an undefined result. To keep the simulator
2407 simple, we just don't bother updating the destination register, so
2408 the overall result will be undefined. If desired we can stop the
2409 simulator by raising a pseudo-exception. */
2410 #define UndefinedResult() undefined_result (sd,cia)
2411 static void
2412 undefined_result(sd,cia)
2413 SIM_DESC sd;
2414 address_word cia;
2415 {
2416 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
2417 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2418 state |= simSTOP;
2419 #endif
2420 return;
2421 }
2422 #endif /* WARN_RESULT */
2423
2424 /*-- FPU support routines ---------------------------------------------------*/
2425
2426 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2427 formats conform to ANSI/IEEE Std 754-1985. */
2428 /* SINGLE precision floating:
2429 * seeeeeeeefffffffffffffffffffffff
2430 * s = 1bit = sign
2431 * e = 8bits = exponent
2432 * f = 23bits = fraction
2433 */
2434 /* SINGLE precision fixed:
2435 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2436 * s = 1bit = sign
2437 * i = 31bits = integer
2438 */
2439 /* DOUBLE precision floating:
2440 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2441 * s = 1bit = sign
2442 * e = 11bits = exponent
2443 * f = 52bits = fraction
2444 */
2445 /* DOUBLE precision fixed:
2446 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2447 * s = 1bit = sign
2448 * i = 63bits = integer
2449 */
2450
2451 /* Extract sign-bit: */
2452 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2453 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2454 /* Extract biased exponent: */
2455 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2456 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2457 /* Extract unbiased Exponent: */
2458 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2459 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2460 /* Extract complete fraction field: */
2461 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2462 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2463 /* Extract numbered fraction bit: */
2464 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2465 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2466
2467 /* Explicit QNaN values used when value required: */
2468 #define FPQNaN_SINGLE (0x7FBFFFFF)
2469 #define FPQNaN_WORD (0x7FFFFFFF)
2470 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2471 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2472
2473 /* Explicit Infinity values used when required: */
2474 #define FPINF_SINGLE (0x7F800000)
2475 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2476
2477 #if 1 /* def DEBUG */
2478 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2479 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2480 #endif /* DEBUG */
2481
2482 uword64
2483 value_fpr (SIM_DESC sd,
2484 sim_cpu *cpu,
2485 address_word cia,
2486 int fpr,
2487 FP_formats fmt)
2488 {
2489 uword64 value = 0;
2490 int err = 0;
2491
2492 /* Treat unused register values, as fixed-point 64bit values: */
2493 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
2494 #if 1
2495 /* If request to read data as "uninterpreted", then use the current
2496 encoding: */
2497 fmt = FPR_STATE[fpr];
2498 #else
2499 fmt = fmt_long;
2500 #endif
2501
2502 /* For values not yet accessed, set to the desired format: */
2503 if (FPR_STATE[fpr] == fmt_uninterpreted) {
2504 FPR_STATE[fpr] = fmt;
2505 #ifdef DEBUG
2506 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
2507 #endif /* DEBUG */
2508 }
2509 if (fmt != FPR_STATE[fpr]) {
2510 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
2511 FPR_STATE[fpr] = fmt_unknown;
2512 }
2513
2514 if (FPR_STATE[fpr] == fmt_unknown) {
2515 /* Set QNaN value: */
2516 switch (fmt) {
2517 case fmt_single:
2518 value = FPQNaN_SINGLE;
2519 break;
2520
2521 case fmt_double:
2522 value = FPQNaN_DOUBLE;
2523 break;
2524
2525 case fmt_word:
2526 value = FPQNaN_WORD;
2527 break;
2528
2529 case fmt_long:
2530 value = FPQNaN_LONG;
2531 break;
2532
2533 default:
2534 err = -1;
2535 break;
2536 }
2537 } else if (SizeFGR() == 64) {
2538 switch (fmt) {
2539 case fmt_single:
2540 case fmt_word:
2541 value = (FGR[fpr] & 0xFFFFFFFF);
2542 break;
2543
2544 case fmt_uninterpreted:
2545 case fmt_double:
2546 case fmt_long:
2547 value = FGR[fpr];
2548 break;
2549
2550 default :
2551 err = -1;
2552 break;
2553 }
2554 } else {
2555 switch (fmt) {
2556 case fmt_single:
2557 case fmt_word:
2558 value = (FGR[fpr] & 0xFFFFFFFF);
2559 break;
2560
2561 case fmt_uninterpreted:
2562 case fmt_double:
2563 case fmt_long:
2564 if ((fpr & 1) == 0) { /* even registers only */
2565 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2566 } else {
2567 SignalException(ReservedInstruction,0);
2568 }
2569 break;
2570
2571 default :
2572 err = -1;
2573 break;
2574 }
2575 }
2576
2577 if (err)
2578 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2579
2580 #ifdef DEBUG
2581 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2582 #endif /* DEBUG */
2583
2584 return(value);
2585 }
2586
2587 void
2588 store_fpr (SIM_DESC sd,
2589 sim_cpu *cpu,
2590 address_word cia,
2591 int fpr,
2592 FP_formats fmt,
2593 uword64 value)
2594 {
2595 int err = 0;
2596
2597 #ifdef DEBUG
2598 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2599 #endif /* DEBUG */
2600
2601 if (SizeFGR() == 64) {
2602 switch (fmt) {
2603 case fmt_uninterpreted_32:
2604 fmt = fmt_uninterpreted;
2605 case fmt_single :
2606 case fmt_word :
2607 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2608 FPR_STATE[fpr] = fmt;
2609 break;
2610
2611 case fmt_uninterpreted_64:
2612 fmt = fmt_uninterpreted;
2613 case fmt_uninterpreted:
2614 case fmt_double :
2615 case fmt_long :
2616 FGR[fpr] = value;
2617 FPR_STATE[fpr] = fmt;
2618 break;
2619
2620 default :
2621 FPR_STATE[fpr] = fmt_unknown;
2622 err = -1;
2623 break;
2624 }
2625 } else {
2626 switch (fmt) {
2627 case fmt_uninterpreted_32:
2628 fmt = fmt_uninterpreted;
2629 case fmt_single :
2630 case fmt_word :
2631 FGR[fpr] = (value & 0xFFFFFFFF);
2632 FPR_STATE[fpr] = fmt;
2633 break;
2634
2635 case fmt_uninterpreted_64:
2636 fmt = fmt_uninterpreted;
2637 case fmt_uninterpreted:
2638 case fmt_double :
2639 case fmt_long :
2640 if ((fpr & 1) == 0) { /* even register number only */
2641 FGR[fpr+1] = (value >> 32);
2642 FGR[fpr] = (value & 0xFFFFFFFF);
2643 FPR_STATE[fpr + 1] = fmt;
2644 FPR_STATE[fpr] = fmt;
2645 } else {
2646 FPR_STATE[fpr] = fmt_unknown;
2647 FPR_STATE[fpr + 1] = fmt_unknown;
2648 SignalException(ReservedInstruction,0);
2649 }
2650 break;
2651
2652 default :
2653 FPR_STATE[fpr] = fmt_unknown;
2654 err = -1;
2655 break;
2656 }
2657 }
2658 #if defined(WARN_RESULT)
2659 else
2660 UndefinedResult();
2661 #endif /* WARN_RESULT */
2662
2663 if (err)
2664 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2665
2666 #ifdef DEBUG
2667 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2668 #endif /* DEBUG */
2669
2670 return;
2671 }
2672
2673 int
2674 NaN(op,fmt)
2675 uword64 op;
2676 FP_formats fmt;
2677 {
2678 int boolean = 0;
2679 switch (fmt) {
2680 case fmt_single:
2681 case fmt_word:
2682 {
2683 sim_fpu wop;
2684 sim_fpu_32to (&wop, op);
2685 boolean = sim_fpu_is_nan (&wop);
2686 break;
2687 }
2688 case fmt_double:
2689 case fmt_long:
2690 {
2691 sim_fpu wop;
2692 sim_fpu_64to (&wop, op);
2693 boolean = sim_fpu_is_nan (&wop);
2694 break;
2695 }
2696 default:
2697 fprintf (stderr, "Bad switch\n");
2698 abort ();
2699 }
2700
2701 #ifdef DEBUG
2702 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2703 #endif /* DEBUG */
2704
2705 return(boolean);
2706 }
2707
2708 int
2709 Infinity(op,fmt)
2710 uword64 op;
2711 FP_formats fmt;
2712 {
2713 int boolean = 0;
2714
2715 #ifdef DEBUG
2716 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
2717 #endif /* DEBUG */
2718
2719 switch (fmt) {
2720 case fmt_single:
2721 {
2722 sim_fpu wop;
2723 sim_fpu_32to (&wop, op);
2724 boolean = sim_fpu_is_infinity (&wop);
2725 break;
2726 }
2727 case fmt_double:
2728 {
2729 sim_fpu wop;
2730 sim_fpu_64to (&wop, op);
2731 boolean = sim_fpu_is_infinity (&wop);
2732 break;
2733 }
2734 default:
2735 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2736 break;
2737 }
2738
2739 #ifdef DEBUG
2740 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2741 #endif /* DEBUG */
2742
2743 return(boolean);
2744 }
2745
2746 int
2747 Less(op1,op2,fmt)
2748 uword64 op1;
2749 uword64 op2;
2750 FP_formats fmt;
2751 {
2752 int boolean = 0;
2753
2754 /* Argument checking already performed by the FPCOMPARE code */
2755
2756 #ifdef DEBUG
2757 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2758 #endif /* DEBUG */
2759
2760 /* The format type should already have been checked: */
2761 switch (fmt) {
2762 case fmt_single:
2763 {
2764 sim_fpu wop1;
2765 sim_fpu wop2;
2766 sim_fpu_32to (&wop1, op1);
2767 sim_fpu_32to (&wop2, op2);
2768 boolean = sim_fpu_is_lt (&wop1, &wop2);
2769 break;
2770 }
2771 case fmt_double:
2772 {
2773 sim_fpu wop1;
2774 sim_fpu wop2;
2775 sim_fpu_64to (&wop1, op1);
2776 sim_fpu_64to (&wop2, op2);
2777 boolean = sim_fpu_is_lt (&wop1, &wop2);
2778 break;
2779 }
2780 default:
2781 fprintf (stderr, "Bad switch\n");
2782 abort ();
2783 }
2784
2785 #ifdef DEBUG
2786 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2787 #endif /* DEBUG */
2788
2789 return(boolean);
2790 }
2791
2792 int
2793 Equal(op1,op2,fmt)
2794 uword64 op1;
2795 uword64 op2;
2796 FP_formats fmt;
2797 {
2798 int boolean = 0;
2799
2800 /* Argument checking already performed by the FPCOMPARE code */
2801
2802 #ifdef DEBUG
2803 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2804 #endif /* DEBUG */
2805
2806 /* The format type should already have been checked: */
2807 switch (fmt) {
2808 case fmt_single:
2809 {
2810 sim_fpu wop1;
2811 sim_fpu wop2;
2812 sim_fpu_32to (&wop1, op1);
2813 sim_fpu_32to (&wop2, op2);
2814 boolean = sim_fpu_is_eq (&wop1, &wop2);
2815 break;
2816 }
2817 case fmt_double:
2818 {
2819 sim_fpu wop1;
2820 sim_fpu wop2;
2821 sim_fpu_64to (&wop1, op1);
2822 sim_fpu_64to (&wop2, op2);
2823 boolean = sim_fpu_is_eq (&wop1, &wop2);
2824 break;
2825 }
2826 default:
2827 fprintf (stderr, "Bad switch\n");
2828 abort ();
2829 }
2830
2831 #ifdef DEBUG
2832 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2833 #endif /* DEBUG */
2834
2835 return(boolean);
2836 }
2837
2838 uword64
2839 AbsoluteValue(op,fmt)
2840 uword64 op;
2841 FP_formats fmt;
2842 {
2843 uword64 result = 0;
2844
2845 #ifdef DEBUG
2846 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2847 #endif /* DEBUG */
2848
2849 /* The format type should already have been checked: */
2850 switch (fmt) {
2851 case fmt_single:
2852 {
2853 sim_fpu wop;
2854 unsigned32 ans;
2855 sim_fpu_32to (&wop, op);
2856 sim_fpu_abs (&wop, &wop);
2857 sim_fpu_to32 (&ans, &wop);
2858 result = ans;
2859 break;
2860 }
2861 case fmt_double:
2862 {
2863 sim_fpu wop;
2864 unsigned64 ans;
2865 sim_fpu_64to (&wop, op);
2866 sim_fpu_abs (&wop, &wop);
2867 sim_fpu_to64 (&ans, &wop);
2868 result = ans;
2869 break;
2870 }
2871 default:
2872 fprintf (stderr, "Bad switch\n");
2873 abort ();
2874 }
2875
2876 return(result);
2877 }
2878
2879 uword64
2880 Negate(op,fmt)
2881 uword64 op;
2882 FP_formats fmt;
2883 {
2884 uword64 result = 0;
2885
2886 #ifdef DEBUG
2887 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2888 #endif /* DEBUG */
2889
2890 /* The format type should already have been checked: */
2891 switch (fmt) {
2892 case fmt_single:
2893 {
2894 sim_fpu wop;
2895 unsigned32 ans;
2896 sim_fpu_32to (&wop, op);
2897 sim_fpu_neg (&wop, &wop);
2898 sim_fpu_to32 (&ans, &wop);
2899 result = ans;
2900 break;
2901 }
2902 case fmt_double:
2903 {
2904 sim_fpu wop;
2905 unsigned64 ans;
2906 sim_fpu_64to (&wop, op);
2907 sim_fpu_neg (&wop, &wop);
2908 sim_fpu_to64 (&ans, &wop);
2909 result = ans;
2910 break;
2911 }
2912 default:
2913 fprintf (stderr, "Bad switch\n");
2914 abort ();
2915 }
2916
2917 return(result);
2918 }
2919
2920 uword64
2921 Add(op1,op2,fmt)
2922 uword64 op1;
2923 uword64 op2;
2924 FP_formats fmt;
2925 {
2926 uword64 result = 0;
2927
2928 #ifdef DEBUG
2929 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2930 #endif /* DEBUG */
2931
2932 /* The registers must specify FPRs valid for operands of type
2933 "fmt". If they are not valid, the result is undefined. */
2934
2935 /* The format type should already have been checked: */
2936 switch (fmt) {
2937 case fmt_single:
2938 {
2939 sim_fpu wop1;
2940 sim_fpu wop2;
2941 sim_fpu ans;
2942 unsigned32 res;
2943 sim_fpu_32to (&wop1, op1);
2944 sim_fpu_32to (&wop2, op2);
2945 sim_fpu_add (&ans, &wop1, &wop2);
2946 sim_fpu_to32 (&res, &ans);
2947 result = res;
2948 break;
2949 }
2950 case fmt_double:
2951 {
2952 sim_fpu wop1;
2953 sim_fpu wop2;
2954 sim_fpu ans;
2955 unsigned64 res;
2956 sim_fpu_64to (&wop1, op1);
2957 sim_fpu_64to (&wop2, op2);
2958 sim_fpu_add (&ans, &wop1, &wop2);
2959 sim_fpu_to64 (&res, &ans);
2960 result = res;
2961 break;
2962 }
2963 default:
2964 fprintf (stderr, "Bad switch\n");
2965 abort ();
2966 }
2967
2968 #ifdef DEBUG
2969 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2970 #endif /* DEBUG */
2971
2972 return(result);
2973 }
2974
2975 uword64
2976 Sub(op1,op2,fmt)
2977 uword64 op1;
2978 uword64 op2;
2979 FP_formats fmt;
2980 {
2981 uword64 result = 0;
2982
2983 #ifdef DEBUG
2984 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2985 #endif /* DEBUG */
2986
2987 /* The registers must specify FPRs valid for operands of type
2988 "fmt". If they are not valid, the result is undefined. */
2989
2990 /* The format type should already have been checked: */
2991 switch (fmt) {
2992 case fmt_single:
2993 {
2994 sim_fpu wop1;
2995 sim_fpu wop2;
2996 sim_fpu ans;
2997 unsigned32 res;
2998 sim_fpu_32to (&wop1, op1);
2999 sim_fpu_32to (&wop2, op2);
3000 sim_fpu_sub (&ans, &wop1, &wop2);
3001 sim_fpu_to32 (&res, &ans);
3002 result = res;
3003 }
3004 break;
3005 case fmt_double:
3006 {
3007 sim_fpu wop1;
3008 sim_fpu wop2;
3009 sim_fpu ans;
3010 unsigned64 res;
3011 sim_fpu_64to (&wop1, op1);
3012 sim_fpu_64to (&wop2, op2);
3013 sim_fpu_sub (&ans, &wop1, &wop2);
3014 sim_fpu_to64 (&res, &ans);
3015 result = res;
3016 }
3017 break;
3018 default:
3019 fprintf (stderr, "Bad switch\n");
3020 abort ();
3021 }
3022
3023 #ifdef DEBUG
3024 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
3025 #endif /* DEBUG */
3026
3027 return(result);
3028 }
3029
3030 uword64
3031 Multiply(op1,op2,fmt)
3032 uword64 op1;
3033 uword64 op2;
3034 FP_formats fmt;
3035 {
3036 uword64 result = 0;
3037
3038 #ifdef DEBUG
3039 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
3040 #endif /* DEBUG */
3041
3042 /* The registers must specify FPRs valid for operands of type
3043 "fmt". If they are not valid, the result is undefined. */
3044
3045 /* The format type should already have been checked: */
3046 switch (fmt) {
3047 case fmt_single:
3048 {
3049 sim_fpu wop1;
3050 sim_fpu wop2;
3051 sim_fpu ans;
3052 unsigned32 res;
3053 sim_fpu_32to (&wop1, op1);
3054 sim_fpu_32to (&wop2, op2);
3055 sim_fpu_mul (&ans, &wop1, &wop2);
3056 sim_fpu_to32 (&res, &ans);
3057 result = res;
3058 break;
3059 }
3060 case fmt_double:
3061 {
3062 sim_fpu wop1;
3063 sim_fpu wop2;
3064 sim_fpu ans;
3065 unsigned64 res;
3066 sim_fpu_64to (&wop1, op1);
3067 sim_fpu_64to (&wop2, op2);
3068 sim_fpu_mul (&ans, &wop1, &wop2);
3069 sim_fpu_to64 (&res, &ans);
3070 result = res;
3071 break;
3072 }
3073 default:
3074 fprintf (stderr, "Bad switch\n");
3075 abort ();
3076 }
3077
3078 #ifdef DEBUG
3079 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
3080 #endif /* DEBUG */
3081
3082 return(result);
3083 }
3084
3085 uword64
3086 Divide(op1,op2,fmt)
3087 uword64 op1;
3088 uword64 op2;
3089 FP_formats fmt;
3090 {
3091 uword64 result = 0;
3092
3093 #ifdef DEBUG
3094 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
3095 #endif /* DEBUG */
3096
3097 /* The registers must specify FPRs valid for operands of type
3098 "fmt". If they are not valid, the result is undefined. */
3099
3100 /* The format type should already have been checked: */
3101 switch (fmt) {
3102 case fmt_single:
3103 {
3104 sim_fpu wop1;
3105 sim_fpu wop2;
3106 sim_fpu ans;
3107 unsigned32 res;
3108 sim_fpu_32to (&wop1, op1);
3109 sim_fpu_32to (&wop2, op2);
3110 sim_fpu_div (&ans, &wop1, &wop2);
3111 sim_fpu_to32 (&res, &ans);
3112 result = res;
3113 break;
3114 }
3115 case fmt_double:
3116 {
3117 sim_fpu wop1;
3118 sim_fpu wop2;
3119 sim_fpu ans;
3120 unsigned64 res;
3121 sim_fpu_64to (&wop1, op1);
3122 sim_fpu_64to (&wop2, op2);
3123 sim_fpu_div (&ans, &wop1, &wop2);
3124 sim_fpu_to64 (&res, &ans);
3125 result = res;
3126 break;
3127 }
3128 default:
3129 fprintf (stderr, "Bad switch\n");
3130 abort ();
3131 }
3132
3133 #ifdef DEBUG
3134 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
3135 #endif /* DEBUG */
3136
3137 return(result);
3138 }
3139
3140 uword64 UNUSED
3141 Recip(op,fmt)
3142 uword64 op;
3143 FP_formats fmt;
3144 {
3145 uword64 result = 0;
3146
3147 #ifdef DEBUG
3148 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
3149 #endif /* DEBUG */
3150
3151 /* The registers must specify FPRs valid for operands of type
3152 "fmt". If they are not valid, the result is undefined. */
3153
3154 /* The format type should already have been checked: */
3155 switch (fmt) {
3156 case fmt_single:
3157 {
3158 sim_fpu wop;
3159 sim_fpu ans;
3160 unsigned32 res;
3161 sim_fpu_32to (&wop, op);
3162 sim_fpu_inv (&ans, &wop);
3163 sim_fpu_to32 (&res, &ans);
3164 result = res;
3165 break;
3166 }
3167 case fmt_double:
3168 {
3169 sim_fpu wop;
3170 sim_fpu ans;
3171 unsigned64 res;
3172 sim_fpu_64to (&wop, op);
3173 sim_fpu_inv (&ans, &wop);
3174 sim_fpu_to64 (&res, &ans);
3175 result = res;
3176 break;
3177 }
3178 default:
3179 fprintf (stderr, "Bad switch\n");
3180 abort ();
3181 }
3182
3183 #ifdef DEBUG
3184 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
3185 #endif /* DEBUG */
3186
3187 return(result);
3188 }
3189
3190 uword64
3191 SquareRoot(op,fmt)
3192 uword64 op;
3193 FP_formats fmt;
3194 {
3195 uword64 result = 0;
3196
3197 #ifdef DEBUG
3198 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
3199 #endif /* DEBUG */
3200
3201 /* The registers must specify FPRs valid for operands of type
3202 "fmt". If they are not valid, the result is undefined. */
3203
3204 /* The format type should already have been checked: */
3205 switch (fmt) {
3206 case fmt_single:
3207 {
3208 sim_fpu wop;
3209 sim_fpu ans;
3210 unsigned32 res;
3211 sim_fpu_32to (&wop, op);
3212 sim_fpu_sqrt (&ans, &wop);
3213 sim_fpu_to32 (&res, &ans);
3214 result = res;
3215 break;
3216 }
3217 case fmt_double:
3218 {
3219 sim_fpu wop;
3220 sim_fpu ans;
3221 unsigned64 res;
3222 sim_fpu_64to (&wop, op);
3223 sim_fpu_sqrt (&ans, &wop);
3224 sim_fpu_to64 (&res, &ans);
3225 result = res;
3226 break;
3227 }
3228 default:
3229 fprintf (stderr, "Bad switch\n");
3230 abort ();
3231 }
3232
3233 #ifdef DEBUG
3234 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
3235 #endif /* DEBUG */
3236
3237 return(result);
3238 }
3239
3240 #if 0
3241 uword64
3242 Max (uword64 op1,
3243 uword64 op2,
3244 FP_formats fmt)
3245 {
3246 int cmp;
3247 unsigned64 result;
3248
3249 #ifdef DEBUG
3250 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
3251 #endif /* DEBUG */
3252
3253 /* The registers must specify FPRs valid for operands of type
3254 "fmt". If they are not valid, the result is undefined. */
3255
3256 /* The format type should already have been checked: */
3257 switch (fmt)
3258 {
3259 case fmt_single:
3260 {
3261 sim_fpu wop1;
3262 sim_fpu wop2;
3263 sim_fpu_32to (&wop1, op1);
3264 sim_fpu_32to (&wop2, op2);
3265 cmp = sim_fpu_cmp (&wop1, &wop2);
3266 break;
3267 }
3268 case fmt_double:
3269 {
3270 sim_fpu wop1;
3271 sim_fpu wop2;
3272 sim_fpu_64to (&wop1, op1);
3273 sim_fpu_64to (&wop2, op2);
3274 cmp = sim_fpu_cmp (&wop1, &wop2);
3275 break;
3276 }
3277 default:
3278 fprintf (stderr, "Bad switch\n");
3279 abort ();
3280 }
3281
3282 switch (cmp)
3283 {
3284 case SIM_FPU_IS_SNAN:
3285 case SIM_FPU_IS_QNAN:
3286 result = op1;
3287 case SIM_FPU_IS_NINF:
3288 case SIM_FPU_IS_NNUMBER:
3289 case SIM_FPU_IS_NDENORM:
3290 case SIM_FPU_IS_NZERO:
3291 result = op2; /* op1 - op2 < 0 */
3292 case SIM_FPU_IS_PINF:
3293 case SIM_FPU_IS_PNUMBER:
3294 case SIM_FPU_IS_PDENORM:
3295 case SIM_FPU_IS_PZERO:
3296 result = op1; /* op1 - op2 > 0 */
3297 default:
3298 fprintf (stderr, "Bad switch\n");
3299 abort ();
3300 }
3301
3302 #ifdef DEBUG
3303 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
3304 #endif /* DEBUG */
3305
3306 return(result);
3307 }
3308 #endif
3309
3310 #if 0
3311 uword64
3312 Min (uword64 op1,
3313 uword64 op2,
3314 FP_formats fmt)
3315 {
3316 int cmp;
3317 unsigned64 result;
3318
3319 #ifdef DEBUG
3320 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
3321 #endif /* DEBUG */
3322
3323 /* The registers must specify FPRs valid for operands of type
3324 "fmt". If they are not valid, the result is undefined. */
3325
3326 /* The format type should already have been checked: */
3327 switch (fmt)
3328 {
3329 case fmt_single:
3330 {
3331 sim_fpu wop1;
3332 sim_fpu wop2;
3333 sim_fpu_32to (&wop1, op1);
3334 sim_fpu_32to (&wop2, op2);
3335 cmp = sim_fpu_cmp (&wop1, &wop2);
3336 break;
3337 }
3338 case fmt_double:
3339 {
3340 sim_fpu wop1;
3341 sim_fpu wop2;
3342 sim_fpu_64to (&wop1, op1);
3343 sim_fpu_64to (&wop2, op2);
3344 cmp = sim_fpu_cmp (&wop1, &wop2);
3345 break;
3346 }
3347 default:
3348 fprintf (stderr, "Bad switch\n");
3349 abort ();
3350 }
3351
3352 switch (cmp)
3353 {
3354 case SIM_FPU_IS_SNAN:
3355 case SIM_FPU_IS_QNAN:
3356 result = op1;
3357 case SIM_FPU_IS_NINF:
3358 case SIM_FPU_IS_NNUMBER:
3359 case SIM_FPU_IS_NDENORM:
3360 case SIM_FPU_IS_NZERO:
3361 result = op1; /* op1 - op2 < 0 */
3362 case SIM_FPU_IS_PINF:
3363 case SIM_FPU_IS_PNUMBER:
3364 case SIM_FPU_IS_PDENORM:
3365 case SIM_FPU_IS_PZERO:
3366 result = op2; /* op1 - op2 > 0 */
3367 default:
3368 fprintf (stderr, "Bad switch\n");
3369 abort ();
3370 }
3371
3372 #ifdef DEBUG
3373 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
3374 #endif /* DEBUG */
3375
3376 return(result);
3377 }
3378 #endif
3379
3380 uword64
3381 convert (SIM_DESC sd,
3382 sim_cpu *cpu,
3383 address_word cia,
3384 int rm,
3385 uword64 op,
3386 FP_formats from,
3387 FP_formats to)
3388 {
3389 sim_fpu wop;
3390 sim_fpu_round round;
3391 unsigned32 result32;
3392 unsigned64 result64;
3393
3394 #ifdef DEBUG
3395 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
3396 #endif /* DEBUG */
3397
3398 switch (rm)
3399 {
3400 case FP_RM_NEAREST:
3401 /* Round result to nearest representable value. When two
3402 representable values are equally near, round to the value
3403 that has a least significant bit of zero (i.e. is even). */
3404 round = sim_fpu_round_near;
3405 break;
3406 case FP_RM_TOZERO:
3407 /* Round result to the value closest to, and not greater in
3408 magnitude than, the result. */
3409 round = sim_fpu_round_zero;
3410 break;
3411 case FP_RM_TOPINF:
3412 /* Round result to the value closest to, and not less than,
3413 the result. */
3414 round = sim_fpu_round_up;
3415 break;
3416
3417 case FP_RM_TOMINF:
3418 /* Round result to the value closest to, and not greater than,
3419 the result. */
3420 round = sim_fpu_round_down;
3421 break;
3422 default:
3423 round = 0;
3424 fprintf (stderr, "Bad switch\n");
3425 abort ();
3426 }
3427
3428 /* Convert the input to sim_fpu internal format */
3429 switch (from)
3430 {
3431 case fmt_double:
3432 sim_fpu_64to (&wop, op);
3433 break;
3434 case fmt_single:
3435 sim_fpu_32to (&wop, op);
3436 break;
3437 case fmt_word:
3438 sim_fpu_i32to (&wop, op, round);
3439 break;
3440 case fmt_long:
3441 sim_fpu_i64to (&wop, op, round);
3442 break;
3443 default:
3444 fprintf (stderr, "Bad switch\n");
3445 abort ();
3446 }
3447
3448 /* Convert sim_fpu format into the output */
3449 /* The value WOP is converted to the destination format, rounding
3450 using mode RM. When the destination is a fixed-point format, then
3451 a source value of Infinity, NaN or one which would round to an
3452 integer outside the fixed point range then an IEEE Invalid
3453 Operation condition is raised. */
3454 switch (to)
3455 {
3456 case fmt_single:
3457 sim_fpu_round_32 (&wop, round, 0);
3458 sim_fpu_to32 (&result32, &wop);
3459 result64 = result32;
3460 break;
3461 case fmt_double:
3462 sim_fpu_round_64 (&wop, round, 0);
3463 sim_fpu_to64 (&result64, &wop);
3464 break;
3465 case fmt_word:
3466 sim_fpu_to32i (&result32, &wop, round);
3467 result64 = result32;
3468 break;
3469 case fmt_long:
3470 sim_fpu_to64i (&result64, &wop, round);
3471 break;
3472 default:
3473 result64 = 0;
3474 fprintf (stderr, "Bad switch\n");
3475 abort ();
3476 }
3477
3478 #ifdef DEBUG
3479 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
3480 #endif /* DEBUG */
3481
3482 return(result64);
3483 }
3484
3485
3486 /*-- co-processor support routines ------------------------------------------*/
3487
3488 static int UNUSED
3489 CoProcPresent(coproc_number)
3490 unsigned int coproc_number;
3491 {
3492 /* Return TRUE if simulator provides a model for the given co-processor number */
3493 return(0);
3494 }
3495
3496 void
3497 cop_lw (SIM_DESC sd,
3498 sim_cpu *cpu,
3499 address_word cia,
3500 int coproc_num,
3501 int coproc_reg,
3502 unsigned int memword)
3503 {
3504 switch (coproc_num)
3505 {
3506 case 1:
3507 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3508 {
3509 #ifdef DEBUG
3510 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
3511 #endif
3512 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
3513 FPR_STATE[coproc_reg] = fmt_uninterpreted;
3514 break;
3515 }
3516
3517 default:
3518 #if 0 /* this should be controlled by a configuration option */
3519 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
3520 #endif
3521 break;
3522 }
3523
3524 return;
3525 }
3526
3527 void
3528 cop_ld (SIM_DESC sd,
3529 sim_cpu *cpu,
3530 address_word cia,
3531 int coproc_num,
3532 int coproc_reg,
3533 uword64 memword)
3534 {
3535 switch (coproc_num) {
3536 case 1:
3537 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3538 {
3539 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
3540 break;
3541 }
3542
3543 default:
3544 #if 0 /* this message should be controlled by a configuration option */
3545 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
3546 #endif
3547 break;
3548 }
3549
3550 return;
3551 }
3552
3553
3554 /* start-sanitize-sky */
3555 #if defined(TARGET_SKY) && !defined(TARGET_SKY_B)
3556 void
3557 cop_lq (SIM_DESC sd,
3558 sim_cpu *cpu,
3559 address_word cia,
3560 int coproc_num,
3561 int coproc_reg,
3562 unsigned128 memword)
3563 {
3564 switch (coproc_num)
3565 {
3566 case 2:
3567 {
3568 int i;
3569
3570 while(vu0_busy())
3571 vu0_issue(sd);
3572
3573 /* one word at a time, argh! */
3574 for(i=0; i<4; i++)
3575 {
3576 unsigned_4 value;
3577 value = H2T_4(*A4_16(& memword, 3-i));
3578 write_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3579 }
3580 }
3581 break;
3582
3583 default:
3584 sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
3585 coproc_num,coproc_reg,pr_addr(cia));
3586 break;
3587 }
3588
3589 return;
3590 }
3591 #endif /* TARGET_SKY */
3592 /* end-sanitize-sky */
3593
3594
3595 unsigned int
3596 cop_sw (SIM_DESC sd,
3597 sim_cpu *cpu,
3598 address_word cia,
3599 int coproc_num,
3600 int coproc_reg)
3601 {
3602 unsigned int value = 0;
3603
3604 switch (coproc_num)
3605 {
3606 case 1:
3607 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3608 {
3609 FP_formats hold;
3610 hold = FPR_STATE[coproc_reg];
3611 FPR_STATE[coproc_reg] = fmt_word;
3612 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
3613 FPR_STATE[coproc_reg] = hold;
3614 break;
3615 }
3616
3617 default:
3618 #if 0 /* should be controlled by configuration option */
3619 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3620 #endif
3621 break;
3622 }
3623
3624 return(value);
3625 }
3626
3627 uword64
3628 cop_sd (SIM_DESC sd,
3629 sim_cpu *cpu,
3630 address_word cia,
3631 int coproc_num,
3632 int coproc_reg)
3633 {
3634 uword64 value = 0;
3635 switch (coproc_num)
3636 {
3637 case 1:
3638 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3639 {
3640 value = ValueFPR(coproc_reg,fmt_uninterpreted);
3641 break;
3642 }
3643
3644 default:
3645 #if 0 /* should be controlled by configuration option */
3646 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3647 #endif
3648 break;
3649 }
3650
3651 return(value);
3652 }
3653
3654
3655 /* start-sanitize-sky */
3656 #if defined(TARGET_SKY) && !defined(TARGET_SKY_B)
3657 unsigned128
3658 cop_sq (SIM_DESC sd,
3659 sim_cpu *cpu,
3660 address_word cia,
3661 int coproc_num,
3662 int coproc_reg)
3663 {
3664 unsigned128 value = U16_8(0, 0);
3665 switch (coproc_num)
3666 {
3667 case 2:
3668 {
3669 unsigned_16 xyzw;
3670 int i;
3671
3672 while(vu0_busy())
3673 vu0_issue(sd);
3674
3675 /* one word at a time, argh! */
3676 for(i=0; i<4; i++)
3677 {
3678 unsigned_4 value;
3679 read_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3680 *A4_16(& xyzw, 3-i) = T2H_4(value);
3681 }
3682 return xyzw;
3683 }
3684 break;
3685
3686 default:
3687 sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
3688 coproc_num,coproc_reg,pr_addr(cia));
3689 break;
3690 }
3691
3692 return(value);
3693 }
3694 #endif /* TARGET_SKY */
3695 /* end-sanitize-sky */
3696
3697
3698 void
3699 decode_coproc (SIM_DESC sd,
3700 sim_cpu *cpu,
3701 address_word cia,
3702 unsigned int instruction)
3703 {
3704 int coprocnum = ((instruction >> 26) & 3);
3705
3706 switch (coprocnum)
3707 {
3708 case 0: /* standard CPU control and cache registers */
3709 {
3710 int code = ((instruction >> 21) & 0x1F);
3711 int rt = ((instruction >> 16) & 0x1F);
3712 int rd = ((instruction >> 11) & 0x1F);
3713 int tail = instruction & 0x3ff;
3714 /* R4000 Users Manual (second edition) lists the following CP0
3715 instructions:
3716 CODE><-RT><RD-><--TAIL--->
3717 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3718 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3719 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3720 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3721 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3722 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3723 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3724 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3725 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3726 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3727 */
3728 if (((code == 0x00) || (code == 0x04)) && tail == 0)
3729 {
3730 /* M[TF]C0 - 32 bit word */
3731
3732 switch (rd) /* NOTEs: Standard CP0 registers */
3733 {
3734 /* 0 = Index R4000 VR4100 VR4300 */
3735 /* 1 = Random R4000 VR4100 VR4300 */
3736 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3737 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3738 /* 4 = Context R4000 VR4100 VR4300 */
3739 /* 5 = PageMask R4000 VR4100 VR4300 */
3740 /* 6 = Wired R4000 VR4100 VR4300 */
3741 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3742 /* 9 = Count R4000 VR4100 VR4300 */
3743 /* 10 = EntryHi R4000 VR4100 VR4300 */
3744 /* 11 = Compare R4000 VR4100 VR4300 */
3745 /* 12 = SR R4000 VR4100 VR4300 */
3746 #ifdef SUBTARGET_R3900
3747 case 3:
3748 /* ignore */
3749 break;
3750 /* 3 = Config R3900 */
3751
3752 case 7:
3753 /* ignore */
3754 break;
3755 /* 3 = Cache R3900 */
3756
3757 #endif /* SUBTARGET_R3900 */
3758 case 12:
3759 if (code == 0x00)
3760 GPR[rt] = SR;
3761 else
3762 SR = GPR[rt];
3763 break;
3764 /* 13 = Cause R4000 VR4100 VR4300 */
3765 case 13:
3766 if (code == 0x00)
3767 GPR[rt] = CAUSE;
3768 else
3769 CAUSE = GPR[rt];
3770 break;
3771 /* 14 = EPC R4000 VR4100 VR4300 */
3772 case 14:
3773 if (code == 0x00)
3774 GPR[rt] = (signed_word) (signed_address) EPC;
3775 else
3776 EPC = GPR[rt];
3777 break;
3778 /* 15 = PRId R4000 VR4100 VR4300 */
3779 #ifdef SUBTARGET_R3900
3780 /* 16 = Debug */
3781 case 16:
3782 if (code == 0x00)
3783 GPR[rt] = Debug;
3784 else
3785 Debug = GPR[rt];
3786 break;
3787 #else
3788 /* 16 = Config R4000 VR4100 VR4300 */
3789 case 16:
3790 if (code == 0x00)
3791 GPR[rt] = C0_CONFIG;
3792 else
3793 C0_CONFIG = GPR[rt];
3794 break;
3795 #endif
3796 #ifdef SUBTARGET_R3900
3797 /* 17 = Debug */
3798 case 17:
3799 if (code == 0x00)
3800 GPR[rt] = DEPC;
3801 else
3802 DEPC = GPR[rt];
3803 break;
3804 #else
3805 /* 17 = LLAddr R4000 VR4100 VR4300 */
3806 #endif
3807 /* 18 = WatchLo R4000 VR4100 VR4300 */
3808 /* 19 = WatchHi R4000 VR4100 VR4300 */
3809 /* 20 = XContext R4000 VR4100 VR4300 */
3810 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3811 /* 27 = CacheErr R4000 VR4100 */
3812 /* 28 = TagLo R4000 VR4100 VR4300 */
3813 /* 29 = TagHi R4000 VR4100 VR4300 */
3814 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3815 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3816 /* CPR[0,rd] = GPR[rt]; */
3817 default:
3818 if (code == 0x00)
3819 GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
3820 else
3821 COP0_GPR[rd] = GPR[rt];
3822 #if 0
3823 if (code == 0x00)
3824 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3825 else
3826 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3827 #endif
3828 }
3829 }
3830 /* start-sanitize-r5900 */
3831 else if (((code == 0x00) || (code == 0x04)) && rd == 0x18 && tail > 0 && tail < NR_COP0_BP)
3832 /* Break-point registers */
3833 {
3834 if (code == 0x00)
3835 GPR[rt] = (signed_word) (signed32) COP0_BP[tail];
3836 else
3837 COP0_BP[tail] = GPR[rt];
3838 }
3839 else if (((code == 0x00) || (code == 0x04)) && rd == 0x19 && tail > 0 && tail < NR_COP0_P)
3840 /* Performance registers */
3841 {
3842 if (code == 0x00)
3843 GPR[rt] = (signed_word) (signed32) COP0_P[tail];
3844 else
3845 COP0_P[tail] = GPR[rt];
3846 }
3847 /* end-sanitize-r5900 */
3848 else if (code == 0x10 && (tail & 0x3f) == 0x18)
3849 {
3850 /* ERET */
3851 if (SR & status_ERL)
3852 {
3853 /* Oops, not yet available */
3854 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3855 PC = EPC;
3856 SR &= ~status_ERL;
3857 }
3858 else
3859 {
3860 PC = EPC;
3861 SR &= ~status_EXL;
3862 }
3863 }
3864 else if (code == 0x10 && (tail & 0x3f) == 0x10)
3865 {
3866 /* RFE */
3867 #ifdef SUBTARGET_R3900
3868 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
3869
3870 /* shift IE/KU history bits right */
3871 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
3872
3873 /* TODO: CACHE register */
3874 #endif /* SUBTARGET_R3900 */
3875 }
3876 else if (code == 0x10 && (tail & 0x3f) == 0x1F)
3877 {
3878 /* DERET */
3879 Debug &= ~Debug_DM;
3880 DELAYSLOT();
3881 DSPC = DEPC;
3882 }
3883 else
3884 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3885 /* TODO: When executing an ERET or RFE instruction we should
3886 clear LLBIT, to ensure that any out-standing atomic
3887 read/modify/write sequence fails. */
3888 }
3889 break;
3890
3891 case 2: /* co-processor 2 */
3892 {
3893 int handle = 0;
3894
3895 /* start-sanitize-sky */
3896 #if defined(TARGET_SKY) && !defined(TARGET_SKY_B)
3897 /* On the R5900, this refers to a "VU" vector co-processor. */
3898
3899 int i_25_21 = (instruction >> 21) & 0x1f;
3900 int i_20_16 = (instruction >> 16) & 0x1f;
3901 int i_20_6 = (instruction >> 6) & 0x7fff;
3902 int i_15_11 = (instruction >> 11) & 0x1f;
3903 int i_15_0 = instruction & 0xffff;
3904 int i_10_1 = (instruction >> 1) & 0x3ff;
3905 int i_10_0 = instruction & 0x7ff;
3906 int i_10_6 = (instruction >> 6) & 0x1f;
3907 int i_5_0 = instruction & 0x03f;
3908 int interlock = instruction & 0x01;
3909
3910 handle = 1;
3911
3912 /* test COP2 usability */
3913 if(! (SR & status_CU2))
3914 {
3915 SignalException(CoProcessorUnusable,instruction);
3916 /* NOTREACHED */
3917 }
3918
3919 /* BC2T/BC2F/BC2TL/BC2FL handled in r5900.igen */
3920
3921 else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
3922 (i_25_21 == 0x01)) /* QMFC2 */
3923 {
3924 int rt = i_20_16;
3925 int id = i_15_11;
3926
3927 /* interlock checking */
3928 /* POLICY: never busy in macro mode */
3929 while(vu0_busy() && interlock)
3930 vu0_issue(sd);
3931
3932 /* perform VU register access */
3933 if(i_25_21 == 0x01) /* QMFC2 */
3934 {
3935 unsigned_4 x,y,z,w;
3936
3937 /* one word at a time, argh! */
3938 read_vu_vec_reg(&(vu0_device.regs), id, 3, &w);
3939 read_vu_vec_reg(&(vu0_device.regs), id, 2, &z);
3940 read_vu_vec_reg(&(vu0_device.regs), id, 1, &y);
3941 read_vu_vec_reg(&(vu0_device.regs), id, 0, &x);
3942
3943 GPR[rt] = U8_4(T2H_4(y), T2H_4(x));
3944 GPR1[rt] = U8_4(T2H_4(w), T2H_4(z));
3945 }
3946 else /* CFC2 */
3947 {
3948 GPR[rt] = vu0_read_cop2_register(id);
3949 }
3950 }
3951 else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
3952 (i_25_21 == 0x05)) /* QMTC2 */
3953 {
3954 int rt = i_20_16;
3955 int id = i_15_11;
3956
3957 /* interlock checking: wait until M or E bits set */
3958 /* POLICY: never busy in macro mode */
3959 while(vu0_busy() && interlock)
3960 {
3961 if(vu0_micro_interlock_released())
3962 {
3963 vu0_micro_interlock_clear();
3964 break;
3965 }
3966
3967 vu0_issue(sd);
3968 }
3969
3970 /* perform VU register access */
3971 if(i_25_21 == 0x05) /* QMTC2 */
3972 {
3973 unsigned_4 x,y,z,w;
3974
3975 x = H2T_4(V4_8(GPR[rt], 1));
3976 y = H2T_4(V4_8(GPR[rt], 0));
3977 z = H2T_4(V4_8(GPR1[rt], 1));
3978 w = H2T_4(V4_8(GPR1[rt], 0));
3979
3980 /* one word at a time, argh! */
3981 write_vu_vec_reg(&(vu0_device.regs), id, 3, & w);
3982 write_vu_vec_reg(&(vu0_device.regs), id, 2, & z);
3983 write_vu_vec_reg(&(vu0_device.regs), id, 1, & y);
3984 write_vu_vec_reg(&(vu0_device.regs), id, 0, & x);
3985 }
3986 else /* CTC2 */
3987 {
3988 vu0_write_cop2_register(id, GPR[rt]);
3989 }
3990 }
3991 else if(i_10_0 == 0x3bf) /* VWAITQ */
3992 {
3993 while(vu0_q_busy())
3994 vu0_issue(sd);
3995 }
3996 else if(i_5_0 == 0x38) /* VCALLMS */
3997 {
3998 unsigned_4 data = H2T_2(i_20_6);
3999
4000 while(vu0_busy())
4001 vu0_issue(sd);
4002
4003 /* write to reserved CIA register to get VU0 moving */
4004 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
4005
4006 ASSERT(vu0_busy());
4007 }
4008 else if(i_5_0 == 0x39) /* VCALLMSR */
4009 {
4010 unsigned_4 data;
4011
4012 while(vu0_busy())
4013 vu0_issue(sd);
4014
4015 read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
4016 /* write to reserved CIA register to get VU0 moving */
4017 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
4018
4019 ASSERT(vu0_busy());
4020 }
4021 /* handle all remaining UPPER VU instructions in one block */
4022 else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
4023 (i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
4024 {
4025 unsigned_4 vu_upper, vu_lower;
4026 vu_upper =
4027 0x00000000 | /* bits 31 .. 25 */
4028 (instruction & 0x01ffffff); /* bits 24 .. 0 */
4029 vu_lower = 0x8000033c; /* NOP */
4030
4031 /* POLICY: never busy in macro mode */
4032 while(vu0_busy())
4033 vu0_issue(sd);
4034
4035 vu0_macro_issue(vu_upper, vu_lower);
4036
4037 /* POLICY: wait for completion of macro-instruction */
4038 while(vu0_busy())
4039 vu0_issue(sd);
4040 }
4041 /* handle all remaining LOWER VU instructions in one block */
4042 else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
4043 (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
4044 { /* N.B.: VWAITQ already covered by prior case */
4045 unsigned_4 vu_upper, vu_lower;
4046 vu_upper = 0x000002ff; /* NOP/NOP */
4047 vu_lower =
4048 0x80000000 | /* bits 31 .. 25 */
4049 (instruction & 0x01ffffff); /* bits 24 .. 0 */
4050
4051 /* POLICY: never busy in macro mode */
4052 while(vu0_busy())
4053 vu0_issue(sd);
4054
4055 vu0_macro_issue(vu_upper, vu_lower);
4056
4057 /* POLICY: wait for completion of macro-instruction */
4058 while(vu0_busy())
4059 vu0_issue(sd);
4060 }
4061 /* ... no other COP2 instructions ... */
4062 else
4063 {
4064 SignalException(ReservedInstruction, instruction);
4065 /* NOTREACHED */
4066 }
4067
4068 #endif /* TARGET_SKY */
4069 /* end-sanitize-sky */
4070
4071 if(! handle)
4072 {
4073 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
4074 instruction,pr_addr(cia));
4075 }
4076 }
4077 break;
4078
4079 case 1: /* should not occur (FPU co-processor) */
4080 case 3: /* should not occur (FPU co-processor) */
4081 SignalException(ReservedInstruction,instruction);
4082 break;
4083 }
4084
4085 return;
4086 }
4087
4088
4089 /*-- instruction simulation -------------------------------------------------*/
4090
4091 /* When the IGEN simulator is being built, the function below is be
4092 replaced by a generated version. However, WITH_IGEN == 2 indicates
4093 that the fubction below should be compiled but under a different
4094 name (to allow backward compatibility) */
4095
4096 #if (WITH_IGEN != 1)
4097 #if (WITH_IGEN > 1)
4098 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
4099 void
4100 old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
4101 #else
4102 void
4103 sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
4104 #endif
4105 SIM_DESC sd;
4106 int next_cpu_nr; /* ignore */
4107 int nr_cpus; /* ignore */
4108 int siggnal; /* ignore */
4109 {
4110 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
4111 #if !defined(FASTSIM)
4112 unsigned int pipeline_count = 1;
4113 #endif
4114
4115 #ifdef DEBUG
4116 if (STATE_MEMORY (sd) == NULL) {
4117 printf("DBG: simulate() entered with no memory\n");
4118 exit(1);
4119 }
4120 #endif /* DEBUG */
4121
4122 #if 0 /* Disabled to check that everything works OK */
4123 /* The VR4300 seems to sign-extend the PC on its first
4124 access. However, this may just be because it is currently
4125 configured in 32bit mode. However... */
4126 PC = SIGNEXTEND(PC,32);
4127 #endif
4128
4129 /* main controlling loop */
4130 while (1) {
4131 /* vaddr is slowly being replaced with cia - current instruction
4132 address */
4133 address_word cia = (uword64)PC;
4134 address_word vaddr = cia;
4135 address_word paddr;
4136 int cca;
4137 unsigned int instruction; /* uword64? what's this used for? FIXME! */
4138
4139 #ifdef DEBUG
4140 {
4141 printf("DBG: state = 0x%08X :",state);
4142 if (state & simHALTEX) printf(" simHALTEX");
4143 if (state & simHALTIN) printf(" simHALTIN");
4144 printf("\n");
4145 }
4146 #endif /* DEBUG */
4147
4148 DSSTATE = (STATE & simDELAYSLOT);
4149 #ifdef DEBUG
4150 if (dsstate)
4151 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
4152 #endif /* DEBUG */
4153
4154 /* Fetch the next instruction from the simulator memory: */
4155 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
4156 if ((vaddr & 1) == 0) {
4157 /* Copy the action of the LW instruction */
4158 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
4159 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
4160 uword64 value;
4161 unsigned int byte;
4162 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
4163 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
4164 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
4165 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
4166 } else {
4167 /* Copy the action of the LH instruction */
4168 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
4169 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
4170 uword64 value;
4171 unsigned int byte;
4172 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
4173 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
4174 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
4175 paddr & ~ (uword64) 1,
4176 vaddr, isINSTRUCTION, isREAL);
4177 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
4178 instruction = ((value >> (8 * byte)) & 0xFFFF);
4179 }
4180 } else {
4181 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
4182 exit(1);
4183 }
4184
4185 #ifdef DEBUG
4186 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
4187 #endif /* DEBUG */
4188
4189 /* This is required by exception processing, to ensure that we can
4190 cope with exceptions in the delay slots of branches that may
4191 already have changed the PC. */
4192 if ((vaddr & 1) == 0)
4193 PC += 4; /* increment ready for the next fetch */
4194 else
4195 PC += 2;
4196 /* NOTE: If we perform a delay slot change to the PC, this
4197 increment is not requuired. However, it would make the
4198 simulator more complicated to try and avoid this small hit. */
4199
4200 /* Currently this code provides a simple model. For more
4201 complicated models we could perform exception status checks at
4202 this point, and set the simSTOP state as required. This could
4203 also include processing any hardware interrupts raised by any
4204 I/O model attached to the simulator context.
4205
4206 Support for "asynchronous" I/O events within the simulated world
4207 could be providing by managing a counter, and calling a I/O
4208 specific handler when a particular threshold is reached. On most
4209 architectures a decrement and check for zero operation is
4210 usually quicker than an increment and compare. However, the
4211 process of managing a known value decrement to zero, is higher
4212 than the cost of using an explicit value UINT_MAX into the
4213 future. Which system is used will depend on how complicated the
4214 I/O model is, and how much it is likely to affect the simulator
4215 bandwidth.
4216
4217 If events need to be scheduled further in the future than
4218 UINT_MAX event ticks, then the I/O model should just provide its
4219 own counter, triggered from the event system. */
4220
4221 /* MIPS pipeline ticks. To allow for future support where the
4222 pipeline hit of individual instructions is known, this control
4223 loop manages a "pipeline_count" variable. It is initialised to
4224 1 (one), and will only be changed by the simulator engine when
4225 executing an instruction. If the engine does not have access to
4226 pipeline cycle count information then all instructions will be
4227 treated as using a single cycle. NOTE: A standard system is not
4228 provided by the default simulator because different MIPS
4229 architectures have different cycle counts for the same
4230 instructions.
4231
4232 [NOTE: pipeline_count has been replaced the event queue] */
4233
4234 /* shuffle the floating point status pipeline state */
4235 ENGINE_ISSUE_PREFIX_HOOK();
4236
4237 /* NOTE: For multi-context simulation environments the "instruction"
4238 variable should be local to this routine. */
4239
4240 /* Shorthand accesses for engine. Note: If we wanted to use global
4241 variables (and a single-threaded simulator engine), then we can
4242 create the actual variables with these names. */
4243
4244 if (!(STATE & simSKIPNEXT)) {
4245 /* Include the simulator engine */
4246 #include "oengine.c"
4247 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
4248 #error "Mismatch between run-time simulator code and simulation engine"
4249 #endif
4250 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
4251 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
4252 #endif
4253 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
4254 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
4255 #endif
4256
4257 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
4258 should check for it being changed. It is better doing it here,
4259 than within the simulator, since it will help keep the simulator
4260 small. */
4261 if (ZERO != 0) {
4262 #if defined(WARN_ZERO)
4263 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
4264 #endif /* WARN_ZERO */
4265 ZERO = 0; /* reset back to zero before next instruction */
4266 }
4267 } else /* simSKIPNEXT check */
4268 STATE &= ~simSKIPNEXT;
4269
4270 /* If the delay slot was active before the instruction is
4271 executed, then update the PC to its new value: */
4272 if (DSSTATE) {
4273 #ifdef DEBUG
4274 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
4275 #endif /* DEBUG */
4276 PC = DSPC;
4277 CANCELDELAYSLOT();
4278 }
4279
4280 if (MIPSISA < 4)
4281 PENDING_TICK();
4282
4283 #if !defined(FASTSIM)
4284 if (sim_events_tickn (sd, pipeline_count))
4285 {
4286 /* cpu->cia = cia; */
4287 sim_events_process (sd);
4288 }
4289 #else
4290 if (sim_events_tick (sd))
4291 {
4292 /* cpu->cia = cia; */
4293 sim_events_process (sd);
4294 }
4295 #endif /* FASTSIM */
4296 }
4297 }
4298 #endif
4299
4300
4301 /* This code copied from gdb's utils.c. Would like to share this code,
4302 but don't know of a common place where both could get to it. */
4303
4304 /* Temporary storage using circular buffer */
4305 #define NUMCELLS 16
4306 #define CELLSIZE 32
4307 static char*
4308 get_cell()
4309 {
4310 static char buf[NUMCELLS][CELLSIZE];
4311 static int cell=0;
4312 if (++cell>=NUMCELLS) cell=0;
4313 return buf[cell];
4314 }
4315
4316 /* Print routines to handle variable size regs, etc */
4317
4318 /* Eliminate warning from compiler on 32-bit systems */
4319 static int thirty_two = 32;
4320
4321 char*
4322 pr_addr(addr)
4323 SIM_ADDR addr;
4324 {
4325 char *paddr_str=get_cell();
4326 switch (sizeof(addr))
4327 {
4328 case 8:
4329 sprintf(paddr_str,"%08lx%08lx",
4330 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
4331 break;
4332 case 4:
4333 sprintf(paddr_str,"%08lx",(unsigned long)addr);
4334 break;
4335 case 2:
4336 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
4337 break;
4338 default:
4339 sprintf(paddr_str,"%x",addr);
4340 }
4341 return paddr_str;
4342 }
4343
4344 char*
4345 pr_uword64(addr)
4346 uword64 addr;
4347 {
4348 char *paddr_str=get_cell();
4349 sprintf(paddr_str,"%08lx%08lx",
4350 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
4351 return paddr_str;
4352 }
4353
4354
4355
4356 /*---------------------------------------------------------------------------*/
4357 /*> EOF interp.c <*/
GDB Binutils - Deliverables
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