6 // CPU Instruction Set (mips16)
9 // The instructions in this section are ordered according
10 // to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
13 // The MIPS16 codes registers in a special way, map from one to the other.
14 // :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
15 :compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
16 :compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
17 :compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
18 :compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
23 // Only the `LB' instruction is implemented. It should be used as a guideline
24 // when implementing other instructions.
26 // How to handle delayslots (for jumps) and extended lwpc instructions
27 // has not been resolved.
30 011101,26.INSTR_INDEX:NORMAL:32::JALX
32 // start-sanitize-tx19
39 // Load and Store Instructions
42 10000,3.RX,3.RY,5.IMMED:RRI:16::LB
44 // start-sanitize-tx19
48 GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
52 10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
54 // start-sanitize-tx19
58 GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
62 10001,3.RX,3.RY,5.IMMED:RRI:16::LH
64 // start-sanitize-tx19
68 GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
72 10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
74 // start-sanitize-tx19
78 GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
82 10011,3.RX,3.RY,5.IMMED:RRI:16::LW
84 // start-sanitize-tx19
88 GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
92 10110,3.RX,8.IMMED:RI:16::LWPC
94 // start-sanitize-tx19
98 GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
99 basepc (SD_) & ~3, IMMED << 2));
103 10010,3.RX,8.IMMED:RI:16::LWSP
105 // start-sanitize-tx19
109 GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
113 10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
115 // start-sanitize-tx19
119 GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
123 00111,3.RX,3.RY,5.IMMED:RRI:16,64::LD
125 // start-sanitize-tx19
129 GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
133 11111,100,3.RY,5.IMMED:RI64:16::LDPC
135 // start-sanitize-tx19
139 GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
140 basepc (SD_) & ~7, IMMED << 3);
144 11111,000,3.RY,5.IMMED:RI64:16::LDSP
146 // start-sanitize-tx19
150 GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
154 11000,3.RX,3.RY,5.IMMED:RRI:16::SB
156 // start-sanitize-tx19
160 do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
164 11001,3.RX,3.RY,5.IMMED:RRI:16::SH
166 // start-sanitize-tx19
170 do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
174 11011,3.RX,3.RY,5.IMMED:RRI:16::SW
176 // start-sanitize-tx19
180 do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
184 11010,3.RX,8.IMMED:RI:16::SWSP
186 // start-sanitize-tx19
190 do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
194 01100,010,8.IMMED:I8:16::SWRASP
196 // start-sanitize-tx19
200 do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
204 01111,3.RX,3.RY,5.IMMED:RRI:16::SD
206 // start-sanitize-tx19
210 do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
214 11111,001,3.RY,5.IMMED:RI64:16::SDSP
216 // start-sanitize-tx19
220 do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
224 11111,010,8.IMMED:I64:16::SDRASP
226 // start-sanitize-tx19
230 do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
234 // ALU Immediate Instructions
237 01101,3.RX,8.IMMED::RI:16::LI
239 // start-sanitize-tx19
243 do_ori (SD_, 0, TRX, IMMED);
247 01000,3.RX,3.RY,0,4.IMMED:RRI_A:16::ADDIU
249 // start-sanitize-tx19
253 do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
257 01001,3.RX,8.IMMED:RI:16::ADDIU8
259 // start-sanitize-tx19
263 do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
267 01100,011,8.IMMED:I8:16::ADJSP
269 // start-sanitize-tx19
273 do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
277 00001,3.RX,8.IMMED:RI:16::ADDIUPC
279 // start-sanitize-tx19
283 unsigned32 temp = (basepc (SD_) & ~3) + (EXTEND8 (IMMED) << 2);
284 GPR[TRX] = EXTEND32 (temp);
288 00000,3.RX,8.IMMED:RI:16::ADDIUSP
290 // start-sanitize-tx19
294 do_addiu (SD_, SPIDX, TRX, EXTEND8 (IMMED) << 2);
298 01000,3.RX,3.RY,1,4.IMMED:RRI_A:16,64::DADDIU
300 // start-sanitize-tx19
304 do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
308 11111,101,3.RY,5.IMMED:RI64:16,64::DADDIU5
310 // start-sanitize-tx19
314 do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
318 11111,011,8.IMMED:I64:16,64::DADJSP
320 // start-sanitize-tx19
324 do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
328 11111,110,3.RY,5.IMMED:RI64:16,64::DADDIUPC
330 // start-sanitize-tx19
334 GPR[TRY] = (basepc (SD_) & ~3) + (EXTEND5 (IMMED) << 2);
338 11111,111,3.RY,5.IMMED:RI64:16,64::DADDIUSP
340 // start-sanitize-tx19
344 do_daddiu (SD_, SPIDX, TRY, EXTEND5 (IMMED) << 2);
348 01010,3.RX,8.IMMED:RI:16::SLTI
350 // start-sanitize-tx19
354 do_slti (SD_, TRX, T8IDX, IMMED);
358 01011,3.RX,8.IMMED:RI:16::SLTIU
360 // start-sanitize-tx19
364 do_sltiu (SD_, TRX, T8IDX, IMMED);
368 11101,3.RX,3.RY,01010:RR:16::CMP
370 // start-sanitize-tx19
374 do_xor (SD_, TRX, TRY, T8IDX);
378 01110,3.RX,8.IMMED:RI:16::CMPI
380 // start-sanitize-tx19
384 do_xori (SD_, TRX, T8IDX, IMMED);
388 // Two/Three Operand, Register-Type
391 11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
393 // start-sanitize-tx19
397 do_addu (SD_, TRX, TRY, TRZ);
401 11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
403 // start-sanitize-tx19
407 do_subu (SD_, TRX, TRY, TRZ);
411 11100,3.RX,3.RY,3.RZ,00:RRR:16,64::DADDU
413 // start-sanitize-tx19
417 do_daddu (SD_, TRX, TRY, TRZ);
421 11100,3.RX,3.RY,3.RZ,10:RRR:16,64::DSUBU
423 // start-sanitize-tx19
427 do_dsubu (SD_, TRX, TRY, TRZ);
431 11101,3.RX,3.RY,00010:RR:16::SLT
433 // start-sanitize-tx19
437 do_slt (SD_, TRX, TRY, T8IDX);
441 11101,3.RX,3.RY,00011:RR:16::SLTU
443 // start-sanitize-tx19
447 do_sltu (SD_, TRX, TRY, T8IDX);
451 11101,3.RX,3.RY,01011:RR:16::NEG
453 // start-sanitize-tx19
457 do_subu (SD_, 0, TRY, TRX);
461 11101,3.RX,3.RY,01100:RR:16::AND
463 // start-sanitize-tx19
467 do_and (SD_, TRX, TRY, TRX);
471 11101,3.RX,3.RY,01101:RR:16::OR
473 // start-sanitize-tx19
477 do_or (SD_, TRX, TRY, TRX);
481 11101,3.RX,3.RY,01110:RR:16::XOR
483 // start-sanitize-tx19
487 do_xor (SD_, TRX, TRY, TRX);
491 11101,3.RX,3.RY,01111:RR:16::NOT
493 // start-sanitize-tx19
497 do_nor (SD_, 0, TRY, TRX);
501 01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
503 // start-sanitize-tx19
507 do_or (SD_, R32, 0, TRY);
511 01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
513 // start-sanitize-tx19
517 do_or (SD_, TRZ, 0, (R32H << 3) | R32L);
521 00110,3.RX,3.RY,3.SHAMT,00:ISHIFT:16::SLL
523 // start-sanitize-tx19
527 do_sll (SD_, TRY, TRX, SHIFT);
531 00110,3.RX,3.RY,3.SHAMT,10:ISHIFT:16::SRL
533 // start-sanitize-tx19
537 do_srl (SD_, TRY, TRX, SHIFT);
541 00110,3.RX,3.RY,3.SHAMT,11:ISHIFT:16::SRA
543 // start-sanitize-tx19
547 do_sra (SD_, TRY, TRX, SHIFT);
551 11101,3.RX,3.RY,00100:RR:16::SLLV
553 // start-sanitize-tx19
557 do_sllv (SD_, TRX, TRY, TRY);
561 11101,3.RX,3.RY,00110:RR:16::SRLV
563 // start-sanitize-tx19
567 do_srlv (SD_, TRX, TRY, TRY);
571 11101,3.RX,3.RY,00111:RR:16::SRAV
573 // start-sanitize-tx19
577 do_srav (SD_, TRX, TRY, TRY);
581 00110,3.RX,3.RY,3.SHAMT,01:ISHIFT:16,64::DSLL
583 // start-sanitize-tx19
587 do_dsll (SD_, 0, TRY, TRX, SHIFT);
591 11101,3.SHAMT,3.RY,01000:RR:16,64::DSRL
593 // start-sanitize-tx19
597 do_dsrl (SD_, 0, TRY, TRY, SHIFT);
601 11101,3.SHAMT,3.RY,10011:RR:16,64::DSRA
603 // start-sanitize-tx19
607 do_dsra (SD_, 0, TRY, TRY, SHIFT);
611 11101,3.RX,3.RY,10100:RR:16,64::DSLLV
613 // start-sanitize-tx19
617 do_dsllv (SD_, TRX, TRY, TRY);
621 11101,3.RX,3.RY,10110:RR:16,64::DSRLV
623 // start-sanitize-tx19
627 do_dsrlv (SD_, TRX, TRY, TRY);
631 11101,3.RX,3.RY,10111:RR:16,64::DSRAV
633 // start-sanitize-tx19
637 do_dsrav (SD_, TRX, TRY, TRY);
641 // Multiply /Divide Instructions
644 11101,3.RX,3.RY,11000:RR:16::MULT
646 // start-sanitize-tx19
650 do_mult (SD_, TRX, TRY, 0);
654 11101,3.RX,3.RY,11001:RR:16::MULTU
656 // start-sanitize-tx19
660 do_multu (SD_, TRX, TRY, 0);
664 11101,3.RX,3.RY,11010:RR:16::DIV
666 // start-sanitize-tx19
670 do_div (SD_, TRX, TRY);
674 11101,3.RX,3.RY,11011:RR:16::DIVU
676 // start-sanitize-tx19
680 do_divu (SD_, TRX, TRY);
684 11101,3.RX,000,10000:RR:16::MFHI
686 // start-sanitize-tx19
694 11101,3.RX,000,10010:RR:16::MFLO
696 // start-sanitize-tx19
704 11101,3.RX,3.RY,11100:RR:16,64::DMULT
706 // start-sanitize-tx19
710 do_dmult (SD_, TRX, TRY);
714 11101,3.RX,3.RY,11101:RR:16,64::DMULTU
716 // start-sanitize-tx19
720 do_dmultu (SD_, TRX, TRY);
724 11101,3.RX,3.RY,11110:RR:16,64::DDIV
726 // start-sanitize-tx19
730 do_ddiv (SD_, TRX, TRY);
734 11101,3.RX,3.RY,11111:RR:16,64::DDIVU
736 // start-sanitize-tx19
740 do_ddivu (SD_, TRX, TRY);
744 // Jump and Branch Instructions
748 // Issue instruction in delay slot of branch
749 :function:::address_word:delayslot16:address_word target
751 instruction_word delay_insn;
752 sim_events_slip (SD, 1);
753 DSPC = CIA; /* save current PC somewhere */
754 CIA = CIA + 2; /* NOTE: mips16 */
755 STATE |= simDELAYSLOT;
756 delay_insn = IMEM16 (CIA); /* NOTE: mips16 */
757 idecode_issue (CPU_, delay_insn, (CIA));
758 STATE &= ~simDELAYSLOT;
762 // compute basepc dependant on us being in a delay slot
763 :function:::address_word:basepc:
765 if (STATE & simDELAYSLOT)
767 return DSPC; /* return saved address of preceeding jmp */
777 00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JAL
779 // start-sanitize-tx19
783 NIA = delayslot16 (SD_,
784 (LSMASKED (NIA, 31, 26)
785 | LSINSERTED (IMM_25_21, 25, 21)
786 | LSINSERTED (IMM_20_16, 20, 16)
787 | LSINSERTED (IMMED_15_0, 15, 0)));
792 00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JALX
794 // start-sanitize-tx19
798 NIA = delayslot16 (SD_,
799 (LSMASKED (NIA, 31, 26)
800 | LSINSERTED (IMM_25_21, 25, 21)
801 | LSINSERTED (IMM_20_16, 20, 16)
802 | LSINSERTED (IMMED_15_0, 15, 0)));
807 11101,3.RX,000,00000:RR:16::JR
809 // start-sanitize-tx19
813 NIA = delayslot16 (SD_, GPR[TRX]);
817 11101,000,001,00000:RR:16::JRRA
819 // start-sanitize-tx19
823 NIA = delayslot16 (SD_, RA);
827 11101,3.RX,010,00000:RR:16::JALR
829 // start-sanitize-tx19
834 NIA = delayslot16 (SD_, GPR[TRX]);
838 00100,3.RX,8.IMMED:RI:16::BEQZ
840 // start-sanitize-tx19
845 NIA = (NIA + (EXTEND8 (IMMED) << 2));
849 00101,3.RX,8.IMMED:RI:16::BNEZ
851 // start-sanitize-tx19
856 NIA = (NIA + (EXTEND8 (IMMED) << 2));
860 01100,000,8.IMMED:I8:16::BTEQZ
862 // start-sanitize-tx19
867 NIA = (NIA + (EXTEND8 (IMMED) << 2));
871 01100,001,8.IMMED:I8:16::BTNEZ
873 // start-sanitize-tx19
878 NIA = (NIA + (EXTEND8 (IMMED) << 2));
882 00010,11.IMMED:I:16::B
884 // start-sanitize-tx19
888 NIA = (NIA + (EXTEND8 (IMMED) << 2));
892 // Special Instructions
895 // See the front of the mips16 doc
896 // -> FIXME need this for most instructions
897 // 11110,eeeeeeeeeee:I:16::EXTEND
899 // // start-sanitize-tx19
901 // // end-sanitize-tx19
904 // 11101,3.RX,3.RY,00101:RR:16::BREAK
906 // // start-sanitize-tx19
908 // // end-sanitize-tx19