sim/mips/m16.igen

   1 // -*- C -*-
   2 //
   3 //
   4 // MIPS Architecture:
   5 //
   6 //        CPU Instruction Set (mips16)
   7 //
   8
   9 // The instructions in this section are ordered according
  10 // to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
  11
  12
  13 // The MIPS16 codes registers in a special way, map from one to the other.
  14 // :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
  15 :compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
  16 :compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
  17 :compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
  18 :compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
  19
  20
  21 // FIXME:
  22 //
  23 // Only the `LB' instruction is implemented.  It should be used as a guideline
  24 // when implementing other instructions.
  25 //
  26 // How to handle delayslots (for jumps) and extended lwpc instructions
  27 // has not been resolved.
  28
  29
  30 011101,26.INSTR_INDEX:NORMAL:32::JALX
  31 *r3900:
  32 // start-sanitize-tx19
  33 *tx19:
  34 // end-sanitize-tx19
  35 /// {
  36 /// }
  37
  38
  39 // Load and Store Instructions
  40
  41
  42 10000,3.RX,3.RY,5.IMMED:RRI:16::LB
  43 *mips16:
  44 // start-sanitize-tx19
  45 *tx19:
  46 // end-sanitize-tx19
  47 {
  48   GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
  49 }
  50
  51
  52 10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
  53 *mips16:
  54 // start-sanitize-tx19
  55 *tx19:
  56 // end-sanitize-tx19
  57 {
  58   GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
  59 }
  60
  61
  62 10001,3.RX,3.RY,5.IMMED:RRI:16::LH
  63 *mips16:
  64 // start-sanitize-tx19
  65 *tx19:
  66 // end-sanitize-tx19
  67 {
  68   GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
  69 }
  70
  71
  72 10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
  73 *mips16:
  74 // start-sanitize-tx19
  75 *tx19:
  76 // end-sanitize-tx19
  77 {
  78   GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
  79 }
  80
  81
  82 10011,3.RX,3.RY,5.IMMED:RRI:16::LW
  83 *mips16:
  84 // start-sanitize-tx19
  85 *tx19:
  86 // end-sanitize-tx19
  87 {
  88   GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
  89 }
  90
  91
  92 10110,3.RX,8.IMMED:RI:16::LWPC
  93 *mips16:
  94 // start-sanitize-tx19
  95 *tx19:
  96 // end-sanitize-tx19
  97 {
  98   GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
  99                                 basepc (SD_) & ~3, IMMED << 2));
 100 }
 101
 102
 103 10010,3.RX,8.IMMED:RI:16::LWSP
 104 *mips16:
 105 // start-sanitize-tx19
 106 *tx19:
 107 // end-sanitize-tx19
 108 {
 109   GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
 110 }
 111
 112
 113 10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
 114 *mips16:
 115 // start-sanitize-tx19
 116 *tx19:
 117 // end-sanitize-tx19
 118 {
 119   GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
 120 }
 121
 122
 123 00111,3.RX,3.RY,5.IMMED:RRI:16,64::LD
 124 *mips16:
 125 // start-sanitize-tx19
 126 *tx19:
 127 // end-sanitize-tx19
 128 {
 129   GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
 130 }
 131
 132
 133 11111,100,3.RY,5.IMMED:RI64:16::LDPC
 134 *mips16:
 135 // start-sanitize-tx19
 136 *tx19:
 137 // end-sanitize-tx19
 138 {
 139   GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
 140                       basepc (SD_) & ~7, IMMED << 3);
 141 }
 142
 143
 144 11111,000,3.RY,5.IMMED:RI64:16::LDSP
 145 *mips16:
 146 // start-sanitize-tx19
 147 *tx19:
 148 // end-sanitize-tx19
 149 {
 150   GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
 151 }
 152
 153
 154 11000,3.RX,3.RY,5.IMMED:RRI:16::SB
 155 *mips16:
 156 // start-sanitize-tx19
 157 *tx19:
 158 // end-sanitize-tx19
 159 {
 160   do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
 161 }
 162
 163
 164 11001,3.RX,3.RY,5.IMMED:RRI:16::SH
 165 *mips16:
 166 // start-sanitize-tx19
 167 *tx19:
 168 // end-sanitize-tx19
 169 {
 170   do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
 171 }
 172
 173
 174 11011,3.RX,3.RY,5.IMMED:RRI:16::SW
 175 *mips16:
 176 // start-sanitize-tx19
 177 *tx19:
 178 // end-sanitize-tx19
 179 {
 180   do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
 181 }
 182
 183
 184 11010,3.RX,8.IMMED:RI:16::SWSP
 185 *mips16:
 186 // start-sanitize-tx19
 187 *tx19:
 188 // end-sanitize-tx19
 189 {
 190   do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
 191 }
 192
 193
 194 01100,010,8.IMMED:I8:16::SWRASP
 195 *mips16:
 196 // start-sanitize-tx19
 197 *tx19:
 198 // end-sanitize-tx19
 199 {
 200   do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
 201 }
 202
 203
 204 01111,3.RX,3.RY,5.IMMED:RRI:16::SD
 205 *mips16:
 206 // start-sanitize-tx19
 207 *tx19:
 208 // end-sanitize-tx19
 209 {
 210   do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
 211 }
 212
 213
 214 11111,001,3.RY,5.IMMED:RI64:16::SDSP
 215 *mips16:
 216 // start-sanitize-tx19
 217 *tx19:
 218 // end-sanitize-tx19
 219 {
 220   do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
 221 }
 222
 223
 224 11111,010,8.IMMED:I64:16::SDRASP
 225 *mips16:
 226 // start-sanitize-tx19
 227 *tx19:
 228 // end-sanitize-tx19
 229 {
 230   do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
 231 }
 232
 233
 234 // ALU Immediate Instructions
 235
 236
 237 01101,3.RX,8.IMMED::RI:16::LI
 238 *mips16:
 239 // start-sanitize-tx19
 240 *tx19:
 241 // end-sanitize-tx19
 242 {
 243   do_ori (SD_, 0, TRX, IMMED);
 244 }
 245
 246
 247 01000,3.RX,3.RY,0,4.IMMED:RRI_A:16::ADDIU
 248 *mips16:
 249 // start-sanitize-tx19
 250 *tx19:
 251 // end-sanitize-tx19
 252 {
 253   do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
 254 }
 255
 256
 257 01001,3.RX,8.IMMED:RI:16::ADDIU8
 258 *mips16:
 259 // start-sanitize-tx19
 260 *tx19:
 261 // end-sanitize-tx19
 262 {
 263   do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
 264 }
 265
 266
 267 01100,011,8.IMMED:I8:16::ADJSP
 268 *mips16:
 269 // start-sanitize-tx19
 270 *tx19:
 271 // end-sanitize-tx19
 272 {
 273   do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
 274 }
 275
 276
 277 00001,3.RX,8.IMMED:RI:16::ADDIUPC
 278 *mips16:
 279 // start-sanitize-tx19
 280 *tx19:
 281 // end-sanitize-tx19
 282 {
 283   unsigned32 temp = (basepc (SD_) & ~3) + (EXTEND8 (IMMED) << 2);
 284   GPR[TRX] = EXTEND32 (temp);
 285 }
 286
 287
 288 00000,3.RX,8.IMMED:RI:16::ADDIUSP
 289 *mips16:
 290 // start-sanitize-tx19
 291 *tx19:
 292 // end-sanitize-tx19
 293 {
 294   do_addiu (SD_, SPIDX, TRX, EXTEND8 (IMMED) << 2);
 295 }
 296
 297
 298 01000,3.RX,3.RY,1,4.IMMED:RRI_A:16,64::DADDIU
 299 *mips16:
 300 // start-sanitize-tx19
 301 *tx19:
 302 // end-sanitize-tx19
 303 {
 304   do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
 305 }
 306
 307
 308 11111,101,3.RY,5.IMMED:RI64:16,64::DADDIU5
 309 *mips16:
 310 // start-sanitize-tx19
 311 *tx19:
 312 // end-sanitize-tx19
 313 {
 314   do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
 315 }
 316
 317
 318 11111,011,8.IMMED:I64:16,64::DADJSP
 319 *mips16:
 320 // start-sanitize-tx19
 321 *tx19:
 322 // end-sanitize-tx19
 323 {
 324   do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
 325 }
 326
 327
 328 11111,110,3.RY,5.IMMED:RI64:16,64::DADDIUPC
 329 *mips16:
 330 // start-sanitize-tx19
 331 *tx19:
 332 // end-sanitize-tx19
 333 {
 334   GPR[TRY] = (basepc (SD_) & ~3) + (EXTEND5 (IMMED) << 2);
 335 }
 336
 337
 338 11111,111,3.RY,5.IMMED:RI64:16,64::DADDIUSP
 339 *mips16:
 340 // start-sanitize-tx19
 341 *tx19:
 342 // end-sanitize-tx19
 343 {
 344   do_daddiu (SD_, SPIDX, TRY, EXTEND5 (IMMED) << 2);
 345 }
 346
 347
 348 01010,3.RX,8.IMMED:RI:16::SLTI
 349 *mips16:
 350 // start-sanitize-tx19
 351 *tx19:
 352 // end-sanitize-tx19
 353 {
 354   do_slti (SD_, TRX, T8IDX, IMMED);
 355 }
 356
 357
 358 01011,3.RX,8.IMMED:RI:16::SLTIU
 359 *mips16:
 360 // start-sanitize-tx19
 361 *tx19:
 362 // end-sanitize-tx19
 363 {
 364   do_sltiu (SD_, TRX, T8IDX, IMMED);
 365 }
 366
 367
 368 11101,3.RX,3.RY,01010:RR:16::CMP
 369 *mips16:
 370 // start-sanitize-tx19
 371 *tx19:
 372 // end-sanitize-tx19
 373 {
 374   do_xor (SD_, TRX, TRY, T8IDX);
 375 }
 376
 377
 378 01110,3.RX,8.IMMED:RI:16::CMPI
 379 *mips16:
 380 // start-sanitize-tx19
 381 *tx19:
 382 // end-sanitize-tx19
 383 {
 384   do_xori (SD_, TRX, T8IDX, IMMED);
 385 }
 386
 387
 388 // Two/Three Operand, Register-Type
 389
 390
 391 11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
 392 *mips16:
 393 // start-sanitize-tx19
 394 *tx19:
 395 // end-sanitize-tx19
 396 {
 397   do_addu (SD_, TRX, TRY, TRZ);
 398 }
 399
 400
 401 11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
 402 *mips16:
 403 // start-sanitize-tx19
 404 *tx19:
 405 // end-sanitize-tx19
 406 {
 407   do_subu (SD_, TRX, TRY, TRZ);
 408 }
 409
 410
 411 11100,3.RX,3.RY,3.RZ,00:RRR:16,64::DADDU
 412 *mips16:
 413 // start-sanitize-tx19
 414 *tx19:
 415 // end-sanitize-tx19
 416 {
 417   do_daddu (SD_, TRX, TRY, TRZ);
 418 }
 419
 420
 421 11100,3.RX,3.RY,3.RZ,10:RRR:16,64::DSUBU
 422 *mips16:
 423 // start-sanitize-tx19
 424 *tx19:
 425 // end-sanitize-tx19
 426 {
 427   do_dsubu (SD_, TRX, TRY, TRZ);
 428 }
 429
 430
 431 11101,3.RX,3.RY,00010:RR:16::SLT
 432 *mips16:
 433 // start-sanitize-tx19
 434 *tx19:
 435 // end-sanitize-tx19
 436 {
 437   do_slt (SD_, TRX, TRY, T8IDX);
 438 }
 439
 440
 441 11101,3.RX,3.RY,00011:RR:16::SLTU
 442 *mips16:
 443 // start-sanitize-tx19
 444 *tx19:
 445 // end-sanitize-tx19
 446 {
 447   do_sltu (SD_, TRX, TRY, T8IDX);
 448 }
 449
 450
 451 11101,3.RX,3.RY,01011:RR:16::NEG
 452 *mips16:
 453 // start-sanitize-tx19
 454 *tx19:
 455 // end-sanitize-tx19
 456 {
 457   do_subu (SD_, 0, TRY, TRX);
 458 }
 459
 460
 461 11101,3.RX,3.RY,01100:RR:16::AND
 462 *mips16:
 463 // start-sanitize-tx19
 464 *tx19:
 465 // end-sanitize-tx19
 466 {
 467   do_and (SD_, TRX, TRY, TRX);
 468 }
 469
 470
 471 11101,3.RX,3.RY,01101:RR:16::OR
 472 *mips16:
 473 // start-sanitize-tx19
 474 *tx19:
 475 // end-sanitize-tx19
 476 {
 477   do_or (SD_, TRX, TRY, TRX);
 478 }
 479
 480
 481 11101,3.RX,3.RY,01110:RR:16::XOR
 482 *mips16:
 483 // start-sanitize-tx19
 484 *tx19:
 485 // end-sanitize-tx19
 486 {
 487   do_xor (SD_, TRX, TRY, TRX);
 488 }
 489
 490
 491 11101,3.RX,3.RY,01111:RR:16::NOT
 492 *mips16:
 493 // start-sanitize-tx19
 494 *tx19:
 495 // end-sanitize-tx19
 496 {
 497   do_nor (SD_, 0, TRY, TRX);
 498 }
 499
 500
 501 01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
 502 *mips16:
 503 // start-sanitize-tx19
 504 *tx19:
 505 // end-sanitize-tx19
 506 {
 507   do_or (SD_, R32, 0, TRY);
 508 }
 509
 510
 511 01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
 512 *mips16:
 513 // start-sanitize-tx19
 514 *tx19:
 515 // end-sanitize-tx19
 516 {
 517   do_or (SD_, TRZ, 0, (R32H << 3) | R32L);
 518 }
 519
 520
 521 00110,3.RX,3.RY,3.SHAMT,00:ISHIFT:16::SLL
 522 *mips16:
 523 // start-sanitize-tx19
 524 *tx19:
 525 // end-sanitize-tx19
 526 {
 527   do_sll (SD_, TRY, TRX, SHIFT);
 528 }
 529
 530
 531 00110,3.RX,3.RY,3.SHAMT,10:ISHIFT:16::SRL
 532 *mips16:
 533 // start-sanitize-tx19
 534 *tx19:
 535 // end-sanitize-tx19
 536 {
 537   do_srl (SD_, TRY, TRX, SHIFT);
 538 }
 539
 540
 541 00110,3.RX,3.RY,3.SHAMT,11:ISHIFT:16::SRA
 542 *mips16:
 543 // start-sanitize-tx19
 544 *tx19:
 545 // end-sanitize-tx19
 546 {
 547   do_sra (SD_, TRY, TRX, SHIFT);
 548 }
 549
 550
 551 11101,3.RX,3.RY,00100:RR:16::SLLV
 552 *mips16:
 553 // start-sanitize-tx19
 554 *tx19:
 555 // end-sanitize-tx19
 556 {
 557   do_sllv (SD_, TRX, TRY, TRY);
 558 }
 559
 560
 561 11101,3.RX,3.RY,00110:RR:16::SRLV
 562 *mips16:
 563 // start-sanitize-tx19
 564 *tx19:
 565 // end-sanitize-tx19
 566 {
 567   do_srlv (SD_, TRX, TRY, TRY);
 568 }
 569
 570
 571 11101,3.RX,3.RY,00111:RR:16::SRAV
 572 *mips16:
 573 // start-sanitize-tx19
 574 *tx19:
 575 // end-sanitize-tx19
 576 {
 577   do_srav (SD_, TRX, TRY, TRY);
 578 }
 579
 580
 581 00110,3.RX,3.RY,3.SHAMT,01:ISHIFT:16,64::DSLL
 582 *mips16:
 583 // start-sanitize-tx19
 584 *tx19:
 585 // end-sanitize-tx19
 586 {
 587   do_dsll (SD_, 0, TRY, TRX, SHIFT);
 588 }
 589
 590
 591 11101,3.SHAMT,3.RY,01000:RR:16,64::DSRL
 592 *mips16:
 593 // start-sanitize-tx19
 594 *tx19:
 595 // end-sanitize-tx19
 596 {
 597   do_dsrl (SD_, 0, TRY, TRY, SHIFT);
 598 }
 599
 600
 601 11101,3.SHAMT,3.RY,10011:RR:16,64::DSRA
 602 *mips16:
 603 // start-sanitize-tx19
 604 *tx19:
 605 // end-sanitize-tx19
 606 {
 607   do_dsra (SD_, 0, TRY, TRY, SHIFT);
 608 }
 609
 610
 611 11101,3.RX,3.RY,10100:RR:16,64::DSLLV
 612 *mips16:
 613 // start-sanitize-tx19
 614 *tx19:
 615 // end-sanitize-tx19
 616 {
 617   do_dsllv (SD_, TRX, TRY, TRY);
 618 }
 619
 620
 621 11101,3.RX,3.RY,10110:RR:16,64::DSRLV
 622 *mips16:
 623 // start-sanitize-tx19
 624 *tx19:
 625 // end-sanitize-tx19
 626 {
 627   do_dsrlv (SD_, TRX, TRY, TRY);
 628 }
 629
 630
 631 11101,3.RX,3.RY,10111:RR:16,64::DSRAV
 632 *mips16:
 633 // start-sanitize-tx19
 634 *tx19:
 635 // end-sanitize-tx19
 636 {
 637   do_dsrav (SD_, TRX, TRY, TRY);
 638 }
 639
 640
 641 // Multiply /Divide Instructions
 642
 643
 644 11101,3.RX,3.RY,11000:RR:16::MULT
 645 *mips16:
 646 // start-sanitize-tx19
 647 *tx19:
 648 // end-sanitize-tx19
 649 {
 650   do_mult (SD_, TRX, TRY, 0);
 651 }
 652
 653
 654 11101,3.RX,3.RY,11001:RR:16::MULTU
 655 *mips16:
 656 // start-sanitize-tx19
 657 *tx19:
 658 // end-sanitize-tx19
 659 {
 660   do_multu (SD_, TRX, TRY, 0);
 661 }
 662
 663
 664 11101,3.RX,3.RY,11010:RR:16::DIV
 665 *mips16:
 666 // start-sanitize-tx19
 667 *tx19:
 668 // end-sanitize-tx19
 669 {
 670   do_div (SD_, TRX, TRY);
 671 }
 672
 673
 674 11101,3.RX,3.RY,11011:RR:16::DIVU
 675 *mips16:
 676 // start-sanitize-tx19
 677 *tx19:
 678 // end-sanitize-tx19
 679 {
 680   do_divu (SD_, TRX, TRY);
 681 }
 682
 683
 684 11101,3.RX,000,10000:RR:16::MFHI
 685 *mips16:
 686 // start-sanitize-tx19
 687 *tx19:
 688 // end-sanitize-tx19
 689 {
 690   do_mfhi (SD_, TRX);
 691 }
 692
 693
 694 11101,3.RX,000,10010:RR:16::MFLO
 695 *mips16:
 696 // start-sanitize-tx19
 697 *tx19:
 698 // end-sanitize-tx19
 699 {
 700   do_mflo (SD_, TRX);
 701 }
 702
 703
 704 11101,3.RX,3.RY,11100:RR:16,64::DMULT
 705 *mips16:
 706 // start-sanitize-tx19
 707 *tx19:
 708 // end-sanitize-tx19
 709 {
 710   do_dmult (SD_, TRX, TRY);
 711 }
 712
 713
 714 11101,3.RX,3.RY,11101:RR:16,64::DMULTU
 715 *mips16:
 716 // start-sanitize-tx19
 717 *tx19:
 718 // end-sanitize-tx19
 719 {
 720   do_dmultu (SD_, TRX, TRY);
 721 }
 722
 723
 724 11101,3.RX,3.RY,11110:RR:16,64::DDIV
 725 *mips16:
 726 // start-sanitize-tx19
 727 *tx19:
 728 // end-sanitize-tx19
 729 {
 730   do_ddiv (SD_, TRX, TRY);
 731 }
 732
 733
 734 11101,3.RX,3.RY,11111:RR:16,64::DDIVU
 735 *mips16:
 736 // start-sanitize-tx19
 737 *tx19:
 738 // end-sanitize-tx19
 739 {
 740   do_ddivu (SD_, TRX, TRY);
 741 }
 742
 743
 744 // Jump and Branch Instructions
 745
 746
 747
 748 // Issue instruction in delay slot of branch
 749 :function:::address_word:delayslot16:address_word target
 750 {
 751   instruction_word delay_insn;
 752   sim_events_slip (SD, 1);
 753   DSPC = CIA; /* save current PC somewhere */
 754   CIA = CIA + 2; /* NOTE: mips16 */
 755   STATE |= simDELAYSLOT;
 756   delay_insn = IMEM16 (CIA); /* NOTE: mips16 */
 757   idecode_issue (CPU_, delay_insn, (CIA));
 758   STATE &= ~simDELAYSLOT;
 759   return target;
 760 }
 761
 762 // compute basepc dependant on us being in a delay slot
 763 :function:::address_word:basepc:
 764 {
 765   if (STATE & simDELAYSLOT)
 766     {
 767       return DSPC; /* return saved address of preceeding jmp */
 768     }
 769   else
 770     {
 771       return CIA;
 772     }
 773 }
 774
 775
 776 // JAL
 777 00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JAL
 778 *mips16:
 779 // start-sanitize-tx19
 780 *tx19:
 781 // end-sanitize-tx19
 782 {
 783   NIA = delayslot16 (SD_,
 784                      (LSMASKED (NIA, 31, 26)
 785                       | LSINSERTED (IMM_25_21, 25, 21)
 786                       | LSINSERTED (IMM_20_16, 20, 16)
 787                       | LSINSERTED (IMMED_15_0, 15, 0)));
 788 }
 789
 790
 791 // JALX
 792 00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:I:16::JALX
 793 *mips16:
 794 // start-sanitize-tx19
 795 *tx19:
 796 // end-sanitize-tx19
 797 {
 798   NIA = delayslot16 (SD_,
 799                      (LSMASKED (NIA, 31, 26)
 800                       | LSINSERTED (IMM_25_21, 25, 21)
 801                       | LSINSERTED (IMM_20_16, 20, 16)
 802                       | LSINSERTED (IMMED_15_0, 15, 0)));
 803   NIA = NIA ^ 1;
 804 }
 805
 806
 807 11101,3.RX,000,00000:RR:16::JR
 808 *mips16:
 809 // start-sanitize-tx19
 810 *tx19:
 811 // end-sanitize-tx19
 812 {
 813   NIA = delayslot16 (SD_, GPR[TRX]);
 814 }
 815
 816
 817 11101,000,001,00000:RR:16::JRRA
 818 *mips16:
 819 // start-sanitize-tx19
 820 *tx19:
 821 // end-sanitize-tx19
 822 {
 823   NIA = delayslot16 (SD_, RA);
 824 }
 825
 826
 827 11101,3.RX,010,00000:RR:16::JALR
 828 *mips16:
 829 // start-sanitize-tx19
 830 *tx19:
 831 // end-sanitize-tx19
 832 {
 833   RA = NIA + 2;
 834   NIA = delayslot16 (SD_, GPR[TRX]);
 835 }
 836
 837
 838 00100,3.RX,8.IMMED:RI:16::BEQZ
 839 *mips16:
 840 // start-sanitize-tx19
 841 *tx19:
 842 // end-sanitize-tx19
 843 {
 844   if (GPR[RX] == 0)
 845     NIA = (NIA + (EXTEND8 (IMMED) << 2));
 846 }
 847
 848
 849 00101,3.RX,8.IMMED:RI:16::BNEZ
 850 *mips16:
 851 // start-sanitize-tx19
 852 *tx19:
 853 // end-sanitize-tx19
 854 {
 855   if (GPR[RX] != 0)
 856     NIA = (NIA + (EXTEND8 (IMMED) << 2));
 857 }
 858
 859
 860 01100,000,8.IMMED:I8:16::BTEQZ
 861 *mips16:
 862 // start-sanitize-tx19
 863 *tx19:
 864 // end-sanitize-tx19
 865 {
 866   if (T8 == 0)
 867     NIA = (NIA + (EXTEND8 (IMMED) << 2));
 868 }
 869
 870
 871 01100,001,8.IMMED:I8:16::BTNEZ
 872 *mips16:
 873 // start-sanitize-tx19
 874 *tx19:
 875 // end-sanitize-tx19
 876 {
 877   if (T8 != 0)
 878     NIA = (NIA + (EXTEND8 (IMMED) << 2));
 879 }
 880
 881
 882 00010,11.IMMED:I:16::B
 883 *mips16:
 884 // start-sanitize-tx19
 885 *tx19:
 886 // end-sanitize-tx19
 887 {
 888   NIA = (NIA + (EXTEND8 (IMMED) << 2));
 889 }
 890
 891
 892 // Special Instructions
 893
 894
 895 // See the front of the mips16 doc
 896 //     -> FIXME need this for most instructions
 897 // 11110,eeeeeeeeeee:I:16::EXTEND
 898 // *mips16:
 899 // // start-sanitize-tx19
 900 // *tx19:
 901 // // end-sanitize-tx19
 902
 903
 904 // 11101,3.RX,3.RY,00101:RR:16::BREAK
 905 // *mips16:
 906 // // start-sanitize-tx19
 907 // *tx19:
 908 // // end-sanitize-tx19