1 // Simulator definition for the micromips ASE.
2 // Copyright (C) 2005-2015 Free Software Foundation, Inc.
3 // Contributed by Imagination Technologies, Ltd.
4 // Written by Andrew Bennett <andrew.bennett@imgtec.com>
6 // This file is part of the MIPS sim.
8 // This program is free software; you can redistribute it and/or modify
9 // it under the terms of the GNU General Public License as published by
10 // the Free Software Foundation; either version 3 of the License, or
11 // (at your option) any later version.
13 // This program is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 // GNU General Public License for more details.
18 // You should have received a copy of the GNU General Public License
19 // along with this program. If not, see <http://www.gnu.org/licenses/>.
21 :compute:::int:TBASE:BASE:((BASE < 2) ? (16 + BASE) \: BASE)
22 :compute:::int:TRD:RD:((RD < 2) ? (16 + RD) \: RD)
23 :compute:::int:TRS:RS:((RS < 2) ? (16 + RS) \: RS)
24 :compute:::int:TRT:RT:((RT < 2) ? (16 + RT) \: RT)
25 :compute:::int:TRT_S:RT_S:((RT_S == 1 ) ? 17 \: RT_S)
26 :compute:::int:ERT:RT:(compute_movep_src_reg (SD_, RT))
27 :compute:::int:ERS:RS:(compute_movep_src_reg (SD_, RS))
29 :compute:::int:IMM_DEC1:IMMEDIATE:((IMMEDIATE == 7) ? -1 \: ((IMMEDIATE == 0) ? 1 \: IMMEDIATE << 2))
30 :compute:::int:IMM_DEC2:IMMEDIATE:((IMMEDIATE < 8) ? IMMEDIATE \: (IMMEDIATE - 16))
31 :compute:::int:IMM_DEC3:IMMEDIATE:((IMMEDIATE < 2) ? IMMEDIATE + 256 \: ((IMMEDIATE < 256) ? IMMEDIATE \: ((IMMEDIATE < 510) ? IMMEDIATE - 512 \: IMMEDIATE - 768)))
32 :compute:::int:IMM_DEC4:IMMEDIATE:(compute_andi16_imm (SD_, IMMEDIATE))
33 :compute:::int:IMM_DEC5:IMMEDIATE:((IMMEDIATE < 15) ? IMMEDIATE \: -1)
34 :compute:::int:IMM_DEC6:IMMEDIATE:((IMMEDIATE < 127) ? IMMEDIATE \: -1)
36 :compute:::int:SHIFT_DEC:SHIFT:((SHIFT == 0) ? 8 \: SHIFT)
38 :compute:::int:IMM_SHIFT_1BIT:IMMEDIATE:(IMMEDIATE << 1)
39 :compute:::int:IMM_SHIFT_2BIT:IMMEDIATE:(IMMEDIATE << 2)
41 :function:::address_word:delayslot_micromips:address_word target, address_word nia, int delayslot_instruction_size
43 instruction_word delay_insn;
44 sim_events_slip (SD, 1);
47 STATE |= simDELAYSLOT;
48 ENGINE_ISSUE_PREFIX_HOOK();
49 micromips_instruction_decode (SD, CPU, CIA, delayslot_instruction_size);
50 STATE &= ~simDELAYSLOT;
54 :function:::address_word:process_isa_mode:address_word target
56 SD->isa_mode = target & 0x1;
57 return (target & (-1 << 1));
60 :function:::address_word:do_micromips_jalr:int rt, int rs, address_word nia, int delayslot_instruction_size
62 GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
63 return (process_isa_mode (SD_,
64 delayslot_micromips (SD_, GPR[rs], nia, delayslot_instruction_size)));
67 :function:::address_word:do_micromips_jal:address_word target, address_word nia, int delayslot_instruction_size
69 RA = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
70 return delayslot_micromips (SD_, target, nia, delayslot_instruction_size);
74 :function:::unsigned32:compute_movep_src_reg:int reg
90 :function:::unsigned32:compute_andi16_imm:int encoded_imm
108 case 14: return 32768;
109 case 15: return 65535;
114 :function:::FP_formats:convert_fmt_micromips:int fmt
118 case 0: return fmt_single;
119 case 1: return fmt_double;
120 case 2: return fmt_ps;
121 default: return fmt_unknown;
125 :function:::FP_formats:convert_fmt_micromips_cvt_d:int fmt
129 case 0: return fmt_single;
130 case 1: return fmt_word;
131 case 2: return fmt_long;
132 default: return fmt_unknown;
137 :function:::FP_formats:convert_fmt_micromips_cvt_s:int fmt
141 case 0: return fmt_double;
142 case 1: return fmt_word;
143 case 2: return fmt_long;
144 default: return fmt_unknown;
149 011011,3.RD,6.IMMEDIATE,1:POOL16E:16::ADDIUR1SP
150 "addiur1sp r<TRD>, <IMMEDIATE>"
154 do_addiu (SD_, SPIDX, TRD, IMMEDIATE << 2);
158 011011,3.RD,3.RS,3.IMMEDIATE,0:POOL16E:16::ADDIUR2
159 "addiur2 r<TRD>, r<TRS>, <IMM_DEC1>"
163 do_addiu (SD_, TRS, TRD, IMM_DEC1);
167 010011,5.RD,4.IMMEDIATE,0:POOL16D:16::ADDIUS5
168 "addius5 r<RD>, <IMM_DEC2>"
172 do_addiu (SD_, RD, RD, IMM_DEC2);
176 010011,9.IMMEDIATE,1:POOL16D:16::ADDIUSP
181 do_addiu (SD_, SPIDX, SPIDX, IMM_DEC3 << 2);
185 000001,3.RD,3.RT,3.RS,0:POOL16A:16::ADDU16
186 "addu16 r<TRD>, r<TRS>, r<TRT>"
190 do_addu (SD_, TRS, TRT, TRD);
194 001011,3.RD,3.RS,4.IMMEDIATE:MICROMIPS:16::ANDI16
195 "andi16 r<TRD>, r<TRS>, <IMM_DEC4>"
199 do_andi (SD_, TRS, TRD, IMM_DEC4);
203 010001,0010,3.RT,3.RS:POOL16C:16::AND16
204 "and16 r<TRT>, r<TRS>"
208 do_and (SD_, TRS, TRT, TRT);
212 110011,10.IMMEDIATE:MICROMIPS:16::B16
217 NIA = delayslot_micromips (SD_, NIA + (EXTEND11 (IMMEDIATE << 1)),
218 NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
222 100011,3.RS,7.IMMEDIATE:MICROMIPS:16::BEQZ16
223 "beqz16 r<TRS>, <IMMEDIATE>"
228 NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
229 NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
233 101011,3.RS,7.IMMEDIATE:MICROMIPS:16::BNEZ16
234 "bnez16 r<TRS>, <IMMEDIATE>"
239 NIA = delayslot_micromips (SD_, NIA + (EXTEND8 (IMMEDIATE << 1)),
240 NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
244 010001,101000,4.CODE:POOL16C:16::BREAK16
249 do_break16 (SD_, instruction_0);
253 010001,01110,5.RS:POOL16C:16::JALR16
258 NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
262 010001,01111,5.RS:POOL16C:16::JALRS16
267 NIA = do_micromips_jalr (SD_, RAIDX, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
271 010001,01100,5.RS:POOL16C:16::JR16
276 NIA = process_isa_mode (SD_,
277 delayslot_micromips (SD_, GPR[RS], NIA, MICROMIPS_DELAYSLOT_SIZE_ANY));
281 010001,11000,5.IMMEDIATE:POOL16C:16::JRADDIUSP
282 "jraddiusp <IMMEDIATE>"
286 address_word temp = RA;
287 do_addiu (SD_, SPIDX, SPIDX, IMMEDIATE << 2);
288 NIA = process_isa_mode (SD_, temp);
292 010001,01101,5.RS:POOL16C:16::JRC
297 NIA = process_isa_mode (SD_, GPR[RS]);
301 000010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LBU16
302 "lbu16 r<TRT>, <IMM_DEC5>(r<TBASE>)"
306 /* LBU can have a negative offset. As the offset argument to do_load is
307 unsigned we need to do the address calcuation before the function call so
308 that the load address has been correctly calculated */
310 GPR[TRT] = do_load (SD_, AccessLength_BYTE, GPR[TBASE] + IMM_DEC5, 0);
314 001010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LHU16
315 "lhu16 r<TRT>, <IMM_SHIFT_1BIT>(r<TBASE>)"
319 GPR[TRT] = do_load (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT);
323 111011,3.RD,7.IMMEDIATE:MICROMIPS:16::LI16
324 "li16 r<TRD>, <IMM_DEC6>"
332 011010,3.RT,3.BASE,4.IMMEDIATE:MICROMIPS:16::LW16
333 "lw16 r<TRT>, <IMM_SHIFT_2BIT>(r<TBASE>)"
337 GPR[TRT] = EXTEND32 (
338 do_load (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT));
341 :%s::::LWMREGS:int lwmregs
346 return "s0, s1, s2, s3, ra";
347 else if (lwmregs == 2)
348 return "s0, s1, s2, ra";
349 else if (lwmregs == 1)
351 else if (lwmregs == 0)
357 010001,0100,2.LWMREGS,4.IMMEDIATE:POOL16C:16::LWM16
358 "lwm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
362 int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
365 for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
366 GPR[16 + reg_offset] = EXTEND32 (
367 do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
369 RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address, reg_offset * 4));
373 011001,3.RT,7.IMMEDIATE:MICROMIPS:16::LWGP
374 "lwgp r<TRT>, <IMM_SHIFT_2BIT>(gp)"
378 GPR[TRT] = EXTEND32 (
379 do_load (SD_, AccessLength_WORD, GPR[28], IMM_SHIFT_2BIT));
383 010010,5.RT,5.IMMEDIATE:MICROMIPS:16::LWSP
384 "lwsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
388 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT));
392 010001,10000,5.RD:POOL16C:16::MFHI16
401 010001,10010,5.RD:POOL16C:16::MFLO16
410 000011,5.RD,5.RS:MICROMIPS:16::MOVE16
412 "move16 r<RD>, r<RS>"
420 :%s::::DESTREGS:int regs
426 case 0: return "a1, a2,";
427 case 1: return "a1, a3,";
428 case 2: return "a2, a3,";
429 case 3: return "a0, s5,";
430 case 4: return "a0, s6,";
431 case 5: return "a0, a1,";
432 case 6: return "a0, a2,";
433 case 7: return "a0, a3,";
438 100001,3.DESTREGS,3.RT,3.RS,0:MICROMIPS:16::MOVEP
439 "movep %s<DESTREGS> r<ERS>, r<ERT>"
447 if (dest == 0 || dest == 1)
454 if (dest == 0 || dest == 6)
456 else if (dest == 1 || dest == 2 || dest == 7)
462 /* assume dest is 5 */
471 010001,0000,3.RT,3.RS:POOL16C:16::NOT16
472 "not16 r<TRT>, r<TRS>"
476 do_nor (SD_, 0, TRS, TRT);
480 010001,0011,3.RT,3.RS:POOL16C:16::OR16
481 "or16 r<TRT>, r<TRS>"
485 do_or (SD_, TRS, TRT, TRT);
489 100010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SB16
490 "sb16 r<TRT_S>, <IMMEDIATE>(r<TBASE>)"
494 do_store (SD_, AccessLength_BYTE, GPR[TBASE], IMMEDIATE, GPR[TRT_S]);
498 010001,101100,4.CODE:POOL16C:16::SDBBP16
503 SignalException (DebugBreakPoint, instruction_0);
507 101010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SH16
508 "sh16 r<TRT_S>, <IMM_SHIFT_1BIT>(r<TBASE>)"
512 do_store (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT, GPR[TRT_S]);
516 001001,3.RD,3.RT,3.SHIFT,0:POOL16B:16::SLL16
517 "sll16 r<TRD>, r<TRT>, <SHIFT_DEC>"
521 do_sll (SD_, TRT, TRD, SHIFT_DEC);
525 001001,3.RD,3.RT,3.SHIFT,1:POOL16B:16::SRL16
526 "srl16 r<TRD>, r<TRT>, <SHIFT_DEC>"
530 do_srl (SD_, TRT, TRD, SHIFT_DEC);
534 000001,3.RD,3.RT,3.RS,1:POOL16A:16::SUBU16
535 "subu16 r<TRD>, r<TRS>, r<TRT>"
539 do_subu (SD_, TRS, TRT, TRD);
543 111010,3.RT_S,3.BASE,4.IMMEDIATE:MICROMIPS:16::SW16
544 "sw16 r<TRT_S>, <IMM_SHIFT_2BIT>(r<TBASE>)"
548 do_store (SD_, AccessLength_WORD, GPR[TBASE], IMM_SHIFT_2BIT, GPR[TRT_S]);
552 110010,5.RT,5.IMMEDIATE:MICROMIPS:16::SWSP
553 "swsp r<RT>, <IMM_SHIFT_2BIT>(sp)"
557 do_store (SD_, AccessLength_WORD, SP, IMM_SHIFT_2BIT, GPR[RT]);
561 010001,0101,2.LWMREGS,4.IMMEDIATE:POOL16C:16::SWM16
562 "swm16 %s<LWMREGS>, <IMM_SHIFT_2BIT>(sp)"
566 int address = GPR[SPIDX] + IMM_SHIFT_2BIT;
569 for (reg_offset = 0; reg_offset <= LWMREGS; reg_offset++)
570 do_store (SD_, AccessLength_WORD, address, reg_offset * 4,
571 GPR[16 + reg_offset]);
573 do_store (SD_, AccessLength_WORD, address, reg_offset * 4, RA);
577 010001,0001,3.RT,3.RS:POOL16C:16::XOR16
578 "xor16 r<TRT>, r<TRS>"
582 do_xor (SD_, TRS, TRT, TRT);
586 000000,5.RT,5.RS,5.RD,00100,010000:POOL32A:32::ADD
587 "add r<RD>, r<RS>, r<RT>"
591 do_add (SD_, RS, RT, RD);
595 000100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDI
596 "addi r<RT>, r<RS>, <IMMEDIATE>"
600 do_addi (SD_, RS, RT, IMMEDIATE);
604 001100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ADDIU
605 "li r<RT>, <IMMEDIATE>":RS==0
606 "addiu r<RT>, r<RS>, <IMMEDIATE>"
610 do_addiu (SD_, RS, RT, IMMEDIATE);
614 011110,3.RS,23.IMMEDIATE:MICROMIPS:32::ADDIUPC
615 "addiupc r<TRS>, <IMM_SHIFT_2BIT>"
619 GPR[TRS] = EXTEND32 ((CIA & ~3) + EXTEND25 (IMM_SHIFT_2BIT));
623 000000,5.RT,5.RS,5.RD,00101,010000:POOL32A:32::ADDU
624 "addu r<RD>, r<RS>, r<RT>"
628 do_addu (SD_, RS, RT, RD);
632 000000,5.RT,5.RS,5.RD,01001,010000:POOL32A:32::AND
633 "and r<RD>, r<RS>, r<RT>"
637 do_and (SD_, RS, RT, RD);
641 110100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ANDI
642 "andi r<RT>, r<RS>, <IMMEDIATE>"
646 do_andi (SD_, RS, RT, IMMEDIATE);
650 010000,1110,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32,f::BC1a
651 "bc1%s<TF> <IMMEDIATE>":CC == 0
652 "bc1%s<TF> <CC>, <IMMEDIATE>"
657 if (GETFCC(CC) == TF)
659 address_word dest = NIA + (EXTEND16 (IMMEDIATE) << 1);
660 NIA = delayslot_micromips (SD_, dest, NIA, MICROMIPS_DELAYSLOT_SIZE_ANY);
665 010000,1010,1.TF,3.CC,00,16.IMMEDIATE:POOL32I:32::BC2a
666 "bc2%s<TF> <CC>, <IMMEDIATE>":CC == 0
667 "bc2%s<TF> <CC>, <IMMEDIATE>"
672 100101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BEQ
673 "b <IMMEDIATE>":RT == 0 && RS == 0
674 "beq r<RS>, r<RT>, <IMMEDIATE>"
678 address_word offset = EXTEND16 (IMMEDIATE) << 1;
679 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
680 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
681 MICROMIPS_DELAYSLOT_SIZE_ANY);
684 010000,00010,5.RS,16.IMMEDIATE:POOL32I:32::BGEZ
685 "bgez r<RS>, <IMMEDIATE>"
689 address_word offset = EXTEND16 (IMMEDIATE) << 1;
690 if ((signed_word) GPR[RS] >= 0)
691 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
692 MICROMIPS_DELAYSLOT_SIZE_ANY);
696 010000,00111,5.RS,16.IMMEDIATE:POOL32I:32::BEQZC
697 "beqzc r<RS>, <IMMEDIATE>"
701 address_word offset = EXTEND16 (IMMEDIATE) << 1;
707 010000,00011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZAL
708 "bal <IMMEDIATE>":RS == 0
709 "bgezal r<RS>, <IMMEDIATE>"
713 address_word offset = EXTEND16 (IMMEDIATE) << 1;
716 RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
717 if ((signed_word) GPR[RS] >= 0)
718 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
719 MICROMIPS_DELAYSLOT_SIZE_32);
723 010000,00110,5.RS,16.IMMEDIATE:POOL32I:32::BGTZ
724 "bgtz r<RS>, <IMMEDIATE>"
728 address_word offset = EXTEND16 (IMMEDIATE) << 1;
729 if ((signed_word) GPR[RS] > 0)
730 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
731 MICROMIPS_DELAYSLOT_SIZE_ANY);
735 010000,10011,5.RS,16.IMMEDIATE:POOL32I:32::BGEZALS
736 "bal <IMMEDIATE>":RS == 0
737 "bgezals r<RS>, <IMMEDIATE>"
741 address_word offset = EXTEND16 (IMMEDIATE) << 1;
744 RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
745 if ((signed_word) GPR[RS] >= 0)
746 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
747 MICROMIPS_DELAYSLOT_SIZE_16);
751 010000,00100,5.RS,16.IMMEDIATE:POOL32I:32::BLEZ
752 "blez r<RS>, <IMMEDIATE>"
756 address_word offset = EXTEND16 (IMMEDIATE) << 1;
757 /* NOTE: The branch occurs AFTER the next instruction has been
759 if ((signed_word) GPR[RS] <= 0)
760 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
761 MICROMIPS_DELAYSLOT_SIZE_ANY);
765 010000,00000,5.RS,16.IMMEDIATE:POOL32I:32::BLTZ
766 "bltz r<RS>, <IMMEDIATE>"
770 address_word offset = EXTEND16 (IMMEDIATE) << 1;
771 if ((signed_word) GPR[RS] < 0)
772 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
773 MICROMIPS_DELAYSLOT_SIZE_ANY);
777 010000,00001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZAL
778 "bltzal r<RS>, <IMMEDIATE>"
782 address_word offset = EXTEND16 (IMMEDIATE) << 1;
785 RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_32) | ISA_MODE_MICROMIPS;
786 /* NOTE: The branch occurs AFTER the next instruction has been
788 if ((signed_word) GPR[RS] < 0)
789 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
790 MICROMIPS_DELAYSLOT_SIZE_32);
793 010000,10001,5.RS,16.IMMEDIATE:POOL32I:32::BLTZALS
794 "bltzals r<RS>, <IMMEDIATE>"
798 address_word offset = EXTEND16 (IMMEDIATE) << 1;
801 RA = (NIA + MICROMIPS_DELAYSLOT_SIZE_16) | ISA_MODE_MICROMIPS;
802 if ((signed_word) GPR[RS] < 0)
803 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
804 MICROMIPS_DELAYSLOT_SIZE_16);
808 101101,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::BNE
809 "bne r<RS>, r<RT>, <IMMEDIATE>"
813 address_word offset = EXTEND16 (IMMEDIATE) << 1;
814 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
815 NIA = delayslot_micromips (SD_, NIA + offset, NIA,
816 MICROMIPS_DELAYSLOT_SIZE_ANY);
820 010000,00101,5.RS,16.IMMEDIATE:POOL32I:32::BNEZC
821 "bnezc r<RS>, <IMMEDIATE>"
825 address_word offset = EXTEND16 (IMMEDIATE) << 1;
826 if ((signed_word) GPR[RS] != 0)
831 000000,20.CODE,000111:POOL32A:32::BREAK
836 do_break (SD_, instruction_0);
840 001000,5.OP,5.BASE,0110,12.IMMEDIATE:POOL32B:32::CACHE
841 "cache <OP>, <IMMEDIATE>(r<BASE>)"
845 address_word base = GPR[BASE];
846 address_word offset = EXTEND12 (IMMEDIATE);
847 address_word vaddr = loadstore_ea (SD_, base, offset);
850 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
852 CacheOp (OP, vaddr, paddr, instruction_0);
856 011000,5.OP,5.BASE,1010011,9.IMMEDIATE:POOL32C:32::CACHEE
857 "cachee <OP>, <IMMEDIATE>(r<BASE>)"
862 010101,5.RT,5.FS,0001000000,111011:POOL32F:32,f::CFC1
867 do_cfc1 (SD_, RT, FS);
871 000000,5.RT,5.IMPL,1100110100,111100:POOL32A:32::CFC2
877 000000,5.RT,5.RS,0100101100,111100:POOL32A:32::CLO
882 do_clo (SD_, RT, RS);
886 000000,5.RT,5.RS,0101101100,111100:POOL32A:32::CLZ
891 do_clz (SD_, RT, RS);
895 000000,23.COFUN,010:POOL32A:32::COP2
901 010101,5.RT,5.FS,0001100000,111011:POOL32F:32,f::CTC1
906 do_ctc1 (SD_, RT, FS);
910 000000,5.RT,5.IMPL,1101110100,111100:POOL32A:32::CTC2
916 000000,00000000001110001101,111100:POOL32A:32::DERET
922 000000,00000,5.RS,0100011101,111100:POOL32A:32::DI
931 000000,5.RT,5.RS,1010101100,111100:POOL32A:32::DIV
936 do_div (SD_, RS, RT);
940 000000,5.RT,5.RS,1011101100,111100:POOL32A:32::DIVU
945 do_divu (SD_, RS, RT);
949 000000,00000000000001100000,000000:POOL32A:32::EHB
955 000000,00000,5.RS,0101011101,111100:POOL32A:32::EI
964 000000,00000000001111001101,111100:POOL32A:32::ERET
971 /* Oops, not yet available */
972 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
984 000000,5.RT,5.RS,5.MSBD,5.LSB,101100:POOL32A:32::EXT
985 "ext r<RT>, r<RS>, <LSB>, <MSBD+1>"
989 do_ext (SD_, RT, RS, LSB, MSBD);
993 000000,5.RT,5.RS,5.MSBD,5.LSB,001100:POOL32A:32::INS
994 "ins r<RT>, r<RS>, <LSB>, <MSBD-LSB+1>"
998 do_ins (SD_, RT, RS, LSB, MSBD);
1002 110101,26.IMMEDIATE:MICROMIPS:32::J
1003 "j <IMM_SHIFT_1BIT>"
1007 address_word region = (NIA & MASK (63, 27));
1008 NIA = delayslot_micromips (SD_, region | (IMM_SHIFT_1BIT), NIA,
1009 MICROMIPS_DELAYSLOT_SIZE_ANY);
1013 111101,26.IMMEDIATE:MICROMIPS:32::JAL
1014 "jal <IMM_SHIFT_1BIT>"
1018 /* NOTE: The region used is that of the delay slot and NOT the
1019 current instruction */
1020 address_word region = (NIA & MASK (63, 27));
1021 NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1022 MICROMIPS_DELAYSLOT_SIZE_32);
1026 011101,26.IMMEDIATE:MICROMIPS:32::JALS
1027 "jals <IMM_SHIFT_1BIT>"
1031 address_word region = (NIA & MASK (63, 27));
1032 NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_1BIT)), NIA,
1033 MICROMIPS_DELAYSLOT_SIZE_16);
1036 000000,5.RT!0,5.RS,0000111100,111100:POOL32A:32::JALR
1037 "jalr r<RS>":RT == 31
1044 NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1047 000000,5.RT,5.RS,0100111100,111100:POOL32A:32::JALRS
1048 "jalrs r<RT>, r<RS>"
1054 NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1058 111100,26.IMMEDIATE:MICROMIPS:32::JALX
1059 "jalx <IMM_SHIFT_2BIT>"
1063 address_word region = (NIA & MASK (63, 26));
1064 NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_2BIT)) | ISA_MODE_MIPS32,
1065 NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1066 SD->isa_mode = ISA_MODE_MIPS32;
1069 000000,00000,5.RS,0000111100,111100:POOL32A:32::JR
1074 NIA = process_isa_mode (SD_,
1075 delayslot_micromips (SD_, GPR[RS], NIA,
1076 MICROMIPS_DELAYSLOT_SIZE_32));
1080 000000,5.RT,5.RS,0001111100,111100:POOL32A:32::JALR.HB
1081 "jalr.hb r<RT>, r<RS>"
1087 NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_32);
1091 000000,5.RT,5.RS,0101111100,111100:POOL32A:32::JALRS.HB
1092 "jalrs.hb r<RT>, r<RS>"
1098 NIA = do_micromips_jalr (SD_, RT, RS, NIA, MICROMIPS_DELAYSLOT_SIZE_16);
1102 000000,00000,5.RS,0111111100,111100:POOL32A:32::JR.HB
1107 NIA = process_isa_mode (SD_,
1108 delayslot_micromips (SD_, GPR[RS], NIA,
1109 MICROMIPS_DELAYSLOT_SIZE_32));
1113 000111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LB
1114 "lb r<RT>, <IMMEDIATE>(r<BASE>)"
1118 do_lb (SD_, RT, IMMEDIATE, BASE);
1122 011000,5.RT,5.BASE,0110100,9.IMMEDIATE:POOL32C:32::LBE
1123 "lbe r<RT>, <IMMEDIATE>(r<BASE>)"
1128 000101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LBU
1129 "lbu r<RT>, <IMMEDIATE>(r<BASE>)"
1133 do_lbu (SD_, RT, IMMEDIATE, BASE);
1137 011000,5.RT,5.BASE,0110000,9.IMMEDIATE:POOL32C:32::LBUE
1138 "lbue r<RT>, <IMMEDIATE>(r<BASE>)"
1143 101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1a
1144 "ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1148 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (IMMEDIATE)));
1152 101111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LDC1b
1153 "ldc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1157 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
1158 EXTEND16 (IMMEDIATE)));
1162 001000,5.RT,5.BASE,0010,12.IMMEDIATE:POOL32B:32::LDC2
1163 "ldc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1168 001111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LH
1169 "lh r<RT>, <IMMEDIATE>(r<BASE>)"
1173 do_lh (SD_, RT, IMMEDIATE, BASE);
1177 011000,5.RT,5.BASE,0110101,9.IMMEDIATE:POOL32C:32::LHE
1178 "lhe r<RT>, <IMMEDIATE>(r<BASE>)"
1183 001101,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LHU
1184 "lhu r<RT>, <IMMEDIATE>(r<BASE>)"
1188 do_lhu (SD_, RT, IMMEDIATE, BASE);
1192 011000,5.RT,5.BASE,0110001,9.IMMEDIATE:POOL32C:32::LHUE
1193 "lhue r<RT>, <IMMEDIATE>(r<BASE>)"
1198 011000,5.RT,5.BASE,0011,12.IMMEDIATE:POOL32C:32::LL
1199 "ll r<RT>, <IMMEDIATE>(r<BASE>)"
1203 do_ll (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1207 011000,5.RT,5.BASE,0110110,9.IMMEDIATE:POOL32C:32::LLE
1208 "lle r<RT>, <IMMEDIATE>(r<BASE>)"
1213 010000,01101,5.RS,16.IMMEDIATE:POOL32I:32::LUI
1214 "lui r<RS>, <IMMEDIATE>"
1218 do_lui (SD_, RS, IMMEDIATE);
1222 010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:32,f::LUXC1
1223 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
1226 do_luxc1_32 (SD_, FD, INDEX, BASE);
1230 010101,5.INDEX,5.BASE,5.FD,00101,001000:POOL32F:64,f::LUXC1
1231 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
1235 check_u64 (SD_, instruction_0);
1236 do_luxc1_64 (SD_, FD, INDEX, BASE);
1240 111111,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::LW
1241 "lw r<RT>, <IMMEDIATE>(r<BASE>)"
1245 do_lw (SD_, RT, IMMEDIATE, BASE);
1249 100111,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::LWC1
1250 "lwc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1254 do_lwc1 (SD_, FT, IMMEDIATE, BASE);
1258 001000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32B:32::LWC2
1259 "lwc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1264 011000,5.RT,5.BASE,0110111,9.IMMEDIATE:POOL32C:32::LWE
1265 "lwe r<RT>, <IMMEDIATE>(r<BASE>)"
1270 011000,5.RT,5.BASE,0110011,9.IMMEDIATE:POOL32C:32::LWEE
1271 "lwee r<RT>, <IMMEDIATE>(r<BASE>)"
1276 011000,5.RT,5.BASE,0000,12.IMMEDIATE:POOL32C:32::LWL
1277 "lwl r<RT>, <IMMEDIATE>(r<BASE>)"
1281 do_lwl (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1285 011000,5.RT,5.BASE,0110010,9.IMMEDIATE:POOL32C:32::LWLE
1286 "lwle r<RT>, <IMMEDIATE>(r<BASE>)"
1290 :%s::::LWM32REGS:int lwmregs
1296 switch(lwmregs & 0xf)
1303 return "s0, s1, ra";
1305 return "s0, s1, s2, ra";
1307 return "s0, s1, s2, s3, ra";
1309 return "s0, s1, s2, s3, s4, ra";
1311 return "s0, s1, s2, s3, s4, s5, ra";
1313 return "s0, s1, s2, s3, s4, s5, s6, ra";
1315 return "s0, s1, s2, s3, s4, s5, s6, s7, ra";
1317 return "s0, s1, s2, s3, s4, s5, s6, s7, s8, ra";
1324 switch(lwmregs & 0xf)
1331 return "s0, s1, s2";
1333 return "s0, s1, s2, s3";
1335 return "s0, s1, s2, s3, s4";
1337 return "s0, s1, s2, s3, s4, s5";
1339 return "s0, s1, s2, s3, s4, s5, s6";
1341 return "s0, s1, s2, s3, s4, s5, s6, s7";
1343 return "s0, s1, s2, s3, s4, s5, s6, s7, s8";
1350 001000,5.LWM32REGS,5.BASE,0101,12.IMMEDIATE:POOL32B:32::LWM32
1351 "lwm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
1355 int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
1357 for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
1359 int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
1360 GPR[dst] = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1364 if (LWM32REGS & 0x10)
1365 RA = EXTEND32 (do_load (SD_, AccessLength_WORD, address_base,
1370 001000,5.RD,5.BASE,0001,12.IMMEDIATE:POOL32B:32::LWP
1371 "lwp r<RD>, <IMMEDIATE>(r<BASE>)"
1375 if (BASE == RD || RD == 31)
1379 do_lw (SD_, RD, EXTEND12 (IMMEDIATE), BASE);
1380 do_lw (SD_, RD + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
1385 011000,5.RT,5.BASE,0001,12.IMMEDIATE:POOL32C:32::LWR
1386 "lwr r<RT>, <IMMEDIATE>(r<BASE>)"
1390 do_lwr (SD_, RT, EXTEND12 (IMMEDIATE), BASE);
1394 011000,5.RT,5.BASE,1110,12.IMMEDIATE:POOL32C:32::LWU
1395 "lwu r<RT>, <IMMEDIATE>(r<BASE>)"
1399 do_lwu (SD_, RT, IMMEDIATE, BASE, instruction_0);
1403 010101,5.INDEX,5.BASE,5.FD,00001,001000:POOL32F:32,f::LWXC1
1404 "lwxc1 f<FD>, <INDEX>(r<BASE>)"
1408 do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0);
1412 000000,5.INDEX,5.BASE,5.RD,00100,011000:POOL32A:32::LWXS
1413 "lwxs r<RD>, r<INDEX>(r<BASE>)"
1417 GPR[RD] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE],
1422 000000,5.RT,5.RS,1100101100,111100:POOL32A:32::MADD
1427 do_madd (SD_, RS, RT);
1431 000000,5.RT,5.RS,1101101100,111100:POOL32A:32::MADDU
1432 "maddu r<RS>, r<RT>"
1436 do_maddu (SD_, RS, RT);
1440 000000,5.RT,5.RS,00,3.SEL,00011,111100:POOL32A:32::MFC0
1441 "mfc0 r<RS>, r<RT>": SEL == 0
1442 "mfc0 r<RS>, r<RT>, <SEL>"
1446 DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RS, SEL);
1450 010101,5.RT,5.FS,0010000000,111011:POOL32F:32,f::MFC1
1455 do_mfc1b (SD_, RT, FS);
1459 000000,5.RT,5.IMPL,0100110100,111100:POOL32A:32::MFC2
1460 "mfc2 r<RT>, <IMPL>"
1465 010101,5.RT,5.FS,0011000000,111011:POOL32F:32,f::MFHC1
1466 "mfhc1 r<RT>, f<FS>"
1470 do_mfhc1 (SD_, RT, FS);
1474 000000,5.RT,5.IMPL,1000110100,111100:POOL32A:32::MFHC2
1475 "mfhc2 r<RT>, <IMPL>"
1480 000000,00000,5.RS,0000110101,111100:POOL32A:32::MFHI
1489 000000,00000,5.RS,0001110101,111100:POOL32A:32::MFLO
1500 010101,5.RT,5.RS,3.CC,0,1.TF,00101,111011:POOL32F:32::MOVtf
1501 "mov%s<TF> r<RT>, r<RS>, CC"
1505 do_movtf (SD_, TF, RT, RS, CC);
1509 000000,5.RT,5.RS,5.RD,00000,011000:POOL32A:32::MOVN
1510 "movn r<RD>, r<RS>, r<RT>"
1514 do_movn (SD_, RD, RS, RT);
1518 000000,5.RT,5.RS,5.RD,00001,011000:POOL32A:32::MOVZ
1519 "movz r<RD>, r<RS>, r<RT>"
1523 do_movz (SD_, RD, RS, RT);
1527 000000,5.RT,5.RS,1110101100,111100:POOL32A:32::MSUB
1532 do_msub (SD_, RS, RT);
1536 000000,5.RT,5.RS,1111101100,111100:POOL32A:32::MSUBU
1537 "msubu r<RS>, r<RT>"
1541 do_msubu (SD_, RS, RT);
1545 000000,5.RT,5.RS,00,3.SEL,01011,111100:POOL32A:32::MTC0
1546 "mtc0 r<RS>, r<RT>": SEL == 0
1547 "mtc0 r<RS>, r<RT>, <SEL>"
1551 DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RS, SEL);
1555 010101,5.RT,5.FS,0010100000,111011:POOL32F:32,f::MTC1
1560 do_mtc1b (SD_, RT, FS);
1564 000000,5.RT,5.IMPL,0101110100,111100:POOL32A:32::MTC2
1565 "mtc2 r<RT>, <IMPL>"
1570 010101,5.RT,5.FS,0011100000,111011:POOL32F:32,f::MTHC1
1571 "mthc1 r<RT>, f<FS>"
1575 do_mthc1 (SD_, RT, FS);
1579 000000,5.RT,5.IMPL,1001110100,111100:POOL32A:32::MTHC2
1580 "mthc2 r<RT>, <IMPL>"
1585 000000,00000,5.RS,0010110101,111100:POOL32A:32::MTHI
1594 000000,00000,5.RS,0011110101,111100:POOL32A:32::MTLO
1603 000000,5.RT,5.RS,5.RD,01000,010000:POOL32A:32::MUL
1604 "mul r<RD>, r<RS>, r<RT>"
1608 do_mul (SD_, RD, RS, RT);
1612 000000,5.RT,5.RS,1000101100,111100:POOL32A:32::MULT
1617 do_mult (SD_, RS, RT, 0);
1621 000000,5.RT,5.RS,1001101100,111100:POOL32A:32::MULTU
1626 do_multu (SD_, RS, RT, 0);
1630 000000,00000000000000000000,000000:POOL32A:32::NOP
1638 000000,5.RT,5.RS,5.RD,01011,010000:POOL32A:32::NOR
1639 "nor r<RD>, r<RS>, r<RT>"
1643 do_nor (SD_, RS, RT, RD);
1647 000000,5.RT,5.RS,5.RD,01010,010000:POOL32A:32::OR
1648 "or r<RD>, r<RS>, r<RT>"
1652 do_or (SD_, RS, RT, RD);
1656 010100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::ORI
1657 "ori r<RT>, r<RS>, <IMMEDIATE>"
1661 do_ori (SD_, RS, RT, IMMEDIATE);
1665 000000,00000000000010100000,000000:POOL32A:32::PAUSE
1671 011000,5.HINT,5.BASE,0010,12.IMMEDIATE:POOL32C:32::PREF
1672 "pref <HINT>, <IMMEDIATE>(r<BASE>)"
1676 do_pref (SD_, HINT, EXTEND12 (IMMEDIATE), BASE);
1680 011000,5.HINT,5.BASE,1010010,9.IMMEDIATE:POOL32C:32::PREFE
1681 "prefe <HINT>, <IMMEDIATE>(r<BASE>)"
1686 010101,5.INDEX,5.BASE,5.HINT,00110,100000:POOL32F:32::PREFX
1687 "prefx <HINT>, r<INDEX>(r<BASE>)"
1691 do_prefx (SD_, HINT, INDEX, BASE);
1694 000000,5.RT,5.RS,0110101100,111100:POOL32A:32::RDHWR
1695 "rdhwr r<RS>, r<RT>"
1699 do_rdhwr (SD_, RT, RS);
1702 000000,5.RT,5.RS,1110000101,111100:POOL32A:32::RDPGPR
1703 "rdpgpr r<RS>, r<RT>"
1708 000000,5.RT,5.RS,5.SHIFT,00011,000000:POOL32A:32::ROTR
1709 "rotr r<RT>, r<RS>, <SHIFT>"
1713 GPR[RT] = do_ror (SD_, GPR[RS], SHIFT);
1717 000000,5.RT,5.RS,5.RD,00011,010000:POOL32A:32::ROTRV
1718 "rotrv r<RD>, r<RT>, r<RS>"
1722 GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
1726 000110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SB
1727 "sb r<RT>, <IMMEDIATE>(r<BASE>)"
1731 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1735 011000,5.RT,5.BASE,1010101,9.IMMEDIATE:POOL32C:32::SBE
1736 "sbe r<RT>, <IMMEDIATE>(r<BASE>)"
1741 011000,5.RT,5.BASE,1011,12.IMMEDIATE:POOL32C:32::SC
1742 "sc r<RT>, <IMMEDIATE>(r<BASE>)"
1746 do_sc (SD_, RT, EXTEND12 (IMMEDIATE), BASE, instruction_0);
1750 011000,5.RT,5.BASE,1010110,9.IMMEDIATE:POOL32C:32::SCE
1751 "sce r<RT>, <IMMEDIATE>(r<BASE>)"
1756 000000,10.CODE,1101101101,111100:POOL32A:32::SDBBP
1761 SignalException (DebugBreakPoint, instruction_0);
1765 101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1a
1766 "sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1769 do_sdc1 (SD_, FT, IMMEDIATE, BASE);
1773 101110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SDC1b
1774 "sdc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1778 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1783 001000,5.RT,5.BASE,1010,12.IMMEDIATE:MICROMIPS:32::SDC2
1784 "sdc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1789 000000,5.RT,5.RS,0010101100,111100:POOL32A:32::SEB
1794 do_seb (SD_, RT, RS);
1798 000000,5.RT,5.RS,0011101100,111100:POOL32A:32::SEH
1803 do_seh (SD_, RT, RS);
1807 001110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SH
1808 "sh r<RT>, <IMMEDIATE>(r<BASE>)"
1812 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (IMMEDIATE),
1817 011000,5.RT,5.BASE,1010100,9.IMMEDIATE:POOL32C:32::SHE
1818 "she r<RT>, <IMMEDIATE>(r<BASE>)"
1823 000000,5.RT!0,5.RS!0,5.SHIFT,00000,000000:POOL32A:32::SLL
1824 "sll r<RT>, r<RS>, <SHIFT>"
1828 do_sll (SD_, RS, RT, SHIFT);
1832 000000,5.RT,5.RS,5.RD,00000,010000:POOL32A:32::SLLV
1833 "sllv r<RD>, r<RT>, r<RS>"
1837 do_sllv (SD_, RS, RT, RD);
1841 000000,5.RT,5.RS,5.RD,01101,010000:POOL32A:32::SLT
1842 "slt r<RD>, r<RS>, r<RT>"
1846 do_slt (SD_, RS, RT, RD);
1850 100100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTI
1851 "slti r<RT>, r<RS>, <IMMEDIATE>"
1855 do_slti (SD_, RS, RT, IMMEDIATE);
1859 101100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::SLTIU
1860 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
1864 do_sltiu (SD_, RS, RT, IMMEDIATE);
1868 000000,5.RT,5.RS,5.RD,01110,010000:POOL32A:32::SLTU
1869 "sltu r<RD>, r<RS>, r<RT>"
1873 do_sltu (SD_, RS, RT, RD);
1877 000000,5.RT,5.RS,5.SHIFT,00010,000000:POOL32A:32::SRA
1878 "sra r<RT>, r<RS>, <SHIFT>"
1882 do_sra (SD_, RS, RT, SHIFT);
1886 000000,5.RT,5.RS,5.RD,00010,010000:POOL32A:32::SRAV
1887 "srav r<RD>, r<RT>, r<RS>"
1891 do_srav (SD_, RS, RT, RD);
1895 000000,5.RT,5.RS,5.SHIFT,00001,000000:POOL32A:32::SRL
1896 "srl r<RT>, r<RS>, <SHIFT>"
1900 do_srl (SD_, RS, RT, SHIFT);
1904 000000,5.RT,5.RS,5.RD,00001,010000:POOL32A:32::SRLV
1905 "srlv r<RD>, r<RT>, r<RS>"
1909 do_srlv (SD_, RS, RT, RD);
1913 000000,00000000000000100000,000000:POOL32A:32::SSNOP
1921 000000,5.RT,5.RS,5.RD,00110,010000:POOL32A:32::SUB
1922 "sub r<RD>, r<RS>, r<RT>"
1926 do_sub (SD_, RD, RS, RT);
1930 000000,5.RT,5.RS,5.RD,00111,010000:POOL32A:32::SUBU
1931 "subu r<RD>, r<RS>, r<RT>"
1935 do_subu (SD_, RS, RT, RD);
1939 010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:32,f::SUXC1
1940 "suxc1 f<FD>, r<INDEX>(r<BASE>)"
1943 do_suxc1_32 (SD_, FD, INDEX, BASE);
1947 010101,5.INDEX,5.BASE,5.FD,00110,001000:POOL32F:64,f::SUXC1
1948 "suxc1 f<FD>, r<INDEX>(r<BASE>)"
1952 check_u64 (SD_, instruction_0);
1953 do_suxc1_64 (SD_, FD, INDEX, BASE);
1956 111110,5.RT,5.BASE,16.IMMEDIATE:MICROMIPS:32::SW
1957 "sw r<RT>, <IMMEDIATE>(r<BASE>)"
1961 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (IMMEDIATE), GPR[RT]);
1965 100110,5.FT,5.BASE,16.IMMEDIATE:MICROMIPS:32,f::SWC1
1966 "swc1 f<FT>, <IMMEDIATE>(r<BASE>)"
1970 do_swc1 (SD_, FT, IMMEDIATE, BASE, instruction_0);
1974 001000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32B:32::SWC2
1975 "swc2 r<RT>, <IMMEDIATE>(r<BASE>)"
1980 011000,5.RT,5.BASE,1010111,9.IMMEDIATE:POOL32C:32::SWE
1981 "swe r<RT>, <IMMEDIATE>(r<BASE>)"
1986 011000,5.RT,5.BASE,1000,12.IMMEDIATE:POOL32C:32::SWL
1987 "swl r<RT>, <IMMEDIATE>(r<BASE>)"
1991 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
1996 011000,5.RT,5.BASE,1010000,9.IMMEDIATE:POOL32C:32::SWLE
1997 "swle r<RT>, <IMMEDIATE>(r<BASE>)"
2002 001000,5.LWM32REGS,5.BASE,1101,12.IMMEDIATE:POOL32B:32::SWM32
2003 "swm32 %s<LWM32REGS>, <IMMEDIATE>(r<BASE>)"
2007 int address_base = GPR[BASE] + EXTEND12 (IMMEDIATE);
2009 for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2011 int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2012 do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset,
2016 if (LWM32REGS & 0x10)
2017 do_store (SD_, AccessLength_WORD, address_base, 4 * reg_offset, RA);
2021 001000,5.RS1,5.BASE,1001,12.IMMEDIATE:POOL32B:32::SWP
2022 "swp r<RS1>, <IMMEDIATE>(r<BASE>)"
2030 do_sw (SD_, RS1, EXTEND12 (IMMEDIATE), BASE);
2031 do_sw (SD_, RS1 + 1, EXTEND12 (IMMEDIATE) + 4, BASE);
2036 011000,5.RT,5.BASE,1001,12.IMMEDIATE:POOL32C:32::SWR
2037 "swr r<RT>, <IMMEDIATE>(r<BASE>)"
2041 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND12 (IMMEDIATE),
2046 011000,5.RT,5.BASE,1010001,9.IMMEDIATE:POOL32C:32::SWRE
2047 "swre r<RT>, <IMMEDIATE>(r<BASE>)"
2052 010101,5.INDEX,5.BASE,5.FD,00010,001000:POOL32F:32,f::SWXC1
2053 "swxc1 f<FD>, r<INDEX>(r<BASE>)"
2057 do_swxc1 (SD_, FD, INDEX, BASE, instruction_0);
2061 000000,00000,5.STYPE,0110101101,111100:POOL32A:32::SYNC
2066 SyncOperation (STYPE);
2070 010000,10000,5.BASE,16.IMMEDIATE:POOL32I:32::SYNCI
2071 "synci <IMMEDIATE>(r<BASE>)"
2077 000000,10.CODE,1000101101,111100:POOL32A:32::SYSCALL
2078 "syscall %#lx<CODE>"
2082 SignalException (SystemCall, instruction_0);
2086 000000,5.RT,5.RS,4.CODE,000000,111100:POOL32A:32::TEQ
2091 do_teq (SD_, RS, RT, instruction_0);
2095 010000,01110,5.RS,16.IMMEDIATE:POOL32I:32::TEQI
2096 "teqi r<RS>, <IMMEDIATE>"
2100 do_teqi (SD_, RS, IMMEDIATE, instruction_0);
2104 000000,5.RT,5.RS,4.CODE,001000,111100:POOL32A:32::TGE
2109 do_tge (SD_, RS, RT, instruction_0);
2113 010000,01001,5.RS,16.IMMEDIATE:POOL32I:32::TGEI
2114 "tgei r<RS>, <IMMEDIATE>"
2118 do_tgei (SD_, RS, IMMEDIATE, instruction_0);
2122 010000,01011,5.RS,16.IMMEDIATE:POOL32I:32::TGEIU
2123 "tgeiu r<RS>, <IMMEDIATE>"
2127 do_tgeiu (SD_, RS, IMMEDIATE, instruction_0);
2131 000000,5.RT,5.RS,4.CODE,010000,111100:POOL32A:32::TGEU
2136 do_tgeu (SD_, RS, RT, instruction_0);
2140 000000,00000000000000001101,111100:POOL32A:32::TLBP
2146 000000,00000000000001001101,111100:POOL32A:32::TLBR
2152 000000,00000000000010001101,111100:POOL32A:32::TLBWI
2158 000000,00000000000011001101,111100:POOL32A:32::TLBWR
2164 000000,5.RT,5.RS,4.CODE,100000,111100:POOL32A:32::TLT
2165 "tlt r<RS>, r<RT>, %#lx<CODE>"
2169 do_tlt (SD_, RS, RT, instruction_0);
2173 010000,01000,5.RS,16.IMMEDIATE:POOL32I:32::TLTI
2174 "tlti r<RS>, <IMMEDIATE>"
2178 do_tlti (SD_, RS, IMMEDIATE, instruction_0);
2182 010000,01010,5.RS,16.IMMEDIATE:POOL32I:32::TLTIU
2183 "tltiu r<RS>, <IMMEDIATE>"
2187 do_tltiu (SD_, RS, IMMEDIATE, instruction_0);
2191 000000,5.RT,5.RS,4.CODE,101000,111100:POOL32A:32::TLTU
2196 do_tltu (SD_, RS, RT, instruction_0);
2200 000000,5.RT,5.RS,4.CODE,110000,111100:POOL32A:32::TNE
2205 do_tne (SD_, RS, RT, instruction_0);
2209 010000,01100,5.RS,16.IMMEDIATE:POOL32I:32::TNEI
2210 "tnei r<RS>, <IMMEDIATE>"
2214 do_tnei (SD_, RS, IMMEDIATE, instruction_0);
2218 000000,10.CODE,1001001101,111100:POOL32A:32::WAIT
2224 000000,5.RT,5.RS,1111000101,111100:POOL32A:32::WRPGPR
2225 "wrpgpr r<RS>, r<RT>"
2230 000000,5.RT,5.RS,0111101100,111100:POOL32A:32::WSBH
2235 do_wsbh (SD_, RT, RS);
2239 000000,5.RT,5.RS,5.RD,01100,010000:POOL32A:32::XOR
2240 "xor r<RD>, r<RS>, r<RT>"
2244 do_xor (SD_, RS, RT, RD);
2248 011100,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:32::XORI
2249 "xori r<RT>, r<RS>, <IMMEDIATE>"
2253 do_xori (SD_, RS, RT, IMMEDIATE);
2257 :%s::::FMT_MICROMIPS:int fmt
2263 case 2: return "ps";
2264 default: return "?";
2269 :%s::::FMT_MICROMIPS_CVT_D:int fmt
2276 default: return "?";
2281 :%s::::FMT_MICROMIPS_CVT_S:int fmt
2288 default: return "?";
2293 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0001101,111011:POOL32F:32,f::ABS.fmt
2294 "abs.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2298 do_abs_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2303 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,110000:POOL32F:32,f::ADD.fmt
2304 "add.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2308 do_add_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2313 010101,5.FT,5.FS,5.FD,5.RS,011001:POOL32F:32,f::ALNV.PS
2314 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
2318 do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0);
2322 010101,5.FT,5.FS,3.CC,0,2.FMT_MICROMIPS!3,4.COND,111100:POOL32F:32,f::C.cond.fmt
2323 "c.%s<COND>.%s<FMT_MICROMIPS> f<FS>, f<FT>":CC == 0
2324 "c.%s<COND>.%s<FMT_MICROMIPS> <CC>, f<FS>, f<FT>"
2328 do_c_cond_fmt (SD_, COND, convert_fmt_micromips (SD_, FMT_MICROMIPS), CC,
2329 FS, FT, instruction_0);
2333 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001100,111011:POOL32F:32,f::CEIL.L.fmt
2334 "ceil.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2338 do_ceil_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS, instruction_0);
2342 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01101100,111011:POOL32F:32,f::CEIL.W.fmt
2343 "ceil.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2347 do_ceil_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS, instruction_0);
2351 010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_D!3,1001101,111011:POOL32F:32,f::CVT.D.fmt
2352 "cvt.d.%s<FMT_MICROMIPS_CVT_D> f<FT>, f<FS>"
2356 do_cvt_d_fmt (SD_, convert_fmt_micromips_cvt_d (SD_, FMT_MICROMIPS_CVT_D),
2357 FT, FS, instruction_0);
2361 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00000100,111011:POOL32F:32,f::CVT.L.fmt
2362 "cvt.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2366 do_cvt_l_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2370 010101,5.FT,5.FS,5.FD,00110,000000:POOL32F:32,f::CVT.PS.S
2371 "cvt.ps.s f<FD>, f<FS>, f<FT>"
2375 do_cvt_ps_s (SD_, FD, FS, FT, instruction_0);
2379 010101,5.FT,5.FS,0,2.FMT_MICROMIPS_CVT_S!3,1101101,111011:POOL32F:32,f::CVT.S.fmt
2380 "cvt.s.%s<FMT_MICROMIPS_CVT_S> f<FT>, f<FS>"
2384 do_cvt_s_fmt (SD_, convert_fmt_micromips_cvt_s (SD_, FMT_MICROMIPS_CVT_S),
2385 FT, FS, instruction_0);
2389 010101,5.FT,5.FS,00,10000100,111011:POOL32F:32,f::CVT.S.PL
2390 "cvt.s.pl f<FT>, f<FS>"
2394 do_cvt_s_pl (SD_, FT, FS, instruction_0);
2398 010101,5.FT,5.FS,00,10100100,111011:POOL32F:32,f::CVT.S.PU
2399 "cvt.s.pu f<FT>, f<FS>"
2403 do_cvt_s_pu (SD_, FT, FS, instruction_0);
2407 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00100100,111011:POOL32F:32,f::CVT.W.fmt
2408 "cvt.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2412 do_cvt_w_fmt (SD_, FMT_MICROMIPS, FT, FS, instruction_0);
2416 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!2!3,11,110000:POOL32F:32,f::DIV.fmt
2417 "div.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2421 do_div_fmt (SD_, FMT_MICROMIPS, FD, FS, FT, instruction_0);
2425 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001100,111011:POOL32F:32,f::FLOOR.L.fmt
2426 "floor.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2430 do_floor_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2434 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101100,111011:POOL32F:32,f::FLOOR.W.fmt
2435 "floor.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2439 do_floor_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2443 010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MADD.fmt
2444 "madd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2448 do_madd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2452 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0000001,111011:POOL32F:32,f::MOV.fmt
2453 "mov.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2457 do_mov_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2462 010101,5.FT,5.FS,3.CC,00,2.FMT_MICROMIPS!3,00,1.TF,100000:POOL32F:32,f::MOVtf.fmt
2463 "mov%s<TF>.%s<FMT_MICROMIPS> f<FT>, f<FS>, <CC>"
2467 do_movtf_fmt (SD_, TF, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT,
2472 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,00,111000:POOL32F:32,f::MOVN.fmt
2473 "movn.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2477 do_movn_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2480 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,111000:POOL32F:32,f::MOVZ.fmt
2481 "movz.%s<FMT_MICROMIPS> f<FD>, f<FS>, r<FT>"
2485 do_movz_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT);
2489 010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,001:POOL32F:32,f::MSUB.fmt
2490 "msub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2494 do_msub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2498 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,10,110000:POOL32F:32,f::MUL.fmt
2499 "mul.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2503 do_mul_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2508 010101,5.FT,5.FS,0,2.FMT_MICROMIPS!3,0101101,111011:POOL32F:32,f::NEG.fmt
2509 "neg.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2513 do_neg_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FT, FS,
2518 010101,5.FT,5.FS,5.FD,5.FR,0,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMADD.fmt
2519 "nmadd.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2523 do_nmadd_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2527 010101,5.FT,5.FS,5.FD,5.FR,1,2.FMT_MICROMIPS!3,010:POOL32F:32,f::NMSUB.fmt
2528 "nmsub.%s<FMT_MICROMIPS> f<FD>, f<FR>, f<FS>, f<FT>"
2532 do_nmsub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FR, FS,
2537 010101,5.FT,5.FS,5.FD,00010,000000:POOL32F:32,f::PLL.PS
2538 "pll.ps f<FD>, f<FS>, f<FT>"
2542 do_pll_ps (SD_, FD, FS, FT, instruction_0);
2546 010101,5.FT,5.FS,5.FD,00011,000000:POOL32F:32,f::PLU.PS
2547 "plu.ps f<FD>, f<FS>, f<FT>"
2551 do_plu_ps (SD_, FD, FS, FT, instruction_0);
2555 010101,5.FT,5.FS,5.FD,00100,000000:POOL32F:32,f::PUL.PS
2556 "pul.ps f<FD>, f<FS>, f<FT>"
2560 do_pul_ps (SD_, FD, FS, FT, instruction_0);
2564 010101,5.FT,5.FS,5.FD,00101,000000:POOL32F:32,f::PUU.PS
2565 "puu.ps f<FD>, f<FS>, f<FT>"
2569 do_puu_ps (SD_, FD, FS, FT, instruction_0);
2573 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,01001000,111011:POOL32F:32,f::RECIP.fmt
2574 "recip.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2578 do_recip_fmt (SD_, FMT_MICROMIPS, FT, FS);
2582 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11001100,111011:POOL32F:32,f::ROUND.L.fmt
2583 "round.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2587 do_round_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2591 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,11101100,111011:POOL32F:32,f::ROUND.W.fmt
2592 "round.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2596 do_round_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2600 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00001000,111011:POOL32F:32,f::RSQRT.fmt
2601 "rsqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2605 do_rsqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2609 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,00101000,111011:POOL32F:32,f::SQRT.fmt
2610 "sqrt.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2614 do_sqrt_fmt (SD_, FMT_MICROMIPS, FT, FS);
2618 010101,5.FT,5.FS,5.FD,0,2.FMT_MICROMIPS!3,01,110000:POOL32F:32,f::SUB.fmt
2619 "sub.%s<FMT_MICROMIPS> f<FD>, f<FS>, f<FT>"
2623 do_sub_fmt (SD_, convert_fmt_micromips (SD_, FMT_MICROMIPS), FD, FS, FT,
2628 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10001100,111011:POOL32F:32,f::TRUNC.L.fmt
2629 "trunc.l.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2633 do_trunc_fmt (SD_, fmt_long, FMT_MICROMIPS, FT, FS);
2637 010101,5.FT,5.FS,0,1.FMT_MICROMIPS,10101100,111011:POOL32F:32,f::TRUNC.W.fmt
2638 "trunc.w.%s<FMT_MICROMIPS> f<FT>, f<FS>"
2642 do_trunc_fmt (SD_, fmt_word, FMT_MICROMIPS, FT, FS);
2645 001000,5.LWM32REGS,5.BASE,0111,12.OFFSET:POOL32B:64::LDM
2646 "ldm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2649 int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2651 for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2653 int dst = (reg_offset == 8) ? 30 : 16 + reg_offset;
2654 GPR[dst] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2658 if (LWM32REGS & 0x10)
2659 RA = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, address_base,
2663 001000,5.RD,5.BASE,0100,12.OFFSET:POOL32B:64::LDP
2664 "ldp r<RD>, <OFFSET>(r<BASE>)"
2667 if (BASE == RD || RD == 31)
2671 check_u64 (SD_, instruction_0);
2672 GPR[RD] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2673 EXTEND12 (OFFSET)));
2674 GPR[RD + 1] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
2675 EXTEND12 (OFFSET) + 8));
2679 001000,5.LWM32REGS,5.BASE,1111,12.OFFSET:POOL32B:64::SDM
2680 "sdm %s<LWM32REGS>, <OFFSET>(r<BASE>)"
2683 int address_base = GPR[BASE] + EXTEND12 (OFFSET);
2685 for (reg_offset = 0; reg_offset < (LWM32REGS & 0xf); reg_offset++)
2687 int src = (reg_offset == 8) ? 30 : 16 + reg_offset;
2688 do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset,
2692 if (LWM32REGS & 0x10)
2693 do_store (SD_, AccessLength_DOUBLEWORD, address_base, 8 * reg_offset, RA);
2696 001000,5.RD,5.BASE,1100,12.OFFSET:POOL32B:64::SDP
2697 "sdp r<RD>, <OFFSET>(r<BASE>)"
2704 check_u64 (SD_, instruction_0);
2705 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
2707 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET) + 8,
2712 010110,5.RT,5.RS,5.RD,00,100010000:POOL32S:64::DADD
2713 "dadd r<RD>, r<RS>, r<RT>"
2716 check_u64 (SD_, instruction_0);
2717 do_dadd (SD_, RD, RS, RT);
2720 010110,5.RT,5.RS,10.IMMEDIATE,011100:POOL32S:64::DADDI
2721 "daddi r<RT>, r<RS>, <IMMEDIATE>"
2724 check_u64 (SD_, instruction_0);
2725 do_daddi (SD_, RT, RS, IMMEDIATE);
2728 010111,5.RT,5.RS,16.IMMEDIATE:MICROMIPS:64::DADDIU
2729 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
2732 check_u64 (SD_, instruction_0);
2733 do_daddiu (SD_, RS, RT, IMMEDIATE);
2736 010110,5.RT,5.RS,5.RD,00,101010000:POOL32S:64::DADDU
2737 "daddu r<RD>, r<RS>, r<RT>"
2740 check_u64 (SD_, instruction_0);
2741 do_daddu (SD_, RS, RT, RD);
2744 010110,5.RT,5.RS,0100101100,111100:POOL32S:64::DCLO
2748 check_u64 (SD_, instruction_0);
2749 do_dclo (SD_, RT, RS);
2752 010110,5.RT,5.RS,0101101100,111100:POOL32S:64::DCLZ
2756 check_u64 (SD_, instruction_0);
2757 do_dclz (SD_, RT, RS);
2760 010110,5.RT,5.RS,1010101100,111100:POOL32S:64::DDIV
2764 check_u64 (SD_, instruction_0);
2765 do_ddiv (SD_, RS, RT);
2768 010110,5.RT,5.RS,1011101100,111100:POOL32S:64::DDIVU
2769 "ddivu r<RS>, r<RT>"
2772 check_u64 (SD_, instruction_0);
2773 do_ddivu (SD_, RS, RT);
2776 010110,5.RT,5.RS,5.SIZE,5.LSB,101100:POOL32S:64::DEXT
2777 "dext r<RT>, r<RS>, <LSB>, <SIZE+1>"
2780 check_u64 (SD_, instruction_0);
2781 do_dext (SD_, RT, RS, LSB, SIZE);
2784 010110,5.RT,5.RS,5.SIZE,5.LSB,100100:POOL32S:64::DEXTM
2785 "dextm r<RT>, r<RS>, <LSB>, <SIZE+33>"
2788 check_u64 (SD_, instruction_0);
2789 do_dextm (SD_, RT, RS, LSB, SIZE);
2792 010110,5.RT,5.RS,5.SIZE,5.LSB,010100:POOL32S:64::DEXTU
2793 "dextu r<RT>, r<RS>, <LSB+32>, <SIZE+1>"
2796 check_u64 (SD_, instruction_0);
2797 do_dextu (SD_, RT, RS, LSB, SIZE);
2800 010110,5.RT,5.RS,5.MSB,5.LSB,001100:POOL32S:64::DINS
2801 "dins r<RT>, r<RS>, <LSB>, <MSB-LSB+1>"
2804 check_u64 (SD_, instruction_0);
2805 do_dins (SD_, RT, RS, LSB, MSB);
2808 010110,5.RT,5.RS,5.MSB,5.LSB,000100:POOL32S:64::DINSM
2809 "dinsm r<RT>, r<RS>, <LSB>, <MSB+32-LSB+1>"
2812 check_u64 (SD_, instruction_0);
2813 do_dinsm (SD_, RT, RS, LSB, MSB);
2816 010110,5.RT,5.RS,5.MSB,5.LSB,110100:POOL32S:64::DINSU
2817 "dinsu r<RT>, r<RS>, <LSB+32>, <MSB-LSB+1>"
2820 check_u64 (SD_, instruction_0);
2821 do_dinsu (SD_, RT, RS, LSB, MSB);
2824 010110,5.RT,5.RS,00,3.SEL,00011,111100:POOL32S:64::DMFC0
2825 "dmfc0 r<RT>, r<RS>": SEL == 0
2826 "dmfc0 r<RT>, r<RS>, <SEL>"
2829 check_u64 (SD_, instruction_0);
2830 DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RS, SEL);
2833 010101,5.RT,5.FS,00,10010000,111011:POOL32F:64::DMFC1
2834 "dmfc1 r<RT>, f<FS>"
2838 check_u64 (SD_, instruction_0);
2839 do_dmfc1b (SD_, RT, FS);
2842 010110,5.RT,5.RS,00,3.SEL,01011,111100:POOL32S:64::DMTC0
2843 "dmtc0 r<RT>, r<RS>": SEL == 0
2844 "dmtc0 r<RT>, r<RS>, <SEL>"
2847 check_u64 (SD_, instruction_0);
2848 DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RS, SEL);
2851 010101,5.RT,5.FS,00,10110000,111011:POOL32F:64::DMTC1
2852 "dmtc1 r<RT>, f<FS>"
2856 check_u64 (SD_, instruction_0);
2857 do_dmtc1b (SD_, RT, FS);
2860 010110,5.RT,5.RS,1000101100,111100:POOL32S:64::DMULT
2861 "dmult r<RS>, r<RT>"
2864 check_u64 (SD_, instruction_0);
2865 do_dmult (SD_, RS, RT, 0);
2868 010110,5.RT,5.RS,1001101100,111100:POOL32S:64::DMULTU
2869 "dmultu r<RS>, r<RT>"
2872 check_u64 (SD_, instruction_0);
2873 do_dmultu (SD_, RS, RT, 0);
2876 010110,5.RT,5.RS,5.SA,00,011000000:POOL32S:64::DROTR
2877 "drotr r<RT>, r<RS>, <SA>"
2880 check_u64 (SD_, instruction_0);
2881 GPR[RT] = do_dror (SD_, GPR[RS], SA);
2884 010110,5.RT,5.RS,5.SA,00,011001000:POOL32S:64::DROTR32
2885 "drotr32 r<RT>, r<RS>, <SA+32>"
2888 check_u64 (SD_, instruction_0);
2889 GPR[RT] = do_dror (SD_, GPR[RS], SA + 32);
2892 010110,5.RT,5.RS,5.RD,00,011010000:POOL32S:64::DROTRV
2893 "drotrv r<RD>, r<RT>, r<RS>"
2896 check_u64 (SD_, instruction_0);
2897 GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
2900 010110,5.RT,5.RS,0111101100,111100:POOL32S:64::DSBH
2904 check_u64 (SD_, instruction_0);
2905 do_dsbh (SD_, RT, RS);
2908 010110,5.RT,5.RS,1111101100,111100:POOL32S:64::DSHD
2912 check_u64 (SD_, instruction_0);
2913 do_dshd (SD_, RS, RT);
2916 010110,5.RT,5.RS,5.SA,00,000000000:POOL32S:64::DSLL
2917 "dsll r<RT>, r<RS>, <SA>"
2920 check_u64 (SD_, instruction_0);
2921 do_dsll (SD_, RS, RT, SA);
2924 010110,5.RT,5.RS,5.SA,00,000001000:POOL32S:64::DSLL32
2925 "dsll32 r<RT>, r<RS>, <SA>"
2928 check_u64 (SD_, instruction_0);
2929 do_dsll32 (SD_, RT, RS, SA);
2932 010110,5.RT,5.RS,5.RD,00,000010000:POOL32S:64::DSLLV
2933 "dsllv r<RD>, r<RT>, r<RS>"
2936 check_u64 (SD_, instruction_0);
2937 do_dsllv (SD_, RS, RT, RD);
2940 010110,5.RT,5.RS,5.SA,00,010000000:POOL32S:64::DSRA
2941 "dsra r<RT>, r<RS>, <SA>"
2944 check_u64 (SD_, instruction_0);
2945 do_dsra (SD_, RS, RT, SA);
2948 010110,5.RT,5.RS,5.SA,00,010001000:POOL32S:64::DSRA32
2949 "dsra32 r<RT>, r<RS>, <SA>"
2952 check_u64 (SD_, instruction_0);
2953 do_dsra32 (SD_, RT, RS, SA);
2956 010110,5.RT,5.RS,5.RD,00,010010000:POOL32S:64::DSRAV
2957 "dsrav r<RD>, r<RS>, r<RT>"
2960 check_u64 (SD_, instruction_0);
2961 do_dsrav (SD_, RS, RT, RD);
2964 010110,5.RT,5.RS,5.SA,00,001000000:POOL32S:64::DSRL
2965 "dsrl r<RT>, r<RS>, <SA>"
2968 check_u64 (SD_, instruction_0);
2969 do_dsrl (SD_, RS, RT, SA);
2972 010110,5.RT,5.RS,5.SA,00,001001000:POOL32S:64::DSRL32
2973 "dsrl32 r<RT>, r<RS>, <SA>"
2976 check_u64 (SD_, instruction_0);
2977 do_dsrl32 (SD_, RT, RS, SA);
2980 010110,5.RT,5.RS,5.RD,00,001010000:POOL32S:64::DSRLV
2981 "dsrlv r<RD>, r<RT>, r<RS>"
2984 check_u64 (SD_, instruction_0);
2985 do_dsrlv (SD_, RS, RT, RD);
2988 010110,5.RT,5.RS,5.RD,00,110001000:POOL32S:64::DSUB
2989 "dsub r<RD>, r<RS>, r<RT>"
2992 check_u64 (SD_, instruction_0);
2993 do_dsub (SD_, RD, RS, RT);
2996 010110,5.RT,5.RS,5.RD,00,111001000:POOL32S:64::DSUBU
2997 "dsubu r<RD>, r<RS>, r<RT>"
3000 check_u64 (SD_, instruction_0);
3001 do_dsubu (SD_, RS, RT, RD);
3004 110111,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::LD
3005 "ld r<RT>, <OFFSET>(r<BASE>)"
3008 check_u64 (SD_, instruction_0);
3009 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3010 EXTEND16 (OFFSET)));
3013 011000,5.RT,5.BASE,0100,12.OFFSET:POOL32C:64::LDL
3014 "ldl r<RT>, <OFFSET>(r<BASE>)"
3017 check_u64 (SD_, instruction_0);
3018 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3019 EXTEND12 (OFFSET), GPR[RT]);
3022 011000,5.RT,5.BASE,0101,12.OFFSET:POOL32C:64::LDR
3023 "ldr r<RT>, <OFFSET>(r<BASE>)"
3026 check_u64 (SD_, instruction_0);
3027 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE],
3028 EXTEND12 (OFFSET), GPR[RT]);
3031 010101,5.INDEX,5.BASE,5.FD,00,011001000:POOL32F:64,f::LDXC1
3032 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3036 check_u64 (SD_, instruction_0);
3037 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3040 011000,5.RT,5.BASE,0111,12.OFFSET:POOL32C:64::LLD
3041 "lld r<RT>, <OFFSET>(r<BASE>)"
3044 check_u64 (SD_, instruction_0);
3045 do_lld (SD_, RT, OFFSET, BASE);
3048 011000,5.RT,5.BASE,1111,12.OFFSET:POOL32C:64::SCD
3049 "scd r<RT>, <OFFSET>(r<BASE>)"
3052 check_u64 (SD_, instruction_0);
3053 do_scd (SD_, RT, OFFSET, BASE);
3056 110110,5.RT,5.BASE,16.OFFSET:MICROMIPS64:64::SD
3057 "sd r<RT>, <OFFSET>(r<BASE>)"
3060 check_u64 (SD_, instruction_0);
3061 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET),
3065 011000,5.RT,5.BASE,1100,12.OFFSET:POOL32C:64::SDL
3066 "sdl r<RT>, <OFFSET>(r<BASE>)"
3069 check_u64 (SD_, instruction_0);
3070 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3074 011000,5.RT,5.BASE,1101,12.OFFSET:POOL32C:64::SDR
3075 "sdr r<RT>, <OFFSET>(r<BASE>)"
3078 check_u64 (SD_, instruction_0);
3079 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND12 (OFFSET),
3083 010101,5.INDEX,5.BASE,5.FD,00,100001000:POOL32F:64,f::SDXC1
3084 "sdxc1 f<FD>, r<INDEX>(r<BASE>)"
3088 check_u64 (SD_, instruction_0);
3089 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX],