3 // In mips.igen, the semantics for many of the instructions were created
4 // using code generated by gencode. Those semantic segments could be
8 // <insn-word> { "+" <insn-word> }
15 // { <insn-mnemonic> }
20 // IGEN config - mips16
21 // :option:16::insn-bit-size:16
22 // :option:16::hi-bit-nr:15
23 :option:16::insn-specifying-widths:true
24 :option:16::gen-delayed-branch:false
26 // IGEN config - mips32/64..
27 // :option:32::insn-bit-size:32
28 // :option:32::hi-bit-nr:31
29 :option:32::insn-specifying-widths:true
30 :option:32::gen-delayed-branch:false
33 // Generate separate simulators for each target
34 // :option:::multi-sim:true
37 // Models known by this simulator
38 :model:::mipsI:mips3000:
39 :model:::mipsII:mips6000:
40 :model:::mipsIII:mips4000:
41 :model:::mipsIV:mips8000:
42 :model:::mips16:mips16:
43 :model:::r3900:mips3900:
44 :model:::vr4100:mips4100:
45 :model:::vr5000:mips5000:
49 // Pseudo instructions known by IGEN
52 SignalException (ReservedInstruction, 0);
56 // Pseudo instructions known by interp.c
57 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
58 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
61 SignalException (ReservedInstruction, instruction_0);
68 // Simulate a 32 bit delayslot instruction
71 :function:::address_word:delayslot32:address_word target
73 instruction_word delay_insn;
74 sim_events_slip (SD, 1);
76 CIA = CIA + 4; /* NOTE not mips16 */
77 STATE |= simDELAYSLOT;
78 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
79 ENGINE_ISSUE_PREFIX_HOOK();
80 idecode_issue (CPU_, delay_insn, (CIA));
81 STATE &= ~simDELAYSLOT;
85 :function:::address_word:nullify_next_insn32:
87 sim_events_slip (SD, 1);
88 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
94 // Check that an access to a HI/LO register meets timing requirements
96 // The following requirements exist:
98 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
99 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
100 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
101 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
104 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
106 if (history->mf.timestamp + 3 > time)
108 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
109 itable[MY_INDEX].name,
111 (long) history->mf.cia);
117 :function:::int:check_mt_hilo:hilo_history *history
118 *mipsI,mipsII,mipsIII,mipsIV:
122 signed64 time = sim_events_time (SD);
123 int ok = check_mf_cycles (SD_, history, time, "MT");
124 history->mt.timestamp = time;
125 history->mt.cia = CIA;
129 :function:::int:check_mt_hilo:hilo_history *history
132 signed64 time = sim_events_time (SD);
133 history->mt.timestamp = time;
134 history->mt.cia = CIA;
139 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
140 *mipsI,mipsII,mipsIII,mipsIV:
145 signed64 time = sim_events_time (SD);
148 && peer->mt.timestamp > history->op.timestamp
149 && history->mt.timestamp < history->op.timestamp
150 && ! (history->mf.timestamp > history->op.timestamp
151 && history->mf.timestamp < peer->mt.timestamp)
152 && ! (peer->mf.timestamp > history->op.timestamp
153 && peer->mf.timestamp < peer->mt.timestamp))
155 /* The peer has been written to since the last OP yet we have
157 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
158 itable[MY_INDEX].name,
160 (long) history->op.cia,
161 (long) peer->mt.cia);
164 history->mf.timestamp = time;
165 history->mf.cia = CIA;
171 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
172 *mipsI,mipsII,mipsIII,mipsIV:
176 signed64 time = sim_events_time (SD);
177 int ok = (check_mf_cycles (SD_, hi, time, "OP")
178 && check_mf_cycles (SD_, lo, time, "OP"));
179 hi->op.timestamp = time;
180 lo->op.timestamp = time;
186 // The r3900 mult and multu insns _can_ be exectuted immediatly after
188 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
191 /* FIXME: could record the fact that a stall occured if we want */
192 signed64 time = sim_events_time (SD);
193 hi->op.timestamp = time;
194 lo->op.timestamp = time;
201 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
202 *mipsI,mipsII,mipsIII,mipsIV:
207 signed64 time = sim_events_time (SD);
208 int ok = (check_mf_cycles (SD_, hi, time, "OP")
209 && check_mf_cycles (SD_, lo, time, "OP"));
210 hi->op.timestamp = time;
211 lo->op.timestamp = time;
222 // Mips Architecture:
224 // CPU Instruction Set (mipsI - mipsIV)
229 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
230 "add r<RD>, r<RS>, r<RT>"
231 *mipsI,mipsII,mipsIII,mipsIV:
236 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
238 ALU32_BEGIN (GPR[RS]);
242 TRACE_ALU_RESULT (GPR[RD]);
247 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
248 "addi r<RT>, r<RS>, IMMEDIATE"
249 *mipsI,mipsII,mipsIII,mipsIV:
254 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
256 ALU32_BEGIN (GPR[RS]);
257 ALU32_ADD (EXTEND16 (IMMEDIATE));
260 TRACE_ALU_RESULT (GPR[RT]);
265 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
267 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
268 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
269 TRACE_ALU_RESULT (GPR[rt]);
272 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
273 "addiu r<RT>, r<RS>, <IMMEDIATE>"
274 *mipsI,mipsII,mipsIII,mipsIV:
279 do_addiu (SD_, RS, RT, IMMEDIATE);
284 :function:::void:do_addu:int rs, int rt, int rd
286 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
287 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
288 TRACE_ALU_RESULT (GPR[rd]);
291 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
292 "addu r<RD>, r<RS>, r<RT>"
293 *mipsI,mipsII,mipsIII,mipsIV:
298 do_addu (SD_, RS, RT, RD);
303 :function:::void:do_and:int rs, int rt, int rd
305 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
306 GPR[rd] = GPR[rs] & GPR[rt];
307 TRACE_ALU_RESULT (GPR[rd]);
310 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
311 "and r<RD>, r<RS>, r<RT>"
312 *mipsI,mipsII,mipsIII,mipsIV:
317 do_and (SD_, RS, RT, RD);
322 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
323 "and r<RT>, r<RS>, <IMMEDIATE>"
324 *mipsI,mipsII,mipsIII,mipsIV:
329 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
330 GPR[RT] = GPR[RS] & IMMEDIATE;
331 TRACE_ALU_RESULT (GPR[RT]);
336 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
337 "beq r<RS>, r<RT>, <OFFSET>"
338 *mipsI,mipsII,mipsIII,mipsIV:
343 address_word offset = EXTEND16 (OFFSET) << 2;
345 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
347 mark_branch_bug (NIA+offset);
348 DELAY_SLOT (NIA + offset);
354 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
355 "beql r<RS>, r<RT>, <OFFSET>"
363 address_word offset = EXTEND16 (OFFSET) << 2;
365 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
367 mark_branch_bug (NIA+offset);
368 DELAY_SLOT (NIA + offset);
371 NULLIFY_NEXT_INSTRUCTION ();
376 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
377 "bgez r<RS>, <OFFSET>"
378 *mipsI,mipsII,mipsIII,mipsIV:
383 address_word offset = EXTEND16 (OFFSET) << 2;
385 if ((signed_word) GPR[RS] >= 0)
387 mark_branch_bug (NIA+offset);
388 DELAY_SLOT (NIA + offset);
394 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
395 "bgezal r<RS>, <OFFSET>"
396 *mipsI,mipsII,mipsIII,mipsIV:
401 address_word offset = EXTEND16 (OFFSET) << 2;
404 if ((signed_word) GPR[RS] >= 0)
406 mark_branch_bug (NIA+offset);
407 DELAY_SLOT (NIA + offset);
413 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
414 "bgezall r<RS>, <OFFSET>"
422 address_word offset = EXTEND16 (OFFSET) << 2;
425 /* NOTE: The branch occurs AFTER the next instruction has been
427 if ((signed_word) GPR[RS] >= 0)
429 mark_branch_bug (NIA+offset);
430 DELAY_SLOT (NIA + offset);
433 NULLIFY_NEXT_INSTRUCTION ();
438 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
439 "bgezl r<RS>, <OFFSET>"
447 address_word offset = EXTEND16 (OFFSET) << 2;
449 if ((signed_word) GPR[RS] >= 0)
451 mark_branch_bug (NIA+offset);
452 DELAY_SLOT (NIA + offset);
455 NULLIFY_NEXT_INSTRUCTION ();
460 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
461 "bgtz r<RS>, <OFFSET>"
462 *mipsI,mipsII,mipsIII,mipsIV:
467 address_word offset = EXTEND16 (OFFSET) << 2;
469 if ((signed_word) GPR[RS] > 0)
471 mark_branch_bug (NIA+offset);
472 DELAY_SLOT (NIA + offset);
478 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
479 "bgtzl r<RS>, <OFFSET>"
487 address_word offset = EXTEND16 (OFFSET) << 2;
489 /* NOTE: The branch occurs AFTER the next instruction has been
491 if ((signed_word) GPR[RS] > 0)
493 mark_branch_bug (NIA+offset);
494 DELAY_SLOT (NIA + offset);
497 NULLIFY_NEXT_INSTRUCTION ();
502 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
503 "blez r<RS>, <OFFSET>"
504 *mipsI,mipsII,mipsIII,mipsIV:
509 address_word offset = EXTEND16 (OFFSET) << 2;
511 /* NOTE: The branch occurs AFTER the next instruction has been
513 if ((signed_word) GPR[RS] <= 0)
515 mark_branch_bug (NIA+offset);
516 DELAY_SLOT (NIA + offset);
522 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
523 "bgezl r<RS>, <OFFSET>"
531 address_word offset = EXTEND16 (OFFSET) << 2;
533 if ((signed_word) GPR[RS] <= 0)
535 mark_branch_bug (NIA+offset);
536 DELAY_SLOT (NIA + offset);
539 NULLIFY_NEXT_INSTRUCTION ();
544 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
545 "bltz r<RS>, <OFFSET>"
546 *mipsI,mipsII,mipsIII,mipsIV:
551 address_word offset = EXTEND16 (OFFSET) << 2;
553 if ((signed_word) GPR[RS] < 0)
555 mark_branch_bug (NIA+offset);
556 DELAY_SLOT (NIA + offset);
562 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
563 "bltzal r<RS>, <OFFSET>"
564 *mipsI,mipsII,mipsIII,mipsIV:
569 address_word offset = EXTEND16 (OFFSET) << 2;
572 /* NOTE: The branch occurs AFTER the next instruction has been
574 if ((signed_word) GPR[RS] < 0)
576 mark_branch_bug (NIA+offset);
577 DELAY_SLOT (NIA + offset);
583 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
584 "bltzall r<RS>, <OFFSET>"
592 address_word offset = EXTEND16 (OFFSET) << 2;
595 if ((signed_word) GPR[RS] < 0)
597 mark_branch_bug (NIA+offset);
598 DELAY_SLOT (NIA + offset);
601 NULLIFY_NEXT_INSTRUCTION ();
606 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
607 "bltzl r<RS>, <OFFSET>"
615 address_word offset = EXTEND16 (OFFSET) << 2;
617 /* NOTE: The branch occurs AFTER the next instruction has been
619 if ((signed_word) GPR[RS] < 0)
621 mark_branch_bug (NIA+offset);
622 DELAY_SLOT (NIA + offset);
625 NULLIFY_NEXT_INSTRUCTION ();
630 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
631 "bne r<RS>, r<RT>, <OFFSET>"
632 *mipsI,mipsII,mipsIII,mipsIV:
637 address_word offset = EXTEND16 (OFFSET) << 2;
639 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
641 mark_branch_bug (NIA+offset);
642 DELAY_SLOT (NIA + offset);
648 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
649 "bnel r<RS>, r<RT>, <OFFSET>"
657 address_word offset = EXTEND16 (OFFSET) << 2;
659 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
661 mark_branch_bug (NIA+offset);
662 DELAY_SLOT (NIA + offset);
665 NULLIFY_NEXT_INSTRUCTION ();
670 000000,20.CODE,001101:SPECIAL:32::BREAK
672 *mipsI,mipsII,mipsIII,mipsIV:
677 /* Check for some break instruction which are reserved for use by the simulator. */
678 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
679 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
680 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
682 sim_engine_halt (SD, CPU, NULL, cia,
683 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
685 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
686 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
688 if (STATE & simDELAYSLOT)
689 PC = cia - 4; /* reference the branch instruction */
692 SignalException(BreakPoint, instruction_0);
697 /* If we get this far, we're not an instruction reserved by the sim. Raise
699 SignalException(BreakPoint, instruction_0);
705 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
706 "dadd r<RD>, r<RS>, r<RT>"
712 /* this check's for overflow */
713 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
715 ALU64_BEGIN (GPR[RS]);
719 TRACE_ALU_RESULT (GPR[RD]);
724 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
725 "daddi r<RT>, r<RS>, <IMMEDIATE>"
731 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
733 ALU64_BEGIN (GPR[RS]);
734 ALU64_ADD (EXTEND16 (IMMEDIATE));
737 TRACE_ALU_RESULT (GPR[RT]);
742 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
744 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
745 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
746 TRACE_ALU_RESULT (GPR[rt]);
749 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
750 "daddu r<RT>, r<RS>, <IMMEDIATE>"
756 do_daddiu (SD_, RS, RT, IMMEDIATE);
761 :function:::void:do_daddu:int rs, int rt, int rd
763 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
764 GPR[rd] = GPR[rs] + GPR[rt];
765 TRACE_ALU_RESULT (GPR[rd]);
768 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
769 "daddu r<RD>, r<RS>, r<RT>"
775 do_daddu (SD_, RS, RT, RD);
780 :function:::void:do_ddiv:int rs, int rt
782 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
783 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
785 signed64 n = GPR[rs];
786 signed64 d = GPR[rt];
791 lo = SIGNED64 (0x8000000000000000);
794 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
796 lo = SIGNED64 (0x8000000000000000);
807 TRACE_ALU_RESULT2 (HI, LO);
810 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
817 do_ddiv (SD_, RS, RT);
822 :function:::void:do_ddivu:int rs, int rt
824 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
825 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
827 unsigned64 n = GPR[rs];
828 unsigned64 d = GPR[rt];
833 lo = SIGNED64 (0x8000000000000000);
844 TRACE_ALU_RESULT2 (HI, LO);
847 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
854 do_ddivu (SD_, RS, RT);
859 :function:::void:do_div:int rs, int rt
861 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
862 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
864 signed32 n = GPR[rs];
865 signed32 d = GPR[rt];
868 LO = EXTEND32 (0x80000000);
871 else if (n == SIGNED32 (0x80000000) && d == -1)
873 LO = EXTEND32 (0x80000000);
878 LO = EXTEND32 (n / d);
879 HI = EXTEND32 (n % d);
882 TRACE_ALU_RESULT2 (HI, LO);
885 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
887 *mipsI,mipsII,mipsIII,mipsIV:
892 do_div (SD_, RS, RT);
897 :function:::void:do_divu:int rs, int rt
899 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
900 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
902 unsigned32 n = GPR[rs];
903 unsigned32 d = GPR[rt];
906 LO = EXTEND32 (0x80000000);
911 LO = EXTEND32 (n / d);
912 HI = EXTEND32 (n % d);
915 TRACE_ALU_RESULT2 (HI, LO);
918 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
920 *mipsI,mipsII,mipsIII,mipsIV:
925 do_divu (SD_, RS, RT);
930 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
940 unsigned64 op1 = GPR[rs];
941 unsigned64 op2 = GPR[rt];
942 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
943 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
944 /* make signed multiply unsigned */
959 /* multiply out the 4 sub products */
960 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
961 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
962 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
963 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
964 /* add the products */
965 mid = ((unsigned64) VH4_8 (m00)
966 + (unsigned64) VL4_8 (m10)
967 + (unsigned64) VL4_8 (m01));
968 lo = U8_4 (mid, m00);
970 + (unsigned64) VH4_8 (mid)
971 + (unsigned64) VH4_8 (m01)
972 + (unsigned64) VH4_8 (m10));
982 /* save the result HI/LO (and a gpr) */
987 TRACE_ALU_RESULT2 (HI, LO);
990 :function:::void:do_dmult:int rs, int rt, int rd
992 do_dmultx (SD_, rs, rt, rd, 1);
995 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1000 do_dmult (SD_, RS, RT, 0);
1003 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1004 "dmult r<RS>, r<RT>":RD == 0
1005 "dmult r<RD>, r<RS>, r<RT>"
1008 do_dmult (SD_, RS, RT, RD);
1013 :function:::void:do_dmultu:int rs, int rt, int rd
1015 do_dmultx (SD_, rs, rt, rd, 0);
1018 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1019 "dmultu r<RS>, r<RT>"
1023 do_dmultu (SD_, RS, RT, 0);
1026 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1027 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1028 "dmultu r<RS>, r<RT>"
1031 do_dmultu (SD_, RS, RT, RD);
1034 :function:::void:do_dsll:int rt, int rd, int shift
1036 GPR[rd] = GPR[rt] << shift;
1039 :function:::void:do_dsllv:int rs, int rt, int rd
1041 int s = MASKED64 (GPR[rs], 5, 0);
1042 GPR[rd] = GPR[rt] << s;
1046 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1047 "dsll r<RD>, r<RT>, <SHIFT>"
1053 do_dsll (SD_, RT, RD, SHIFT);
1057 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1058 "dsll32 r<RD>, r<RT>, <SHIFT>"
1065 GPR[RD] = GPR[RT] << s;
1068 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1069 "dsllv r<RD>, r<RT>, r<RS>"
1075 do_dsllv (SD_, RS, RT, RD);
1078 :function:::void:do_dsra:int rt, int rd, int shift
1080 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1084 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1085 "dsra r<RD>, r<RT>, <SHIFT>"
1091 do_dsra (SD_, RT, RD, SHIFT);
1095 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1096 "dsra32 r<RT>, r<RD>, <SHIFT>"
1103 GPR[RD] = ((signed64) GPR[RT]) >> s;
1107 :function:::void:do_dsrav:int rs, int rt, int rd
1109 int s = MASKED64 (GPR[rs], 5, 0);
1110 TRACE_ALU_INPUT2 (GPR[rt], s);
1111 GPR[rd] = ((signed64) GPR[rt]) >> s;
1112 TRACE_ALU_RESULT (GPR[rd]);
1115 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1116 "dsra32 r<RT>, r<RD>, r<RS>"
1122 do_dsrav (SD_, RS, RT, RD);
1125 :function:::void:do_dsrl:int rt, int rd, int shift
1127 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1131 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1132 "dsrl r<RD>, r<RT>, <SHIFT>"
1138 do_dsrl (SD_, RT, RD, SHIFT);
1142 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1143 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1150 GPR[RD] = (unsigned64) GPR[RT] >> s;
1154 :function:::void:do_dsrlv:int rs, int rt, int rd
1156 int s = MASKED64 (GPR[rs], 5, 0);
1157 GPR[rd] = (unsigned64) GPR[rt] >> s;
1162 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1163 "dsrl32 r<RD>, r<RT>, r<RS>"
1169 do_dsrlv (SD_, RS, RT, RD);
1173 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1174 "dsub r<RD>, r<RS>, r<RT>"
1180 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1182 ALU64_BEGIN (GPR[RS]);
1183 ALU64_SUB (GPR[RT]);
1184 ALU64_END (GPR[RD]);
1186 TRACE_ALU_RESULT (GPR[RD]);
1190 :function:::void:do_dsubu:int rs, int rt, int rd
1192 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1193 GPR[rd] = GPR[rs] - GPR[rt];
1194 TRACE_ALU_RESULT (GPR[rd]);
1197 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1198 "dsubu r<RD>, r<RS>, r<RT>"
1204 do_dsubu (SD_, RS, RT, RD);
1208 000010,26.INSTR_INDEX:NORMAL:32::J
1210 *mipsI,mipsII,mipsIII,mipsIV:
1215 /* NOTE: The region used is that of the delay slot NIA and NOT the
1216 current instruction */
1217 address_word region = (NIA & MASK (63, 28));
1218 DELAY_SLOT (region | (INSTR_INDEX << 2));
1222 000011,26.INSTR_INDEX:NORMAL:32::JAL
1224 *mipsI,mipsII,mipsIII,mipsIV:
1229 /* NOTE: The region used is that of the delay slot and NOT the
1230 current instruction */
1231 address_word region = (NIA & MASK (63, 28));
1233 DELAY_SLOT (region | (INSTR_INDEX << 2));
1236 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1237 "jalr r<RS>":RD == 31
1239 *mipsI,mipsII,mipsIII,mipsIV:
1244 address_word temp = GPR[RS];
1250 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1252 *mipsI,mipsII,mipsIII,mipsIV:
1257 DELAY_SLOT (GPR[RS]);
1261 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1263 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1264 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1265 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1272 vaddr = base + offset;
1273 if ((vaddr & access) != 0)
1275 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1277 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1278 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1279 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1280 byte = ((vaddr & mask) ^ bigendiancpu);
1281 return (memval >> (8 * byte));
1285 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1286 "lb r<RT>, <OFFSET>(r<BASE>)"
1287 *mipsI,mipsII,mipsIII,mipsIV:
1292 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1296 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1297 "lbu r<RT>, <OFFSET>(r<BASE>)"
1298 *mipsI,mipsII,mipsIII,mipsIV:
1303 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1307 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1308 "ld r<RT>, <OFFSET>(r<BASE>)"
1314 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1318 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1319 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1327 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1333 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1334 "ldl r<RT>, <OFFSET>(r<BASE>)"
1340 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1344 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1345 "ldr r<RT>, <OFFSET>(r<BASE>)"
1351 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1355 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1356 "lh r<RT>, <OFFSET>(r<BASE>)"
1357 *mipsI,mipsII,mipsIII,mipsIV:
1362 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1366 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1367 "lhu r<RT>, <OFFSET>(r<BASE>)"
1368 *mipsI,mipsII,mipsIII,mipsIV:
1373 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1377 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1378 "ll r<RT>, <OFFSET>(r<BASE>)"
1385 unsigned32 instruction = instruction_0;
1386 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1387 int destreg = ((instruction >> 16) & 0x0000001F);
1388 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1390 address_word vaddr = ((unsigned64)op1 + offset);
1393 if ((vaddr & 3) != 0)
1395 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1399 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1401 unsigned64 memval = 0;
1402 unsigned64 memval1 = 0;
1403 unsigned64 mask = 0x7;
1404 unsigned int shift = 2;
1405 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1406 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1408 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1409 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1410 byte = ((vaddr & mask) ^ (bigend << shift));
1411 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1419 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1420 "lld r<RT>, <OFFSET>(r<BASE>)"
1426 unsigned32 instruction = instruction_0;
1427 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1428 int destreg = ((instruction >> 16) & 0x0000001F);
1429 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1431 address_word vaddr = ((unsigned64)op1 + offset);
1434 if ((vaddr & 7) != 0)
1436 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1440 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1442 unsigned64 memval = 0;
1443 unsigned64 memval1 = 0;
1444 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1445 GPR[destreg] = memval;
1453 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1454 "lui r<RT>, <IMMEDIATE>"
1455 *mipsI,mipsII,mipsIII,mipsIV:
1460 TRACE_ALU_INPUT1 (IMMEDIATE);
1461 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1462 TRACE_ALU_RESULT (GPR[RT]);
1466 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1467 "lw r<RT>, <OFFSET>(r<BASE>)"
1468 *mipsI,mipsII,mipsIII,mipsIV:
1473 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1477 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1478 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1479 *mipsI,mipsII,mipsIII,mipsIV:
1484 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1488 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1490 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1491 address_word reverseendian = (ReverseEndian ? -1 : 0);
1492 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1501 unsigned_word lhs_mask;
1504 vaddr = base + offset;
1505 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1506 paddr = (paddr ^ (reverseendian & mask));
1507 if (BigEndianMem == 0)
1508 paddr = paddr & ~access;
1510 /* compute where within the word/mem we are */
1511 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1512 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1513 nr_lhs_bits = 8 * byte + 8;
1514 nr_rhs_bits = 8 * access - 8 * byte;
1515 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1517 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1518 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1519 (long) ((unsigned64) paddr >> 32), (long) paddr,
1520 word, byte, nr_lhs_bits, nr_rhs_bits); */
1522 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1525 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1526 temp = (memval << nr_rhs_bits);
1530 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1531 temp = (memval >> nr_lhs_bits);
1533 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1534 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1536 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1537 (long) ((unsigned64) memval >> 32), (long) memval,
1538 (long) ((unsigned64) temp >> 32), (long) temp,
1539 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1540 (long) (rt >> 32), (long) rt); */
1545 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1546 "lwl r<RT>, <OFFSET>(r<BASE>)"
1547 *mipsI,mipsII,mipsIII,mipsIV:
1552 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1556 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1558 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1559 address_word reverseendian = (ReverseEndian ? -1 : 0);
1560 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1567 vaddr = base + offset;
1568 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1569 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1570 paddr = (paddr ^ (reverseendian & mask));
1571 if (BigEndianMem != 0)
1572 paddr = paddr & ~access;
1573 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1574 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1575 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1576 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1577 (long) paddr, byte, (long) paddr, (long) memval); */
1579 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1581 rt |= (memval >> (8 * byte)) & screen;
1587 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1588 "lwr r<RT>, <OFFSET>(r<BASE>)"
1589 *mipsI,mipsII,mipsIII,mipsIV:
1594 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1598 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1599 "lwu r<RT>, <OFFSET>(r<BASE>)"
1605 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1609 :function:::void:do_mfhi:int rd
1611 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1612 TRACE_ALU_INPUT1 (HI);
1614 TRACE_ALU_RESULT (GPR[rd]);
1617 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1619 *mipsI,mipsII,mipsIII,mipsIV:
1629 :function:::void:do_mflo:int rd
1631 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1632 TRACE_ALU_INPUT1 (LO);
1634 TRACE_ALU_RESULT (GPR[rd]);
1637 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1639 *mipsI,mipsII,mipsIII,mipsIV:
1649 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
1650 "movn r<RD>, r<RS>, r<RT>"
1660 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
1661 "movz r<RD>, r<RS>, r<RT>"
1671 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1673 *mipsI,mipsII,mipsIII,mipsIV:
1678 check_mt_hilo (SD_, HIHISTORY);
1684 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
1686 *mipsI,mipsII,mipsIII,mipsIV:
1691 check_mt_hilo (SD_, LOHISTORY);
1697 :function:::void:do_mult:int rs, int rt, int rd
1700 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1701 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1702 prod = (((signed64)(signed32) GPR[rs])
1703 * ((signed64)(signed32) GPR[rt]));
1704 LO = EXTEND32 (VL4_8 (prod));
1705 HI = EXTEND32 (VH4_8 (prod));
1708 TRACE_ALU_RESULT2 (HI, LO);
1711 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
1713 *mipsI,mipsII,mipsIII,mipsIV:
1716 do_mult (SD_, RS, RT, 0);
1720 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
1721 "mult r<RS>, r<RT>":RD == 0
1722 "mult r<RD>, r<RS>, r<RT>"
1726 do_mult (SD_, RS, RT, RD);
1730 :function:::void:do_multu:int rs, int rt, int rd
1733 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1734 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1735 prod = (((unsigned64)(unsigned32) GPR[rs])
1736 * ((unsigned64)(unsigned32) GPR[rt]));
1737 LO = EXTEND32 (VL4_8 (prod));
1738 HI = EXTEND32 (VH4_8 (prod));
1741 TRACE_ALU_RESULT2 (HI, LO);
1744 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
1745 "multu r<RS>, r<RT>"
1746 *mipsI,mipsII,mipsIII,mipsIV:
1749 do_multu (SD_, RS, RT, 0);
1752 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
1753 "multu r<RS>, r<RT>":RD == 0
1754 "multu r<RD>, r<RS>, r<RT>"
1758 do_multu (SD_, RS, RT, RD);
1762 :function:::void:do_nor:int rs, int rt, int rd
1764 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1765 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
1766 TRACE_ALU_RESULT (GPR[rd]);
1769 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
1770 "nor r<RD>, r<RS>, r<RT>"
1771 *mipsI,mipsII,mipsIII,mipsIV:
1776 do_nor (SD_, RS, RT, RD);
1780 :function:::void:do_or:int rs, int rt, int rd
1782 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1783 GPR[rd] = (GPR[rs] | GPR[rt]);
1784 TRACE_ALU_RESULT (GPR[rd]);
1787 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
1788 "or r<RD>, r<RS>, r<RT>"
1789 *mipsI,mipsII,mipsIII,mipsIV:
1794 do_or (SD_, RS, RT, RD);
1799 :function:::void:do_ori:int rs, int rt, unsigned immediate
1801 TRACE_ALU_INPUT2 (GPR[rs], immediate);
1802 GPR[rt] = (GPR[rs] | immediate);
1803 TRACE_ALU_RESULT (GPR[rt]);
1806 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
1807 "ori r<RT>, r<RS>, <IMMEDIATE>"
1808 *mipsI,mipsII,mipsIII,mipsIV:
1813 do_ori (SD_, RS, RT, IMMEDIATE);
1817 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
1821 unsigned32 instruction = instruction_0;
1822 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1823 int hint = ((instruction >> 16) & 0x0000001F);
1824 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1826 address_word vaddr = ((unsigned64)op1 + offset);
1830 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1831 Prefetch(uncached,paddr,vaddr,isDATA,hint);
1836 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
1838 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1839 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1840 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1847 vaddr = base + offset;
1848 if ((vaddr & access) != 0)
1850 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
1852 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
1853 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1854 byte = ((vaddr & mask) ^ bigendiancpu);
1855 memval = (word << (8 * byte));
1856 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
1860 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
1861 "sb r<RT>, <OFFSET>(r<BASE>)"
1862 *mipsI,mipsII,mipsIII,mipsIV:
1867 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1871 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
1872 "sc r<RT>, <OFFSET>(r<BASE>)"
1879 unsigned32 instruction = instruction_0;
1880 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1881 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1882 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1884 address_word vaddr = ((unsigned64)op1 + offset);
1887 if ((vaddr & 3) != 0)
1889 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
1893 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1895 unsigned64 memval = 0;
1896 unsigned64 memval1 = 0;
1897 unsigned64 mask = 0x7;
1899 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
1900 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
1901 memval = ((unsigned64) op2 << (8 * byte));
1904 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
1906 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1913 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
1914 "scd r<RT>, <OFFSET>(r<BASE>)"
1920 unsigned32 instruction = instruction_0;
1921 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1922 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1923 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1925 address_word vaddr = ((unsigned64)op1 + offset);
1928 if ((vaddr & 7) != 0)
1930 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
1934 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1936 unsigned64 memval = 0;
1937 unsigned64 memval1 = 0;
1941 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
1943 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1950 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
1951 "sd r<RT>, <OFFSET>(r<BASE>)"
1957 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1961 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
1962 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1969 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
1973 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
1974 "sdl r<RT>, <OFFSET>(r<BASE>)"
1980 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1984 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
1985 "sdr r<RT>, <OFFSET>(r<BASE>)"
1991 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1995 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
1996 "sh r<RT>, <OFFSET>(r<BASE>)"
1997 *mipsI,mipsII,mipsIII,mipsIV:
2002 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2006 :function:::void:do_sll:int rt, int rd, int shift
2008 unsigned32 temp = (GPR[rt] << shift);
2009 TRACE_ALU_INPUT2 (GPR[rt], shift);
2010 GPR[rd] = EXTEND32 (temp);
2011 TRACE_ALU_RESULT (GPR[rd]);
2014 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2015 "sll r<RD>, r<RT>, <SHIFT>"
2016 *mipsI,mipsII,mipsIII,mipsIV:
2021 do_sll (SD_, RT, RD, SHIFT);
2025 :function:::void:do_sllv:int rs, int rt, int rd
2027 int s = MASKED (GPR[rs], 4, 0);
2028 unsigned32 temp = (GPR[rt] << s);
2029 TRACE_ALU_INPUT2 (GPR[rt], s);
2030 GPR[rd] = EXTEND32 (temp);
2031 TRACE_ALU_RESULT (GPR[rd]);
2034 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2035 "sllv r<RD>, r<RT>, r<RS>"
2036 *mipsI,mipsII,mipsIII,mipsIV:
2041 do_sllv (SD_, RS, RT, RD);
2045 :function:::void:do_slt:int rs, int rt, int rd
2047 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2048 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2049 TRACE_ALU_RESULT (GPR[rd]);
2052 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2053 "slt r<RD>, r<RS>, r<RT>"
2054 *mipsI,mipsII,mipsIII,mipsIV:
2059 do_slt (SD_, RS, RT, RD);
2063 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2065 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2066 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2067 TRACE_ALU_RESULT (GPR[rt]);
2070 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2071 "slti r<RT>, r<RS>, <IMMEDIATE>"
2072 *mipsI,mipsII,mipsIII,mipsIV:
2077 do_slti (SD_, RS, RT, IMMEDIATE);
2081 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2083 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2084 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2085 TRACE_ALU_RESULT (GPR[rt]);
2088 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2089 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2090 *mipsI,mipsII,mipsIII,mipsIV:
2095 do_sltiu (SD_, RS, RT, IMMEDIATE);
2100 :function:::void:do_sltu:int rs, int rt, int rd
2102 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2103 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2104 TRACE_ALU_RESULT (GPR[rd]);
2107 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2108 "sltu r<RD>, r<RS>, r<RT>"
2109 *mipsI,mipsII,mipsIII,mipsIV:
2114 do_sltu (SD_, RS, RT, RD);
2118 :function:::void:do_sra:int rt, int rd, int shift
2120 signed32 temp = (signed32) GPR[rt] >> shift;
2121 TRACE_ALU_INPUT2 (GPR[rt], shift);
2122 GPR[rd] = EXTEND32 (temp);
2123 TRACE_ALU_RESULT (GPR[rd]);
2126 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2127 "sra r<RD>, r<RT>, <SHIFT>"
2128 *mipsI,mipsII,mipsIII,mipsIV:
2133 do_sra (SD_, RT, RD, SHIFT);
2138 :function:::void:do_srav:int rs, int rt, int rd
2140 int s = MASKED (GPR[rs], 4, 0);
2141 signed32 temp = (signed32) GPR[rt] >> s;
2142 TRACE_ALU_INPUT2 (GPR[rt], s);
2143 GPR[rd] = EXTEND32 (temp);
2144 TRACE_ALU_RESULT (GPR[rd]);
2147 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2148 "srav r<RD>, r<RT>, r<RS>"
2149 *mipsI,mipsII,mipsIII,mipsIV:
2154 do_srav (SD_, RS, RT, RD);
2159 :function:::void:do_srl:int rt, int rd, int shift
2161 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2162 TRACE_ALU_INPUT2 (GPR[rt], shift);
2163 GPR[rd] = EXTEND32 (temp);
2164 TRACE_ALU_RESULT (GPR[rd]);
2167 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2168 "srl r<RD>, r<RT>, <SHIFT>"
2169 *mipsI,mipsII,mipsIII,mipsIV:
2174 do_srl (SD_, RT, RD, SHIFT);
2178 :function:::void:do_srlv:int rs, int rt, int rd
2180 int s = MASKED (GPR[rs], 4, 0);
2181 unsigned32 temp = (unsigned32) GPR[rt] >> s;
2182 TRACE_ALU_INPUT2 (GPR[rt], s);
2183 GPR[rd] = EXTEND32 (temp);
2184 TRACE_ALU_RESULT (GPR[rd]);
2187 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2188 "srlv r<RD>, r<RT>, r<RS>"
2189 *mipsI,mipsII,mipsIII,mipsIV:
2194 do_srlv (SD_, RS, RT, RD);
2198 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2199 "sub r<RD>, r<RS>, r<RT>"
2200 *mipsI,mipsII,mipsIII,mipsIV:
2205 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2207 ALU32_BEGIN (GPR[RS]);
2208 ALU32_SUB (GPR[RT]);
2209 ALU32_END (GPR[RD]);
2211 TRACE_ALU_RESULT (GPR[RD]);
2215 :function:::void:do_subu:int rs, int rt, int rd
2217 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2218 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2219 TRACE_ALU_RESULT (GPR[rd]);
2222 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2223 "subu r<RD>, r<RS>, r<RT>"
2224 *mipsI,mipsII,mipsIII,mipsIV:
2229 do_subu (SD_, RS, RT, RD);
2233 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2234 "sw r<RT>, <OFFSET>(r<BASE>)"
2235 *mipsI,mipsII,mipsIII,mipsIV:
2240 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2244 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2245 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2246 *mipsI,mipsII,mipsIII,mipsIV:
2251 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2256 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2258 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2259 address_word reverseendian = (ReverseEndian ? -1 : 0);
2260 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2270 vaddr = base + offset;
2271 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2272 paddr = (paddr ^ (reverseendian & mask));
2273 if (BigEndianMem == 0)
2274 paddr = paddr & ~access;
2276 /* compute where within the word/mem we are */
2277 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2278 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2279 nr_lhs_bits = 8 * byte + 8;
2280 nr_rhs_bits = 8 * access - 8 * byte;
2281 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2282 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2283 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2284 (long) ((unsigned64) paddr >> 32), (long) paddr,
2285 word, byte, nr_lhs_bits, nr_rhs_bits); */
2289 memval = (rt >> nr_rhs_bits);
2293 memval = (rt << nr_lhs_bits);
2295 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2296 (long) ((unsigned64) rt >> 32), (long) rt,
2297 (long) ((unsigned64) memval >> 32), (long) memval); */
2298 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2302 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2303 "swl r<RT>, <OFFSET>(r<BASE>)"
2304 *mipsI,mipsII,mipsIII,mipsIV:
2309 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2313 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2315 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2316 address_word reverseendian = (ReverseEndian ? -1 : 0);
2317 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2324 vaddr = base + offset;
2325 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2326 paddr = (paddr ^ (reverseendian & mask));
2327 if (BigEndianMem != 0)
2329 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2330 memval = (rt << (byte * 8));
2331 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2334 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2335 "swr r<RT>, <OFFSET>(r<BASE>)"
2336 *mipsI,mipsII,mipsIII,mipsIV:
2341 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2345 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2355 SyncOperation (STYPE);
2359 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2361 *mipsI,mipsII,mipsIII,mipsIV:
2366 SignalException(SystemCall, instruction_0);
2370 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2378 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2379 SignalException(Trap, instruction_0);
2383 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2384 "teqi r<RS>, <IMMEDIATE>"
2391 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2392 SignalException(Trap, instruction_0);
2396 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2404 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2405 SignalException(Trap, instruction_0);
2409 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2410 "tgei r<RS>, <IMMEDIATE>"
2417 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2418 SignalException(Trap, instruction_0);
2422 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2423 "tgeiu r<RS>, <IMMEDIATE>"
2430 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2431 SignalException(Trap, instruction_0);
2435 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2443 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2444 SignalException(Trap, instruction_0);
2448 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2456 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2457 SignalException(Trap, instruction_0);
2461 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2462 "tlti r<RS>, <IMMEDIATE>"
2469 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2470 SignalException(Trap, instruction_0);
2474 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2475 "tltiu r<RS>, <IMMEDIATE>"
2482 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2483 SignalException(Trap, instruction_0);
2487 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2495 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2496 SignalException(Trap, instruction_0);
2500 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2508 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2509 SignalException(Trap, instruction_0);
2513 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2514 "tne r<RS>, <IMMEDIATE>"
2521 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2522 SignalException(Trap, instruction_0);
2526 :function:::void:do_xor:int rs, int rt, int rd
2528 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2529 GPR[rd] = GPR[rs] ^ GPR[rt];
2530 TRACE_ALU_RESULT (GPR[rd]);
2533 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
2534 "xor r<RD>, r<RS>, r<RT>"
2535 *mipsI,mipsII,mipsIII,mipsIV:
2540 do_xor (SD_, RS, RT, RD);
2544 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
2546 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2547 GPR[rt] = GPR[rs] ^ immediate;
2548 TRACE_ALU_RESULT (GPR[rt]);
2551 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2552 "xori r<RT>, r<RS>, <IMMEDIATE>"
2553 *mipsI,mipsII,mipsIII,mipsIV:
2558 do_xori (SD_, RS, RT, IMMEDIATE);
2563 // MIPS Architecture:
2565 // FPU Instruction Set (COP1 & COP1X)
2573 case fmt_single: return "s";
2574 case fmt_double: return "d";
2575 case fmt_word: return "w";
2576 case fmt_long: return "l";
2577 default: return "?";
2587 default: return "?";
2607 :%s::::COND:int cond
2611 case 00: return "f";
2612 case 01: return "un";
2613 case 02: return "eq";
2614 case 03: return "ueq";
2615 case 04: return "olt";
2616 case 05: return "ult";
2617 case 06: return "ole";
2618 case 07: return "ule";
2619 case 010: return "sf";
2620 case 011: return "ngle";
2621 case 012: return "seq";
2622 case 013: return "ngl";
2623 case 014: return "lt";
2624 case 015: return "nge";
2625 case 016: return "le";
2626 case 017: return "ngt";
2627 default: return "?";
2632 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
2633 "abs.%s<FMT> f<FD>, f<FS>"
2634 *mipsI,mipsII,mipsIII,mipsIV:
2639 unsigned32 instruction = instruction_0;
2640 int destreg = ((instruction >> 6) & 0x0000001F);
2641 int fs = ((instruction >> 11) & 0x0000001F);
2642 int format = ((instruction >> 21) & 0x00000007);
2644 if ((format != fmt_single) && (format != fmt_double))
2645 SignalException(ReservedInstruction,instruction);
2647 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
2653 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
2654 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
2655 *mipsI,mipsII,mipsIII,mipsIV:
2660 unsigned32 instruction = instruction_0;
2661 int destreg = ((instruction >> 6) & 0x0000001F);
2662 int fs = ((instruction >> 11) & 0x0000001F);
2663 int ft = ((instruction >> 16) & 0x0000001F);
2664 int format = ((instruction >> 21) & 0x00000007);
2666 if ((format != fmt_single) && (format != fmt_double))
2667 SignalException(ReservedInstruction, instruction);
2669 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
2680 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
2681 "bc1%s<TF>%s<ND> <OFFSET>"
2682 *mipsI,mipsII,mipsIII:
2684 check_branch_bug ();
2685 TRACE_BRANCH_INPUT (PREVCOC1());
2686 if (PREVCOC1() == TF)
2688 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2689 TRACE_BRANCH_RESULT (dest);
2690 mark_branch_bug (dest);
2695 TRACE_BRANCH_RESULT (0);
2696 NULLIFY_NEXT_INSTRUCTION ();
2700 TRACE_BRANCH_RESULT (NIA);
2704 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
2705 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
2706 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
2712 check_branch_bug ();
2713 if (GETFCC(CC) == TF)
2715 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2716 mark_branch_bug (dest);
2721 NULLIFY_NEXT_INSTRUCTION ();
2734 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
2736 if ((fmt != fmt_single) && (fmt != fmt_double))
2737 SignalException (ReservedInstruction, insn);
2744 unsigned64 ofs = ValueFPR (fs, fmt);
2745 unsigned64 oft = ValueFPR (ft, fmt);
2746 if (NaN (ofs, fmt) || NaN (oft, fmt))
2748 if (FCSR & FP_ENABLE (IO))
2750 FCSR |= FP_CAUSE (IO);
2751 SignalExceptionFPE ();
2759 less = Less (ofs, oft, fmt);
2760 equal = Equal (ofs, oft, fmt);
2763 condition = (((cond & (1 << 2)) && less)
2764 || ((cond & (1 << 1)) && equal)
2765 || ((cond & (1 << 0)) && unordered));
2766 SETFCC (cc, condition);
2770 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
2771 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
2772 *mipsI,mipsII,mipsIII:
2774 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
2777 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
2778 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
2779 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
2785 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
2789 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
2790 "ceil.l.%s<FMT> f<FD>, f<FS>"
2797 unsigned32 instruction = instruction_0;
2798 int destreg = ((instruction >> 6) & 0x0000001F);
2799 int fs = ((instruction >> 11) & 0x0000001F);
2800 int format = ((instruction >> 21) & 0x00000007);
2802 if ((format != fmt_single) && (format != fmt_double))
2803 SignalException(ReservedInstruction,instruction);
2805 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
2810 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
2818 unsigned32 instruction = instruction_0;
2819 int destreg = ((instruction >> 6) & 0x0000001F);
2820 int fs = ((instruction >> 11) & 0x0000001F);
2821 int format = ((instruction >> 21) & 0x00000007);
2823 if ((format != fmt_single) && (format != fmt_double))
2824 SignalException(ReservedInstruction,instruction);
2826 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
2833 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
2834 "c%s<X>c1 r<RT>, f<FS>"
2842 PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
2844 PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
2846 PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
2849 { /* control from */
2851 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
2853 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
2857 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
2858 "c%s<X>c1 r<RT>, f<FS>"
2867 TRACE_ALU_INPUT1 (GPR[RT]);
2870 FCR0 = VL4_8(GPR[RT]);
2871 TRACE_ALU_RESULT (FCR0);
2875 FCR31 = VL4_8(GPR[RT]);
2876 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
2877 TRACE_ALU_RESULT (FCR31);
2881 TRACE_ALU_RESULT0 ();
2886 { /* control from */
2889 TRACE_ALU_INPUT1 (FCR0);
2890 GPR[RT] = SIGNEXTEND (FCR0, 32);
2894 TRACE_ALU_INPUT1 (FCR31);
2895 GPR[RT] = SIGNEXTEND (FCR31, 32);
2897 TRACE_ALU_RESULT (GPR[RT]);
2904 // FIXME: Does not correctly differentiate between mips*
2906 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
2907 "cvt.d.%s<FMT> f<FD>, f<FS>"
2908 *mipsI,mipsII,mipsIII,mipsIV:
2913 unsigned32 instruction = instruction_0;
2914 int destreg = ((instruction >> 6) & 0x0000001F);
2915 int fs = ((instruction >> 11) & 0x0000001F);
2916 int format = ((instruction >> 21) & 0x00000007);
2918 if ((format == fmt_double) | 0)
2919 SignalException(ReservedInstruction,instruction);
2921 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
2926 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
2927 "cvt.l.%s<FMT> f<FD>, f<FS>"
2934 unsigned32 instruction = instruction_0;
2935 int destreg = ((instruction >> 6) & 0x0000001F);
2936 int fs = ((instruction >> 11) & 0x0000001F);
2937 int format = ((instruction >> 21) & 0x00000007);
2939 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
2940 SignalException(ReservedInstruction,instruction);
2942 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
2948 // FIXME: Does not correctly differentiate between mips*
2950 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
2951 "cvt.s.%s<FMT> f<FD>, f<FS>"
2952 *mipsI,mipsII,mipsIII,mipsIV:
2957 unsigned32 instruction = instruction_0;
2958 int destreg = ((instruction >> 6) & 0x0000001F);
2959 int fs = ((instruction >> 11) & 0x0000001F);
2960 int format = ((instruction >> 21) & 0x00000007);
2962 if ((format == fmt_single) | 0)
2963 SignalException(ReservedInstruction,instruction);
2965 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
2970 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
2971 "cvt.w.%s<FMT> f<FD>, f<FS>"
2972 *mipsI,mipsII,mipsIII,mipsIV:
2977 unsigned32 instruction = instruction_0;
2978 int destreg = ((instruction >> 6) & 0x0000001F);
2979 int fs = ((instruction >> 11) & 0x0000001F);
2980 int format = ((instruction >> 21) & 0x00000007);
2982 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
2983 SignalException(ReservedInstruction,instruction);
2985 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
2990 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
2991 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
2992 *mipsI,mipsII,mipsIII,mipsIV:
2997 unsigned32 instruction = instruction_0;
2998 int destreg = ((instruction >> 6) & 0x0000001F);
2999 int fs = ((instruction >> 11) & 0x0000001F);
3000 int ft = ((instruction >> 16) & 0x0000001F);
3001 int format = ((instruction >> 21) & 0x00000007);
3003 if ((format != fmt_single) && (format != fmt_double))
3004 SignalException(ReservedInstruction,instruction);
3006 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3013 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
3014 "dm%s<X>c1 r<RT>, f<FS>"
3019 if (SizeFGR() == 64)
3020 PENDING_FILL((FS + FGRIDX),GPR[RT]);
3021 else if ((FS & 0x1) == 0)
3023 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3024 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3029 if (SizeFGR() == 64)
3030 PENDING_FILL(RT,FGR[FS]);
3031 else if ((FS & 0x1) == 0)
3032 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3035 if (STATE_VERBOSE_P(SD))
3037 "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
3039 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3043 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
3044 "dm%s<X>c1 r<RT>, f<FS>"
3052 if (SizeFGR() == 64)
3053 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3054 else if ((FS & 0x1) == 0)
3055 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3059 if (SizeFGR() == 64)
3061 else if ((FS & 0x1) == 0)
3062 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3065 if (STATE_VERBOSE_P(SD))
3067 "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
3069 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3075 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3076 "floor.l.%s<FMT> f<FD>, f<FS>"
3083 unsigned32 instruction = instruction_0;
3084 int destreg = ((instruction >> 6) & 0x0000001F);
3085 int fs = ((instruction >> 11) & 0x0000001F);
3086 int format = ((instruction >> 21) & 0x00000007);
3088 if ((format != fmt_single) && (format != fmt_double))
3089 SignalException(ReservedInstruction,instruction);
3091 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3096 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3097 "floor.w.%s<FMT> f<FD>, f<FS>"
3105 unsigned32 instruction = instruction_0;
3106 int destreg = ((instruction >> 6) & 0x0000001F);
3107 int fs = ((instruction >> 11) & 0x0000001F);
3108 int format = ((instruction >> 21) & 0x00000007);
3110 if ((format != fmt_single) && (format != fmt_double))
3111 SignalException(ReservedInstruction,instruction);
3113 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3118 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
3119 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
3128 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3132 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3133 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3137 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3142 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
3143 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
3144 *mipsI,mipsII,mipsIII,mipsIV:
3149 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3153 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
3154 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3158 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3164 // FIXME: Not correct for mips*
3166 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3167 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3171 unsigned32 instruction = instruction_0;
3172 int destreg = ((instruction >> 6) & 0x0000001F);
3173 int fs = ((instruction >> 11) & 0x0000001F);
3174 int ft = ((instruction >> 16) & 0x0000001F);
3175 int fr = ((instruction >> 21) & 0x0000001F);
3177 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3182 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3183 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3187 unsigned32 instruction = instruction_0;
3188 int destreg = ((instruction >> 6) & 0x0000001F);
3189 int fs = ((instruction >> 11) & 0x0000001F);
3190 int ft = ((instruction >> 16) & 0x0000001F);
3191 int fr = ((instruction >> 21) & 0x0000001F);
3193 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3200 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
3201 "m%s<X>c1 r<RT>, f<FS>"
3208 if (SizeFGR() == 64)
3210 if (STATE_VERBOSE_P(SD))
3212 "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
3214 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3217 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3220 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
3222 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
3223 "m%s<X>c1 r<RT>, f<FS>"
3232 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3234 GPR[RT] = SIGNEXTEND(FGR[FS],32);
3238 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
3239 "mov.%s<FMT> f<FD>, f<FS>"
3240 *mipsI,mipsII,mipsIII,mipsIV:
3245 unsigned32 instruction = instruction_0;
3246 int destreg = ((instruction >> 6) & 0x0000001F);
3247 int fs = ((instruction >> 11) & 0x0000001F);
3248 int format = ((instruction >> 21) & 0x00000007);
3250 StoreFPR(destreg,format,ValueFPR(fs,format));
3257 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
3258 "mov%s<TF> r<RD>, r<RS>, <CC>"
3262 if (GETFCC(CC) == TF)
3269 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
3270 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3274 unsigned32 instruction = instruction_0;
3275 int format = ((instruction >> 21) & 0x00000007);
3277 if (GETFCC(CC) == TF)
3278 StoreFPR (FD, format, ValueFPR (FS, format));
3280 StoreFPR (FD, format, ValueFPR (FD, format));
3285 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
3286 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
3291 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3293 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3300 // MOVT.fmt see MOVtf.fmt
3304 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
3305 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3310 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3312 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3317 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
3318 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3322 unsigned32 instruction = instruction_0;
3323 int destreg = ((instruction >> 6) & 0x0000001F);
3324 int fs = ((instruction >> 11) & 0x0000001F);
3325 int ft = ((instruction >> 16) & 0x0000001F);
3326 int fr = ((instruction >> 21) & 0x0000001F);
3328 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3334 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
3335 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3339 unsigned32 instruction = instruction_0;
3340 int destreg = ((instruction >> 6) & 0x0000001F);
3341 int fs = ((instruction >> 11) & 0x0000001F);
3342 int ft = ((instruction >> 16) & 0x0000001F);
3343 int fr = ((instruction >> 21) & 0x0000001F);
3345 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3353 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
3354 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3355 *mipsI,mipsII,mipsIII,mipsIV:
3360 unsigned32 instruction = instruction_0;
3361 int destreg = ((instruction >> 6) & 0x0000001F);
3362 int fs = ((instruction >> 11) & 0x0000001F);
3363 int ft = ((instruction >> 16) & 0x0000001F);
3364 int format = ((instruction >> 21) & 0x00000007);
3366 if ((format != fmt_single) && (format != fmt_double))
3367 SignalException(ReservedInstruction,instruction);
3369 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3374 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
3375 "neg.%s<FMT> f<FD>, f<FS>"
3376 *mipsI,mipsII,mipsIII,mipsIV:
3381 unsigned32 instruction = instruction_0;
3382 int destreg = ((instruction >> 6) & 0x0000001F);
3383 int fs = ((instruction >> 11) & 0x0000001F);
3384 int format = ((instruction >> 21) & 0x00000007);
3386 if ((format != fmt_single) && (format != fmt_double))
3387 SignalException(ReservedInstruction,instruction);
3389 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3395 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
3396 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3400 unsigned32 instruction = instruction_0;
3401 int destreg = ((instruction >> 6) & 0x0000001F);
3402 int fs = ((instruction >> 11) & 0x0000001F);
3403 int ft = ((instruction >> 16) & 0x0000001F);
3404 int fr = ((instruction >> 21) & 0x0000001F);
3406 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3412 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
3413 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3417 unsigned32 instruction = instruction_0;
3418 int destreg = ((instruction >> 6) & 0x0000001F);
3419 int fs = ((instruction >> 11) & 0x0000001F);
3420 int ft = ((instruction >> 16) & 0x0000001F);
3421 int fr = ((instruction >> 21) & 0x0000001F);
3423 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3429 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
3430 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3434 unsigned32 instruction = instruction_0;
3435 int destreg = ((instruction >> 6) & 0x0000001F);
3436 int fs = ((instruction >> 11) & 0x0000001F);
3437 int ft = ((instruction >> 16) & 0x0000001F);
3438 int fr = ((instruction >> 21) & 0x0000001F);
3440 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3446 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
3447 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3451 unsigned32 instruction = instruction_0;
3452 int destreg = ((instruction >> 6) & 0x0000001F);
3453 int fs = ((instruction >> 11) & 0x0000001F);
3454 int ft = ((instruction >> 16) & 0x0000001F);
3455 int fr = ((instruction >> 21) & 0x0000001F);
3457 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3462 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
3463 "prefx <HINT>, r<INDEX>(r<BASE>)"
3467 unsigned32 instruction = instruction_0;
3468 int fs = ((instruction >> 11) & 0x0000001F);
3469 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3470 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3472 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
3475 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3476 Prefetch(uncached,paddr,vaddr,isDATA,fs);
3480 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
3481 "recip.%s<FMT> f<FD>, f<FS>"
3485 unsigned32 instruction = instruction_0;
3486 int destreg = ((instruction >> 6) & 0x0000001F);
3487 int fs = ((instruction >> 11) & 0x0000001F);
3488 int format = ((instruction >> 21) & 0x00000007);
3490 if ((format != fmt_single) && (format != fmt_double))
3491 SignalException(ReservedInstruction,instruction);
3493 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
3498 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
3499 "round.l.%s<FMT> f<FD>, f<FS>"
3506 unsigned32 instruction = instruction_0;
3507 int destreg = ((instruction >> 6) & 0x0000001F);
3508 int fs = ((instruction >> 11) & 0x0000001F);
3509 int format = ((instruction >> 21) & 0x00000007);
3511 if ((format != fmt_single) && (format != fmt_double))
3512 SignalException(ReservedInstruction,instruction);
3514 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
3519 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
3520 "round.w.%s<FMT> f<FD>, f<FS>"
3528 unsigned32 instruction = instruction_0;
3529 int destreg = ((instruction >> 6) & 0x0000001F);
3530 int fs = ((instruction >> 11) & 0x0000001F);
3531 int format = ((instruction >> 21) & 0x00000007);
3533 if ((format != fmt_single) && (format != fmt_double))
3534 SignalException(ReservedInstruction,instruction);
3536 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
3541 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
3543 "rsqrt.%s<FMT> f<FD>, f<FS>"
3546 unsigned32 instruction = instruction_0;
3547 int destreg = ((instruction >> 6) & 0x0000001F);
3548 int fs = ((instruction >> 11) & 0x0000001F);
3549 int format = ((instruction >> 21) & 0x00000007);
3551 if ((format != fmt_single) && (format != fmt_double))
3552 SignalException(ReservedInstruction,instruction);
3554 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
3559 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
3560 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
3569 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
3573 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
3574 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
3578 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
3582 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
3583 "sqrt.%s<FMT> f<FD>, f<FS>"
3591 unsigned32 instruction = instruction_0;
3592 int destreg = ((instruction >> 6) & 0x0000001F);
3593 int fs = ((instruction >> 11) & 0x0000001F);
3594 int format = ((instruction >> 21) & 0x00000007);
3596 if ((format != fmt_single) && (format != fmt_double))
3597 SignalException(ReservedInstruction,instruction);
3599 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
3604 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
3605 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
3606 *mipsI,mipsII,mipsIII,mipsIV:
3611 unsigned32 instruction = instruction_0;
3612 int destreg = ((instruction >> 6) & 0x0000001F);
3613 int fs = ((instruction >> 11) & 0x0000001F);
3614 int ft = ((instruction >> 16) & 0x0000001F);
3615 int format = ((instruction >> 21) & 0x00000007);
3617 if ((format != fmt_single) && (format != fmt_double))
3618 SignalException(ReservedInstruction,instruction);
3620 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
3626 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
3627 "swc1 f<FT>, <OFFSET>(r<BASE>)"
3628 *mipsI,mipsII,mipsIII,mipsIV:
3633 unsigned32 instruction = instruction_0;
3634 signed_word offset = EXTEND16 (OFFSET);
3635 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
3636 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
3638 address_word vaddr = ((uword64)op1 + offset);
3641 if ((vaddr & 3) != 0)
3643 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
3647 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3650 uword64 memval1 = 0;
3651 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3652 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
3653 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
3655 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3656 byte = ((vaddr & mask) ^ bigendiancpu);
3657 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
3658 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3665 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
3666 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
3670 unsigned32 instruction = instruction_0;
3671 int fs = ((instruction >> 11) & 0x0000001F);
3672 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3673 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3675 address_word vaddr = ((unsigned64)op1 + op2);
3678 if ((vaddr & 3) != 0)
3680 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3684 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3686 unsigned64 memval = 0;
3687 unsigned64 memval1 = 0;
3688 unsigned64 mask = 0x7;
3690 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3691 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3692 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
3694 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3702 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
3703 "trunc.l.%s<FMT> f<FD>, f<FS>"
3710 unsigned32 instruction = instruction_0;
3711 int destreg = ((instruction >> 6) & 0x0000001F);
3712 int fs = ((instruction >> 11) & 0x0000001F);
3713 int format = ((instruction >> 21) & 0x00000007);
3715 if ((format != fmt_single) && (format != fmt_double))
3716 SignalException(ReservedInstruction,instruction);
3718 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
3723 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
3724 "trunc.w.%s<FMT> f<FD>, f<FS>"
3732 unsigned32 instruction = instruction_0;
3733 int destreg = ((instruction >> 6) & 0x0000001F);
3734 int fs = ((instruction >> 11) & 0x0000001F);
3735 int format = ((instruction >> 21) & 0x00000007);
3737 if ((format != fmt_single) && (format != fmt_double))
3738 SignalException(ReservedInstruction,instruction);
3740 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
3746 // MIPS Architecture:
3748 // System Control Instruction Set (COP0)
3752 010000,01000,00000,16.OFFSET:COP0:32::BC0F
3754 *mipsI,mipsII,mipsIII,mipsIV:
3758 010000,01000,00000,16.OFFSET:COP0:32::BC0F
3760 // stub needed for eCos as tx39 hardware bug workaround
3767 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
3769 *mipsI,mipsII,mipsIII,mipsIV:
3774 010000,01000,00001,16.OFFSET:COP0:32::BC0T
3776 *mipsI,mipsII,mipsIII,mipsIV:
3780 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
3782 *mipsI,mipsII,mipsIII,mipsIV:
3787 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
3794 unsigned32 instruction = instruction_0;
3795 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3796 int hint = ((instruction >> 16) & 0x0000001F);
3797 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3799 address_word vaddr = (op1 + offset);
3802 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3803 CacheOp(hint,vaddr,paddr,instruction);
3808 010000,10000,000000000000000,111001:COP0:32::DI
3810 *mipsI,mipsII,mipsIII,mipsIV:
3815 010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
3816 "dmfc0 r<RT>, r<RD>"
3819 DecodeCoproc (instruction_0);
3823 010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
3824 "dmtc0 r<RT>, r<RD>"
3827 DecodeCoproc (instruction_0);
3831 010000,10000,000000000000000,111000:COP0:32::EI
3833 *mipsI,mipsII,mipsIII,mipsIV:
3838 010000,10000,000000000000000,011000:COP0:32::ERET
3845 if (SR & status_ERL)
3847 /* Oops, not yet available */
3848 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
3860 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
3861 "mfc0 r<RT>, r<RD> # <REGX>"
3862 *mipsI,mipsII,mipsIII,mipsIV:
3867 TRACE_ALU_INPUT0 ();
3868 DecodeCoproc (instruction_0);
3869 TRACE_ALU_RESULT (GPR[RT]);
3872 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
3873 "mtc0 r<RT>, r<RD> # <REGX>"
3874 *mipsI,mipsII,mipsIII,mipsIV:
3879 DecodeCoproc (instruction_0);
3883 010000,10000,000000000000000,010000:COP0:32::RFE
3885 *mipsI,mipsII,mipsIII,mipsIV:
3890 DecodeCoproc (instruction_0);
3894 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
3895 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
3896 *mipsI,mipsII,mipsIII,mipsIV:
3900 DecodeCoproc (instruction_0);
3905 010000,10000,000000000000000,001000:COP0:32::TLBP
3907 *mipsI,mipsII,mipsIII,mipsIV:
3912 010000,10000,000000000000000,000001:COP0:32::TLBR
3914 *mipsI,mipsII,mipsIII,mipsIV:
3919 010000,10000,000000000000000,000010:COP0:32::TLBWI
3921 *mipsI,mipsII,mipsIII,mipsIV:
3926 010000,10000,000000000000000,000110:COP0:32::TLBWR
3928 *mipsI,mipsII,mipsIII,mipsIV: