sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips32r2:mipsisa32r2:
  49 :model:::mips64:mipsisa64:
  50 :model:::mips64r2:mipsisa64r2:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr4120:mips4120:
  61 :model:::vr5000:mips5000:
  62 :model:::vr5400:mips5400:
  63 :model:::vr5500:mips5500:
  64 :model:::r3900:mips3900:                // tx.igen
  65
  66 //  MIPS Application Specific Extensions (ASEs)
  67 //
  68 //  Instructions for the ASEs are in separate .igen files.
  69 //  ASEs add instructions on to a base ISA.
  70 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  71 :model:::mips16e:mips16e:               // m16e.igen
  72 :model:::mips3d:mips3d:                 // mips3d.igen
  73 :model:::mdmx:mdmx:                     // mdmx.igen
  74 :model:::dsp:dsp:                       // dsp.igen
  75 :model:::dsp2:dsp2:                     // dsp2.igen
  76 :model:::smartmips:smartmips:           // smartmips.igen
  77 :model:::micromips32:micromips64:       // micromips.igen
  78 :model:::micromips64:micromips64:       // micromips.igen
  79 :model:::micromipsdsp:micromipsdsp:     // micromipsdsp.igen
  80
  81 //  Vendor Extensions
  82 //
  83 //  Instructions specific to these extensions are in separate .igen files.
  84 //  Extensions add instructions on to a base ISA.
  85 :model:::sb1:sb1:                       // sb1.igen
  86
  87
  88 // Pseudo instructions known by IGEN
  89 :internal::::illegal:
  90 {
  91   SignalException (ReservedInstruction, 0);
  92 }
  93
  94
  95 // Pseudo instructions known by interp.c
  96 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  97 000000,5.*,5.*,5.*,5.OP,111001:SPECIAL:32::RSVD
  98 "rsvd <OP>"
  99 {
 100   SignalException (ReservedInstruction, instruction_0);
 101 }
 102
 103
 104
 105 // Helper:
 106 //
 107 // Simulate a 32 bit delayslot instruction
 108 //
 109
 110 :function:::address_word:delayslot32:address_word target
 111 {
 112   instruction_word delay_insn;
 113   sim_events_slip (SD, 1);
 114   DSPC = CIA;
 115   CIA = CIA + 4; /* NOTE not mips16 */
 116   STATE |= simDELAYSLOT;
 117   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 118   ENGINE_ISSUE_PREFIX_HOOK();
 119   idecode_issue (CPU_, delay_insn, (CIA));
 120   STATE &= ~simDELAYSLOT;
 121   return target;
 122 }
 123
 124 :function:::address_word:nullify_next_insn32:
 125 {
 126   sim_events_slip (SD, 1);
 127   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 128   return CIA + 8;
 129 }
 130
 131
 132 // Helper:
 133 //
 134 // Calculate an effective address given a base and an offset.
 135 //
 136
 137 :function:::address_word:loadstore_ea:address_word base, address_word offset
 138 *mipsI:
 139 *mipsII:
 140 *mipsIII:
 141 *mipsIV:
 142 *mipsV:
 143 *mips32:
 144 *mips32r2:
 145 *vr4100:
 146 *vr5000:
 147 *r3900:
 148 *micromips32:
 149 {
 150   return base + offset;
 151 }
 152
 153 :function:::address_word:loadstore_ea:address_word base, address_word offset
 154 *mips64:
 155 *mips64r2:
 156 *micromips64:
 157 {
 158 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 159   /* If in user mode and UX is not set, use 32-bit compatibility effective
 160      address computations as defined in the MIPS64 Architecture for
 161      Programmers Volume III, Revision 0.95, section 4.9.  */
 162   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 163       == (ksu_user << status_KSU_shift))
 164     return (address_word)((signed32)base + (signed32)offset);
 165 #endif
 166   return base + offset;
 167 }
 168
 169
 170 // Helper:
 171 //
 172 // Check that a 32-bit register value is properly sign-extended.
 173 // (See NotWordValue in ISA spec.)
 174 //
 175
 176 :function:::int:not_word_value:unsigned_word value
 177 *mipsI:
 178 *mipsII:
 179 *mipsIII:
 180 *mipsIV:
 181 *mipsV:
 182 *vr4100:
 183 *vr5000:
 184 *r3900:
 185 *mips32:
 186 *mips32r2:
 187 *mips64:
 188 *mips64r2:
 189 *micromips32:
 190 *micromips64:
 191 {
 192 #if WITH_TARGET_WORD_BITSIZE == 64
 193   return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
 194 #else
 195   return 0;
 196 #endif
 197 }
 198
 199 // Helper:
 200 //
 201 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 202 // theoretically portable code which invokes non-portable behaviour from
 203 // running with no indication of the portability issue.
 204 // (See definition of UNPREDICTABLE in ISA spec.)
 205 //
 206
 207 :function:::void:unpredictable:
 208 *mipsI:
 209 *mipsII:
 210 *mipsIII:
 211 *mipsIV:
 212 *mipsV:
 213 *vr4100:
 214 *vr5000:
 215 *r3900:
 216 {
 217 }
 218
 219 :function:::void:unpredictable:
 220 *mips32:
 221 *mips32r2:
 222 *mips64:
 223 *mips64r2:
 224 *micromips32:
 225 *micromips64:
 226 {
 227   unpredictable_action (CPU, CIA);
 228 }
 229
 230
 231 // Helpers:
 232 //
 233 // Check that an access to a HI/LO register meets timing requirements
 234 //
 235 // In all MIPS ISAs,
 236 //
 237 //      OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
 238 //      makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
 239 //
 240 // The following restrictions exist for MIPS I - MIPS III:
 241 //
 242 //      MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
 243 //      in between makes MF UNPREDICTABLE. (2)
 244 //
 245 //      MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
 246 //      in between makes MF UNPREDICTABLE. (3)
 247 //
 248 // On the r3900, restriction (2) is not present, and restriction (3) is not
 249 // present for multiplication.
 250 //
 251 // Unfortunately, there seems to be some confusion about whether the last
 252 // two restrictions should apply to "MIPS IV" as well.  One edition of
 253 // the MIPS IV ISA says they do, but references in later ISA documents
 254 // suggest they don't.
 255 //
 256 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
 257 // these restrictions, while others, like the VR5500, don't.  To accomodate
 258 // such differences, the MIPS IV and MIPS V version of these helper functions
 259 // use auxillary routines to determine whether the restriction applies.
 260
 261 // check_mf_cycles:
 262 //
 263 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
 264 // to check for restrictions (2) and (3) above.
 265 //
 266 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 267 {
 268   if (history->mf.timestamp + 3 > time)
 269     {
 270       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 271                         itable[MY_INDEX].name,
 272                         new, (long) CIA,
 273                         (long) history->mf.cia);
 274       return 0;
 275     }
 276   return 1;
 277 }
 278
 279
 280 // check_mt_hilo:
 281 //
 282 // Check for restriction (2) above (for ISAs/processors that have it),
 283 // and record timestamps for restriction (1) above.
 284 //
 285 :function:::int:check_mt_hilo:hilo_history *history
 286 *mipsI:
 287 *mipsII:
 288 *mipsIII:
 289 *vr4100:
 290 *vr5000:
 291 {
 292   signed64 time = sim_events_time (SD);
 293   int ok = check_mf_cycles (SD_, history, time, "MT");
 294   history->mt.timestamp = time;
 295   history->mt.cia = CIA;
 296   return ok;
 297 }
 298
 299 :function:::int:check_mt_hilo:hilo_history *history
 300 *mipsIV:
 301 *mipsV:
 302 {
 303   signed64 time = sim_events_time (SD);
 304   int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
 305             || check_mf_cycles (SD_, history, time, "MT"));
 306   history->mt.timestamp = time;
 307   history->mt.cia = CIA;
 308   return ok;
 309 }
 310
 311 :function:::int:check_mt_hilo:hilo_history *history
 312 *mips32:
 313 *mips32r2:
 314 *mips64:
 315 *mips64r2:
 316 *r3900:
 317 *micromips32:
 318 *micromips64:
 319 {
 320   signed64 time = sim_events_time (SD);
 321   history->mt.timestamp = time;
 322   history->mt.cia = CIA;
 323   return 1;
 324 }
 325
 326
 327 // check_mf_hilo:
 328 //
 329 // Check for restriction (1) above, and record timestamps for
 330 // restriction (2) and (3) above.
 331 //
 332 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 333 *mipsI:
 334 *mipsII:
 335 *mipsIII:
 336 *mipsIV:
 337 *mipsV:
 338 *mips32:
 339 *mips32r2:
 340 *mips64:
 341 *mips64r2:
 342 *vr4100:
 343 *vr5000:
 344 *r3900:
 345 *micromips32:
 346 *micromips64:
 347 {
 348   signed64 time = sim_events_time (SD);
 349   int ok = 1;
 350   if (peer != NULL
 351       && peer->mt.timestamp > history->op.timestamp
 352       && history->mt.timestamp < history->op.timestamp
 353       && ! (history->mf.timestamp > history->op.timestamp
 354             && history->mf.timestamp < peer->mt.timestamp)
 355       && ! (peer->mf.timestamp > history->op.timestamp
 356             && peer->mf.timestamp < peer->mt.timestamp))
 357     {
 358       /* The peer has been written to since the last OP yet we have
 359          not */
 360       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 361                         itable[MY_INDEX].name,
 362                         (long) CIA,
 363                         (long) history->op.cia,
 364                         (long) peer->mt.cia);
 365       ok = 0;
 366     }
 367   history->mf.timestamp = time;
 368   history->mf.cia = CIA;
 369   return ok;
 370 }
 371
 372
 373
 374 // check_mult_hilo:
 375 //
 376 // Check for restriction (3) above (for ISAs/processors that have it)
 377 // for MULT ops, and record timestamps for restriction (1) above.
 378 //
 379 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 380 *mipsI:
 381 *mipsII:
 382 *mipsIII:
 383 *vr4100:
 384 *vr5000:
 385 {
 386   signed64 time = sim_events_time (SD);
 387   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 388             && check_mf_cycles (SD_, lo, time, "OP"));
 389   hi->op.timestamp = time;
 390   lo->op.timestamp = time;
 391   hi->op.cia = CIA;
 392   lo->op.cia = CIA;
 393   return ok;
 394 }
 395
 396 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 397 *mipsIV:
 398 *mipsV:
 399 {
 400   signed64 time = sim_events_time (SD);
 401   int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
 402             || (check_mf_cycles (SD_, hi, time, "OP")
 403                 && check_mf_cycles (SD_, lo, time, "OP")));
 404   hi->op.timestamp = time;
 405   lo->op.timestamp = time;
 406   hi->op.cia = CIA;
 407   lo->op.cia = CIA;
 408   return ok;
 409 }
 410
 411 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 412 *mips32:
 413 *mips32r2:
 414 *mips64:
 415 *mips64r2:
 416 *r3900:
 417 *micromips32:
 418 *micromips64:
 419 {
 420   /* FIXME: could record the fact that a stall occured if we want */
 421   signed64 time = sim_events_time (SD);
 422   hi->op.timestamp = time;
 423   lo->op.timestamp = time;
 424   hi->op.cia = CIA;
 425   lo->op.cia = CIA;
 426   return 1;
 427 }
 428
 429
 430 // check_div_hilo:
 431 //
 432 // Check for restriction (3) above (for ISAs/processors that have it)
 433 // for DIV ops, and record timestamps for restriction (1) above.
 434 //
 435 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 436 *mipsI:
 437 *mipsII:
 438 *mipsIII:
 439 *vr4100:
 440 *vr5000:
 441 *r3900:
 442 {
 443   signed64 time = sim_events_time (SD);
 444   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 445             && check_mf_cycles (SD_, lo, time, "OP"));
 446   hi->op.timestamp = time;
 447   lo->op.timestamp = time;
 448   hi->op.cia = CIA;
 449   lo->op.cia = CIA;
 450   return ok;
 451 }
 452
 453 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 454 *mipsIV:
 455 *mipsV:
 456 {
 457   signed64 time = sim_events_time (SD);
 458   int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
 459             || (check_mf_cycles (SD_, hi, time, "OP")
 460                 && check_mf_cycles (SD_, lo, time, "OP")));
 461   hi->op.timestamp = time;
 462   lo->op.timestamp = time;
 463   hi->op.cia = CIA;
 464   lo->op.cia = CIA;
 465   return ok;
 466 }
 467
 468 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 469 *mips32:
 470 *mips32r2:
 471 *mips64:
 472 *mips64r2:
 473 *micromips32:
 474 *micromips64:
 475 {
 476   signed64 time = sim_events_time (SD);
 477   hi->op.timestamp = time;
 478   lo->op.timestamp = time;
 479   hi->op.cia = CIA;
 480   lo->op.cia = CIA;
 481   return 1;
 482 }
 483
 484
 485 // Helper:
 486 //
 487 // Check that the 64-bit instruction can currently be used, and signal
 488 // a ReservedInstruction exception if not.
 489 //
 490
 491 :function:::void:check_u64:instruction_word insn
 492 *mipsIII:
 493 *mipsIV:
 494 *mipsV:
 495 *vr4100:
 496 *vr5000:
 497 *vr5400:
 498 *vr5500:
 499 {
 500   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 501 }
 502
 503 :function:::void:check_u64:instruction_word insn
 504 *mips16e:
 505 *mips64:
 506 *mips64r2:
 507 *mips32:
 508 *mips32r2:
 509 *micromips64:
 510 *micromips32:
 511 {
 512 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 513   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 514     SignalException (ReservedInstruction, insn);
 515 #endif
 516 }
 517
 518
 519
 520 //
 521 // MIPS Architecture:
 522 //
 523 //        CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
 524 //
 525
 526
 527 :function:::void:do_add:int rs, int rt, int rd
 528 {
 529   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 530     Unpredictable ();
 531   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 532   {
 533     ALU32_BEGIN (GPR[rs]);
 534     ALU32_ADD (GPR[rt]);
 535     ALU32_END (GPR[rd]);   /* This checks for overflow.  */
 536   }
 537   TRACE_ALU_RESULT (GPR[rd]);
 538 }
 539
 540 :function:::void:do_addi:int rs, int rt, unsigned16 immediate
 541 {
 542   if (NotWordValue (GPR[rs]))
 543     Unpredictable ();
 544   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 545   {
 546     ALU32_BEGIN (GPR[rs]);
 547     ALU32_ADD (EXTEND16 (immediate));
 548     ALU32_END (GPR[rt]);   /* This checks for overflow.  */
 549   }
 550   TRACE_ALU_RESULT (GPR[rt]);
 551 }
 552
 553 :function:::void:do_andi:int rs, int rt, unsigned int immediate
 554 {
 555   TRACE_ALU_INPUT2 (GPR[rs], immediate);
 556   GPR[rt] = GPR[rs] & immediate;
 557   TRACE_ALU_RESULT (GPR[rt]);
 558 }
 559
 560 :function:::void:do_dadd:int rd, int rs, int rt
 561 {
 562   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 563   {
 564     ALU64_BEGIN (GPR[rs]);
 565     ALU64_ADD (GPR[rt]);
 566     ALU64_END (GPR[rd]);   /* This checks for overflow.  */
 567   }
 568   TRACE_ALU_RESULT (GPR[rd]);
 569 }
 570
 571 :function:::void:do_daddi:int rt, int rs, int immediate
 572 {
 573   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 574   {
 575     ALU64_BEGIN (GPR[rs]);
 576     ALU64_ADD (EXTEND16 (immediate));
 577     ALU64_END (GPR[rt]);   /* This checks for overflow.  */
 578   }
 579   TRACE_ALU_RESULT (GPR[rt]);
 580 }
 581
 582 :function:::void:do_dsll32:int rd, int rt, int shift
 583 {
 584   int s = 32 + shift;
 585   TRACE_ALU_INPUT2 (GPR[rt], s);
 586   GPR[rd] = GPR[rt] << s;
 587   TRACE_ALU_RESULT (GPR[rd]);
 588 }
 589
 590 :function:::void:do_dsra32:int rd, int rt, int shift
 591 {
 592   int s = 32 + shift;
 593   TRACE_ALU_INPUT2 (GPR[rt], s);
 594   GPR[rd] = ((signed64) GPR[rt]) >> s;
 595   TRACE_ALU_RESULT (GPR[rd]);
 596 }
 597
 598 :function:::void:do_dsrl32:int rd, int rt, int shift
 599 {
 600   int s = 32 + shift;
 601   TRACE_ALU_INPUT2 (GPR[rt], s);
 602   GPR[rd] = (unsigned64) GPR[rt] >> s;
 603   TRACE_ALU_RESULT (GPR[rd]);
 604 }
 605
 606 :function:::void:do_dsub:int rd, int rs, int rt
 607 {
 608   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 609   {
 610     ALU64_BEGIN (GPR[rs]);
 611     ALU64_SUB (GPR[rt]);
 612     ALU64_END (GPR[rd]);   /* This checks for overflow.  */
 613   }
 614   TRACE_ALU_RESULT (GPR[rd]);
 615 }
 616
 617 :function:::void:do_break:address_word instruction_0
 618 {
 619   /* Check for some break instruction which are reserved for use by the
 620      simulator.  */
 621   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 622   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 623       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 624     {
 625       sim_engine_halt (SD, CPU, NULL, cia,
 626                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 627     }
 628   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 629            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 630     {
 631       if (STATE & simDELAYSLOT)
 632         PC = cia - 4; /* reference the branch instruction */
 633       else
 634         PC = cia;
 635       SignalException (BreakPoint, instruction_0);
 636     }
 637
 638   else
 639     {
 640       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 641          the exception. */
 642       SignalException (BreakPoint, instruction_0);
 643     }
 644 }
 645
 646 :function:::void:do_break16:address_word instruction_0
 647 {
 648   if (STATE & simDELAYSLOT)
 649     PC = cia - 2; /* reference the branch instruction */
 650   else
 651     PC = cia;
 652   SignalException (BreakPoint, instruction_0);
 653 }
 654
 655 :function:::void:do_clo:int rd, int rs
 656 {
 657   unsigned32 temp = GPR[rs];
 658   unsigned32 i, mask;
 659   if (NotWordValue (GPR[rs]))
 660     Unpredictable ();
 661   TRACE_ALU_INPUT1 (GPR[rs]);
 662   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
 663     {
 664       if ((temp & mask) == 0)
 665         break;
 666       mask >>= 1;
 667     }
 668   GPR[rd] = EXTEND32 (i);
 669   TRACE_ALU_RESULT (GPR[rd]);
 670 }
 671
 672 :function:::void:do_clz:int rd, int rs
 673 {
 674   unsigned32 temp = GPR[rs];
 675   unsigned32 i, mask;
 676   if (NotWordValue (GPR[rs]))
 677     Unpredictable ();
 678   TRACE_ALU_INPUT1 (GPR[rs]);
 679   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
 680     {
 681       if ((temp & mask) != 0)
 682         break;
 683       mask >>= 1;
 684     }
 685   GPR[rd] = EXTEND32 (i);
 686   TRACE_ALU_RESULT (GPR[rd]);
 687 }
 688
 689 :function:::void:do_dclo:int rd, int rs
 690 {
 691   unsigned64 temp = GPR[rs];
 692   unsigned32 i;
 693   unsigned64 mask;
 694   TRACE_ALU_INPUT1 (GPR[rs]);
 695   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
 696     {
 697       if ((temp & mask) == 0)
 698         break;
 699       mask >>= 1;
 700     }
 701   GPR[rd] = EXTEND32 (i);
 702   TRACE_ALU_RESULT (GPR[rd]);
 703 }
 704
 705 :function:::void:do_dclz:int rd, int rs
 706 {
 707   unsigned64 temp = GPR[rs];
 708   unsigned32 i;
 709   unsigned64 mask;
 710   TRACE_ALU_INPUT1 (GPR[rs]);
 711   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
 712     {
 713       if ((temp & mask) != 0)
 714         break;
 715       mask >>= 1;
 716     }
 717   GPR[rd] = EXTEND32 (i);
 718   TRACE_ALU_RESULT (GPR[rd]);
 719 }
 720
 721 :function:::void:do_lb:int rt, int offset, int base
 722 {
 723   GPR[rt] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[base],
 724                               EXTEND16 (offset)));
 725 }
 726
 727 :function:::void:do_lh:int rt, int offset, int base
 728 {
 729   GPR[rt] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base],
 730                                EXTEND16 (offset)));
 731 }
 732
 733 :function:::void:do_lwr:int rt, int offset, int base
 734 {
 735   GPR[rt] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[base],
 736                                      EXTEND16 (offset), GPR[rt]));
 737 }
 738
 739 :function:::void:do_lwl:int rt, int offset, int base
 740 {
 741   GPR[rt] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[base],
 742                                     EXTEND16 (offset), GPR[rt]));
 743 }
 744
 745 :function:::void:do_lwc:int num, int rt, int offset, int base
 746 {
 747   COP_LW (num, rt, do_load (SD_, AccessLength_WORD, GPR[base],
 748                             EXTEND16 (offset)));
 749 }
 750
 751 :function:::void:do_lw:int rt, int offset, int base
 752 {
 753   GPR[rt] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base],
 754                                EXTEND16 (offset)));
 755 }
 756
 757 :function:::void:do_lwu:int rt, int offset, int base, address_word instruction_0
 758 {
 759   check_u64 (SD_, instruction_0);
 760   GPR[rt] = do_load (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset));
 761 }
 762
 763 :function:::void:do_lhu:int rt, int offset, int base
 764 {
 765   GPR[rt] = do_load (SD_, AccessLength_HALFWORD, GPR[base], EXTEND16 (offset));
 766 }
 767
 768 :function:::void:do_ldc:int num, int rt, int offset, int base
 769 {
 770   COP_LD (num, rt, do_load (SD_, AccessLength_DOUBLEWORD, GPR[base],
 771                             EXTEND16 (offset)));
 772 }
 773
 774 :function:::void:do_lbu:int rt, int offset, int base
 775 {
 776   GPR[rt] = do_load (SD_, AccessLength_BYTE, GPR[base], EXTEND16 (offset));
 777 }
 778
 779 :function:::void:do_ll:int rt, int insn_offset, int basereg
 780 {
 781   address_word base = GPR[basereg];
 782   address_word offset = EXTEND16 (insn_offset);
 783     {
 784       address_word vaddr = loadstore_ea (SD_, base, offset);
 785       address_word paddr;
 786       int uncached;
 787       if ((vaddr & 3) != 0)
 788         {
 789           SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer,
 790                            sim_core_unaligned_signal);
 791         }
 792       else
 793         {
 794           if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
 795                                   isTARGET, isREAL))
 796             {
 797               unsigned64 memval = 0;
 798               unsigned64 memval1 = 0;
 799               unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
 800               unsigned int shift = 2;
 801               unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
 802               unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
 803               unsigned int byte;
 804               paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
 805               LoadMemory (&memval, &memval1, uncached, AccessLength_WORD, paddr,
 806                          vaddr, isDATA, isREAL);
 807               byte = ((vaddr & mask) ^ (bigend << shift));
 808               GPR[rt] = EXTEND32 (memval >> (8 * byte));
 809               LLBIT = 1;
 810             }
 811         }
 812     }
 813 }
 814
 815 :function:::void:do_lld:int rt, int roffset, int rbase
 816 {
 817   address_word base = GPR[rbase];
 818   address_word offset = EXTEND16 (roffset);
 819   {
 820     address_word vaddr = loadstore_ea (SD_, base, offset);
 821     address_word paddr;
 822     int uncached;
 823     if ((vaddr & 7) != 0)
 824       {
 825         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer,
 826                 sim_core_unaligned_signal);
 827       }
 828     else
 829       {
 830         if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
 831                                isTARGET, isREAL))
 832           {
 833             unsigned64 memval = 0;
 834             unsigned64 memval1 = 0;
 835             LoadMemory (&memval, &memval1, uncached, AccessLength_DOUBLEWORD,
 836                         paddr, vaddr, isDATA, isREAL);
 837             GPR[rt] = memval;
 838             LLBIT = 1;
 839           }
 840       }
 841   }
 842 }
 843
 844 :function:::void:do_lui:int rt, int immediate
 845 {
 846   TRACE_ALU_INPUT1 (immediate);
 847   GPR[rt] = EXTEND32 (immediate << 16);
 848   TRACE_ALU_RESULT (GPR[rt]);
 849 }
 850
 851 :function:::void:do_madd:int rs, int rt
 852 {
 853   signed64 temp;
 854   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 855   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 856     Unpredictable ();
 857   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 858   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
 859           + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
 860   LO = EXTEND32 (temp);
 861   HI = EXTEND32 (VH4_8 (temp));
 862   TRACE_ALU_RESULT2 (HI, LO);
 863 }
 864
 865 :function:::void:do_dsp_madd:int ac, int rs, int rt
 866 {
 867   signed64 temp;
 868   if (ac == 0)
 869     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 870   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 871     Unpredictable ();
 872   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 873   temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
 874           + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
 875   DSPLO(ac) = EXTEND32 (temp);
 876   DSPHI(ac) = EXTEND32 (VH4_8 (temp));
 877   if (ac == 0)
 878     TRACE_ALU_RESULT2 (HI, LO);
 879 }
 880
 881 :function:::void:do_maddu:int rs, int rt
 882 {
 883   unsigned64 temp;
 884   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 885   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 886     Unpredictable ();
 887   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 888   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
 889           + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
 890   ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp;  /* SmartMIPS */
 891   LO = EXTEND32 (temp);
 892   HI = EXTEND32 (VH4_8 (temp));
 893   TRACE_ALU_RESULT2 (HI, LO);
 894 }
 895
 896 :function:::void:do_dsp_maddu:int ac, int rs, int rt
 897 {
 898   unsigned64 temp;
 899   if (ac == 0)
 900     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 901   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 902     Unpredictable ();
 903   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 904   temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
 905           + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
 906   if (ac == 0)
 907     ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp;  /* SmartMIPS */
 908   DSPLO(ac) = EXTEND32 (temp);
 909   DSPHI(ac) = EXTEND32 (VH4_8 (temp));
 910   if (ac == 0)
 911     TRACE_ALU_RESULT2 (HI, LO);
 912 }
 913
 914 :function:::void:do_dsp_mfhi:int ac, int rd
 915 {
 916   if (ac == 0)
 917     do_mfhi (SD_, rd);
 918   else
 919     GPR[rd] = DSPHI(ac);
 920 }
 921
 922 :function:::void:do_dsp_mflo:int ac, int rd
 923 {
 924   if (ac == 0)
 925     do_mflo (SD_, rd);
 926   else
 927     GPR[rd] = DSPLO(ac);
 928 }
 929
 930 :function:::void:do_movn:int rd, int rs, int rt
 931 {
 932   if (GPR[rt] != 0)
 933     {
 934       GPR[rd] = GPR[rs];
 935       TRACE_ALU_RESULT (GPR[rd]);
 936     }
 937 }
 938
 939 :function:::void:do_movz:int rd, int rs, int rt
 940 {
 941   if (GPR[rt] == 0)
 942     {
 943       GPR[rd] = GPR[rs];
 944       TRACE_ALU_RESULT (GPR[rd]);
 945     }
 946 }
 947
 948 :function:::void:do_msub:int rs, int rt
 949 {
 950   signed64 temp;
 951   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 952   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 953     Unpredictable ();
 954   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 955   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
 956           - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
 957   LO = EXTEND32 (temp);
 958   HI = EXTEND32 (VH4_8 (temp));
 959   TRACE_ALU_RESULT2 (HI, LO);
 960 }
 961
 962 :function:::void:do_dsp_msub:int ac, int rs, int rt
 963 {
 964   signed64 temp;
 965   if (ac == 0)
 966     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 967   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 968     Unpredictable ();
 969   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 970   temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
 971           - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
 972   DSPLO(ac) = EXTEND32 (temp);
 973   DSPHI(ac) = EXTEND32 (VH4_8 (temp));
 974   if (ac == 0)
 975     TRACE_ALU_RESULT2 (HI, LO);
 976 }
 977
 978 :function:::void:do_msubu:int rs, int rt
 979 {
 980   unsigned64 temp;
 981   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 982   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 983     Unpredictable ();
 984   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 985   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
 986           - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
 987   LO = EXTEND32 (temp);
 988   HI = EXTEND32 (VH4_8 (temp));
 989   TRACE_ALU_RESULT2 (HI, LO);
 990 }
 991
 992 :function:::void:do_dsp_msubu:int ac, int rs, int rt
 993 {
 994   unsigned64 temp;
 995   if (ac == 0)
 996     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 997   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 998     Unpredictable ();
 999   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1000   temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
1001           - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
1002   DSPLO(ac) = EXTEND32 (temp);
1003   DSPHI(ac) = EXTEND32 (VH4_8 (temp));
1004   if (ac == 0)
1005     TRACE_ALU_RESULT2 (HI, LO);
1006 }
1007
1008 :function:::void:do_mthi:int rs
1009 {
1010   check_mt_hilo (SD_, HIHISTORY);
1011   HI = GPR[rs];
1012 }
1013
1014 :function:::void:do_dsp_mthi:int ac, int rs
1015 {
1016   if (ac == 0)
1017     check_mt_hilo (SD_, HIHISTORY);
1018   DSPHI(ac) = GPR[rs];
1019 }
1020
1021 :function:::void:do_mtlo:int rs
1022 {
1023   check_mt_hilo (SD_, LOHISTORY);
1024   LO = GPR[rs];
1025 }
1026
1027 :function:::void:do_dsp_mtlo:int ac, int rs
1028 {
1029   if (ac == 0)
1030     check_mt_hilo (SD_, LOHISTORY);
1031   DSPLO(ac) = GPR[rs];
1032 }
1033
1034 :function:::void:do_mul:int rd, int rs, int rt
1035 {
1036   signed64 prod;
1037   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1038     Unpredictable ();
1039   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1040   prod = (((signed64)(signed32) GPR[rs])
1041           * ((signed64)(signed32) GPR[rt]));
1042   GPR[rd] = EXTEND32 (VL4_8 (prod));
1043   TRACE_ALU_RESULT (GPR[rd]);
1044 }
1045
1046 :function:::void:do_dsp_mult:int ac, int rs, int rt
1047 {
1048   signed64 prod;
1049   if (ac == 0)
1050     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1051   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1052     Unpredictable ();
1053   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1054   prod = ((signed64)(signed32) GPR[rs])
1055           * ((signed64)(signed32) GPR[rt]);
1056   DSPLO(ac) = EXTEND32 (VL4_8 (prod));
1057   DSPHI(ac) = EXTEND32 (VH4_8 (prod));
1058   if (ac == 0)
1059   {
1060     ACX = 0;  /* SmartMIPS */
1061     TRACE_ALU_RESULT2 (HI, LO);
1062   }
1063 }
1064
1065 :function:::void:do_dsp_multu:int ac, int rs, int rt
1066 {
1067   unsigned64 prod;
1068   if (ac == 0)
1069     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1070   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1071     Unpredictable ();
1072   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1073   prod = ((unsigned64)(unsigned32) GPR[rs])
1074           * ((unsigned64)(unsigned32) GPR[rt]);
1075   DSPLO(ac) = EXTEND32 (VL4_8 (prod));
1076   DSPHI(ac) = EXTEND32 (VH4_8 (prod));
1077   if (ac == 0)
1078     TRACE_ALU_RESULT2 (HI, LO);
1079 }
1080
1081 :function:::void:do_pref:int hint, int insn_offset, int insn_base
1082 {
1083   address_word base = GPR[insn_base];
1084   address_word offset = EXTEND16 (insn_offset);
1085   {
1086     address_word vaddr = loadstore_ea (SD_, base, offset);
1087     address_word paddr;
1088     int uncached;
1089     {
1090       if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1091                               isTARGET, isREAL))
1092         Prefetch (uncached, paddr, vaddr, isDATA, hint);
1093     }
1094   }
1095 }
1096
1097 :function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0
1098 {
1099   unsigned32 instruction = instruction_0;
1100   address_word base = GPR[basereg];
1101   address_word offset = EXTEND16 (offsetarg);
1102   {
1103     address_word vaddr = loadstore_ea (SD_, base, offset);
1104     address_word paddr;
1105     int uncached;
1106     if ((vaddr & 3) != 0)
1107       {
1108         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
1109                          sim_core_unaligned_signal);
1110       }
1111     else
1112       {
1113         if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1114                                 isTARGET, isREAL))
1115           {
1116             unsigned64 memval = 0;
1117             unsigned64 memval1 = 0;
1118             unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1119             address_word reverseendian =
1120               (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
1121             address_word bigendiancpu =
1122               (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
1123             unsigned int byte;
1124             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1125             byte = ((vaddr & mask) ^ bigendiancpu);
1126             memval = ((unsigned64) GPR[rt] << (8 * byte));
1127             if (LLBIT)
1128               {
1129                 StoreMemory (uncached, AccessLength_WORD, memval, memval1,
1130                              paddr, vaddr, isREAL);
1131               }
1132             GPR[rt] = LLBIT;
1133           }
1134       }
1135   }
1136 }
1137
1138 :function:::void:do_scd:int rt, int roffset, int rbase
1139 {
1140   address_word base = GPR[rbase];
1141   address_word offset = EXTEND16 (roffset);
1142   {
1143     address_word vaddr = loadstore_ea (SD_, base, offset);
1144     address_word paddr;
1145     int uncached;
1146     if ((vaddr & 7) != 0)
1147       {
1148         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer,
1149                          sim_core_unaligned_signal);
1150       }
1151     else
1152       {
1153         if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1154                                 isTARGET, isREAL))
1155           {
1156             unsigned64 memval = 0;
1157             unsigned64 memval1 = 0;
1158             memval = GPR[rt];
1159             if (LLBIT)
1160               {
1161                 StoreMemory (uncached, AccessLength_DOUBLEWORD, memval, memval1,
1162                              paddr, vaddr, isREAL);
1163               }
1164             GPR[rt] = LLBIT;
1165           }
1166       }
1167   }
1168 }
1169
1170 :function:::void:do_sub:int rs, int rt, int rd
1171 {
1172   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1173     Unpredictable ();
1174   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1175   {
1176     ALU32_BEGIN (GPR[rs]);
1177     ALU32_SUB (GPR[rt]);
1178     ALU32_END (GPR[rd]);   /* This checks for overflow.  */
1179   }
1180   TRACE_ALU_RESULT (GPR[rd]);
1181 }
1182
1183 :function:::void:do_sw:int rt, int offset, int base
1184 {
1185   do_store (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset), GPR[rt]);
1186 }
1187
1188 :function:::void:do_teq:int rs, int rt, address_word instruction_0
1189 {
1190   if ((signed_word) GPR[rs] == (signed_word) GPR[rt])
1191     SignalException (Trap, instruction_0);
1192 }
1193
1194 :function:::void:do_teqi:int rs, int immediate, address_word instruction_0
1195 {
1196   if ((signed_word) GPR[rs] == (signed_word) EXTEND16 (immediate))
1197     SignalException (Trap, instruction_0);
1198 }
1199
1200 :function:::void:do_tge:int rs, int rt, address_word instruction_0
1201 {
1202   if ((signed_word) GPR[rs] >= (signed_word) GPR[rt])
1203     SignalException (Trap, instruction_0);
1204 }
1205
1206 :function:::void:do_tgei:int rs, int immediate, address_word instruction_0
1207 {
1208   if ((signed_word) GPR[rs] >= (signed_word) EXTEND16 (immediate))
1209     SignalException (Trap, instruction_0);
1210 }
1211
1212 :function:::void:do_tgeiu:int rs, int immediate, address_word instruction_0
1213 {
1214   if ((unsigned_word) GPR[rs] >= (unsigned_word) EXTEND16 (immediate))
1215     SignalException (Trap, instruction_0);
1216 }
1217
1218 :function:::void:do_tgeu:int rs ,int rt, address_word instruction_0
1219 {
1220   if ((unsigned_word) GPR[rs] >= (unsigned_word) GPR[rt])
1221     SignalException (Trap, instruction_0);
1222 }
1223
1224 :function:::void:do_tlt:int rs, int rt, address_word instruction_0
1225 {
1226   if ((signed_word) GPR[rs] < (signed_word) GPR[rt])
1227     SignalException (Trap, instruction_0);
1228 }
1229
1230 :function:::void:do_tlti:int rs, int immediate, address_word instruction_0
1231 {
1232   if ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate))
1233     SignalException (Trap, instruction_0);
1234 }
1235
1236 :function:::void:do_tltiu:int rs, int immediate, address_word instruction_0
1237 {
1238   if ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate))
1239     SignalException (Trap, instruction_0);
1240 }
1241
1242 :function:::void:do_tltu:int rs, int rt, address_word instruction_0
1243 {
1244   if ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt])
1245     SignalException (Trap, instruction_0);
1246 }
1247
1248 :function:::void:do_tne:int rs, int rt, address_word instruction_0
1249 {
1250   if ((signed_word) GPR[rs] != (signed_word) GPR[rt])
1251     SignalException (Trap, instruction_0);
1252 }
1253
1254 :function:::void:do_tnei:int rs, int immediate, address_word instruction_0
1255 {
1256   if ((signed_word) GPR[rs] != (signed_word) EXTEND16 (immediate))
1257     SignalException (Trap, instruction_0);
1258 }
1259
1260 :function:::void:do_abs_fmt:int fmt, int fd, int fs, address_word instruction_0
1261 {
1262   check_fpu (SD_);
1263   check_fmt_p (SD_, fmt, instruction_0);
1264   StoreFPR (fd, fmt, AbsoluteValue (ValueFPR (fs, fmt), fmt));
1265 }
1266
1267 :function:::void:do_add_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1268 {
1269   check_fpu (SD_);
1270   check_fmt_p (SD_, fmt, instruction_0);
1271   StoreFPR (fd, fmt, Add (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1272 }
1273
1274 :function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0
1275 {
1276   unsigned64 fsx;
1277   unsigned64 ftx;
1278   unsigned64 fdx;
1279   check_fpu (SD_);
1280   check_u64 (SD_, instruction_0);
1281   fsx = ValueFPR (fs, fmt_ps);
1282   if ((GPR[rs] & 0x3) != 0)
1283     Unpredictable ();
1284   if ((GPR[rs] & 0x4) == 0)
1285     fdx = fsx;
1286   else
1287     {
1288       ftx = ValueFPR (ft, fmt_ps);
1289       if (BigEndianCPU)
1290         fdx = PackPS (PSLower (fsx), PSUpper (ftx));
1291       else
1292         fdx = PackPS (PSLower (ftx), PSUpper (fsx));
1293     }
1294   StoreFPR (fd, fmt_ps, fdx);
1295 }
1296
1297 :function:::void:do_c_cond_fmt:int cond, int fmt, int cc, int fs, int ft, address_word instruction_0
1298 {
1299   check_fpu (SD_);
1300   check_fmt_p (SD_, fmt, instruction_0);
1301   Compare (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt, cond, cc);
1302   TRACE_ALU_RESULT (ValueFCR (31));
1303 }
1304
1305 :function:::void:do_ceil_fmt:int type, int fmt, int fd, int fs, address_word instruction_0
1306 {
1307   check_fpu (SD_);
1308   check_fmt_p (SD_, fmt, instruction_0);
1309   StoreFPR (fd, type, Convert (FP_RM_TOPINF, ValueFPR (fs, fmt), fmt,
1310             type));
1311 }
1312
1313 :function:::void:do_cfc1:int rt, int fs
1314 {
1315   check_fpu (SD_);
1316   if (fs == 0 || fs == 25 || fs == 26 || fs == 28 || fs == 31)
1317     {
1318       unsigned_word  fcr = ValueFCR (fs);
1319       TRACE_ALU_INPUT1 (fcr);
1320       GPR[rt] = fcr;
1321     }
1322   /* else NOP */
1323   TRACE_ALU_RESULT (GPR[rt]);
1324 }
1325
1326 :function:::void:do_ctc1:int rt, int fs
1327 {
1328   check_fpu (SD_);
1329   TRACE_ALU_INPUT1 (GPR[rt]);
1330   if (fs == 25 || fs == 26 || fs == 28 || fs == 31)
1331       StoreFCR (fs, GPR[rt]);
1332   /* else NOP */
1333 }
1334
1335 :function:::void:do_cvt_d_fmt:int fmt, int fd, int fs, address_word instruction_0
1336 {
1337   check_fpu (SD_);
1338   if ((fmt == fmt_double) | 0)
1339     SignalException (ReservedInstruction, instruction_0);
1340   StoreFPR (fd, fmt_double, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1341             fmt_double));
1342 }
1343
1344 :function:::void:do_cvt_l_fmt:int fmt, int fd, int fs, address_word instruction_0
1345 {
1346   check_fpu (SD_);
1347   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
1348     SignalException (ReservedInstruction, instruction_0);
1349   StoreFPR (fd, fmt_long, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1350             fmt_long));
1351 }
1352
1353 :function:::void:do_cvt_ps_s:int fd, int fs, int ft, address_word instruction_0
1354 {
1355   check_fpu (SD_);
1356   check_u64 (SD_, instruction_0);
1357   StoreFPR (fd, fmt_ps, PackPS (ValueFPR (fs, fmt_single),
1358                                 ValueFPR (ft, fmt_single)));
1359 }
1360
1361 :function:::void:do_cvt_s_fmt:int fmt, int fd, int fs, address_word instruction_0
1362 {
1363   check_fpu (SD_);
1364   if ((fmt == fmt_single) | 0)
1365     SignalException (ReservedInstruction, instruction_0);
1366   StoreFPR (fd, fmt_single, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1367             fmt_single));
1368 }
1369
1370 :function:::void:do_cvt_s_pl:int fd, int fs, address_word instruction_0
1371 {
1372   check_fpu (SD_);
1373   check_u64 (SD_, instruction_0);
1374   StoreFPR (fd, fmt_single, PSLower (ValueFPR (fs, fmt_ps)));
1375 }
1376
1377 :function:::void:do_cvt_s_pu:int fd, int fs, address_word instruction_0
1378 {
1379   check_fpu (SD_);
1380   check_u64 (SD_, instruction_0);
1381   StoreFPR (fd, fmt_single, PSUpper (ValueFPR (fs, fmt_ps)));
1382 }
1383
1384 :function:::void:do_cvt_w_fmt:int fmt, int fd, int fs, address_word instruction_0
1385 {
1386   check_fpu (SD_);
1387   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
1388     SignalException (ReservedInstruction, instruction_0);
1389   StoreFPR (fd, fmt_word, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1390             fmt_word));
1391 }
1392
1393 :function:::void:do_div_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1394 {
1395   check_fpu (SD_);
1396   StoreFPR (fd, fmt, Divide (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1397 }
1398
1399 :function:::void:do_dmfc1b:int rt, int fs
1400 *mipsIV:
1401 *mipsV:
1402 *mips64:
1403 *mips64r2:
1404 *vr4100:
1405 *vr5000:
1406 *r3900:
1407 *micromips64:
1408 {
1409   if (SizeFGR () == 64)
1410     GPR[rt] = FGR[fs];
1411   else if ((fs & 0x1) == 0)
1412     GPR[rt] = SET64HI (FGR[fs+1]) | FGR[fs];
1413   else
1414     GPR[rt] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
1415   TRACE_ALU_RESULT (GPR[rt]);
1416 }
1417
1418 :function:::void:do_dmtc1b:int rt, int fs
1419 {
1420   if (SizeFGR () == 64)
1421     StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
1422   else if ((fs & 0x1) == 0)
1423     StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
1424   else
1425     Unpredictable ();
1426 }
1427
1428 :function:::void:do_floor_fmt:int type, int fmt, int fd, int fs
1429 {
1430   check_fpu (SD_);
1431   StoreFPR (fd, type, Convert (FP_RM_TOMINF, ValueFPR (fs, fmt), fmt,
1432             type));
1433 }
1434
1435 :function:::void:do_luxc1_32:int fd, int rindex, int rbase
1436 *mips32r2:
1437 *micromips32:
1438 {
1439   address_word base = GPR[rbase];
1440   address_word index = GPR[rindex];
1441   address_word vaddr = base + index;
1442   check_fpu (SD_);
1443   if (SizeFGR () != 64)
1444     Unpredictable ();
1445   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
1446   if ((vaddr & 0x7) != 0)
1447     index -= (vaddr & 0x7);
1448   COP_LD (1, fd, do_load_double (SD_, base, index));
1449 }
1450
1451 :function:::void:do_luxc1_64:int fd, int rindex, int rbase
1452 {
1453   address_word base = GPR[rbase];
1454   address_word index = GPR[rindex];
1455   address_word vaddr = base + index;
1456   if (SizeFGR () != 64)
1457     Unpredictable ();
1458   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
1459   if ((vaddr & 0x7) != 0)
1460     index -= (vaddr & 0x7);
1461   COP_LD (1, fd, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
1462
1463 }
1464
1465 :function:::void:do_lwc1:int ft, int offset, int base
1466 {
1467   check_fpu (SD_);
1468   COP_LW (1, ft, do_load (SD_, AccessLength_WORD, GPR[base],
1469                           EXTEND16 (offset)));
1470 }
1471
1472 :function:::void:do_lwxc1:int fd, int index, int base, address_word instruction_0
1473 {
1474   check_fpu (SD_);
1475   check_u64 (SD_, instruction_0);
1476   COP_LW (1, fd, do_load (SD_, AccessLength_WORD, GPR[base], GPR[index]));
1477 }
1478
1479 :function:::void:do_madd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1480 {
1481   check_fpu (SD_);
1482   check_u64 (SD_, instruction_0);
1483   check_fmt_p (SD_, fmt, instruction_0);
1484   StoreFPR (fd, fmt, MultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1485                                   ValueFPR (fr, fmt), fmt));
1486 }
1487
1488 :function:::void:do_mfc1b:int rt, int fs
1489 {
1490   check_fpu (SD_);
1491   GPR[rt] = EXTEND32 (FGR[fs]);
1492   TRACE_ALU_RESULT (GPR[rt]);
1493 }
1494
1495 :function:::void:do_mov_fmt:int fmt, int fd, int fs, address_word instruction_0
1496 {
1497   check_fpu (SD_);
1498   check_fmt_p (SD_, fmt, instruction_0);
1499   StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1500 }
1501
1502 :function:::void:do_movtf:int tf, int rd, int rs, int cc
1503 {
1504   check_fpu (SD_);
1505   if (GETFCC(cc) == tf)
1506     GPR[rd] = GPR[rs];
1507 }
1508
1509 :function:::void:do_movtf_fmt:int tf, int fmt, int fd, int fs, int cc
1510 {
1511   check_fpu (SD_);
1512   if (fmt != fmt_ps)
1513   {
1514     if (GETFCC(cc) == tf)
1515       StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1516     else
1517       StoreFPR (fd, fmt, ValueFPR (fd, fmt));   /* set fmt */
1518   }
1519   else
1520   {
1521     unsigned64 fdx;
1522     fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd,
1523                                       fmt_ps)),
1524                   PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd,
1525                                       fmt_ps)));
1526     StoreFPR (fd, fmt_ps, fdx);
1527   }
1528 }
1529
1530 :function:::void:do_movn_fmt:int fmt, int fd, int fs, int rt
1531 {
1532   check_fpu (SD_);
1533   if (GPR[rt] != 0)
1534     StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1535   else
1536     StoreFPR (fd, fmt, ValueFPR (fd, fmt));
1537 }
1538
1539 :function:::void:do_movz_fmt:int fmt, int fd, int fs, int rt
1540 {
1541   check_fpu (SD_);
1542   if (GPR[rt] == 0)
1543     StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1544   else
1545     StoreFPR (fd, fmt, ValueFPR (fd, fmt));
1546 }
1547
1548 :function:::void:do_msub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1549 {
1550   check_fpu (SD_);
1551   check_u64 (SD_, instruction_0);
1552   check_fmt_p (SD_, fmt, instruction_0);
1553   StoreFPR (fd, fmt, MultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1554                                   ValueFPR (fr, fmt), fmt));
1555 }
1556
1557 :function:::void:do_mtc1b:int rt, int fs
1558 {
1559   check_fpu (SD_);
1560   StoreFPR (fs, fmt_uninterpreted_32, VL4_8 (GPR[rt]));
1561 }
1562
1563 :function:::void:do_mul_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1564 {
1565   check_fpu (SD_);
1566   check_fmt_p (SD_, fmt, instruction_0);
1567   StoreFPR (fd, fmt, Multiply (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1568 }
1569
1570 :function:::void:do_neg_fmt:int fmt, int fd, int fs, address_word instruction_0
1571 {
1572   check_fpu (SD_);
1573   check_fmt_p (SD_, fmt, instruction_0);
1574   StoreFPR (fd, fmt, Negate (ValueFPR (fs, fmt), fmt));
1575 }
1576
1577 :function:::void:do_nmadd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1578 {
1579   check_fpu (SD_);
1580   check_u64 (SD_, instruction_0);
1581   check_fmt_p (SD_, fmt, instruction_0);
1582   StoreFPR (fd, fmt, NegMultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1583                                      ValueFPR (fr, fmt), fmt));
1584 }
1585
1586 :function:::void:do_nmsub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1587 {
1588   check_fpu (SD_);
1589   check_u64 (SD_, instruction_0);
1590   check_fmt_p (SD_, fmt, instruction_0);
1591   StoreFPR (fd, fmt, NegMultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1592                                      ValueFPR (fr, fmt), fmt));
1593 }
1594
1595 :function:::void:do_pll_ps:int fd, int fs, int ft, address_word instruction_0
1596 {
1597   check_fpu (SD_);
1598   check_u64 (SD_, instruction_0);
1599   StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
1600                                 PSLower (ValueFPR (ft, fmt_ps))));
1601 }
1602
1603 :function:::void:do_plu_ps:int fd, int fs, int ft, address_word instruction_0
1604 {
1605   check_fpu (SD_);
1606   check_u64 (SD_, instruction_0);
1607   StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
1608                                 PSUpper (ValueFPR (ft, fmt_ps))));
1609 }
1610
1611 :function:::void:do_pul_ps:int fd, int fs, int ft, address_word instruction_0
1612 {
1613   check_fpu (SD_);
1614   check_u64 (SD_, instruction_0);
1615   StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
1616                                 PSLower (ValueFPR (ft, fmt_ps))));
1617 }
1618
1619 :function:::void:do_puu_ps:int fd, int fs, int ft, address_word instruction_0
1620 {
1621   check_fpu (SD_);
1622   check_u64 (SD_, instruction_0);
1623   StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
1624                                 PSUpper (ValueFPR (ft, fmt_ps))));
1625 }
1626
1627 :function:::void:do_recip_fmt:int fmt, int fd, int fs
1628 {
1629   check_fpu (SD_);
1630   StoreFPR (fd, fmt, Recip (ValueFPR (fs, fmt), fmt));
1631 }
1632
1633 :function:::void:do_round_fmt:int type, int fmt, int fd, int fs
1634 {
1635   check_fpu (SD_);
1636   StoreFPR (fd, type, Convert (FP_RM_NEAREST, ValueFPR (fs, fmt), fmt,
1637             type));
1638 }
1639
1640 :function:::void:do_rsqrt_fmt:int fmt, int fd, int fs
1641 {
1642   check_fpu (SD_);
1643   StoreFPR (fd, fmt, RSquareRoot (ValueFPR (fs, fmt), fmt));
1644 }
1645
1646 :function:::void:do_prefx:int hint, int rindex, int rbase
1647 {
1648   address_word base = GPR[rbase];
1649   address_word index = GPR[rindex];
1650   {
1651     address_word vaddr = loadstore_ea (SD_, base, index);
1652     address_word paddr;
1653     int uncached;
1654     if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
1655                             isREAL))
1656       Prefetch (uncached, paddr, vaddr, isDATA, hint);
1657   }
1658 }
1659
1660 :function:::void:do_sdc1:int ft, int offset, int base
1661 *mipsII:
1662 *mips32:
1663 *mips32r2:
1664 *micromips32:
1665 {
1666   check_fpu (SD_);
1667   do_store_double (SD_, GPR[base], EXTEND16 (offset), COP_SD (1, ft));
1668 }
1669
1670 :function:::void:do_suxc1_32:int fs, int rindex, int rbase
1671 *mips32r2:
1672 *micromips32:
1673 {
1674   address_word base = GPR[rbase];
1675   address_word index = GPR[rindex];
1676   address_word vaddr = base + index;
1677   check_fpu (SD_);
1678   if (SizeFGR () != 64)
1679     Unpredictable ();
1680   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
1681   if ((vaddr & 0x7) != 0)
1682     index -= (vaddr & 0x7);
1683   do_store_double (SD_, base, index, COP_SD (1, fs));
1684 }
1685
1686 :function:::void:do_suxc1_64:int fs, int rindex, int rbase
1687 {
1688   address_word base = GPR[rbase];
1689   address_word index = GPR[rindex];
1690   address_word vaddr = base + index;
1691   if (SizeFGR () != 64)
1692     Unpredictable ();
1693   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
1694   if ((vaddr & 0x7) != 0)
1695     index -= (vaddr & 0x7);
1696   do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, fs));
1697 }
1698
1699 :function:::void:do_sqrt_fmt:int fmt, int fd, int fs
1700 {
1701   check_fpu (SD_);
1702   StoreFPR (fd, fmt,  (SquareRoot (ValueFPR (fs, fmt), fmt)));
1703 }
1704
1705 :function:::void:do_sub_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1706 {
1707   check_fpu (SD_);
1708   check_fmt_p (SD_, fmt, instruction_0);
1709   StoreFPR (fd, fmt, Sub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1710 }
1711
1712 :function:::void:do_swc1:int ft, int roffset, int rbase, address_word instruction_0
1713 {
1714   address_word base = GPR[rbase];
1715   address_word offset = EXTEND16 (roffset);
1716   check_fpu (SD_);
1717   {
1718     address_word vaddr = loadstore_ea (SD_, base, offset);
1719     address_word paddr;
1720     int uncached;
1721     if ((vaddr & 3) != 0)
1722       {
1723         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr,
1724                          write_transfer, sim_core_unaligned_signal);
1725       }
1726     else
1727       {
1728         if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1729                                 isTARGET, isREAL))
1730           {
1731             uword64 memval = 0;
1732             uword64 memval1 = 0;
1733             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1734             address_word reverseendian =
1735               (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
1736             address_word bigendiancpu =
1737               (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
1738             unsigned int byte;
1739             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1740             byte = ((vaddr & mask) ^ bigendiancpu);
1741             memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
1742             StoreMemory (uncached, AccessLength_WORD, memval, memval1, paddr,
1743                          vaddr, isREAL);
1744           }
1745       }
1746   }
1747 }
1748
1749 :function:::void:do_swxc1:int fs, int rindex, int rbase, address_word instruction_0
1750 {
1751   address_word base = GPR[rbase];
1752   address_word index = GPR[rindex];
1753   check_fpu (SD_);
1754   check_u64 (SD_, instruction_0);
1755     {
1756       address_word vaddr = loadstore_ea (SD_, base, index);
1757       address_word paddr;
1758       int uncached;
1759       if ((vaddr & 3) != 0)
1760         {
1761           SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
1762                            sim_core_unaligned_signal);
1763         }
1764       else
1765         {
1766           if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1767                                  isTARGET, isREAL))
1768             {
1769               unsigned64 memval = 0;
1770               unsigned64 memval1 = 0;
1771               unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1772               address_word reverseendian =
1773                 (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
1774               address_word bigendiancpu =
1775                 (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
1776               unsigned int byte;
1777               paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1778               byte = ((vaddr & mask) ^ bigendiancpu);
1779               memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
1780               StoreMemory (uncached, AccessLength_WORD, memval, memval1, paddr,
1781                            vaddr, isREAL);
1782             }
1783         }
1784   }
1785 }
1786
1787 :function:::void:do_trunc_fmt:int type, int fmt, int fd, int fs
1788 {
1789   check_fpu (SD_);
1790   StoreFPR (fd, type, Convert (FP_RM_TOZERO, ValueFPR (fs, fmt), fmt,
1791             type));
1792 }
1793
1794 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
1795 "add r<RD>, r<RS>, r<RT>"
1796 *mipsI:
1797 *mipsII:
1798 *mipsIII:
1799 *mipsIV:
1800 *mipsV:
1801 *mips32:
1802 *mips32r2:
1803 *mips64:
1804 *mips64r2:
1805 *vr4100:
1806 *vr5000:
1807 *r3900:
1808 {
1809   do_add (SD_, RS, RT, RD);
1810 }
1811
1812
1813
1814 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
1815 "addi r<RT>, r<RS>, <IMMEDIATE>"
1816 *mipsI:
1817 *mipsII:
1818 *mipsIII:
1819 *mipsIV:
1820 *mipsV:
1821 *mips32:
1822 *mips32r2:
1823 *mips64:
1824 *mips64r2:
1825 *vr4100:
1826 *vr5000:
1827 *r3900:
1828 {
1829   do_addi (SD_, RS, RT, IMMEDIATE);
1830 }
1831
1832
1833
1834 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
1835 {
1836   if (NotWordValue (GPR[rs]))
1837     Unpredictable ();
1838   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1839   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
1840   TRACE_ALU_RESULT (GPR[rt]);
1841 }
1842
1843 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
1844 "addiu r<RT>, r<RS>, <IMMEDIATE>"
1845 *mipsI:
1846 *mipsII:
1847 *mipsIII:
1848 *mipsIV:
1849 *mipsV:
1850 *mips32:
1851 *mips32r2:
1852 *mips64:
1853 *mips64r2:
1854 *vr4100:
1855 *vr5000:
1856 *r3900:
1857 {
1858   do_addiu (SD_, RS, RT, IMMEDIATE);
1859 }
1860
1861
1862
1863 :function:::void:do_addu:int rs, int rt, int rd
1864 {
1865   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1866     Unpredictable ();
1867   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1868   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
1869   TRACE_ALU_RESULT (GPR[rd]);
1870 }
1871
1872 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
1873 "addu r<RD>, r<RS>, r<RT>"
1874 *mipsI:
1875 *mipsII:
1876 *mipsIII:
1877 *mipsIV:
1878 *mipsV:
1879 *mips32:
1880 *mips32r2:
1881 *mips64:
1882 *mips64r2:
1883 *vr4100:
1884 *vr5000:
1885 *r3900:
1886 {
1887   do_addu (SD_, RS, RT, RD);
1888 }
1889
1890
1891
1892 :function:::void:do_and:int rs, int rt, int rd
1893 {
1894   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1895   GPR[rd] = GPR[rs] & GPR[rt];
1896   TRACE_ALU_RESULT (GPR[rd]);
1897 }
1898
1899 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
1900 "and r<RD>, r<RS>, r<RT>"
1901 *mipsI:
1902 *mipsII:
1903 *mipsIII:
1904 *mipsIV:
1905 *mipsV:
1906 *mips32:
1907 *mips32r2:
1908 *mips64:
1909 *mips64r2:
1910 *vr4100:
1911 *vr5000:
1912 *r3900:
1913 {
1914   do_and (SD_, RS, RT, RD);
1915 }
1916
1917
1918
1919 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
1920 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
1921 *mipsI:
1922 *mipsII:
1923 *mipsIII:
1924 *mipsIV:
1925 *mipsV:
1926 *mips32:
1927 *mips32r2:
1928 *mips64:
1929 *mips64r2:
1930 *vr4100:
1931 *vr5000:
1932 *r3900:
1933 {
1934   do_andi (SD_,RS, RT, IMMEDIATE);
1935 }
1936
1937
1938
1939 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
1940 "beq r<RS>, r<RT>, <OFFSET>"
1941 *mipsI:
1942 *mipsII:
1943 *mipsIII:
1944 *mipsIV:
1945 *mipsV:
1946 *mips32:
1947 *mips32r2:
1948 *mips64:
1949 *mips64r2:
1950 *vr4100:
1951 *vr5000:
1952 *r3900:
1953 {
1954   address_word offset = EXTEND16 (OFFSET) << 2;
1955   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
1956     {
1957       DELAY_SLOT (NIA + offset);
1958     }
1959 }
1960
1961
1962
1963 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
1964 "beql r<RS>, r<RT>, <OFFSET>"
1965 *mipsII:
1966 *mipsIII:
1967 *mipsIV:
1968 *mipsV:
1969 *mips32:
1970 *mips32r2:
1971 *mips64:
1972 *mips64r2:
1973 *vr4100:
1974 *vr5000:
1975 *r3900:
1976 {
1977   address_word offset = EXTEND16 (OFFSET) << 2;
1978   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
1979     {
1980       DELAY_SLOT (NIA + offset);
1981     }
1982   else
1983     NULLIFY_NEXT_INSTRUCTION ();
1984 }
1985
1986
1987
1988 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
1989 "bgez r<RS>, <OFFSET>"
1990 *mipsI:
1991 *mipsII:
1992 *mipsIII:
1993 *mipsIV:
1994 *mipsV:
1995 *mips32:
1996 *mips32r2:
1997 *mips64:
1998 *mips64r2:
1999 *vr4100:
2000 *vr5000:
2001 *r3900:
2002 {
2003   address_word offset = EXTEND16 (OFFSET) << 2;
2004   if ((signed_word) GPR[RS] >= 0)
2005     {
2006       DELAY_SLOT (NIA + offset);
2007     }
2008 }
2009
2010
2011
2012 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
2013 "bgezal r<RS>, <OFFSET>"
2014 *mipsI:
2015 *mipsII:
2016 *mipsIII:
2017 *mipsIV:
2018 *mipsV:
2019 *mips32:
2020 *mips32r2:
2021 *mips64:
2022 *mips64r2:
2023 *vr4100:
2024 *vr5000:
2025 *r3900:
2026 {
2027   address_word offset = EXTEND16 (OFFSET) << 2;
2028   if (RS == 31)
2029     Unpredictable ();
2030   RA = (CIA + 8);
2031   if ((signed_word) GPR[RS] >= 0)
2032     {
2033       DELAY_SLOT (NIA + offset);
2034     }
2035 }
2036
2037
2038
2039 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
2040 "bgezall r<RS>, <OFFSET>"
2041 *mipsII:
2042 *mipsIII:
2043 *mipsIV:
2044 *mipsV:
2045 *mips32:
2046 *mips32r2:
2047 *mips64:
2048 *mips64r2:
2049 *vr4100:
2050 *vr5000:
2051 *r3900:
2052 {
2053   address_word offset = EXTEND16 (OFFSET) << 2;
2054   if (RS == 31)
2055     Unpredictable ();
2056   RA = (CIA + 8);
2057   /* NOTE: The branch occurs AFTER the next instruction has been
2058      executed */
2059   if ((signed_word) GPR[RS] >= 0)
2060     {
2061       DELAY_SLOT (NIA + offset);
2062     }
2063   else
2064     NULLIFY_NEXT_INSTRUCTION ();
2065 }
2066
2067
2068
2069 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
2070 "bgezl r<RS>, <OFFSET>"
2071 *mipsII:
2072 *mipsIII:
2073 *mipsIV:
2074 *mipsV:
2075 *mips32:
2076 *mips32r2:
2077 *mips64:
2078 *mips64r2:
2079 *vr4100:
2080 *vr5000:
2081 *r3900:
2082 {
2083   address_word offset = EXTEND16 (OFFSET) << 2;
2084   if ((signed_word) GPR[RS] >= 0)
2085     {
2086       DELAY_SLOT (NIA + offset);
2087     }
2088   else
2089     NULLIFY_NEXT_INSTRUCTION ();
2090 }
2091
2092
2093
2094 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
2095 "bgtz r<RS>, <OFFSET>"
2096 *mipsI:
2097 *mipsII:
2098 *mipsIII:
2099 *mipsIV:
2100 *mipsV:
2101 *mips32:
2102 *mips32r2:
2103 *mips64:
2104 *mips64r2:
2105 *vr4100:
2106 *vr5000:
2107 *r3900:
2108 {
2109   address_word offset = EXTEND16 (OFFSET) << 2;
2110   if ((signed_word) GPR[RS] > 0)
2111     {
2112       DELAY_SLOT (NIA + offset);
2113     }
2114 }
2115
2116
2117
2118 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
2119 "bgtzl r<RS>, <OFFSET>"
2120 *mipsII:
2121 *mipsIII:
2122 *mipsIV:
2123 *mipsV:
2124 *mips32:
2125 *mips32r2:
2126 *mips64:
2127 *mips64r2:
2128 *vr4100:
2129 *vr5000:
2130 *r3900:
2131 {
2132   address_word offset = EXTEND16 (OFFSET) << 2;
2133   /* NOTE: The branch occurs AFTER the next instruction has been
2134      executed */
2135   if ((signed_word) GPR[RS] > 0)
2136     {
2137       DELAY_SLOT (NIA + offset);
2138     }
2139   else
2140     NULLIFY_NEXT_INSTRUCTION ();
2141 }
2142
2143
2144
2145 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
2146 "blez r<RS>, <OFFSET>"
2147 *mipsI:
2148 *mipsII:
2149 *mipsIII:
2150 *mipsIV:
2151 *mipsV:
2152 *mips32:
2153 *mips32r2:
2154 *mips64:
2155 *mips64r2:
2156 *vr4100:
2157 *vr5000:
2158 *r3900:
2159 {
2160   address_word offset = EXTEND16 (OFFSET) << 2;
2161   /* NOTE: The branch occurs AFTER the next instruction has been
2162      executed */
2163   if ((signed_word) GPR[RS] <= 0)
2164     {
2165       DELAY_SLOT (NIA + offset);
2166     }
2167 }
2168
2169
2170
2171 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
2172 "bgezl r<RS>, <OFFSET>"
2173 *mipsII:
2174 *mipsIII:
2175 *mipsIV:
2176 *mipsV:
2177 *mips32:
2178 *mips32r2:
2179 *mips64:
2180 *mips64r2:
2181 *vr4100:
2182 *vr5000:
2183 *r3900:
2184 {
2185   address_word offset = EXTEND16 (OFFSET) << 2;
2186   if ((signed_word) GPR[RS] <= 0)
2187     {
2188       DELAY_SLOT (NIA + offset);
2189     }
2190   else
2191     NULLIFY_NEXT_INSTRUCTION ();
2192 }
2193
2194
2195
2196 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
2197 "bltz r<RS>, <OFFSET>"
2198 *mipsI:
2199 *mipsII:
2200 *mipsIII:
2201 *mipsIV:
2202 *mipsV:
2203 *mips32:
2204 *mips32r2:
2205 *mips64:
2206 *mips64r2:
2207 *vr4100:
2208 *vr5000:
2209 *r3900:
2210 {
2211   address_word offset = EXTEND16 (OFFSET) << 2;
2212   if ((signed_word) GPR[RS] < 0)
2213     {
2214       DELAY_SLOT (NIA + offset);
2215     }
2216 }
2217
2218
2219
2220 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
2221 "bltzal r<RS>, <OFFSET>"
2222 *mipsI:
2223 *mipsII:
2224 *mipsIII:
2225 *mipsIV:
2226 *mipsV:
2227 *mips32:
2228 *mips32r2:
2229 *mips64:
2230 *mips64r2:
2231 *vr4100:
2232 *vr5000:
2233 *r3900:
2234 {
2235   address_word offset = EXTEND16 (OFFSET) << 2;
2236   if (RS == 31)
2237     Unpredictable ();
2238   RA = (CIA + 8);
2239   /* NOTE: The branch occurs AFTER the next instruction has been
2240      executed */
2241   if ((signed_word) GPR[RS] < 0)
2242     {
2243       DELAY_SLOT (NIA + offset);
2244     }
2245 }
2246
2247
2248
2249 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
2250 "bltzall r<RS>, <OFFSET>"
2251 *mipsII:
2252 *mipsIII:
2253 *mipsIV:
2254 *mipsV:
2255 *mips32:
2256 *mips32r2:
2257 *mips64:
2258 *mips64r2:
2259 *vr4100:
2260 *vr5000:
2261 *r3900:
2262 {
2263   address_word offset = EXTEND16 (OFFSET) << 2;
2264   if (RS == 31)
2265     Unpredictable ();
2266   RA = (CIA + 8);
2267   if ((signed_word) GPR[RS] < 0)
2268     {
2269       DELAY_SLOT (NIA + offset);
2270     }
2271   else
2272     NULLIFY_NEXT_INSTRUCTION ();
2273 }
2274
2275
2276
2277 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
2278 "bltzl r<RS>, <OFFSET>"
2279 *mipsII:
2280 *mipsIII:
2281 *mipsIV:
2282 *mipsV:
2283 *mips32:
2284 *mips32r2:
2285 *mips64:
2286 *mips64r2:
2287 *vr4100:
2288 *vr5000:
2289 *r3900:
2290 {
2291   address_word offset = EXTEND16 (OFFSET) << 2;
2292   /* NOTE: The branch occurs AFTER the next instruction has been
2293      executed */
2294   if ((signed_word) GPR[RS] < 0)
2295     {
2296       DELAY_SLOT (NIA + offset);
2297     }
2298   else
2299     NULLIFY_NEXT_INSTRUCTION ();
2300 }
2301
2302
2303
2304 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
2305 "bne r<RS>, r<RT>, <OFFSET>"
2306 *mipsI:
2307 *mipsII:
2308 *mipsIII:
2309 *mipsIV:
2310 *mipsV:
2311 *mips32:
2312 *mips32r2:
2313 *mips64:
2314 *mips64r2:
2315 *vr4100:
2316 *vr5000:
2317 *r3900:
2318 {
2319   address_word offset = EXTEND16 (OFFSET) << 2;
2320   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2321     {
2322       DELAY_SLOT (NIA + offset);
2323     }
2324 }
2325
2326
2327
2328 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
2329 "bnel r<RS>, r<RT>, <OFFSET>"
2330 *mipsII:
2331 *mipsIII:
2332 *mipsIV:
2333 *mipsV:
2334 *mips32:
2335 *mips32r2:
2336 *mips64:
2337 *mips64r2:
2338 *vr4100:
2339 *vr5000:
2340 *r3900:
2341 {
2342   address_word offset = EXTEND16 (OFFSET) << 2;
2343   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2344     {
2345       DELAY_SLOT (NIA + offset);
2346     }
2347   else
2348     NULLIFY_NEXT_INSTRUCTION ();
2349 }
2350
2351
2352
2353 000000,20.CODE,001101:SPECIAL:32::BREAK
2354 "break %#lx<CODE>"
2355 *mipsI:
2356 *mipsII:
2357 *mipsIII:
2358 *mipsIV:
2359 *mipsV:
2360 *mips32:
2361 *mips32r2:
2362 *mips64:
2363 *mips64r2:
2364 *vr4100:
2365 *vr5000:
2366 *r3900:
2367 {
2368   do_break (SD_, instruction_0);
2369 }
2370
2371
2372
2373 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
2374 "clo r<RD>, r<RS>"
2375 *mips32:
2376 *mips32r2:
2377 *mips64:
2378 *mips64r2:
2379 *vr5500:
2380 {
2381   if (RT != RD)
2382     Unpredictable ();
2383   do_clo (SD_, RD, RS);
2384 }
2385
2386
2387
2388 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
2389 "clz r<RD>, r<RS>"
2390 *mips32:
2391 *mips32r2:
2392 *mips64:
2393 *mips64r2:
2394 *vr5500:
2395 {
2396   if (RT != RD)
2397     Unpredictable ();
2398   do_clz (SD_, RD, RS);
2399 }
2400
2401
2402
2403 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
2404 "dadd r<RD>, r<RS>, r<RT>"
2405 *mipsIII:
2406 *mipsIV:
2407 *mipsV:
2408 *mips64:
2409 *mips64r2:
2410 *vr4100:
2411 *vr5000:
2412 {
2413   check_u64 (SD_, instruction_0);
2414   do_dadd (SD_, RD, RS, RT);
2415 }
2416
2417
2418
2419 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
2420 "daddi r<RT>, r<RS>, <IMMEDIATE>"
2421 *mipsIII:
2422 *mipsIV:
2423 *mipsV:
2424 *mips64:
2425 *mips64r2:
2426 *vr4100:
2427 *vr5000:
2428 {
2429   check_u64 (SD_, instruction_0);
2430   do_daddi (SD_, RT, RS, IMMEDIATE);
2431 }
2432
2433
2434
2435 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
2436 {
2437   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2438   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
2439   TRACE_ALU_RESULT (GPR[rt]);
2440 }
2441
2442 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
2443 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
2444 *mipsIII:
2445 *mipsIV:
2446 *mipsV:
2447 *mips64:
2448 *mips64r2:
2449 *vr4100:
2450 *vr5000:
2451 {
2452   check_u64 (SD_, instruction_0);
2453   do_daddiu (SD_, RS, RT, IMMEDIATE);
2454 }
2455
2456
2457
2458 :function:::void:do_daddu:int rs, int rt, int rd
2459 {
2460   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2461   GPR[rd] = GPR[rs] + GPR[rt];
2462   TRACE_ALU_RESULT (GPR[rd]);
2463 }
2464
2465 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
2466 "daddu r<RD>, r<RS>, r<RT>"
2467 *mipsIII:
2468 *mipsIV:
2469 *mipsV:
2470 *mips64:
2471 *mips64r2:
2472 *vr4100:
2473 *vr5000:
2474 {
2475   check_u64 (SD_, instruction_0);
2476   do_daddu (SD_, RS, RT, RD);
2477 }
2478
2479
2480
2481 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
2482 "dclo r<RD>, r<RS>"
2483 *mips64:
2484 *mips64r2:
2485 *vr5500:
2486 {
2487   if (RT != RD)
2488     Unpredictable ();
2489   check_u64 (SD_, instruction_0);
2490   do_dclo (SD_, RD, RS);
2491 }
2492
2493
2494
2495 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
2496 "dclz r<RD>, r<RS>"
2497 *mips64:
2498 *mips64r2:
2499 *vr5500:
2500 {
2501   if (RT != RD)
2502     Unpredictable ();
2503   check_u64 (SD_, instruction_0);
2504   do_dclz (SD_, RD, RS);
2505 }
2506
2507
2508
2509 :function:::void:do_ddiv:int rs, int rt
2510 {
2511   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2512   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2513   {
2514     signed64 n = GPR[rs];
2515     signed64 d = GPR[rt];
2516     signed64 hi;
2517     signed64 lo;
2518     if (d == 0)
2519       {
2520         lo = SIGNED64 (0x8000000000000000);
2521         hi = 0;
2522       }
2523     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
2524       {
2525         lo = SIGNED64 (0x8000000000000000);
2526         hi = 0;
2527       }
2528     else
2529       {
2530         lo = (n / d);
2531         hi = (n % d);
2532       }
2533     HI = hi;
2534     LO = lo;
2535   }
2536   TRACE_ALU_RESULT2 (HI, LO);
2537 }
2538
2539 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
2540 "ddiv r<RS>, r<RT>"
2541 *mipsIII:
2542 *mipsIV:
2543 *mipsV:
2544 *mips64:
2545 *mips64r2:
2546 *vr4100:
2547 *vr5000:
2548 {
2549   check_u64 (SD_, instruction_0);
2550   do_ddiv (SD_, RS, RT);
2551 }
2552
2553
2554
2555 :function:::void:do_ddivu:int rs, int rt
2556 {
2557   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2558   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2559   {
2560     unsigned64 n = GPR[rs];
2561     unsigned64 d = GPR[rt];
2562     unsigned64 hi;
2563     unsigned64 lo;
2564     if (d == 0)
2565       {
2566         lo = SIGNED64 (0x8000000000000000);
2567         hi = 0;
2568       }
2569     else
2570       {
2571         lo = (n / d);
2572         hi = (n % d);
2573       }
2574     HI = hi;
2575     LO = lo;
2576   }
2577   TRACE_ALU_RESULT2 (HI, LO);
2578 }
2579
2580 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
2581 "ddivu r<RS>, r<RT>"
2582 *mipsIII:
2583 *mipsIV:
2584 *mipsV:
2585 *mips64:
2586 *mips64r2:
2587 *vr4100:
2588 *vr5000:
2589 {
2590   check_u64 (SD_, instruction_0);
2591   do_ddivu (SD_, RS, RT);
2592 }
2593
2594 :function:::void:do_div:int rs, int rt
2595 {
2596   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2597   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2598   {
2599     signed32 n = GPR[rs];
2600     signed32 d = GPR[rt];
2601     if (d == 0)
2602       {
2603         LO = EXTEND32 (0x80000000);
2604         HI = EXTEND32 (0);
2605       }
2606     else if (n == SIGNED32 (0x80000000) && d == -1)
2607       {
2608         LO = EXTEND32 (0x80000000);
2609         HI = EXTEND32 (0);
2610       }
2611     else
2612       {
2613         LO = EXTEND32 (n / d);
2614         HI = EXTEND32 (n % d);
2615       }
2616   }
2617   TRACE_ALU_RESULT2 (HI, LO);
2618 }
2619
2620 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
2621 "div r<RS>, r<RT>"
2622 *mipsI:
2623 *mipsII:
2624 *mipsIII:
2625 *mipsIV:
2626 *mipsV:
2627 *mips32:
2628 *mips32r2:
2629 *mips64:
2630 *mips64r2:
2631 *vr4100:
2632 *vr5000:
2633 *r3900:
2634 {
2635   do_div (SD_, RS, RT);
2636 }
2637
2638
2639
2640 :function:::void:do_divu:int rs, int rt
2641 {
2642   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2643   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2644   {
2645     unsigned32 n = GPR[rs];
2646     unsigned32 d = GPR[rt];
2647     if (d == 0)
2648       {
2649         LO = EXTEND32 (0x80000000);
2650         HI = EXTEND32 (0);
2651       }
2652     else
2653       {
2654         LO = EXTEND32 (n / d);
2655         HI = EXTEND32 (n % d);
2656       }
2657   }
2658   TRACE_ALU_RESULT2 (HI, LO);
2659 }
2660
2661 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
2662 "divu r<RS>, r<RT>"
2663 *mipsI:
2664 *mipsII:
2665 *mipsIII:
2666 *mipsIV:
2667 *mipsV:
2668 *mips32:
2669 *mips32r2:
2670 *mips64:
2671 *mips64r2:
2672 *vr4100:
2673 *vr5000:
2674 *r3900:
2675 {
2676   do_divu (SD_, RS, RT);
2677 }
2678
2679
2680 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
2681 {
2682   unsigned64 lo;
2683   unsigned64 hi;
2684   unsigned64 m00;
2685   unsigned64 m01;
2686   unsigned64 m10;
2687   unsigned64 m11;
2688   unsigned64 mid;
2689   int sign;
2690   unsigned64 op1 = GPR[rs];
2691   unsigned64 op2 = GPR[rt];
2692   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2693   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2694   /* make signed multiply unsigned */
2695   sign = 0;
2696   if (signed_p)
2697     {
2698       if ((signed64) op1 < 0)
2699         {
2700           op1 = - op1;
2701           ++sign;
2702         }
2703       if ((signed64) op2 < 0)
2704         {
2705           op2 = - op2;
2706           ++sign;
2707         }
2708     }
2709   /* multiply out the 4 sub products */
2710   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
2711   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
2712   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
2713   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
2714   /* add the products */
2715   mid = ((unsigned64) VH4_8 (m00)
2716          + (unsigned64) VL4_8 (m10)
2717          + (unsigned64) VL4_8 (m01));
2718   lo = U8_4 (mid, m00);
2719   hi = (m11
2720         + (unsigned64) VH4_8 (mid)
2721         + (unsigned64) VH4_8 (m01)
2722         + (unsigned64) VH4_8 (m10));
2723   /* fix the sign */
2724   if (sign & 1)
2725     {
2726       lo = -lo;
2727       if (lo == 0)
2728         hi = -hi;
2729       else
2730         hi = -hi - 1;
2731     }
2732   /* save the result HI/LO (and a gpr) */
2733   LO = lo;
2734   HI = hi;
2735   if (rd != 0)
2736     GPR[rd] = lo;
2737   TRACE_ALU_RESULT2 (HI, LO);
2738 }
2739
2740 :function:::void:do_dmult:int rs, int rt, int rd
2741 {
2742   do_dmultx (SD_, rs, rt, rd, 1);
2743 }
2744
2745 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
2746 "dmult r<RS>, r<RT>"
2747 *mipsIII:
2748 *mipsIV:
2749 *mipsV:
2750 *mips64:
2751 *mips64r2:
2752 *vr4100:
2753 {
2754   check_u64 (SD_, instruction_0);
2755   do_dmult (SD_, RS, RT, 0);
2756 }
2757
2758 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
2759 "dmult r<RS>, r<RT>":RD == 0
2760 "dmult r<RD>, r<RS>, r<RT>"
2761 *vr5000:
2762 {
2763   check_u64 (SD_, instruction_0);
2764   do_dmult (SD_, RS, RT, RD);
2765 }
2766
2767
2768
2769 :function:::void:do_dmultu:int rs, int rt, int rd
2770 {
2771   do_dmultx (SD_, rs, rt, rd, 0);
2772 }
2773
2774 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
2775 "dmultu r<RS>, r<RT>"
2776 *mipsIII:
2777 *mipsIV:
2778 *mipsV:
2779 *mips64:
2780 *mips64r2:
2781 *vr4100:
2782 {
2783   check_u64 (SD_, instruction_0);
2784   do_dmultu (SD_, RS, RT, 0);
2785 }
2786
2787 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
2788 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
2789 "dmultu r<RS>, r<RT>"
2790 *vr5000:
2791 {
2792   check_u64 (SD_, instruction_0);
2793   do_dmultu (SD_, RS, RT, RD);
2794 }
2795
2796
2797 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
2798 {
2799   unsigned64 result;
2800
2801   y &= 63;
2802   TRACE_ALU_INPUT2 (x, y);
2803   result = ROTR64 (x, y);
2804   TRACE_ALU_RESULT (result);
2805   return result;
2806 }
2807
2808 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
2809 "dror r<RD>, r<RT>, <SHIFT>"
2810 *mips64r2:
2811 *vr5400:
2812 *vr5500:
2813 {
2814   check_u64 (SD_, instruction_0);
2815   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
2816 }
2817
2818 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
2819 "dror32 r<RD>, r<RT>, <SHIFT>"
2820 *mips64r2:
2821 *vr5400:
2822 *vr5500:
2823 {
2824   check_u64 (SD_, instruction_0);
2825   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
2826 }
2827
2828 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
2829 "drorv r<RD>, r<RT>, r<RS>"
2830 *mips64r2:
2831 *vr5400:
2832 *vr5500:
2833 {
2834   check_u64 (SD_, instruction_0);
2835   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
2836 }
2837
2838
2839 :function:::void:do_dsll:int rt, int rd, int shift
2840 {
2841   TRACE_ALU_INPUT2 (GPR[rt], shift);
2842   GPR[rd] = GPR[rt] << shift;
2843   TRACE_ALU_RESULT (GPR[rd]);
2844 }
2845
2846 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
2847 "dsll r<RD>, r<RT>, <SHIFT>"
2848 *mipsIII:
2849 *mipsIV:
2850 *mipsV:
2851 *mips64:
2852 *mips64r2:
2853 *vr4100:
2854 *vr5000:
2855 {
2856   check_u64 (SD_, instruction_0);
2857   do_dsll (SD_, RT, RD, SHIFT);
2858 }
2859
2860
2861 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
2862 "dsll32 r<RD>, r<RT>, <SHIFT>"
2863 *mipsIII:
2864 *mipsIV:
2865 *mipsV:
2866 *mips64:
2867 *mips64r2:
2868 *vr4100:
2869 *vr5000:
2870 {
2871   check_u64 (SD_, instruction_0);
2872   do_dsll32 (SD_, RD, RT, SHIFT);
2873 }
2874
2875 :function:::void:do_dsllv:int rs, int rt, int rd
2876 {
2877   int s = MASKED64 (GPR[rs], 5, 0);
2878   TRACE_ALU_INPUT2 (GPR[rt], s);
2879   GPR[rd] = GPR[rt] << s;
2880   TRACE_ALU_RESULT (GPR[rd]);
2881 }
2882
2883 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
2884 "dsllv r<RD>, r<RT>, r<RS>"
2885 *mipsIII:
2886 *mipsIV:
2887 *mipsV:
2888 *mips64:
2889 *mips64r2:
2890 *vr4100:
2891 *vr5000:
2892 {
2893   check_u64 (SD_, instruction_0);
2894   do_dsllv (SD_, RS, RT, RD);
2895 }
2896
2897 :function:::void:do_dsra:int rt, int rd, int shift
2898 {
2899   TRACE_ALU_INPUT2 (GPR[rt], shift);
2900   GPR[rd] = ((signed64) GPR[rt]) >> shift;
2901   TRACE_ALU_RESULT (GPR[rd]);
2902 }
2903
2904
2905 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
2906 "dsra r<RD>, r<RT>, <SHIFT>"
2907 *mipsIII:
2908 *mipsIV:
2909 *mipsV:
2910 *mips64:
2911 *mips64r2:
2912 *vr4100:
2913 *vr5000:
2914 {
2915   check_u64 (SD_, instruction_0);
2916   do_dsra (SD_, RT, RD, SHIFT);
2917 }
2918
2919
2920 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
2921 "dsra32 r<RD>, r<RT>, <SHIFT>"
2922 *mipsIII:
2923 *mipsIV:
2924 *mipsV:
2925 *mips64:
2926 *mips64r2:
2927 *vr4100:
2928 *vr5000:
2929 {
2930   check_u64 (SD_, instruction_0);
2931   do_dsra32 (SD_, RD, RT, SHIFT);
2932 }
2933
2934
2935 :function:::void:do_dsrav:int rs, int rt, int rd
2936 {
2937   int s = MASKED64 (GPR[rs], 5, 0);
2938   TRACE_ALU_INPUT2 (GPR[rt], s);
2939   GPR[rd] = ((signed64) GPR[rt]) >> s;
2940   TRACE_ALU_RESULT (GPR[rd]);
2941 }
2942
2943 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
2944 "dsrav r<RD>, r<RT>, r<RS>"
2945 *mipsIII:
2946 *mipsIV:
2947 *mipsV:
2948 *mips64:
2949 *mips64r2:
2950 *vr4100:
2951 *vr5000:
2952 {
2953   check_u64 (SD_, instruction_0);
2954   do_dsrav (SD_, RS, RT, RD);
2955 }
2956
2957 :function:::void:do_dsrl:int rt, int rd, int shift
2958 {
2959   TRACE_ALU_INPUT2 (GPR[rt], shift);
2960   GPR[rd] = (unsigned64) GPR[rt] >> shift;
2961   TRACE_ALU_RESULT (GPR[rd]);
2962 }
2963
2964
2965 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
2966 "dsrl r<RD>, r<RT>, <SHIFT>"
2967 *mipsIII:
2968 *mipsIV:
2969 *mipsV:
2970 *mips64:
2971 *mips64r2:
2972 *vr4100:
2973 *vr5000:
2974 {
2975   check_u64 (SD_, instruction_0);
2976   do_dsrl (SD_, RT, RD, SHIFT);
2977 }
2978
2979
2980 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
2981 "dsrl32 r<RD>, r<RT>, <SHIFT>"
2982 *mipsIII:
2983 *mipsIV:
2984 *mipsV:
2985 *mips64:
2986 *mips64r2:
2987 *vr4100:
2988 *vr5000:
2989 {
2990   check_u64 (SD_, instruction_0);
2991   do_dsrl32 (SD_, RD, RT, SHIFT);
2992 }
2993
2994
2995 :function:::void:do_dsrlv:int rs, int rt, int rd
2996 {
2997   int s = MASKED64 (GPR[rs], 5, 0);
2998   TRACE_ALU_INPUT2 (GPR[rt], s);
2999   GPR[rd] = (unsigned64) GPR[rt] >> s;
3000   TRACE_ALU_RESULT (GPR[rd]);
3001 }
3002
3003
3004
3005 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
3006 "dsrlv r<RD>, r<RT>, r<RS>"
3007 *mipsIII:
3008 *mipsIV:
3009 *mipsV:
3010 *mips64:
3011 *mips64r2:
3012 *vr4100:
3013 *vr5000:
3014 {
3015   check_u64 (SD_, instruction_0);
3016   do_dsrlv (SD_, RS, RT, RD);
3017 }
3018
3019
3020 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
3021 "dsub r<RD>, r<RS>, r<RT>"
3022 *mipsIII:
3023 *mipsIV:
3024 *mipsV:
3025 *mips64:
3026 *mips64r2:
3027 *vr4100:
3028 *vr5000:
3029 {
3030   check_u64 (SD_, instruction_0);
3031   do_dsub (SD_, RD, RS, RT);
3032 }
3033
3034
3035 :function:::void:do_dsubu:int rs, int rt, int rd
3036 {
3037   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3038   GPR[rd] = GPR[rs] - GPR[rt];
3039   TRACE_ALU_RESULT (GPR[rd]);
3040 }
3041
3042 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
3043 "dsubu r<RD>, r<RS>, r<RT>"
3044 *mipsIII:
3045 *mipsIV:
3046 *mipsV:
3047 *mips64:
3048 *mips64r2:
3049 *vr4100:
3050 *vr5000:
3051 {
3052   check_u64 (SD_, instruction_0);
3053   do_dsubu (SD_, RS, RT, RD);
3054 }
3055
3056
3057 000010,26.INSTR_INDEX:NORMAL:32::J
3058 "j <INSTR_INDEX>"
3059 *mipsI:
3060 *mipsII:
3061 *mipsIII:
3062 *mipsIV:
3063 *mipsV:
3064 *mips32:
3065 *mips32r2:
3066 *mips64:
3067 *mips64r2:
3068 *vr4100:
3069 *vr5000:
3070 *r3900:
3071 {
3072   /* NOTE: The region used is that of the delay slot NIA and NOT the
3073      current instruction */
3074   address_word region = (NIA & MASK (63, 28));
3075   DELAY_SLOT (region | (INSTR_INDEX << 2));
3076 }
3077
3078
3079 000011,26.INSTR_INDEX:NORMAL:32::JAL
3080 "jal <INSTR_INDEX>"
3081 *mipsI:
3082 *mipsII:
3083 *mipsIII:
3084 *mipsIV:
3085 *mipsV:
3086 *mips32:
3087 *mips32r2:
3088 *mips64:
3089 *mips64r2:
3090 *vr4100:
3091 *vr5000:
3092 *r3900:
3093 {
3094   /* NOTE: The region used is that of the delay slot and NOT the
3095      current instruction */
3096   address_word region = (NIA & MASK (63, 28));
3097   GPR[31] = CIA + 8;
3098   DELAY_SLOT (region | (INSTR_INDEX << 2));
3099 }
3100
3101 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
3102 "jalr r<RS>":RD == 31
3103 "jalr r<RD>, r<RS>"
3104 *mipsI:
3105 *mipsII:
3106 *mipsIII:
3107 *mipsIV:
3108 *mipsV:
3109 *mips32:
3110 *mips32r2:
3111 *mips64:
3112 *mips64r2:
3113 *vr4100:
3114 *vr5000:
3115 *r3900:
3116 {
3117   address_word temp = GPR[RS];
3118   GPR[RD] = CIA + 8;
3119   DELAY_SLOT (temp);
3120 }
3121
3122 000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
3123 "jalr.hb r<RS>":RD == 31
3124 "jalr.hb r<RD>, r<RS>"
3125 *mips32r2:
3126 *mips64r2:
3127 {
3128   address_word temp = GPR[RS];
3129   GPR[RD] = CIA + 8;
3130   DELAY_SLOT (temp);
3131 }
3132
3133 000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
3134 "jr r<RS>"
3135 *mipsI:
3136 *mipsII:
3137 *mipsIII:
3138 *mipsIV:
3139 *mipsV:
3140 *mips32:
3141 *mips32r2:
3142 *mips64:
3143 *mips64r2:
3144 *vr4100:
3145 *vr5000:
3146 *r3900:
3147 {
3148   DELAY_SLOT (GPR[RS]);
3149 }
3150
3151 000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
3152 "jr.hb r<RS>"
3153 *mips32r2:
3154 *mips64r2:
3155 {
3156   DELAY_SLOT (GPR[RS]);
3157 }
3158
3159 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
3160 {
3161   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3162   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3163   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3164   unsigned int byte;
3165   address_word paddr;
3166   int uncached;
3167   unsigned64 memval;
3168   address_word vaddr;
3169
3170   vaddr = loadstore_ea (SD_, base, offset);
3171   if ((vaddr & access) != 0)
3172     {
3173       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
3174     }
3175   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
3176   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3177   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
3178   byte = ((vaddr & mask) ^ bigendiancpu);
3179   return (memval >> (8 * byte));
3180 }
3181
3182 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3183 {
3184   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3185   address_word reverseendian = (ReverseEndian ? -1 : 0);
3186   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3187   unsigned int byte;
3188   unsigned int word;
3189   address_word paddr;
3190   int uncached;
3191   unsigned64 memval;
3192   address_word vaddr;
3193   int nr_lhs_bits;
3194   int nr_rhs_bits;
3195   unsigned_word lhs_mask;
3196   unsigned_word temp;
3197
3198   vaddr = loadstore_ea (SD_, base, offset);
3199   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
3200   paddr = (paddr ^ (reverseendian & mask));
3201   if (BigEndianMem == 0)
3202     paddr = paddr & ~access;
3203
3204   /* compute where within the word/mem we are */
3205   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3206   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3207   nr_lhs_bits = 8 * byte + 8;
3208   nr_rhs_bits = 8 * access - 8 * byte;
3209   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3210
3211   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3212            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3213            (long) ((unsigned64) paddr >> 32), (long) paddr,
3214            word, byte, nr_lhs_bits, nr_rhs_bits); */
3215
3216   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
3217   if (word == 0)
3218     {
3219       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
3220       temp = (memval << nr_rhs_bits);
3221     }
3222   else
3223     {
3224       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
3225       temp = (memval >> nr_lhs_bits);
3226     }
3227   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
3228   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
3229
3230   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
3231            (long) ((unsigned64) memval >> 32), (long) memval,
3232            (long) ((unsigned64) temp >> 32), (long) temp,
3233            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
3234            (long) (rt >> 32), (long) rt); */
3235   return rt;
3236 }
3237
3238 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3239 {
3240   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3241   address_word reverseendian = (ReverseEndian ? -1 : 0);
3242   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3243   unsigned int byte;
3244   address_word paddr;
3245   int uncached;
3246   unsigned64 memval;
3247   address_word vaddr;
3248
3249   vaddr = loadstore_ea (SD_, base, offset);
3250   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
3251   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
3252   paddr = (paddr ^ (reverseendian & mask));
3253   if (BigEndianMem != 0)
3254     paddr = paddr & ~access;
3255   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3256   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
3257   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
3258   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
3259      (long) paddr, byte, (long) paddr, (long) memval); */
3260   {
3261     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
3262     rt &= ~screen;
3263     rt |= (memval >> (8 * byte)) & screen;
3264   }
3265   return rt;
3266 }
3267
3268
3269 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
3270 "lb r<RT>, <OFFSET>(r<BASE>)"
3271 *mipsI:
3272 *mipsII:
3273 *mipsIII:
3274 *mipsIV:
3275 *mipsV:
3276 *mips32:
3277 *mips32r2:
3278 *mips64:
3279 *mips64r2:
3280 *vr4100:
3281 *vr5000:
3282 *r3900:
3283 {
3284   do_lb (SD_,RT,OFFSET,BASE);
3285 }
3286
3287
3288 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
3289 "lbu r<RT>, <OFFSET>(r<BASE>)"
3290 *mipsI:
3291 *mipsII:
3292 *mipsIII:
3293 *mipsIV:
3294 *mipsV:
3295 *mips32:
3296 *mips32r2:
3297 *mips64:
3298 *mips64r2:
3299 *vr4100:
3300 *vr5000:
3301 *r3900:
3302 {
3303   do_lbu (SD_, RT,OFFSET,BASE);
3304 }
3305
3306
3307 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
3308 "ld r<RT>, <OFFSET>(r<BASE>)"
3309 *mipsIII:
3310 *mipsIV:
3311 *mipsV:
3312 *mips64:
3313 *mips64r2:
3314 *vr4100:
3315 *vr5000:
3316 {
3317   check_u64 (SD_, instruction_0);
3318   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3319 }
3320
3321
3322 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
3323 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3324 *mipsII:
3325 *mipsIII:
3326 *mipsIV:
3327 *mipsV:
3328 *mips32:
3329 *mips32r2:
3330 *mips64:
3331 *mips64r2:
3332 *vr4100:
3333 *vr5000:
3334 *r3900:
3335 {
3336   do_ldc (SD_, ZZ, RT, OFFSET, BASE);
3337 }
3338
3339
3340
3341
3342 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
3343 "ldl r<RT>, <OFFSET>(r<BASE>)"
3344 *mipsIII:
3345 *mipsIV:
3346 *mipsV:
3347 *mips64:
3348 *mips64r2:
3349 *vr4100:
3350 *vr5000:
3351 {
3352   check_u64 (SD_, instruction_0);
3353   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3354 }
3355
3356
3357 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
3358 "ldr r<RT>, <OFFSET>(r<BASE>)"
3359 *mipsIII:
3360 *mipsIV:
3361 *mipsV:
3362 *mips64:
3363 *mips64r2:
3364 *vr4100:
3365 *vr5000:
3366 {
3367   check_u64 (SD_, instruction_0);
3368   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3369 }
3370
3371
3372 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
3373 "lh r<RT>, <OFFSET>(r<BASE>)"
3374 *mipsI:
3375 *mipsII:
3376 *mipsIII:
3377 *mipsIV:
3378 *mipsV:
3379 *mips32:
3380 *mips32r2:
3381 *mips64:
3382 *mips64r2:
3383 *vr4100:
3384 *vr5000:
3385 *r3900:
3386 {
3387   do_lh (SD_,RT,OFFSET,BASE);
3388 }
3389
3390
3391 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
3392 "lhu r<RT>, <OFFSET>(r<BASE>)"
3393 *mipsI:
3394 *mipsII:
3395 *mipsIII:
3396 *mipsIV:
3397 *mipsV:
3398 *mips32:
3399 *mips32r2:
3400 *mips64:
3401 *mips64r2:
3402 *vr4100:
3403 *vr5000:
3404 *r3900:
3405 {
3406   do_lhu (SD_,RT,OFFSET,BASE);
3407 }
3408
3409
3410 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
3411 "ll r<RT>, <OFFSET>(r<BASE>)"
3412 *mipsII:
3413 *mipsIII:
3414 *mipsIV:
3415 *mipsV:
3416 *mips32:
3417 *mips32r2:
3418 *mips64:
3419 *mips64r2:
3420 *vr4100:
3421 *vr5000:
3422 {
3423   do_ll (SD_, RT, OFFSET, BASE);
3424 }
3425
3426
3427 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
3428 "lld r<RT>, <OFFSET>(r<BASE>)"
3429 *mipsIII:
3430 *mipsIV:
3431 *mipsV:
3432 *mips64:
3433 *mips64r2:
3434 *vr4100:
3435 *vr5000:
3436 {
3437   check_u64 (SD_, instruction_0);
3438   do_lld (SD_, RT, OFFSET, BASE);
3439 }
3440
3441
3442 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
3443 "lui r<RT>, %#lx<IMMEDIATE>"
3444 *mipsI:
3445 *mipsII:
3446 *mipsIII:
3447 *mipsIV:
3448 *mipsV:
3449 *mips32:
3450 *mips32r2:
3451 *mips64:
3452 *mips64r2:
3453 *vr4100:
3454 *vr5000:
3455 *r3900:
3456 {
3457   do_lui (SD_, RT, IMMEDIATE);
3458 }
3459
3460
3461 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
3462 "lw r<RT>, <OFFSET>(r<BASE>)"
3463 *mipsI:
3464 *mipsII:
3465 *mipsIII:
3466 *mipsIV:
3467 *mipsV:
3468 *mips32:
3469 *mips32r2:
3470 *mips64:
3471 *mips64r2:
3472 *vr4100:
3473 *vr5000:
3474 *r3900:
3475 {
3476   do_lw (SD_,RT,OFFSET,BASE);
3477 }
3478
3479
3480 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
3481 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3482 *mipsI:
3483 *mipsII:
3484 *mipsIII:
3485 *mipsIV:
3486 *mipsV:
3487 *mips32:
3488 *mips32r2:
3489 *mips64:
3490 *mips64r2:
3491 *vr4100:
3492 *vr5000:
3493 *r3900:
3494 {
3495   do_lwc (SD_, ZZ, RT, OFFSET, BASE);
3496 }
3497
3498
3499 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
3500 "lwl r<RT>, <OFFSET>(r<BASE>)"
3501 *mipsI:
3502 *mipsII:
3503 *mipsIII:
3504 *mipsIV:
3505 *mipsV:
3506 *mips32:
3507 *mips32r2:
3508 *mips64:
3509 *mips64r2:
3510 *vr4100:
3511 *vr5000:
3512 *r3900:
3513 {
3514   do_lwl (SD_, RT, OFFSET, BASE);
3515 }
3516
3517
3518 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
3519 "lwr r<RT>, <OFFSET>(r<BASE>)"
3520 *mipsI:
3521 *mipsII:
3522 *mipsIII:
3523 *mipsIV:
3524 *mipsV:
3525 *mips32:
3526 *mips32r2:
3527 *mips64:
3528 *mips64r2:
3529 *vr4100:
3530 *vr5000:
3531 *r3900:
3532 {
3533   do_lwr (SD_, RT, OFFSET, BASE);
3534 }
3535
3536
3537 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
3538 "lwu r<RT>, <OFFSET>(r<BASE>)"
3539 *mipsIII:
3540 *mipsIV:
3541 *mipsV:
3542 *mips64:
3543 *mips64r2:
3544 *vr4100:
3545 *vr5000:
3546 {
3547   do_lwu (SD_, RT, OFFSET, BASE, instruction_0);
3548 }
3549
3550
3551
3552 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
3553 "madd r<RS>, r<RT>"
3554 *mips32:
3555 *mips64:
3556 *vr5500:
3557 {
3558   do_madd (SD_, RS, RT);
3559 }
3560
3561
3562 011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
3563 "madd r<RS>, r<RT>":AC == 0
3564 "madd ac<AC>, r<RS>, r<RT>"
3565 *mips32r2:
3566 *mips64r2:
3567 *dsp2:
3568 {
3569   do_dsp_madd (SD_, AC, RS, RT);
3570 }
3571
3572
3573 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
3574 "maddu r<RS>, r<RT>"
3575 *mips32:
3576 *mips64:
3577 *vr5500:
3578 {
3579   do_maddu (SD_, RS, RT);
3580 }
3581
3582
3583 011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
3584 "maddu r<RS>, r<RT>":AC == 0
3585 "maddu ac<AC>, r<RS>, r<RT>"
3586 *mips32r2:
3587 *mips64r2:
3588 *dsp2:
3589 {
3590   do_dsp_maddu (SD_, AC, RS, RT);
3591 }
3592
3593
3594 :function:::void:do_mfhi:int rd
3595 {
3596   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
3597   TRACE_ALU_INPUT1 (HI);
3598   GPR[rd] = HI;
3599   TRACE_ALU_RESULT (GPR[rd]);
3600 }
3601
3602 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
3603 "mfhi r<RD>"
3604 *mipsI:
3605 *mipsII:
3606 *mipsIII:
3607 *mipsIV:
3608 *mipsV:
3609 *vr4100:
3610 *vr5000:
3611 *r3900:
3612 *mips32:
3613 *mips64:
3614 {
3615   do_mfhi (SD_, RD);
3616 }
3617
3618
3619 000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
3620 "mfhi r<RD>":AC == 0
3621 "mfhi r<RD>, ac<AC>"
3622 *mips32r2:
3623 *mips64r2:
3624 *dsp:
3625 {
3626   do_dsp_mfhi (SD_, AC, RD);
3627 }
3628
3629
3630 :function:::void:do_mflo:int rd
3631 {
3632   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
3633   TRACE_ALU_INPUT1 (LO);
3634   GPR[rd] = LO;
3635   TRACE_ALU_RESULT (GPR[rd]);
3636 }
3637
3638 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
3639 "mflo r<RD>"
3640 *mipsI:
3641 *mipsII:
3642 *mipsIII:
3643 *mipsIV:
3644 *mipsV:
3645 *vr4100:
3646 *vr5000:
3647 *r3900:
3648 *mips32:
3649 *mips64:
3650 {
3651   do_mflo (SD_, RD);
3652 }
3653
3654
3655 000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
3656 "mflo r<RD>":AC == 0
3657 "mflo r<RD>, ac<AC>"
3658 *mips32r2:
3659 *mips64r2:
3660 *dsp:
3661 {
3662   do_dsp_mflo (SD_, AC, RD);
3663 }
3664
3665
3666 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
3667 "movn r<RD>, r<RS>, r<RT>"
3668 *mipsIV:
3669 *mipsV:
3670 *mips32:
3671 *mips32r2:
3672 *mips64:
3673 *mips64r2:
3674 *vr5000:
3675 {
3676   do_movn (SD_, RD, RS, RT);
3677 }
3678
3679
3680
3681 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
3682 "movz r<RD>, r<RS>, r<RT>"
3683 *mipsIV:
3684 *mipsV:
3685 *mips32:
3686 *mips32r2:
3687 *mips64:
3688 *mips64r2:
3689 *vr5000:
3690 {
3691   do_movz (SD_, RD, RS, RT);
3692 }
3693
3694
3695
3696 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
3697 "msub r<RS>, r<RT>"
3698 *mips32:
3699 *mips64:
3700 *vr5500:
3701 {
3702   do_msub (SD_, RS, RT);
3703 }
3704
3705
3706 011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
3707 "msub r<RS>, r<RT>":AC == 0
3708 "msub ac<AC>, r<RS>, r<RT>"
3709 *mips32r2:
3710 *mips64r2:
3711 *dsp2:
3712 {
3713   do_dsp_msub (SD_, AC, RS, RT);
3714 }
3715
3716
3717 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
3718 "msubu r<RS>, r<RT>"
3719 *mips32:
3720 *mips64:
3721 *vr5500:
3722 {
3723   do_msubu (SD_, RS, RT);
3724 }
3725
3726
3727 011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
3728 "msubu r<RS>, r<RT>":AC == 0
3729 "msubu ac<AC>, r<RS>, r<RT>"
3730 *mips32r2:
3731 *mips64r2:
3732 *dsp2:
3733 {
3734   do_dsp_msubu (SD_, AC, RS, RT);
3735 }
3736
3737
3738 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
3739 "mthi r<RS>"
3740 *mipsI:
3741 *mipsII:
3742 *mipsIII:
3743 *mipsIV:
3744 *mipsV:
3745 *vr4100:
3746 *vr5000:
3747 *r3900:
3748 *mips32:
3749 *mips64:
3750 {
3751   do_mthi (SD_, RS);
3752 }
3753
3754
3755 000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
3756 "mthi r<RS>":AC == 0
3757 "mthi r<RS>, ac<AC>"
3758 *mips32r2:
3759 *mips64r2:
3760 *dsp:
3761 {
3762   do_dsp_mthi (SD_, AC, RS);
3763 }
3764
3765
3766 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
3767 "mtlo r<RS>"
3768 *mipsI:
3769 *mipsII:
3770 *mipsIII:
3771 *mipsIV:
3772 *mipsV:
3773 *vr4100:
3774 *vr5000:
3775 *r3900:
3776 *mips32:
3777 *mips64:
3778 {
3779   do_mtlo (SD_, RS);
3780 }
3781
3782
3783 000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
3784 "mtlo r<RS>":AC == 0
3785 "mtlo r<RS>, ac<AC>"
3786 *mips32r2:
3787 *mips64r2:
3788 *dsp:
3789 {
3790   do_dsp_mtlo (SD_, AC, RS);
3791 }
3792
3793
3794 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
3795 "mul r<RD>, r<RS>, r<RT>"
3796 *mips32:
3797 *mips32r2:
3798 *mips64:
3799 *mips64r2:
3800 *vr5500:
3801 {
3802   do_mul (SD_, RD, RS, RT);
3803 }
3804
3805
3806
3807 :function:::void:do_mult:int rs, int rt, int rd
3808 {
3809   signed64 prod;
3810   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
3811   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3812     Unpredictable ();
3813   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3814   prod = (((signed64)(signed32) GPR[rs])
3815           * ((signed64)(signed32) GPR[rt]));
3816   LO = EXTEND32 (VL4_8 (prod));
3817   HI = EXTEND32 (VH4_8 (prod));
3818   ACX = 0;  /* SmartMIPS */
3819   if (rd != 0)
3820     GPR[rd] = LO;
3821   TRACE_ALU_RESULT2 (HI, LO);
3822 }
3823
3824 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
3825 "mult r<RS>, r<RT>"
3826 *mipsI:
3827 *mipsII:
3828 *mipsIII:
3829 *mipsIV:
3830 *mipsV:
3831 *mips32:
3832 *mips64:
3833 *vr4100:
3834 {
3835   do_mult (SD_, RS, RT, 0);
3836 }
3837
3838
3839 000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
3840 "mult r<RS>, r<RT>":AC == 0
3841 "mult ac<AC>, r<RS>, r<RT>"
3842 *mips32r2:
3843 *mips64r2:
3844 *dsp2:
3845 {
3846   do_dsp_mult (SD_, AC, RS, RT);
3847 }
3848
3849
3850 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
3851 "mult r<RS>, r<RT>":RD == 0
3852 "mult r<RD>, r<RS>, r<RT>"
3853 *vr5000:
3854 *r3900:
3855 {
3856   do_mult (SD_, RS, RT, RD);
3857 }
3858
3859
3860 :function:::void:do_multu:int rs, int rt, int rd
3861 {
3862   unsigned64 prod;
3863   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
3864   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3865     Unpredictable ();
3866   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3867   prod = (((unsigned64)(unsigned32) GPR[rs])
3868           * ((unsigned64)(unsigned32) GPR[rt]));
3869   LO = EXTEND32 (VL4_8 (prod));
3870   HI = EXTEND32 (VH4_8 (prod));
3871   if (rd != 0)
3872     GPR[rd] = LO;
3873   TRACE_ALU_RESULT2 (HI, LO);
3874 }
3875
3876 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
3877 "multu r<RS>, r<RT>"
3878 *mipsI:
3879 *mipsII:
3880 *mipsIII:
3881 *mipsIV:
3882 *mipsV:
3883 *mips32:
3884 *mips64:
3885 *vr4100:
3886 {
3887   do_multu (SD_, RS, RT, 0);
3888 }
3889
3890
3891 000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
3892 "multu r<RS>, r<RT>":AC == 0
3893 "multu r<RS>, r<RT>"
3894 *mips32r2:
3895 *mips64r2:
3896 *dsp2:
3897 {
3898   do_dsp_multu (SD_, AC, RS, RT);
3899 }
3900
3901
3902 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
3903 "multu r<RS>, r<RT>":RD == 0
3904 "multu r<RD>, r<RS>, r<RT>"
3905 *vr5000:
3906 *r3900:
3907 {
3908   do_multu (SD_, RS, RT, RD);
3909 }
3910
3911
3912 :function:::void:do_nor:int rs, int rt, int rd
3913 {
3914   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3915   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
3916   TRACE_ALU_RESULT (GPR[rd]);
3917 }
3918
3919 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
3920 "nor r<RD>, r<RS>, r<RT>"
3921 *mipsI:
3922 *mipsII:
3923 *mipsIII:
3924 *mipsIV:
3925 *mipsV:
3926 *mips32:
3927 *mips32r2:
3928 *mips64:
3929 *mips64r2:
3930 *vr4100:
3931 *vr5000:
3932 *r3900:
3933 {
3934   do_nor (SD_, RS, RT, RD);
3935 }
3936
3937
3938 :function:::void:do_or:int rs, int rt, int rd
3939 {
3940   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3941   GPR[rd] = (GPR[rs] | GPR[rt]);
3942   TRACE_ALU_RESULT (GPR[rd]);
3943 }
3944
3945 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
3946 "or r<RD>, r<RS>, r<RT>"
3947 *mipsI:
3948 *mipsII:
3949 *mipsIII:
3950 *mipsIV:
3951 *mipsV:
3952 *mips32:
3953 *mips32r2:
3954 *mips64:
3955 *mips64r2:
3956 *vr4100:
3957 *vr5000:
3958 *r3900:
3959 {
3960   do_or (SD_, RS, RT, RD);
3961 }
3962
3963
3964
3965 :function:::void:do_ori:int rs, int rt, unsigned immediate
3966 {
3967   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3968   GPR[rt] = (GPR[rs] | immediate);
3969   TRACE_ALU_RESULT (GPR[rt]);
3970 }
3971
3972 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
3973 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3974 *mipsI:
3975 *mipsII:
3976 *mipsIII:
3977 *mipsIV:
3978 *mipsV:
3979 *mips32:
3980 *mips32r2:
3981 *mips64:
3982 *mips64r2:
3983 *vr4100:
3984 *vr5000:
3985 *r3900:
3986 {
3987   do_ori (SD_, RS, RT, IMMEDIATE);
3988 }
3989
3990
3991 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
3992 "pref <HINT>, <OFFSET>(r<BASE>)"
3993 *mipsIV:
3994 *mipsV:
3995 *mips32:
3996 *mips32r2:
3997 *mips64:
3998 *mips64r2:
3999 *vr5000:
4000 {
4001   do_pref (SD_, HINT, OFFSET, BASE);
4002 }
4003
4004
4005 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
4006 {
4007   unsigned64 result;
4008
4009   y &= 31;
4010   TRACE_ALU_INPUT2 (x, y);
4011   result = EXTEND32 (ROTR32 (x, y));
4012   TRACE_ALU_RESULT (result);
4013   return result;
4014 }
4015
4016 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
4017 "ror r<RD>, r<RT>, <SHIFT>"
4018 *mips32r2:
4019 *mips64r2:
4020 *smartmips:
4021 *vr5400:
4022 *vr5500:
4023 {
4024   GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
4025 }
4026
4027 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
4028 "rorv r<RD>, r<RT>, r<RS>"
4029 *mips32r2:
4030 *mips64r2:
4031 *smartmips:
4032 *vr5400:
4033 *vr5500:
4034 {
4035   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
4036 }
4037
4038
4039 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
4040 {
4041   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4042   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
4043   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
4044   unsigned int byte;
4045   address_word paddr;
4046   int uncached;
4047   unsigned64 memval;
4048   address_word vaddr;
4049
4050   vaddr = loadstore_ea (SD_, base, offset);
4051   if ((vaddr & access) != 0)
4052     {
4053       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
4054     }
4055   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
4056   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4057   byte = ((vaddr & mask) ^ bigendiancpu);
4058   memval = (word << (8 * byte));
4059   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
4060 }
4061
4062 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
4063 {
4064   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4065   address_word reverseendian = (ReverseEndian ? -1 : 0);
4066   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
4067   unsigned int byte;
4068   unsigned int word;
4069   address_word paddr;
4070   int uncached;
4071   unsigned64 memval;
4072   address_word vaddr;
4073   int nr_lhs_bits;
4074   int nr_rhs_bits;
4075
4076   vaddr = loadstore_ea (SD_, base, offset);
4077   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
4078   paddr = (paddr ^ (reverseendian & mask));
4079   if (BigEndianMem == 0)
4080     paddr = paddr & ~access;
4081
4082   /* compute where within the word/mem we are */
4083   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
4084   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
4085   nr_lhs_bits = 8 * byte + 8;
4086   nr_rhs_bits = 8 * access - 8 * byte;
4087   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
4088   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
4089            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
4090            (long) ((unsigned64) paddr >> 32), (long) paddr,
4091            word, byte, nr_lhs_bits, nr_rhs_bits); */
4092
4093   if (word == 0)
4094     {
4095       memval = (rt >> nr_rhs_bits);
4096     }
4097   else
4098     {
4099       memval = (rt << nr_lhs_bits);
4100     }
4101   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
4102            (long) ((unsigned64) rt >> 32), (long) rt,
4103            (long) ((unsigned64) memval >> 32), (long) memval); */
4104   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
4105 }
4106
4107 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
4108 {
4109   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4110   address_word reverseendian = (ReverseEndian ? -1 : 0);
4111   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
4112   unsigned int byte;
4113   address_word paddr;
4114   int uncached;
4115   unsigned64 memval;
4116   address_word vaddr;
4117
4118   vaddr = loadstore_ea (SD_, base, offset);
4119   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
4120   paddr = (paddr ^ (reverseendian & mask));
4121   if (BigEndianMem != 0)
4122     paddr &= ~access;
4123   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
4124   memval = (rt << (byte * 8));
4125   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
4126 }
4127
4128
4129 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
4130 "sb r<RT>, <OFFSET>(r<BASE>)"
4131 *mipsI:
4132 *mipsII:
4133 *mipsIII:
4134 *mipsIV:
4135 *mipsV:
4136 *mips32:
4137 *mips32r2:
4138 *mips64:
4139 *mips64r2:
4140 *vr4100:
4141 *vr5000:
4142 *r3900:
4143 {
4144   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4145 }
4146
4147
4148 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
4149 "sc r<RT>, <OFFSET>(r<BASE>)"
4150 *mipsII:
4151 *mipsIII:
4152 *mipsIV:
4153 *mipsV:
4154 *mips32:
4155 *mips32r2:
4156 *mips64:
4157 *mips64r2:
4158 *vr4100:
4159 *vr5000:
4160 {
4161   do_sc (SD_, RT, OFFSET, BASE, instruction_0);
4162 }
4163
4164
4165 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
4166 "scd r<RT>, <OFFSET>(r<BASE>)"
4167 *mipsIII:
4168 *mipsIV:
4169 *mipsV:
4170 *mips64:
4171 *mips64r2:
4172 *vr4100:
4173 *vr5000:
4174 {
4175   check_u64 (SD_, instruction_0);
4176   do_scd (SD_, RT, OFFSET, BASE);
4177 }
4178
4179
4180 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
4181 "sd r<RT>, <OFFSET>(r<BASE>)"
4182 *mipsIII:
4183 *mipsIV:
4184 *mipsV:
4185 *mips64:
4186 *mips64r2:
4187 *vr4100:
4188 *vr5000:
4189 {
4190   check_u64 (SD_, instruction_0);
4191   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4192 }
4193
4194
4195 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
4196 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
4197 *mipsII:
4198 *mipsIII:
4199 *mipsIV:
4200 *mipsV:
4201 *mips32:
4202 *mips32r2:
4203 *mips64:
4204 *mips64r2:
4205 *vr4100:
4206 *vr5000:
4207 {
4208   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
4209 }
4210
4211
4212 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
4213 "sdl r<RT>, <OFFSET>(r<BASE>)"
4214 *mipsIII:
4215 *mipsIV:
4216 *mipsV:
4217 *mips64:
4218 *mips64r2:
4219 *vr4100:
4220 *vr5000:
4221 {
4222   check_u64 (SD_, instruction_0);
4223   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4224 }
4225
4226
4227 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
4228 "sdr r<RT>, <OFFSET>(r<BASE>)"
4229 *mipsIII:
4230 *mipsIV:
4231 *mipsV:
4232 *mips64:
4233 *mips64r2:
4234 *vr4100:
4235 *vr5000:
4236 {
4237   check_u64 (SD_, instruction_0);
4238   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4239 }
4240
4241
4242
4243 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
4244 "sh r<RT>, <OFFSET>(r<BASE>)"
4245 *mipsI:
4246 *mipsII:
4247 *mipsIII:
4248 *mipsIV:
4249 *mipsV:
4250 *mips32:
4251 *mips32r2:
4252 *mips64:
4253 *mips64r2:
4254 *vr4100:
4255 *vr5000:
4256 *r3900:
4257 {
4258   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4259 }
4260
4261
4262 :function:::void:do_sll:int rt, int rd, int shift
4263 {
4264   unsigned32 temp = (GPR[rt] << shift);
4265   TRACE_ALU_INPUT2 (GPR[rt], shift);
4266   GPR[rd] = EXTEND32 (temp);
4267   TRACE_ALU_RESULT (GPR[rd]);
4268 }
4269
4270 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
4271 "nop":RD == 0 && RT == 0 && SHIFT == 0
4272 "sll r<RD>, r<RT>, <SHIFT>"
4273 *mipsI:
4274 *mipsII:
4275 *mipsIII:
4276 *mipsIV:
4277 *mipsV:
4278 *vr4100:
4279 *vr5000:
4280 *r3900:
4281 {
4282   /* Skip shift for NOP, so that there won't be lots of extraneous
4283      trace output.  */
4284   if (RD != 0 || RT != 0 || SHIFT != 0)
4285     do_sll (SD_, RT, RD, SHIFT);
4286 }
4287
4288 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
4289 "nop":RD == 0 && RT == 0 && SHIFT == 0
4290 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
4291 "sll r<RD>, r<RT>, <SHIFT>"
4292 *mips32:
4293 *mips32r2:
4294 *mips64:
4295 *mips64r2:
4296 {
4297   /* Skip shift for NOP and SSNOP, so that there won't be lots of
4298      extraneous trace output.  */
4299   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
4300     do_sll (SD_, RT, RD, SHIFT);
4301 }
4302
4303
4304 :function:::void:do_sllv:int rs, int rt, int rd
4305 {
4306   int s = MASKED (GPR[rs], 4, 0);
4307   unsigned32 temp = (GPR[rt] << s);
4308   TRACE_ALU_INPUT2 (GPR[rt], s);
4309   GPR[rd] = EXTEND32 (temp);
4310   TRACE_ALU_RESULT (GPR[rd]);
4311 }
4312
4313 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
4314 "sllv r<RD>, r<RT>, r<RS>"
4315 *mipsI:
4316 *mipsII:
4317 *mipsIII:
4318 *mipsIV:
4319 *mipsV:
4320 *mips32:
4321 *mips32r2:
4322 *mips64:
4323 *mips64r2:
4324 *vr4100:
4325 *vr5000:
4326 *r3900:
4327 {
4328   do_sllv (SD_, RS, RT, RD);
4329 }
4330
4331
4332 :function:::void:do_slt:int rs, int rt, int rd
4333 {
4334   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4335   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
4336   TRACE_ALU_RESULT (GPR[rd]);
4337 }
4338
4339 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
4340 "slt r<RD>, r<RS>, r<RT>"
4341 *mipsI:
4342 *mipsII:
4343 *mipsIII:
4344 *mipsIV:
4345 *mipsV:
4346 *mips32:
4347 *mips32r2:
4348 *mips64:
4349 *mips64r2:
4350 *vr4100:
4351 *vr5000:
4352 *r3900:
4353 {
4354   do_slt (SD_, RS, RT, RD);
4355 }
4356
4357
4358 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
4359 {
4360   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
4361   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
4362   TRACE_ALU_RESULT (GPR[rt]);
4363 }
4364
4365 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
4366 "slti r<RT>, r<RS>, <IMMEDIATE>"
4367 *mipsI:
4368 *mipsII:
4369 *mipsIII:
4370 *mipsIV:
4371 *mipsV:
4372 *mips32:
4373 *mips32r2:
4374 *mips64:
4375 *mips64r2:
4376 *vr4100:
4377 *vr5000:
4378 *r3900:
4379 {
4380   do_slti (SD_, RS, RT, IMMEDIATE);
4381 }
4382
4383
4384 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
4385 {
4386   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
4387   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
4388   TRACE_ALU_RESULT (GPR[rt]);
4389 }
4390
4391 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
4392 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
4393 *mipsI:
4394 *mipsII:
4395 *mipsIII:
4396 *mipsIV:
4397 *mipsV:
4398 *mips32:
4399 *mips32r2:
4400 *mips64:
4401 *mips64r2:
4402 *vr4100:
4403 *vr5000:
4404 *r3900:
4405 {
4406   do_sltiu (SD_, RS, RT, IMMEDIATE);
4407 }
4408
4409
4410
4411 :function:::void:do_sltu:int rs, int rt, int rd
4412 {
4413   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4414   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
4415   TRACE_ALU_RESULT (GPR[rd]);
4416 }
4417
4418 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
4419 "sltu r<RD>, r<RS>, r<RT>"
4420 *mipsI:
4421 *mipsII:
4422 *mipsIII:
4423 *mipsIV:
4424 *mipsV:
4425 *mips32:
4426 *mips32r2:
4427 *mips64:
4428 *mips64r2:
4429 *vr4100:
4430 *vr5000:
4431 *r3900:
4432 {
4433   do_sltu (SD_, RS, RT, RD);
4434 }
4435
4436
4437 :function:::void:do_sra:int rt, int rd, int shift
4438 {
4439   signed32 temp = (signed32) GPR[rt] >> shift;
4440   if (NotWordValue (GPR[rt]))
4441     Unpredictable ();
4442   TRACE_ALU_INPUT2 (GPR[rt], shift);
4443   GPR[rd] = EXTEND32 (temp);
4444   TRACE_ALU_RESULT (GPR[rd]);
4445 }
4446
4447 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
4448 "sra r<RD>, r<RT>, <SHIFT>"
4449 *mipsI:
4450 *mipsII:
4451 *mipsIII:
4452 *mipsIV:
4453 *mipsV:
4454 *mips32:
4455 *mips32r2:
4456 *mips64:
4457 *mips64r2:
4458 *vr4100:
4459 *vr5000:
4460 *r3900:
4461 {
4462   do_sra (SD_, RT, RD, SHIFT);
4463 }
4464
4465
4466
4467 :function:::void:do_srav:int rs, int rt, int rd
4468 {
4469   int s = MASKED (GPR[rs], 4, 0);
4470   signed32 temp = (signed32) GPR[rt] >> s;
4471   if (NotWordValue (GPR[rt]))
4472     Unpredictable ();
4473   TRACE_ALU_INPUT2 (GPR[rt], s);
4474   GPR[rd] = EXTEND32 (temp);
4475   TRACE_ALU_RESULT (GPR[rd]);
4476 }
4477
4478 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
4479 "srav r<RD>, r<RT>, r<RS>"
4480 *mipsI:
4481 *mipsII:
4482 *mipsIII:
4483 *mipsIV:
4484 *mipsV:
4485 *mips32:
4486 *mips32r2:
4487 *mips64:
4488 *mips64r2:
4489 *vr4100:
4490 *vr5000:
4491 *r3900:
4492 {
4493   do_srav (SD_, RS, RT, RD);
4494 }
4495
4496
4497
4498 :function:::void:do_srl:int rt, int rd, int shift
4499 {
4500   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
4501   if (NotWordValue (GPR[rt]))
4502     Unpredictable ();
4503   TRACE_ALU_INPUT2 (GPR[rt], shift);
4504   GPR[rd] = EXTEND32 (temp);
4505   TRACE_ALU_RESULT (GPR[rd]);
4506 }
4507
4508 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
4509 "srl r<RD>, r<RT>, <SHIFT>"
4510 *mipsI:
4511 *mipsII:
4512 *mipsIII:
4513 *mipsIV:
4514 *mipsV:
4515 *mips32:
4516 *mips32r2:
4517 *mips64:
4518 *mips64r2:
4519 *vr4100:
4520 *vr5000:
4521 *r3900:
4522 {
4523   do_srl (SD_, RT, RD, SHIFT);
4524 }
4525
4526
4527 :function:::void:do_srlv:int rs, int rt, int rd
4528 {
4529   int s = MASKED (GPR[rs], 4, 0);
4530   unsigned32 temp = (unsigned32) GPR[rt] >> s;
4531   if (NotWordValue (GPR[rt]))
4532     Unpredictable ();
4533   TRACE_ALU_INPUT2 (GPR[rt], s);
4534   GPR[rd] = EXTEND32 (temp);
4535   TRACE_ALU_RESULT (GPR[rd]);
4536 }
4537
4538 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
4539 "srlv r<RD>, r<RT>, r<RS>"
4540 *mipsI:
4541 *mipsII:
4542 *mipsIII:
4543 *mipsIV:
4544 *mipsV:
4545 *mips32:
4546 *mips32r2:
4547 *mips64:
4548 *mips64r2:
4549 *vr4100:
4550 *vr5000:
4551 *r3900:
4552 {
4553   do_srlv (SD_, RS, RT, RD);
4554 }
4555
4556
4557 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
4558 "sub r<RD>, r<RS>, r<RT>"
4559 *mipsI:
4560 *mipsII:
4561 *mipsIII:
4562 *mipsIV:
4563 *mipsV:
4564 *mips32:
4565 *mips32r2:
4566 *mips64:
4567 *mips64r2:
4568 *vr4100:
4569 *vr5000:
4570 *r3900:
4571 {
4572   do_sub (SD_, RD, RS, RT);
4573 }
4574
4575
4576 :function:::void:do_subu:int rs, int rt, int rd
4577 {
4578   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
4579     Unpredictable ();
4580   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4581   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
4582   TRACE_ALU_RESULT (GPR[rd]);
4583 }
4584
4585 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
4586 "subu r<RD>, r<RS>, r<RT>"
4587 *mipsI:
4588 *mipsII:
4589 *mipsIII:
4590 *mipsIV:
4591 *mipsV:
4592 *mips32:
4593 *mips32r2:
4594 *mips64:
4595 *mips64r2:
4596 *vr4100:
4597 *vr5000:
4598 *r3900:
4599 {
4600   do_subu (SD_, RS, RT, RD);
4601 }
4602
4603
4604 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
4605 "sw r<RT>, <OFFSET>(r<BASE>)"
4606 *mipsI:
4607 *mipsII:
4608 *mipsIII:
4609 *mipsIV:
4610 *mipsV:
4611 *mips32:
4612 *mips32r2:
4613 *mips64:
4614 *mips64r2:
4615 *vr4100:
4616 *r3900:
4617 *vr5000:
4618 {
4619   do_sw (SD_, RT, OFFSET, BASE);
4620 }
4621
4622
4623 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
4624 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
4625 *mipsI:
4626 *mipsII:
4627 *mipsIII:
4628 *mipsIV:
4629 *mipsV:
4630 *mips32:
4631 *mips32r2:
4632 *mips64:
4633 *mips64r2:
4634 *vr4100:
4635 *vr5000:
4636 *r3900:
4637 {
4638   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
4639 }
4640
4641
4642 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
4643 "swl r<RT>, <OFFSET>(r<BASE>)"
4644 *mipsI:
4645 *mipsII:
4646 *mipsIII:
4647 *mipsIV:
4648 *mipsV:
4649 *mips32:
4650 *mips32r2:
4651 *mips64:
4652 *mips64r2:
4653 *vr4100:
4654 *vr5000:
4655 *r3900:
4656 {
4657   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4658 }
4659
4660
4661 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
4662 "swr r<RT>, <OFFSET>(r<BASE>)"
4663 *mipsI:
4664 *mipsII:
4665 *mipsIII:
4666 *mipsIV:
4667 *mipsV:
4668 *mips32:
4669 *mips32r2:
4670 *mips64:
4671 *mips64r2:
4672 *vr4100:
4673 *vr5000:
4674 *r3900:
4675 {
4676   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4677 }
4678
4679
4680 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
4681 "sync":STYPE == 0
4682 "sync <STYPE>"
4683 *mipsII:
4684 *mipsIII:
4685 *mipsIV:
4686 *mipsV:
4687 *mips32:
4688 *mips32r2:
4689 *mips64:
4690 *mips64r2:
4691 *vr4100:
4692 *vr5000:
4693 *r3900:
4694 {
4695   SyncOperation (STYPE);
4696 }
4697
4698
4699 000000,20.CODE,001100:SPECIAL:32::SYSCALL
4700 "syscall %#lx<CODE>"
4701 *mipsI:
4702 *mipsII:
4703 *mipsIII:
4704 *mipsIV:
4705 *mipsV:
4706 *mips32:
4707 *mips32r2:
4708 *mips64:
4709 *mips64r2:
4710 *vr4100:
4711 *vr5000:
4712 *r3900:
4713 {
4714   SignalException (SystemCall, instruction_0);
4715 }
4716
4717
4718 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
4719 "teq r<RS>, r<RT>"
4720 *mipsII:
4721 *mipsIII:
4722 *mipsIV:
4723 *mipsV:
4724 *mips32:
4725 *mips32r2:
4726 *mips64:
4727 *mips64r2:
4728 *vr4100:
4729 *vr5000:
4730 {
4731   do_teq (SD_, RS, RT, instruction_0);
4732 }
4733
4734
4735 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
4736 "teqi r<RS>, <IMMEDIATE>"
4737 *mipsII:
4738 *mipsIII:
4739 *mipsIV:
4740 *mipsV:
4741 *mips32:
4742 *mips32r2:
4743 *mips64:
4744 *mips64r2:
4745 *vr4100:
4746 *vr5000:
4747 {
4748   do_teqi (SD_, RS, IMMEDIATE, instruction_0);
4749 }
4750
4751
4752 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
4753 "tge r<RS>, r<RT>"
4754 *mipsII:
4755 *mipsIII:
4756 *mipsIV:
4757 *mipsV:
4758 *mips32:
4759 *mips32r2:
4760 *mips64:
4761 *mips64r2:
4762 *vr4100:
4763 *vr5000:
4764 {
4765   do_tge (SD_, RS, RT, instruction_0);
4766 }
4767
4768
4769 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
4770 "tgei r<RS>, <IMMEDIATE>"
4771 *mipsII:
4772 *mipsIII:
4773 *mipsIV:
4774 *mipsV:
4775 *mips32:
4776 *mips32r2:
4777 *mips64:
4778 *mips64r2:
4779 *vr4100:
4780 *vr5000:
4781 {
4782   do_tgei (SD_, RS, IMMEDIATE, instruction_0);
4783 }
4784
4785
4786 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
4787 "tgeiu r<RS>, <IMMEDIATE>"
4788 *mipsII:
4789 *mipsIII:
4790 *mipsIV:
4791 *mipsV:
4792 *mips32:
4793 *mips32r2:
4794 *mips64:
4795 *mips64r2:
4796 *vr4100:
4797 *vr5000:
4798 {
4799   do_tgeiu (SD_, RS, IMMEDIATE, instruction_0);
4800 }
4801
4802
4803 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
4804 "tgeu r<RS>, r<RT>"
4805 *mipsII:
4806 *mipsIII:
4807 *mipsIV:
4808 *mipsV:
4809 *mips32:
4810 *mips32r2:
4811 *mips64:
4812 *mips64r2:
4813 *vr4100:
4814 *vr5000:
4815 {
4816   do_tgeu (SD_, RS, RT, instruction_0);
4817 }
4818
4819
4820 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
4821 "tlt r<RS>, r<RT>"
4822 *mipsII:
4823 *mipsIII:
4824 *mipsIV:
4825 *mipsV:
4826 *mips32:
4827 *mips32r2:
4828 *mips64:
4829 *mips64r2:
4830 *vr4100:
4831 *vr5000:
4832 {
4833   do_tlt (SD_, RS, RT, instruction_0);
4834 }
4835
4836
4837 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
4838 "tlti r<RS>, <IMMEDIATE>"
4839 *mipsII:
4840 *mipsIII:
4841 *mipsIV:
4842 *mipsV:
4843 *mips32:
4844 *mips32r2:
4845 *mips64:
4846 *mips64r2:
4847 *vr4100:
4848 *vr5000:
4849 {
4850   do_tlti (SD_, RS, IMMEDIATE, instruction_0);
4851 }
4852
4853
4854 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
4855 "tltiu r<RS>, <IMMEDIATE>"
4856 *mipsII:
4857 *mipsIII:
4858 *mipsIV:
4859 *mipsV:
4860 *mips32:
4861 *mips32r2:
4862 *mips64:
4863 *mips64r2:
4864 *vr4100:
4865 *vr5000:
4866 {
4867   do_tltiu (SD_, RS, IMMEDIATE, instruction_0);
4868 }
4869
4870
4871 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
4872 "tltu r<RS>, r<RT>"
4873 *mipsII:
4874 *mipsIII:
4875 *mipsIV:
4876 *mipsV:
4877 *mips32:
4878 *mips32r2:
4879 *mips64:
4880 *mips64r2:
4881 *vr4100:
4882 *vr5000:
4883 {
4884   do_tltu (SD_, RS, RT, instruction_0);
4885 }
4886
4887
4888 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
4889 "tne r<RS>, r<RT>"
4890 *mipsII:
4891 *mipsIII:
4892 *mipsIV:
4893 *mipsV:
4894 *mips32:
4895 *mips32r2:
4896 *mips64:
4897 *mips64r2:
4898 *vr4100:
4899 *vr5000:
4900 {
4901   do_tne (SD_, RS, RT, instruction_0);
4902 }
4903
4904
4905 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
4906 "tnei r<RS>, <IMMEDIATE>"
4907 *mipsII:
4908 *mipsIII:
4909 *mipsIV:
4910 *mipsV:
4911 *mips32:
4912 *mips32r2:
4913 *mips64:
4914 *mips64r2:
4915 *vr4100:
4916 *vr5000:
4917 {
4918   do_tnei (SD_, RS, IMMEDIATE, instruction_0);
4919 }
4920
4921
4922 :function:::void:do_xor:int rs, int rt, int rd
4923 {
4924   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4925   GPR[rd] = GPR[rs] ^ GPR[rt];
4926   TRACE_ALU_RESULT (GPR[rd]);
4927 }
4928
4929 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
4930 "xor r<RD>, r<RS>, r<RT>"
4931 *mipsI:
4932 *mipsII:
4933 *mipsIII:
4934 *mipsIV:
4935 *mipsV:
4936 *mips32:
4937 *mips32r2:
4938 *mips64:
4939 *mips64r2:
4940 *vr4100:
4941 *vr5000:
4942 *r3900:
4943 {
4944   do_xor (SD_, RS, RT, RD);
4945 }
4946
4947
4948 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
4949 {
4950   TRACE_ALU_INPUT2 (GPR[rs], immediate);
4951   GPR[rt] = GPR[rs] ^ immediate;
4952   TRACE_ALU_RESULT (GPR[rt]);
4953 }
4954
4955 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
4956 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
4957 *mipsI:
4958 *mipsII:
4959 *mipsIII:
4960 *mipsIV:
4961 *mipsV:
4962 *mips32:
4963 *mips32r2:
4964 *mips64:
4965 *mips64r2:
4966 *vr4100:
4967 *vr5000:
4968 *r3900:
4969 {
4970   do_xori (SD_, RS, RT, IMMEDIATE);
4971 }
4972
4973 \f
4974 //
4975 // MIPS Architecture:
4976 //
4977 //        FPU Instruction Set (COP1 & COP1X)
4978 //
4979
4980
4981 :%s::::FMT:int fmt
4982 {
4983   switch (fmt)
4984     {
4985     case fmt_single: return "s";
4986     case fmt_double: return "d";
4987     case fmt_word: return "w";
4988     case fmt_long: return "l";
4989     case fmt_ps: return "ps";
4990     default: return "?";
4991     }
4992 }
4993
4994 :%s::::TF:int tf
4995 {
4996   if (tf)
4997     return "t";
4998   else
4999     return "f";
5000 }
5001
5002 :%s::::ND:int nd
5003 {
5004   if (nd)
5005     return "l";
5006   else
5007     return "";
5008 }
5009
5010 :%s::::COND:int cond
5011 {
5012   switch (cond)
5013     {
5014     case 00: return "f";
5015     case 01: return "un";
5016     case 02: return "eq";
5017     case 03: return "ueq";
5018     case 04: return "olt";
5019     case 05: return "ult";
5020     case 06: return "ole";
5021     case 07: return "ule";
5022     case 010: return "sf";
5023     case 011: return "ngle";
5024     case 012: return "seq";
5025     case 013: return "ngl";
5026     case 014: return "lt";
5027     case 015: return "nge";
5028     case 016: return "le";
5029     case 017: return "ngt";
5030     default: return "?";
5031     }
5032 }
5033
5034
5035 // Helpers:
5036 //
5037 // Check that the given FPU format is usable, and signal a
5038 // ReservedInstruction exception if not.
5039 //
5040
5041 // check_fmt_p checks that the format is single, double, or paired single.
5042 :function:::void:check_fmt_p:int fmt, instruction_word insn
5043 *mipsI:
5044 *mipsII:
5045 *mipsIII:
5046 *mipsIV:
5047 *mips32:
5048 *vr4100:
5049 *vr5000:
5050 *r3900:
5051 {
5052   /* None of these ISAs support Paired Single, so just fall back to
5053      the single/double check.  */
5054   if ((fmt != fmt_single) && (fmt != fmt_double))
5055     SignalException (ReservedInstruction, insn);
5056 }
5057
5058 :function:::void:check_fmt_p:int fmt, instruction_word insn
5059 *mips32r2:
5060 *micromips32:
5061 {
5062   if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
5063     SignalException (ReservedInstruction, insn);
5064 }
5065
5066 :function:::void:check_fmt_p:int fmt, instruction_word insn
5067 *mipsV:
5068 *mips64:
5069 *mips64r2:
5070 *micromips64:
5071 {
5072   if ((fmt != fmt_single) && (fmt != fmt_double)
5073       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
5074     SignalException (ReservedInstruction, insn);
5075 }
5076
5077
5078 // Helper:
5079 //
5080 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
5081 // exception if not.
5082 //
5083
5084 :function:::void:check_fpu:
5085 *mipsI:
5086 *mipsII:
5087 *mipsIII:
5088 *mipsIV:
5089 *mipsV:
5090 *mips32:
5091 *mips32r2:
5092 *mips64:
5093 *mips64r2:
5094 *vr4100:
5095 *vr5000:
5096 *r3900:
5097 *micromips32:
5098 *micromips64:
5099 {
5100   if (! COP_Usable (1))
5101     SignalExceptionCoProcessorUnusable (1);
5102 }
5103
5104
5105 // Helper:
5106 //
5107 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
5108 // or MIPS32.  do_load cannot be used instead because it returns an
5109 // unsigned_word, which is limited to the size of the machine's registers.
5110 //
5111
5112 :function:::unsigned64:do_load_double:address_word base, address_word offset
5113 *mipsII:
5114 *mips32:
5115 *mips32r2:
5116 *micromips32:
5117 {
5118   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
5119   address_word vaddr;
5120   address_word paddr;
5121   int uncached;
5122   unsigned64 memval;
5123   unsigned64 v;
5124
5125   vaddr = loadstore_ea (SD_, base, offset);
5126   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
5127     {
5128       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
5129                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
5130                        sim_core_unaligned_signal);
5131     }
5132   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
5133                       isREAL);
5134   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
5135               isDATA, isREAL);
5136   v = (unsigned64)memval;
5137   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
5138               isDATA, isREAL);
5139   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
5140 }
5141
5142
5143 // Helper:
5144 //
5145 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
5146 // or MIPS32.  do_load cannot be used instead because it returns an
5147 // unsigned_word, which is limited to the size of the machine's registers.
5148 //
5149
5150 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
5151 *mipsII:
5152 *mips32:
5153 *mips32r2:
5154 *micromips32:
5155 {
5156   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
5157   address_word vaddr;
5158   address_word paddr;
5159   int uncached;
5160   unsigned64 memval;
5161
5162   vaddr = loadstore_ea (SD_, base, offset);
5163   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
5164     {
5165       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
5166                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
5167                        sim_core_unaligned_signal);
5168     }
5169   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
5170                       isREAL);
5171   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
5172   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
5173                isREAL);
5174   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
5175   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
5176                isREAL);
5177 }
5178
5179
5180 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
5181 "abs.%s<FMT> f<FD>, f<FS>"
5182 *mipsI:
5183 *mipsII:
5184 *mipsIII:
5185 *mipsIV:
5186 *mipsV:
5187 *mips32:
5188 *mips32r2:
5189 *mips64:
5190 *mips64r2:
5191 *vr4100:
5192 *vr5000:
5193 *r3900:
5194 {
5195   do_abs_fmt (SD_, FMT, FD, FS, instruction_0);
5196 }
5197
5198
5199
5200 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
5201 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
5202 *mipsI:
5203 *mipsII:
5204 *mipsIII:
5205 *mipsIV:
5206 *mipsV:
5207 *mips32:
5208 *mips32r2:
5209 *mips64:
5210 *mips64r2:
5211 *vr4100:
5212 *vr5000:
5213 *r3900:
5214 {
5215   do_add_fmt (SD_, FMT, FD, FS, FT, instruction_0);
5216 }
5217
5218
5219 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
5220 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
5221 *mipsV:
5222 *mips32r2:
5223 *mips64:
5224 *mips64r2:
5225 {
5226   do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0);
5227 }
5228
5229
5230 // BC1F
5231 // BC1FL
5232 // BC1T
5233 // BC1TL
5234
5235 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
5236 "bc1%s<TF>%s<ND> <OFFSET>"
5237 *mipsI:
5238 *mipsII:
5239 *mipsIII:
5240 {
5241   check_fpu (SD_);
5242   TRACE_BRANCH_INPUT (PREVCOC1());
5243   if (PREVCOC1() == TF)
5244     {
5245       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
5246       TRACE_BRANCH_RESULT (dest);
5247       DELAY_SLOT (dest);
5248     }
5249   else if (ND)
5250     {
5251       TRACE_BRANCH_RESULT (0);
5252       NULLIFY_NEXT_INSTRUCTION ();
5253     }
5254   else
5255     {
5256       TRACE_BRANCH_RESULT (NIA);
5257     }
5258 }
5259
5260 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
5261 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
5262 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
5263 *mipsIV:
5264 *mipsV:
5265 *mips32:
5266 *mips32r2:
5267 *mips64:
5268 *mips64r2:
5269 #*vr4100:
5270 *vr5000:
5271 *r3900:
5272 {
5273   check_fpu (SD_);
5274   if (GETFCC(CC) == TF)
5275     {
5276       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
5277       DELAY_SLOT (dest);
5278     }
5279   else if (ND)
5280     {
5281       NULLIFY_NEXT_INSTRUCTION ();
5282     }
5283 }
5284
5285
5286 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
5287 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
5288 *mipsI:
5289 *mipsII:
5290 *mipsIII:
5291 {
5292   int fmt = FMT;
5293   check_fpu (SD_);
5294   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
5295   TRACE_ALU_RESULT (ValueFCR (31));
5296 }
5297
5298 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
5299 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
5300 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
5301 *mipsIV:
5302 *mipsV:
5303 *mips32:
5304 *mips32r2:
5305 *mips64:
5306 *mips64r2:
5307 *vr4100:
5308 *vr5000:
5309 *r3900:
5310 {
5311   do_c_cond_fmt (SD_, COND, FMT, CC, FS, FT, instruction_0);
5312 }
5313
5314
5315 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
5316 "ceil.l.%s<FMT> f<FD>, f<FS>"
5317 *mipsIII:
5318 *mipsIV:
5319 *mipsV:
5320 *mips32r2:
5321 *mips64:
5322 *mips64r2:
5323 *vr4100:
5324 *vr5000:
5325 *r3900:
5326 {
5327   do_ceil_fmt (SD_, fmt_long, FMT, FD, FS, instruction_0);
5328 }
5329
5330
5331 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
5332 "ceil.w.%s<FMT> f<FD>, f<FS>"
5333 *mipsII:
5334 *mipsIII:
5335 *mipsIV:
5336 *mipsV:
5337 *mips32:
5338 *mips32r2:
5339 *mips64:
5340 *mips64r2:
5341 *vr4100:
5342 *vr5000:
5343 *r3900:
5344 {
5345   do_ceil_fmt (SD_, fmt_word, FMT, FD, FS, instruction_0);
5346 }
5347
5348
5349 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
5350 "cfc1 r<RT>, f<FS>"
5351 *mipsI:
5352 *mipsII:
5353 *mipsIII:
5354 {
5355   check_fpu (SD_);
5356   if (FS == 0)
5357     PENDING_FILL (RT, EXTEND32 (FCR0));
5358   else if (FS == 31)
5359     PENDING_FILL (RT, EXTEND32 (FCR31));
5360   /* else NOP */
5361 }
5362
5363 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
5364 "cfc1 r<RT>, f<FS>"
5365 *mipsIV:
5366 *vr4100:
5367 *vr5000:
5368 *r3900:
5369 {
5370   check_fpu (SD_);
5371   if (FS == 0 || FS == 31)
5372     {
5373       unsigned_word  fcr = ValueFCR (FS);
5374       TRACE_ALU_INPUT1 (fcr);
5375       GPR[RT] = fcr;
5376     }
5377   /* else NOP */
5378   TRACE_ALU_RESULT (GPR[RT]);
5379 }
5380
5381 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
5382 "cfc1 r<RT>, f<FS>"
5383 *mipsV:
5384 *mips32:
5385 *mips32r2:
5386 *mips64:
5387 *mips64r2:
5388 {
5389   do_cfc1 (SD_, RT, FS);
5390 }
5391
5392 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
5393 "ctc1 r<RT>, f<FS>"
5394 *mipsI:
5395 *mipsII:
5396 *mipsIII:
5397 {
5398   check_fpu (SD_);
5399   if (FS == 31)
5400     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
5401   /* else NOP */
5402 }
5403
5404 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
5405 "ctc1 r<RT>, f<FS>"
5406 *mipsIV:
5407 *vr4100:
5408 *vr5000:
5409 *r3900:
5410 {
5411   check_fpu (SD_);
5412   TRACE_ALU_INPUT1 (GPR[RT]);
5413   if (FS == 31)
5414     StoreFCR (FS, GPR[RT]);
5415   /* else NOP */
5416 }
5417
5418 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
5419 "ctc1 r<RT>, f<FS>"
5420 *mipsV:
5421 *mips32:
5422 *mips32r2:
5423 *mips64:
5424 *mips64r2:
5425 {
5426   do_ctc1 (SD_, RT, FS);
5427 }
5428
5429
5430 //
5431 // FIXME: Does not correctly differentiate between mips*
5432 //
5433 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
5434 "cvt.d.%s<FMT> f<FD>, f<FS>"
5435 *mipsI:
5436 *mipsII:
5437 *mipsIII:
5438 *mipsIV:
5439 *mipsV:
5440 *mips32:
5441 *mips32r2:
5442 *mips64:
5443 *mips64r2:
5444 *vr4100:
5445 *vr5000:
5446 *r3900:
5447 {
5448   do_cvt_d_fmt (SD_, FMT, FD, FS, instruction_0);
5449 }
5450
5451
5452 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
5453 "cvt.l.%s<FMT> f<FD>, f<FS>"
5454 *mipsIII:
5455 *mipsIV:
5456 *mipsV:
5457 *mips32r2:
5458 *mips64:
5459 *mips64r2:
5460 *vr4100:
5461 *vr5000:
5462 *r3900:
5463 {
5464   do_cvt_l_fmt (SD_, FMT, FD, FS, instruction_0);
5465 }
5466
5467
5468 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
5469 "cvt.ps.s f<FD>, f<FS>, f<FT>"
5470 *mipsV:
5471 *mips32r2:
5472 *mips64:
5473 *mips64r2:
5474 {
5475   do_cvt_ps_s (SD_, FD, FS, FT, instruction_0);
5476 }
5477
5478
5479 //
5480 // FIXME: Does not correctly differentiate between mips*
5481 //
5482 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
5483 "cvt.s.%s<FMT> f<FD>, f<FS>"
5484 *mipsI:
5485 *mipsII:
5486 *mipsIII:
5487 *mipsIV:
5488 *mipsV:
5489 *mips32:
5490 *mips32r2:
5491 *mips64:
5492 *mips64r2:
5493 *vr4100:
5494 *vr5000:
5495 *r3900:
5496 {
5497   do_cvt_s_fmt (SD_, FMT, FD, FS, instruction_0);
5498 }
5499
5500
5501 010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
5502 "cvt.s.pl f<FD>, f<FS>"
5503 *mipsV:
5504 *mips32r2:
5505 *mips64:
5506 *mips64r2:
5507 {
5508   do_cvt_s_pl (SD_, FD, FS, instruction_0);
5509 }
5510
5511
5512 010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
5513 "cvt.s.pu f<FD>, f<FS>"
5514 *mipsV:
5515 *mips32r2:
5516 *mips64:
5517 *mips64r2:
5518 {
5519   do_cvt_s_pu (SD_, FD, FS, instruction_0);
5520 }
5521
5522
5523 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
5524 "cvt.w.%s<FMT> f<FD>, f<FS>"
5525 *mipsI:
5526 *mipsII:
5527 *mipsIII:
5528 *mipsIV:
5529 *mipsV:
5530 *mips32:
5531 *mips32r2:
5532 *mips64:
5533 *mips64r2:
5534 *vr4100:
5535 *vr5000:
5536 *r3900:
5537 {
5538   do_cvt_w_fmt (SD_, FMT, FD, FS, instruction_0);
5539 }
5540
5541
5542 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
5543 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
5544 *mipsI:
5545 *mipsII:
5546 *mipsIII:
5547 *mipsIV:
5548 *mipsV:
5549 *mips32:
5550 *mips32r2:
5551 *mips64:
5552 *mips64r2:
5553 *vr4100:
5554 *vr5000:
5555 *r3900:
5556 {
5557   do_div_fmt (SD_, FMT, FD, FS, FT, instruction_0);
5558 }
5559
5560
5561 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
5562 "dmfc1 r<RT>, f<FS>"
5563 *mipsIII:
5564 {
5565   unsigned64 v;
5566   check_fpu (SD_);
5567   check_u64 (SD_, instruction_0);
5568   if (SizeFGR () == 64)
5569     v = FGR[FS];
5570   else if ((FS & 0x1) == 0)
5571     v = SET64HI (FGR[FS+1]) | FGR[FS];
5572   else
5573     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
5574   PENDING_FILL (RT, v);
5575   TRACE_ALU_RESULT (v);
5576 }
5577
5578 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
5579 "dmfc1 r<RT>, f<FS>"
5580 *mipsIV:
5581 *mipsV:
5582 *mips64:
5583 *mips64r2:
5584 *vr4100:
5585 *vr5000:
5586 *r3900:
5587 {
5588   check_fpu (SD_);
5589   check_u64 (SD_, instruction_0);
5590   do_dmfc1b (SD_, RT, FS);
5591 }
5592
5593
5594 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
5595 "dmtc1 r<RT>, f<FS>"
5596 *mipsIII:
5597 {
5598   unsigned64 v;
5599   check_fpu (SD_);
5600   check_u64 (SD_, instruction_0);
5601   if (SizeFGR () == 64)
5602     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
5603   else if ((FS & 0x1) == 0)
5604     {
5605       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
5606       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
5607     }
5608   else
5609     Unpredictable ();
5610   TRACE_FP_RESULT (GPR[RT]);
5611 }
5612
5613 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
5614 "dmtc1 r<RT>, f<FS>"
5615 *mipsIV:
5616 *mipsV:
5617 *mips64:
5618 *mips64r2:
5619 *vr4100:
5620 *vr5000:
5621 *r3900:
5622 {
5623   check_fpu (SD_);
5624   check_u64 (SD_, instruction_0);
5625   do_dmtc1b (SD_, RT, FS);
5626 }
5627
5628
5629 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
5630 "floor.l.%s<FMT> f<FD>, f<FS>"
5631 *mipsIII:
5632 *mipsIV:
5633 *mipsV:
5634 *mips32r2:
5635 *mips64:
5636 *mips64r2:
5637 *vr4100:
5638 *vr5000:
5639 *r3900:
5640 {
5641   do_floor_fmt (SD_, fmt_long, FMT, FD, FS);
5642 }
5643
5644
5645 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
5646 "floor.w.%s<FMT> f<FD>, f<FS>"
5647 *mipsII:
5648 *mipsIII:
5649 *mipsIV:
5650 *mipsV:
5651 *mips32:
5652 *mips32r2:
5653 *mips64:
5654 *mips64r2:
5655 *vr4100:
5656 *vr5000:
5657 *r3900:
5658 {
5659   do_floor_fmt (SD_, fmt_word, FMT, FD, FS);
5660 }
5661
5662
5663 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
5664 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
5665 *mipsII:
5666 *mips32:
5667 *mips32r2:
5668 {
5669   check_fpu (SD_);
5670   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
5671 }
5672
5673
5674 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
5675 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
5676 *mipsIII:
5677 *mipsIV:
5678 *mipsV:
5679 *mips64:
5680 *mips64r2:
5681 *vr4100:
5682 *vr5000:
5683 *r3900:
5684 {
5685   check_fpu (SD_);
5686   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
5687 }
5688
5689
5690 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
5691 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5692 *mips32r2:
5693 {
5694   check_fpu (SD_);
5695   COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
5696 }
5697
5698
5699 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
5700 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5701 *mipsIV:
5702 *mipsV:
5703 *mips64:
5704 *mips64r2:
5705 *vr5000:
5706 {
5707   check_fpu (SD_);
5708   check_u64 (SD_, instruction_0);
5709   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
5710 }
5711
5712
5713 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
5714 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
5715 *mips32r2:
5716 {
5717   do_luxc1_32 (SD_, FD, INDEX, BASE);
5718 }
5719
5720
5721 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
5722 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
5723 *mipsV:
5724 *mips64:
5725 *mips64r2:
5726 {
5727   check_fpu (SD_);
5728   check_u64 (SD_, instruction_0);
5729   do_luxc1_64 (SD_, FD, INDEX, BASE);
5730 }
5731
5732
5733 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
5734 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
5735 *mipsI:
5736 *mipsII:
5737 *mipsIII:
5738 *mipsIV:
5739 *mipsV:
5740 *mips32:
5741 *mips32r2:
5742 *mips64:
5743 *mips64r2:
5744 *vr4100:
5745 *vr5000:
5746 *r3900:
5747 {
5748   do_lwc1 (SD_, FT, OFFSET, BASE);
5749 }
5750
5751
5752 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
5753 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
5754 *mipsIV:
5755 *mipsV:
5756 *mips32r2:
5757 *mips64:
5758 *mips64r2:
5759 *vr5000:
5760 {
5761   do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0);
5762 }
5763
5764
5765
5766 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
5767 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5768 *mipsIV:
5769 *mipsV:
5770 *mips32r2:
5771 *mips64:
5772 *mips64r2:
5773 *vr5000:
5774 {
5775   do_madd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
5776 }
5777
5778
5779 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
5780 "mfc1 r<RT>, f<FS>"
5781 *mipsI:
5782 *mipsII:
5783 *mipsIII:
5784 {
5785   unsigned64 v;
5786   check_fpu (SD_);
5787   v = EXTEND32 (FGR[FS]);
5788   PENDING_FILL (RT, v);
5789   TRACE_ALU_RESULT (v);
5790 }
5791
5792 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
5793 "mfc1 r<RT>, f<FS>"
5794 *mipsIV:
5795 *mipsV:
5796 *mips32:
5797 *mips32r2:
5798 *mips64:
5799 *mips64r2:
5800 *vr4100:
5801 *vr5000:
5802 *r3900:
5803 {
5804   do_mfc1b (SD_, RT, FS);
5805 }
5806
5807
5808 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
5809 "mov.%s<FMT> f<FD>, f<FS>"
5810 *mipsI:
5811 *mipsII:
5812 *mipsIII:
5813 *mipsIV:
5814 *mipsV:
5815 *mips32:
5816 *mips32r2:
5817 *mips64:
5818 *mips64r2:
5819 *vr4100:
5820 *vr5000:
5821 *r3900:
5822 {
5823   do_mov_fmt (SD_, FMT, FD, FS, instruction_0);
5824 }
5825
5826
5827 // MOVF
5828 // MOVT
5829 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
5830 "mov%s<TF> r<RD>, r<RS>, <CC>"
5831 *mipsIV:
5832 *mipsV:
5833 *mips32:
5834 *mips32r2:
5835 *mips64:
5836 *mips64r2:
5837 *vr5000:
5838 {
5839   do_movtf (SD_, TF, RD, RS, CC);
5840 }
5841
5842
5843 // MOVF.fmt
5844 // MOVT.fmt
5845 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
5846 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
5847 *mipsIV:
5848 *mipsV:
5849 *mips32:
5850 *mips32r2:
5851 *mips64:
5852 *mips64r2:
5853 *vr5000:
5854 {
5855   do_movtf_fmt (SD_, TF, FMT, FD, FS, CC);
5856 }
5857
5858
5859 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
5860 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
5861 *mipsIV:
5862 *mipsV:
5863 *mips32:
5864 *mips32r2:
5865 *mips64:
5866 *mips64r2:
5867 *vr5000:
5868 {
5869   do_movn_fmt (SD_, FMT, FD, FS, RT);
5870 }
5871
5872
5873 // MOVT see MOVtf
5874
5875
5876 // MOVT.fmt see MOVtf.fmt
5877
5878
5879
5880 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
5881 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5882 *mipsIV:
5883 *mipsV:
5884 *mips32:
5885 *mips32r2:
5886 *mips64:
5887 *mips64r2:
5888 *vr5000:
5889 {
5890   do_movz_fmt (SD_, FMT, FD, FS, RT);
5891 }
5892
5893
5894 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
5895 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5896 *mipsIV:
5897 *mipsV:
5898 *mips32r2:
5899 *mips64:
5900 *mips64r2:
5901 *vr5000:
5902 {
5903   do_msub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
5904 }
5905
5906
5907 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
5908 "mtc1 r<RT>, f<FS>"
5909 *mipsI:
5910 *mipsII:
5911 *mipsIII:
5912 {
5913   check_fpu (SD_);
5914   if (SizeFGR () == 64)
5915     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
5916   else
5917     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
5918   TRACE_FP_RESULT (GPR[RT]);
5919 }
5920
5921 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
5922 "mtc1 r<RT>, f<FS>"
5923 *mipsIV:
5924 *mipsV:
5925 *mips32:
5926 *mips32r2:
5927 *mips64:
5928 *mips64r2:
5929 *vr4100:
5930 *vr5000:
5931 *r3900:
5932 {
5933   do_mtc1b (SD_, RT, FS);
5934 }
5935
5936
5937 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
5938 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
5939 *mipsI:
5940 *mipsII:
5941 *mipsIII:
5942 *mipsIV:
5943 *mipsV:
5944 *mips32:
5945 *mips32r2:
5946 *mips64:
5947 *mips64r2:
5948 *vr4100:
5949 *vr5000:
5950 *r3900:
5951 {
5952   do_mul_fmt (SD_, FMT, FD, FS, FT, instruction_0);
5953 }
5954
5955
5956 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
5957 "neg.%s<FMT> f<FD>, f<FS>"
5958 *mipsI:
5959 *mipsII:
5960 *mipsIII:
5961 *mipsIV:
5962 *mipsV:
5963 *mips32:
5964 *mips32r2:
5965 *mips64:
5966 *mips64r2:
5967 *vr4100:
5968 *vr5000:
5969 *r3900:
5970 {
5971   do_neg_fmt (SD_, FMT, FD, FS, instruction_0);
5972 }
5973
5974
5975 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
5976 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5977 *mipsIV:
5978 *mipsV:
5979 *mips32r2:
5980 *mips64:
5981 *mips64r2:
5982 *vr5000:
5983 {
5984   do_nmadd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
5985 }
5986
5987
5988 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
5989 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5990 *mipsIV:
5991 *mipsV:
5992 *mips32r2:
5993 *mips64:
5994 *mips64r2:
5995 *vr5000:
5996 {
5997   do_nmsub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
5998 }
5999
6000
6001 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
6002 "pll.ps f<FD>, f<FS>, f<FT>"
6003 *mipsV:
6004 *mips32r2:
6005 *mips64:
6006 *mips64r2:
6007 {
6008   do_pll_ps (SD_, FD, FS, FT, instruction_0);
6009 }
6010
6011
6012 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
6013 "plu.ps f<FD>, f<FS>, f<FT>"
6014 *mipsV:
6015 *mips32r2:
6016 *mips64:
6017 *mips64r2:
6018 {
6019   do_plu_ps (SD_, FD, FS, FT, instruction_0);
6020 }
6021
6022
6023 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
6024 "prefx <HINT>, r<INDEX>(r<BASE>)"
6025 *mipsIV:
6026 *mipsV:
6027 *mips32r2:
6028 *mips64:
6029 *mips64r2:
6030 *vr5000:
6031 {
6032   do_prefx (SD_, HINT, INDEX, BASE);
6033 }
6034
6035
6036 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
6037 "pul.ps f<FD>, f<FS>, f<FT>"
6038 *mipsV:
6039 *mips32r2:
6040 *mips64:
6041 *mips64r2:
6042 {
6043   do_pul_ps (SD_, FD, FS, FT, instruction_0);
6044 }
6045
6046
6047 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
6048 "puu.ps f<FD>, f<FS>, f<FT>"
6049 *mipsV:
6050 *mips32r2:
6051 *mips64:
6052 *mips64r2:
6053 {
6054   do_puu_ps (SD_, FD, FS, FT, instruction_0);
6055 }
6056
6057
6058 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
6059 "recip.%s<FMT> f<FD>, f<FS>"
6060 *mipsIV:
6061 *mipsV:
6062 *mips32r2:
6063 *mips64:
6064 *mips64r2:
6065 *vr5000:
6066 {
6067   do_recip_fmt (SD_, FMT, FD, FS);
6068 }
6069
6070
6071 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
6072 "round.l.%s<FMT> f<FD>, f<FS>"
6073 *mipsIII:
6074 *mipsIV:
6075 *mipsV:
6076 *mips32r2:
6077 *mips64:
6078 *mips64r2:
6079 *vr4100:
6080 *vr5000:
6081 *r3900:
6082 {
6083   do_round_fmt (SD_, fmt_long, FMT, FD, FS);
6084 }
6085
6086
6087 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
6088 "round.w.%s<FMT> f<FD>, f<FS>"
6089 *mipsII:
6090 *mipsIII:
6091 *mipsIV:
6092 *mipsV:
6093 *mips32:
6094 *mips32r2:
6095 *mips64:
6096 *mips64r2:
6097 *vr4100:
6098 *vr5000:
6099 *r3900:
6100 {
6101   do_round_fmt (SD_, fmt_word, FMT, FD, FS);
6102 }
6103
6104
6105 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
6106 "rsqrt.%s<FMT> f<FD>, f<FS>"
6107 *mipsIV:
6108 *mipsV:
6109 *mips32r2:
6110 *mips64:
6111 *mips64r2:
6112 *vr5000:
6113 {
6114   do_rsqrt_fmt (SD_, FMT, FD, FS);
6115 }
6116
6117
6118 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
6119 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
6120 *mipsII:
6121 *mips32:
6122 *mips32r2:
6123 {
6124   do_sdc1 (SD_, FT, OFFSET, BASE);
6125 }
6126
6127
6128 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
6129 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
6130 *mipsIII:
6131 *mipsIV:
6132 *mipsV:
6133 *mips64:
6134 *mips64r2:
6135 *vr4100:
6136 *vr5000:
6137 *r3900:
6138 {
6139   check_fpu (SD_);
6140   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
6141 }
6142
6143
6144 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
6145 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
6146 *mips32r2
6147 {
6148   check_fpu (SD_);
6149   do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
6150 }
6151
6152
6153 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
6154 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
6155 *mipsIV:
6156 *mipsV:
6157 *mips64:
6158 *mips64r2:
6159 *vr5000:
6160 {
6161   check_fpu (SD_);
6162   check_u64 (SD_, instruction_0);
6163   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
6164 }
6165
6166
6167 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
6168 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
6169 *mips32r2:
6170 {
6171   do_suxc1_32 (SD_, FS, INDEX, BASE);
6172 }
6173
6174
6175 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
6176 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
6177 *mipsV:
6178 *mips64:
6179 *mips64r2:
6180 {
6181   check_fpu (SD_);
6182   check_u64 (SD_, instruction_0);
6183   do_suxc1_64 (SD_, FS, INDEX, BASE);
6184 }
6185
6186
6187 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
6188 "sqrt.%s<FMT> f<FD>, f<FS>"
6189 *mipsII:
6190 *mipsIII:
6191 *mipsIV:
6192 *mipsV:
6193 *mips32:
6194 *mips32r2:
6195 *mips64:
6196 *mips64r2:
6197 *vr4100:
6198 *vr5000:
6199 *r3900:
6200 {
6201   do_sqrt_fmt (SD_, FMT, FD, FS);
6202 }
6203
6204
6205 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
6206 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
6207 *mipsI:
6208 *mipsII:
6209 *mipsIII:
6210 *mipsIV:
6211 *mipsV:
6212 *mips32:
6213 *mips32r2:
6214 *mips64:
6215 *mips64r2:
6216 *vr4100:
6217 *vr5000:
6218 *r3900:
6219 {
6220   do_sub_fmt (SD_, FMT, FD, FS, FT, instruction_0);
6221 }
6222
6223
6224
6225 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
6226 "swc1 f<FT>, <OFFSET>(r<BASE>)"
6227 *mipsI:
6228 *mipsII:
6229 *mipsIII:
6230 *mipsIV:
6231 *mipsV:
6232 *mips32:
6233 *mips32r2:
6234 *mips64:
6235 *mips64r2:
6236 *vr4100:
6237 *vr5000:
6238 *r3900:
6239 {
6240   do_swc1 (SD_, FT, OFFSET, BASE, instruction_0);
6241 }
6242
6243
6244 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
6245 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
6246 *mipsIV:
6247 *mipsV:
6248 *mips32r2:
6249 *mips64:
6250 *mips64r2:
6251 *vr5000:
6252 {
6253   do_swxc1 (SD_, FS, INDEX, BASE, instruction_0);
6254 }
6255
6256
6257 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
6258 "trunc.l.%s<FMT> f<FD>, f<FS>"
6259 *mipsIII:
6260 *mipsIV:
6261 *mipsV:
6262 *mips32r2:
6263 *mips64:
6264 *mips64r2:
6265 *vr4100:
6266 *vr5000:
6267 *r3900:
6268 {
6269   do_trunc_fmt (SD_, fmt_long, FMT, FD, FS);
6270 }
6271
6272
6273 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
6274 "trunc.w.%s<FMT> f<FD>, f<FS>"
6275 *mipsII:
6276 *mipsIII:
6277 *mipsIV:
6278 *mipsV:
6279 *mips32:
6280 *mips32r2:
6281 *mips64:
6282 *mips64r2:
6283 *vr4100:
6284 *vr5000:
6285 *r3900:
6286 {
6287   do_trunc_fmt (SD_, fmt_word, FMT, FD, FS);
6288 }
6289
6290 \f
6291 //
6292 // MIPS Architecture:
6293 //
6294 //        System Control Instruction Set (COP0)
6295 //
6296
6297
6298 010000,01000,00000,16.OFFSET:COP0:32::BC0F
6299 "bc0f <OFFSET>"
6300 *mipsI:
6301 *mipsII:
6302 *mipsIII:
6303 *mipsIV:
6304 *mipsV:
6305 *mips32:
6306 *mips32r2:
6307 *mips64:
6308 *mips64r2:
6309 *vr4100:
6310 *vr5000:
6311
6312 010000,01000,00000,16.OFFSET:COP0:32::BC0F
6313 "bc0f <OFFSET>"
6314 // stub needed for eCos as tx39 hardware bug workaround
6315 *r3900:
6316 {
6317   /* do nothing */
6318 }
6319
6320
6321 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
6322 "bc0fl <OFFSET>"
6323 *mipsI:
6324 *mipsII:
6325 *mipsIII:
6326 *mipsIV:
6327 *mipsV:
6328 *mips32:
6329 *mips32r2:
6330 *mips64:
6331 *mips64r2:
6332 *vr4100:
6333 *vr5000:
6334
6335
6336 010000,01000,00001,16.OFFSET:COP0:32::BC0T
6337 "bc0t <OFFSET>"
6338 *mipsI:
6339 *mipsII:
6340 *mipsIII:
6341 *mipsIV:
6342 *mipsV:
6343 *mips32:
6344 *mips32r2:
6345 *mips64:
6346 *mips64r2:
6347 *vr4100:
6348
6349
6350 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
6351 "bc0tl <OFFSET>"
6352 *mipsI:
6353 *mipsII:
6354 *mipsIII:
6355 *mipsIV:
6356 *mipsV:
6357 *mips32:
6358 *mips32r2:
6359 *mips64:
6360 *mips64r2:
6361 *vr4100:
6362 *vr5000:
6363
6364
6365 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
6366 "cache <OP>, <OFFSET>(r<BASE>)"
6367 *mipsIII:
6368 *mipsIV:
6369 *mipsV:
6370 *mips32:
6371 *mips32r2:
6372 *mips64:
6373 *mips64r2:
6374 *vr4100:
6375 *vr5000:
6376 *r3900:
6377 {
6378   address_word base = GPR[BASE];
6379   address_word offset = EXTEND16 (OFFSET);
6380   {
6381     address_word vaddr = loadstore_ea (SD_, base, offset);
6382     address_word paddr;
6383     int uncached;
6384     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
6385       CacheOp(OP,vaddr,paddr,instruction_0);
6386   }
6387 }
6388
6389
6390 010000,00001,5.RT,5.RD,00000000,3.SEL:COP0:64::DMFC0
6391 "dmfc0 r<RT>, r<RD>"
6392 *mipsIII:
6393 *mipsIV:
6394 *mipsV:
6395 *mips64:
6396 *mips64r2:
6397 {
6398   check_u64 (SD_, instruction_0);
6399   DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RD, SEL);
6400 }
6401
6402
6403 010000,00101,5.RT,5.RD,00000000,3.SEL:COP0:64::DMTC0
6404 "dmtc0 r<RT>, r<RD>"
6405 *mipsIII:
6406 *mipsIV:
6407 *mipsV:
6408 *mips64:
6409 *mips64r2:
6410 {
6411   check_u64 (SD_, instruction_0);
6412   DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RD, SEL);
6413 }
6414
6415
6416 010000,1,0000000000000000000,011000:COP0:32::ERET
6417 "eret"
6418 *mipsIII:
6419 *mipsIV:
6420 *mipsV:
6421 *mips32:
6422 *mips32r2:
6423 *mips64:
6424 *mips64r2:
6425 *vr4100:
6426 *vr5000:
6427 {
6428   if (SR & status_ERL)
6429     {
6430       /* Oops, not yet available */
6431       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
6432       NIA = EPC;
6433       SR &= ~status_ERL;
6434     }
6435   else
6436     {
6437       NIA = EPC;
6438       SR &= ~status_EXL;
6439     }
6440 }
6441
6442
6443 010000,00000,5.RT,5.RD,00000000,3.SEL:COP0:32::MFC0
6444 "mfc0 r<RT>, r<RD> # <SEL>"
6445 *mipsI:
6446 *mipsII:
6447 *mipsIII:
6448 *mipsIV:
6449 *mipsV:
6450 *mips32:
6451 *mips32r2:
6452 *mips64:
6453 *mips64r2:
6454 *vr4100:
6455 *vr5000:
6456 *r3900:
6457 {
6458   TRACE_ALU_INPUT0 ();
6459   DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RD, SEL);
6460   TRACE_ALU_RESULT (GPR[RT]);
6461 }
6462
6463 010000,00100,5.RT,5.RD,00000000,3.SEL:COP0:32::MTC0
6464 "mtc0 r<RT>, r<RD> # <SEL>"
6465 *mipsI:
6466 *mipsII:
6467 *mipsIII:
6468 *mipsIV:
6469 *mipsV:
6470 *mips32:
6471 *mips32r2:
6472 *mips64:
6473 *mips64r2:
6474 *vr4100:
6475 *vr5000:
6476 *r3900:
6477 {
6478   DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RD, SEL);
6479 }
6480
6481
6482 010000,1,0000000000000000000,010000:COP0:32::RFE
6483 "rfe"
6484 *mipsI:
6485 *mipsII:
6486 *mipsIII:
6487 *mipsIV:
6488 *mipsV:
6489 *vr4100:
6490 *vr5000:
6491 *r3900:
6492 {
6493   DecodeCoproc (instruction_0, 0, cp0_rfe, 0, 0, 0x10);
6494 }
6495
6496
6497 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
6498 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
6499 *mipsI:
6500 *mipsII:
6501 *mipsIII:
6502 *mipsIV:
6503 *mipsV:
6504 *mips32:
6505 *mips32r2:
6506 *mips64:
6507 *mips64r2:
6508 *vr4100:
6509 *r3900:
6510 {
6511   DecodeCoproc (instruction_0, 2, 0, 0, 0, 0);
6512 }
6513
6514
6515
6516 010000,1,0000000000000000000,001000:COP0:32::TLBP
6517 "tlbp"
6518 *mipsI:
6519 *mipsII:
6520 *mipsIII:
6521 *mipsIV:
6522 *mipsV:
6523 *mips32:
6524 *mips32r2:
6525 *mips64:
6526 *mips64r2:
6527 *vr4100:
6528 *vr5000:
6529
6530
6531 010000,1,0000000000000000000,000001:COP0:32::TLBR
6532 "tlbr"
6533 *mipsI:
6534 *mipsII:
6535 *mipsIII:
6536 *mipsIV:
6537 *mipsV:
6538 *mips32:
6539 *mips32r2:
6540 *mips64:
6541 *mips64r2:
6542 *vr4100:
6543 *vr5000:
6544
6545
6546 010000,1,0000000000000000000,000010:COP0:32::TLBWI
6547 "tlbwi"
6548 *mipsI:
6549 *mipsII:
6550 *mipsIII:
6551 *mipsIV:
6552 *mipsV:
6553 *mips32:
6554 *mips32r2:
6555 *mips64:
6556 *mips64r2:
6557 *vr4100:
6558 *vr5000:
6559
6560
6561 010000,1,0000000000000000000,000110:COP0:32::TLBWR
6562 "tlbwr"
6563 *mipsI:
6564 *mipsII:
6565 *mipsIII:
6566 *mipsIV:
6567 *mipsV:
6568 *mips32:
6569 *mips32r2:
6570 *mips64:
6571 *mips64r2:
6572 *vr4100:
6573 *vr5000:
6574
6575
6576 :include:::mips3264r2.igen
6577 :include:::m16.igen
6578 :include:::m16e.igen
6579 :include:::mdmx.igen
6580 :include:::mips3d.igen
6581 :include:::sb1.igen
6582 :include:::tx.igen
6583 :include:::vr.igen
6584 :include:::dsp.igen
6585 :include:::dsp2.igen
6586 :include:::smartmips.igen
6587 :include:::micromips.igen
6588 :include:::micromipsdsp.igen
6589