4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator are defined below.
35 // When placing models in the instruction descriptions, please place
36 // them one per line, in the order given here.
40 // Instructions and related functions for these models are included in
42 :model:::mipsI:mips3000:
43 :model:::mipsII:mips6000:
44 :model:::mipsIII:mips4000:
45 :model:::mipsIV:mips8000:
46 :model:::mipsV:mipsisaV:
47 :model:::mips32:mipsisa32:
48 :model:::mips64:mipsisa64:
52 // Standard MIPS ISA instructions used for these models are listed here,
53 // as are functions needed by those standard instructions. Instructions
54 // which are model-dependent and which are not in the standard MIPS ISAs
55 // (or which pre-date or use different encodings than the standard
56 // instructions) are (for the most part) in separate .igen files.
57 :model:::vr4100:mips4100: // vr.igen
58 :model:::vr5000:mips5000:
59 :model:::r3900:mips3900: // tx.igen
61 // MIPS Application Specific Extensions (ASEs)
63 // Instructions for the ASEs are in separate .igen files.
64 // ASEs add instructions on to a base ISA.
65 :model:::mips16:mips16: // m16.igen (and m16.dc)
66 :model:::mips3d:mips3d: // mips3d.igen
67 :model:::mdmx:mdmx: // mdmx.igen
71 // Instructions specific to these extensions are in separate .igen files.
72 // Extensions add instructions on to a base ISA.
73 :model:::sb1:sb1: // sb1.igen
76 // Pseudo instructions known by IGEN
79 SignalException (ReservedInstruction, 0);
83 // Pseudo instructions known by interp.c
84 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
85 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
88 SignalException (ReservedInstruction, instruction_0);
95 // Simulate a 32 bit delayslot instruction
98 :function:::address_word:delayslot32:address_word target
100 instruction_word delay_insn;
101 sim_events_slip (SD, 1);
103 CIA = CIA + 4; /* NOTE not mips16 */
104 STATE |= simDELAYSLOT;
105 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
106 ENGINE_ISSUE_PREFIX_HOOK();
107 idecode_issue (CPU_, delay_insn, (CIA));
108 STATE &= ~simDELAYSLOT;
112 :function:::address_word:nullify_next_insn32:
114 sim_events_slip (SD, 1);
115 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
122 // Calculate an effective address given a base and an offset.
125 :function:::address_word:loadstore_ea:address_word base, address_word offset
136 return base + offset;
139 :function:::address_word:loadstore_ea:address_word base, address_word offset
142 #if 0 /* XXX FIXME: enable this only after some additional testing. */
143 /* If in user mode and UX is not set, use 32-bit compatibility effective
144 address computations as defined in the MIPS64 Architecture for
145 Programmers Volume III, Revision 0.95, section 4.9. */
146 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
147 == (ksu_user << status_KSU_shift))
148 return (address_word)((signed32)base + (signed32)offset);
150 return base + offset;
156 // Check that a 32-bit register value is properly sign-extended.
157 // (See NotWordValue in ISA spec.)
160 :function:::int:not_word_value:unsigned_word value
170 /* For historical simulator compatibility (until documentation is
171 found that makes these operations unpredictable on some of these
172 architectures), this check never returns true. */
176 :function:::int:not_word_value:unsigned_word value
179 /* On MIPS32, since registers are 32-bits, there's no check to be done. */
183 :function:::int:not_word_value:unsigned_word value
186 return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
192 // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
193 // theoretically portable code which invokes non-portable behaviour from
194 // running with no indication of the portability issue.
195 // (See definition of UNPREDICTABLE in ISA spec.)
198 :function:::void:unpredictable:
210 :function:::void:unpredictable:
214 unpredictable_action (CPU, CIA);
220 // Check that an access to a HI/LO register meets timing requirements
222 // The following requirements exist:
224 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
225 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
226 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
227 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
230 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
232 if (history->mf.timestamp + 3 > time)
234 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
235 itable[MY_INDEX].name,
237 (long) history->mf.cia);
243 :function:::int:check_mt_hilo:hilo_history *history
252 signed64 time = sim_events_time (SD);
253 int ok = check_mf_cycles (SD_, history, time, "MT");
254 history->mt.timestamp = time;
255 history->mt.cia = CIA;
259 :function:::int:check_mt_hilo:hilo_history *history
264 signed64 time = sim_events_time (SD);
265 history->mt.timestamp = time;
266 history->mt.cia = CIA;
271 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
283 signed64 time = sim_events_time (SD);
286 && peer->mt.timestamp > history->op.timestamp
287 && history->mt.timestamp < history->op.timestamp
288 && ! (history->mf.timestamp > history->op.timestamp
289 && history->mf.timestamp < peer->mt.timestamp)
290 && ! (peer->mf.timestamp > history->op.timestamp
291 && peer->mf.timestamp < peer->mt.timestamp))
293 /* The peer has been written to since the last OP yet we have
295 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
296 itable[MY_INDEX].name,
298 (long) history->op.cia,
299 (long) peer->mt.cia);
302 history->mf.timestamp = time;
303 history->mf.cia = CIA;
309 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
318 signed64 time = sim_events_time (SD);
319 int ok = (check_mf_cycles (SD_, hi, time, "OP")
320 && check_mf_cycles (SD_, lo, time, "OP"));
321 hi->op.timestamp = time;
322 lo->op.timestamp = time;
328 // The r3900 mult and multu insns _can_ be exectuted immediatly after
330 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
335 /* FIXME: could record the fact that a stall occured if we want */
336 signed64 time = sim_events_time (SD);
337 hi->op.timestamp = time;
338 lo->op.timestamp = time;
345 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
357 signed64 time = sim_events_time (SD);
358 int ok = (check_mf_cycles (SD_, hi, time, "OP")
359 && check_mf_cycles (SD_, lo, time, "OP"));
360 hi->op.timestamp = time;
361 lo->op.timestamp = time;
370 // Check that the 64-bit instruction can currently be used, and signal
371 // a ReservedInstruction exception if not.
374 :function:::void:check_u64:instruction_word insn
381 // The check should be similar to mips64 for any with PX/UX bit equivalents.
384 :function:::void:check_u64:instruction_word insn
387 #if 0 /* XXX FIXME: enable this only after some additional testing. */
388 if (UserMode && (SR & (status_UX|status_PX)) == 0)
389 SignalException (ReservedInstruction, insn);
396 // MIPS Architecture:
398 // CPU Instruction Set (mipsI - mipsV, mips32, mips64)
403 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
404 "add r<RD>, r<RS>, r<RT>"
416 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
418 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
420 ALU32_BEGIN (GPR[RS]);
422 ALU32_END (GPR[RD]); /* This checks for overflow. */
424 TRACE_ALU_RESULT (GPR[RD]);
429 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
430 "addi r<RT>, r<RS>, <IMMEDIATE>"
442 if (NotWordValue (GPR[RS]))
444 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
446 ALU32_BEGIN (GPR[RS]);
447 ALU32_ADD (EXTEND16 (IMMEDIATE));
448 ALU32_END (GPR[RT]); /* This checks for overflow. */
450 TRACE_ALU_RESULT (GPR[RT]);
455 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
457 if (NotWordValue (GPR[rs]))
459 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
460 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
461 TRACE_ALU_RESULT (GPR[rt]);
464 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
465 "addiu r<RT>, r<RS>, <IMMEDIATE>"
477 do_addiu (SD_, RS, RT, IMMEDIATE);
482 :function:::void:do_addu:int rs, int rt, int rd
484 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
486 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
487 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
488 TRACE_ALU_RESULT (GPR[rd]);
491 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
492 "addu r<RD>, r<RS>, r<RT>"
504 do_addu (SD_, RS, RT, RD);
509 :function:::void:do_and:int rs, int rt, int rd
511 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
512 GPR[rd] = GPR[rs] & GPR[rt];
513 TRACE_ALU_RESULT (GPR[rd]);
516 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
517 "and r<RD>, r<RS>, r<RT>"
529 do_and (SD_, RS, RT, RD);
534 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
535 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
547 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
548 GPR[RT] = GPR[RS] & IMMEDIATE;
549 TRACE_ALU_RESULT (GPR[RT]);
554 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
555 "beq r<RS>, r<RT>, <OFFSET>"
567 address_word offset = EXTEND16 (OFFSET) << 2;
569 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
571 mark_branch_bug (NIA+offset);
572 DELAY_SLOT (NIA + offset);
578 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
579 "beql r<RS>, r<RT>, <OFFSET>"
590 address_word offset = EXTEND16 (OFFSET) << 2;
592 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
594 mark_branch_bug (NIA+offset);
595 DELAY_SLOT (NIA + offset);
598 NULLIFY_NEXT_INSTRUCTION ();
603 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
604 "bgez r<RS>, <OFFSET>"
616 address_word offset = EXTEND16 (OFFSET) << 2;
618 if ((signed_word) GPR[RS] >= 0)
620 mark_branch_bug (NIA+offset);
621 DELAY_SLOT (NIA + offset);
627 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
628 "bgezal r<RS>, <OFFSET>"
640 address_word offset = EXTEND16 (OFFSET) << 2;
645 if ((signed_word) GPR[RS] >= 0)
647 mark_branch_bug (NIA+offset);
648 DELAY_SLOT (NIA + offset);
654 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
655 "bgezall r<RS>, <OFFSET>"
666 address_word offset = EXTEND16 (OFFSET) << 2;
671 /* NOTE: The branch occurs AFTER the next instruction has been
673 if ((signed_word) GPR[RS] >= 0)
675 mark_branch_bug (NIA+offset);
676 DELAY_SLOT (NIA + offset);
679 NULLIFY_NEXT_INSTRUCTION ();
684 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
685 "bgezl r<RS>, <OFFSET>"
696 address_word offset = EXTEND16 (OFFSET) << 2;
698 if ((signed_word) GPR[RS] >= 0)
700 mark_branch_bug (NIA+offset);
701 DELAY_SLOT (NIA + offset);
704 NULLIFY_NEXT_INSTRUCTION ();
709 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
710 "bgtz r<RS>, <OFFSET>"
722 address_word offset = EXTEND16 (OFFSET) << 2;
724 if ((signed_word) GPR[RS] > 0)
726 mark_branch_bug (NIA+offset);
727 DELAY_SLOT (NIA + offset);
733 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
734 "bgtzl r<RS>, <OFFSET>"
745 address_word offset = EXTEND16 (OFFSET) << 2;
747 /* NOTE: The branch occurs AFTER the next instruction has been
749 if ((signed_word) GPR[RS] > 0)
751 mark_branch_bug (NIA+offset);
752 DELAY_SLOT (NIA + offset);
755 NULLIFY_NEXT_INSTRUCTION ();
760 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
761 "blez r<RS>, <OFFSET>"
773 address_word offset = EXTEND16 (OFFSET) << 2;
775 /* NOTE: The branch occurs AFTER the next instruction has been
777 if ((signed_word) GPR[RS] <= 0)
779 mark_branch_bug (NIA+offset);
780 DELAY_SLOT (NIA + offset);
786 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
787 "bgezl r<RS>, <OFFSET>"
798 address_word offset = EXTEND16 (OFFSET) << 2;
800 if ((signed_word) GPR[RS] <= 0)
802 mark_branch_bug (NIA+offset);
803 DELAY_SLOT (NIA + offset);
806 NULLIFY_NEXT_INSTRUCTION ();
811 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
812 "bltz r<RS>, <OFFSET>"
824 address_word offset = EXTEND16 (OFFSET) << 2;
826 if ((signed_word) GPR[RS] < 0)
828 mark_branch_bug (NIA+offset);
829 DELAY_SLOT (NIA + offset);
835 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
836 "bltzal r<RS>, <OFFSET>"
848 address_word offset = EXTEND16 (OFFSET) << 2;
853 /* NOTE: The branch occurs AFTER the next instruction has been
855 if ((signed_word) GPR[RS] < 0)
857 mark_branch_bug (NIA+offset);
858 DELAY_SLOT (NIA + offset);
864 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
865 "bltzall r<RS>, <OFFSET>"
876 address_word offset = EXTEND16 (OFFSET) << 2;
881 if ((signed_word) GPR[RS] < 0)
883 mark_branch_bug (NIA+offset);
884 DELAY_SLOT (NIA + offset);
887 NULLIFY_NEXT_INSTRUCTION ();
892 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
893 "bltzl r<RS>, <OFFSET>"
904 address_word offset = EXTEND16 (OFFSET) << 2;
906 /* NOTE: The branch occurs AFTER the next instruction has been
908 if ((signed_word) GPR[RS] < 0)
910 mark_branch_bug (NIA+offset);
911 DELAY_SLOT (NIA + offset);
914 NULLIFY_NEXT_INSTRUCTION ();
919 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
920 "bne r<RS>, r<RT>, <OFFSET>"
932 address_word offset = EXTEND16 (OFFSET) << 2;
934 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
936 mark_branch_bug (NIA+offset);
937 DELAY_SLOT (NIA + offset);
943 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
944 "bnel r<RS>, r<RT>, <OFFSET>"
955 address_word offset = EXTEND16 (OFFSET) << 2;
957 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
959 mark_branch_bug (NIA+offset);
960 DELAY_SLOT (NIA + offset);
963 NULLIFY_NEXT_INSTRUCTION ();
968 000000,20.CODE,001101:SPECIAL:32::BREAK
981 /* Check for some break instruction which are reserved for use by the simulator. */
982 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
983 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
984 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
986 sim_engine_halt (SD, CPU, NULL, cia,
987 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
989 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
990 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
992 if (STATE & simDELAYSLOT)
993 PC = cia - 4; /* reference the branch instruction */
996 SignalException (BreakPoint, instruction_0);
1001 /* If we get this far, we're not an instruction reserved by the sim. Raise
1003 SignalException (BreakPoint, instruction_0);
1009 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1014 unsigned32 temp = GPR[RS];
1018 if (NotWordValue (GPR[RS]))
1020 TRACE_ALU_INPUT1 (GPR[RS]);
1021 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1023 if ((temp & mask) == 0)
1027 GPR[RD] = EXTEND32 (i);
1028 TRACE_ALU_RESULT (GPR[RD]);
1033 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1038 unsigned32 temp = GPR[RS];
1042 if (NotWordValue (GPR[RS]))
1044 TRACE_ALU_INPUT1 (GPR[RS]);
1045 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1047 if ((temp & mask) != 0)
1051 GPR[RD] = EXTEND32 (i);
1052 TRACE_ALU_RESULT (GPR[RD]);
1057 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1058 "dadd r<RD>, r<RS>, r<RT>"
1066 check_u64 (SD_, instruction_0);
1067 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1069 ALU64_BEGIN (GPR[RS]);
1070 ALU64_ADD (GPR[RT]);
1071 ALU64_END (GPR[RD]); /* This checks for overflow. */
1073 TRACE_ALU_RESULT (GPR[RD]);
1078 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1079 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1087 check_u64 (SD_, instruction_0);
1088 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1090 ALU64_BEGIN (GPR[RS]);
1091 ALU64_ADD (EXTEND16 (IMMEDIATE));
1092 ALU64_END (GPR[RT]); /* This checks for overflow. */
1094 TRACE_ALU_RESULT (GPR[RT]);
1099 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1101 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1102 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1103 TRACE_ALU_RESULT (GPR[rt]);
1106 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1107 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1115 check_u64 (SD_, instruction_0);
1116 do_daddiu (SD_, RS, RT, IMMEDIATE);
1121 :function:::void:do_daddu:int rs, int rt, int rd
1123 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1124 GPR[rd] = GPR[rs] + GPR[rt];
1125 TRACE_ALU_RESULT (GPR[rd]);
1128 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1129 "daddu r<RD>, r<RS>, r<RT>"
1137 check_u64 (SD_, instruction_0);
1138 do_daddu (SD_, RS, RT, RD);
1143 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1147 unsigned64 temp = GPR[RS];
1150 check_u64 (SD_, instruction_0);
1153 TRACE_ALU_INPUT1 (GPR[RS]);
1154 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1156 if ((temp & mask) == 0)
1160 GPR[RD] = EXTEND32 (i);
1161 TRACE_ALU_RESULT (GPR[RD]);
1166 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1170 unsigned64 temp = GPR[RS];
1173 check_u64 (SD_, instruction_0);
1176 TRACE_ALU_INPUT1 (GPR[RS]);
1177 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1179 if ((temp & mask) != 0)
1183 GPR[RD] = EXTEND32 (i);
1184 TRACE_ALU_RESULT (GPR[RD]);
1189 :function:::void:do_ddiv:int rs, int rt
1191 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1192 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1194 signed64 n = GPR[rs];
1195 signed64 d = GPR[rt];
1200 lo = SIGNED64 (0x8000000000000000);
1203 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1205 lo = SIGNED64 (0x8000000000000000);
1216 TRACE_ALU_RESULT2 (HI, LO);
1219 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1228 check_u64 (SD_, instruction_0);
1229 do_ddiv (SD_, RS, RT);
1234 :function:::void:do_ddivu:int rs, int rt
1236 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1237 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1239 unsigned64 n = GPR[rs];
1240 unsigned64 d = GPR[rt];
1245 lo = SIGNED64 (0x8000000000000000);
1256 TRACE_ALU_RESULT2 (HI, LO);
1259 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1260 "ddivu r<RS>, r<RT>"
1268 check_u64 (SD_, instruction_0);
1269 do_ddivu (SD_, RS, RT);
1274 :function:::void:do_div:int rs, int rt
1276 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1277 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1279 signed32 n = GPR[rs];
1280 signed32 d = GPR[rt];
1283 LO = EXTEND32 (0x80000000);
1286 else if (n == SIGNED32 (0x80000000) && d == -1)
1288 LO = EXTEND32 (0x80000000);
1293 LO = EXTEND32 (n / d);
1294 HI = EXTEND32 (n % d);
1297 TRACE_ALU_RESULT2 (HI, LO);
1300 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1313 do_div (SD_, RS, RT);
1318 :function:::void:do_divu:int rs, int rt
1320 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1321 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1323 unsigned32 n = GPR[rs];
1324 unsigned32 d = GPR[rt];
1327 LO = EXTEND32 (0x80000000);
1332 LO = EXTEND32 (n / d);
1333 HI = EXTEND32 (n % d);
1336 TRACE_ALU_RESULT2 (HI, LO);
1339 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1352 do_divu (SD_, RS, RT);
1357 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1367 unsigned64 op1 = GPR[rs];
1368 unsigned64 op2 = GPR[rt];
1369 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1370 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1371 /* make signed multiply unsigned */
1386 /* multiply out the 4 sub products */
1387 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1388 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1389 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1390 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1391 /* add the products */
1392 mid = ((unsigned64) VH4_8 (m00)
1393 + (unsigned64) VL4_8 (m10)
1394 + (unsigned64) VL4_8 (m01));
1395 lo = U8_4 (mid, m00);
1397 + (unsigned64) VH4_8 (mid)
1398 + (unsigned64) VH4_8 (m01)
1399 + (unsigned64) VH4_8 (m10));
1409 /* save the result HI/LO (and a gpr) */
1414 TRACE_ALU_RESULT2 (HI, LO);
1417 :function:::void:do_dmult:int rs, int rt, int rd
1419 do_dmultx (SD_, rs, rt, rd, 1);
1422 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1423 "dmult r<RS>, r<RT>"
1430 check_u64 (SD_, instruction_0);
1431 do_dmult (SD_, RS, RT, 0);
1434 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1435 "dmult r<RS>, r<RT>":RD == 0
1436 "dmult r<RD>, r<RS>, r<RT>"
1439 check_u64 (SD_, instruction_0);
1440 do_dmult (SD_, RS, RT, RD);
1445 :function:::void:do_dmultu:int rs, int rt, int rd
1447 do_dmultx (SD_, rs, rt, rd, 0);
1450 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1451 "dmultu r<RS>, r<RT>"
1458 check_u64 (SD_, instruction_0);
1459 do_dmultu (SD_, RS, RT, 0);
1462 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1463 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1464 "dmultu r<RS>, r<RT>"
1467 check_u64 (SD_, instruction_0);
1468 do_dmultu (SD_, RS, RT, RD);
1471 :function:::void:do_dsll:int rt, int rd, int shift
1473 TRACE_ALU_INPUT2 (GPR[rt], shift);
1474 GPR[rd] = GPR[rt] << shift;
1475 TRACE_ALU_RESULT (GPR[rd]);
1478 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1479 "dsll r<RD>, r<RT>, <SHIFT>"
1487 check_u64 (SD_, instruction_0);
1488 do_dsll (SD_, RT, RD, SHIFT);
1492 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1493 "dsll32 r<RD>, r<RT>, <SHIFT>"
1502 check_u64 (SD_, instruction_0);
1503 TRACE_ALU_INPUT2 (GPR[RT], s);
1504 GPR[RD] = GPR[RT] << s;
1505 TRACE_ALU_RESULT (GPR[RD]);
1508 :function:::void:do_dsllv:int rs, int rt, int rd
1510 int s = MASKED64 (GPR[rs], 5, 0);
1511 TRACE_ALU_INPUT2 (GPR[rt], s);
1512 GPR[rd] = GPR[rt] << s;
1513 TRACE_ALU_RESULT (GPR[rd]);
1516 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1517 "dsllv r<RD>, r<RT>, r<RS>"
1525 check_u64 (SD_, instruction_0);
1526 do_dsllv (SD_, RS, RT, RD);
1529 :function:::void:do_dsra:int rt, int rd, int shift
1531 TRACE_ALU_INPUT2 (GPR[rt], shift);
1532 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1533 TRACE_ALU_RESULT (GPR[rd]);
1537 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1538 "dsra r<RD>, r<RT>, <SHIFT>"
1546 check_u64 (SD_, instruction_0);
1547 do_dsra (SD_, RT, RD, SHIFT);
1551 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1552 "dsra32 r<RD>, r<RT>, <SHIFT>"
1561 check_u64 (SD_, instruction_0);
1562 TRACE_ALU_INPUT2 (GPR[RT], s);
1563 GPR[RD] = ((signed64) GPR[RT]) >> s;
1564 TRACE_ALU_RESULT (GPR[RD]);
1568 :function:::void:do_dsrav:int rs, int rt, int rd
1570 int s = MASKED64 (GPR[rs], 5, 0);
1571 TRACE_ALU_INPUT2 (GPR[rt], s);
1572 GPR[rd] = ((signed64) GPR[rt]) >> s;
1573 TRACE_ALU_RESULT (GPR[rd]);
1576 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1577 "dsrav r<RD>, r<RT>, r<RS>"
1585 check_u64 (SD_, instruction_0);
1586 do_dsrav (SD_, RS, RT, RD);
1589 :function:::void:do_dsrl:int rt, int rd, int shift
1591 TRACE_ALU_INPUT2 (GPR[rt], shift);
1592 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1593 TRACE_ALU_RESULT (GPR[rd]);
1597 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1598 "dsrl r<RD>, r<RT>, <SHIFT>"
1606 check_u64 (SD_, instruction_0);
1607 do_dsrl (SD_, RT, RD, SHIFT);
1611 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1612 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1621 check_u64 (SD_, instruction_0);
1622 TRACE_ALU_INPUT2 (GPR[RT], s);
1623 GPR[RD] = (unsigned64) GPR[RT] >> s;
1624 TRACE_ALU_RESULT (GPR[RD]);
1628 :function:::void:do_dsrlv:int rs, int rt, int rd
1630 int s = MASKED64 (GPR[rs], 5, 0);
1631 TRACE_ALU_INPUT2 (GPR[rt], s);
1632 GPR[rd] = (unsigned64) GPR[rt] >> s;
1633 TRACE_ALU_RESULT (GPR[rd]);
1638 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1639 "dsrlv r<RD>, r<RT>, r<RS>"
1647 check_u64 (SD_, instruction_0);
1648 do_dsrlv (SD_, RS, RT, RD);
1652 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1653 "dsub r<RD>, r<RS>, r<RT>"
1661 check_u64 (SD_, instruction_0);
1662 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1664 ALU64_BEGIN (GPR[RS]);
1665 ALU64_SUB (GPR[RT]);
1666 ALU64_END (GPR[RD]); /* This checks for overflow. */
1668 TRACE_ALU_RESULT (GPR[RD]);
1672 :function:::void:do_dsubu:int rs, int rt, int rd
1674 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1675 GPR[rd] = GPR[rs] - GPR[rt];
1676 TRACE_ALU_RESULT (GPR[rd]);
1679 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1680 "dsubu r<RD>, r<RS>, r<RT>"
1688 check_u64 (SD_, instruction_0);
1689 do_dsubu (SD_, RS, RT, RD);
1693 000010,26.INSTR_INDEX:NORMAL:32::J
1706 /* NOTE: The region used is that of the delay slot NIA and NOT the
1707 current instruction */
1708 address_word region = (NIA & MASK (63, 28));
1709 DELAY_SLOT (region | (INSTR_INDEX << 2));
1713 000011,26.INSTR_INDEX:NORMAL:32::JAL
1726 /* NOTE: The region used is that of the delay slot and NOT the
1727 current instruction */
1728 address_word region = (NIA & MASK (63, 28));
1730 DELAY_SLOT (region | (INSTR_INDEX << 2));
1733 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1734 "jalr r<RS>":RD == 31
1747 address_word temp = GPR[RS];
1753 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1766 DELAY_SLOT (GPR[RS]);
1770 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1772 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1773 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1774 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1781 vaddr = loadstore_ea (SD_, base, offset);
1782 if ((vaddr & access) != 0)
1784 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1786 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1787 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1788 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1789 byte = ((vaddr & mask) ^ bigendiancpu);
1790 return (memval >> (8 * byte));
1793 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1795 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1796 address_word reverseendian = (ReverseEndian ? -1 : 0);
1797 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1806 unsigned_word lhs_mask;
1809 vaddr = loadstore_ea (SD_, base, offset);
1810 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1811 paddr = (paddr ^ (reverseendian & mask));
1812 if (BigEndianMem == 0)
1813 paddr = paddr & ~access;
1815 /* compute where within the word/mem we are */
1816 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1817 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1818 nr_lhs_bits = 8 * byte + 8;
1819 nr_rhs_bits = 8 * access - 8 * byte;
1820 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1822 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1823 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1824 (long) ((unsigned64) paddr >> 32), (long) paddr,
1825 word, byte, nr_lhs_bits, nr_rhs_bits); */
1827 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1830 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1831 temp = (memval << nr_rhs_bits);
1835 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1836 temp = (memval >> nr_lhs_bits);
1838 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1839 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1841 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1842 (long) ((unsigned64) memval >> 32), (long) memval,
1843 (long) ((unsigned64) temp >> 32), (long) temp,
1844 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1845 (long) (rt >> 32), (long) rt); */
1849 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1851 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1852 address_word reverseendian = (ReverseEndian ? -1 : 0);
1853 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1860 vaddr = loadstore_ea (SD_, base, offset);
1861 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1862 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1863 paddr = (paddr ^ (reverseendian & mask));
1864 if (BigEndianMem != 0)
1865 paddr = paddr & ~access;
1866 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1867 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1868 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1869 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1870 (long) paddr, byte, (long) paddr, (long) memval); */
1872 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1874 rt |= (memval >> (8 * byte)) & screen;
1880 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1881 "lb r<RT>, <OFFSET>(r<BASE>)"
1893 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1897 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1898 "lbu r<RT>, <OFFSET>(r<BASE>)"
1910 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1914 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1915 "ld r<RT>, <OFFSET>(r<BASE>)"
1923 check_u64 (SD_, instruction_0);
1924 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1928 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1929 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1940 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1946 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1947 "ldl r<RT>, <OFFSET>(r<BASE>)"
1955 check_u64 (SD_, instruction_0);
1956 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1960 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1961 "ldr r<RT>, <OFFSET>(r<BASE>)"
1969 check_u64 (SD_, instruction_0);
1970 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1974 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1975 "lh r<RT>, <OFFSET>(r<BASE>)"
1987 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1991 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1992 "lhu r<RT>, <OFFSET>(r<BASE>)"
2004 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2008 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2009 "ll r<RT>, <OFFSET>(r<BASE>)"
2019 address_word base = GPR[BASE];
2020 address_word offset = EXTEND16 (OFFSET);
2022 address_word vaddr = loadstore_ea (SD_, base, offset);
2025 if ((vaddr & 3) != 0)
2027 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2031 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2033 unsigned64 memval = 0;
2034 unsigned64 memval1 = 0;
2035 unsigned64 mask = 0x7;
2036 unsigned int shift = 2;
2037 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2038 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2040 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2041 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2042 byte = ((vaddr & mask) ^ (bigend << shift));
2043 GPR[RT] = EXTEND32 (memval >> (8 * byte));
2051 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2052 "lld r<RT>, <OFFSET>(r<BASE>)"
2060 address_word base = GPR[BASE];
2061 address_word offset = EXTEND16 (OFFSET);
2062 check_u64 (SD_, instruction_0);
2064 address_word vaddr = loadstore_ea (SD_, base, offset);
2067 if ((vaddr & 7) != 0)
2069 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2073 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2075 unsigned64 memval = 0;
2076 unsigned64 memval1 = 0;
2077 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2086 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2087 "lui r<RT>, %#lx<IMMEDIATE>"
2099 TRACE_ALU_INPUT1 (IMMEDIATE);
2100 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2101 TRACE_ALU_RESULT (GPR[RT]);
2105 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2106 "lw r<RT>, <OFFSET>(r<BASE>)"
2118 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2122 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2123 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2135 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2139 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2140 "lwl r<RT>, <OFFSET>(r<BASE>)"
2152 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2156 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2157 "lwr r<RT>, <OFFSET>(r<BASE>)"
2169 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2173 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2174 "lwu r<RT>, <OFFSET>(r<BASE>)"
2182 check_u64 (SD_, instruction_0);
2183 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2188 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2194 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2195 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2197 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2198 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2199 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2200 LO = EXTEND32 (temp);
2201 HI = EXTEND32 (VH4_8 (temp));
2202 TRACE_ALU_RESULT2 (HI, LO);
2207 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2208 "maddu r<RS>, r<RT>"
2213 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2214 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2216 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2217 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2218 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2219 LO = EXTEND32 (temp);
2220 HI = EXTEND32 (VH4_8 (temp));
2221 TRACE_ALU_RESULT2 (HI, LO);
2225 :function:::void:do_mfhi:int rd
2227 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2228 TRACE_ALU_INPUT1 (HI);
2230 TRACE_ALU_RESULT (GPR[rd]);
2233 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2251 :function:::void:do_mflo:int rd
2253 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2254 TRACE_ALU_INPUT1 (LO);
2256 TRACE_ALU_RESULT (GPR[rd]);
2259 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2277 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2278 "movn r<RD>, r<RS>, r<RT>"
2288 TRACE_ALU_RESULT (GPR[RD]);
2294 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2295 "movz r<RD>, r<RS>, r<RT>"
2305 TRACE_ALU_RESULT (GPR[RD]);
2311 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2317 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2318 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2320 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2321 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2322 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2323 LO = EXTEND32 (temp);
2324 HI = EXTEND32 (VH4_8 (temp));
2325 TRACE_ALU_RESULT2 (HI, LO);
2330 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2331 "msubu r<RS>, r<RT>"
2336 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2337 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2339 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2340 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2341 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2342 LO = EXTEND32 (temp);
2343 HI = EXTEND32 (VH4_8 (temp));
2344 TRACE_ALU_RESULT2 (HI, LO);
2349 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2362 check_mt_hilo (SD_, HIHISTORY);
2368 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2381 check_mt_hilo (SD_, LOHISTORY);
2387 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2388 "mul r<RD>, r<RS>, r<RT>"
2393 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2395 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2396 prod = (((signed64)(signed32) GPR[RS])
2397 * ((signed64)(signed32) GPR[RT]));
2398 GPR[RD] = EXTEND32 (VL4_8 (prod));
2399 TRACE_ALU_RESULT (GPR[RD]);
2404 :function:::void:do_mult:int rs, int rt, int rd
2407 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2408 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2410 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2411 prod = (((signed64)(signed32) GPR[rs])
2412 * ((signed64)(signed32) GPR[rt]));
2413 LO = EXTEND32 (VL4_8 (prod));
2414 HI = EXTEND32 (VH4_8 (prod));
2417 TRACE_ALU_RESULT2 (HI, LO);
2420 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2431 do_mult (SD_, RS, RT, 0);
2435 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2436 "mult r<RS>, r<RT>":RD == 0
2437 "mult r<RD>, r<RS>, r<RT>"
2441 do_mult (SD_, RS, RT, RD);
2445 :function:::void:do_multu:int rs, int rt, int rd
2448 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2449 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2451 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2452 prod = (((unsigned64)(unsigned32) GPR[rs])
2453 * ((unsigned64)(unsigned32) GPR[rt]));
2454 LO = EXTEND32 (VL4_8 (prod));
2455 HI = EXTEND32 (VH4_8 (prod));
2458 TRACE_ALU_RESULT2 (HI, LO);
2461 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2462 "multu r<RS>, r<RT>"
2472 do_multu (SD_, RS, RT, 0);
2475 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2476 "multu r<RS>, r<RT>":RD == 0
2477 "multu r<RD>, r<RS>, r<RT>"
2481 do_multu (SD_, RS, RT, RD);
2485 :function:::void:do_nor:int rs, int rt, int rd
2487 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2488 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2489 TRACE_ALU_RESULT (GPR[rd]);
2492 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2493 "nor r<RD>, r<RS>, r<RT>"
2505 do_nor (SD_, RS, RT, RD);
2509 :function:::void:do_or:int rs, int rt, int rd
2511 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2512 GPR[rd] = (GPR[rs] | GPR[rt]);
2513 TRACE_ALU_RESULT (GPR[rd]);
2516 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2517 "or r<RD>, r<RS>, r<RT>"
2529 do_or (SD_, RS, RT, RD);
2534 :function:::void:do_ori:int rs, int rt, unsigned immediate
2536 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2537 GPR[rt] = (GPR[rs] | immediate);
2538 TRACE_ALU_RESULT (GPR[rt]);
2541 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2542 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2554 do_ori (SD_, RS, RT, IMMEDIATE);
2558 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2559 "pref <HINT>, <OFFSET>(r<BASE>)"
2566 address_word base = GPR[BASE];
2567 address_word offset = EXTEND16 (OFFSET);
2569 address_word vaddr = loadstore_ea (SD_, base, offset);
2573 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2574 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2580 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2582 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2583 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2584 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2591 vaddr = loadstore_ea (SD_, base, offset);
2592 if ((vaddr & access) != 0)
2594 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2596 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2597 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2598 byte = ((vaddr & mask) ^ bigendiancpu);
2599 memval = (word << (8 * byte));
2600 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2603 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2605 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2606 address_word reverseendian = (ReverseEndian ? -1 : 0);
2607 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2617 vaddr = loadstore_ea (SD_, base, offset);
2618 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2619 paddr = (paddr ^ (reverseendian & mask));
2620 if (BigEndianMem == 0)
2621 paddr = paddr & ~access;
2623 /* compute where within the word/mem we are */
2624 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2625 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2626 nr_lhs_bits = 8 * byte + 8;
2627 nr_rhs_bits = 8 * access - 8 * byte;
2628 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2629 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2630 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2631 (long) ((unsigned64) paddr >> 32), (long) paddr,
2632 word, byte, nr_lhs_bits, nr_rhs_bits); */
2636 memval = (rt >> nr_rhs_bits);
2640 memval = (rt << nr_lhs_bits);
2642 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2643 (long) ((unsigned64) rt >> 32), (long) rt,
2644 (long) ((unsigned64) memval >> 32), (long) memval); */
2645 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2648 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2650 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2651 address_word reverseendian = (ReverseEndian ? -1 : 0);
2652 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2659 vaddr = loadstore_ea (SD_, base, offset);
2660 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2661 paddr = (paddr ^ (reverseendian & mask));
2662 if (BigEndianMem != 0)
2664 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2665 memval = (rt << (byte * 8));
2666 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2670 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2671 "sb r<RT>, <OFFSET>(r<BASE>)"
2683 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2687 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2688 "sc r<RT>, <OFFSET>(r<BASE>)"
2698 unsigned32 instruction = instruction_0;
2699 address_word base = GPR[BASE];
2700 address_word offset = EXTEND16 (OFFSET);
2702 address_word vaddr = loadstore_ea (SD_, base, offset);
2705 if ((vaddr & 3) != 0)
2707 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2711 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2713 unsigned64 memval = 0;
2714 unsigned64 memval1 = 0;
2715 unsigned64 mask = 0x7;
2717 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2718 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2719 memval = ((unsigned64) GPR[RT] << (8 * byte));
2722 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2731 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2732 "scd r<RT>, <OFFSET>(r<BASE>)"
2740 address_word base = GPR[BASE];
2741 address_word offset = EXTEND16 (OFFSET);
2742 check_u64 (SD_, instruction_0);
2744 address_word vaddr = loadstore_ea (SD_, base, offset);
2747 if ((vaddr & 7) != 0)
2749 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2753 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2755 unsigned64 memval = 0;
2756 unsigned64 memval1 = 0;
2760 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2769 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2770 "sd r<RT>, <OFFSET>(r<BASE>)"
2778 check_u64 (SD_, instruction_0);
2779 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2783 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2784 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2794 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2798 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2799 "sdl r<RT>, <OFFSET>(r<BASE>)"
2807 check_u64 (SD_, instruction_0);
2808 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2812 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2813 "sdr r<RT>, <OFFSET>(r<BASE>)"
2821 check_u64 (SD_, instruction_0);
2822 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2826 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2827 "sh r<RT>, <OFFSET>(r<BASE>)"
2839 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2843 :function:::void:do_sll:int rt, int rd, int shift
2845 unsigned32 temp = (GPR[rt] << shift);
2846 TRACE_ALU_INPUT2 (GPR[rt], shift);
2847 GPR[rd] = EXTEND32 (temp);
2848 TRACE_ALU_RESULT (GPR[rd]);
2851 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2852 "nop":RD == 0 && RT == 0 && SHIFT == 0
2853 "sll r<RD>, r<RT>, <SHIFT>"
2863 /* Skip shift for NOP, so that there won't be lots of extraneous
2865 if (RD != 0 || RT != 0 || SHIFT != 0)
2866 do_sll (SD_, RT, RD, SHIFT);
2869 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2870 "nop":RD == 0 && RT == 0 && SHIFT == 0
2871 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2872 "sll r<RD>, r<RT>, <SHIFT>"
2876 /* Skip shift for NOP and SSNOP, so that there won't be lots of
2877 extraneous trace output. */
2878 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2879 do_sll (SD_, RT, RD, SHIFT);
2883 :function:::void:do_sllv:int rs, int rt, int rd
2885 int s = MASKED (GPR[rs], 4, 0);
2886 unsigned32 temp = (GPR[rt] << s);
2887 TRACE_ALU_INPUT2 (GPR[rt], s);
2888 GPR[rd] = EXTEND32 (temp);
2889 TRACE_ALU_RESULT (GPR[rd]);
2892 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2893 "sllv r<RD>, r<RT>, r<RS>"
2905 do_sllv (SD_, RS, RT, RD);
2909 :function:::void:do_slt:int rs, int rt, int rd
2911 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2912 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2913 TRACE_ALU_RESULT (GPR[rd]);
2916 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2917 "slt r<RD>, r<RS>, r<RT>"
2929 do_slt (SD_, RS, RT, RD);
2933 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2935 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2936 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2937 TRACE_ALU_RESULT (GPR[rt]);
2940 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2941 "slti r<RT>, r<RS>, <IMMEDIATE>"
2953 do_slti (SD_, RS, RT, IMMEDIATE);
2957 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2959 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2960 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2961 TRACE_ALU_RESULT (GPR[rt]);
2964 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2965 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2977 do_sltiu (SD_, RS, RT, IMMEDIATE);
2982 :function:::void:do_sltu:int rs, int rt, int rd
2984 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2985 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2986 TRACE_ALU_RESULT (GPR[rd]);
2989 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2990 "sltu r<RD>, r<RS>, r<RT>"
3002 do_sltu (SD_, RS, RT, RD);
3006 :function:::void:do_sra:int rt, int rd, int shift
3008 signed32 temp = (signed32) GPR[rt] >> shift;
3009 if (NotWordValue (GPR[rt]))
3011 TRACE_ALU_INPUT2 (GPR[rt], shift);
3012 GPR[rd] = EXTEND32 (temp);
3013 TRACE_ALU_RESULT (GPR[rd]);
3016 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3017 "sra r<RD>, r<RT>, <SHIFT>"
3029 do_sra (SD_, RT, RD, SHIFT);
3034 :function:::void:do_srav:int rs, int rt, int rd
3036 int s = MASKED (GPR[rs], 4, 0);
3037 signed32 temp = (signed32) GPR[rt] >> s;
3038 if (NotWordValue (GPR[rt]))
3040 TRACE_ALU_INPUT2 (GPR[rt], s);
3041 GPR[rd] = EXTEND32 (temp);
3042 TRACE_ALU_RESULT (GPR[rd]);
3045 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3046 "srav r<RD>, r<RT>, r<RS>"
3058 do_srav (SD_, RS, RT, RD);
3063 :function:::void:do_srl:int rt, int rd, int shift
3065 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3066 if (NotWordValue (GPR[rt]))
3068 TRACE_ALU_INPUT2 (GPR[rt], shift);
3069 GPR[rd] = EXTEND32 (temp);
3070 TRACE_ALU_RESULT (GPR[rd]);
3073 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3074 "srl r<RD>, r<RT>, <SHIFT>"
3086 do_srl (SD_, RT, RD, SHIFT);
3090 :function:::void:do_srlv:int rs, int rt, int rd
3092 int s = MASKED (GPR[rs], 4, 0);
3093 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3094 if (NotWordValue (GPR[rt]))
3096 TRACE_ALU_INPUT2 (GPR[rt], s);
3097 GPR[rd] = EXTEND32 (temp);
3098 TRACE_ALU_RESULT (GPR[rd]);
3101 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3102 "srlv r<RD>, r<RT>, r<RS>"
3114 do_srlv (SD_, RS, RT, RD);
3118 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3119 "sub r<RD>, r<RS>, r<RT>"
3131 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3133 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3135 ALU32_BEGIN (GPR[RS]);
3136 ALU32_SUB (GPR[RT]);
3137 ALU32_END (GPR[RD]); /* This checks for overflow. */
3139 TRACE_ALU_RESULT (GPR[RD]);
3143 :function:::void:do_subu:int rs, int rt, int rd
3145 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3147 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3148 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3149 TRACE_ALU_RESULT (GPR[rd]);
3152 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3153 "subu r<RD>, r<RS>, r<RT>"
3165 do_subu (SD_, RS, RT, RD);
3169 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3170 "sw r<RT>, <OFFSET>(r<BASE>)"
3182 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3186 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3187 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3199 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3203 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3204 "swl r<RT>, <OFFSET>(r<BASE>)"
3216 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3220 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3221 "swr r<RT>, <OFFSET>(r<BASE>)"
3233 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3237 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3250 SyncOperation (STYPE);
3254 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3255 "syscall %#lx<CODE>"
3267 SignalException (SystemCall, instruction_0);
3271 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3282 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3283 SignalException (Trap, instruction_0);
3287 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3288 "teqi r<RS>, <IMMEDIATE>"
3298 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3299 SignalException (Trap, instruction_0);
3303 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3314 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3315 SignalException (Trap, instruction_0);
3319 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3320 "tgei r<RS>, <IMMEDIATE>"
3330 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3331 SignalException (Trap, instruction_0);
3335 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3336 "tgeiu r<RS>, <IMMEDIATE>"
3346 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3347 SignalException (Trap, instruction_0);
3351 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3362 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3363 SignalException (Trap, instruction_0);
3367 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3378 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3379 SignalException (Trap, instruction_0);
3383 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3384 "tlti r<RS>, <IMMEDIATE>"
3394 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3395 SignalException (Trap, instruction_0);
3399 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3400 "tltiu r<RS>, <IMMEDIATE>"
3410 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3411 SignalException (Trap, instruction_0);
3415 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3426 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3427 SignalException (Trap, instruction_0);
3431 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3442 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3443 SignalException (Trap, instruction_0);
3447 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3448 "tnei r<RS>, <IMMEDIATE>"
3458 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3459 SignalException (Trap, instruction_0);
3463 :function:::void:do_xor:int rs, int rt, int rd
3465 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3466 GPR[rd] = GPR[rs] ^ GPR[rt];
3467 TRACE_ALU_RESULT (GPR[rd]);
3470 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3471 "xor r<RD>, r<RS>, r<RT>"
3483 do_xor (SD_, RS, RT, RD);
3487 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3489 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3490 GPR[rt] = GPR[rs] ^ immediate;
3491 TRACE_ALU_RESULT (GPR[rt]);
3494 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3495 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3507 do_xori (SD_, RS, RT, IMMEDIATE);
3512 // MIPS Architecture:
3514 // FPU Instruction Set (COP1 & COP1X)
3522 case fmt_single: return "s";
3523 case fmt_double: return "d";
3524 case fmt_word: return "w";
3525 case fmt_long: return "l";
3526 case fmt_ps: return "ps";
3527 default: return "?";
3547 :%s::::COND:int cond
3551 case 00: return "f";
3552 case 01: return "un";
3553 case 02: return "eq";
3554 case 03: return "ueq";
3555 case 04: return "olt";
3556 case 05: return "ult";
3557 case 06: return "ole";
3558 case 07: return "ule";
3559 case 010: return "sf";
3560 case 011: return "ngle";
3561 case 012: return "seq";
3562 case 013: return "ngl";
3563 case 014: return "lt";
3564 case 015: return "nge";
3565 case 016: return "le";
3566 case 017: return "ngt";
3567 default: return "?";
3574 // Check that the given FPU format is usable, and signal a
3575 // ReservedInstruction exception if not.
3578 // check_fmt checks that the format is single or double.
3579 :function:::void:check_fmt:int fmt, instruction_word insn
3591 if ((fmt != fmt_single) && (fmt != fmt_double))
3592 SignalException (ReservedInstruction, insn);
3595 // check_fmt_p checks that the format is single, double, or paired single.
3596 :function:::void:check_fmt_p:int fmt, instruction_word insn
3606 /* None of these ISAs support Paired Single, so just fall back to
3607 the single/double check. */
3608 check_fmt (SD_, fmt, insn);
3611 :function:::void:check_fmt_p:int fmt, instruction_word insn
3615 if ((fmt != fmt_single) && (fmt != fmt_double)
3616 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3617 SignalException (ReservedInstruction, insn);
3623 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3624 // exception if not.
3627 :function:::void:check_fpu:
3639 if (! COP_Usable (1))
3640 SignalExceptionCoProcessorUnusable (1);
3646 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
3647 // or MIPS32. do_load cannot be used instead because it returns an
3648 // unsigned_word, which is limited to the size of the machine's registers.
3651 :function:::unsigned64:do_load_double:address_word base, address_word offset
3655 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3662 vaddr = loadstore_ea (SD_, base, offset);
3663 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3665 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
3666 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
3667 sim_core_unaligned_signal);
3669 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
3671 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
3673 v = (unsigned64)memval;
3674 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
3676 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
3682 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
3683 // or MIPS32. do_load cannot be used instead because it returns an
3684 // unsigned_word, which is limited to the size of the machine's registers.
3687 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
3691 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3697 vaddr = loadstore_ea (SD_, base, offset);
3698 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3700 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
3701 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
3702 sim_core_unaligned_signal);
3704 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
3706 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
3707 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
3709 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
3710 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
3715 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3716 "abs.%s<FMT> f<FD>, f<FS>"
3730 check_fmt_p (SD_, fmt, instruction_0);
3731 StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
3736 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3737 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3751 check_fmt_p (SD_, fmt, instruction_0);
3752 StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
3756 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
3757 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
3765 check_u64 (SD_, instruction_0);
3766 fs = ValueFPR (FS, fmt_ps);
3767 if ((GPR[RS] & 0x3) != 0)
3769 if ((GPR[RS] & 0x4) == 0)
3773 ft = ValueFPR (FT, fmt_ps);
3775 fd = PackPS (PSLower (fs), PSUpper (ft));
3777 fd = PackPS (PSLower (ft), PSUpper (fs));
3779 StoreFPR (FD, fmt_ps, fd);
3788 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3789 "bc1%s<TF>%s<ND> <OFFSET>"
3795 check_branch_bug ();
3796 TRACE_BRANCH_INPUT (PREVCOC1());
3797 if (PREVCOC1() == TF)
3799 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3800 TRACE_BRANCH_RESULT (dest);
3801 mark_branch_bug (dest);
3806 TRACE_BRANCH_RESULT (0);
3807 NULLIFY_NEXT_INSTRUCTION ();
3811 TRACE_BRANCH_RESULT (NIA);
3815 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3816 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3817 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3827 check_branch_bug ();
3828 if (GETFCC(CC) == TF)
3830 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3831 mark_branch_bug (dest);
3836 NULLIFY_NEXT_INSTRUCTION ();
3841 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3842 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3849 check_fmt_p (SD_, fmt, instruction_0);
3850 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
3851 TRACE_ALU_RESULT (ValueFCR (31));
3854 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3855 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3856 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3867 check_fmt_p (SD_, fmt, instruction_0);
3868 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
3869 TRACE_ALU_RESULT (ValueFCR (31));
3873 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3874 "ceil.l.%s<FMT> f<FD>, f<FS>"
3885 check_fmt (SD_, fmt, instruction_0);
3886 StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3891 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3892 "ceil.w.%s<FMT> f<FD>, f<FS>"
3905 check_fmt (SD_, fmt, instruction_0);
3906 StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3911 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
3919 PENDING_FILL (RT, EXTEND32 (FCR0));
3921 PENDING_FILL (RT, EXTEND32 (FCR31));
3925 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
3933 if (FS == 0 || FS == 31)
3935 unsigned_word fcr = ValueFCR (FS);
3936 TRACE_ALU_INPUT1 (fcr);
3940 TRACE_ALU_RESULT (GPR[RT]);
3943 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
3950 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
3952 unsigned_word fcr = ValueFCR (FS);
3953 TRACE_ALU_INPUT1 (fcr);
3957 TRACE_ALU_RESULT (GPR[RT]);
3960 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
3968 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
3972 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
3980 TRACE_ALU_INPUT1 (GPR[RT]);
3982 StoreFCR (FS, GPR[RT]);
3986 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
3993 TRACE_ALU_INPUT1 (GPR[RT]);
3994 if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
3995 StoreFCR (FS, GPR[RT]);
4001 // FIXME: Does not correctly differentiate between mips*
4003 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4004 "cvt.d.%s<FMT> f<FD>, f<FS>"
4018 if ((fmt == fmt_double) | 0)
4019 SignalException (ReservedInstruction, instruction_0);
4020 StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4025 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4026 "cvt.l.%s<FMT> f<FD>, f<FS>"
4037 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4038 SignalException (ReservedInstruction, instruction_0);
4039 StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4044 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4045 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4050 check_u64 (SD_, instruction_0);
4051 StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4052 ValueFPR (FT, fmt_single)));
4057 // FIXME: Does not correctly differentiate between mips*
4059 010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4060 "cvt.s.%s<FMT> f<FD>, f<FS>"
4074 if ((fmt == fmt_single) | 0)
4075 SignalException (ReservedInstruction, instruction_0);
4076 StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4081 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4082 "cvt.s.pl f<FD>, f<FS>"
4087 check_u64 (SD_, instruction_0);
4088 StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4092 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4093 "cvt.s.pu f<FD>, f<FS>"
4098 check_u64 (SD_, instruction_0);
4099 StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4103 010001,10,3.FMT!6,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4104 "cvt.w.%s<FMT> f<FD>, f<FS>"
4118 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4119 SignalException (ReservedInstruction, instruction_0);
4120 StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4125 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4126 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4140 check_fmt (SD_, fmt, instruction_0);
4141 StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4145 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4146 "dmfc1 r<RT>, f<FS>"
4151 check_u64 (SD_, instruction_0);
4152 if (SizeFGR () == 64)
4154 else if ((FS & 0x1) == 0)
4155 v = SET64HI (FGR[FS+1]) | FGR[FS];
4157 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4158 PENDING_FILL (RT, v);
4159 TRACE_ALU_RESULT (v);
4162 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4163 "dmfc1 r<RT>, f<FS>"
4172 check_u64 (SD_, instruction_0);
4173 if (SizeFGR () == 64)
4175 else if ((FS & 0x1) == 0)
4176 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4178 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4179 TRACE_ALU_RESULT (GPR[RT]);
4183 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4184 "dmtc1 r<RT>, f<FS>"
4189 check_u64 (SD_, instruction_0);
4190 if (SizeFGR () == 64)
4191 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4192 else if ((FS & 0x1) == 0)
4194 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4195 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4199 TRACE_FP_RESULT (GPR[RT]);
4202 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4203 "dmtc1 r<RT>, f<FS>"
4212 check_u64 (SD_, instruction_0);
4213 if (SizeFGR () == 64)
4214 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4215 else if ((FS & 0x1) == 0)
4216 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4222 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4223 "floor.l.%s<FMT> f<FD>, f<FS>"
4234 check_fmt (SD_, fmt, instruction_0);
4235 StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4240 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4241 "floor.w.%s<FMT> f<FD>, f<FS>"
4254 check_fmt (SD_, fmt, instruction_0);
4255 StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4260 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4261 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4266 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4270 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4271 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4281 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4285 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4286 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4293 check_u64 (SD_, instruction_0);
4294 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4299 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4300 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4313 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4317 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4318 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4325 check_u64 (SD_, instruction_0);
4326 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4331 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
4332 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4340 check_u64 (SD_, instruction_0);
4341 check_fmt_p (SD_, fmt, instruction_0);
4342 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4343 ValueFPR (FR, fmt), fmt));
4347 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4355 v = EXTEND32 (FGR[FS]);
4356 PENDING_FILL (RT, v);
4357 TRACE_ALU_RESULT (v);
4360 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4371 GPR[RT] = EXTEND32 (FGR[FS]);
4372 TRACE_ALU_RESULT (GPR[RT]);
4376 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4377 "mov.%s<FMT> f<FD>, f<FS>"
4391 check_fmt_p (SD_, fmt, instruction_0);
4392 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4398 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4399 "mov%s<TF> r<RD>, r<RS>, <CC>"
4407 if (GETFCC(CC) == TF)
4414 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4415 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4426 if (GETFCC(CC) == TF)
4427 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4429 StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
4434 fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4436 PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4438 StoreFPR (FD, fmt_ps, fd);
4443 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4444 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4453 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4455 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4462 // MOVT.fmt see MOVtf.fmt
4466 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4467 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4476 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4478 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4482 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
4483 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4491 check_u64 (SD_, instruction_0);
4492 check_fmt_p (SD_, fmt, instruction_0);
4493 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4494 ValueFPR (FR, fmt), fmt));
4498 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4505 if (SizeFGR () == 64)
4506 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4508 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4509 TRACE_FP_RESULT (GPR[RT]);
4512 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4523 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4527 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4528 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4542 check_fmt_p (SD_, fmt, instruction_0);
4543 StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4547 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4548 "neg.%s<FMT> f<FD>, f<FS>"
4562 check_fmt_p (SD_, fmt, instruction_0);
4563 StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4567 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
4568 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4576 check_u64 (SD_, instruction_0);
4577 check_fmt_p (SD_, fmt, instruction_0);
4578 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4579 ValueFPR (FR, fmt), fmt));
4583 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
4584 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4592 check_u64 (SD_, instruction_0);
4593 check_fmt_p (SD_, fmt, instruction_0);
4594 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4595 ValueFPR (FR, fmt), fmt));
4599 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
4600 "pll.ps f<FD>, f<FS>, f<FT>"
4605 check_u64 (SD_, instruction_0);
4606 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4607 PSLower (ValueFPR (FT, fmt_ps))));
4611 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
4612 "plu.ps f<FD>, f<FS>, f<FT>"
4617 check_u64 (SD_, instruction_0);
4618 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4619 PSUpper (ValueFPR (FT, fmt_ps))));
4623 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4624 "prefx <HINT>, r<INDEX>(r<BASE>)"
4630 address_word base = GPR[BASE];
4631 address_word index = GPR[INDEX];
4633 address_word vaddr = loadstore_ea (SD_, base, index);
4636 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4637 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4642 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
4643 "pul.ps f<FD>, f<FS>, f<FT>"
4648 check_u64 (SD_, instruction_0);
4649 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4650 PSLower (ValueFPR (FT, fmt_ps))));
4654 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
4655 "puu.ps f<FD>, f<FS>, f<FT>"
4660 check_u64 (SD_, instruction_0);
4661 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4662 PSUpper (ValueFPR (FT, fmt_ps))));
4666 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4667 "recip.%s<FMT> f<FD>, f<FS>"
4675 check_fmt (SD_, fmt, instruction_0);
4676 StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
4680 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4681 "round.l.%s<FMT> f<FD>, f<FS>"
4692 check_fmt (SD_, fmt, instruction_0);
4693 StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4698 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4699 "round.w.%s<FMT> f<FD>, f<FS>"
4712 check_fmt (SD_, fmt, instruction_0);
4713 StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4718 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4719 "rsqrt.%s<FMT> f<FD>, f<FS>"
4727 check_fmt (SD_, fmt, instruction_0);
4728 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
4732 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
4733 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4738 do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4742 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
4743 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4753 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4757 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4758 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4765 check_u64 (SD_, instruction_0);
4766 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4770 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4771 "sqrt.%s<FMT> f<FD>, f<FS>"
4784 check_fmt (SD_, fmt, instruction_0);
4785 StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
4789 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4790 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4804 check_fmt_p (SD_, fmt, instruction_0);
4805 StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4810 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4811 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4823 address_word base = GPR[BASE];
4824 address_word offset = EXTEND16 (OFFSET);
4827 address_word vaddr = loadstore_ea (SD_, base, offset);
4830 if ((vaddr & 3) != 0)
4832 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4836 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4839 uword64 memval1 = 0;
4840 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4841 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4842 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4844 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4845 byte = ((vaddr & mask) ^ bigendiancpu);
4846 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4847 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4854 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4855 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4862 address_word base = GPR[BASE];
4863 address_word index = GPR[INDEX];
4865 check_u64 (SD_, instruction_0);
4867 address_word vaddr = loadstore_ea (SD_, base, index);
4870 if ((vaddr & 3) != 0)
4872 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4876 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4878 unsigned64 memval = 0;
4879 unsigned64 memval1 = 0;
4880 unsigned64 mask = 0x7;
4882 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4883 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4884 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4886 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4894 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4895 "trunc.l.%s<FMT> f<FD>, f<FS>"
4906 check_fmt (SD_, fmt, instruction_0);
4907 StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4912 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4913 "trunc.w.%s<FMT> f<FD>, f<FS>"
4926 check_fmt (SD_, fmt, instruction_0);
4927 StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4933 // MIPS Architecture:
4935 // System Control Instruction Set (COP0)
4939 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4951 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4953 // stub needed for eCos as tx39 hardware bug workaround
4960 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4973 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4985 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4998 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4999 "cache <OP>, <OFFSET>(r<BASE>)"
5009 address_word base = GPR[BASE];
5010 address_word offset = EXTEND16 (OFFSET);
5012 address_word vaddr = loadstore_ea (SD_, base, offset);
5015 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5016 CacheOp(OP,vaddr,paddr,instruction_0);
5021 010000,1,0000000000000000000,111001:COP0:32::DI
5032 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5033 "dmfc0 r<RT>, r<RD>"
5039 check_u64 (SD_, instruction_0);
5040 DecodeCoproc (instruction_0);
5044 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5045 "dmtc0 r<RT>, r<RD>"
5051 check_u64 (SD_, instruction_0);
5052 DecodeCoproc (instruction_0);
5056 010000,1,0000000000000000000,111000:COP0:32::EI
5068 010000,1,0000000000000000000,011000:COP0:32::ERET
5078 if (SR & status_ERL)
5080 /* Oops, not yet available */
5081 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5093 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5094 "mfc0 r<RT>, r<RD> # <REGX>"
5106 TRACE_ALU_INPUT0 ();
5107 DecodeCoproc (instruction_0);
5108 TRACE_ALU_RESULT (GPR[RT]);
5111 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5112 "mtc0 r<RT>, r<RD> # <REGX>"
5124 DecodeCoproc (instruction_0);
5128 010000,1,0000000000000000000,010000:COP0:32::RFE
5139 DecodeCoproc (instruction_0);
5143 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5144 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5155 DecodeCoproc (instruction_0);
5160 010000,1,0000000000000000000,001000:COP0:32::TLBP
5173 010000,1,0000000000000000000,000001:COP0:32::TLBR
5186 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5199 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5213 :include:::mdmx.igen
5214 :include:::mips3d.igen