sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 :model:::vr4100:mips4100:
  47 // start-sanitize-vr4320
  48 :model:::vr4320:mips4320:
  49 // end-sanitize-vr4320
  50 // start-sanitize-cygnus
  51 :model:::vr5400:mips5400:
  52 :model:::mdmx:mdmx:
  53 // end-sanitize-cygnus
  54 :model:::vr5000:mips5000:
  55
  56
  57
  58 // Pseudo instructions known by IGEN
  59 :internal::::illegal:
  60 {
  61   SignalException (ReservedInstruction, 0);
  62 }
  63
  64
  65 // Pseudo instructions known by interp.c
  66 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  67 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  68 "rsvd <OP>"
  69 {
  70   SignalException (ReservedInstruction, instruction_0);
  71 }
  72
  73
  74
  75 // Helper:
  76 //
  77 // Simulate a 32 bit delayslot instruction
  78 //
  79
  80 :function:::address_word:delayslot32:address_word target
  81 {
  82   instruction_word delay_insn;
  83   sim_events_slip (SD, 1);
  84   DSPC = CIA;
  85   CIA = CIA + 4; /* NOTE not mips16 */
  86   STATE |= simDELAYSLOT;
  87   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  88   idecode_issue (CPU_, delay_insn, (CIA));
  89   STATE &= ~simDELAYSLOT;
  90   return target;
  91 }
  92
  93 :function:::address_word:nullify_next_insn32:
  94 {
  95   sim_events_slip (SD, 1);
  96   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  97   return CIA + 8;
  98 }
  99
 100 // start-sanitize-branchbug4011
 101 :function:::void:check_4011_branch_bug:
 102 {
 103   if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
 104     sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
 105                       itable[MY_INDEX].name,
 106                       (long) CIA,
 107                       (long) BRANCHBUG4011_LAST_CIA);
 108 }
 109
 110 :function:::void:mark_4011_branch_bug:address_word target
 111 {
 112   if (BRANCHBUG4011_OPTION)
 113     {
 114       BRANCHBUG4011_OPTION = 2;
 115       BRANCHBUG4011_LAST_TARGET = target;
 116       BRANCHBUG4011_LAST_CIA = CIA;
 117     }
 118 }
 119
 120 // end-sanitize-branchbug4011
 121 // Helper:
 122 //
 123 // Check that an access to a HI/LO register meets timing requirements
 124 //
 125 // The following requirements exist:
 126 //
 127 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 128 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 129 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 130 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 131 //
 132
 133 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 134 {
 135   if (history->mf.timestamp + 3 > time)
 136     {
 137       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 138                         itable[MY_INDEX].name,
 139                         new, (long) CIA,
 140                         (long) history->mf.cia);
 141       return 0;
 142     }
 143   return 1;
 144 }
 145
 146 :function:::int:check_mt_hilo:hilo_history *history
 147 *mipsI,mipsII,mipsIII,mipsIV:
 148 *vr5000:
 149 // start-sanitize-vr4320
 150 *vr4320:
 151 // end-sanitize-vr4320
 152 // start-sanitize-cygnus
 153 *vr5400:
 154 // end-sanitize-cygnus
 155 {
 156   signed64 time = sim_events_time (SD);
 157   int ok = check_mf_cycles (SD_, history, time, "MT");
 158   history->mt.timestamp = time;
 159   history->mt.cia = CIA;
 160   return ok;
 161 }
 162
 163 :function:::int:check_mt_hilo:hilo_history *history
 164 *r3900:
 165 // start-sanitize-tx19
 166 *tx19:
 167 // end-sanitize-tx19
 168 // start-sanitize-r5900
 169 *r5900:
 170 // end-sanitize-r5900
 171 {
 172   signed64 time = sim_events_time (SD);
 173   history->mt.timestamp = time;
 174   history->mt.cia = CIA;
 175   return 1;
 176 }
 177
 178
 179 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 180 *mipsI,mipsII,mipsIII,mipsIV:
 181 *vr5000:
 182 // start-sanitize-vr4320
 183 *vr4320:
 184 // end-sanitize-vr4320
 185 // start-sanitize-cygnus
 186 *vr5400:
 187 // end-sanitize-cygnus
 188 *r3900:
 189 // start-sanitize-tx19
 190 *tx19:
 191 // end-sanitize-tx19
 192 {
 193   signed64 time = sim_events_time (SD);
 194   int ok = 1;
 195   if (peer != NULL
 196       && peer->mt.timestamp > history->op.timestamp
 197       && history->mt.timestamp < history->op.timestamp
 198       && ! (history->mf.timestamp > history->op.timestamp
 199             && history->mf.timestamp < peer->mt.timestamp)
 200       && ! (peer->mf.timestamp > history->op.timestamp
 201             && peer->mf.timestamp < peer->mt.timestamp))
 202     {
 203       /* The peer has been written to since the last OP yet we have
 204          not */
 205       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 206                         itable[MY_INDEX].name,
 207                         (long) CIA,
 208                         (long) history->op.cia,
 209                         (long) peer->mt.cia);
 210       ok = 0;
 211     }
 212   history->mf.timestamp = time;
 213   history->mf.cia = CIA;
 214   return ok;
 215 }
 216
 217 // start-sanitize-r5900
 218 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
 219 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 220 // end-sanitize-r5900
 221 // start-sanitize-r5900
 222 *r5900:
 223 // end-sanitize-r5900
 224 // start-sanitize-r5900
 225 {
 226   /* FIXME: could record the fact that a stall occured if we want */
 227   signed64 time = sim_events_time (SD);
 228   history->mf.timestamp = time;
 229   history->mf.cia = CIA;
 230   return 1;
 231 }
 232 // end-sanitize-r5900
 233
 234
 235 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 236 *mipsI,mipsII,mipsIII,mipsIV:
 237 *vr5000:
 238 // start-sanitize-vr4320
 239 *vr4320:
 240 // end-sanitize-vr4320
 241 // start-sanitize-cygnus
 242 *vr5400:
 243 // end-sanitize-cygnus
 244 {
 245   signed64 time = sim_events_time (SD);
 246   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 247             && check_mf_cycles (SD_, lo, time, "OP"));
 248   hi->op.timestamp = time;
 249   lo->op.timestamp = time;
 250   hi->op.cia = CIA;
 251   lo->op.cia = CIA;
 252   return ok;
 253 }
 254
 255 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 256 // a mf{hi,lo}
 257 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 258 *r3900:
 259 // start-sanitize-tx19
 260 *tx19:
 261 // end-sanitize-tx19
 262 // start-sanitize-r5900
 263 *r5900:
 264 // end-sanitize-r5900
 265 {
 266   /* FIXME: could record the fact that a stall occured if we want */
 267   signed64 time = sim_events_time (SD);
 268   hi->op.timestamp = time;
 269   lo->op.timestamp = time;
 270   hi->op.cia = CIA;
 271   lo->op.cia = CIA;
 272   return 1;
 273 }
 274
 275
 276 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 277 *mipsI,mipsII,mipsIII,mipsIV:
 278 *vr5000:
 279 // start-sanitize-vr4320
 280 *vr4320:
 281 // end-sanitize-vr4320
 282 // start-sanitize-cygnus
 283 *vr5400:
 284 // end-sanitize-cygnus
 285 *r3900:
 286 // start-sanitize-tx19
 287 *tx19:
 288 // end-sanitize-tx19
 289 {
 290   signed64 time = sim_events_time (SD);
 291   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 292             && check_mf_cycles (SD_, lo, time, "OP"));
 293   hi->op.timestamp = time;
 294   lo->op.timestamp = time;
 295   hi->op.cia = CIA;
 296   lo->op.cia = CIA;
 297   return ok;
 298 }
 299
 300
 301 // start-sanitize-r5900
 302 // The r5900 div et.al insns _can_ be exectuted immediatly after
 303 // a mf{hi,lo}
 304 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 305 // end-sanitize-r5900
 306 // start-sanitize-r5900
 307 *r5900:
 308 // end-sanitize-r5900
 309 // start-sanitize-r5900
 310 {
 311   /* FIXME: could record the fact that a stall occured if we want */
 312   signed64 time = sim_events_time (SD);
 313   hi->op.timestamp = time;
 314   lo->op.timestamp = time;
 315   hi->op.cia = CIA;
 316   lo->op.cia = CIA;
 317   return 1;
 318 }
 319 // end-sanitize-r5900
 320
 321
 322
 323 //
 324 // Mips Architecture:
 325 //
 326 //        CPU Instruction Set (mipsI - mipsIV)
 327 //
 328
 329
 330
 331 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 332 "add r<RD>, r<RS>, r<RT>"
 333 *mipsI,mipsII,mipsIII,mipsIV:
 334 *vr5000:
 335 // start-sanitize-vr4320
 336 *vr4320:
 337 // end-sanitize-vr4320
 338 // start-sanitize-cygnus
 339 *vr5400:
 340 // end-sanitize-cygnus
 341 // start-sanitize-r5900
 342 *r5900:
 343 // end-sanitize-r5900
 344 *r3900:
 345 // start-sanitize-tx19
 346 *tx19:
 347 // end-sanitize-tx19
 348 {
 349   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 350   {
 351     ALU32_BEGIN (GPR[RS]);
 352     ALU32_ADD (GPR[RT]);
 353     ALU32_END (GPR[RD]);
 354   }
 355   TRACE_ALU_RESULT (GPR[RD]);
 356 }
 357
 358
 359
 360 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 361 "addi r<RT>, r<RS>, IMMEDIATE"
 362 *mipsI,mipsII,mipsIII,mipsIV:
 363 *vr5000:
 364 // start-sanitize-vr4320
 365 *vr4320:
 366 // end-sanitize-vr4320
 367 // start-sanitize-cygnus
 368 *vr5400:
 369 // end-sanitize-cygnus
 370 // start-sanitize-r5900
 371 *r5900:
 372 // end-sanitize-r5900
 373 *r3900:
 374 // start-sanitize-tx19
 375 *tx19:
 376 // end-sanitize-tx19
 377 {
 378   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 379   {
 380     ALU32_BEGIN (GPR[RS]);
 381     ALU32_ADD (EXTEND16 (IMMEDIATE));
 382     ALU32_END (GPR[RT]);
 383   }
 384   TRACE_ALU_RESULT (GPR[RT]);
 385 }
 386
 387
 388
 389 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 390 {
 391   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 392   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 393   TRACE_ALU_RESULT (GPR[rt]);
 394 }
 395
 396 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 397 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 398 *mipsI,mipsII,mipsIII,mipsIV:
 399 *vr5000:
 400 // start-sanitize-vr4320
 401 *vr4320:
 402 // end-sanitize-vr4320
 403 // start-sanitize-cygnus
 404 *vr5400:
 405 // end-sanitize-cygnus
 406 // start-sanitize-r5900
 407 *r5900:
 408 // end-sanitize-r5900
 409 *r3900:
 410 // start-sanitize-tx19
 411 *tx19:
 412 // end-sanitize-tx19
 413 {
 414   do_addiu (SD_, RS, RT, IMMEDIATE);
 415 }
 416
 417
 418
 419 :function:::void:do_addu:int rs, int rt, int rd
 420 {
 421   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 422   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 423   TRACE_ALU_RESULT (GPR[rd]);
 424 }
 425
 426 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 427 "addu r<RD>, r<RS>, r<RT>"
 428 *mipsI,mipsII,mipsIII,mipsIV:
 429 *vr5000:
 430 // start-sanitize-vr4320
 431 *vr4320:
 432 // end-sanitize-vr4320
 433 // start-sanitize-cygnus
 434 *vr5400:
 435 // end-sanitize-cygnus
 436 // start-sanitize-r5900
 437 *r5900:
 438 // end-sanitize-r5900
 439 *r3900:
 440 // start-sanitize-tx19
 441 *tx19:
 442 // end-sanitize-tx19
 443 {
 444   do_addu (SD_, RS, RT, RD);
 445 }
 446
 447
 448
 449 :function:::void:do_and:int rs, int rt, int rd
 450 {
 451   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 452   GPR[rd] = GPR[rs] & GPR[rt];
 453   TRACE_ALU_RESULT (GPR[rd]);
 454 }
 455
 456 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 457 "and r<RD>, r<RS>, r<RT>"
 458 *mipsI,mipsII,mipsIII,mipsIV:
 459 *vr5000:
 460 // start-sanitize-vr4320
 461 *vr4320:
 462 // end-sanitize-vr4320
 463 // start-sanitize-cygnus
 464 *vr5400:
 465 // end-sanitize-cygnus
 466 // start-sanitize-r5900
 467 *r5900:
 468 // end-sanitize-r5900
 469 *r3900:
 470 // start-sanitize-tx19
 471 *tx19:
 472 // end-sanitize-tx19
 473 {
 474   do_and (SD_, RS, RT, RD);
 475 }
 476
 477
 478
 479 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 480 "and r<RT>, r<RS>, <IMMEDIATE>"
 481 *mipsI,mipsII,mipsIII,mipsIV:
 482 *vr5000:
 483 // start-sanitize-vr4320
 484 *vr4320:
 485 // end-sanitize-vr4320
 486 // start-sanitize-cygnus
 487 *vr5400:
 488 // end-sanitize-cygnus
 489 // start-sanitize-r5900
 490 *r5900:
 491 // end-sanitize-r5900
 492 *r3900:
 493 // start-sanitize-tx19
 494 *tx19:
 495 // end-sanitize-tx19
 496 {
 497   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 498   GPR[RT] = GPR[RS] & IMMEDIATE;
 499   TRACE_ALU_RESULT (GPR[RT]);
 500 }
 501
 502
 503
 504 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 505 "beq r<RS>, r<RT>, <OFFSET>"
 506 *mipsI,mipsII,mipsIII,mipsIV:
 507 *vr5000:
 508 // start-sanitize-vr4320
 509 *vr4320:
 510 // end-sanitize-vr4320
 511 // start-sanitize-cygnus
 512 *vr5400:
 513 // end-sanitize-cygnus
 514 // start-sanitize-r5900
 515 *r5900:
 516 // end-sanitize-r5900
 517 *r3900:
 518 // start-sanitize-tx19
 519 *tx19:
 520 // end-sanitize-tx19
 521 {
 522   address_word offset = EXTEND16 (OFFSET) << 2;
 523   check_branch_bug ();
 524   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 525     {
 526       mark_branch_bug (NIA+offset);
 527       DELAY_SLOT (NIA + offset);
 528     }
 529 }
 530
 531
 532
 533 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 534 "beql r<RS>, r<RT>, <OFFSET>"
 535 *mipsII:
 536 *mipsIII:
 537 *mipsIV:
 538 *vr5000:
 539 // start-sanitize-vr4320
 540 *vr4320:
 541 // end-sanitize-vr4320
 542 // start-sanitize-cygnus
 543 *vr5400:
 544 // end-sanitize-cygnus
 545 // start-sanitize-r5900
 546 *r5900:
 547 // end-sanitize-r5900
 548 *r3900:
 549 // start-sanitize-tx19
 550 *tx19:
 551 // end-sanitize-tx19
 552 {
 553   address_word offset = EXTEND16 (OFFSET) << 2;
 554   check_branch_bug ();
 555   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 556     {
 557       mark_branch_bug (NIA+offset);
 558       DELAY_SLOT (NIA + offset);
 559     }
 560   else
 561     NULLIFY_NEXT_INSTRUCTION ();
 562 }
 563
 564
 565
 566 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 567 "bgez r<RS>, <OFFSET>"
 568 *mipsI,mipsII,mipsIII,mipsIV:
 569 *vr5000:
 570 // start-sanitize-vr4320
 571 *vr4320:
 572 // end-sanitize-vr4320
 573 // start-sanitize-cygnus
 574 *vr5400:
 575 // end-sanitize-cygnus
 576 // start-sanitize-r5900
 577 *r5900:
 578 // end-sanitize-r5900
 579 *r3900:
 580 // start-sanitize-tx19
 581 *tx19:
 582 // end-sanitize-tx19
 583 {
 584   address_word offset = EXTEND16 (OFFSET) << 2;
 585   check_branch_bug ();
 586   if ((signed_word) GPR[RS] >= 0)
 587     {
 588       mark_branch_bug (NIA+offset);
 589       DELAY_SLOT (NIA + offset);
 590     }
 591 }
 592
 593
 594
 595 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 596 "bgezal r<RS>, <OFFSET>"
 597 *mipsI,mipsII,mipsIII,mipsIV:
 598 *vr5000:
 599 // start-sanitize-vr4320
 600 *vr4320:
 601 // end-sanitize-vr4320
 602 // start-sanitize-cygnus
 603 *vr5400:
 604 // end-sanitize-cygnus
 605 // start-sanitize-r5900
 606 *r5900:
 607 // end-sanitize-r5900
 608 *r3900:
 609 // start-sanitize-tx19
 610 *tx19:
 611 // end-sanitize-tx19
 612 {
 613   address_word offset = EXTEND16 (OFFSET) << 2;
 614   check_branch_bug ();
 615   RA = (CIA + 8);
 616   if ((signed_word) GPR[RS] >= 0)
 617     {
 618       mark_branch_bug (NIA+offset);
 619       DELAY_SLOT (NIA + offset);
 620     }
 621 }
 622
 623
 624
 625 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 626 "bgezall r<RS>, <OFFSET>"
 627 *mipsII:
 628 *mipsIII:
 629 *mipsIV:
 630 *vr5000:
 631 // start-sanitize-vr4320
 632 *vr4320:
 633 // end-sanitize-vr4320
 634 // start-sanitize-cygnus
 635 *vr5400:
 636 // end-sanitize-cygnus
 637 // start-sanitize-r5900
 638 *r5900:
 639 // end-sanitize-r5900
 640 *r3900:
 641 // start-sanitize-tx19
 642 *tx19:
 643 // end-sanitize-tx19
 644 {
 645   address_word offset = EXTEND16 (OFFSET) << 2;
 646   check_branch_bug ();
 647   RA = (CIA + 8);
 648   /* NOTE: The branch occurs AFTER the next instruction has been
 649      executed */
 650   if ((signed_word) GPR[RS] >= 0)
 651     {
 652       mark_branch_bug (NIA+offset);
 653       DELAY_SLOT (NIA + offset);
 654     }
 655   else
 656     NULLIFY_NEXT_INSTRUCTION ();
 657 }
 658
 659
 660
 661 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 662 "bgezl r<RS>, <OFFSET>"
 663 *mipsII:
 664 *mipsIII:
 665 *mipsIV:
 666 *vr5000:
 667 // start-sanitize-vr4320
 668 *vr4320:
 669 // end-sanitize-vr4320
 670 // start-sanitize-cygnus
 671 *vr5400:
 672 // end-sanitize-cygnus
 673 // start-sanitize-r5900
 674 *r5900:
 675 // end-sanitize-r5900
 676 *r3900:
 677 // start-sanitize-tx19
 678 *tx19:
 679 // end-sanitize-tx19
 680 {
 681   address_word offset = EXTEND16 (OFFSET) << 2;
 682   check_branch_bug ();
 683   if ((signed_word) GPR[RS] >= 0)
 684     {
 685       mark_branch_bug (NIA+offset);
 686       DELAY_SLOT (NIA + offset);
 687     }
 688   else
 689     NULLIFY_NEXT_INSTRUCTION ();
 690 }
 691
 692
 693
 694 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 695 "bgtz r<RS>, <OFFSET>"
 696 *mipsI,mipsII,mipsIII,mipsIV:
 697 *vr5000:
 698 // start-sanitize-vr4320
 699 *vr4320:
 700 // end-sanitize-vr4320
 701 // start-sanitize-cygnus
 702 *vr5400:
 703 // end-sanitize-cygnus
 704 // start-sanitize-r5900
 705 *r5900:
 706 // end-sanitize-r5900
 707 *r3900:
 708 // start-sanitize-tx19
 709 *tx19:
 710 // end-sanitize-tx19
 711 {
 712   address_word offset = EXTEND16 (OFFSET) << 2;
 713   check_branch_bug ();
 714   if ((signed_word) GPR[RS] > 0)
 715     {
 716       mark_branch_bug (NIA+offset);
 717       DELAY_SLOT (NIA + offset);
 718     }
 719 }
 720
 721
 722
 723 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 724 "bgtzl r<RS>, <OFFSET>"
 725 *mipsII:
 726 *mipsIII:
 727 *mipsIV:
 728 *vr5000:
 729 // start-sanitize-vr4320
 730 *vr4320:
 731 // end-sanitize-vr4320
 732 // start-sanitize-cygnus
 733 *vr5400:
 734 // end-sanitize-cygnus
 735 // start-sanitize-r5900
 736 *r5900:
 737 // end-sanitize-r5900
 738 *r3900:
 739 // start-sanitize-tx19
 740 *tx19:
 741 // end-sanitize-tx19
 742 {
 743   address_word offset = EXTEND16 (OFFSET) << 2;
 744   check_branch_bug ();
 745   /* NOTE: The branch occurs AFTER the next instruction has been
 746      executed */
 747   if ((signed_word) GPR[RS] > 0)
 748     {
 749       mark_branch_bug (NIA+offset);
 750       DELAY_SLOT (NIA + offset);
 751     }
 752   else
 753     NULLIFY_NEXT_INSTRUCTION ();
 754 }
 755
 756
 757
 758 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 759 "blez r<RS>, <OFFSET>"
 760 *mipsI,mipsII,mipsIII,mipsIV:
 761 *vr5000:
 762 // start-sanitize-vr4320
 763 *vr4320:
 764 // end-sanitize-vr4320
 765 // start-sanitize-cygnus
 766 *vr5400:
 767 // end-sanitize-cygnus
 768 // start-sanitize-r5900
 769 *r5900:
 770 // end-sanitize-r5900
 771 *r3900:
 772 // start-sanitize-tx19
 773 *tx19:
 774 // end-sanitize-tx19
 775 {
 776   address_word offset = EXTEND16 (OFFSET) << 2;
 777   check_branch_bug ();
 778   /* NOTE: The branch occurs AFTER the next instruction has been
 779      executed */
 780   if ((signed_word) GPR[RS] <= 0)
 781     {
 782       mark_branch_bug (NIA+offset);
 783       DELAY_SLOT (NIA + offset);
 784     }
 785 }
 786
 787
 788
 789 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 790 "bgezl r<RS>, <OFFSET>"
 791 *mipsII:
 792 *mipsIII:
 793 *mipsIV:
 794 *vr5000:
 795 // start-sanitize-vr4320
 796 *vr4320:
 797 // end-sanitize-vr4320
 798 // start-sanitize-cygnus
 799 *vr5400:
 800 // end-sanitize-cygnus
 801 // start-sanitize-r5900
 802 *r5900:
 803 // end-sanitize-r5900
 804 *r3900:
 805 // start-sanitize-tx19
 806 *tx19:
 807 // end-sanitize-tx19
 808 {
 809   address_word offset = EXTEND16 (OFFSET) << 2;
 810   check_branch_bug ();
 811   if ((signed_word) GPR[RS] <= 0)
 812     {
 813       mark_branch_bug (NIA+offset);
 814       DELAY_SLOT (NIA + offset);
 815     }
 816   else
 817     NULLIFY_NEXT_INSTRUCTION ();
 818 }
 819
 820
 821
 822 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 823 "bltz r<RS>, <OFFSET>"
 824 *mipsI,mipsII,mipsIII,mipsIV:
 825 *vr5000:
 826 // start-sanitize-vr4320
 827 *vr4320:
 828 // end-sanitize-vr4320
 829 // start-sanitize-cygnus
 830 *vr5400:
 831 // end-sanitize-cygnus
 832 // start-sanitize-r5900
 833 *r5900:
 834 // end-sanitize-r5900
 835 *r3900:
 836 // start-sanitize-tx19
 837 *tx19:
 838 // end-sanitize-tx19
 839 {
 840   address_word offset = EXTEND16 (OFFSET) << 2;
 841   check_branch_bug ();
 842   if ((signed_word) GPR[RS] < 0)
 843     {
 844       mark_branch_bug (NIA+offset);
 845       DELAY_SLOT (NIA + offset);
 846     }
 847 }
 848
 849
 850
 851 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 852 "bltzal r<RS>, <OFFSET>"
 853 *mipsI,mipsII,mipsIII,mipsIV:
 854 *vr5000:
 855 // start-sanitize-vr4320
 856 *vr4320:
 857 // end-sanitize-vr4320
 858 // start-sanitize-cygnus
 859 *vr5400:
 860 // end-sanitize-cygnus
 861 // start-sanitize-r5900
 862 *r5900:
 863 // end-sanitize-r5900
 864 *r3900:
 865 // start-sanitize-tx19
 866 *tx19:
 867 // end-sanitize-tx19
 868 {
 869   address_word offset = EXTEND16 (OFFSET) << 2;
 870   check_branch_bug ();
 871   RA = (CIA + 8);
 872   /* NOTE: The branch occurs AFTER the next instruction has been
 873      executed */
 874   if ((signed_word) GPR[RS] < 0)
 875     {
 876       mark_branch_bug (NIA+offset);
 877       DELAY_SLOT (NIA + offset);
 878     }
 879 }
 880
 881
 882
 883 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 884 "bltzall r<RS>, <OFFSET>"
 885 *mipsII:
 886 *mipsIII:
 887 *mipsIV:
 888 *vr5000:
 889 // start-sanitize-vr4320
 890 *vr4320:
 891 // end-sanitize-vr4320
 892 // start-sanitize-cygnus
 893 *vr5400:
 894 // end-sanitize-cygnus
 895 // start-sanitize-r5900
 896 *r5900:
 897 // end-sanitize-r5900
 898 *r3900:
 899 // start-sanitize-tx19
 900 *tx19:
 901 // end-sanitize-tx19
 902 {
 903   address_word offset = EXTEND16 (OFFSET) << 2;
 904   check_branch_bug ();
 905   RA = (CIA + 8);
 906   if ((signed_word) GPR[RS] < 0)
 907     {
 908       mark_branch_bug (NIA+offset);
 909       DELAY_SLOT (NIA + offset);
 910     }
 911   else
 912     NULLIFY_NEXT_INSTRUCTION ();
 913 }
 914
 915
 916
 917 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 918 "bltzl r<RS>, <OFFSET>"
 919 *mipsII:
 920 *mipsIII:
 921 *mipsIV:
 922 *vr5000:
 923 // start-sanitize-vr4320
 924 *vr4320:
 925 // end-sanitize-vr4320
 926 // start-sanitize-cygnus
 927 *vr5400:
 928 // end-sanitize-cygnus
 929 // start-sanitize-r5900
 930 *r5900:
 931 // end-sanitize-r5900
 932 *r3900:
 933 // start-sanitize-tx19
 934 *tx19:
 935 // end-sanitize-tx19
 936 {
 937   address_word offset = EXTEND16 (OFFSET) << 2;
 938   check_branch_bug ();
 939   /* NOTE: The branch occurs AFTER the next instruction has been
 940      executed */
 941   if ((signed_word) GPR[RS] < 0)
 942     {
 943       mark_branch_bug (NIA+offset);
 944       DELAY_SLOT (NIA + offset);
 945     }
 946   else
 947     NULLIFY_NEXT_INSTRUCTION ();
 948 }
 949
 950
 951
 952 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 953 "bne r<RS>, r<RT>, <OFFSET>"
 954 *mipsI,mipsII,mipsIII,mipsIV:
 955 *vr5000:
 956 // start-sanitize-vr4320
 957 *vr4320:
 958 // end-sanitize-vr4320
 959 // start-sanitize-cygnus
 960 *vr5400:
 961 // end-sanitize-cygnus
 962 // start-sanitize-r5900
 963 *r5900:
 964 // end-sanitize-r5900
 965 *r3900:
 966 // start-sanitize-tx19
 967 *tx19:
 968 // end-sanitize-tx19
 969 {
 970   address_word offset = EXTEND16 (OFFSET) << 2;
 971   check_branch_bug ();
 972   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 973     {
 974       mark_branch_bug (NIA+offset);
 975       DELAY_SLOT (NIA + offset);
 976     }
 977 }
 978
 979
 980
 981 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 982 "bnel r<RS>, r<RT>, <OFFSET>"
 983 *mipsII:
 984 *mipsIII:
 985 *mipsIV:
 986 *vr5000:
 987 // start-sanitize-vr4320
 988 *vr4320:
 989 // end-sanitize-vr4320
 990 // start-sanitize-cygnus
 991 *vr5400:
 992 // end-sanitize-cygnus
 993 // start-sanitize-r5900
 994 *r5900:
 995 // end-sanitize-r5900
 996 *r3900:
 997 // start-sanitize-tx19
 998 *tx19:
 999 // end-sanitize-tx19
1000 {
1001   address_word offset = EXTEND16 (OFFSET) << 2;
1002   check_branch_bug ();
1003   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1004     {
1005       mark_branch_bug (NIA+offset);
1006       DELAY_SLOT (NIA + offset);
1007     }
1008   else
1009     NULLIFY_NEXT_INSTRUCTION ();
1010 }
1011
1012
1013
1014 000000,20.CODE,001101:SPECIAL:32::BREAK
1015 "break"
1016 *mipsI,mipsII,mipsIII,mipsIV:
1017 *vr5000:
1018 // start-sanitize-vr4320
1019 *vr4320:
1020 // end-sanitize-vr4320
1021 // start-sanitize-cygnus
1022 *vr5400:
1023 // end-sanitize-cygnus
1024 // start-sanitize-r5900
1025 *r5900:
1026 // end-sanitize-r5900
1027 *r3900:
1028 // start-sanitize-tx19
1029 *tx19:
1030 // end-sanitize-tx19
1031 {
1032   /* Check for some break instruction which are reserved for use by the simulator.  */
1033   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1034   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1035       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1036     {
1037       sim_engine_halt (SD, CPU, NULL, cia,
1038                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1039     }
1040   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1041            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1042     {
1043       if (STATE & simDELAYSLOT)
1044         PC = cia - 4; /* reference the branch instruction */
1045       else
1046         PC = cia;
1047       sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1048     }
1049 // start-sanitize-sky
1050   else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
1051     {
1052       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
1053     }
1054   else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
1055     {
1056       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
1057     }
1058 // end-sanitize-sky
1059
1060   /* If we get this far, we're not an instruction reserved by the sim.  Raise
1061      the exception. */
1062   SignalException(BreakPoint, instruction_0);
1063 }
1064
1065
1066
1067
1068
1069
1070 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1071 "dadd r<RD>, r<RS>, r<RT>"
1072 *mipsIII:
1073 *mipsIV:
1074 *vr5000:
1075 // start-sanitize-vr4320
1076 *vr4320:
1077 // end-sanitize-vr4320
1078 // start-sanitize-cygnus
1079 *vr5400:
1080 // end-sanitize-cygnus
1081 // start-sanitize-r5900
1082 *r5900:
1083 // end-sanitize-r5900
1084 // start-sanitize-tx19
1085 *tx19:
1086 // end-sanitize-tx19
1087 {
1088   /* this check's for overflow */
1089   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1090   {
1091     ALU64_BEGIN (GPR[RS]);
1092     ALU64_ADD (GPR[RT]);
1093     ALU64_END (GPR[RD]);
1094   }
1095   TRACE_ALU_RESULT (GPR[RD]);
1096 }
1097
1098
1099
1100 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1101 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1102 *mipsIII:
1103 *mipsIV:
1104 *vr5000:
1105 // start-sanitize-vr4320
1106 *vr4320:
1107 // end-sanitize-vr4320
1108 // start-sanitize-cygnus
1109 *vr5400:
1110 // end-sanitize-cygnus
1111 // start-sanitize-r5900
1112 *r5900:
1113 // end-sanitize-r5900
1114 // start-sanitize-tx19
1115 *tx19:
1116 // end-sanitize-tx19
1117 {
1118   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1119   {
1120     ALU64_BEGIN (GPR[RS]);
1121     ALU64_ADD (EXTEND16 (IMMEDIATE));
1122     ALU64_END (GPR[RT]);
1123   }
1124   TRACE_ALU_RESULT (GPR[RT]);
1125 }
1126
1127
1128
1129 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1130 {
1131   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1132   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1133   TRACE_ALU_RESULT (GPR[rt]);
1134 }
1135
1136 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1137 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1138 *mipsIII:
1139 *mipsIV:
1140 *vr5000:
1141 // start-sanitize-vr4320
1142 *vr4320:
1143 // end-sanitize-vr4320
1144 // start-sanitize-cygnus
1145 *vr5400:
1146 // end-sanitize-cygnus
1147 // start-sanitize-r5900
1148 *r5900:
1149 // end-sanitize-r5900
1150 // start-sanitize-tx19
1151 *tx19:
1152 // end-sanitize-tx19
1153 {
1154   do_daddiu (SD_, RS, RT, IMMEDIATE);
1155 }
1156
1157
1158
1159 :function:::void:do_daddu:int rs, int rt, int rd
1160 {
1161   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1162   GPR[rd] = GPR[rs] + GPR[rt];
1163   TRACE_ALU_RESULT (GPR[rd]);
1164 }
1165
1166 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1167 "daddu r<RD>, r<RS>, r<RT>"
1168 *mipsIII:
1169 *mipsIV:
1170 *vr5000:
1171 // start-sanitize-vr4320
1172 *vr4320:
1173 // end-sanitize-vr4320
1174 // start-sanitize-cygnus
1175 *vr5400:
1176 // end-sanitize-cygnus
1177 // start-sanitize-r5900
1178 *r5900:
1179 // end-sanitize-r5900
1180 // start-sanitize-tx19
1181 *tx19:
1182 // end-sanitize-tx19
1183 {
1184   do_daddu (SD_, RS, RT, RD);
1185 }
1186
1187
1188
1189 :function:64::void:do_ddiv:int rs, int rt
1190 {
1191   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1192   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1193   {
1194     signed64 n = GPR[rs];
1195     signed64 d = GPR[rt];
1196     if (d == 0)
1197       {
1198         LO = SIGNED64 (0x8000000000000000);
1199         HI = 0;
1200       }
1201     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1202       {
1203         LO = SIGNED64 (0x8000000000000000);
1204         HI = 0;
1205       }
1206     else
1207       {
1208         LO = (n / d);
1209         HI = (n % d);
1210       }
1211   }
1212   TRACE_ALU_RESULT2 (HI, LO);
1213 }
1214
1215 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1216 "ddiv r<RS>, r<RT>"
1217 *mipsIII:
1218 *mipsIV:
1219 *vr5000:
1220 // start-sanitize-vr4320
1221 *vr4320:
1222 // end-sanitize-vr4320
1223 // start-sanitize-cygnus
1224 *vr5400:
1225 // end-sanitize-cygnus
1226 // start-sanitize-r5900
1227 *r5900:
1228 // end-sanitize-r5900
1229 // start-sanitize-tx19
1230 *tx19:
1231 // end-sanitize-tx19
1232 {
1233   do_ddiv (SD_, RS, RT);
1234 }
1235
1236
1237
1238 :function:64::void:do_ddivu:int rs, int rt
1239 {
1240   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1241   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1242   {
1243     unsigned64 n = GPR[rs];
1244     unsigned64 d = GPR[rt];
1245     if (d == 0)
1246       {
1247         LO = SIGNED64 (0x8000000000000000);
1248         HI = 0;
1249       }
1250     else
1251       {
1252         LO = (n / d);
1253         HI = (n % d);
1254       }
1255   }
1256   TRACE_ALU_RESULT2 (HI, LO);
1257 }
1258
1259 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1260 "ddivu r<RS>, r<RT>"
1261 *mipsIII:
1262 *mipsIV:
1263 *vr5000:
1264 // start-sanitize-vr4320
1265 *vr4320:
1266 // end-sanitize-vr4320
1267 // start-sanitize-cygnus
1268 *vr5400:
1269 // end-sanitize-cygnus
1270 // start-sanitize-tx19
1271 *tx19:
1272 // end-sanitize-tx19
1273 {
1274   do_ddivu (SD_, RS, RT);
1275 }
1276
1277
1278
1279 :function:::void:do_div:int rs, int rt
1280 {
1281   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1282   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1283   {
1284     signed32 n = GPR[rs];
1285     signed32 d = GPR[rt];
1286     if (d == 0)
1287       {
1288         LO = EXTEND32 (0x80000000);
1289         HI = EXTEND32 (0);
1290       }
1291     else if (n == SIGNED32 (0x80000000) && d == -1)
1292       {
1293         LO = EXTEND32 (0x80000000);
1294         HI = EXTEND32 (0);
1295       }
1296     else
1297       {
1298         LO = EXTEND32 (n / d);
1299         HI = EXTEND32 (n % d);
1300       }
1301   }
1302   TRACE_ALU_RESULT2 (HI, LO);
1303 }
1304
1305 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1306 "div r<RS>, r<RT>"
1307 *mipsI,mipsII,mipsIII,mipsIV:
1308 *vr5000:
1309 // start-sanitize-vr4320
1310 *vr4320:
1311 // end-sanitize-vr4320
1312 // start-sanitize-cygnus
1313 *vr5400:
1314 // end-sanitize-cygnus
1315 // start-sanitize-r5900
1316 *r5900:
1317 // end-sanitize-r5900
1318 *r3900:
1319 // start-sanitize-tx19
1320 *tx19:
1321 // end-sanitize-tx19
1322 {
1323   do_div (SD_, RS, RT);
1324 }
1325
1326
1327
1328 :function:::void:do_divu:int rs, int rt
1329 {
1330   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1331   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1332   {
1333     unsigned32 n = GPR[rs];
1334     unsigned32 d = GPR[rt];
1335     if (d == 0)
1336       {
1337         LO = EXTEND32 (0x80000000);
1338         HI = EXTEND32 (0);
1339       }
1340    else
1341      {
1342        LO = EXTEND32 (n / d);
1343        HI = EXTEND32 (n % d);
1344      }
1345   }
1346   TRACE_ALU_RESULT2 (HI, LO);
1347 }
1348
1349 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1350 "divu r<RS>, r<RT>"
1351 *mipsI,mipsII,mipsIII,mipsIV:
1352 *vr5000:
1353 // start-sanitize-vr4320
1354 *vr4320:
1355 // end-sanitize-vr4320
1356 // start-sanitize-cygnus
1357 *vr5400:
1358 // end-sanitize-cygnus
1359 // start-sanitize-r5900
1360 *r5900:
1361 // end-sanitize-r5900
1362 *r3900:
1363 // start-sanitize-tx19
1364 *tx19:
1365 // end-sanitize-tx19
1366 {
1367   do_divu (SD_, RS, RT);
1368 }
1369
1370
1371
1372 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1373 {
1374   unsigned64 lo;
1375   unsigned64 hi;
1376   unsigned64 m00;
1377   unsigned64 m01;
1378   unsigned64 m10;
1379   unsigned64 m11;
1380   unsigned64 mid;
1381   int sign;
1382   unsigned64 op1 = GPR[rs];
1383   unsigned64 op2 = GPR[rt];
1384   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1385   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1386   /* make signed multiply unsigned */
1387   sign = 0;
1388   if (signed_p)
1389     {
1390       if (op1 < 0)
1391         {
1392           op1 = - op1;
1393           ++sign;
1394         }
1395       if (op2 < 0)
1396         {
1397           op2 = - op2;
1398           ++sign;
1399         }
1400     }
1401   /* multuply out the 4 sub products */
1402   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1403   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1404   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1405   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1406   /* add the products */
1407   mid = ((unsigned64) VH4_8 (m00)
1408          + (unsigned64) VL4_8 (m10)
1409          + (unsigned64) VL4_8 (m01));
1410   lo = U8_4 (mid, m00);
1411   hi = (m11
1412         + (unsigned64) VH4_8 (mid)
1413         + (unsigned64) VH4_8 (m01)
1414         + (unsigned64) VH4_8 (m10));
1415   /* fix the sign */
1416   if (sign & 1)
1417     {
1418       lo = -lo;
1419       if (lo == 0)
1420         hi = -hi;
1421       else
1422         hi = -hi - 1;
1423     }
1424   /* save the result HI/LO (and a gpr) */
1425   LO = lo;
1426   HI = hi;
1427   if (rd != 0)
1428     GPR[rd] = lo;
1429   TRACE_ALU_RESULT2 (HI, LO);
1430 }
1431
1432 :function:::void:do_dmult:int rs, int rt, int rd
1433 {
1434   do_dmultx (SD_, rs, rt, rd, 1);
1435 }
1436
1437 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1438 "dmult r<RS>, r<RT>"
1439 *mipsIII,mipsIV:
1440 // start-sanitize-tx19
1441 *tx19:
1442 // end-sanitize-tx19
1443 // start-sanitize-vr4320
1444 *vr4320:
1445 // end-sanitize-vr4320
1446 {
1447   do_dmult (SD_, RS, RT, 0);
1448 }
1449
1450 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1451 "dmult r<RS>, r<RT>":RD == 0
1452 "dmult r<RD>, r<RS>, r<RT>"
1453 *vr5000:
1454 // start-sanitize-cygnus
1455 *vr5400:
1456 // end-sanitize-cygnus
1457 {
1458   do_dmult (SD_, RS, RT, RD);
1459 }
1460
1461
1462
1463 :function:::void:do_dmultu:int rs, int rt, int rd
1464 {
1465   do_dmultx (SD_, rs, rt, rd, 0);
1466 }
1467
1468 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1469 "dmultu r<RS>, r<RT>"
1470 *mipsIII,mipsIV:
1471 // start-sanitize-tx19
1472 *tx19:
1473 // end-sanitize-tx19
1474 // start-sanitize-vr4320
1475 *vr4320:
1476 // end-sanitize-vr4320
1477 {
1478   do_dmultu (SD_, RS, RT, 0);
1479 }
1480
1481 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1482 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1483 "dmultu r<RS>, r<RT>"
1484 *vr5000:
1485 // start-sanitize-cygnus
1486 *vr5400:
1487 // end-sanitize-cygnus
1488 {
1489   do_dmultu (SD_, RS, RT, RD);
1490 }
1491
1492
1493
1494 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1495 "dsll r<RD>, r<RT>, <SHIFT>"
1496 *mipsIII:
1497 *mipsIV:
1498 *vr5000:
1499 // start-sanitize-vr4320
1500 *vr4320:
1501 // end-sanitize-vr4320
1502 // start-sanitize-cygnus
1503 *vr5400:
1504 // end-sanitize-cygnus
1505 // start-sanitize-r5900
1506 *r5900:
1507 // end-sanitize-r5900
1508 // start-sanitize-tx19
1509 *tx19:
1510 // end-sanitize-tx19
1511 {
1512   int s = SHIFT;
1513   GPR[RD] = GPR[RT] << s;
1514 }
1515
1516
1517 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1518 "dsll32 r<RD>, r<RT>, <SHIFT>"
1519 *mipsIII:
1520 *mipsIV:
1521 *vr5000:
1522 // start-sanitize-vr4320
1523 *vr4320:
1524 // end-sanitize-vr4320
1525 // start-sanitize-cygnus
1526 *vr5400:
1527 // end-sanitize-cygnus
1528 // start-sanitize-r5900
1529 *r5900:
1530 // end-sanitize-r5900
1531 // start-sanitize-tx19
1532 *tx19:
1533 // end-sanitize-tx19
1534 {
1535   int s = 32 + SHIFT;
1536   GPR[RD] = GPR[RT] << s;
1537 }
1538
1539
1540
1541 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1542 "dsllv r<RD>, r<RT>, r<RS>"
1543 *mipsIII:
1544 *mipsIV:
1545 *vr5000:
1546 // start-sanitize-vr4320
1547 *vr4320:
1548 // end-sanitize-vr4320
1549 // start-sanitize-cygnus
1550 *vr5400:
1551 // end-sanitize-cygnus
1552 // start-sanitize-r5900
1553 *r5900:
1554 // end-sanitize-r5900
1555 // start-sanitize-tx19
1556 *tx19:
1557 // end-sanitize-tx19
1558 {
1559   int s = MASKED64 (GPR[RS], 5, 0);
1560   GPR[RD] = GPR[RT] << s;
1561 }
1562
1563
1564
1565 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1566 "dsra r<RD>, r<RT>, <SHIFT>"
1567 *mipsIII:
1568 *mipsIV:
1569 *vr5000:
1570 // start-sanitize-vr4320
1571 *vr4320:
1572 // end-sanitize-vr4320
1573 // start-sanitize-cygnus
1574 *vr5400:
1575 // end-sanitize-cygnus
1576 // start-sanitize-r5900
1577 *r5900:
1578 // end-sanitize-r5900
1579 // start-sanitize-tx19
1580 *tx19:
1581 // end-sanitize-tx19
1582 {
1583   int s = SHIFT;
1584   GPR[RD] = ((signed64) GPR[RT]) >> s;
1585 }
1586
1587
1588 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1589 "dsra32 r<RT>, r<RD>, <SHIFT>"
1590 *mipsIII:
1591 *mipsIV:
1592 *vr5000:
1593 // start-sanitize-vr4320
1594 *vr4320:
1595 // end-sanitize-vr4320
1596 // start-sanitize-cygnus
1597 *vr5400:
1598 // end-sanitize-cygnus
1599 // start-sanitize-r5900
1600 *r5900:
1601 // end-sanitize-r5900
1602 // start-sanitize-tx19
1603 *tx19:
1604 // end-sanitize-tx19
1605 {
1606   int s = 32 + SHIFT;
1607   GPR[RD] = ((signed64) GPR[RT]) >> s;
1608 }
1609
1610
1611 :function:::void:do_dsrav:int rs, int rt, int rd
1612 {
1613   int s = MASKED64 (GPR[rs], 5, 0);
1614   TRACE_ALU_INPUT2 (GPR[rt], s);
1615   GPR[rd] = ((signed64) GPR[rt]) >> s;
1616   TRACE_ALU_RESULT (GPR[rd]);
1617 }
1618
1619 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1620 "dsra32 r<RT>, r<RD>, r<RS>"
1621 *mipsIII:
1622 *mipsIV:
1623 *vr5000:
1624 // start-sanitize-vr4320
1625 *vr4320:
1626 // end-sanitize-vr4320
1627 // start-sanitize-cygnus
1628 *vr5400:
1629 // end-sanitize-cygnus
1630 // start-sanitize-r5900
1631 *r5900:
1632 // end-sanitize-r5900
1633 // start-sanitize-tx19
1634 *tx19:
1635 // end-sanitize-tx19
1636 {
1637   do_dsrav (SD_, RS, RT, RD);
1638 }
1639
1640
1641 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1642 "dsrl r<RD>, r<RT>, <SHIFT>"
1643 *mipsIII:
1644 *mipsIV:
1645 *vr5000:
1646 // start-sanitize-vr4320
1647 *vr4320:
1648 // end-sanitize-vr4320
1649 // start-sanitize-cygnus
1650 *vr5400:
1651 // end-sanitize-cygnus
1652 // start-sanitize-r5900
1653 *r5900:
1654 // end-sanitize-r5900
1655 // start-sanitize-tx19
1656 *tx19:
1657 // end-sanitize-tx19
1658 {
1659   int s = SHIFT;
1660   GPR[RD] = (unsigned64) GPR[RT] >> s;
1661 }
1662
1663
1664 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1665 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1666 *mipsIII:
1667 *mipsIV:
1668 *vr5000:
1669 // start-sanitize-vr4320
1670 *vr4320:
1671 // end-sanitize-vr4320
1672 // start-sanitize-cygnus
1673 *vr5400:
1674 // end-sanitize-cygnus
1675 // start-sanitize-r5900
1676 *r5900:
1677 // end-sanitize-r5900
1678 // start-sanitize-tx19
1679 *tx19:
1680 // end-sanitize-tx19
1681 {
1682   int s = 32 + SHIFT;
1683   GPR[RD] = (unsigned64) GPR[RT] >> s;
1684 }
1685
1686
1687 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1688 "dsrl32 r<RD>, r<RT>, r<RS>"
1689 *mipsIII:
1690 *mipsIV:
1691 *vr5000:
1692 // start-sanitize-vr4320
1693 *vr4320:
1694 // end-sanitize-vr4320
1695 // start-sanitize-cygnus
1696 *vr5400:
1697 // end-sanitize-cygnus
1698 // start-sanitize-r5900
1699 *r5900:
1700 // end-sanitize-r5900
1701 // start-sanitize-tx19
1702 *tx19:
1703 // end-sanitize-tx19
1704 {
1705   int s = MASKED64 (GPR[RS], 5, 0);
1706   GPR[RD] = (unsigned64) GPR[RT] >> s;
1707 }
1708
1709
1710 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1711 "dsub r<RD>, r<RS>, r<RT>"
1712 *mipsIII:
1713 *mipsIV:
1714 *vr5000:
1715 // start-sanitize-vr4320
1716 *vr4320:
1717 // end-sanitize-vr4320
1718 // start-sanitize-cygnus
1719 *vr5400:
1720 // end-sanitize-cygnus
1721 // start-sanitize-r5900
1722 *r5900:
1723 // end-sanitize-r5900
1724 // start-sanitize-tx19
1725 *tx19:
1726 // end-sanitize-tx19
1727 {
1728   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1729   {
1730     ALU64_BEGIN (GPR[RS]);
1731     ALU64_SUB (GPR[RT]);
1732     ALU64_END (GPR[RD]);
1733   }
1734   TRACE_ALU_RESULT (GPR[RD]);
1735 }
1736
1737
1738 :function:::void:do_dsubu:int rs, int rt, int rd
1739 {
1740   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1741   GPR[rd] = GPR[rs] - GPR[rt];
1742   TRACE_ALU_RESULT (GPR[rd]);
1743 }
1744
1745 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1746 "dsubu r<RD>, r<RS>, r<RT>"
1747 *mipsIII:
1748 *mipsIV:
1749 *vr5000:
1750 // start-sanitize-vr4320
1751 *vr4320:
1752 // end-sanitize-vr4320
1753 // start-sanitize-cygnus
1754 *vr5400:
1755 // end-sanitize-cygnus
1756 // start-sanitize-r5900
1757 *r5900:
1758 // end-sanitize-r5900
1759 // start-sanitize-tx19
1760 *tx19:
1761 // end-sanitize-tx19
1762 {
1763   do_dsubu (SD_, RS, RT, RD);
1764 }
1765
1766
1767 000010,26.INSTR_INDEX:NORMAL:32::J
1768 "j <INSTR_INDEX>"
1769 *mipsI,mipsII,mipsIII,mipsIV:
1770 *vr5000:
1771 // start-sanitize-vr4320
1772 *vr4320:
1773 // end-sanitize-vr4320
1774 // start-sanitize-cygnus
1775 *vr5400:
1776 // end-sanitize-cygnus
1777 // start-sanitize-r5900
1778 *r5900:
1779 // end-sanitize-r5900
1780 *r3900:
1781 // start-sanitize-tx19
1782 *tx19:
1783 // end-sanitize-tx19
1784 {
1785   /* NOTE: The region used is that of the delay slot NIA and NOT the
1786      current instruction */
1787   address_word region = (NIA & MASK (63, 28));
1788   DELAY_SLOT (region | (INSTR_INDEX << 2));
1789 }
1790
1791
1792 000011,26.INSTR_INDEX:NORMAL:32::JAL
1793 "jal <INSTR_INDEX>"
1794 *mipsI,mipsII,mipsIII,mipsIV:
1795 *vr5000:
1796 // start-sanitize-vr4320
1797 *vr4320:
1798 // end-sanitize-vr4320
1799 // start-sanitize-cygnus
1800 *vr5400:
1801 // end-sanitize-cygnus
1802 // start-sanitize-r5900
1803 *r5900:
1804 // end-sanitize-r5900
1805 *r3900:
1806 // start-sanitize-tx19
1807 *tx19:
1808 // end-sanitize-tx19
1809 {
1810   /* NOTE: The region used is that of the delay slot and NOT the
1811      current instruction */
1812   address_word region = (NIA & MASK (63, 28));
1813   GPR[31] = CIA + 8;
1814   DELAY_SLOT (region | (INSTR_INDEX << 2));
1815 }
1816
1817
1818 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1819 "jalr r<RS>":RD == 31
1820 "jalr r<RD>, r<RS>"
1821 *mipsI,mipsII,mipsIII,mipsIV:
1822 *vr5000:
1823 // start-sanitize-vr4320
1824 *vr4320:
1825 // end-sanitize-vr4320
1826 // start-sanitize-cygnus
1827 *vr5400:
1828 // end-sanitize-cygnus
1829 // start-sanitize-r5900
1830 *r5900:
1831 // end-sanitize-r5900
1832 *r3900:
1833 // start-sanitize-tx19
1834 *tx19:
1835 // end-sanitize-tx19
1836 {
1837   address_word temp = GPR[RS];
1838   GPR[RD] = CIA + 8;
1839   DELAY_SLOT (temp);
1840 }
1841
1842
1843 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1844 "jr r<RS>"
1845 *mipsI,mipsII,mipsIII,mipsIV:
1846 *vr5000:
1847 // start-sanitize-vr4320
1848 *vr4320:
1849 // end-sanitize-vr4320
1850 // start-sanitize-cygnus
1851 *vr5400:
1852 // end-sanitize-cygnus
1853 // start-sanitize-r5900
1854 *r5900:
1855 // end-sanitize-r5900
1856 *r3900:
1857 // start-sanitize-tx19
1858 *tx19:
1859 // end-sanitize-tx19
1860 {
1861   DELAY_SLOT (GPR[RS]);
1862 }
1863
1864
1865 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1866 {
1867   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1868   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1869   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1870   unsigned int byte;
1871   address_word paddr;
1872   int uncached;
1873   unsigned64 memval;
1874   address_word vaddr;
1875
1876   vaddr = base + offset;
1877   if ((vaddr & access) != 0)
1878     SignalExceptionAddressLoad ();
1879   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1880   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1881   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1882   byte = ((vaddr & mask) ^ bigendiancpu);
1883   return (memval >> (8 * byte));
1884 }
1885
1886
1887 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1888 "lb r<RT>, <OFFSET>(r<BASE>)"
1889 *mipsI,mipsII,mipsIII,mipsIV:
1890 *vr5000:
1891 // start-sanitize-vr4320
1892 *vr4320:
1893 // end-sanitize-vr4320
1894 // start-sanitize-cygnus
1895 *vr5400:
1896 // end-sanitize-cygnus
1897 // start-sanitize-r5900
1898 *r5900:
1899 // end-sanitize-r5900
1900 *r3900:
1901 // start-sanitize-tx19
1902 *tx19:
1903 // end-sanitize-tx19
1904 {
1905   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1906 }
1907
1908
1909 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1910 "lbu r<RT>, <OFFSET>(r<BASE>)"
1911 *mipsI,mipsII,mipsIII,mipsIV:
1912 *vr5000:
1913 // start-sanitize-vr4320
1914 *vr4320:
1915 // end-sanitize-vr4320
1916 // start-sanitize-cygnus
1917 *vr5400:
1918 // end-sanitize-cygnus
1919 // start-sanitize-r5900
1920 *r5900:
1921 // end-sanitize-r5900
1922 *r3900:
1923 // start-sanitize-tx19
1924 *tx19:
1925 // end-sanitize-tx19
1926 {
1927   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1928 }
1929
1930
1931 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1932 "ld r<RT>, <OFFSET>(r<BASE>)"
1933 *mipsIII:
1934 *mipsIV:
1935 *vr5000:
1936 // start-sanitize-vr4320
1937 *vr4320:
1938 // end-sanitize-vr4320
1939 // start-sanitize-cygnus
1940 *vr5400:
1941 // end-sanitize-cygnus
1942 // start-sanitize-r5900
1943 *r5900:
1944 // end-sanitize-r5900
1945 // start-sanitize-tx19
1946 *tx19:
1947 // end-sanitize-tx19
1948 {
1949   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1950 }
1951
1952
1953 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1954 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1955 *mipsII:
1956 *mipsIII:
1957 *mipsIV:
1958 *vr5000:
1959 // start-sanitize-vr4320
1960 *vr4320:
1961 // end-sanitize-vr4320
1962 // start-sanitize-cygnus
1963 *vr5400:
1964 // end-sanitize-cygnus
1965 *r3900:
1966 // start-sanitize-tx19
1967 *tx19:
1968 // end-sanitize-tx19
1969 {
1970   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1971 }
1972
1973
1974
1975
1976 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1977 "ldl r<RT>, <OFFSET>(r<BASE>)"
1978 *mipsIII:
1979 *mipsIV:
1980 *vr5000:
1981 // start-sanitize-vr4320
1982 *vr4320:
1983 // end-sanitize-vr4320
1984 // start-sanitize-cygnus
1985 *vr5400:
1986 // end-sanitize-cygnus
1987 // start-sanitize-r5900
1988 *r5900:
1989 // end-sanitize-r5900
1990 // start-sanitize-tx19
1991 *tx19:
1992 // end-sanitize-tx19
1993 {
1994   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1995 }
1996
1997
1998 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1999 "ldr r<RT>, <OFFSET>(r<BASE>)"
2000 *mipsIII:
2001 *mipsIV:
2002 *vr5000:
2003 // start-sanitize-vr4320
2004 *vr4320:
2005 // end-sanitize-vr4320
2006 // start-sanitize-cygnus
2007 *vr5400:
2008 // end-sanitize-cygnus
2009 // start-sanitize-r5900
2010 *r5900:
2011 // end-sanitize-r5900
2012 // start-sanitize-tx19
2013 *tx19:
2014 // end-sanitize-tx19
2015 {
2016   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2017 }
2018
2019
2020 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2021 "lh r<RT>, <OFFSET>(r<BASE>)"
2022 *mipsI,mipsII,mipsIII,mipsIV:
2023 *vr5000:
2024 // start-sanitize-vr4320
2025 *vr4320:
2026 // end-sanitize-vr4320
2027 // start-sanitize-cygnus
2028 *vr5400:
2029 // end-sanitize-cygnus
2030 // start-sanitize-r5900
2031 *r5900:
2032 // end-sanitize-r5900
2033 *r3900:
2034 // start-sanitize-tx19
2035 *tx19:
2036 // end-sanitize-tx19
2037 {
2038   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2039 }
2040
2041
2042 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2043 "lhu r<RT>, <OFFSET>(r<BASE>)"
2044 *mipsI,mipsII,mipsIII,mipsIV:
2045 *vr5000:
2046 // start-sanitize-vr4320
2047 *vr4320:
2048 // end-sanitize-vr4320
2049 // start-sanitize-cygnus
2050 *vr5400:
2051 // end-sanitize-cygnus
2052 // start-sanitize-r5900
2053 *r5900:
2054 // end-sanitize-r5900
2055 *r3900:
2056 // start-sanitize-tx19
2057 *tx19:
2058 // end-sanitize-tx19
2059 {
2060   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2061 }
2062
2063
2064 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2065 "ll r<RT>, <OFFSET>(r<BASE>)"
2066 *mipsII:
2067 *mipsIII:
2068 *mipsIV:
2069 *vr5000:
2070 // start-sanitize-vr4320
2071 *vr4320:
2072 // end-sanitize-vr4320
2073 // start-sanitize-cygnus
2074 *vr5400:
2075 // end-sanitize-cygnus
2076 // start-sanitize-r5900
2077 *r5900:
2078 // end-sanitize-r5900
2079 // start-sanitize-tx19
2080 *tx19:
2081 // end-sanitize-tx19
2082 {
2083   unsigned32 instruction = instruction_0;
2084   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2085   int destreg = ((instruction >> 16) & 0x0000001F);
2086   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2087   {
2088     address_word vaddr = ((unsigned64)op1 + offset);
2089     address_word paddr;
2090     int uncached;
2091     if ((vaddr & 3) != 0)
2092       SignalExceptionAddressLoad();
2093     else
2094       {
2095         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2096           {
2097             unsigned64 memval = 0;
2098             unsigned64 memval1 = 0;
2099             unsigned64 mask = 0x7;
2100             unsigned int shift = 2;
2101             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2102             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2103             unsigned int byte;
2104             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2105             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2106             byte = ((vaddr & mask) ^ (bigend << shift));
2107             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2108             LLBIT = 1;
2109           }
2110       }
2111   }
2112 }
2113
2114
2115 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2116 "lld r<RT>, <OFFSET>(r<BASE>)"
2117 *mipsIII:
2118 *mipsIV:
2119 *vr5000:
2120 // start-sanitize-vr4320
2121 *vr4320:
2122 // end-sanitize-vr4320
2123 // start-sanitize-cygnus
2124 *vr5400:
2125 // end-sanitize-cygnus
2126 // start-sanitize-r5900
2127 *r5900:
2128 // end-sanitize-r5900
2129 // start-sanitize-tx19
2130 *tx19:
2131 // end-sanitize-tx19
2132 {
2133   unsigned32 instruction = instruction_0;
2134   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2135   int destreg = ((instruction >> 16) & 0x0000001F);
2136   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2137   {
2138     address_word vaddr = ((unsigned64)op1 + offset);
2139     address_word paddr;
2140     int uncached;
2141     if ((vaddr & 7) != 0)
2142       SignalExceptionAddressLoad();
2143     else
2144       {
2145         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2146           {
2147             unsigned64 memval = 0;
2148             unsigned64 memval1 = 0;
2149             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2150             GPR[destreg] = memval;
2151             LLBIT = 1;
2152           }
2153       }
2154   }
2155 }
2156
2157
2158 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2159 "lui r<RT>, <IMMEDIATE>"
2160 *mipsI,mipsII,mipsIII,mipsIV:
2161 *vr5000:
2162 // start-sanitize-vr4320
2163 *vr4320:
2164 // end-sanitize-vr4320
2165 // start-sanitize-cygnus
2166 *vr5400:
2167 // end-sanitize-cygnus
2168 // start-sanitize-r5900
2169 *r5900:
2170 // end-sanitize-r5900
2171 *r3900:
2172 // start-sanitize-tx19
2173 *tx19:
2174 // end-sanitize-tx19
2175 {
2176   TRACE_ALU_INPUT1 (IMMEDIATE);
2177   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2178   TRACE_ALU_RESULT (GPR[RT]);
2179 }
2180
2181
2182 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2183 "lw r<RT>, <OFFSET>(r<BASE>)"
2184 *mipsI,mipsII,mipsIII,mipsIV:
2185 *vr5000:
2186 // start-sanitize-vr4320
2187 *vr4320:
2188 // end-sanitize-vr4320
2189 // start-sanitize-cygnus
2190 *vr5400:
2191 // end-sanitize-cygnus
2192 // start-sanitize-r5900
2193 *r5900:
2194 // end-sanitize-r5900
2195 *r3900:
2196 // start-sanitize-tx19
2197 *tx19:
2198 // end-sanitize-tx19
2199 {
2200   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2201 }
2202
2203
2204 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2205 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2206 *mipsI,mipsII,mipsIII,mipsIV:
2207 *vr5000:
2208 // start-sanitize-vr4320
2209 *vr4320:
2210 // end-sanitize-vr4320
2211 // start-sanitize-cygnus
2212 *vr5400:
2213 // end-sanitize-cygnus
2214 // start-sanitize-r5900
2215 *r5900:
2216 // end-sanitize-r5900
2217 *r3900:
2218 // start-sanitize-tx19
2219 *tx19:
2220 // end-sanitize-tx19
2221 {
2222   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2223 }
2224
2225
2226 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2227 {
2228   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2229   address_word reverseendian = (ReverseEndian ? -1 : 0);
2230   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2231   unsigned int byte;
2232   unsigned int word;
2233   address_word paddr;
2234   int uncached;
2235   unsigned64 memval;
2236   address_word vaddr;
2237   int nr_lhs_bits;
2238   int nr_rhs_bits;
2239   unsigned_word lhs_mask;
2240   unsigned_word temp;
2241
2242   vaddr = base + offset;
2243   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2244   paddr = (paddr ^ (reverseendian & mask));
2245   if (BigEndianMem == 0)
2246     paddr = paddr & ~access;
2247
2248   /* compute where within the word/mem we are */
2249   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2250   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2251   nr_lhs_bits = 8 * byte + 8;
2252   nr_rhs_bits = 8 * access - 8 * byte;
2253   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2254
2255   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2256            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2257            (long) ((unsigned64) paddr >> 32), (long) paddr,
2258            word, byte, nr_lhs_bits, nr_rhs_bits); */
2259
2260   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2261   if (word == 0)
2262     {
2263       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2264       temp = (memval << nr_rhs_bits);
2265     }
2266   else
2267     {
2268       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2269       temp = (memval >> nr_lhs_bits);
2270     }
2271   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2272   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2273
2274   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2275            (long) ((unsigned64) memval >> 32), (long) memval,
2276            (long) ((unsigned64) temp >> 32), (long) temp,
2277            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2278            (long) (rt >> 32), (long) rt); */
2279   return rt;
2280 }
2281
2282
2283 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2284 "lwl r<RT>, <OFFSET>(r<BASE>)"
2285 *mipsI,mipsII,mipsIII,mipsIV:
2286 *vr5000:
2287 // start-sanitize-vr4320
2288 *vr4320:
2289 // end-sanitize-vr4320
2290 // start-sanitize-cygnus
2291 *vr5400:
2292 // end-sanitize-cygnus
2293 // start-sanitize-r5900
2294 *r5900:
2295 // end-sanitize-r5900
2296 *r3900:
2297 // start-sanitize-tx19
2298 *tx19:
2299 // end-sanitize-tx19
2300 {
2301   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2302 }
2303
2304
2305 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2306 {
2307   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2308   address_word reverseendian = (ReverseEndian ? -1 : 0);
2309   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2310   unsigned int byte;
2311   address_word paddr;
2312   int uncached;
2313   unsigned64 memval;
2314   address_word vaddr;
2315
2316   vaddr = base + offset;
2317   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2318   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2319   paddr = (paddr ^ (reverseendian & mask));
2320   if (BigEndianMem != 0)
2321     paddr = paddr & ~access;
2322   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2323   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2324   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2325   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2326      (long) paddr, byte, (long) paddr, (long) memval); */
2327   {
2328     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2329     rt &= ~screen;
2330     rt |= (memval >> (8 * byte)) & screen;
2331   }
2332   return rt;
2333 }
2334
2335
2336 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2337 "lwr r<RT>, <OFFSET>(r<BASE>)"
2338 *mipsI,mipsII,mipsIII,mipsIV:
2339 *vr5000:
2340 // start-sanitize-vr4320
2341 *vr4320:
2342 // end-sanitize-vr4320
2343 // start-sanitize-cygnus
2344 *vr5400:
2345 // end-sanitize-cygnus
2346 // start-sanitize-r5900
2347 *r5900:
2348 // end-sanitize-r5900
2349 *r3900:
2350 // start-sanitize-tx19
2351 *tx19:
2352 // end-sanitize-tx19
2353 {
2354   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2355 }
2356
2357
2358 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2359 "lwu r<RT>, <OFFSET>(r<BASE>)"
2360 *mipsIII:
2361 *mipsIV:
2362 *vr5000:
2363 // start-sanitize-vr4320
2364 *vr4320:
2365 // end-sanitize-vr4320
2366 // start-sanitize-cygnus
2367 *vr5400:
2368 // end-sanitize-cygnus
2369 // start-sanitize-r5900
2370 *r5900:
2371 // end-sanitize-r5900
2372 // start-sanitize-tx19
2373 *tx19:
2374 // end-sanitize-tx19
2375 {
2376   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2377 }
2378
2379
2380 :function:::void:do_mfhi:int rd
2381 {
2382   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2383   TRACE_ALU_INPUT1 (HI);
2384   GPR[rd] = HI;
2385   TRACE_ALU_RESULT (GPR[rd]);
2386 }
2387
2388 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2389 "mfhi r<RD>"
2390 *mipsI,mipsII,mipsIII,mipsIV:
2391 *vr5000:
2392 // start-sanitize-vr4320
2393 *vr4320:
2394 // end-sanitize-vr4320
2395 // start-sanitize-cygnus
2396 *vr5400:
2397 // end-sanitize-cygnus
2398 // start-sanitize-r5900
2399 *r5900:
2400 // end-sanitize-r5900
2401 *r3900:
2402 // start-sanitize-tx19
2403 *tx19:
2404 // end-sanitize-tx19
2405 {
2406   do_mfhi (SD_, RD);
2407 }
2408
2409
2410
2411 :function:::void:do_mflo:int rd
2412 {
2413   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2414   TRACE_ALU_INPUT1 (LO);
2415   GPR[rd] = LO;
2416   TRACE_ALU_RESULT (GPR[rd]);
2417 }
2418
2419 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2420 "mflo r<RD>"
2421 *mipsI,mipsII,mipsIII,mipsIV:
2422 *vr5000:
2423 // start-sanitize-vr4320
2424 *vr4320:
2425 // end-sanitize-vr4320
2426 // start-sanitize-cygnus
2427 *vr5400:
2428 // end-sanitize-cygnus
2429 // start-sanitize-r5900
2430 *r5900:
2431 // end-sanitize-r5900
2432 *r3900:
2433 // start-sanitize-tx19
2434 *tx19:
2435 // end-sanitize-tx19
2436 {
2437   do_mflo (SD_, RD);
2438 }
2439
2440
2441
2442 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2443 "movn r<RD>, r<RS>, r<RT>"
2444 *mipsIV:
2445 *vr5000:
2446 // start-sanitize-vr4320
2447 *vr4320:
2448 // end-sanitize-vr4320
2449 // start-sanitize-cygnus
2450 *vr5400:
2451 // end-sanitize-cygnus
2452 // start-sanitize-r5900
2453 *r5900:
2454 // end-sanitize-r5900
2455 {
2456   if (GPR[RT] != 0)
2457     GPR[RD] = GPR[RS];
2458 }
2459
2460
2461
2462 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2463 "movz r<RD>, r<RS>, r<RT>"
2464 *mipsIV:
2465 *vr5000:
2466 // start-sanitize-vr4320
2467 *vr4320:
2468 // end-sanitize-vr4320
2469 // start-sanitize-cygnus
2470 *vr5400:
2471 // end-sanitize-cygnus
2472 // start-sanitize-r5900
2473 *r5900:
2474 // end-sanitize-r5900
2475 {
2476   if (GPR[RT] == 0)
2477     GPR[RD] = GPR[RS];
2478 }
2479
2480
2481
2482 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2483 "mthi r<RS>"
2484 *mipsI,mipsII,mipsIII,mipsIV:
2485 *vr5000:
2486 // start-sanitize-vr4320
2487 *vr4320:
2488 // end-sanitize-vr4320
2489 // start-sanitize-cygnus
2490 *vr5400:
2491 // end-sanitize-cygnus
2492 // start-sanitize-r5900
2493 *r5900:
2494 // end-sanitize-r5900
2495 *r3900:
2496 // start-sanitize-tx19
2497 *tx19:
2498 // end-sanitize-tx19
2499 {
2500   check_mt_hilo (SD_, HIHISTORY);
2501   HI = GPR[RS];
2502 }
2503
2504
2505
2506 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2507 "mtlo r<RS>"
2508 *mipsI,mipsII,mipsIII,mipsIV:
2509 *vr5000:
2510 // start-sanitize-vr4320
2511 *vr4320:
2512 // end-sanitize-vr4320
2513 // start-sanitize-cygnus
2514 *vr5400:
2515 // end-sanitize-cygnus
2516 // start-sanitize-r5900
2517 *r5900:
2518 // end-sanitize-r5900
2519 *r3900:
2520 // start-sanitize-tx19
2521 *tx19:
2522 // end-sanitize-tx19
2523 {
2524   check_mt_hilo (SD_, LOHISTORY);
2525   LO = GPR[RS];
2526 }
2527
2528
2529
2530 :function:::void:do_mult:int rs, int rt, int rd
2531 {
2532   signed64 prod;
2533   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2534   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2535   prod = (((signed64)(signed32) GPR[rs])
2536           * ((signed64)(signed32) GPR[rt]));
2537   LO = EXTEND32 (VL4_8 (prod));
2538   HI = EXTEND32 (VH4_8 (prod));
2539   if (rd != 0)
2540     GPR[rd] = LO;
2541   TRACE_ALU_RESULT2 (HI, LO);
2542 }
2543
2544 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2545 "mult r<RS>, r<RT>"
2546 *mipsI,mipsII,mipsIII,mipsIV:
2547 // start-sanitize-vr4320
2548 *vr4320:
2549 // end-sanitize-vr4320
2550 {
2551   do_mult (SD_, RS, RT, 0);
2552 }
2553
2554
2555 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2556 "mult r<RD>, r<RS>, r<RT>"
2557 *vr5000:
2558 // start-sanitize-cygnus
2559 *vr5400:
2560 // end-sanitize-cygnus
2561 // start-sanitize-r5900
2562 *r5900:
2563 // end-sanitize-r5900
2564 *r3900:
2565 // start-sanitize-tx19
2566 *tx19:
2567 // end-sanitize-tx19
2568 {
2569   do_mult (SD_, RS, RT, RD);
2570 }
2571
2572
2573 :function:::void:do_multu:int rs, int rt, int rd
2574 {
2575   unsigned64 prod;
2576   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2577   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2578   prod = (((unsigned64)(unsigned32) GPR[rs])
2579           * ((unsigned64)(unsigned32) GPR[rt]));
2580   LO = EXTEND32 (VL4_8 (prod));
2581   HI = EXTEND32 (VH4_8 (prod));
2582   if (rd != 0)
2583     GPR[rd] = LO;
2584   TRACE_ALU_RESULT2 (HI, LO);
2585 }
2586
2587 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2588 "multu r<RS>, r<RT>"
2589 *mipsI,mipsII,mipsIII,mipsIV:
2590 // start-sanitize-vr4320
2591 *vr4320:
2592 // end-sanitize-vr4320
2593 {
2594   do_multu (SD_, RS, RT, 0);
2595 }
2596
2597 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2598 "multu r<RD>, r<RS>, r<RT>"
2599 *vr5000:
2600 // start-sanitize-cygnus
2601 *vr5400:
2602 // end-sanitize-cygnus
2603 // start-sanitize-r5900
2604 *r5900:
2605 // end-sanitize-r5900
2606 *r3900:
2607 // start-sanitize-tx19
2608 *tx19:
2609 // end-sanitize-tx19
2610 {
2611   do_multu (SD_, RS, RT, 0);
2612 }
2613
2614
2615 :function:::void:do_nor:int rs, int rt, int rd
2616 {
2617   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2618   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2619   TRACE_ALU_RESULT (GPR[rd]);
2620 }
2621
2622 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2623 "nor r<RD>, r<RS>, r<RT>"
2624 *mipsI,mipsII,mipsIII,mipsIV:
2625 *vr5000:
2626 // start-sanitize-vr4320
2627 *vr4320:
2628 // end-sanitize-vr4320
2629 // start-sanitize-cygnus
2630 *vr5400:
2631 // end-sanitize-cygnus
2632 // start-sanitize-r5900
2633 *r5900:
2634 // end-sanitize-r5900
2635 *r3900:
2636 // start-sanitize-tx19
2637 *tx19:
2638 // end-sanitize-tx19
2639 {
2640   do_nor (SD_, RS, RT, RD);
2641 }
2642
2643
2644 :function:::void:do_or:int rs, int rt, int rd
2645 {
2646   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2647   GPR[rd] = (GPR[rs] | GPR[rt]);
2648   TRACE_ALU_RESULT (GPR[rd]);
2649 }
2650
2651 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2652 "or r<RD>, r<RS>, r<RT>"
2653 *mipsI,mipsII,mipsIII,mipsIV:
2654 *vr5000:
2655 // start-sanitize-vr4320
2656 *vr4320:
2657 // end-sanitize-vr4320
2658 // start-sanitize-cygnus
2659 *vr5400:
2660 // end-sanitize-cygnus
2661 // start-sanitize-r5900
2662 *r5900:
2663 // end-sanitize-r5900
2664 *r3900:
2665 // start-sanitize-tx19
2666 *tx19:
2667 // end-sanitize-tx19
2668 {
2669   do_or (SD_, RS, RT, RD);
2670 }
2671
2672
2673
2674 :function:::void:do_ori:int rs, int rt, unsigned immediate
2675 {
2676   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2677   GPR[rt] = (GPR[rs] | immediate);
2678   TRACE_ALU_RESULT (GPR[rt]);
2679 }
2680
2681 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2682 "ori r<RT>, r<RS>, <IMMEDIATE>"
2683 *mipsI,mipsII,mipsIII,mipsIV:
2684 *vr5000:
2685 // start-sanitize-vr4320
2686 *vr4320:
2687 // end-sanitize-vr4320
2688 // start-sanitize-cygnus
2689 *vr5400:
2690 // end-sanitize-cygnus
2691 // start-sanitize-r5900
2692 *r5900:
2693 // end-sanitize-r5900
2694 *r3900:
2695 // start-sanitize-tx19
2696 *tx19:
2697 // end-sanitize-tx19
2698 {
2699   do_ori (SD_, RS, RT, IMMEDIATE);
2700 }
2701
2702
2703 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2704 *mipsIV:
2705 *vr5000:
2706 // start-sanitize-vr4320
2707 *vr4320:
2708 // end-sanitize-vr4320
2709 // start-sanitize-cygnus
2710 *vr5400:
2711 // end-sanitize-cygnus
2712 // start-sanitize-r5900
2713 *r5900:
2714 // end-sanitize-r5900
2715 {
2716   unsigned32 instruction = instruction_0;
2717   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2718   int hint = ((instruction >> 16) & 0x0000001F);
2719   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2720   {
2721     address_word vaddr = ((unsigned64)op1 + offset);
2722     address_word paddr;
2723     int uncached;
2724     {
2725       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2726         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2727     }
2728   }
2729 }
2730
2731 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2732 {
2733   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2734   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2735   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2736   unsigned int byte;
2737   address_word paddr;
2738   int uncached;
2739   unsigned64 memval;
2740   address_word vaddr;
2741
2742   vaddr = base + offset;
2743   if ((vaddr & access) != 0)
2744     SignalExceptionAddressStore ();
2745   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2746   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2747   byte = ((vaddr & mask) ^ bigendiancpu);
2748   memval = (word << (8 * byte));
2749   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2750 }
2751
2752
2753 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2754 "sb r<RT>, <OFFSET>(r<BASE>)"
2755 *mipsI,mipsII,mipsIII,mipsIV:
2756 *vr5000:
2757 // start-sanitize-vr4320
2758 *vr4320:
2759 // end-sanitize-vr4320
2760 // start-sanitize-cygnus
2761 *vr5400:
2762 // end-sanitize-cygnus
2763 // start-sanitize-r5900
2764 *r5900:
2765 // end-sanitize-r5900
2766 *r3900:
2767 // start-sanitize-tx19
2768 *tx19:
2769 // end-sanitize-tx19
2770 {
2771   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2772 }
2773
2774
2775 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2776 "sc r<RT>, <OFFSET>(r<BASE>)"
2777 *mipsII:
2778 *mipsIII:
2779 *mipsIV:
2780 *vr5000:
2781 // start-sanitize-vr4320
2782 *vr4320:
2783 // end-sanitize-vr4320
2784 // start-sanitize-cygnus
2785 *vr5400:
2786 // end-sanitize-cygnus
2787 // start-sanitize-r5900
2788 *r5900:
2789 // end-sanitize-r5900
2790 // start-sanitize-tx19
2791 *tx19:
2792 // end-sanitize-tx19
2793 {
2794   unsigned32 instruction = instruction_0;
2795   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2796   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2797   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2798   {
2799     address_word vaddr = ((unsigned64)op1 + offset);
2800     address_word paddr;
2801     int uncached;
2802     if ((vaddr & 3) != 0)
2803       SignalExceptionAddressStore();
2804     else
2805       {
2806         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2807           {
2808             unsigned64 memval = 0;
2809             unsigned64 memval1 = 0;
2810             unsigned64 mask = 0x7;
2811             unsigned int byte;
2812             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2813             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2814             memval = ((unsigned64) op2 << (8 * byte));
2815             if (LLBIT)
2816               {
2817                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2818               }
2819             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2820           }
2821       }
2822   }
2823 }
2824
2825
2826 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2827 "scd r<RT>, <OFFSET>(r<BASE>)"
2828 *mipsIII:
2829 *mipsIV:
2830 *vr5000:
2831 // start-sanitize-vr4320
2832 *vr4320:
2833 // end-sanitize-vr4320
2834 // start-sanitize-cygnus
2835 *vr5400:
2836 // end-sanitize-cygnus
2837 // start-sanitize-r5900
2838 *r5900:
2839 // end-sanitize-r5900
2840 // start-sanitize-tx19
2841 *tx19:
2842 // end-sanitize-tx19
2843 {
2844   unsigned32 instruction = instruction_0;
2845   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2846   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2847   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2848   {
2849     address_word vaddr = ((unsigned64)op1 + offset);
2850     address_word paddr;
2851     int uncached;
2852     if ((vaddr & 7) != 0)
2853       SignalExceptionAddressStore();
2854     else
2855       {
2856         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2857           {
2858             unsigned64 memval = 0;
2859             unsigned64 memval1 = 0;
2860             memval = op2;
2861             if (LLBIT)
2862               {
2863                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2864               }
2865             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2866           }
2867       }
2868   }
2869 }
2870
2871
2872 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2873 "sd r<RT>, <OFFSET>(r<BASE>)"
2874 *mipsIII:
2875 *mipsIV:
2876 *vr5000:
2877 // start-sanitize-vr4320
2878 *vr4320:
2879 // end-sanitize-vr4320
2880 // start-sanitize-cygnus
2881 *vr5400:
2882 // end-sanitize-cygnus
2883 // start-sanitize-r5900
2884 *r5900:
2885 // end-sanitize-r5900
2886 // start-sanitize-tx19
2887 *tx19:
2888 // end-sanitize-tx19
2889 {
2890   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2891 }
2892
2893
2894 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2895 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2896 *mipsII:
2897 *mipsIII:
2898 *mipsIV:
2899 *vr5000:
2900 // start-sanitize-vr4320
2901 *vr4320:
2902 // end-sanitize-vr4320
2903 // start-sanitize-cygnus
2904 *vr5400:
2905 // end-sanitize-cygnus
2906 // start-sanitize-tx19
2907 *tx19:
2908 // end-sanitize-tx19
2909 {
2910   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2911 }
2912
2913
2914 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2915 "sdl r<RT>, <OFFSET>(r<BASE>)"
2916 *mipsIII:
2917 *mipsIV:
2918 *vr5000:
2919 // start-sanitize-vr4320
2920 *vr4320:
2921 // end-sanitize-vr4320
2922 // start-sanitize-cygnus
2923 *vr5400:
2924 // end-sanitize-cygnus
2925 // start-sanitize-r5900
2926 *r5900:
2927 // end-sanitize-r5900
2928 // start-sanitize-tx19
2929 *tx19:
2930 // end-sanitize-tx19
2931 {
2932   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2933 }
2934
2935
2936 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2937 "sdr r<RT>, <OFFSET>(r<BASE>)"
2938 *mipsIII:
2939 *mipsIV:
2940 *vr5000:
2941 // start-sanitize-vr4320
2942 *vr4320:
2943 // end-sanitize-vr4320
2944 // start-sanitize-cygnus
2945 *vr5400:
2946 // end-sanitize-cygnus
2947 // start-sanitize-r5900
2948 *r5900:
2949 // end-sanitize-r5900
2950 // start-sanitize-tx19
2951 *tx19:
2952 // end-sanitize-tx19
2953 {
2954   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2955 }
2956
2957
2958 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2959 "sh r<RT>, <OFFSET>(r<BASE>)"
2960 *mipsI,mipsII,mipsIII,mipsIV:
2961 *vr5000:
2962 // start-sanitize-vr4320
2963 *vr4320:
2964 // end-sanitize-vr4320
2965 // start-sanitize-cygnus
2966 *vr5400:
2967 // end-sanitize-cygnus
2968 // start-sanitize-r5900
2969 *r5900:
2970 // end-sanitize-r5900
2971 *r3900:
2972 // start-sanitize-tx19
2973 *tx19:
2974 // end-sanitize-tx19
2975 {
2976   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2977 }
2978
2979
2980 :function:::void:do_sll:int rt, int rd, int shift
2981 {
2982   unsigned32 temp = (GPR[rt] << shift);
2983   TRACE_ALU_INPUT2 (GPR[rt], shift);
2984   GPR[rd] = EXTEND32 (temp);
2985   TRACE_ALU_RESULT (GPR[rd]);
2986 }
2987
2988 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2989 "sll r<RD>, r<RT>, <SHIFT>"
2990 *mipsI,mipsII,mipsIII,mipsIV:
2991 *vr5000:
2992 // start-sanitize-vr4320
2993 *vr4320:
2994 // end-sanitize-vr4320
2995 // start-sanitize-cygnus
2996 *vr5400:
2997 // end-sanitize-cygnus
2998 // start-sanitize-r5900
2999 *r5900:
3000 // end-sanitize-r5900
3001 *r3900:
3002 // start-sanitize-tx19
3003 *tx19:
3004 // end-sanitize-tx19
3005 {
3006   do_sll (SD_, RT, RD, SHIFT);
3007 }
3008
3009
3010 :function:::void:do_sllv:int rs, int rt, int rd
3011 {
3012   int s = MASKED (GPR[rs], 4, 0);
3013   unsigned32 temp = (GPR[rt] << s);
3014   TRACE_ALU_INPUT2 (GPR[rt], s);
3015   GPR[rd] = EXTEND32 (temp);
3016   TRACE_ALU_RESULT (GPR[rd]);
3017 }
3018
3019 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
3020 "sllv r<RD>, r<RT>, r<RS>"
3021 *mipsI,mipsII,mipsIII,mipsIV:
3022 *vr5000:
3023 // start-sanitize-vr4320
3024 *vr4320:
3025 // end-sanitize-vr4320
3026 // start-sanitize-cygnus
3027 *vr5400:
3028 // end-sanitize-cygnus
3029 // start-sanitize-r5900
3030 *r5900:
3031 // end-sanitize-r5900
3032 *r3900:
3033 // start-sanitize-tx19
3034 *tx19:
3035 // end-sanitize-tx19
3036 {
3037   do_sllv (SD_, RS, RT, RD);
3038 }
3039
3040
3041 :function:::void:do_slt:int rs, int rt, int rd
3042 {
3043   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3044   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3045   TRACE_ALU_RESULT (GPR[rd]);
3046 }
3047
3048 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3049 "slt r<RD>, r<RS>, r<RT>"
3050 *mipsI,mipsII,mipsIII,mipsIV:
3051 *vr5000:
3052 // start-sanitize-vr4320
3053 *vr4320:
3054 // end-sanitize-vr4320
3055 // start-sanitize-cygnus
3056 *vr5400:
3057 // end-sanitize-cygnus
3058 // start-sanitize-r5900
3059 *r5900:
3060 // end-sanitize-r5900
3061 *r3900:
3062 // start-sanitize-tx19
3063 *tx19:
3064 // end-sanitize-tx19
3065 {
3066   do_slt (SD_, RS, RT, RD);
3067 }
3068
3069
3070 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3071 {
3072   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3073   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3074   TRACE_ALU_RESULT (GPR[rt]);
3075 }
3076
3077 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3078 "slti r<RT>, r<RS>, <IMMEDIATE>"
3079 *mipsI,mipsII,mipsIII,mipsIV:
3080 *vr5000:
3081 // start-sanitize-vr4320
3082 *vr4320:
3083 // end-sanitize-vr4320
3084 // start-sanitize-cygnus
3085 *vr5400:
3086 // end-sanitize-cygnus
3087 // start-sanitize-r5900
3088 *r5900:
3089 // end-sanitize-r5900
3090 *r3900:
3091 // start-sanitize-tx19
3092 *tx19:
3093 // end-sanitize-tx19
3094 {
3095   do_slti (SD_, RS, RT, IMMEDIATE);
3096 }
3097
3098
3099 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3100 {
3101   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3102   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3103   TRACE_ALU_RESULT (GPR[rt]);
3104 }
3105
3106 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3107 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3108 *mipsI,mipsII,mipsIII,mipsIV:
3109 *vr5000:
3110 // start-sanitize-vr4320
3111 *vr4320:
3112 // end-sanitize-vr4320
3113 // start-sanitize-cygnus
3114 *vr5400:
3115 // end-sanitize-cygnus
3116 // start-sanitize-r5900
3117 *r5900:
3118 // end-sanitize-r5900
3119 *r3900:
3120 // start-sanitize-tx19
3121 *tx19:
3122 // end-sanitize-tx19
3123 {
3124   do_sltiu (SD_, RS, RT, IMMEDIATE);
3125 }
3126
3127
3128
3129 :function:::void:do_sltu:int rs, int rt, int rd
3130 {
3131   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3132   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3133   TRACE_ALU_RESULT (GPR[rd]);
3134 }
3135
3136 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3137 "sltu r<RD>, r<RS>, r<RT>"
3138 *mipsI,mipsII,mipsIII,mipsIV:
3139 *vr5000:
3140 // start-sanitize-vr4320
3141 *vr4320:
3142 // end-sanitize-vr4320
3143 // start-sanitize-cygnus
3144 *vr5400:
3145 // end-sanitize-cygnus
3146 // start-sanitize-r5900
3147 *r5900:
3148 // end-sanitize-r5900
3149 *r3900:
3150 // start-sanitize-tx19
3151 *tx19:
3152 // end-sanitize-tx19
3153 {
3154   do_sltu (SD_, RS, RT, RD);
3155 }
3156
3157
3158 :function:::void:do_sra:int rt, int rd, int shift
3159 {
3160   signed32 temp = (signed32) GPR[rt] >> shift;
3161   TRACE_ALU_INPUT2 (GPR[rt], shift);
3162   GPR[rd] = EXTEND32 (temp);
3163   TRACE_ALU_RESULT (GPR[rd]);
3164 }
3165
3166 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3167 "sra r<RD>, r<RT>, <SHIFT>"
3168 *mipsI,mipsII,mipsIII,mipsIV:
3169 *vr5000:
3170 // start-sanitize-vr4320
3171 *vr4320:
3172 // end-sanitize-vr4320
3173 // start-sanitize-cygnus
3174 *vr5400:
3175 // end-sanitize-cygnus
3176 // start-sanitize-r5900
3177 *r5900:
3178 // end-sanitize-r5900
3179 *r3900:
3180 // start-sanitize-tx19
3181 *tx19:
3182 // end-sanitize-tx19
3183 {
3184   do_sra (SD_, RT, RD, SHIFT);
3185 }
3186
3187
3188
3189 :function:::void:do_srav:int rs, int rt, int rd
3190 {
3191   int s = MASKED (GPR[rs], 4, 0);
3192   signed32 temp = (signed32) GPR[rt] >> s;
3193   TRACE_ALU_INPUT2 (GPR[rt], s);
3194   GPR[rd] = EXTEND32 (temp);
3195   TRACE_ALU_RESULT (GPR[rd]);
3196 }
3197
3198 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3199 "srav r<RD>, r<RT>, r<RS>"
3200 *mipsI,mipsII,mipsIII,mipsIV:
3201 *vr5000:
3202 // start-sanitize-vr4320
3203 *vr4320:
3204 // end-sanitize-vr4320
3205 // start-sanitize-cygnus
3206 *vr5400:
3207 // end-sanitize-cygnus
3208 // start-sanitize-r5900
3209 *r5900:
3210 // end-sanitize-r5900
3211 *r3900:
3212 // start-sanitize-tx19
3213 *tx19:
3214 // end-sanitize-tx19
3215 {
3216   do_srav (SD_, RS, RT, RD);
3217 }
3218
3219
3220
3221 :function:::void:do_srl:int rt, int rd, int shift
3222 {
3223   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3224   TRACE_ALU_INPUT2 (GPR[rt], shift);
3225   GPR[rd] = EXTEND32 (temp);
3226   TRACE_ALU_RESULT (GPR[rd]);
3227 }
3228
3229 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3230 "srl r<RD>, r<RT>, <SHIFT>"
3231 *mipsI,mipsII,mipsIII,mipsIV:
3232 *vr5000:
3233 // start-sanitize-vr4320
3234 *vr4320:
3235 // end-sanitize-vr4320
3236 // start-sanitize-cygnus
3237 *vr5400:
3238 // end-sanitize-cygnus
3239 // start-sanitize-r5900
3240 *r5900:
3241 // end-sanitize-r5900
3242 *r3900:
3243 // start-sanitize-tx19
3244 *tx19:
3245 // end-sanitize-tx19
3246 {
3247   do_srl (SD_, RT, RD, SHIFT);
3248 }
3249
3250
3251 :function:::void:do_srlv:int rs, int rt, int rd
3252 {
3253   int s = MASKED (GPR[rs], 4, 0);
3254   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3255   TRACE_ALU_INPUT2 (GPR[rt], s);
3256   GPR[rd] = EXTEND32 (temp);
3257   TRACE_ALU_RESULT (GPR[rd]);
3258 }
3259
3260 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3261 "srlv r<RD>, r<RT>, r<RS>"
3262 *mipsI,mipsII,mipsIII,mipsIV:
3263 *vr5000:
3264 // start-sanitize-vr4320
3265 *vr4320:
3266 // end-sanitize-vr4320
3267 // start-sanitize-cygnus
3268 *vr5400:
3269 // end-sanitize-cygnus
3270 // start-sanitize-r5900
3271 *r5900:
3272 // end-sanitize-r5900
3273 *r3900:
3274 // start-sanitize-tx19
3275 *tx19:
3276 // end-sanitize-tx19
3277 {
3278   do_srlv (SD_, RS, RT, RD);
3279 }
3280
3281
3282 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3283 "sub r<RD>, r<RS>, r<RT>"
3284 *mipsI,mipsII,mipsIII,mipsIV:
3285 *vr5000:
3286 // start-sanitize-vr4320
3287 *vr4320:
3288 // end-sanitize-vr4320
3289 // start-sanitize-cygnus
3290 *vr5400:
3291 // end-sanitize-cygnus
3292 // start-sanitize-r5900
3293 *r5900:
3294 // end-sanitize-r5900
3295 *r3900:
3296 // start-sanitize-tx19
3297 *tx19:
3298 // end-sanitize-tx19
3299 {
3300   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3301   {
3302     ALU32_BEGIN (GPR[RS]);
3303     ALU32_SUB (GPR[RT]);
3304     ALU32_END (GPR[RD]);
3305   }
3306   TRACE_ALU_RESULT (GPR[RD]);
3307 }
3308
3309
3310 :function:::void:do_subu:int rs, int rt, int rd
3311 {
3312   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3313   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3314   TRACE_ALU_RESULT (GPR[rd]);
3315 }
3316
3317 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3318 "subu r<RD>, r<RS>, r<RT>"
3319 *mipsI,mipsII,mipsIII,mipsIV:
3320 *vr5000:
3321 // start-sanitize-vr4320
3322 *vr4320:
3323 // end-sanitize-vr4320
3324 // start-sanitize-cygnus
3325 *vr5400:
3326 // end-sanitize-cygnus
3327 // start-sanitize-r5900
3328 *r5900:
3329 // end-sanitize-r5900
3330 *r3900:
3331 // start-sanitize-tx19
3332 *tx19:
3333 // end-sanitize-tx19
3334 {
3335   do_subu (SD_, RS, RT, RD);
3336 }
3337
3338
3339 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3340 "sw r<RT>, <OFFSET>(r<BASE>)"
3341 *mipsI,mipsII,mipsIII,mipsIV:
3342 // start-sanitize-tx19
3343 *tx19:
3344 // end-sanitize-tx19
3345 *r3900:
3346 // start-sanitize-vr4320
3347 *vr4320:
3348 // end-sanitize-vr4320
3349 *vr5000:
3350 // start-sanitize-cygnus
3351 *vr5400:
3352 // end-sanitize-cygnus
3353 // start-sanitize-r5900
3354 *r5900:
3355 // end-sanitize-r5900
3356 {
3357   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3358 }
3359
3360
3361 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3362 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3363 *mipsI,mipsII,mipsIII,mipsIV:
3364 *vr5000:
3365 // start-sanitize-vr4320
3366 *vr4320:
3367 // end-sanitize-vr4320
3368 // start-sanitize-cygnus
3369 *vr5400:
3370 // end-sanitize-cygnus
3371 *r3900:
3372 // start-sanitize-tx19
3373 *tx19:
3374 // end-sanitize-tx19
3375 {
3376   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3377 }
3378
3379
3380
3381 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3382 {
3383   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3384   address_word reverseendian = (ReverseEndian ? -1 : 0);
3385   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3386   unsigned int byte;
3387   unsigned int word;
3388   address_word paddr;
3389   int uncached;
3390   unsigned64 memval;
3391   address_word vaddr;
3392   int nr_lhs_bits;
3393   int nr_rhs_bits;
3394
3395   vaddr = base + offset;
3396   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3397   paddr = (paddr ^ (reverseendian & mask));
3398   if (BigEndianMem == 0)
3399     paddr = paddr & ~access;
3400
3401   /* compute where within the word/mem we are */
3402   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3403   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3404   nr_lhs_bits = 8 * byte + 8;
3405   nr_rhs_bits = 8 * access - 8 * byte;
3406   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3407   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3408            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3409            (long) ((unsigned64) paddr >> 32), (long) paddr,
3410            word, byte, nr_lhs_bits, nr_rhs_bits); */
3411
3412   if (word == 0)
3413     {
3414       memval = (rt >> nr_rhs_bits);
3415     }
3416   else
3417     {
3418       memval = (rt << nr_lhs_bits);
3419     }
3420   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3421            (long) ((unsigned64) rt >> 32), (long) rt,
3422            (long) ((unsigned64) memval >> 32), (long) memval); */
3423   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3424 }
3425
3426
3427 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3428 "swl r<RT>, <OFFSET>(r<BASE>)"
3429 *mipsI,mipsII,mipsIII,mipsIV:
3430 *vr5000:
3431 // start-sanitize-vr4320
3432 *vr4320:
3433 // end-sanitize-vr4320
3434 // start-sanitize-cygnus
3435 *vr5400:
3436 // end-sanitize-cygnus
3437 // start-sanitize-r5900
3438 *r5900:
3439 // end-sanitize-r5900
3440 *r3900:
3441 // start-sanitize-tx19
3442 *tx19:
3443 // end-sanitize-tx19
3444 {
3445   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3446 }
3447
3448
3449 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3450 {
3451   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3452   address_word reverseendian = (ReverseEndian ? -1 : 0);
3453   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3454   unsigned int byte;
3455   address_word paddr;
3456   int uncached;
3457   unsigned64 memval;
3458   address_word vaddr;
3459
3460   vaddr = base + offset;
3461   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3462   paddr = (paddr ^ (reverseendian & mask));
3463   if (BigEndianMem != 0)
3464     paddr &= ~access;
3465   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3466   memval = (rt << (byte * 8));
3467   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3468 }
3469
3470 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3471 "swr r<RT>, <OFFSET>(r<BASE>)"
3472 *mipsI,mipsII,mipsIII,mipsIV:
3473 *vr5000:
3474 // start-sanitize-vr4320
3475 *vr4320:
3476 // end-sanitize-vr4320
3477 // start-sanitize-cygnus
3478 *vr5400:
3479 // end-sanitize-cygnus
3480 // start-sanitize-r5900
3481 *r5900:
3482 // end-sanitize-r5900
3483 *r3900:
3484 // start-sanitize-tx19
3485 *tx19:
3486 // end-sanitize-tx19
3487 {
3488   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3489 }
3490
3491
3492 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3493 "sync":STYPE == 0
3494 "sync <STYPE>"
3495 *mipsII:
3496 *mipsIII:
3497 *mipsIV:
3498 *vr5000:
3499 // start-sanitize-vr4320
3500 *vr4320:
3501 // end-sanitize-vr4320
3502 // start-sanitize-cygnus
3503 *vr5400:
3504 // end-sanitize-cygnus
3505 // start-sanitize-r5900
3506 *r5900:
3507 // end-sanitize-r5900
3508 *r3900:
3509 // start-sanitize-tx19
3510 *tx19:
3511 // end-sanitize-tx19
3512 {
3513   SyncOperation (STYPE);
3514 }
3515
3516
3517 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3518 "syscall <CODE>"
3519 *mipsI,mipsII,mipsIII,mipsIV:
3520 *vr5000:
3521 // start-sanitize-vr4320
3522 *vr4320:
3523 // end-sanitize-vr4320
3524 // start-sanitize-cygnus
3525 *vr5400:
3526 // end-sanitize-cygnus
3527 // start-sanitize-r5900
3528 *r5900:
3529 // end-sanitize-r5900
3530 *r3900:
3531 // start-sanitize-tx19
3532 *tx19:
3533 // end-sanitize-tx19
3534 {
3535   SignalException(SystemCall, instruction_0);
3536 }
3537
3538
3539 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3540 "teq r<RS>, r<RT>"
3541 *mipsII:
3542 *mipsIII:
3543 *mipsIV:
3544 *vr5000:
3545 // start-sanitize-vr4320
3546 *vr4320:
3547 // end-sanitize-vr4320
3548 // start-sanitize-cygnus
3549 *vr5400:
3550 // end-sanitize-cygnus
3551 // start-sanitize-r5900
3552 *r5900:
3553 // end-sanitize-r5900
3554 // start-sanitize-tx19
3555 *tx19:
3556 // end-sanitize-tx19
3557 {
3558   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3559     SignalException(Trap, instruction_0);
3560 }
3561
3562
3563 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3564 "teqi r<RS>, <IMMEDIATE>"
3565 *mipsII:
3566 *mipsIII:
3567 *mipsIV:
3568 *vr5000:
3569 // start-sanitize-vr4320
3570 *vr4320:
3571 // end-sanitize-vr4320
3572 // start-sanitize-cygnus
3573 *vr5400:
3574 // end-sanitize-cygnus
3575 // start-sanitize-r5900
3576 *r5900:
3577 // end-sanitize-r5900
3578 // start-sanitize-tx19
3579 *tx19:
3580 // end-sanitize-tx19
3581 {
3582   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3583     SignalException(Trap, instruction_0);
3584 }
3585
3586
3587 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3588 "tge r<RS>, r<RT>"
3589 *mipsII:
3590 *mipsIII:
3591 *mipsIV:
3592 *vr5000:
3593 // start-sanitize-vr4320
3594 *vr4320:
3595 // end-sanitize-vr4320
3596 // start-sanitize-cygnus
3597 *vr5400:
3598 // end-sanitize-cygnus
3599 // start-sanitize-r5900
3600 *r5900:
3601 // end-sanitize-r5900
3602 // start-sanitize-tx19
3603 *tx19:
3604 // end-sanitize-tx19
3605 {
3606   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3607     SignalException(Trap, instruction_0);
3608 }
3609
3610
3611 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3612 "tgei r<RS>, <IMMEDIATE>"
3613 *mipsII:
3614 *mipsIII:
3615 *mipsIV:
3616 *vr5000:
3617 // start-sanitize-vr4320
3618 *vr4320:
3619 // end-sanitize-vr4320
3620 // start-sanitize-cygnus
3621 *vr5400:
3622 // end-sanitize-cygnus
3623 // start-sanitize-r5900
3624 *r5900:
3625 // end-sanitize-r5900
3626 // start-sanitize-tx19
3627 *tx19:
3628 // end-sanitize-tx19
3629 {
3630   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3631     SignalException(Trap, instruction_0);
3632 }
3633
3634
3635 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3636 "tgeiu r<RS>, <IMMEDIATE>"
3637 *mipsII:
3638 *mipsIII:
3639 *mipsIV:
3640 *vr5000:
3641 // start-sanitize-vr4320
3642 *vr4320:
3643 // end-sanitize-vr4320
3644 // start-sanitize-cygnus
3645 *vr5400:
3646 // end-sanitize-cygnus
3647 // start-sanitize-r5900
3648 *r5900:
3649 // end-sanitize-r5900
3650 // start-sanitize-tx19
3651 *tx19:
3652 // end-sanitize-tx19
3653 {
3654   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3655     SignalException(Trap, instruction_0);
3656 }
3657
3658
3659 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3660 "tgeu r<RS>, r<RT>"
3661 *mipsII:
3662 *mipsIII:
3663 *mipsIV:
3664 *vr5000:
3665 // start-sanitize-vr4320
3666 *vr4320:
3667 // end-sanitize-vr4320
3668 // start-sanitize-cygnus
3669 *vr5400:
3670 // end-sanitize-cygnus
3671 // start-sanitize-r5900
3672 *r5900:
3673 // end-sanitize-r5900
3674 // start-sanitize-tx19
3675 *tx19:
3676 // end-sanitize-tx19
3677 {
3678   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3679     SignalException(Trap, instruction_0);
3680 }
3681
3682
3683 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3684 "tlt r<RS>, r<RT>"
3685 *mipsII:
3686 *mipsIII:
3687 *mipsIV:
3688 *vr5000:
3689 // start-sanitize-vr4320
3690 *vr4320:
3691 // end-sanitize-vr4320
3692 // start-sanitize-cygnus
3693 *vr5400:
3694 // end-sanitize-cygnus
3695 // start-sanitize-r5900
3696 *r5900:
3697 // end-sanitize-r5900
3698 // start-sanitize-tx19
3699 *tx19:
3700 // end-sanitize-tx19
3701 {
3702   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3703     SignalException(Trap, instruction_0);
3704 }
3705
3706
3707 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3708 "tlti r<RS>, <IMMEDIATE>"
3709 *mipsII:
3710 *mipsIII:
3711 *mipsIV:
3712 *vr5000:
3713 // start-sanitize-vr4320
3714 *vr4320:
3715 // end-sanitize-vr4320
3716 // start-sanitize-cygnus
3717 *vr5400:
3718 // end-sanitize-cygnus
3719 // start-sanitize-r5900
3720 *r5900:
3721 // end-sanitize-r5900
3722 // start-sanitize-tx19
3723 *tx19:
3724 // end-sanitize-tx19
3725 {
3726   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3727     SignalException(Trap, instruction_0);
3728 }
3729
3730
3731 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3732 "tltiu r<RS>, <IMMEDIATE>"
3733 *mipsII:
3734 *mipsIII:
3735 *mipsIV:
3736 *vr5000:
3737 // start-sanitize-vr4320
3738 *vr4320:
3739 // end-sanitize-vr4320
3740 // start-sanitize-cygnus
3741 *vr5400:
3742 // end-sanitize-cygnus
3743 // start-sanitize-r5900
3744 *r5900:
3745 // end-sanitize-r5900
3746 // start-sanitize-tx19
3747 *tx19:
3748 // end-sanitize-tx19
3749 {
3750   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3751     SignalException(Trap, instruction_0);
3752 }
3753
3754
3755 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3756 "tltu r<RS>, r<RT>"
3757 *mipsII:
3758 *mipsIII:
3759 *mipsIV:
3760 *vr5000:
3761 // start-sanitize-vr4320
3762 *vr4320:
3763 // end-sanitize-vr4320
3764 // start-sanitize-cygnus
3765 *vr5400:
3766 // end-sanitize-cygnus
3767 // start-sanitize-r5900
3768 *r5900:
3769 // end-sanitize-r5900
3770 // start-sanitize-tx19
3771 *tx19:
3772 // end-sanitize-tx19
3773 {
3774   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3775     SignalException(Trap, instruction_0);
3776 }
3777
3778
3779 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3780 "tne r<RS>, r<RT>"
3781 *mipsII:
3782 *mipsIII:
3783 *mipsIV:
3784 *vr5000:
3785 // start-sanitize-vr4320
3786 *vr4320:
3787 // end-sanitize-vr4320
3788 // start-sanitize-cygnus
3789 *vr5400:
3790 // end-sanitize-cygnus
3791 // start-sanitize-r5900
3792 *r5900:
3793 // end-sanitize-r5900
3794 // start-sanitize-tx19
3795 *tx19:
3796 // end-sanitize-tx19
3797 {
3798   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3799     SignalException(Trap, instruction_0);
3800 }
3801
3802
3803 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3804 "tne r<RS>, <IMMEDIATE>"
3805 *mipsII:
3806 *mipsIII:
3807 *mipsIV:
3808 *vr5000:
3809 // start-sanitize-vr4320
3810 *vr4320:
3811 // end-sanitize-vr4320
3812 // start-sanitize-cygnus
3813 *vr5400:
3814 // end-sanitize-cygnus
3815 // start-sanitize-r5900
3816 *r5900:
3817 // end-sanitize-r5900
3818 // start-sanitize-tx19
3819 *tx19:
3820 // end-sanitize-tx19
3821 {
3822   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3823     SignalException(Trap, instruction_0);
3824 }
3825
3826
3827 :function:::void:do_xor:int rs, int rt, int rd
3828 {
3829   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3830   GPR[rd] = GPR[rs] ^ GPR[rt];
3831   TRACE_ALU_RESULT (GPR[rd]);
3832 }
3833
3834 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3835 "xor r<RD>, r<RS>, r<RT>"
3836 *mipsI,mipsII,mipsIII,mipsIV:
3837 *vr5000:
3838 // start-sanitize-vr4320
3839 *vr4320:
3840 // end-sanitize-vr4320
3841 // start-sanitize-cygnus
3842 *vr5400:
3843 // end-sanitize-cygnus
3844 // start-sanitize-r5900
3845 *r5900:
3846 // end-sanitize-r5900
3847 *r3900:
3848 // start-sanitize-tx19
3849 *tx19:
3850 // end-sanitize-tx19
3851 {
3852   do_xor (SD_, RS, RT, RD);
3853 }
3854
3855
3856 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3857 {
3858   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3859   GPR[rt] = GPR[rs] ^ immediate;
3860   TRACE_ALU_RESULT (GPR[rt]);
3861 }
3862
3863 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3864 "xori r<RT>, r<RS>, <IMMEDIATE>"
3865 *mipsI,mipsII,mipsIII,mipsIV:
3866 *vr5000:
3867 // start-sanitize-vr4320
3868 *vr4320:
3869 // end-sanitize-vr4320
3870 // start-sanitize-cygnus
3871 *vr5400:
3872 // end-sanitize-cygnus
3873 // start-sanitize-r5900
3874 *r5900:
3875 // end-sanitize-r5900
3876 *r3900:
3877 // start-sanitize-tx19
3878 *tx19:
3879 // end-sanitize-tx19
3880 {
3881   do_xori (SD_, RS, RT, IMMEDIATE);
3882 }
3883
3884 \f
3885 //
3886 // MIPS Architecture:
3887 //
3888 //        FPU Instruction Set (COP1 & COP1X)
3889 //
3890
3891
3892 :%s::::FMT:int fmt
3893 {
3894   switch (fmt)
3895     {
3896     case fmt_single: return "s";
3897     case fmt_double: return "d";
3898     case fmt_word: return "w";
3899     case fmt_long: return "l";
3900     default: return "?";
3901     }
3902 }
3903
3904 :%s::::X:int x
3905 {
3906   switch (x)
3907     {
3908     case 0: return "f";
3909     case 1: return "t";
3910     default: return "?";
3911     }
3912 }
3913
3914 :%s::::TF:int tf
3915 {
3916   if (tf)
3917     return "t";
3918   else
3919     return "f";
3920 }
3921
3922 :%s::::ND:int nd
3923 {
3924   if (nd)
3925     return "l";
3926   else
3927     return "";
3928 }
3929
3930 :%s::::COND:int cond
3931 {
3932   switch (cond)
3933     {
3934     case 00: return "f";
3935     case 01: return "un";
3936     case 02: return "eq";
3937     case 03: return "ueq";
3938     case 04: return "olt";
3939     case 05: return "ult";
3940     case 06: return "ole";
3941     case 07: return "ule";
3942     case 010: return "sf";
3943     case 011: return "ngle";
3944     case 012: return "seq";
3945     case 013: return "ngl";
3946     case 014: return "lt";
3947     case 015: return "nge";
3948     case 016: return "le";
3949     case 017: return "ngt";
3950     default: return "?";
3951     }
3952 }
3953
3954
3955 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3956 "abs.%s<FMT> f<FD>, f<FS>"
3957 *mipsI,mipsII,mipsIII,mipsIV:
3958 *vr5000:
3959 // start-sanitize-vr4320
3960 *vr4320:
3961 // end-sanitize-vr4320
3962 // start-sanitize-cygnus
3963 *vr5400:
3964 // end-sanitize-cygnus
3965 *r3900:
3966 // start-sanitize-tx19
3967 *tx19:
3968 // end-sanitize-tx19
3969 {
3970   unsigned32 instruction = instruction_0;
3971   int destreg = ((instruction >> 6) & 0x0000001F);
3972   int fs = ((instruction >> 11) & 0x0000001F);
3973   int format = ((instruction >> 21) & 0x00000007);
3974   {
3975     if ((format != fmt_single) && (format != fmt_double))
3976       SignalException(ReservedInstruction,instruction);
3977     else
3978       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3979   }
3980 }
3981
3982
3983
3984 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3985 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3986 *mipsI,mipsII,mipsIII,mipsIV:
3987 *vr5000:
3988 // start-sanitize-vr4320
3989 *vr4320:
3990 // end-sanitize-vr4320
3991 // start-sanitize-cygnus
3992 *vr5400:
3993 // end-sanitize-cygnus
3994 *r3900:
3995 // start-sanitize-tx19
3996 *tx19:
3997 // end-sanitize-tx19
3998 {
3999   unsigned32 instruction = instruction_0;
4000   int destreg = ((instruction >> 6) & 0x0000001F);
4001   int fs = ((instruction >> 11) & 0x0000001F);
4002   int ft = ((instruction >> 16) & 0x0000001F);
4003   int format = ((instruction >> 21) & 0x00000007);
4004   {
4005     if ((format != fmt_single) && (format != fmt_double))
4006       SignalException(ReservedInstruction, instruction);
4007     else
4008       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
4009   }
4010 }
4011
4012
4013
4014 // BC1F
4015 // BC1FL
4016 // BC1T
4017 // BC1TL
4018
4019 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4020 "bc1%s<TF>%s<ND> <OFFSET>"
4021 *mipsI,mipsII,mipsIII:
4022 // start-sanitize-r5900
4023 *r5900:
4024 // end-sanitize-r5900
4025 {
4026   check_branch_bug ();
4027   TRACE_BRANCH_INPUT (PREVCOC1());
4028   if (PREVCOC1() == TF)
4029     {
4030       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4031       TRACE_BRANCH_RESULT (dest);
4032       mark_branch_bug (dest);
4033       DELAY_SLOT (dest);
4034     }
4035   else if (ND)
4036     {
4037       TRACE_BRANCH_RESULT (0);
4038       NULLIFY_NEXT_INSTRUCTION ();
4039     }
4040   else
4041     {
4042       TRACE_BRANCH_RESULT (NIA);
4043     }
4044 }
4045
4046 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4047 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4048 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4049 *mipsIV:
4050 *vr5000:
4051 // start-sanitize-vr4320
4052 *vr4320:
4053 // end-sanitize-vr4320
4054 // start-sanitize-cygnus
4055 *vr5400:
4056 // end-sanitize-cygnus
4057 *r3900:
4058 // start-sanitize-tx19
4059 *tx19:
4060 // end-sanitize-tx19
4061 {
4062   check_branch_bug ();
4063   if (GETFCC(CC) == TF)
4064     {
4065       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4066       mark_branch_bug (dest);
4067       DELAY_SLOT (dest);
4068     }
4069   else if (ND)
4070     {
4071       NULLIFY_NEXT_INSTRUCTION ();
4072     }
4073 }
4074
4075
4076
4077
4078
4079
4080 // C.EQ.S
4081 // C.EQ.D
4082 // ...
4083
4084 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4085 {
4086   if ((fmt != fmt_single) && (fmt != fmt_double))
4087     SignalException (ReservedInstruction, insn);
4088   else
4089     {
4090       int less;
4091       int equal;
4092       int unordered;
4093       int condition;
4094       unsigned64 ofs = ValueFPR (fs, fmt);
4095       unsigned64 oft = ValueFPR (ft, fmt);
4096       if (NaN (ofs, fmt) || NaN (oft, fmt))
4097         {
4098           if (FCSR & FP_ENABLE (IO))
4099             {
4100               FCSR |= FP_CAUSE (IO);
4101               SignalExceptionFPE ();
4102             }
4103           less = 0;
4104           equal = 0;
4105           unordered = 1;
4106         }
4107       else
4108         {
4109           less = Less (ofs, oft, fmt);
4110           equal = Equal (ofs, oft, fmt);
4111           unordered = 0;
4112         }
4113       condition = (((cond & (1 << 2)) && less)
4114                    || ((cond & (1 << 1)) && equal)
4115                    || ((cond & (1 << 0)) && unordered));
4116       SETFCC (cc, condition);
4117     }
4118 }
4119
4120 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4121 *mipsI,mipsII,mipsIII:
4122 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4123 {
4124   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4125 }
4126
4127 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4128 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4129 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4130 *mipsIV:
4131 *vr5000:
4132 // start-sanitize-vr4320
4133 *vr4320:
4134 // end-sanitize-vr4320
4135 // start-sanitize-cygnus
4136 *vr5400:
4137 // end-sanitize-cygnus
4138 *r3900:
4139 // start-sanitize-tx19
4140 *tx19:
4141 // end-sanitize-tx19
4142 {
4143   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4144 }
4145
4146
4147 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4148 "ceil.l.%s<FMT> f<FD>, f<FS>"
4149 *mipsIII:
4150 *mipsIV:
4151 *vr5000:
4152 // start-sanitize-vr4320
4153 *vr4320:
4154 // end-sanitize-vr4320
4155 // start-sanitize-cygnus
4156 *vr5400:
4157 // end-sanitize-cygnus
4158 // start-sanitize-r5900
4159 *r5900:
4160 // end-sanitize-r5900
4161 *r3900:
4162 // start-sanitize-tx19
4163 *tx19:
4164 // end-sanitize-tx19
4165 {
4166   unsigned32 instruction = instruction_0;
4167   int destreg = ((instruction >> 6) & 0x0000001F);
4168   int fs = ((instruction >> 11) & 0x0000001F);
4169   int format = ((instruction >> 21) & 0x00000007);
4170   {
4171     if ((format != fmt_single) && (format != fmt_double))
4172       SignalException(ReservedInstruction,instruction);
4173     else
4174       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4175   }
4176 }
4177
4178
4179 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4180 *mipsII:
4181 *mipsIII:
4182 *mipsIV:
4183 *vr5000:
4184 // start-sanitize-vr4320
4185 *vr4320:
4186 // end-sanitize-vr4320
4187 // start-sanitize-cygnus
4188 *vr5400:
4189 // end-sanitize-cygnus
4190 // start-sanitize-r5900
4191 *r5900:
4192 // end-sanitize-r5900
4193 *r3900:
4194 // start-sanitize-tx19
4195 *tx19:
4196 // end-sanitize-tx19
4197 {
4198   unsigned32 instruction = instruction_0;
4199   int destreg = ((instruction >> 6) & 0x0000001F);
4200   int fs = ((instruction >> 11) & 0x0000001F);
4201   int format = ((instruction >> 21) & 0x00000007);
4202   {
4203   if ((format != fmt_single) && (format != fmt_double))
4204    SignalException(ReservedInstruction,instruction);
4205   else
4206    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4207   }
4208 }
4209
4210
4211 // CFC1
4212 // CTC1
4213 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4214 "c%s<X>c1 r<RT>, f<FS>"
4215 *mipsI:
4216 *mipsII:
4217 *mipsIII:
4218 {
4219   if (X)
4220     {
4221       if (FS == 0)
4222         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4223       else if (FS == 31)
4224         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4225       /* else NOP */
4226       PENDING_FILL(COCIDX,0); /* special case */
4227     }
4228   else
4229     { /* control from */
4230       if (FS == 0)
4231         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4232       else if (FS == 31)
4233         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4234       /* else NOP */
4235     }
4236 }
4237 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4238 "c%s<X>c1 r<RT>, f<FS>"
4239 *mipsIV:
4240 *vr5000:
4241 // start-sanitize-vr4320
4242 *vr4320:
4243 // end-sanitize-vr4320
4244 // start-sanitize-cygnus
4245 *vr5400:
4246 // end-sanitize-cygnus
4247 *r3900:
4248 // start-sanitize-tx19
4249 *tx19:
4250 // end-sanitize-tx19
4251 {
4252   if (X)
4253     {
4254       /* control to */
4255       TRACE_ALU_INPUT1 (GPR[RT]);
4256       if (FS == 0)
4257         {
4258           FCR0 = VL4_8(GPR[RT]);
4259           TRACE_ALU_RESULT (FCR0);
4260         }
4261       else if (FS == 31)
4262         {
4263           FCR31 = VL4_8(GPR[RT]);
4264           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4265           TRACE_ALU_RESULT (FCR31);
4266         }
4267       else
4268         {
4269           TRACE_ALU_RESULT0 ();
4270         }
4271       /* else NOP */
4272     }
4273   else
4274     { /* control from */
4275       if (FS == 0)
4276         {
4277           TRACE_ALU_INPUT1 (FCR0);
4278           GPR[RT] = SIGNEXTEND (FCR0, 32);
4279         }
4280       else if (FS == 31)
4281         {
4282           TRACE_ALU_INPUT1 (FCR31);
4283           GPR[RT] = SIGNEXTEND (FCR31, 32);
4284         }
4285       TRACE_ALU_RESULT (GPR[RT]);
4286       /* else NOP */
4287     }
4288 }
4289
4290
4291 //
4292 // FIXME: Does not correctly differentiate between mips*
4293 //
4294 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4295 "cvt.d.%s<FMT> f<FD>, f<FS>"
4296 *mipsI,mipsII,mipsIII,mipsIV:
4297 *vr5000:
4298 // start-sanitize-vr4320
4299 *vr4320:
4300 // end-sanitize-vr4320
4301 // start-sanitize-cygnus
4302 *vr5400:
4303 // end-sanitize-cygnus
4304 *r3900:
4305 // start-sanitize-tx19
4306 *tx19:
4307 // end-sanitize-tx19
4308 {
4309   unsigned32 instruction = instruction_0;
4310   int destreg = ((instruction >> 6) & 0x0000001F);
4311   int fs = ((instruction >> 11) & 0x0000001F);
4312   int format = ((instruction >> 21) & 0x00000007);
4313   {
4314     if ((format == fmt_double) | 0)
4315       SignalException(ReservedInstruction,instruction);
4316     else
4317       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4318   }
4319 }
4320
4321
4322 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4323 "cvt.l.%s<FMT> f<FD>, f<FS>"
4324 *mipsIII:
4325 *mipsIV:
4326 *vr5000:
4327 // start-sanitize-vr4320
4328 *vr4320:
4329 // end-sanitize-vr4320
4330 // start-sanitize-cygnus
4331 *vr5400:
4332 // end-sanitize-cygnus
4333 *r3900:
4334 // start-sanitize-tx19
4335 *tx19:
4336 // end-sanitize-tx19
4337 {
4338   unsigned32 instruction = instruction_0;
4339   int destreg = ((instruction >> 6) & 0x0000001F);
4340   int fs = ((instruction >> 11) & 0x0000001F);
4341   int format = ((instruction >> 21) & 0x00000007);
4342   {
4343     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4344       SignalException(ReservedInstruction,instruction);
4345     else
4346       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4347   }
4348 }
4349
4350
4351 //
4352 // FIXME: Does not correctly differentiate between mips*
4353 //
4354 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4355 "cvt.s.%s<FMT> f<FD>, f<FS>"
4356 *mipsI,mipsII,mipsIII,mipsIV:
4357 *vr5000:
4358 // start-sanitize-vr4320
4359 *vr4320:
4360 // end-sanitize-vr4320
4361 // start-sanitize-cygnus
4362 *vr5400:
4363 // end-sanitize-cygnus
4364 *r3900:
4365 // start-sanitize-tx19
4366 *tx19:
4367 // end-sanitize-tx19
4368 {
4369   unsigned32 instruction = instruction_0;
4370   int destreg = ((instruction >> 6) & 0x0000001F);
4371   int fs = ((instruction >> 11) & 0x0000001F);
4372   int format = ((instruction >> 21) & 0x00000007);
4373   {
4374     if ((format == fmt_single) | 0)
4375       SignalException(ReservedInstruction,instruction);
4376     else
4377       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4378   }
4379 }
4380
4381
4382 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4383 "cvt.w.%s<FMT> f<FD>, f<FS>"
4384 *mipsI,mipsII,mipsIII,mipsIV:
4385 *vr5000:
4386 // start-sanitize-vr4320
4387 *vr4320:
4388 // end-sanitize-vr4320
4389 // start-sanitize-cygnus
4390 *vr5400:
4391 // end-sanitize-cygnus
4392 *r3900:
4393 // start-sanitize-tx19
4394 *tx19:
4395 // end-sanitize-tx19
4396 {
4397   unsigned32 instruction = instruction_0;
4398   int destreg = ((instruction >> 6) & 0x0000001F);
4399   int fs = ((instruction >> 11) & 0x0000001F);
4400   int format = ((instruction >> 21) & 0x00000007);
4401   {
4402     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4403       SignalException(ReservedInstruction,instruction);
4404     else
4405       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4406   }
4407 }
4408
4409
4410 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4411 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4412 *mipsI,mipsII,mipsIII,mipsIV:
4413 *vr5000:
4414 // start-sanitize-vr4320
4415 *vr4320:
4416 // end-sanitize-vr4320
4417 // start-sanitize-cygnus
4418 *vr5400:
4419 // end-sanitize-cygnus
4420 *r3900:
4421 // start-sanitize-tx19
4422 *tx19:
4423 // end-sanitize-tx19
4424 {
4425   unsigned32 instruction = instruction_0;
4426   int destreg = ((instruction >> 6) & 0x0000001F);
4427   int fs = ((instruction >> 11) & 0x0000001F);
4428   int ft = ((instruction >> 16) & 0x0000001F);
4429   int format = ((instruction >> 21) & 0x00000007);
4430   {
4431     if ((format != fmt_single) && (format != fmt_double))
4432       SignalException(ReservedInstruction,instruction);
4433     else
4434       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4435   }
4436 }
4437
4438
4439 // DMFC1
4440 // DMTC1
4441 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4442 "dm%s<X>c1 r<RT>, f<FS>"
4443 *mipsIII:
4444 {
4445   if (X)
4446     {
4447       if (SizeFGR() == 64)
4448         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4449       else if ((FS & 0x1) == 0)
4450         {
4451           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4452           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4453         }
4454     }
4455   else
4456     {
4457       if (SizeFGR() == 64)
4458         PENDING_FILL(RT,FGR[FS]);
4459       else if ((FS & 0x1) == 0)
4460         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4461       else
4462         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4463     }
4464 }
4465 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4466 "dm%s<X>c1 r<RT>, f<FS>"
4467 *mipsIV:
4468 *vr5000:
4469 // start-sanitize-vr4320
4470 *vr4320:
4471 // end-sanitize-vr4320
4472 // start-sanitize-cygnus
4473 *vr5400:
4474 // end-sanitize-cygnus
4475 // start-sanitize-r5900
4476 *r5900:
4477 // end-sanitize-r5900
4478 *r3900:
4479 // start-sanitize-tx19
4480 *tx19:
4481 // end-sanitize-tx19
4482 {
4483   if (X)
4484     {
4485       if (SizeFGR() == 64)
4486         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4487       else if ((FS & 0x1) == 0)
4488         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4489     }
4490   else
4491     {
4492       if (SizeFGR() == 64)
4493         GPR[RT] = FGR[FS];
4494       else if ((FS & 0x1) == 0)
4495         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4496       else
4497         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4498     }
4499 }
4500
4501
4502 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4503 "floor.l.%s<FMT> f<FD>, f<FS>"
4504 *mipsIII:
4505 *mipsIV:
4506 *vr5000:
4507 // start-sanitize-vr4320
4508 *vr4320:
4509 // end-sanitize-vr4320
4510 // start-sanitize-cygnus
4511 *vr5400:
4512 // end-sanitize-cygnus
4513 // start-sanitize-r5900
4514 *r5900:
4515 // end-sanitize-r5900
4516 *r3900:
4517 // start-sanitize-tx19
4518 *tx19:
4519 // end-sanitize-tx19
4520 {
4521   unsigned32 instruction = instruction_0;
4522   int destreg = ((instruction >> 6) & 0x0000001F);
4523   int fs = ((instruction >> 11) & 0x0000001F);
4524   int format = ((instruction >> 21) & 0x00000007);
4525   {
4526     if ((format != fmt_single) && (format != fmt_double))
4527       SignalException(ReservedInstruction,instruction);
4528     else
4529       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4530   }
4531 }
4532
4533
4534 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4535 "floor.w.%s<FMT> f<FD>, f<FS>"
4536 *mipsII:
4537 *mipsIII:
4538 *mipsIV:
4539 *vr5000:
4540 // start-sanitize-vr4320
4541 *vr4320:
4542 // end-sanitize-vr4320
4543 // start-sanitize-cygnus
4544 *vr5400:
4545 // end-sanitize-cygnus
4546 // start-sanitize-r5900
4547 *r5900:
4548 // end-sanitize-r5900
4549 *r3900:
4550 // start-sanitize-tx19
4551 *tx19:
4552 // end-sanitize-tx19
4553 {
4554   unsigned32 instruction = instruction_0;
4555   int destreg = ((instruction >> 6) & 0x0000001F);
4556   int fs = ((instruction >> 11) & 0x0000001F);
4557   int format = ((instruction >> 21) & 0x00000007);
4558   {
4559     if ((format != fmt_single) && (format != fmt_double))
4560       SignalException(ReservedInstruction,instruction);
4561     else
4562       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4563   }
4564 }
4565
4566
4567 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4568 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4569 *mipsII:
4570 *mipsIII:
4571 *mipsIV:
4572 *vr5000:
4573 // start-sanitize-vr4320
4574 *vr4320:
4575 // end-sanitize-vr4320
4576 // start-sanitize-cygnus
4577 *vr5400:
4578 // end-sanitize-cygnus
4579 *r3900:
4580 // start-sanitize-tx19
4581 *tx19:
4582 // end-sanitize-tx19
4583 {
4584   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4585 }
4586
4587
4588 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4589 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4590 *mipsIV:
4591 *vr5000:
4592 // start-sanitize-vr4320
4593 *vr4320:
4594 // end-sanitize-vr4320
4595 // start-sanitize-cygnus
4596 *vr5400:
4597 // end-sanitize-cygnus
4598 {
4599   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4600 }
4601
4602
4603
4604 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4605 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4606 *mipsI,mipsII,mipsIII,mipsIV:
4607 *vr5000:
4608 // start-sanitize-vr4320
4609 *vr4320:
4610 // end-sanitize-vr4320
4611 // start-sanitize-cygnus
4612 *vr5400:
4613 // end-sanitize-cygnus
4614 // start-sanitize-r5900
4615 *r5900:
4616 // end-sanitize-r5900
4617 *r3900:
4618 // start-sanitize-tx19
4619 *tx19:
4620 // end-sanitize-tx19
4621 {
4622   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4623 }
4624
4625
4626 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4627 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4628 *mipsIV:
4629 *vr5000:
4630 // start-sanitize-vr4320
4631 *vr4320:
4632 // end-sanitize-vr4320
4633 // start-sanitize-cygnus
4634 *vr5400:
4635 // end-sanitize-cygnus
4636 {
4637   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4638 }
4639
4640
4641
4642 //
4643 // FIXME: Not correct for mips*
4644 //
4645 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4646 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4647 *mipsIV:
4648 *vr5000:
4649 // start-sanitize-vr4320
4650 *vr4320:
4651 // end-sanitize-vr4320
4652 // start-sanitize-cygnus
4653 *vr5400:
4654 // end-sanitize-cygnus
4655 {
4656   unsigned32 instruction = instruction_0;
4657   int destreg = ((instruction >> 6) & 0x0000001F);
4658   int fs = ((instruction >> 11) & 0x0000001F);
4659   int ft = ((instruction >> 16) & 0x0000001F);
4660   int fr = ((instruction >> 21) & 0x0000001F);
4661   {
4662     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4663   }
4664 }
4665
4666
4667 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4668 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4669 *mipsIV:
4670 *vr5000:
4671 // start-sanitize-vr4320
4672 *vr4320:
4673 // end-sanitize-vr4320
4674 // start-sanitize-cygnus
4675 *vr5400:
4676 // end-sanitize-cygnus
4677 {
4678   unsigned32 instruction = instruction_0;
4679   int destreg = ((instruction >> 6) & 0x0000001F);
4680   int fs = ((instruction >> 11) & 0x0000001F);
4681   int ft = ((instruction >> 16) & 0x0000001F);
4682   int fr = ((instruction >> 21) & 0x0000001F);
4683   {
4684     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4685   }
4686 }
4687
4688
4689 // MFC1
4690 // MTC1
4691 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4692 "m%s<X>c1 r<RT>, f<FS>"
4693 *mipsI:
4694 *mipsII:
4695 *mipsIII:
4696 {
4697   if (X)
4698     { /*MTC1*/
4699       if (SizeFGR() == 64)
4700         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4701       else
4702         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4703     }
4704   else /*MFC1*/
4705     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4706 }
4707 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4708 "m%s<X>c1 r<RT>, f<FS>"
4709 *mipsIV:
4710 *vr5000:
4711 // start-sanitize-vr4320
4712 *vr4320:
4713 // end-sanitize-vr4320
4714 // start-sanitize-cygnus
4715 *vr5400:
4716 // end-sanitize-cygnus
4717 *r3900:
4718 // start-sanitize-tx19
4719 *tx19:
4720 // end-sanitize-tx19
4721 {
4722   if (X)
4723     /*MTC1*/
4724     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4725   else /*MFC1*/
4726     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4727 }
4728
4729
4730 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4731 "mov.%s<FMT> f<FD>, f<FS>"
4732 *mipsI,mipsII,mipsIII,mipsIV:
4733 *vr5000:
4734 // start-sanitize-vr4320
4735 *vr4320:
4736 // end-sanitize-vr4320
4737 // start-sanitize-cygnus
4738 *vr5400:
4739 // end-sanitize-cygnus
4740 *r3900:
4741 // start-sanitize-tx19
4742 *tx19:
4743 // end-sanitize-tx19
4744 {
4745   unsigned32 instruction = instruction_0;
4746   int destreg = ((instruction >> 6) & 0x0000001F);
4747   int fs = ((instruction >> 11) & 0x0000001F);
4748   int format = ((instruction >> 21) & 0x00000007);
4749   {
4750     StoreFPR(destreg,format,ValueFPR(fs,format));
4751   }
4752 }
4753
4754
4755 // MOVF
4756 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4757 "mov%s<TF> r<RD>, r<RS>, <CC>"
4758 *mipsIV:
4759 *vr5000:
4760 // start-sanitize-vr4320
4761 *vr4320:
4762 // end-sanitize-vr4320
4763 // start-sanitize-cygnus
4764 *vr5400:
4765 // end-sanitize-cygnus
4766 // start-sanitize-r5900
4767 *r5900:
4768 // end-sanitize-r5900
4769 {
4770   if (GETFCC(CC) == TF)
4771     GPR[RD] = GPR[RS];
4772 }
4773
4774
4775 // MOVF.fmt
4776 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4777 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4778 *mipsIV:
4779 *vr5000:
4780 // start-sanitize-vr4320
4781 *vr4320:
4782 // end-sanitize-vr4320
4783 // start-sanitize-cygnus
4784 *vr5400:
4785 // end-sanitize-cygnus
4786 // start-sanitize-r5900
4787 *r5900:
4788 // end-sanitize-r5900
4789 {
4790   unsigned32 instruction = instruction_0;
4791   int format = ((instruction >> 21) & 0x00000007);
4792   {
4793    if (GETFCC(CC) == TF)
4794      StoreFPR (FD, format, ValueFPR (FS, format));
4795    else
4796      StoreFPR (FD, format, ValueFPR (FD, format));
4797   }
4798 }
4799
4800
4801 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4802 *mipsIV:
4803 *vr5000:
4804 // start-sanitize-vr4320
4805 *vr4320:
4806 // end-sanitize-vr4320
4807 // start-sanitize-cygnus
4808 *vr5400:
4809 // end-sanitize-cygnus
4810 // start-sanitize-r5900
4811 *r5900:
4812 // end-sanitize-r5900
4813 {
4814   unsigned32 instruction = instruction_0;
4815   int destreg = ((instruction >> 6) & 0x0000001F);
4816   int fs = ((instruction >> 11) & 0x0000001F);
4817   int format = ((instruction >> 21) & 0x00000007);
4818   {
4819     StoreFPR(destreg,format,ValueFPR(fs,format));
4820   }
4821 }
4822
4823
4824 // MOVT see MOVtf
4825
4826
4827 // MOVT.fmt see MOVtf.fmt
4828
4829
4830
4831 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4832 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4833 *mipsIV:
4834 *vr5000:
4835 // start-sanitize-vr4320
4836 *vr4320:
4837 // end-sanitize-vr4320
4838 // start-sanitize-cygnus
4839 *vr5400:
4840 // end-sanitize-cygnus
4841 // start-sanitize-r5900
4842 *r5900:
4843 // end-sanitize-r5900
4844 {
4845   unsigned32 instruction = instruction_0;
4846   int destreg = ((instruction >> 6) & 0x0000001F);
4847   int fs = ((instruction >> 11) & 0x0000001F);
4848   int format = ((instruction >> 21) & 0x00000007);
4849   {
4850    StoreFPR(destreg,format,ValueFPR(fs,format));
4851   }
4852 }
4853
4854
4855 // MSUB.fmt
4856 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4857 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4858 *mipsIV:
4859 *vr5000:
4860 // start-sanitize-vr4320
4861 *vr4320:
4862 // end-sanitize-vr4320
4863 // start-sanitize-cygnus
4864 *vr5400:
4865 // end-sanitize-cygnus
4866 // start-sanitize-r5900
4867 *r5900:
4868 // end-sanitize-r5900
4869 {
4870   unsigned32 instruction = instruction_0;
4871   int destreg = ((instruction >> 6) & 0x0000001F);
4872   int fs = ((instruction >> 11) & 0x0000001F);
4873   int ft = ((instruction >> 16) & 0x0000001F);
4874   int fr = ((instruction >> 21) & 0x0000001F);
4875   {
4876     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4877   }
4878 }
4879
4880
4881 // MSUB.fmt
4882 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4883 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4884 *mipsIV:
4885 *vr5000:
4886 // start-sanitize-vr4320
4887 *vr4320:
4888 // end-sanitize-vr4320
4889 // start-sanitize-cygnus
4890 *vr5400:
4891 // end-sanitize-cygnus
4892 // start-sanitize-r5900
4893 *r5900:
4894 // end-sanitize-r5900
4895 {
4896   unsigned32 instruction = instruction_0;
4897   int destreg = ((instruction >> 6) & 0x0000001F);
4898   int fs = ((instruction >> 11) & 0x0000001F);
4899   int ft = ((instruction >> 16) & 0x0000001F);
4900   int fr = ((instruction >> 21) & 0x0000001F);
4901   {
4902    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4903   }
4904 }
4905
4906
4907 // MTC1 see MxC1
4908
4909
4910 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4911 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4912 *mipsI,mipsII,mipsIII,mipsIV:
4913 *vr5000:
4914 // start-sanitize-vr4320
4915 *vr4320:
4916 // end-sanitize-vr4320
4917 // start-sanitize-cygnus
4918 *vr5400:
4919 // end-sanitize-cygnus
4920 *r3900:
4921 // start-sanitize-tx19
4922 *tx19:
4923 // end-sanitize-tx19
4924 {
4925   unsigned32 instruction = instruction_0;
4926   int destreg = ((instruction >> 6) & 0x0000001F);
4927   int fs = ((instruction >> 11) & 0x0000001F);
4928   int ft = ((instruction >> 16) & 0x0000001F);
4929   int format = ((instruction >> 21) & 0x00000007);
4930   {
4931     if ((format != fmt_single) && (format != fmt_double))
4932       SignalException(ReservedInstruction,instruction);
4933     else
4934       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4935   }
4936 }
4937
4938
4939 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4940 "neg.%s<FMT> f<FD>, f<FS>"
4941 *mipsI,mipsII,mipsIII,mipsIV:
4942 *vr5000:
4943 // start-sanitize-vr4320
4944 *vr4320:
4945 // end-sanitize-vr4320
4946 // start-sanitize-cygnus
4947 *vr5400:
4948 // end-sanitize-cygnus
4949 *r3900:
4950 // start-sanitize-tx19
4951 *tx19:
4952 // end-sanitize-tx19
4953 {
4954   unsigned32 instruction = instruction_0;
4955   int destreg = ((instruction >> 6) & 0x0000001F);
4956   int fs = ((instruction >> 11) & 0x0000001F);
4957   int format = ((instruction >> 21) & 0x00000007);
4958   {
4959     if ((format != fmt_single) && (format != fmt_double))
4960       SignalException(ReservedInstruction,instruction);
4961     else
4962       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4963   }
4964 }
4965
4966
4967 // NMADD.fmt
4968 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4969 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4970 *mipsIV:
4971 *vr5000:
4972 // start-sanitize-vr4320
4973 *vr4320:
4974 // end-sanitize-vr4320
4975 // start-sanitize-cygnus
4976 *vr5400:
4977 // end-sanitize-cygnus
4978 {
4979   unsigned32 instruction = instruction_0;
4980   int destreg = ((instruction >> 6) & 0x0000001F);
4981   int fs = ((instruction >> 11) & 0x0000001F);
4982   int ft = ((instruction >> 16) & 0x0000001F);
4983   int fr = ((instruction >> 21) & 0x0000001F);
4984   {
4985    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4986   }
4987 }
4988
4989
4990 // NMADD.fmt
4991 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4992 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4993 *mipsIV:
4994 *vr5000:
4995 // start-sanitize-vr4320
4996 *vr4320:
4997 // end-sanitize-vr4320
4998 // start-sanitize-cygnus
4999 *vr5400:
5000 // end-sanitize-cygnus
5001 {
5002   unsigned32 instruction = instruction_0;
5003   int destreg = ((instruction >> 6) & 0x0000001F);
5004   int fs = ((instruction >> 11) & 0x0000001F);
5005   int ft = ((instruction >> 16) & 0x0000001F);
5006   int fr = ((instruction >> 21) & 0x0000001F);
5007   {
5008    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5009   }
5010 }
5011
5012
5013 // NMSUB.fmt
5014 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5015 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5016 *mipsIV:
5017 *vr5000:
5018 // start-sanitize-vr4320
5019 *vr4320:
5020 // end-sanitize-vr4320
5021 // start-sanitize-cygnus
5022 *vr5400:
5023 // end-sanitize-cygnus
5024 {
5025   unsigned32 instruction = instruction_0;
5026   int destreg = ((instruction >> 6) & 0x0000001F);
5027   int fs = ((instruction >> 11) & 0x0000001F);
5028   int ft = ((instruction >> 16) & 0x0000001F);
5029   int fr = ((instruction >> 21) & 0x0000001F);
5030   {
5031    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5032   }
5033 }
5034
5035
5036 // NMSUB.fmt
5037 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5038 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5039 *mipsIV:
5040 *vr5000:
5041 // start-sanitize-vr4320
5042 *vr4320:
5043 // end-sanitize-vr4320
5044 // start-sanitize-cygnus
5045 *vr5400:
5046 // end-sanitize-cygnus
5047 {
5048   unsigned32 instruction = instruction_0;
5049   int destreg = ((instruction >> 6) & 0x0000001F);
5050   int fs = ((instruction >> 11) & 0x0000001F);
5051   int ft = ((instruction >> 16) & 0x0000001F);
5052   int fr = ((instruction >> 21) & 0x0000001F);
5053   {
5054     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5055   }
5056 }
5057
5058
5059 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5060 "prefx <HINT>, r<INDEX>(r<BASE>)"
5061 *mipsIV:
5062 *vr5000:
5063 // start-sanitize-vr4320
5064 *vr4320:
5065 // end-sanitize-vr4320
5066 // start-sanitize-cygnus
5067 *vr5400:
5068 // end-sanitize-cygnus
5069 {
5070   unsigned32 instruction = instruction_0;
5071   int fs = ((instruction >> 11) & 0x0000001F);
5072   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5073   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5074   {
5075     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5076     address_word paddr;
5077     int uncached;
5078     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5079       Prefetch(uncached,paddr,vaddr,isDATA,fs);
5080   }
5081 }
5082
5083 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5084 *mipsIV:
5085 "recip.%s<FMT> f<FD>, f<FS>"
5086 *vr5000:
5087 // start-sanitize-vr4320
5088 *vr4320:
5089 // end-sanitize-vr4320
5090 // start-sanitize-cygnus
5091 *vr5400:
5092 // end-sanitize-cygnus
5093 {
5094   unsigned32 instruction = instruction_0;
5095   int destreg = ((instruction >> 6) & 0x0000001F);
5096   int fs = ((instruction >> 11) & 0x0000001F);
5097   int format = ((instruction >> 21) & 0x00000007);
5098   {
5099   if ((format != fmt_single) && (format != fmt_double))
5100    SignalException(ReservedInstruction,instruction);
5101   else
5102    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5103   }
5104 }
5105
5106
5107 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5108 "round.l.%s<FMT> f<FD>, f<FS>"
5109 *mipsIII:
5110 *mipsIV:
5111 *vr5000:
5112 // start-sanitize-vr4320
5113 *vr4320:
5114 // end-sanitize-vr4320
5115 // start-sanitize-cygnus
5116 *vr5400:
5117 // end-sanitize-cygnus
5118 // start-sanitize-r5900
5119 *r5900:
5120 // end-sanitize-r5900
5121 *r3900:
5122 // start-sanitize-tx19
5123 *tx19:
5124 // end-sanitize-tx19
5125 {
5126   unsigned32 instruction = instruction_0;
5127   int destreg = ((instruction >> 6) & 0x0000001F);
5128   int fs = ((instruction >> 11) & 0x0000001F);
5129   int format = ((instruction >> 21) & 0x00000007);
5130   {
5131     if ((format != fmt_single) && (format != fmt_double))
5132       SignalException(ReservedInstruction,instruction);
5133     else
5134       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5135   }
5136 }
5137
5138
5139 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5140 "round.w.%s<FMT> f<FD>, f<FS>"
5141 *mipsII:
5142 *mipsIII:
5143 *mipsIV:
5144 *vr5000:
5145 // start-sanitize-vr4320
5146 *vr4320:
5147 // end-sanitize-vr4320
5148 // start-sanitize-cygnus
5149 *vr5400:
5150 // end-sanitize-cygnus
5151 // start-sanitize-r5900
5152 *r5900:
5153 // end-sanitize-r5900
5154 *r3900:
5155 // start-sanitize-tx19
5156 *tx19:
5157 // end-sanitize-tx19
5158 {
5159   unsigned32 instruction = instruction_0;
5160   int destreg = ((instruction >> 6) & 0x0000001F);
5161   int fs = ((instruction >> 11) & 0x0000001F);
5162   int format = ((instruction >> 21) & 0x00000007);
5163   {
5164   if ((format != fmt_single) && (format != fmt_double))
5165    SignalException(ReservedInstruction,instruction);
5166   else
5167    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5168   }
5169 }
5170
5171
5172 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5173 *mipsIV:
5174 "rsqrt.%s<FMT> f<FD>, f<FS>"
5175 *vr5000:
5176 // start-sanitize-vr4320
5177 *vr4320:
5178 // end-sanitize-vr4320
5179 // start-sanitize-cygnus
5180 *vr5400:
5181 // end-sanitize-cygnus
5182 {
5183   unsigned32 instruction = instruction_0;
5184   int destreg = ((instruction >> 6) & 0x0000001F);
5185   int fs = ((instruction >> 11) & 0x0000001F);
5186   int format = ((instruction >> 21) & 0x00000007);
5187   {
5188   if ((format != fmt_single) && (format != fmt_double))
5189    SignalException(ReservedInstruction,instruction);
5190   else
5191    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5192   }
5193 }
5194
5195
5196 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5197 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5198 *mipsII:
5199 *mipsIII:
5200 *mipsIV:
5201 *vr5000:
5202 // start-sanitize-vr4320
5203 *vr4320:
5204 // end-sanitize-vr4320
5205 // start-sanitize-cygnus
5206 *vr5400:
5207 // end-sanitize-cygnus
5208 *r3900:
5209 // start-sanitize-tx19
5210 *tx19:
5211 // end-sanitize-tx19
5212 {
5213   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5214 }
5215
5216
5217 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5218 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5219 *mipsIV:
5220 *vr5000:
5221 // start-sanitize-vr4320
5222 *vr4320:
5223 // end-sanitize-vr4320
5224 // start-sanitize-cygnus
5225 *vr5400:
5226 // end-sanitize-cygnus
5227 {
5228   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5229 }
5230
5231
5232 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5233 "sqrt.%s<FMT> f<FD>, f<FS>"
5234 *mipsII:
5235 *mipsIII:
5236 *mipsIV:
5237 *vr5000:
5238 // start-sanitize-vr4320
5239 *vr4320:
5240 // end-sanitize-vr4320
5241 // start-sanitize-cygnus
5242 *vr5400:
5243 // end-sanitize-cygnus
5244 *r3900:
5245 // start-sanitize-tx19
5246 *tx19:
5247 // end-sanitize-tx19
5248 {
5249   unsigned32 instruction = instruction_0;
5250   int destreg = ((instruction >> 6) & 0x0000001F);
5251   int fs = ((instruction >> 11) & 0x0000001F);
5252   int format = ((instruction >> 21) & 0x00000007);
5253   {
5254     if ((format != fmt_single) && (format != fmt_double))
5255       SignalException(ReservedInstruction,instruction);
5256     else
5257       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5258   }
5259 }
5260
5261
5262 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5263 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5264 *mipsI,mipsII,mipsIII,mipsIV:
5265 *vr5000:
5266 // start-sanitize-vr4320
5267 *vr4320:
5268 // end-sanitize-vr4320
5269 // start-sanitize-cygnus
5270 *vr5400:
5271 // end-sanitize-cygnus
5272 *r3900:
5273 // start-sanitize-tx19
5274 *tx19:
5275 // end-sanitize-tx19
5276 {
5277   unsigned32 instruction = instruction_0;
5278   int destreg = ((instruction >> 6) & 0x0000001F);
5279   int fs = ((instruction >> 11) & 0x0000001F);
5280   int ft = ((instruction >> 16) & 0x0000001F);
5281   int format = ((instruction >> 21) & 0x00000007);
5282   {
5283     if ((format != fmt_single) && (format != fmt_double))
5284       SignalException(ReservedInstruction,instruction);
5285     else
5286       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5287   }
5288 }
5289
5290
5291
5292 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5293 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5294 *mipsI,mipsII,mipsIII,mipsIV:
5295 *vr5000:
5296 // start-sanitize-vr4320
5297 *vr4320:
5298 // end-sanitize-vr4320
5299 // start-sanitize-cygnus
5300 *vr5400:
5301 // end-sanitize-cygnus
5302 // start-sanitize-r5900
5303 *r5900:
5304 // end-sanitize-r5900
5305 *r3900:
5306 // start-sanitize-tx19
5307 *tx19:
5308 // end-sanitize-tx19
5309 {
5310   unsigned32 instruction = instruction_0;
5311   signed_word offset = EXTEND16 (OFFSET);
5312   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5313   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5314   {
5315     address_word vaddr = ((uword64)op1 + offset);
5316     address_word paddr;
5317     int uncached;
5318     if ((vaddr & 3) != 0)
5319       SignalExceptionAddressStore();
5320     else
5321       {
5322         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5323           {
5324             uword64 memval = 0;
5325             uword64 memval1 = 0;
5326             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5327             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5328             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5329             unsigned int byte;
5330             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5331             byte = ((vaddr & mask) ^ bigendiancpu);
5332             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5333             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5334           }
5335       }
5336   }
5337 }
5338
5339
5340 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5341 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5342 *mipsIV:
5343 *vr5000:
5344 // start-sanitize-vr4320
5345 *vr4320:
5346 // end-sanitize-vr4320
5347 // start-sanitize-cygnus
5348 *vr5400:
5349 // end-sanitize-cygnus
5350 {
5351   unsigned32 instruction = instruction_0;
5352   int fs = ((instruction >> 11) & 0x0000001F);
5353   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5354   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5355   {
5356    address_word vaddr = ((unsigned64)op1 + op2);
5357    address_word paddr;
5358    int uncached;
5359    if ((vaddr & 3) != 0)
5360     SignalExceptionAddressStore();
5361    else
5362    {
5363     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5364     {
5365      unsigned64 memval = 0;
5366      unsigned64 memval1 = 0;
5367      unsigned64 mask = 0x7;
5368      unsigned int byte;
5369      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5370      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5371      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5372       {
5373        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5374       }
5375     }
5376    }
5377   }
5378 }
5379
5380
5381 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5382 "trunc.l.%s<FMT> f<FD>, f<FS>"
5383 *mipsIII:
5384 *mipsIV:
5385 *vr5000:
5386 // start-sanitize-vr4320
5387 *vr4320:
5388 // end-sanitize-vr4320
5389 // start-sanitize-cygnus
5390 *vr5400:
5391 // end-sanitize-cygnus
5392 // start-sanitize-r5900
5393 *r5900:
5394 // end-sanitize-r5900
5395 *r3900:
5396 // start-sanitize-tx19
5397 *tx19:
5398 // end-sanitize-tx19
5399 {
5400   unsigned32 instruction = instruction_0;
5401   int destreg = ((instruction >> 6) & 0x0000001F);
5402   int fs = ((instruction >> 11) & 0x0000001F);
5403   int format = ((instruction >> 21) & 0x00000007);
5404   {
5405   if ((format != fmt_single) && (format != fmt_double))
5406    SignalException(ReservedInstruction,instruction);
5407   else
5408    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5409   }
5410 }
5411
5412
5413 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5414 "trunc.w.%s<FMT> f<FD>, f<FS>"
5415 *mipsII:
5416 *mipsIII:
5417 *mipsIV:
5418 *vr5000:
5419 // start-sanitize-vr4320
5420 *vr4320:
5421 // end-sanitize-vr4320
5422 // start-sanitize-cygnus
5423 *vr5400:
5424 // end-sanitize-cygnus
5425 // start-sanitize-r5900
5426 *r5900:
5427 // end-sanitize-r5900
5428 *r3900:
5429 // start-sanitize-tx19
5430 *tx19:
5431 // end-sanitize-tx19
5432 {
5433   unsigned32 instruction = instruction_0;
5434   int destreg = ((instruction >> 6) & 0x0000001F);
5435   int fs = ((instruction >> 11) & 0x0000001F);
5436   int format = ((instruction >> 21) & 0x00000007);
5437   {
5438   if ((format != fmt_single) && (format != fmt_double))
5439    SignalException(ReservedInstruction,instruction);
5440   else
5441    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5442   }
5443 }
5444
5445 \f
5446 //
5447 // MIPS Architecture:
5448 //
5449 //        System Control Instruction Set (COP0)
5450 //
5451
5452
5453 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5454 "bc0f <OFFSET>"
5455 *mipsI,mipsII,mipsIII,mipsIV:
5456 *vr5000:
5457 // start-sanitize-vr4320
5458 *vr4320:
5459 // end-sanitize-vr4320
5460 // start-sanitize-cygnus
5461 *vr5400:
5462 // end-sanitize-cygnus
5463
5464
5465 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5466 "bc0fl <OFFSET>"
5467 *mipsI,mipsII,mipsIII,mipsIV:
5468 *vr5000:
5469 // start-sanitize-vr4320
5470 *vr4320:
5471 // end-sanitize-vr4320
5472 // start-sanitize-cygnus
5473 *vr5400:
5474 // end-sanitize-cygnus
5475
5476
5477 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5478 "bc0t <OFFSET>"
5479 *mipsI,mipsII,mipsIII,mipsIV:
5480
5481
5482
5483 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5484 "bc0tl <OFFSET>"
5485 *mipsI,mipsII,mipsIII,mipsIV:
5486 *vr5000:
5487 // start-sanitize-vr4320
5488 *vr4320:
5489 // end-sanitize-vr4320
5490 // start-sanitize-cygnus
5491 *vr5400:
5492 // end-sanitize-cygnus
5493
5494
5495 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5496 *mipsIII:
5497 *mipsIV:
5498 *vr5000:
5499 // start-sanitize-vr4320
5500 *vr4320:
5501 // end-sanitize-vr4320
5502 // start-sanitize-cygnus
5503 *vr5400:
5504 // end-sanitize-cygnus
5505 *r3900:
5506 // start-sanitize-tx19
5507 *tx19:
5508 // end-sanitize-tx19
5509 {
5510   unsigned32 instruction = instruction_0;
5511   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5512   int hint = ((instruction >> 16) & 0x0000001F);
5513   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5514   {
5515     address_word vaddr = (op1 + offset);
5516     address_word paddr;
5517     int uncached;
5518     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5519       CacheOp(hint,vaddr,paddr,instruction);
5520   }
5521 }
5522
5523
5524 010000,10000,000000000000000,111001:COP0:32::DI
5525 "di"
5526 *mipsI,mipsII,mipsIII,mipsIV:
5527 *vr5000:
5528 // start-sanitize-vr4320
5529 *vr4320:
5530 // end-sanitize-vr4320
5531 // start-sanitize-cygnus
5532 *vr5400:
5533 // end-sanitize-cygnus
5534
5535
5536 010000,10000,000000000000000,111000:COP0:32::EI
5537 "ei"
5538 *mipsI,mipsII,mipsIII,mipsIV:
5539 *vr5000:
5540 // start-sanitize-vr4320
5541 *vr4320:
5542 // end-sanitize-vr4320
5543 // start-sanitize-cygnus
5544 *vr5400:
5545 // end-sanitize-cygnus
5546
5547
5548 010000,10000,000000000000000,011000:COP0:32::ERET
5549 "eret"
5550 *mipsIII:
5551 *mipsIV:
5552 *vr5000:
5553 // start-sanitize-vr4320
5554 *vr4320:
5555 // end-sanitize-vr4320
5556 // start-sanitize-cygnus
5557 *vr5400:
5558 // end-sanitize-cygnus
5559 // start-sanitize-r5900
5560 *r5900:
5561 // end-sanitize-r5900
5562 {
5563   if (SR & status_ERL)
5564     {
5565       /* Oops, not yet available */
5566       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5567       NIA = EPC;
5568       SR &= ~status_ERL;
5569     }
5570   else
5571     {
5572       NIA = EPC;
5573       SR &= ~status_EXL;
5574     }
5575 }
5576
5577
5578 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5579 "mfc0 r<RT>, r<RD> # <REGX>"
5580 *mipsI,mipsII,mipsIII,mipsIV:
5581 *r3900:
5582 *vr5000:
5583 // start-sanitize-vr4320
5584 *vr4320:
5585 // end-sanitize-vr4320
5586 // start-sanitize-cygnus
5587 *vr5400:
5588 // end-sanitize-cygnus
5589 // start-sanitize-r5900
5590 *r5900:
5591 // end-sanitize-r5900
5592 {
5593   TRACE_ALU_INPUT0 ();
5594   DecodeCoproc (instruction_0);
5595   TRACE_ALU_RESULT (GPR[RT]);
5596 }
5597
5598 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5599 "mtc0 r<RT>, r<RD> # <REGX>"
5600 *mipsI,mipsII,mipsIII,mipsIV:
5601 // start-sanitize-tx19
5602 *tx19:
5603 // end-sanitize-tx19
5604 *r3900:
5605 // start-sanitize-vr4320
5606 *vr4320:
5607 // end-sanitize-vr4320
5608 *vr5000:
5609 // start-sanitize-cygnus
5610 *vr5400:
5611 // end-sanitize-cygnus
5612 // start-sanitize-r5900
5613 *r5900:
5614 // end-sanitize-r5900
5615 {
5616   DecodeCoproc (instruction_0);
5617 }
5618
5619
5620 010000,10000,000000000000000,010000:COP0:32::RFE
5621 "rfe"
5622 *mipsI,mipsII,mipsIII,mipsIV:
5623 // start-sanitize-tx19
5624 *tx19:
5625 // end-sanitize-tx19
5626 *r3900:
5627 // start-sanitize-vr4320
5628 *vr4320:
5629 // end-sanitize-vr4320
5630 *vr5000:
5631 // start-sanitize-cygnus
5632 *vr5400:
5633 // end-sanitize-cygnus
5634 // start-sanitize-r5900
5635 *r5900:
5636 // end-sanitize-r5900
5637 {
5638   DecodeCoproc (instruction_0);
5639 }
5640
5641
5642 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5643 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5644 *mipsI,mipsII,mipsIII,mipsIV:
5645 // start-sanitize-r5900
5646 *r5900:
5647 // end-sanitize-r5900
5648 *r3900:
5649 // start-sanitize-tx19
5650 *tx19:
5651 // end-sanitize-tx19
5652 {
5653   DecodeCoproc (instruction_0);
5654 }
5655
5656
5657
5658 010000,10000,000000000000000,001000:COP0:32::TLBP
5659 "tlbp"
5660 *mipsI,mipsII,mipsIII,mipsIV:
5661 *vr5000:
5662 // start-sanitize-vr4320
5663 *vr4320:
5664 // end-sanitize-vr4320
5665 // start-sanitize-cygnus
5666 *vr5400:
5667 // end-sanitize-cygnus
5668
5669
5670 010000,10000,000000000000000,000001:COP0:32::TLBR
5671 "tlbr"
5672 *mipsI,mipsII,mipsIII,mipsIV:
5673 *vr5000:
5674 // start-sanitize-vr4320
5675 *vr4320:
5676 // end-sanitize-vr4320
5677 // start-sanitize-cygnus
5678 *vr5400:
5679 // end-sanitize-cygnus
5680
5681
5682 010000,10000,000000000000000,000010:COP0:32::TLBWI
5683 "tlbwi"
5684 *mipsI,mipsII,mipsIII,mipsIV:
5685 *vr5000:
5686 // start-sanitize-vr4320
5687 *vr4320:
5688 // end-sanitize-vr4320
5689 // start-sanitize-cygnus
5690 *vr5400:
5691 // end-sanitize-cygnus
5692
5693
5694 010000,10000,000000000000000,000110:COP0:32::TLBWR
5695 "tlbwr"
5696 *mipsI,mipsII,mipsIII,mipsIV:
5697 *vr5000:
5698 // start-sanitize-vr4320
5699 *vr4320:
5700 // end-sanitize-vr4320
5701 // start-sanitize-cygnus
5702 *vr5400:
5703 // end-sanitize-cygnus
5704
5705 \f
5706 :include:::m16.igen
5707 // start-sanitize-cygnus
5708 :include:64,f::mdmx.igen
5709 // end-sanitize-cygnus
5710 // start-sanitize-r5900
5711 :include::r5900:r5900.igen
5712 // end-sanitize-r5900
5713 :include:::tx.igen
5714 :include:::vr.igen
5715 \f
5716 // start-sanitize-cygnus-never
5717
5718 // // FIXME FIXME FIXME What is this instruction?
5719 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5720 // *mipsI:
5721 // *mipsII:
5722 // *mipsIII:
5723 // *mipsIV:
5724 // // start-sanitize-r5900
5725 // *r5900:
5726 // // end-sanitize-r5900
5727 // *r3900:
5728 // // start-sanitize-tx19
5729 // *tx19:
5730 // // end-sanitize-tx19
5731 // {
5732 //   unsigned32 instruction = instruction_0;
5733 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5734 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5735 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5736 //   {
5737 //     if (CoProcPresent(3))
5738 //       SignalException(CoProcessorUnusable);
5739 //     else
5740 //       SignalException(ReservedInstruction,instruction);
5741 //   }
5742 // }
5743
5744 // end-sanitize-cygnus-never
5745 // start-sanitize-cygnus-never
5746
5747 // // FIXME FIXME FIXME What is this?
5748 // 11100,******,00001:RR:16::SDBBP
5749 // *mips16:
5750 // {
5751 //   unsigned32 instruction = instruction_0;
5752 //   if (have_extendval)
5753 //     SignalException (ReservedInstruction, instruction);
5754 //   {
5755 //     SignalException(DebugBreakPoint,instruction);
5756 //   }
5757 // }
5758
5759 // end-sanitize-cygnus-never
5760 // start-sanitize-cygnus-never
5761
5762 // // FIXME FIXME FIXME What is this?
5763 // 000000,********************,001110:SPECIAL:32::SDBBP
5764 // *r3900:
5765 // {
5766 //   unsigned32 instruction = instruction_0;
5767 //   {
5768 //     SignalException(DebugBreakPoint,instruction);
5769 //   }
5770 // }
5771
5772 // end-sanitize-cygnus-never