4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator
34 :model:::mipsI:mips3000:
35 :model:::mipsII:mips6000:
36 :model:::mipsIII:mips4000:
37 :model:::mipsIV:mips8000:
38 :model:::mips16:mips16:
39 // start-sanitize-r5900
40 :model:::r5900:mips5900:
42 :model:::r3900:mips3900:
43 // start-sanitize-tx19
46 // start-sanitize-vr4320
47 :model:::vr4320:mips4320:
48 // end-sanitize-vr4320
49 // start-sanitize-vr5400
50 :model:::vr5400:mips5400:
52 // end-sanitize-vr5400
53 :model:::vr5000:mips5000:
57 // Pseudo instructions known by IGEN
60 SignalException (ReservedInstruction, 0);
64 // Pseudo instructions known by interp.c
65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
69 SignalException (ReservedInstruction, instruction_0);
76 // Simulate a 32 bit delayslot instruction
79 :function:::address_word:delayslot32:address_word target
81 instruction_word delay_insn;
82 sim_events_slip (SD, 1);
84 CIA = CIA + 4; /* NOTE not mips16 */
85 STATE |= simDELAYSLOT;
86 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
87 idecode_issue (CPU_, delay_insn, (CIA));
88 STATE &= ~simDELAYSLOT;
92 :function:::address_word:nullify_next_insn32:
94 sim_events_slip (SD, 1);
95 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
103 // Check that an access to a HI/LO register meets timing requirements
105 // The following requirements exist:
107 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
108 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
109 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
110 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
113 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
115 if (history->mf.timestamp + 3 > time)
117 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
118 itable[MY_INDEX].name,
120 (long) history->mf.cia);
126 :function:::int:check_mt_hilo:hilo_history *history
127 *mipsI,mipsII,mipsIII,mipsIV:
129 // start-sanitize-vr4320
131 // end-sanitize-vr4320
132 // start-sanitize-vr5400
134 // end-sanitize-vr5400
136 signed64 time = sim_events_time (SD);
137 int ok = check_mf_cycles (SD_, history, time, "MT");
138 history->mt.timestamp = time;
139 history->mt.cia = CIA;
143 :function:::int:check_mt_hilo:hilo_history *history
145 // start-sanitize-tx19
148 // start-sanitize-r5900
150 // end-sanitize-r5900
152 signed64 time = sim_events_time (SD);
153 history->mt.timestamp = time;
154 history->mt.cia = CIA;
159 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
160 *mipsI,mipsII,mipsIII,mipsIV:
162 // start-sanitize-vr4320
164 // end-sanitize-vr4320
165 // start-sanitize-vr5400
167 // end-sanitize-vr5400
169 // start-sanitize-tx19
173 signed64 time = sim_events_time (SD);
176 && peer->mt.timestamp > history->op.timestamp
177 && history->mf.timestamp < history->op.timestamp)
179 /* The peer has been written to since the last OP yet we have
181 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
182 itable[MY_INDEX].name,
184 (long) history->op.cia,
185 (long) peer->mt.cia);
188 history->mf.timestamp = time;
189 history->mf.cia = CIA;
193 // start-sanitize-r5900
194 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
195 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
196 // end-sanitize-r5900
197 // start-sanitize-r5900
199 // end-sanitize-r5900
200 // start-sanitize-r5900
202 /* FIXME: could record the fact that a stall occured if we want */
203 signed64 time = sim_events_time (SD);
204 history->mf.timestamp = time;
205 history->mf.cia = CIA;
208 // end-sanitize-r5900
211 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
212 *mipsI,mipsII,mipsIII,mipsIV:
214 // start-sanitize-vr4320
216 // end-sanitize-vr4320
217 // start-sanitize-vr5400
219 // end-sanitize-vr5400
221 signed64 time = sim_events_time (SD);
222 int ok = (check_mf_cycles (SD_, hi, time, "OP")
223 && check_mf_cycles (SD_, lo, time, "OP"));
224 hi->op.timestamp = time;
225 lo->op.timestamp = time;
231 // The r3900 mult and multu insns _can_ be exectuted immediatly after
233 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
235 // start-sanitize-tx19
238 // start-sanitize-r5900
240 // end-sanitize-r5900
242 /* FIXME: could record the fact that a stall occured if we want */
243 signed64 time = sim_events_time (SD);
244 hi->op.timestamp = time;
245 lo->op.timestamp = time;
252 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
253 *mipsI,mipsII,mipsIII,mipsIV:
255 // start-sanitize-vr4320
257 // end-sanitize-vr4320
258 // start-sanitize-vr5400
260 // end-sanitize-vr5400
262 // start-sanitize-tx19
266 signed64 time = sim_events_time (SD);
267 int ok = (check_mf_cycles (SD_, hi, time, "OP")
268 && check_mf_cycles (SD_, lo, time, "OP"));
269 hi->op.timestamp = time;
270 lo->op.timestamp = time;
277 // start-sanitize-r5900
278 // The r5900 div et.al insns _can_ be exectuted immediatly after
280 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
281 // end-sanitize-r5900
282 // start-sanitize-r5900
284 // end-sanitize-r5900
285 // start-sanitize-r5900
287 /* FIXME: could record the fact that a stall occured if we want */
288 signed64 time = sim_events_time (SD);
289 hi->op.timestamp = time;
290 lo->op.timestamp = time;
295 // end-sanitize-r5900
300 // Mips Architecture:
302 // CPU Instruction Set (mipsI - mipsIV)
307 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
308 "add r<RD>, r<RS>, r<RT>"
309 *mipsI,mipsII,mipsIII,mipsIV:
311 // start-sanitize-vr4320
313 // end-sanitize-vr4320
314 // start-sanitize-vr5400
316 // end-sanitize-vr5400
317 // start-sanitize-r5900
319 // end-sanitize-r5900
321 // start-sanitize-tx19
325 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
327 ALU32_BEGIN (GPR[RS]);
331 TRACE_ALU_RESULT (GPR[RD]);
336 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
337 "addi r<RT>, r<RS>, IMMEDIATE"
338 *mipsI,mipsII,mipsIII,mipsIV:
340 // start-sanitize-vr4320
342 // end-sanitize-vr4320
343 // start-sanitize-vr5400
345 // end-sanitize-vr5400
346 // start-sanitize-r5900
348 // end-sanitize-r5900
350 // start-sanitize-tx19
354 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
356 ALU32_BEGIN (GPR[RS]);
357 ALU32_ADD (EXTEND16 (IMMEDIATE));
360 TRACE_ALU_RESULT (GPR[RT]);
365 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
367 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
368 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
369 TRACE_ALU_RESULT (GPR[rt]);
372 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
373 "addiu r<RT>, r<RS>, <IMMEDIATE>"
374 *mipsI,mipsII,mipsIII,mipsIV:
376 // start-sanitize-vr4320
378 // end-sanitize-vr4320
379 // start-sanitize-vr5400
381 // end-sanitize-vr5400
382 // start-sanitize-r5900
384 // end-sanitize-r5900
386 // start-sanitize-tx19
390 do_addiu (SD_, RS, RT, IMMEDIATE);
395 :function:::void:do_addu:int rs, int rt, int rd
397 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
398 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
399 TRACE_ALU_RESULT (GPR[rd]);
402 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
403 "addu r<RD>, r<RS>, r<RT>"
404 *mipsI,mipsII,mipsIII,mipsIV:
406 // start-sanitize-vr4320
408 // end-sanitize-vr4320
409 // start-sanitize-vr5400
411 // end-sanitize-vr5400
412 // start-sanitize-r5900
414 // end-sanitize-r5900
416 // start-sanitize-tx19
420 do_addu (SD_, RS, RT, RD);
425 :function:::void:do_and:int rs, int rt, int rd
427 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
428 GPR[rd] = GPR[rs] & GPR[rt];
429 TRACE_ALU_RESULT (GPR[rd]);
432 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
433 "and r<RD>, r<RS>, r<RT>"
434 *mipsI,mipsII,mipsIII,mipsIV:
436 // start-sanitize-vr4320
438 // end-sanitize-vr4320
439 // start-sanitize-vr5400
441 // end-sanitize-vr5400
442 // start-sanitize-r5900
444 // end-sanitize-r5900
446 // start-sanitize-tx19
450 do_and (SD_, RS, RT, RD);
455 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
456 "and r<RT>, r<RS>, <IMMEDIATE>"
457 *mipsI,mipsII,mipsIII,mipsIV:
459 // start-sanitize-vr4320
461 // end-sanitize-vr4320
462 // start-sanitize-vr5400
464 // end-sanitize-vr5400
465 // start-sanitize-r5900
467 // end-sanitize-r5900
469 // start-sanitize-tx19
473 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
474 GPR[RT] = GPR[RS] & IMMEDIATE;
475 TRACE_ALU_RESULT (GPR[RT]);
480 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
481 "beq r<RS>, r<RT>, <OFFSET>"
482 *mipsI,mipsII,mipsIII,mipsIV:
484 // start-sanitize-vr4320
486 // end-sanitize-vr4320
487 // start-sanitize-vr5400
489 // end-sanitize-vr5400
490 // start-sanitize-r5900
492 // end-sanitize-r5900
494 // start-sanitize-tx19
498 address_word offset = EXTEND16 (OFFSET) << 2;
499 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
500 DELAY_SLOT (NIA + offset);
505 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
506 "beql r<RS>, r<RT>, <OFFSET>"
511 // start-sanitize-vr4320
513 // end-sanitize-vr4320
514 // start-sanitize-vr5400
516 // end-sanitize-vr5400
517 // start-sanitize-r5900
519 // end-sanitize-r5900
521 // start-sanitize-tx19
525 address_word offset = EXTEND16 (OFFSET) << 2;
526 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
527 DELAY_SLOT (NIA + offset);
529 NULLIFY_NEXT_INSTRUCTION ();
534 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
535 "bgez r<RS>, <OFFSET>"
536 *mipsI,mipsII,mipsIII,mipsIV:
538 // start-sanitize-vr4320
540 // end-sanitize-vr4320
541 // start-sanitize-vr5400
543 // end-sanitize-vr5400
544 // start-sanitize-r5900
546 // end-sanitize-r5900
548 // start-sanitize-tx19
552 address_word offset = EXTEND16 (OFFSET) << 2;
553 if ((signed_word) GPR[RS] >= 0)
554 DELAY_SLOT (NIA + offset);
559 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
560 "bgezal r<RS>, <OFFSET>"
561 *mipsI,mipsII,mipsIII,mipsIV:
563 // start-sanitize-vr4320
565 // end-sanitize-vr4320
566 // start-sanitize-vr5400
568 // end-sanitize-vr5400
569 // start-sanitize-r5900
571 // end-sanitize-r5900
573 // start-sanitize-tx19
577 address_word offset = EXTEND16 (OFFSET) << 2;
579 if ((signed_word) GPR[RS] >= 0)
580 DELAY_SLOT (NIA + offset);
585 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
586 "bgezall r<RS>, <OFFSET>"
591 // start-sanitize-vr4320
593 // end-sanitize-vr4320
594 // start-sanitize-vr5400
596 // end-sanitize-vr5400
597 // start-sanitize-r5900
599 // end-sanitize-r5900
601 // start-sanitize-tx19
605 address_word offset = EXTEND16 (OFFSET) << 2;
607 /* NOTE: The branch occurs AFTER the next instruction has been
609 if ((signed_word) GPR[RS] >= 0)
610 DELAY_SLOT (NIA + offset);
612 NULLIFY_NEXT_INSTRUCTION ();
617 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
618 "bgezl r<RS>, <OFFSET>"
623 // start-sanitize-vr4320
625 // end-sanitize-vr4320
626 // start-sanitize-vr5400
628 // end-sanitize-vr5400
629 // start-sanitize-r5900
631 // end-sanitize-r5900
633 // start-sanitize-tx19
637 address_word offset = EXTEND16 (OFFSET) << 2;
638 if ((signed_word) GPR[RS] >= 0)
639 DELAY_SLOT (NIA + offset);
641 NULLIFY_NEXT_INSTRUCTION ();
646 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
647 "bgtz r<RS>, <OFFSET>"
648 *mipsI,mipsII,mipsIII,mipsIV:
650 // start-sanitize-vr4320
652 // end-sanitize-vr4320
653 // start-sanitize-vr5400
655 // end-sanitize-vr5400
656 // start-sanitize-r5900
658 // end-sanitize-r5900
660 // start-sanitize-tx19
664 address_word offset = EXTEND16 (OFFSET) << 2;
665 if ((signed_word) GPR[RS] > 0)
666 DELAY_SLOT (NIA + offset);
671 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
672 "bgtzl r<RS>, <OFFSET>"
677 // start-sanitize-vr4320
679 // end-sanitize-vr4320
680 // start-sanitize-vr5400
682 // end-sanitize-vr5400
683 // start-sanitize-r5900
685 // end-sanitize-r5900
687 // start-sanitize-tx19
691 address_word offset = EXTEND16 (OFFSET) << 2;
692 /* NOTE: The branch occurs AFTER the next instruction has been
694 if ((signed_word) GPR[RS] > 0)
695 DELAY_SLOT (NIA + offset);
697 NULLIFY_NEXT_INSTRUCTION ();
702 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
703 "blez r<RS>, <OFFSET>"
704 *mipsI,mipsII,mipsIII,mipsIV:
706 // start-sanitize-vr4320
708 // end-sanitize-vr4320
709 // start-sanitize-vr5400
711 // end-sanitize-vr5400
712 // start-sanitize-r5900
714 // end-sanitize-r5900
716 // start-sanitize-tx19
720 address_word offset = EXTEND16 (OFFSET) << 2;
721 /* NOTE: The branch occurs AFTER the next instruction has been
723 if ((signed_word) GPR[RS] <= 0)
724 DELAY_SLOT (NIA + offset);
729 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
730 "bgezl r<RS>, <OFFSET>"
735 // start-sanitize-vr4320
737 // end-sanitize-vr4320
738 // start-sanitize-vr5400
740 // end-sanitize-vr5400
741 // start-sanitize-r5900
743 // end-sanitize-r5900
745 // start-sanitize-tx19
749 address_word offset = EXTEND16 (OFFSET) << 2;
750 if ((signed_word) GPR[RS] <= 0)
751 DELAY_SLOT (NIA + offset);
753 NULLIFY_NEXT_INSTRUCTION ();
758 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
759 "bltz r<RS>, <OFFSET>"
760 *mipsI,mipsII,mipsIII,mipsIV:
762 // start-sanitize-vr4320
764 // end-sanitize-vr4320
765 // start-sanitize-vr5400
767 // end-sanitize-vr5400
768 // start-sanitize-r5900
770 // end-sanitize-r5900
772 // start-sanitize-tx19
776 address_word offset = EXTEND16 (OFFSET) << 2;
777 if ((signed_word) GPR[RS] < 0)
778 DELAY_SLOT (NIA + offset);
783 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
784 "bltzal r<RS>, <OFFSET>"
785 *mipsI,mipsII,mipsIII,mipsIV:
787 // start-sanitize-vr4320
789 // end-sanitize-vr4320
790 // start-sanitize-vr5400
792 // end-sanitize-vr5400
793 // start-sanitize-r5900
795 // end-sanitize-r5900
797 // start-sanitize-tx19
801 address_word offset = EXTEND16 (OFFSET) << 2;
803 /* NOTE: The branch occurs AFTER the next instruction has been
805 if ((signed_word) GPR[RS] < 0)
806 DELAY_SLOT (NIA + offset);
811 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
812 "bltzall r<RS>, <OFFSET>"
817 // start-sanitize-vr4320
819 // end-sanitize-vr4320
820 // start-sanitize-vr5400
822 // end-sanitize-vr5400
823 // start-sanitize-r5900
825 // end-sanitize-r5900
827 // start-sanitize-tx19
831 address_word offset = EXTEND16 (OFFSET) << 2;
833 if ((signed_word) GPR[RS] < 0)
834 DELAY_SLOT (NIA + offset);
836 NULLIFY_NEXT_INSTRUCTION ();
841 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
842 "bltzl r<RS>, <OFFSET>"
847 // start-sanitize-vr4320
849 // end-sanitize-vr4320
850 // start-sanitize-vr5400
852 // end-sanitize-vr5400
853 // start-sanitize-r5900
855 // end-sanitize-r5900
857 // start-sanitize-tx19
861 address_word offset = EXTEND16 (OFFSET) << 2;
862 /* NOTE: The branch occurs AFTER the next instruction has been
864 if ((signed_word) GPR[RS] < 0)
865 DELAY_SLOT (NIA + offset);
867 NULLIFY_NEXT_INSTRUCTION ();
872 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
873 "bne r<RS>, r<RT>, <OFFSET>"
874 *mipsI,mipsII,mipsIII,mipsIV:
876 // start-sanitize-vr4320
878 // end-sanitize-vr4320
879 // start-sanitize-vr5400
881 // end-sanitize-vr5400
882 // start-sanitize-r5900
884 // end-sanitize-r5900
886 // start-sanitize-tx19
890 address_word offset = EXTEND16 (OFFSET) << 2;
891 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
892 DELAY_SLOT (NIA + offset);
897 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
898 "bnel r<RS>, r<RT>, <OFFSET>"
903 // start-sanitize-vr4320
905 // end-sanitize-vr4320
906 // start-sanitize-vr5400
908 // end-sanitize-vr5400
909 // start-sanitize-r5900
911 // end-sanitize-r5900
913 // start-sanitize-tx19
917 address_word offset = EXTEND16 (OFFSET) << 2;
918 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
919 DELAY_SLOT (NIA + offset);
921 NULLIFY_NEXT_INSTRUCTION ();
926 000000,20.CODE,001101:SPECIAL:32::BREAK
928 *mipsI,mipsII,mipsIII,mipsIV:
930 // start-sanitize-vr4320
932 // end-sanitize-vr4320
933 // start-sanitize-vr5400
935 // end-sanitize-vr5400
936 // start-sanitize-r5900
938 // end-sanitize-r5900
940 // start-sanitize-tx19
944 /* Check for some break instruction which are reserved for use by the simulator. */
945 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
946 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
947 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
949 sim_engine_halt (SD, CPU, NULL, cia,
950 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
952 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
953 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
955 if (STATE & simDELAYSLOT)
956 PC = cia - 4; /* reference the branch instruction */
959 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
961 // start-sanitize-sky
962 else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
964 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
966 else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
968 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
972 /* If we get this far, we're not an instruction reserved by the sim. Raise
974 SignalException(BreakPoint, instruction_0);
979 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
981 *mipsI,mipsII,mipsIII,mipsIV:
982 // start-sanitize-r5900
984 // end-sanitize-r5900
986 // start-sanitize-tx19
990 DecodeCoproc (instruction_0);
995 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
996 "dadd r<RD>, r<RS>, r<RT>"
1000 // start-sanitize-vr4320
1002 // end-sanitize-vr4320
1003 // start-sanitize-vr5400
1005 // end-sanitize-vr5400
1006 // start-sanitize-r5900
1008 // end-sanitize-r5900
1009 // start-sanitize-tx19
1011 // end-sanitize-tx19
1013 /* this check's for overflow */
1014 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1016 ALU64_BEGIN (GPR[RS]);
1017 ALU64_ADD (GPR[RT]);
1018 ALU64_END (GPR[RD]);
1020 TRACE_ALU_RESULT (GPR[RD]);
1025 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1026 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1030 // start-sanitize-vr4320
1032 // end-sanitize-vr4320
1033 // start-sanitize-vr5400
1035 // end-sanitize-vr5400
1036 // start-sanitize-r5900
1038 // end-sanitize-r5900
1039 // start-sanitize-tx19
1041 // end-sanitize-tx19
1043 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1045 ALU64_BEGIN (GPR[RS]);
1046 ALU64_ADD (EXTEND16 (IMMEDIATE));
1047 ALU64_END (GPR[RT]);
1049 TRACE_ALU_RESULT (GPR[RT]);
1054 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1056 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1057 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1058 TRACE_ALU_RESULT (GPR[rt]);
1061 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1062 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1066 // start-sanitize-vr4320
1068 // end-sanitize-vr4320
1069 // start-sanitize-vr5400
1071 // end-sanitize-vr5400
1072 // start-sanitize-r5900
1074 // end-sanitize-r5900
1075 // start-sanitize-tx19
1077 // end-sanitize-tx19
1079 do_daddiu (SD_, RS, RT, IMMEDIATE);
1084 :function:::void:do_daddu:int rs, int rt, int rd
1086 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1087 GPR[rd] = GPR[rs] + GPR[rt];
1088 TRACE_ALU_RESULT (GPR[rd]);
1091 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1092 "daddu r<RD>, r<RS>, r<RT>"
1096 // start-sanitize-vr4320
1098 // end-sanitize-vr4320
1099 // start-sanitize-vr5400
1101 // end-sanitize-vr5400
1102 // start-sanitize-r5900
1104 // end-sanitize-r5900
1105 // start-sanitize-tx19
1107 // end-sanitize-tx19
1109 do_daddu (SD_, RS, RT, RD);
1114 :function:64::void:do_ddiv:int rs, int rt
1116 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1117 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1119 signed64 n = GPR[rs];
1120 signed64 d = GPR[rt];
1123 LO = SIGNED64 (0x8000000000000000);
1126 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1128 LO = SIGNED64 (0x8000000000000000);
1137 TRACE_ALU_RESULT2 (HI, LO);
1140 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1145 // start-sanitize-vr4320
1147 // end-sanitize-vr4320
1148 // start-sanitize-vr5400
1150 // end-sanitize-vr5400
1151 // start-sanitize-r5900
1153 // end-sanitize-r5900
1154 // start-sanitize-tx19
1156 // end-sanitize-tx19
1158 do_ddiv (SD_, RS, RT);
1163 :function:64::void:do_ddivu:int rs, int rt
1165 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1166 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1168 unsigned64 n = GPR[rs];
1169 unsigned64 d = GPR[rt];
1172 LO = SIGNED64 (0x8000000000000000);
1181 TRACE_ALU_RESULT2 (HI, LO);
1184 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1185 "ddivu r<RS>, r<RT>"
1189 // start-sanitize-vr4320
1191 // end-sanitize-vr4320
1192 // start-sanitize-vr5400
1194 // end-sanitize-vr5400
1195 // start-sanitize-tx19
1197 // end-sanitize-tx19
1199 do_ddivu (SD_, RS, RT);
1204 :function:::void:do_div:int rs, int rt
1206 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1207 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1209 signed32 n = GPR[rs];
1210 signed32 d = GPR[rt];
1213 LO = EXTEND32 (0x80000000);
1216 else if (n == SIGNED32 (0x80000000) && d == -1)
1218 LO = EXTEND32 (0x80000000);
1223 LO = EXTEND32 (n / d);
1224 HI = EXTEND32 (n % d);
1227 TRACE_ALU_RESULT2 (HI, LO);
1230 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1232 *mipsI,mipsII,mipsIII,mipsIV:
1234 // start-sanitize-vr4320
1236 // end-sanitize-vr4320
1237 // start-sanitize-vr5400
1239 // end-sanitize-vr5400
1240 // start-sanitize-r5900
1242 // end-sanitize-r5900
1244 // start-sanitize-tx19
1246 // end-sanitize-tx19
1248 do_div (SD_, RS, RT);
1253 :function:::void:do_divu:int rs, int rt
1255 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1256 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1258 unsigned32 n = GPR[rs];
1259 unsigned32 d = GPR[rt];
1262 LO = EXTEND32 (0x80000000);
1267 LO = EXTEND32 (n / d);
1268 HI = EXTEND32 (n % d);
1271 TRACE_ALU_RESULT2 (HI, LO);
1274 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1276 *mipsI,mipsII,mipsIII,mipsIV:
1278 // start-sanitize-vr4320
1280 // end-sanitize-vr4320
1281 // start-sanitize-vr5400
1283 // end-sanitize-vr5400
1284 // start-sanitize-r5900
1286 // end-sanitize-r5900
1288 // start-sanitize-tx19
1290 // end-sanitize-tx19
1292 do_divu (SD_, RS, RT);
1297 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1307 unsigned64 op1 = GPR[rs];
1308 unsigned64 op2 = GPR[rt];
1309 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1310 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1311 /* make signed multiply unsigned */
1326 /* multuply out the 4 sub products */
1327 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1328 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1329 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1330 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1331 /* add the products */
1332 mid = ((unsigned64) VH4_8 (m00)
1333 + (unsigned64) VL4_8 (m10)
1334 + (unsigned64) VL4_8 (m01));
1335 lo = U8_4 (mid, m00);
1337 + (unsigned64) VH4_8 (mid)
1338 + (unsigned64) VH4_8 (m01)
1339 + (unsigned64) VH4_8 (m10));
1349 /* save the result HI/LO (and a gpr) */
1354 TRACE_ALU_RESULT2 (HI, LO);
1357 :function:::void:do_dmult:int rs, int rt, int rd
1359 do_dmultx (SD_, rs, rt, rd, 1);
1362 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1363 "dmult r<RS>, r<RT>"
1365 // start-sanitize-tx19
1367 // end-sanitize-tx19
1368 // start-sanitize-vr4320
1370 // end-sanitize-vr4320
1372 do_dmult (SD_, RS, RT, 0);
1375 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1376 "dmult r<RS>, r<RT>":RD == 0
1377 "dmult r<RD>, r<RS>, r<RT>"
1379 // start-sanitize-vr5400
1381 // end-sanitize-vr5400
1383 do_dmult (SD_, RS, RT, RD);
1388 :function:::void:do_dmultu:int rs, int rt, int rd
1390 do_dmultx (SD_, rs, rt, rd, 0);
1393 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1394 "dmultu r<RS>, r<RT>"
1396 // start-sanitize-tx19
1398 // end-sanitize-tx19
1399 // start-sanitize-vr4320
1401 // end-sanitize-vr4320
1403 do_dmultu (SD_, RS, RT, 0);
1406 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1407 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1408 "dmultu r<RS>, r<RT>"
1410 // start-sanitize-vr5400
1412 // end-sanitize-vr5400
1414 do_dmultu (SD_, RS, RT, RD);
1419 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1420 "dsll r<RD>, r<RT>, <SHIFT>"
1424 // start-sanitize-vr4320
1426 // end-sanitize-vr4320
1427 // start-sanitize-vr5400
1429 // end-sanitize-vr5400
1430 // start-sanitize-r5900
1432 // end-sanitize-r5900
1433 // start-sanitize-tx19
1435 // end-sanitize-tx19
1438 GPR[RD] = GPR[RT] << s;
1442 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1443 "dsll32 r<RD>, r<RT>, <SHIFT>"
1447 // start-sanitize-vr4320
1449 // end-sanitize-vr4320
1450 // start-sanitize-vr5400
1452 // end-sanitize-vr5400
1453 // start-sanitize-r5900
1455 // end-sanitize-r5900
1456 // start-sanitize-tx19
1458 // end-sanitize-tx19
1461 GPR[RD] = GPR[RT] << s;
1466 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1467 "dsllv r<RD>, r<RT>, r<RS>"
1471 // start-sanitize-vr4320
1473 // end-sanitize-vr4320
1474 // start-sanitize-vr5400
1476 // end-sanitize-vr5400
1477 // start-sanitize-r5900
1479 // end-sanitize-r5900
1480 // start-sanitize-tx19
1482 // end-sanitize-tx19
1484 int s = MASKED64 (GPR[RS], 5, 0);
1485 GPR[RD] = GPR[RT] << s;
1490 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1491 "dsra r<RD>, r<RT>, <SHIFT>"
1495 // start-sanitize-vr4320
1497 // end-sanitize-vr4320
1498 // start-sanitize-vr5400
1500 // end-sanitize-vr5400
1501 // start-sanitize-r5900
1503 // end-sanitize-r5900
1504 // start-sanitize-tx19
1506 // end-sanitize-tx19
1509 GPR[RD] = ((signed64) GPR[RT]) >> s;
1513 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1514 "dsra32 r<RT>, r<RD>, <SHIFT>"
1518 // start-sanitize-vr4320
1520 // end-sanitize-vr4320
1521 // start-sanitize-vr5400
1523 // end-sanitize-vr5400
1524 // start-sanitize-r5900
1526 // end-sanitize-r5900
1527 // start-sanitize-tx19
1529 // end-sanitize-tx19
1532 GPR[RD] = ((signed64) GPR[RT]) >> s;
1536 :function:::void:do_dsrav:int rs, int rt, int rd
1538 int s = MASKED64 (GPR[rs], 5, 0);
1539 TRACE_ALU_INPUT2 (GPR[rt], s);
1540 GPR[rd] = ((signed64) GPR[rt]) >> s;
1541 TRACE_ALU_RESULT (GPR[rd]);
1544 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1545 "dsra32 r<RT>, r<RD>, r<RS>"
1549 // start-sanitize-vr4320
1551 // end-sanitize-vr4320
1552 // start-sanitize-vr5400
1554 // end-sanitize-vr5400
1555 // start-sanitize-r5900
1557 // end-sanitize-r5900
1558 // start-sanitize-tx19
1560 // end-sanitize-tx19
1562 do_dsrav (SD_, RS, RT, RD);
1566 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1567 "dsrl r<RD>, r<RT>, <SHIFT>"
1571 // start-sanitize-vr4320
1573 // end-sanitize-vr4320
1574 // start-sanitize-vr5400
1576 // end-sanitize-vr5400
1577 // start-sanitize-r5900
1579 // end-sanitize-r5900
1580 // start-sanitize-tx19
1582 // end-sanitize-tx19
1585 GPR[RD] = (unsigned64) GPR[RT] >> s;
1589 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1590 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1594 // start-sanitize-vr4320
1596 // end-sanitize-vr4320
1597 // start-sanitize-vr5400
1599 // end-sanitize-vr5400
1600 // start-sanitize-r5900
1602 // end-sanitize-r5900
1603 // start-sanitize-tx19
1605 // end-sanitize-tx19
1608 GPR[RD] = (unsigned64) GPR[RT] >> s;
1612 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1613 "dsrl32 r<RD>, r<RT>, r<RS>"
1617 // start-sanitize-vr4320
1619 // end-sanitize-vr4320
1620 // start-sanitize-vr5400
1622 // end-sanitize-vr5400
1623 // start-sanitize-r5900
1625 // end-sanitize-r5900
1626 // start-sanitize-tx19
1628 // end-sanitize-tx19
1630 int s = MASKED64 (GPR[RS], 5, 0);
1631 GPR[RD] = (unsigned64) GPR[RT] >> s;
1635 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1636 "dsub r<RD>, r<RS>, r<RT>"
1640 // start-sanitize-vr4320
1642 // end-sanitize-vr4320
1643 // start-sanitize-vr5400
1645 // end-sanitize-vr5400
1646 // start-sanitize-r5900
1648 // end-sanitize-r5900
1649 // start-sanitize-tx19
1651 // end-sanitize-tx19
1653 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1655 ALU64_BEGIN (GPR[RS]);
1656 ALU64_SUB (GPR[RT]);
1657 ALU64_END (GPR[RD]);
1659 TRACE_ALU_RESULT (GPR[RD]);
1663 :function:::void:do_dsubu:int rs, int rt, int rd
1665 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1666 GPR[rd] = GPR[rs] - GPR[rt];
1667 TRACE_ALU_RESULT (GPR[rd]);
1670 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1671 "dsubu r<RD>, r<RS>, r<RT>"
1675 // start-sanitize-vr4320
1677 // end-sanitize-vr4320
1678 // start-sanitize-vr5400
1680 // end-sanitize-vr5400
1681 // start-sanitize-r5900
1683 // end-sanitize-r5900
1684 // start-sanitize-tx19
1686 // end-sanitize-tx19
1688 do_dsubu (SD_, RS, RT, RD);
1692 000010,26.INSTR_INDEX:NORMAL:32::J
1694 *mipsI,mipsII,mipsIII,mipsIV:
1696 // start-sanitize-vr4320
1698 // end-sanitize-vr4320
1699 // start-sanitize-vr5400
1701 // end-sanitize-vr5400
1702 // start-sanitize-r5900
1704 // end-sanitize-r5900
1706 // start-sanitize-tx19
1708 // end-sanitize-tx19
1710 /* NOTE: The region used is that of the delay slot NIA and NOT the
1711 current instruction */
1712 address_word region = (NIA & MASK (63, 28));
1713 DELAY_SLOT (region | (INSTR_INDEX << 2));
1717 000011,26.INSTR_INDEX:NORMAL:32::JAL
1719 *mipsI,mipsII,mipsIII,mipsIV:
1721 // start-sanitize-vr4320
1723 // end-sanitize-vr4320
1724 // start-sanitize-vr5400
1726 // end-sanitize-vr5400
1727 // start-sanitize-r5900
1729 // end-sanitize-r5900
1731 // start-sanitize-tx19
1733 // end-sanitize-tx19
1735 /* NOTE: The region used is that of the delay slot and NOT the
1736 current instruction */
1737 address_word region = (NIA & MASK (63, 28));
1739 DELAY_SLOT (region | (INSTR_INDEX << 2));
1743 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1744 "jalr r<RS>":RD == 31
1746 *mipsI,mipsII,mipsIII,mipsIV:
1748 // start-sanitize-vr4320
1750 // end-sanitize-vr4320
1751 // start-sanitize-vr5400
1753 // end-sanitize-vr5400
1754 // start-sanitize-r5900
1756 // end-sanitize-r5900
1758 // start-sanitize-tx19
1760 // end-sanitize-tx19
1762 address_word temp = GPR[RS];
1768 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1770 *mipsI,mipsII,mipsIII,mipsIV:
1772 // start-sanitize-vr4320
1774 // end-sanitize-vr4320
1775 // start-sanitize-vr5400
1777 // end-sanitize-vr5400
1778 // start-sanitize-r5900
1780 // end-sanitize-r5900
1782 // start-sanitize-tx19
1784 // end-sanitize-tx19
1786 DELAY_SLOT (GPR[RS]);
1790 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1792 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1793 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1794 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1801 vaddr = base + offset;
1802 if ((vaddr & access) != 0)
1803 SignalExceptionAddressLoad ();
1804 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1805 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1806 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1807 byte = ((vaddr & mask) ^ bigendiancpu);
1808 return (memval >> (8 * byte));
1812 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1813 "lb r<RT>, <OFFSET>(r<BASE>)"
1814 *mipsI,mipsII,mipsIII,mipsIV:
1816 // start-sanitize-vr4320
1818 // end-sanitize-vr4320
1819 // start-sanitize-vr5400
1821 // end-sanitize-vr5400
1822 // start-sanitize-r5900
1824 // end-sanitize-r5900
1826 // start-sanitize-tx19
1828 // end-sanitize-tx19
1830 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1834 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1835 "lbu r<RT>, <OFFSET>(r<BASE>)"
1836 *mipsI,mipsII,mipsIII,mipsIV:
1838 // start-sanitize-vr4320
1840 // end-sanitize-vr4320
1841 // start-sanitize-vr5400
1843 // end-sanitize-vr5400
1844 // start-sanitize-r5900
1846 // end-sanitize-r5900
1848 // start-sanitize-tx19
1850 // end-sanitize-tx19
1852 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1856 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1857 "ld r<RT>, <OFFSET>(r<BASE>)"
1861 // start-sanitize-vr4320
1863 // end-sanitize-vr4320
1864 // start-sanitize-vr5400
1866 // end-sanitize-vr5400
1867 // start-sanitize-r5900
1869 // end-sanitize-r5900
1870 // start-sanitize-tx19
1872 // end-sanitize-tx19
1874 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1878 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1879 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1884 // start-sanitize-vr4320
1886 // end-sanitize-vr4320
1887 // start-sanitize-vr5400
1889 // end-sanitize-vr5400
1891 // start-sanitize-tx19
1893 // end-sanitize-tx19
1895 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1901 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1902 "ldl r<RT>, <OFFSET>(r<BASE>)"
1906 // start-sanitize-vr4320
1908 // end-sanitize-vr4320
1909 // start-sanitize-vr5400
1911 // end-sanitize-vr5400
1912 // start-sanitize-r5900
1914 // end-sanitize-r5900
1915 // start-sanitize-tx19
1917 // end-sanitize-tx19
1919 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1923 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1924 "ldr r<RT>, <OFFSET>(r<BASE>)"
1928 // start-sanitize-vr4320
1930 // end-sanitize-vr4320
1931 // start-sanitize-vr5400
1933 // end-sanitize-vr5400
1934 // start-sanitize-r5900
1936 // end-sanitize-r5900
1937 // start-sanitize-tx19
1939 // end-sanitize-tx19
1941 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1945 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1946 "lh r<RT>, <OFFSET>(r<BASE>)"
1947 *mipsI,mipsII,mipsIII,mipsIV:
1949 // start-sanitize-vr4320
1951 // end-sanitize-vr4320
1952 // start-sanitize-vr5400
1954 // end-sanitize-vr5400
1955 // start-sanitize-r5900
1957 // end-sanitize-r5900
1959 // start-sanitize-tx19
1961 // end-sanitize-tx19
1963 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1967 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1968 "lhu r<RT>, <OFFSET>(r<BASE>)"
1969 *mipsI,mipsII,mipsIII,mipsIV:
1971 // start-sanitize-vr4320
1973 // end-sanitize-vr4320
1974 // start-sanitize-vr5400
1976 // end-sanitize-vr5400
1977 // start-sanitize-r5900
1979 // end-sanitize-r5900
1981 // start-sanitize-tx19
1983 // end-sanitize-tx19
1985 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1989 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1990 "ll r<RT>, <OFFSET>(r<BASE>)"
1995 // start-sanitize-vr4320
1997 // end-sanitize-vr4320
1998 // start-sanitize-vr5400
2000 // end-sanitize-vr5400
2001 // start-sanitize-r5900
2003 // end-sanitize-r5900
2004 // start-sanitize-tx19
2006 // end-sanitize-tx19
2008 unsigned32 instruction = instruction_0;
2009 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2010 int destreg = ((instruction >> 16) & 0x0000001F);
2011 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2013 address_word vaddr = ((unsigned64)op1 + offset);
2016 if ((vaddr & 3) != 0)
2017 SignalExceptionAddressLoad();
2020 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2022 unsigned64 memval = 0;
2023 unsigned64 memval1 = 0;
2024 unsigned64 mask = 0x7;
2025 unsigned int shift = 2;
2026 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2027 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2029 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2030 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2031 byte = ((vaddr & mask) ^ (bigend << shift));
2032 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2040 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2041 "lld r<RT>, <OFFSET>(r<BASE>)"
2045 // start-sanitize-vr4320
2047 // end-sanitize-vr4320
2048 // start-sanitize-vr5400
2050 // end-sanitize-vr5400
2051 // start-sanitize-r5900
2053 // end-sanitize-r5900
2054 // start-sanitize-tx19
2056 // end-sanitize-tx19
2058 unsigned32 instruction = instruction_0;
2059 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2060 int destreg = ((instruction >> 16) & 0x0000001F);
2061 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2063 address_word vaddr = ((unsigned64)op1 + offset);
2066 if ((vaddr & 7) != 0)
2067 SignalExceptionAddressLoad();
2070 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2072 unsigned64 memval = 0;
2073 unsigned64 memval1 = 0;
2074 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2075 GPR[destreg] = memval;
2083 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2084 "lui r<RT>, <IMMEDIATE>"
2085 *mipsI,mipsII,mipsIII,mipsIV:
2087 // start-sanitize-vr4320
2089 // end-sanitize-vr4320
2090 // start-sanitize-vr5400
2092 // end-sanitize-vr5400
2093 // start-sanitize-r5900
2095 // end-sanitize-r5900
2097 // start-sanitize-tx19
2099 // end-sanitize-tx19
2101 TRACE_ALU_INPUT1 (IMMEDIATE);
2102 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2103 TRACE_ALU_RESULT (GPR[RT]);
2107 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2108 "lw r<RT>, <OFFSET>(r<BASE>)"
2109 *mipsI,mipsII,mipsIII,mipsIV:
2111 // start-sanitize-vr4320
2113 // end-sanitize-vr4320
2114 // start-sanitize-vr5400
2116 // end-sanitize-vr5400
2117 // start-sanitize-r5900
2119 // end-sanitize-r5900
2121 // start-sanitize-tx19
2123 // end-sanitize-tx19
2125 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2129 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2130 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2131 *mipsI,mipsII,mipsIII,mipsIV:
2133 // start-sanitize-vr4320
2135 // end-sanitize-vr4320
2136 // start-sanitize-vr5400
2138 // end-sanitize-vr5400
2139 // start-sanitize-r5900
2141 // end-sanitize-r5900
2143 // start-sanitize-tx19
2145 // end-sanitize-tx19
2147 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2151 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2153 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2154 address_word reverseendian = (ReverseEndian ? -1 : 0);
2155 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2164 unsigned_word lhs_mask;
2167 vaddr = base + offset;
2168 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2169 paddr = (paddr ^ (reverseendian & mask));
2170 if (BigEndianMem == 0)
2171 paddr = paddr & ~access;
2173 /* compute where within the word/mem we are */
2174 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2175 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2176 nr_lhs_bits = 8 * byte + 8;
2177 nr_rhs_bits = 8 * access - 8 * byte;
2178 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2180 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2181 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2182 (long) ((unsigned64) paddr >> 32), (long) paddr,
2183 word, byte, nr_lhs_bits, nr_rhs_bits); */
2185 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2188 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2189 temp = (memval << nr_rhs_bits);
2193 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2194 temp = (memval >> nr_lhs_bits);
2196 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2197 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2199 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2200 (long) ((unsigned64) memval >> 32), (long) memval,
2201 (long) ((unsigned64) temp >> 32), (long) temp,
2202 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2203 (long) (rt >> 32), (long) rt); */
2208 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2209 "lwl r<RT>, <OFFSET>(r<BASE>)"
2210 *mipsI,mipsII,mipsIII,mipsIV:
2212 // start-sanitize-vr4320
2214 // end-sanitize-vr4320
2215 // start-sanitize-vr5400
2217 // end-sanitize-vr5400
2218 // start-sanitize-r5900
2220 // end-sanitize-r5900
2222 // start-sanitize-tx19
2224 // end-sanitize-tx19
2226 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2230 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2232 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2233 address_word reverseendian = (ReverseEndian ? -1 : 0);
2234 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2241 vaddr = base + offset;
2242 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2243 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2244 paddr = (paddr ^ (reverseendian & mask));
2245 if (BigEndianMem != 0)
2246 paddr = paddr & ~access;
2247 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2248 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2249 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2250 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2251 (long) paddr, byte, (long) paddr, (long) memval); */
2253 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2255 rt |= (memval >> (8 * byte)) & screen;
2261 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2262 "lwr r<RT>, <OFFSET>(r<BASE>)"
2263 *mipsI,mipsII,mipsIII,mipsIV:
2265 // start-sanitize-vr4320
2267 // end-sanitize-vr4320
2268 // start-sanitize-vr5400
2270 // end-sanitize-vr5400
2271 // start-sanitize-r5900
2273 // end-sanitize-r5900
2275 // start-sanitize-tx19
2277 // end-sanitize-tx19
2279 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2283 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2284 "lwu r<RT>, <OFFSET>(r<BASE>)"
2288 // start-sanitize-vr4320
2290 // end-sanitize-vr4320
2291 // start-sanitize-vr5400
2293 // end-sanitize-vr5400
2294 // start-sanitize-r5900
2296 // end-sanitize-r5900
2297 // start-sanitize-tx19
2299 // end-sanitize-tx19
2301 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2305 :function:::void:do_mfhi:int rd
2307 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2308 TRACE_ALU_INPUT1 (HI);
2310 TRACE_ALU_RESULT (GPR[rd]);
2313 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2315 *mipsI,mipsII,mipsIII,mipsIV:
2317 // start-sanitize-vr4320
2319 // end-sanitize-vr4320
2320 // start-sanitize-vr5400
2322 // end-sanitize-vr5400
2323 // start-sanitize-r5900
2325 // end-sanitize-r5900
2327 // start-sanitize-tx19
2329 // end-sanitize-tx19
2336 :function:::void:do_mflo:int rd
2338 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2339 TRACE_ALU_INPUT1 (LO);
2341 TRACE_ALU_RESULT (GPR[rd]);
2344 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2346 *mipsI,mipsII,mipsIII,mipsIV:
2348 // start-sanitize-vr4320
2350 // end-sanitize-vr4320
2351 // start-sanitize-vr5400
2353 // end-sanitize-vr5400
2354 // start-sanitize-r5900
2356 // end-sanitize-r5900
2358 // start-sanitize-tx19
2360 // end-sanitize-tx19
2367 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2368 "movn r<RD>, r<RS>, r<RT>"
2371 // start-sanitize-vr4320
2373 // end-sanitize-vr4320
2374 // start-sanitize-vr5400
2376 // end-sanitize-vr5400
2377 // start-sanitize-r5900
2379 // end-sanitize-r5900
2387 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2388 "movz r<RD>, r<RS>, r<RT>"
2391 // start-sanitize-vr4320
2393 // end-sanitize-vr4320
2394 // start-sanitize-vr5400
2396 // end-sanitize-vr5400
2397 // start-sanitize-r5900
2399 // end-sanitize-r5900
2407 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2409 *mipsI,mipsII,mipsIII,mipsIV:
2411 // start-sanitize-vr4320
2413 // end-sanitize-vr4320
2414 // start-sanitize-vr5400
2416 // end-sanitize-vr5400
2417 // start-sanitize-r5900
2419 // end-sanitize-r5900
2421 // start-sanitize-tx19
2423 // end-sanitize-tx19
2425 check_mt_hilo (SD_, HIHISTORY);
2431 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2433 *mipsI,mipsII,mipsIII,mipsIV:
2435 // start-sanitize-vr4320
2437 // end-sanitize-vr4320
2438 // start-sanitize-vr5400
2440 // end-sanitize-vr5400
2441 // start-sanitize-r5900
2443 // end-sanitize-r5900
2445 // start-sanitize-tx19
2447 // end-sanitize-tx19
2449 check_mt_hilo (SD_, LOHISTORY);
2455 :function:::void:do_mult:int rs, int rt, int rd
2458 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2459 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2460 prod = (((signed64)(signed32) GPR[rs])
2461 * ((signed64)(signed32) GPR[rt]));
2462 LO = EXTEND32 (VL4_8 (prod));
2463 HI = EXTEND32 (VH4_8 (prod));
2466 TRACE_ALU_RESULT2 (HI, LO);
2469 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2471 *mipsI,mipsII,mipsIII,mipsIV:
2472 // start-sanitize-vr4320
2474 // end-sanitize-vr4320
2476 do_mult (SD_, RS, RT, 0);
2480 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2481 "mult r<RD>, r<RS>, r<RT>"
2483 // start-sanitize-vr5400
2485 // end-sanitize-vr5400
2486 // start-sanitize-r5900
2488 // end-sanitize-r5900
2490 // start-sanitize-tx19
2492 // end-sanitize-tx19
2494 do_mult (SD_, RS, RT, RD);
2498 :function:::void:do_multu:int rs, int rt, int rd
2501 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2502 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2503 prod = (((unsigned64)(unsigned32) GPR[rs])
2504 * ((unsigned64)(unsigned32) GPR[rt]));
2505 LO = EXTEND32 (VL4_8 (prod));
2506 HI = EXTEND32 (VH4_8 (prod));
2509 TRACE_ALU_RESULT2 (HI, LO);
2512 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2513 "multu r<RS>, r<RT>"
2514 *mipsI,mipsII,mipsIII,mipsIV:
2515 // start-sanitize-vr4320
2517 // end-sanitize-vr4320
2519 do_multu (SD_, RS, RT, 0);
2522 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2523 "multu r<RD>, r<RS>, r<RT>"
2525 // start-sanitize-vr5400
2527 // end-sanitize-vr5400
2528 // start-sanitize-r5900
2530 // end-sanitize-r5900
2532 // start-sanitize-tx19
2534 // end-sanitize-tx19
2536 do_multu (SD_, RS, RT, 0);
2540 :function:::void:do_nor:int rs, int rt, int rd
2542 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2543 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2544 TRACE_ALU_RESULT (GPR[rd]);
2547 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2548 "nor r<RD>, r<RS>, r<RT>"
2549 *mipsI,mipsII,mipsIII,mipsIV:
2551 // start-sanitize-vr4320
2553 // end-sanitize-vr4320
2554 // start-sanitize-vr5400
2556 // end-sanitize-vr5400
2557 // start-sanitize-r5900
2559 // end-sanitize-r5900
2561 // start-sanitize-tx19
2563 // end-sanitize-tx19
2565 do_nor (SD_, RS, RT, RD);
2569 :function:::void:do_or:int rs, int rt, int rd
2571 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2572 GPR[rd] = (GPR[rs] | GPR[rt]);
2573 TRACE_ALU_RESULT (GPR[rd]);
2576 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2577 "or r<RD>, r<RS>, r<RT>"
2578 *mipsI,mipsII,mipsIII,mipsIV:
2580 // start-sanitize-vr4320
2582 // end-sanitize-vr4320
2583 // start-sanitize-vr5400
2585 // end-sanitize-vr5400
2586 // start-sanitize-r5900
2588 // end-sanitize-r5900
2590 // start-sanitize-tx19
2592 // end-sanitize-tx19
2594 do_or (SD_, RS, RT, RD);
2599 :function:::void:do_ori:int rs, int rt, unsigned immediate
2601 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2602 GPR[rt] = (GPR[rs] | immediate);
2603 TRACE_ALU_RESULT (GPR[rt]);
2606 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2607 "ori r<RT>, r<RS>, <IMMEDIATE>"
2608 *mipsI,mipsII,mipsIII,mipsIV:
2610 // start-sanitize-vr4320
2612 // end-sanitize-vr4320
2613 // start-sanitize-vr5400
2615 // end-sanitize-vr5400
2616 // start-sanitize-r5900
2618 // end-sanitize-r5900
2620 // start-sanitize-tx19
2622 // end-sanitize-tx19
2624 do_ori (SD_, RS, RT, IMMEDIATE);
2628 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2631 // start-sanitize-vr4320
2633 // end-sanitize-vr4320
2634 // start-sanitize-vr5400
2636 // end-sanitize-vr5400
2637 // start-sanitize-r5900
2639 // end-sanitize-r5900
2641 unsigned32 instruction = instruction_0;
2642 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2643 int hint = ((instruction >> 16) & 0x0000001F);
2644 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2646 address_word vaddr = ((unsigned64)op1 + offset);
2650 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2651 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2656 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2658 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2659 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2660 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2667 vaddr = base + offset;
2668 if ((vaddr & access) != 0)
2669 SignalExceptionAddressStore ();
2670 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2671 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2672 byte = ((vaddr & mask) ^ bigendiancpu);
2673 memval = (word << (8 * byte));
2674 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2678 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2679 "sb r<RT>, <OFFSET>(r<BASE>)"
2680 *mipsI,mipsII,mipsIII,mipsIV:
2682 // start-sanitize-vr4320
2684 // end-sanitize-vr4320
2685 // start-sanitize-vr5400
2687 // end-sanitize-vr5400
2688 // start-sanitize-r5900
2690 // end-sanitize-r5900
2692 // start-sanitize-tx19
2694 // end-sanitize-tx19
2696 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2700 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2701 "sc r<RT>, <OFFSET>(r<BASE>)"
2706 // start-sanitize-vr4320
2708 // end-sanitize-vr4320
2709 // start-sanitize-vr5400
2711 // end-sanitize-vr5400
2712 // start-sanitize-r5900
2714 // end-sanitize-r5900
2715 // start-sanitize-tx19
2717 // end-sanitize-tx19
2719 unsigned32 instruction = instruction_0;
2720 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2721 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2722 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2724 address_word vaddr = ((unsigned64)op1 + offset);
2727 if ((vaddr & 3) != 0)
2728 SignalExceptionAddressStore();
2731 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2733 unsigned64 memval = 0;
2734 unsigned64 memval1 = 0;
2735 unsigned64 mask = 0x7;
2737 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2738 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2739 memval = ((unsigned64) op2 << (8 * byte));
2742 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2744 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2751 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2752 "scd r<RT>, <OFFSET>(r<BASE>)"
2756 // start-sanitize-vr4320
2758 // end-sanitize-vr4320
2759 // start-sanitize-vr5400
2761 // end-sanitize-vr5400
2762 // start-sanitize-r5900
2764 // end-sanitize-r5900
2765 // start-sanitize-tx19
2767 // end-sanitize-tx19
2769 unsigned32 instruction = instruction_0;
2770 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2771 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2772 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2774 address_word vaddr = ((unsigned64)op1 + offset);
2777 if ((vaddr & 7) != 0)
2778 SignalExceptionAddressStore();
2781 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2783 unsigned64 memval = 0;
2784 unsigned64 memval1 = 0;
2788 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2790 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2797 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2798 "sd r<RT>, <OFFSET>(r<BASE>)"
2802 // start-sanitize-vr4320
2804 // end-sanitize-vr4320
2805 // start-sanitize-vr5400
2807 // end-sanitize-vr5400
2808 // start-sanitize-r5900
2810 // end-sanitize-r5900
2811 // start-sanitize-tx19
2813 // end-sanitize-tx19
2815 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2819 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2820 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2825 // start-sanitize-vr4320
2827 // end-sanitize-vr4320
2828 // start-sanitize-vr5400
2830 // end-sanitize-vr5400
2831 // start-sanitize-r5900
2833 // end-sanitize-r5900
2834 // start-sanitize-tx19
2836 // end-sanitize-tx19
2838 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2842 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2843 "sdl r<RT>, <OFFSET>(r<BASE>)"
2847 // start-sanitize-vr4320
2849 // end-sanitize-vr4320
2850 // start-sanitize-vr5400
2852 // end-sanitize-vr5400
2853 // start-sanitize-r5900
2855 // end-sanitize-r5900
2856 // start-sanitize-tx19
2858 // end-sanitize-tx19
2860 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2864 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2865 "sdr r<RT>, <OFFSET>(r<BASE>)"
2869 // start-sanitize-vr4320
2871 // end-sanitize-vr4320
2872 // start-sanitize-vr5400
2874 // end-sanitize-vr5400
2875 // start-sanitize-r5900
2877 // end-sanitize-r5900
2878 // start-sanitize-tx19
2880 // end-sanitize-tx19
2882 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2886 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2887 "sh r<RT>, <OFFSET>(r<BASE>)"
2888 *mipsI,mipsII,mipsIII,mipsIV:
2890 // start-sanitize-vr4320
2892 // end-sanitize-vr4320
2893 // start-sanitize-vr5400
2895 // end-sanitize-vr5400
2896 // start-sanitize-r5900
2898 // end-sanitize-r5900
2900 // start-sanitize-tx19
2902 // end-sanitize-tx19
2904 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2908 :function:::void:do_sll:int rt, int rd, int shift
2910 unsigned32 temp = (GPR[rt] << shift);
2911 TRACE_ALU_INPUT2 (GPR[rt], shift);
2912 GPR[rd] = EXTEND32 (temp);
2913 TRACE_ALU_RESULT (GPR[rd]);
2916 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2917 "sll r<RD>, r<RT>, <SHIFT>"
2918 *mipsI,mipsII,mipsIII,mipsIV:
2920 // start-sanitize-vr4320
2922 // end-sanitize-vr4320
2923 // start-sanitize-vr5400
2925 // end-sanitize-vr5400
2926 // start-sanitize-r5900
2928 // end-sanitize-r5900
2930 // start-sanitize-tx19
2932 // end-sanitize-tx19
2934 do_sll (SD_, RT, RD, SHIFT);
2938 :function:::void:do_sllv:int rs, int rt, int rd
2940 int s = MASKED (GPR[rs], 4, 0);
2941 unsigned32 temp = (GPR[rt] << s);
2942 TRACE_ALU_INPUT2 (GPR[rt], s);
2943 GPR[rd] = EXTEND32 (temp);
2944 TRACE_ALU_RESULT (GPR[rd]);
2947 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2948 "sllv r<RD>, r<RT>, r<RS>"
2949 *mipsI,mipsII,mipsIII,mipsIV:
2951 // start-sanitize-vr4320
2953 // end-sanitize-vr4320
2954 // start-sanitize-vr5400
2956 // end-sanitize-vr5400
2957 // start-sanitize-r5900
2959 // end-sanitize-r5900
2961 // start-sanitize-tx19
2963 // end-sanitize-tx19
2965 do_sllv (SD_, RS, RT, RD);
2969 :function:::void:do_slt:int rs, int rt, int rd
2971 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2972 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2973 TRACE_ALU_RESULT (GPR[rd]);
2976 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2977 "slt r<RD>, r<RS>, r<RT>"
2978 *mipsI,mipsII,mipsIII,mipsIV:
2980 // start-sanitize-vr4320
2982 // end-sanitize-vr4320
2983 // start-sanitize-vr5400
2985 // end-sanitize-vr5400
2986 // start-sanitize-r5900
2988 // end-sanitize-r5900
2990 // start-sanitize-tx19
2992 // end-sanitize-tx19
2994 do_slt (SD_, RS, RT, RD);
2998 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3000 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3001 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3002 TRACE_ALU_RESULT (GPR[rt]);
3005 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3006 "slti r<RT>, r<RS>, <IMMEDIATE>"
3007 *mipsI,mipsII,mipsIII,mipsIV:
3009 // start-sanitize-vr4320
3011 // end-sanitize-vr4320
3012 // start-sanitize-vr5400
3014 // end-sanitize-vr5400
3015 // start-sanitize-r5900
3017 // end-sanitize-r5900
3019 // start-sanitize-tx19
3021 // end-sanitize-tx19
3023 do_slti (SD_, RS, RT, IMMEDIATE);
3027 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3029 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3030 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3031 TRACE_ALU_RESULT (GPR[rt]);
3034 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3035 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3036 *mipsI,mipsII,mipsIII,mipsIV:
3038 // start-sanitize-vr4320
3040 // end-sanitize-vr4320
3041 // start-sanitize-vr5400
3043 // end-sanitize-vr5400
3044 // start-sanitize-r5900
3046 // end-sanitize-r5900
3048 // start-sanitize-tx19
3050 // end-sanitize-tx19
3052 do_sltiu (SD_, RS, RT, IMMEDIATE);
3057 :function:::void:do_sltu:int rs, int rt, int rd
3059 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3060 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3061 TRACE_ALU_RESULT (GPR[rd]);
3064 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3065 "sltu r<RD>, r<RS>, r<RT>"
3066 *mipsI,mipsII,mipsIII,mipsIV:
3068 // start-sanitize-vr4320
3070 // end-sanitize-vr4320
3071 // start-sanitize-vr5400
3073 // end-sanitize-vr5400
3074 // start-sanitize-r5900
3076 // end-sanitize-r5900
3078 // start-sanitize-tx19
3080 // end-sanitize-tx19
3082 do_sltu (SD_, RS, RT, RD);
3086 :function:::void:do_sra:int rt, int rd, int shift
3088 signed32 temp = (signed32) GPR[rt] >> shift;
3089 TRACE_ALU_INPUT2 (GPR[rt], shift);
3090 GPR[rd] = EXTEND32 (temp);
3091 TRACE_ALU_RESULT (GPR[rd]);
3094 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3095 "sra r<RD>, r<RT>, <SHIFT>"
3096 *mipsI,mipsII,mipsIII,mipsIV:
3098 // start-sanitize-vr4320
3100 // end-sanitize-vr4320
3101 // start-sanitize-vr5400
3103 // end-sanitize-vr5400
3104 // start-sanitize-r5900
3106 // end-sanitize-r5900
3108 // start-sanitize-tx19
3110 // end-sanitize-tx19
3112 do_sra (SD_, RT, RD, SHIFT);
3117 :function:::void:do_srav:int rs, int rt, int rd
3119 int s = MASKED (GPR[rs], 4, 0);
3120 signed32 temp = (signed32) GPR[rt] >> s;
3121 TRACE_ALU_INPUT2 (GPR[rt], s);
3122 GPR[rd] = EXTEND32 (temp);
3123 TRACE_ALU_RESULT (GPR[rd]);
3126 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3127 "srav r<RD>, r<RT>, r<RS>"
3128 *mipsI,mipsII,mipsIII,mipsIV:
3130 // start-sanitize-vr4320
3132 // end-sanitize-vr4320
3133 // start-sanitize-vr5400
3135 // end-sanitize-vr5400
3136 // start-sanitize-r5900
3138 // end-sanitize-r5900
3140 // start-sanitize-tx19
3142 // end-sanitize-tx19
3144 do_srav (SD_, RS, RT, RD);
3149 :function:::void:do_srl:int rt, int rd, int shift
3151 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3152 TRACE_ALU_INPUT2 (GPR[rt], shift);
3153 GPR[rd] = EXTEND32 (temp);
3154 TRACE_ALU_RESULT (GPR[rd]);
3157 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3158 "srl r<RD>, r<RT>, <SHIFT>"
3159 *mipsI,mipsII,mipsIII,mipsIV:
3161 // start-sanitize-vr4320
3163 // end-sanitize-vr4320
3164 // start-sanitize-vr5400
3166 // end-sanitize-vr5400
3167 // start-sanitize-r5900
3169 // end-sanitize-r5900
3171 // start-sanitize-tx19
3173 // end-sanitize-tx19
3175 do_srl (SD_, RT, RD, SHIFT);
3179 :function:::void:do_srlv:int rs, int rt, int rd
3181 int s = MASKED (GPR[rs], 4, 0);
3182 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3183 TRACE_ALU_INPUT2 (GPR[rt], s);
3184 GPR[rd] = EXTEND32 (temp);
3185 TRACE_ALU_RESULT (GPR[rd]);
3188 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3189 "srlv r<RD>, r<RT>, r<RS>"
3190 *mipsI,mipsII,mipsIII,mipsIV:
3192 // start-sanitize-vr4320
3194 // end-sanitize-vr4320
3195 // start-sanitize-vr5400
3197 // end-sanitize-vr5400
3198 // start-sanitize-r5900
3200 // end-sanitize-r5900
3202 // start-sanitize-tx19
3204 // end-sanitize-tx19
3206 do_srlv (SD_, RS, RT, RD);
3210 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3211 "sub r<RD>, r<RS>, r<RT>"
3212 *mipsI,mipsII,mipsIII,mipsIV:
3214 // start-sanitize-vr4320
3216 // end-sanitize-vr4320
3217 // start-sanitize-vr5400
3219 // end-sanitize-vr5400
3220 // start-sanitize-r5900
3222 // end-sanitize-r5900
3224 // start-sanitize-tx19
3226 // end-sanitize-tx19
3228 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3230 ALU32_BEGIN (GPR[RS]);
3231 ALU32_SUB (GPR[RT]);
3232 ALU32_END (GPR[RD]);
3234 TRACE_ALU_RESULT (GPR[RD]);
3238 :function:::void:do_subu:int rs, int rt, int rd
3240 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3241 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3242 TRACE_ALU_RESULT (GPR[rd]);
3245 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3246 "subu r<RD>, r<RS>, r<RT>"
3247 *mipsI,mipsII,mipsIII,mipsIV:
3249 // start-sanitize-vr4320
3251 // end-sanitize-vr4320
3252 // start-sanitize-vr5400
3254 // end-sanitize-vr5400
3255 // start-sanitize-r5900
3257 // end-sanitize-r5900
3259 // start-sanitize-tx19
3261 // end-sanitize-tx19
3263 do_subu (SD_, RS, RT, RD);
3267 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3268 "sw r<RT>, <OFFSET>(r<BASE>)"
3269 *mipsI,mipsII,mipsIII,mipsIV:
3270 // start-sanitize-tx19
3272 // end-sanitize-tx19
3274 // start-sanitize-vr4320
3276 // end-sanitize-vr4320
3278 // start-sanitize-vr5400
3280 // end-sanitize-vr5400
3281 // start-sanitize-r5900
3283 // end-sanitize-r5900
3285 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3289 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3290 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3291 *mipsI,mipsII,mipsIII,mipsIV:
3293 // start-sanitize-vr4320
3295 // end-sanitize-vr4320
3296 // start-sanitize-vr5400
3298 // end-sanitize-vr5400
3300 // start-sanitize-tx19
3302 // end-sanitize-tx19
3304 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3309 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3311 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3312 address_word reverseendian = (ReverseEndian ? -1 : 0);
3313 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3323 vaddr = base + offset;
3324 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3325 paddr = (paddr ^ (reverseendian & mask));
3326 if (BigEndianMem == 0)
3327 paddr = paddr & ~access;
3329 /* compute where within the word/mem we are */
3330 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3331 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3332 nr_lhs_bits = 8 * byte + 8;
3333 nr_rhs_bits = 8 * access - 8 * byte;
3334 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3335 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3336 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3337 (long) ((unsigned64) paddr >> 32), (long) paddr,
3338 word, byte, nr_lhs_bits, nr_rhs_bits); */
3342 memval = (rt >> nr_rhs_bits);
3346 memval = (rt << nr_lhs_bits);
3348 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3349 (long) ((unsigned64) rt >> 32), (long) rt,
3350 (long) ((unsigned64) memval >> 32), (long) memval); */
3351 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3355 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3356 "swl r<RT>, <OFFSET>(r<BASE>)"
3357 *mipsI,mipsII,mipsIII,mipsIV:
3359 // start-sanitize-vr4320
3361 // end-sanitize-vr4320
3362 // start-sanitize-vr5400
3364 // end-sanitize-vr5400
3365 // start-sanitize-r5900
3367 // end-sanitize-r5900
3369 // start-sanitize-tx19
3371 // end-sanitize-tx19
3373 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3377 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3379 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3380 address_word reverseendian = (ReverseEndian ? -1 : 0);
3381 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3388 vaddr = base + offset;
3389 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3390 paddr = (paddr ^ (reverseendian & mask));
3391 if (BigEndianMem != 0)
3393 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3394 memval = (rt << (byte * 8));
3395 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3398 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3399 "swr r<RT>, <OFFSET>(r<BASE>)"
3400 *mipsI,mipsII,mipsIII,mipsIV:
3402 // start-sanitize-vr4320
3404 // end-sanitize-vr4320
3405 // start-sanitize-vr5400
3407 // end-sanitize-vr5400
3408 // start-sanitize-r5900
3410 // end-sanitize-r5900
3412 // start-sanitize-tx19
3414 // end-sanitize-tx19
3416 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3420 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3427 // start-sanitize-vr4320
3429 // end-sanitize-vr4320
3430 // start-sanitize-vr5400
3432 // end-sanitize-vr5400
3433 // start-sanitize-r5900
3435 // end-sanitize-r5900
3437 // start-sanitize-tx19
3439 // end-sanitize-tx19
3441 SyncOperation (STYPE);
3445 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3447 *mipsI,mipsII,mipsIII,mipsIV:
3449 // start-sanitize-vr4320
3451 // end-sanitize-vr4320
3452 // start-sanitize-vr5400
3454 // end-sanitize-vr5400
3455 // start-sanitize-r5900
3457 // end-sanitize-r5900
3459 // start-sanitize-tx19
3461 // end-sanitize-tx19
3463 SignalException(SystemCall, instruction_0);
3467 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3473 // start-sanitize-vr4320
3475 // end-sanitize-vr4320
3476 // start-sanitize-vr5400
3478 // end-sanitize-vr5400
3479 // start-sanitize-r5900
3481 // end-sanitize-r5900
3482 // start-sanitize-tx19
3484 // end-sanitize-tx19
3486 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3487 SignalException(Trap, instruction_0);
3491 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3492 "teqi r<RS>, <IMMEDIATE>"
3497 // start-sanitize-vr4320
3499 // end-sanitize-vr4320
3500 // start-sanitize-vr5400
3502 // end-sanitize-vr5400
3503 // start-sanitize-r5900
3505 // end-sanitize-r5900
3506 // start-sanitize-tx19
3508 // end-sanitize-tx19
3510 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3511 SignalException(Trap, instruction_0);
3515 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3521 // start-sanitize-vr4320
3523 // end-sanitize-vr4320
3524 // start-sanitize-vr5400
3526 // end-sanitize-vr5400
3527 // start-sanitize-r5900
3529 // end-sanitize-r5900
3530 // start-sanitize-tx19
3532 // end-sanitize-tx19
3534 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3535 SignalException(Trap, instruction_0);
3539 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3540 "tgei r<RS>, <IMMEDIATE>"
3545 // start-sanitize-vr4320
3547 // end-sanitize-vr4320
3548 // start-sanitize-vr5400
3550 // end-sanitize-vr5400
3551 // start-sanitize-r5900
3553 // end-sanitize-r5900
3554 // start-sanitize-tx19
3556 // end-sanitize-tx19
3558 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3559 SignalException(Trap, instruction_0);
3563 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3564 "tgeiu r<RS>, <IMMEDIATE>"
3569 // start-sanitize-vr4320
3571 // end-sanitize-vr4320
3572 // start-sanitize-vr5400
3574 // end-sanitize-vr5400
3575 // start-sanitize-r5900
3577 // end-sanitize-r5900
3578 // start-sanitize-tx19
3580 // end-sanitize-tx19
3582 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3583 SignalException(Trap, instruction_0);
3587 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3593 // start-sanitize-vr4320
3595 // end-sanitize-vr4320
3596 // start-sanitize-vr5400
3598 // end-sanitize-vr5400
3599 // start-sanitize-r5900
3601 // end-sanitize-r5900
3602 // start-sanitize-tx19
3604 // end-sanitize-tx19
3606 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3607 SignalException(Trap, instruction_0);
3611 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3617 // start-sanitize-vr4320
3619 // end-sanitize-vr4320
3620 // start-sanitize-vr5400
3622 // end-sanitize-vr5400
3623 // start-sanitize-r5900
3625 // end-sanitize-r5900
3626 // start-sanitize-tx19
3628 // end-sanitize-tx19
3630 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3631 SignalException(Trap, instruction_0);
3635 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3636 "tlti r<RS>, <IMMEDIATE>"
3641 // start-sanitize-vr4320
3643 // end-sanitize-vr4320
3644 // start-sanitize-vr5400
3646 // end-sanitize-vr5400
3647 // start-sanitize-r5900
3649 // end-sanitize-r5900
3650 // start-sanitize-tx19
3652 // end-sanitize-tx19
3654 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3655 SignalException(Trap, instruction_0);
3659 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3660 "tltiu r<RS>, <IMMEDIATE>"
3665 // start-sanitize-vr4320
3667 // end-sanitize-vr4320
3668 // start-sanitize-vr5400
3670 // end-sanitize-vr5400
3671 // start-sanitize-r5900
3673 // end-sanitize-r5900
3674 // start-sanitize-tx19
3676 // end-sanitize-tx19
3678 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3679 SignalException(Trap, instruction_0);
3683 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3689 // start-sanitize-vr4320
3691 // end-sanitize-vr4320
3692 // start-sanitize-vr5400
3694 // end-sanitize-vr5400
3695 // start-sanitize-r5900
3697 // end-sanitize-r5900
3698 // start-sanitize-tx19
3700 // end-sanitize-tx19
3702 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3703 SignalException(Trap, instruction_0);
3707 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3713 // start-sanitize-vr4320
3715 // end-sanitize-vr4320
3716 // start-sanitize-vr5400
3718 // end-sanitize-vr5400
3719 // start-sanitize-r5900
3721 // end-sanitize-r5900
3722 // start-sanitize-tx19
3724 // end-sanitize-tx19
3726 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3727 SignalException(Trap, instruction_0);
3731 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3732 "tne r<RS>, <IMMEDIATE>"
3737 // start-sanitize-vr4320
3739 // end-sanitize-vr4320
3740 // start-sanitize-vr5400
3742 // end-sanitize-vr5400
3743 // start-sanitize-r5900
3745 // end-sanitize-r5900
3746 // start-sanitize-tx19
3748 // end-sanitize-tx19
3750 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3751 SignalException(Trap, instruction_0);
3755 :function:::void:do_xor:int rs, int rt, int rd
3757 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3758 GPR[rd] = GPR[rs] ^ GPR[rt];
3759 TRACE_ALU_RESULT (GPR[rd]);
3762 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3763 "xor r<RD>, r<RS>, r<RT>"
3764 *mipsI,mipsII,mipsIII,mipsIV:
3766 // start-sanitize-vr4320
3768 // end-sanitize-vr4320
3769 // start-sanitize-vr5400
3771 // end-sanitize-vr5400
3772 // start-sanitize-r5900
3774 // end-sanitize-r5900
3776 // start-sanitize-tx19
3778 // end-sanitize-tx19
3780 do_xor (SD_, RS, RT, RD);
3784 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3786 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3787 GPR[rt] = GPR[rs] ^ immediate;
3788 TRACE_ALU_RESULT (GPR[rt]);
3791 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3792 "xori r<RT>, r<RS>, <IMMEDIATE>"
3793 *mipsI,mipsII,mipsIII,mipsIV:
3795 // start-sanitize-vr4320
3797 // end-sanitize-vr4320
3798 // start-sanitize-vr5400
3800 // end-sanitize-vr5400
3801 // start-sanitize-r5900
3803 // end-sanitize-r5900
3805 // start-sanitize-tx19
3807 // end-sanitize-tx19
3809 do_xori (SD_, RS, RT, IMMEDIATE);
3814 // MIPS Architecture:
3816 // FPU Instruction Set (COP1 & COP1X)
3824 case fmt_single: return "s";
3825 case fmt_double: return "d";
3826 case fmt_word: return "w";
3827 case fmt_long: return "l";
3828 default: return "?";
3838 default: return "?";
3858 :%s::::COND:int cond
3862 case 00: return "f";
3863 case 01: return "un";
3864 case 02: return "eq";
3865 case 03: return "ueq";
3866 case 04: return "olt";
3867 case 05: return "ult";
3868 case 06: return "ole";
3869 case 07: return "ule";
3870 case 010: return "sf";
3871 case 011: return "ngle";
3872 case 012: return "seq";
3873 case 013: return "ngl";
3874 case 014: return "lt";
3875 case 015: return "nge";
3876 case 016: return "le";
3877 case 017: return "ngt";
3878 default: return "?";
3883 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3884 "abs.%s<FMT> f<FD>, f<FS>"
3885 *mipsI,mipsII,mipsIII,mipsIV:
3887 // start-sanitize-vr4320
3889 // end-sanitize-vr4320
3890 // start-sanitize-vr5400
3892 // end-sanitize-vr5400
3894 // start-sanitize-tx19
3896 // end-sanitize-tx19
3898 unsigned32 instruction = instruction_0;
3899 int destreg = ((instruction >> 6) & 0x0000001F);
3900 int fs = ((instruction >> 11) & 0x0000001F);
3901 int format = ((instruction >> 21) & 0x00000007);
3903 if ((format != fmt_single) && (format != fmt_double))
3904 SignalException(ReservedInstruction,instruction);
3906 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3912 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3913 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3914 *mipsI,mipsII,mipsIII,mipsIV:
3916 // start-sanitize-vr4320
3918 // end-sanitize-vr4320
3919 // start-sanitize-vr5400
3921 // end-sanitize-vr5400
3923 // start-sanitize-tx19
3925 // end-sanitize-tx19
3927 unsigned32 instruction = instruction_0;
3928 int destreg = ((instruction >> 6) & 0x0000001F);
3929 int fs = ((instruction >> 11) & 0x0000001F);
3930 int ft = ((instruction >> 16) & 0x0000001F);
3931 int format = ((instruction >> 21) & 0x00000007);
3933 if ((format != fmt_single) && (format != fmt_double))
3934 SignalException(ReservedInstruction, instruction);
3936 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3947 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3948 "bc1%s<TF>%s<ND> <OFFSET>"
3949 *mipsI,mipsII,mipsIII:
3950 // start-sanitize-r5900
3952 // end-sanitize-r5900
3954 TRACE_BRANCH_INPUT (PREVCOC1());
3955 if (PREVCOC1() == TF)
3957 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3958 TRACE_BRANCH_RESULT (dest);
3963 TRACE_BRANCH_RESULT (0);
3964 NULLIFY_NEXT_INSTRUCTION ();
3968 TRACE_BRANCH_RESULT (NIA);
3972 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3973 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3974 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3977 // start-sanitize-vr4320
3979 // end-sanitize-vr4320
3980 // start-sanitize-vr5400
3982 // end-sanitize-vr5400
3984 // start-sanitize-tx19
3986 // end-sanitize-tx19
3988 if (GETFCC(CC) == TF)
3990 DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3994 NULLIFY_NEXT_INSTRUCTION ();
4004 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4006 if ((fmt != fmt_single) && (fmt != fmt_double))
4007 SignalException (ReservedInstruction, insn);
4014 unsigned64 ofs = ValueFPR (fs, fmt);
4015 unsigned64 oft = ValueFPR (ft, fmt);
4016 if (NaN (ofs, fmt) || NaN (oft, fmt))
4018 if (FCSR & FP_ENABLE (IO))
4020 FCSR |= FP_CAUSE (IO);
4021 SignalExceptionFPE ();
4029 less = Less (ofs, oft, fmt);
4030 equal = Equal (ofs, oft, fmt);
4033 condition = (((cond & (1 << 2)) && less)
4034 || ((cond & (1 << 1)) && equal)
4035 || ((cond & (1 << 0)) && unordered));
4036 SETFCC (cc, condition);
4040 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4041 *mipsI,mipsII,mipsIII:
4042 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
4044 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4047 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4048 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4049 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4052 // start-sanitize-vr4320
4054 // end-sanitize-vr4320
4055 // start-sanitize-vr5400
4057 // end-sanitize-vr5400
4059 // start-sanitize-tx19
4061 // end-sanitize-tx19
4063 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4067 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4068 "ceil.l.%s<FMT> f<FD>, f<FS>"
4072 // start-sanitize-vr4320
4074 // end-sanitize-vr4320
4075 // start-sanitize-vr5400
4077 // end-sanitize-vr5400
4078 // start-sanitize-r5900
4080 // end-sanitize-r5900
4082 // start-sanitize-tx19
4084 // end-sanitize-tx19
4086 unsigned32 instruction = instruction_0;
4087 int destreg = ((instruction >> 6) & 0x0000001F);
4088 int fs = ((instruction >> 11) & 0x0000001F);
4089 int format = ((instruction >> 21) & 0x00000007);
4091 if ((format != fmt_single) && (format != fmt_double))
4092 SignalException(ReservedInstruction,instruction);
4094 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4099 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4104 // start-sanitize-vr4320
4106 // end-sanitize-vr4320
4107 // start-sanitize-vr5400
4109 // end-sanitize-vr5400
4110 // start-sanitize-r5900
4112 // end-sanitize-r5900
4114 // start-sanitize-tx19
4116 // end-sanitize-tx19
4118 unsigned32 instruction = instruction_0;
4119 int destreg = ((instruction >> 6) & 0x0000001F);
4120 int fs = ((instruction >> 11) & 0x0000001F);
4121 int format = ((instruction >> 21) & 0x00000007);
4123 if ((format != fmt_single) && (format != fmt_double))
4124 SignalException(ReservedInstruction,instruction);
4126 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4133 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4134 "c%s<X>c1 r<RT>, f<FS>"
4142 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4144 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4146 PENDING_FILL(COCIDX,0); /* special case */
4149 { /* control from */
4151 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4153 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4157 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4158 "c%s<X>c1 r<RT>, f<FS>"
4161 // start-sanitize-vr4320
4163 // end-sanitize-vr4320
4164 // start-sanitize-vr5400
4166 // end-sanitize-vr5400
4168 // start-sanitize-tx19
4170 // end-sanitize-tx19
4175 TRACE_ALU_INPUT1 (GPR[RT]);
4178 FCR0 = VL4_8(GPR[RT]);
4179 TRACE_ALU_RESULT (FCR0);
4183 FCR31 = VL4_8(GPR[RT]);
4184 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4185 TRACE_ALU_RESULT (FCR31);
4189 TRACE_ALU_RESULT0 ();
4194 { /* control from */
4197 TRACE_ALU_INPUT1 (FCR0);
4198 GPR[RT] = SIGNEXTEND (FCR0, 32);
4202 TRACE_ALU_INPUT1 (FCR31);
4203 GPR[RT] = SIGNEXTEND (FCR31, 32);
4205 TRACE_ALU_RESULT (GPR[RT]);
4212 // FIXME: Does not correctly differentiate between mips*
4214 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4215 "cvt.d.%s<FMT> f<FD>, f<FS>"
4216 *mipsI,mipsII,mipsIII,mipsIV:
4218 // start-sanitize-vr4320
4220 // end-sanitize-vr4320
4221 // start-sanitize-vr5400
4223 // end-sanitize-vr5400
4225 // start-sanitize-tx19
4227 // end-sanitize-tx19
4229 unsigned32 instruction = instruction_0;
4230 int destreg = ((instruction >> 6) & 0x0000001F);
4231 int fs = ((instruction >> 11) & 0x0000001F);
4232 int format = ((instruction >> 21) & 0x00000007);
4234 if ((format == fmt_double) | 0)
4235 SignalException(ReservedInstruction,instruction);
4237 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4242 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4243 "cvt.l.%s<FMT> f<FD>, f<FS>"
4247 // start-sanitize-vr4320
4249 // end-sanitize-vr4320
4250 // start-sanitize-vr5400
4252 // end-sanitize-vr5400
4254 // start-sanitize-tx19
4256 // end-sanitize-tx19
4258 unsigned32 instruction = instruction_0;
4259 int destreg = ((instruction >> 6) & 0x0000001F);
4260 int fs = ((instruction >> 11) & 0x0000001F);
4261 int format = ((instruction >> 21) & 0x00000007);
4263 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4264 SignalException(ReservedInstruction,instruction);
4266 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4272 // FIXME: Does not correctly differentiate between mips*
4274 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4275 "cvt.s.%s<FMT> f<FD>, f<FS>"
4276 *mipsI,mipsII,mipsIII,mipsIV:
4278 // start-sanitize-vr4320
4280 // end-sanitize-vr4320
4281 // start-sanitize-vr5400
4283 // end-sanitize-vr5400
4285 // start-sanitize-tx19
4287 // end-sanitize-tx19
4289 unsigned32 instruction = instruction_0;
4290 int destreg = ((instruction >> 6) & 0x0000001F);
4291 int fs = ((instruction >> 11) & 0x0000001F);
4292 int format = ((instruction >> 21) & 0x00000007);
4294 if ((format == fmt_single) | 0)
4295 SignalException(ReservedInstruction,instruction);
4297 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4302 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4303 "cvt.w.%s<FMT> f<FD>, f<FS>"
4304 *mipsI,mipsII,mipsIII,mipsIV:
4306 // start-sanitize-vr4320
4308 // end-sanitize-vr4320
4309 // start-sanitize-vr5400
4311 // end-sanitize-vr5400
4313 // start-sanitize-tx19
4315 // end-sanitize-tx19
4317 unsigned32 instruction = instruction_0;
4318 int destreg = ((instruction >> 6) & 0x0000001F);
4319 int fs = ((instruction >> 11) & 0x0000001F);
4320 int format = ((instruction >> 21) & 0x00000007);
4322 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4323 SignalException(ReservedInstruction,instruction);
4325 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4330 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4331 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4332 *mipsI,mipsII,mipsIII,mipsIV:
4334 // start-sanitize-vr4320
4336 // end-sanitize-vr4320
4337 // start-sanitize-vr5400
4339 // end-sanitize-vr5400
4341 // start-sanitize-tx19
4343 // end-sanitize-tx19
4345 unsigned32 instruction = instruction_0;
4346 int destreg = ((instruction >> 6) & 0x0000001F);
4347 int fs = ((instruction >> 11) & 0x0000001F);
4348 int ft = ((instruction >> 16) & 0x0000001F);
4349 int format = ((instruction >> 21) & 0x00000007);
4351 if ((format != fmt_single) && (format != fmt_double))
4352 SignalException(ReservedInstruction,instruction);
4354 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4361 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4362 "dm%s<X>c1 r<RT>, f<FS>"
4367 if (SizeFGR() == 64)
4368 PENDING_FILL((FS + FGRIDX),GPR[RT]);
4369 else if ((FS & 0x1) == 0)
4371 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4372 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4377 if (SizeFGR() == 64)
4378 PENDING_FILL(RT,FGR[FS]);
4379 else if ((FS & 0x1) == 0)
4380 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4382 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4385 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4386 "dm%s<X>c1 r<RT>, f<FS>"
4389 // start-sanitize-vr4320
4391 // end-sanitize-vr4320
4392 // start-sanitize-vr5400
4394 // end-sanitize-vr5400
4395 // start-sanitize-r5900
4397 // end-sanitize-r5900
4399 // start-sanitize-tx19
4401 // end-sanitize-tx19
4405 if (SizeFGR() == 64)
4406 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4407 else if ((FS & 0x1) == 0)
4408 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4412 if (SizeFGR() == 64)
4414 else if ((FS & 0x1) == 0)
4415 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4417 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4422 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4423 "floor.l.%s<FMT> f<FD>, f<FS>"
4427 // start-sanitize-vr4320
4429 // end-sanitize-vr4320
4430 // start-sanitize-vr5400
4432 // end-sanitize-vr5400
4433 // start-sanitize-r5900
4435 // end-sanitize-r5900
4437 // start-sanitize-tx19
4439 // end-sanitize-tx19
4441 unsigned32 instruction = instruction_0;
4442 int destreg = ((instruction >> 6) & 0x0000001F);
4443 int fs = ((instruction >> 11) & 0x0000001F);
4444 int format = ((instruction >> 21) & 0x00000007);
4446 if ((format != fmt_single) && (format != fmt_double))
4447 SignalException(ReservedInstruction,instruction);
4449 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4454 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4455 "floor.w.%s<FMT> f<FD>, f<FS>"
4460 // start-sanitize-vr4320
4462 // end-sanitize-vr4320
4463 // start-sanitize-vr5400
4465 // end-sanitize-vr5400
4466 // start-sanitize-r5900
4468 // end-sanitize-r5900
4470 // start-sanitize-tx19
4472 // end-sanitize-tx19
4474 unsigned32 instruction = instruction_0;
4475 int destreg = ((instruction >> 6) & 0x0000001F);
4476 int fs = ((instruction >> 11) & 0x0000001F);
4477 int format = ((instruction >> 21) & 0x00000007);
4479 if ((format != fmt_single) && (format != fmt_double))
4480 SignalException(ReservedInstruction,instruction);
4482 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4487 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4488 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4493 // start-sanitize-vr4320
4495 // end-sanitize-vr4320
4496 // start-sanitize-vr5400
4498 // end-sanitize-vr5400
4500 // start-sanitize-tx19
4502 // end-sanitize-tx19
4504 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4508 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4509 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4512 // start-sanitize-vr4320
4514 // end-sanitize-vr4320
4515 // start-sanitize-vr5400
4517 // end-sanitize-vr5400
4519 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4524 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4525 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4526 *mipsI,mipsII,mipsIII,mipsIV:
4528 // start-sanitize-vr4320
4530 // end-sanitize-vr4320
4531 // start-sanitize-vr5400
4533 // end-sanitize-vr5400
4534 // start-sanitize-r5900
4536 // end-sanitize-r5900
4538 // start-sanitize-tx19
4540 // end-sanitize-tx19
4542 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4546 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4547 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4550 // start-sanitize-vr4320
4552 // end-sanitize-vr4320
4553 // start-sanitize-vr5400
4555 // end-sanitize-vr5400
4557 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4563 // FIXME: Not correct for mips*
4565 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4566 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4569 // start-sanitize-vr4320
4571 // end-sanitize-vr4320
4572 // start-sanitize-vr5400
4574 // end-sanitize-vr5400
4576 unsigned32 instruction = instruction_0;
4577 int destreg = ((instruction >> 6) & 0x0000001F);
4578 int fs = ((instruction >> 11) & 0x0000001F);
4579 int ft = ((instruction >> 16) & 0x0000001F);
4580 int fr = ((instruction >> 21) & 0x0000001F);
4582 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4587 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4588 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4591 // start-sanitize-vr4320
4593 // end-sanitize-vr4320
4594 // start-sanitize-vr5400
4596 // end-sanitize-vr5400
4598 unsigned32 instruction = instruction_0;
4599 int destreg = ((instruction >> 6) & 0x0000001F);
4600 int fs = ((instruction >> 11) & 0x0000001F);
4601 int ft = ((instruction >> 16) & 0x0000001F);
4602 int fr = ((instruction >> 21) & 0x0000001F);
4604 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4611 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4612 "m%s<X>c1 r<RT>, f<FS>"
4619 if (SizeFGR() == 64)
4620 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4622 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4625 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4627 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4628 "m%s<X>c1 r<RT>, f<FS>"
4631 // start-sanitize-vr4320
4633 // end-sanitize-vr4320
4634 // start-sanitize-vr5400
4636 // end-sanitize-vr5400
4638 // start-sanitize-tx19
4640 // end-sanitize-tx19
4644 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4646 GPR[RT] = SIGNEXTEND(FGR[FS],32);
4650 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4651 "mov.%s<FMT> f<FD>, f<FS>"
4652 *mipsI,mipsII,mipsIII,mipsIV:
4654 // start-sanitize-vr4320
4656 // end-sanitize-vr4320
4657 // start-sanitize-vr5400
4659 // end-sanitize-vr5400
4661 // start-sanitize-tx19
4663 // end-sanitize-tx19
4665 unsigned32 instruction = instruction_0;
4666 int destreg = ((instruction >> 6) & 0x0000001F);
4667 int fs = ((instruction >> 11) & 0x0000001F);
4668 int format = ((instruction >> 21) & 0x00000007);
4670 StoreFPR(destreg,format,ValueFPR(fs,format));
4676 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4677 "mov%s<TF> r<RD>, r<RS>, <CC>"
4680 // start-sanitize-vr4320
4682 // end-sanitize-vr4320
4683 // start-sanitize-vr5400
4685 // end-sanitize-vr5400
4686 // start-sanitize-r5900
4688 // end-sanitize-r5900
4690 if (GETFCC(CC) == TF)
4696 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4697 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4700 // start-sanitize-vr4320
4702 // end-sanitize-vr4320
4703 // start-sanitize-vr5400
4705 // end-sanitize-vr5400
4706 // start-sanitize-r5900
4708 // end-sanitize-r5900
4710 unsigned32 instruction = instruction_0;
4711 int format = ((instruction >> 21) & 0x00000007);
4713 if (GETFCC(CC) == TF)
4714 StoreFPR (FD, format, ValueFPR (FS, format));
4716 StoreFPR (FD, format, ValueFPR (FD, format));
4721 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4724 // start-sanitize-vr4320
4726 // end-sanitize-vr4320
4727 // start-sanitize-vr5400
4729 // end-sanitize-vr5400
4730 // start-sanitize-r5900
4732 // end-sanitize-r5900
4734 unsigned32 instruction = instruction_0;
4735 int destreg = ((instruction >> 6) & 0x0000001F);
4736 int fs = ((instruction >> 11) & 0x0000001F);
4737 int format = ((instruction >> 21) & 0x00000007);
4739 StoreFPR(destreg,format,ValueFPR(fs,format));
4747 // MOVT.fmt see MOVtf.fmt
4751 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4752 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4755 // start-sanitize-vr4320
4757 // end-sanitize-vr4320
4758 // start-sanitize-vr5400
4760 // end-sanitize-vr5400
4761 // start-sanitize-r5900
4763 // end-sanitize-r5900
4765 unsigned32 instruction = instruction_0;
4766 int destreg = ((instruction >> 6) & 0x0000001F);
4767 int fs = ((instruction >> 11) & 0x0000001F);
4768 int format = ((instruction >> 21) & 0x00000007);
4770 StoreFPR(destreg,format,ValueFPR(fs,format));
4776 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4777 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4780 // start-sanitize-vr4320
4782 // end-sanitize-vr4320
4783 // start-sanitize-vr5400
4785 // end-sanitize-vr5400
4786 // start-sanitize-r5900
4788 // end-sanitize-r5900
4790 unsigned32 instruction = instruction_0;
4791 int destreg = ((instruction >> 6) & 0x0000001F);
4792 int fs = ((instruction >> 11) & 0x0000001F);
4793 int ft = ((instruction >> 16) & 0x0000001F);
4794 int fr = ((instruction >> 21) & 0x0000001F);
4796 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4802 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4803 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4806 // start-sanitize-vr4320
4808 // end-sanitize-vr4320
4809 // start-sanitize-vr5400
4811 // end-sanitize-vr5400
4812 // start-sanitize-r5900
4814 // end-sanitize-r5900
4816 unsigned32 instruction = instruction_0;
4817 int destreg = ((instruction >> 6) & 0x0000001F);
4818 int fs = ((instruction >> 11) & 0x0000001F);
4819 int ft = ((instruction >> 16) & 0x0000001F);
4820 int fr = ((instruction >> 21) & 0x0000001F);
4822 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4830 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4831 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4832 *mipsI,mipsII,mipsIII,mipsIV:
4834 // start-sanitize-vr4320
4836 // end-sanitize-vr4320
4837 // start-sanitize-vr5400
4839 // end-sanitize-vr5400
4841 // start-sanitize-tx19
4843 // end-sanitize-tx19
4845 unsigned32 instruction = instruction_0;
4846 int destreg = ((instruction >> 6) & 0x0000001F);
4847 int fs = ((instruction >> 11) & 0x0000001F);
4848 int ft = ((instruction >> 16) & 0x0000001F);
4849 int format = ((instruction >> 21) & 0x00000007);
4851 if ((format != fmt_single) && (format != fmt_double))
4852 SignalException(ReservedInstruction,instruction);
4854 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4859 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4860 "neg.%s<FMT> f<FD>, f<FS>"
4861 *mipsI,mipsII,mipsIII,mipsIV:
4863 // start-sanitize-vr4320
4865 // end-sanitize-vr4320
4866 // start-sanitize-vr5400
4868 // end-sanitize-vr5400
4870 // start-sanitize-tx19
4872 // end-sanitize-tx19
4874 unsigned32 instruction = instruction_0;
4875 int destreg = ((instruction >> 6) & 0x0000001F);
4876 int fs = ((instruction >> 11) & 0x0000001F);
4877 int format = ((instruction >> 21) & 0x00000007);
4879 if ((format != fmt_single) && (format != fmt_double))
4880 SignalException(ReservedInstruction,instruction);
4882 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4888 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4889 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4892 // start-sanitize-vr4320
4894 // end-sanitize-vr4320
4895 // start-sanitize-vr5400
4897 // end-sanitize-vr5400
4899 unsigned32 instruction = instruction_0;
4900 int destreg = ((instruction >> 6) & 0x0000001F);
4901 int fs = ((instruction >> 11) & 0x0000001F);
4902 int ft = ((instruction >> 16) & 0x0000001F);
4903 int fr = ((instruction >> 21) & 0x0000001F);
4905 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4911 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4912 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4915 // start-sanitize-vr4320
4917 // end-sanitize-vr4320
4918 // start-sanitize-vr5400
4920 // end-sanitize-vr5400
4922 unsigned32 instruction = instruction_0;
4923 int destreg = ((instruction >> 6) & 0x0000001F);
4924 int fs = ((instruction >> 11) & 0x0000001F);
4925 int ft = ((instruction >> 16) & 0x0000001F);
4926 int fr = ((instruction >> 21) & 0x0000001F);
4928 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4934 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4935 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4938 // start-sanitize-vr4320
4940 // end-sanitize-vr4320
4941 // start-sanitize-vr5400
4943 // end-sanitize-vr5400
4945 unsigned32 instruction = instruction_0;
4946 int destreg = ((instruction >> 6) & 0x0000001F);
4947 int fs = ((instruction >> 11) & 0x0000001F);
4948 int ft = ((instruction >> 16) & 0x0000001F);
4949 int fr = ((instruction >> 21) & 0x0000001F);
4951 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4957 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4958 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4961 // start-sanitize-vr4320
4963 // end-sanitize-vr4320
4964 // start-sanitize-vr5400
4966 // end-sanitize-vr5400
4968 unsigned32 instruction = instruction_0;
4969 int destreg = ((instruction >> 6) & 0x0000001F);
4970 int fs = ((instruction >> 11) & 0x0000001F);
4971 int ft = ((instruction >> 16) & 0x0000001F);
4972 int fr = ((instruction >> 21) & 0x0000001F);
4974 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4979 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4980 "prefx <HINT>, r<INDEX>(r<BASE>)"
4983 // start-sanitize-vr4320
4985 // end-sanitize-vr4320
4986 // start-sanitize-vr5400
4988 // end-sanitize-vr5400
4990 unsigned32 instruction = instruction_0;
4991 int fs = ((instruction >> 11) & 0x0000001F);
4992 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4993 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4995 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4998 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4999 Prefetch(uncached,paddr,vaddr,isDATA,fs);
5003 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5005 "recip.%s<FMT> f<FD>, f<FS>"
5007 // start-sanitize-vr4320
5009 // end-sanitize-vr4320
5010 // start-sanitize-vr5400
5012 // end-sanitize-vr5400
5014 unsigned32 instruction = instruction_0;
5015 int destreg = ((instruction >> 6) & 0x0000001F);
5016 int fs = ((instruction >> 11) & 0x0000001F);
5017 int format = ((instruction >> 21) & 0x00000007);
5019 if ((format != fmt_single) && (format != fmt_double))
5020 SignalException(ReservedInstruction,instruction);
5022 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5027 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5028 "round.l.%s<FMT> f<FD>, f<FS>"
5032 // start-sanitize-vr4320
5034 // end-sanitize-vr4320
5035 // start-sanitize-vr5400
5037 // end-sanitize-vr5400
5038 // start-sanitize-r5900
5040 // end-sanitize-r5900
5042 // start-sanitize-tx19
5044 // end-sanitize-tx19
5046 unsigned32 instruction = instruction_0;
5047 int destreg = ((instruction >> 6) & 0x0000001F);
5048 int fs = ((instruction >> 11) & 0x0000001F);
5049 int format = ((instruction >> 21) & 0x00000007);
5051 if ((format != fmt_single) && (format != fmt_double))
5052 SignalException(ReservedInstruction,instruction);
5054 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5059 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5060 "round.w.%s<FMT> f<FD>, f<FS>"
5065 // start-sanitize-vr4320
5067 // end-sanitize-vr4320
5068 // start-sanitize-vr5400
5070 // end-sanitize-vr5400
5071 // start-sanitize-r5900
5073 // end-sanitize-r5900
5075 // start-sanitize-tx19
5077 // end-sanitize-tx19
5079 unsigned32 instruction = instruction_0;
5080 int destreg = ((instruction >> 6) & 0x0000001F);
5081 int fs = ((instruction >> 11) & 0x0000001F);
5082 int format = ((instruction >> 21) & 0x00000007);
5084 if ((format != fmt_single) && (format != fmt_double))
5085 SignalException(ReservedInstruction,instruction);
5087 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5092 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5094 "rsqrt.%s<FMT> f<FD>, f<FS>"
5096 // start-sanitize-vr4320
5098 // end-sanitize-vr4320
5099 // start-sanitize-vr5400
5101 // end-sanitize-vr5400
5103 unsigned32 instruction = instruction_0;
5104 int destreg = ((instruction >> 6) & 0x0000001F);
5105 int fs = ((instruction >> 11) & 0x0000001F);
5106 int format = ((instruction >> 21) & 0x00000007);
5108 if ((format != fmt_single) && (format != fmt_double))
5109 SignalException(ReservedInstruction,instruction);
5111 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5116 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5117 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5122 // start-sanitize-vr4320
5124 // end-sanitize-vr4320
5125 // start-sanitize-vr5400
5127 // end-sanitize-vr5400
5129 // start-sanitize-tx19
5131 // end-sanitize-tx19
5133 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5137 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5138 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5141 // start-sanitize-vr4320
5143 // end-sanitize-vr4320
5144 // start-sanitize-vr5400
5146 // end-sanitize-vr5400
5148 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5152 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5153 "sqrt.%s<FMT> f<FD>, f<FS>"
5158 // start-sanitize-vr4320
5160 // end-sanitize-vr4320
5161 // start-sanitize-vr5400
5163 // end-sanitize-vr5400
5165 // start-sanitize-tx19
5167 // end-sanitize-tx19
5169 unsigned32 instruction = instruction_0;
5170 int destreg = ((instruction >> 6) & 0x0000001F);
5171 int fs = ((instruction >> 11) & 0x0000001F);
5172 int format = ((instruction >> 21) & 0x00000007);
5174 if ((format != fmt_single) && (format != fmt_double))
5175 SignalException(ReservedInstruction,instruction);
5177 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5182 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5183 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5184 *mipsI,mipsII,mipsIII,mipsIV:
5186 // start-sanitize-vr4320
5188 // end-sanitize-vr4320
5189 // start-sanitize-vr5400
5191 // end-sanitize-vr5400
5193 // start-sanitize-tx19
5195 // end-sanitize-tx19
5197 unsigned32 instruction = instruction_0;
5198 int destreg = ((instruction >> 6) & 0x0000001F);
5199 int fs = ((instruction >> 11) & 0x0000001F);
5200 int ft = ((instruction >> 16) & 0x0000001F);
5201 int format = ((instruction >> 21) & 0x00000007);
5203 if ((format != fmt_single) && (format != fmt_double))
5204 SignalException(ReservedInstruction,instruction);
5206 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5212 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5213 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5214 *mipsI,mipsII,mipsIII,mipsIV:
5216 // start-sanitize-vr4320
5218 // end-sanitize-vr4320
5219 // start-sanitize-vr5400
5221 // end-sanitize-vr5400
5222 // start-sanitize-r5900
5224 // end-sanitize-r5900
5226 // start-sanitize-tx19
5228 // end-sanitize-tx19
5230 unsigned32 instruction = instruction_0;
5231 signed_word offset = EXTEND16 (OFFSET);
5232 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5233 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5235 address_word vaddr = ((uword64)op1 + offset);
5238 if ((vaddr & 3) != 0)
5239 SignalExceptionAddressStore();
5242 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5245 uword64 memval1 = 0;
5246 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5247 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5248 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5250 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5251 byte = ((vaddr & mask) ^ bigendiancpu);
5252 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5253 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5260 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5261 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5264 // start-sanitize-vr4320
5266 // end-sanitize-vr4320
5267 // start-sanitize-vr5400
5269 // end-sanitize-vr5400
5271 unsigned32 instruction = instruction_0;
5272 int fs = ((instruction >> 11) & 0x0000001F);
5273 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5274 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5276 address_word vaddr = ((unsigned64)op1 + op2);
5279 if ((vaddr & 3) != 0)
5280 SignalExceptionAddressStore();
5283 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5285 unsigned64 memval = 0;
5286 unsigned64 memval1 = 0;
5287 unsigned64 mask = 0x7;
5289 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5290 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5291 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5293 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5301 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5302 "trunc.l.%s<FMT> f<FD>, f<FS>"
5306 // start-sanitize-vr4320
5308 // end-sanitize-vr4320
5309 // start-sanitize-vr5400
5311 // end-sanitize-vr5400
5312 // start-sanitize-r5900
5314 // end-sanitize-r5900
5316 // start-sanitize-tx19
5318 // end-sanitize-tx19
5320 unsigned32 instruction = instruction_0;
5321 int destreg = ((instruction >> 6) & 0x0000001F);
5322 int fs = ((instruction >> 11) & 0x0000001F);
5323 int format = ((instruction >> 21) & 0x00000007);
5325 if ((format != fmt_single) && (format != fmt_double))
5326 SignalException(ReservedInstruction,instruction);
5328 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5333 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5334 "trunc.w.%s<FMT> f<FD>, f<FS>"
5339 // start-sanitize-vr4320
5341 // end-sanitize-vr4320
5342 // start-sanitize-vr5400
5344 // end-sanitize-vr5400
5345 // start-sanitize-r5900
5347 // end-sanitize-r5900
5349 // start-sanitize-tx19
5351 // end-sanitize-tx19
5353 unsigned32 instruction = instruction_0;
5354 int destreg = ((instruction >> 6) & 0x0000001F);
5355 int fs = ((instruction >> 11) & 0x0000001F);
5356 int format = ((instruction >> 21) & 0x00000007);
5358 if ((format != fmt_single) && (format != fmt_double))
5359 SignalException(ReservedInstruction,instruction);
5361 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5367 // MIPS Architecture:
5369 // System Control Instruction Set (COP0)
5373 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5375 *mipsI,mipsII,mipsIII,mipsIV:
5377 // start-sanitize-vr4320
5379 // end-sanitize-vr4320
5380 // start-sanitize-vr5400
5382 // end-sanitize-vr5400
5383 // start-sanitize-r5900
5385 // start-sanitize-sky
5387 address_word offset = EXTEND16 (OFFSET) << 2;
5388 extern int sky_cpcond0;
5389 if (sky_cpcond0 == 0)
5390 DELAY_SLOT (NIA + offset);
5393 // end-sanitize-r5900
5396 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5398 *mipsI,mipsII,mipsIII,mipsIV:
5400 // start-sanitize-vr4320
5402 // end-sanitize-vr4320
5403 // start-sanitize-vr5400
5405 // end-sanitize-vr5400
5406 // start-sanitize-r5900
5408 // start-sanitize-sky
5410 address_word offset = EXTEND16 (OFFSET) << 2;
5411 extern int sky_cpcond0;
5412 if (sky_cpcond0 == 0)
5413 DELAY_SLOT (NIA + offset);
5416 // end-sanitize-r5900
5419 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5421 *mipsI,mipsII,mipsIII,mipsIV:
5422 // start-sanitize-r5900
5424 // start-sanitize-sky
5426 address_word offset = EXTEND16 (OFFSET) << 2;
5427 extern int sky_cpcond0;
5428 if (sky_cpcond0 != 0)
5429 DELAY_SLOT (NIA + offset);
5432 // end-sanitize-r5900
5436 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5438 *mipsI,mipsII,mipsIII,mipsIV:
5440 // start-sanitize-vr4320
5442 // end-sanitize-vr4320
5443 // start-sanitize-vr5400
5445 // end-sanitize-vr5400
5446 // start-sanitize-r5900
5448 // start-sanitize-sky
5450 address_word offset = EXTEND16 (OFFSET) << 2;
5451 extern int sky_cpcond0;
5452 if (sky_cpcond0 != 0)
5453 DELAY_SLOT (NIA + offset);
5456 // end-sanitize-r5900
5459 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5463 // start-sanitize-vr4320
5465 // end-sanitize-vr4320
5466 // start-sanitize-vr5400
5468 // end-sanitize-vr5400
5469 // start-sanitize-r5900
5471 // end-sanitize-r5900
5473 // start-sanitize-tx19
5475 // end-sanitize-tx19
5477 unsigned32 instruction = instruction_0;
5478 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5479 int hint = ((instruction >> 16) & 0x0000001F);
5480 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5482 address_word vaddr = (op1 + offset);
5485 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5486 CacheOp(hint,vaddr,paddr,instruction);
5491 010000,10000,000000000000000,111001:COP0:32::DI
5493 *mipsI,mipsII,mipsIII,mipsIV:
5495 // start-sanitize-vr4320
5497 // end-sanitize-vr4320
5498 // start-sanitize-vr5400
5500 // end-sanitize-vr5400
5501 // start-sanitize-r5900
5503 // end-sanitize-r5900
5506 010000,10000,000000000000000,111000:COP0:32::EI
5508 *mipsI,mipsII,mipsIII,mipsIV:
5510 // start-sanitize-vr4320
5512 // end-sanitize-vr4320
5513 // start-sanitize-vr5400
5515 // end-sanitize-vr5400
5516 // start-sanitize-r5900
5518 // end-sanitize-r5900
5521 010000,10000,000000000000000,011000:COP0:32::ERET
5526 // start-sanitize-vr4320
5528 // end-sanitize-vr4320
5529 // start-sanitize-vr5400
5531 // end-sanitize-vr5400
5532 // start-sanitize-r5900
5534 // end-sanitize-r5900
5536 if (SR & status_ERL)
5538 /* Oops, not yet available */
5539 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5551 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5552 "mfc0 r<RT>, r<RD> # <REGX>"
5553 *mipsI,mipsII,mipsIII,mipsIV:
5556 // start-sanitize-vr4320
5558 // end-sanitize-vr4320
5559 // start-sanitize-vr5400
5561 // end-sanitize-vr5400
5562 // start-sanitize-r5900
5564 // end-sanitize-r5900
5566 TRACE_ALU_INPUT0 ();
5567 DecodeCoproc (instruction_0);
5568 TRACE_ALU_RESULT (GPR[RT]);
5571 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5572 "mtc0 r<RT>, r<RD> # <REGX>"
5573 *mipsI,mipsII,mipsIII,mipsIV:
5574 // start-sanitize-tx19
5576 // end-sanitize-tx19
5578 // start-sanitize-vr4320
5580 // end-sanitize-vr4320
5582 // start-sanitize-vr5400
5584 // end-sanitize-vr5400
5585 // start-sanitize-r5900
5587 // end-sanitize-r5900
5589 DecodeCoproc (instruction_0);
5593 010000,10000,000000000000000,010000:COP0:32::RFE
5595 *mipsI,mipsII,mipsIII,mipsIV:
5596 // start-sanitize-tx19
5598 // end-sanitize-tx19
5600 // start-sanitize-vr4320
5602 // end-sanitize-vr4320
5604 // start-sanitize-vr5400
5606 // end-sanitize-vr5400
5607 // start-sanitize-r5900
5609 // end-sanitize-r5900
5611 DecodeCoproc (instruction_0);
5615 010000,10000,000000000000000,001000:COP0:32::TLBP
5617 *mipsI,mipsII,mipsIII,mipsIV:
5619 // start-sanitize-vr4320
5621 // end-sanitize-vr4320
5622 // start-sanitize-vr5400
5624 // end-sanitize-vr5400
5625 // start-sanitize-r5900
5627 // end-sanitize-r5900
5630 010000,10000,000000000000000,000001:COP0:32::TLBR
5632 *mipsI,mipsII,mipsIII,mipsIV:
5634 // start-sanitize-vr4320
5636 // end-sanitize-vr4320
5637 // start-sanitize-vr5400
5639 // end-sanitize-vr5400
5640 // start-sanitize-r5900
5642 // end-sanitize-r5900
5645 010000,10000,000000000000000,000010:COP0:32::TLBWI
5647 *mipsI,mipsII,mipsIII,mipsIV:
5649 // start-sanitize-vr4320
5651 // end-sanitize-vr4320
5652 // start-sanitize-vr5400
5654 // end-sanitize-vr5400
5655 // start-sanitize-r5900
5657 // end-sanitize-r5900
5660 010000,10000,000000000000000,000110:COP0:32::TLBWR
5662 *mipsI,mipsII,mipsIII,mipsIV:
5664 // start-sanitize-vr4320
5666 // end-sanitize-vr4320
5667 // start-sanitize-vr5400
5669 // end-sanitize-vr5400
5670 // start-sanitize-r5900
5672 // end-sanitize-r5900
5676 // start-sanitize-vr4320
5677 :include::vr4320:vr4320.igen
5678 // end-sanitize-vr4320
5679 // start-sanitize-vr5400
5680 :include::vr5400:vr5400.igen
5681 :include:64,f::mdmx.igen
5682 // end-sanitize-vr5400
5683 // start-sanitize-r5900
5684 :include::r5900:r5900.igen
5685 // end-sanitize-r5900
5688 // start-sanitize-cygnus-never
5690 // // FIXME FIXME FIXME What is this instruction?
5691 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5696 // // start-sanitize-r5900
5698 // // end-sanitize-r5900
5700 // // start-sanitize-tx19
5702 // // end-sanitize-tx19
5704 // unsigned32 instruction = instruction_0;
5705 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5706 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5707 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5709 // if (CoProcPresent(3))
5710 // SignalException(CoProcessorUnusable);
5712 // SignalException(ReservedInstruction,instruction);
5716 // end-sanitize-cygnus-never
5717 // start-sanitize-cygnus-never
5719 // // FIXME FIXME FIXME What is this?
5720 // 11100,******,00001:RR:16::SDBBP
5723 // unsigned32 instruction = instruction_0;
5724 // if (have_extendval)
5725 // SignalException (ReservedInstruction, instruction);
5727 // SignalException(DebugBreakPoint,instruction);
5731 // end-sanitize-cygnus-never
5732 // start-sanitize-cygnus-never
5734 // // FIXME FIXME FIXME What is this?
5735 // 000000,********************,001110:SPECIAL:32::SDBBP
5738 // unsigned32 instruction = instruction_0;
5740 // SignalException(DebugBreakPoint,instruction);
5744 // end-sanitize-cygnus-never
5745 // start-sanitize-cygnus-never
5747 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5748 // // isn't yet reconized by this simulator.
5749 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5752 // unsigned32 instruction = instruction_0;
5753 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5754 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5756 // CHECKHILO("Multiply-Add");
5758 // unsigned64 temp = (op1 * op2);
5759 // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5760 // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5761 // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5766 // end-sanitize-cygnus-never
5767 // start-sanitize-cygnus-never
5769 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5770 // // isn't yet reconized by this simulator.
5771 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5774 // unsigned32 instruction = instruction_0;
5775 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5776 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5778 // CHECKHILO("Multiply-Add");
5780 // unsigned64 temp = (op1 * op2);
5786 // end-sanitize-cygnus-never