4050a2c730e49294ac35450f6fd94fea921c1ac2
[deliverable/binutils-gdb.git] / sim / mips / mips.igen
1 // -*- C -*-
2 //
3 // <insn> ::=
4 // <insn-word> { "+" <insn-word> }
5 // ":" <format-name>
6 // ":" <filter-flags>
7 // ":" <options>
8 // ":" <name>
9 // <nl>
10 // { <insn-model> }
11 // { <insn-mnemonic> }
12 // <code-block>
13 //
14
15
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
21
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
27
28
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
31
32
33 // Models known by this simulator
34 :model:::mipsI:mips3000:
35 :model:::mipsII:mips6000:
36 :model:::mipsIII:mips4000:
37 :model:::mipsIV:mips8000:
38 :model:::mips16:mips16:
39 // start-sanitize-r5900
40 :model:::r5900:mips5900:
41 // end-sanitize-r5900
42 :model:::r3900:mips3900:
43 // start-sanitize-tx19
44 :model:::tx19:tx19:
45 // end-sanitize-tx19
46 // start-sanitize-vr4320
47 :model:::vr4320:mips4320:
48 // end-sanitize-vr4320
49 // start-sanitize-vr5400
50 :model:::vr5400:mips5400:
51 :model:::mdmx:mdmx:
52 // end-sanitize-vr5400
53 :model:::vr5000:mips5000:
54
55
56
57 // Pseudo instructions known by IGEN
58 :internal::::illegal:
59 {
60 SignalException (ReservedInstruction, 0);
61 }
62
63
64 // Pseudo instructions known by interp.c
65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
67 "rsvd <OP>"
68 {
69 SignalException (ReservedInstruction, instruction_0);
70 }
71
72
73
74 // Helper:
75 //
76 // Simulate a 32 bit delayslot instruction
77 //
78
79 :function:::address_word:delayslot32:address_word target
80 {
81 instruction_word delay_insn;
82 sim_events_slip (SD, 1);
83 DSPC = CIA;
84 CIA = CIA + 4; /* NOTE not mips16 */
85 STATE |= simDELAYSLOT;
86 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
87 idecode_issue (CPU_, delay_insn, (CIA));
88 STATE &= ~simDELAYSLOT;
89 return target;
90 }
91
92 :function:::address_word:nullify_next_insn32:
93 {
94 sim_events_slip (SD, 1);
95 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
96 return CIA + 8;
97 }
98
99
100
101 // Helper:
102 //
103 // Check that an access to a HI/LO register meets timing requirements
104 //
105 // The following requirements exist:
106 //
107 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
108 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
109 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
110 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
111 //
112
113 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
114 {
115 if (history->mf.timestamp + 3 > time)
116 {
117 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
118 itable[MY_INDEX].name,
119 new, (long) CIA,
120 (long) history->mf.cia);
121 return 0;
122 }
123 return 1;
124 }
125
126 :function:::int:check_mt_hilo:hilo_history *history
127 {
128 signed64 time = sim_events_time (SD);
129 int ok = check_mf_cycles (SD_, history, time, "MT");
130 history->mt.timestamp = time;
131 history->mt.cia = CIA;
132 return ok;
133 }
134
135 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
136 {
137 signed64 time = sim_events_time (SD);
138 int ok = 1;
139 if (peer != NULL
140 && peer->mt.timestamp > history->op.timestamp
141 && history->mf.timestamp < history->op.timestamp)
142 {
143 /* The peer has been written to since the last OP yet we have
144 not */
145 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
146 itable[MY_INDEX].name,
147 (long) CIA,
148 (long) history->op.cia,
149 (long) peer->mt.cia);
150 ok = 0;
151 }
152 history->mf.timestamp = time;
153 history->mf.cia = CIA;
154 return ok;
155 }
156
157 :function:::int:check_op_hilo:hilo_history *hi, hilo_history *lo
158 *mipsI,mipsII,mipsIII,mipsIV:
159 *vr5000:
160 // start-sanitize-vr4320
161 *vr4320:
162 // end-sanitize-vr4320
163 // start-sanitize-vr5400
164 *vr5400:
165 // end-sanitize-vr5400
166 *r3900:
167 // start-sanitize-tx19
168 *tx19:
169 // end-sanitize-tx19
170 // start-sanitize-r5900
171 *r5900:
172 // end-sanitize-r5900
173 {
174 signed64 time = sim_events_time (SD);
175 int ok = (check_mf_cycles (SD_, hi, time, "OP")
176 && check_mf_cycles (SD_, lo, time, "OP"));
177 hi->op.timestamp = time;
178 lo->op.timestamp = time;
179 hi->op.cia = CIA;
180 lo->op.cia = CIA;
181 return ok;
182 }
183
184
185
186 //
187 // Mips Architecture:
188 //
189 // CPU Instruction Set (mipsI - mipsIV)
190 //
191
192
193
194 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
195 "add r<RD>, r<RS>, r<RT>"
196 *mipsI,mipsII,mipsIII,mipsIV:
197 *vr5000:
198 // start-sanitize-vr4320
199 *vr4320:
200 // end-sanitize-vr4320
201 // start-sanitize-vr5400
202 *vr5400:
203 // end-sanitize-vr5400
204 // start-sanitize-r5900
205 *r5900:
206 // end-sanitize-r5900
207 *r3900:
208 // start-sanitize-tx19
209 *tx19:
210 // end-sanitize-tx19
211 {
212 ALU32_BEGIN (GPR[RS]);
213 ALU32_ADD (GPR[RT]);
214 ALU32_END (GPR[RD]);
215 }
216
217
218
219 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
220 "addi r<RT>, r<RS>, IMMEDIATE"
221 *mipsI,mipsII,mipsIII,mipsIV:
222 *vr5000:
223 // start-sanitize-vr4320
224 *vr4320:
225 // end-sanitize-vr4320
226 // start-sanitize-vr5400
227 *vr5400:
228 // end-sanitize-vr5400
229 // start-sanitize-r5900
230 *r5900:
231 // end-sanitize-r5900
232 *r3900:
233 // start-sanitize-tx19
234 *tx19:
235 // end-sanitize-tx19
236 {
237 ALU32_BEGIN (GPR[RS]);
238 ALU32_ADD (EXTEND16 (IMMEDIATE));
239 ALU32_END (GPR[RT]);
240 }
241
242
243
244 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
245 {
246 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
247 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
248 TRACE_ALU_RESULT (GPR[rt]);
249 }
250
251 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
252 "addiu r<RT>, r<RS>, <IMMEDIATE>"
253 *mipsI,mipsII,mipsIII,mipsIV:
254 *vr5000:
255 // start-sanitize-vr4320
256 *vr4320:
257 // end-sanitize-vr4320
258 // start-sanitize-vr5400
259 *vr5400:
260 // end-sanitize-vr5400
261 // start-sanitize-r5900
262 *r5900:
263 // end-sanitize-r5900
264 *r3900:
265 // start-sanitize-tx19
266 *tx19:
267 // end-sanitize-tx19
268 {
269 do_addiu (SD_, RS, RT, IMMEDIATE);
270 }
271
272
273
274 :function:::void:do_addu:int rs, int rt, int rd
275 {
276 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
277 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
278 TRACE_ALU_RESULT (GPR[rd]);
279 }
280
281 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
282 "addu r<RD>, r<RS>, r<RT>"
283 *mipsI,mipsII,mipsIII,mipsIV:
284 *vr5000:
285 // start-sanitize-vr4320
286 *vr4320:
287 // end-sanitize-vr4320
288 // start-sanitize-vr5400
289 *vr5400:
290 // end-sanitize-vr5400
291 // start-sanitize-r5900
292 *r5900:
293 // end-sanitize-r5900
294 *r3900:
295 // start-sanitize-tx19
296 *tx19:
297 // end-sanitize-tx19
298 {
299 do_addu (SD_, RS, RT, RD);
300 }
301
302
303
304 :function:::void:do_and:int rs, int rt, int rd
305 {
306 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
307 GPR[rd] = GPR[rs] & GPR[rt];
308 TRACE_ALU_RESULT (GPR[rd]);
309 }
310
311 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
312 "and r<RD>, r<RS>, r<RT>"
313 *mipsI,mipsII,mipsIII,mipsIV:
314 *vr5000:
315 // start-sanitize-vr4320
316 *vr4320:
317 // end-sanitize-vr4320
318 // start-sanitize-vr5400
319 *vr5400:
320 // end-sanitize-vr5400
321 // start-sanitize-r5900
322 *r5900:
323 // end-sanitize-r5900
324 *r3900:
325 // start-sanitize-tx19
326 *tx19:
327 // end-sanitize-tx19
328 {
329 do_and (SD_, RS, RT, RD);
330 }
331
332
333
334 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
335 "and r<RT>, r<RS>, <IMMEDIATE>"
336 *mipsI,mipsII,mipsIII,mipsIV:
337 *vr5000:
338 // start-sanitize-vr4320
339 *vr4320:
340 // end-sanitize-vr4320
341 // start-sanitize-vr5400
342 *vr5400:
343 // end-sanitize-vr5400
344 // start-sanitize-r5900
345 *r5900:
346 // end-sanitize-r5900
347 *r3900:
348 // start-sanitize-tx19
349 *tx19:
350 // end-sanitize-tx19
351 {
352 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
353 GPR[RT] = GPR[RS] & IMMEDIATE;
354 TRACE_ALU_RESULT (GPR[RT]);
355 }
356
357
358
359 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
360 "beq r<RS>, r<RT>, <OFFSET>"
361 *mipsI,mipsII,mipsIII,mipsIV:
362 *vr5000:
363 // start-sanitize-vr4320
364 *vr4320:
365 // end-sanitize-vr4320
366 // start-sanitize-vr5400
367 *vr5400:
368 // end-sanitize-vr5400
369 // start-sanitize-r5900
370 *r5900:
371 // end-sanitize-r5900
372 *r3900:
373 // start-sanitize-tx19
374 *tx19:
375 // end-sanitize-tx19
376 {
377 address_word offset = EXTEND16 (OFFSET) << 2;
378 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
379 DELAY_SLOT (NIA + offset);
380 }
381
382
383
384 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
385 "beql r<RS>, r<RT>, <OFFSET>"
386 *mipsII:
387 *mipsIII:
388 *mipsIV:
389 *vr5000:
390 // start-sanitize-vr4320
391 *vr4320:
392 // end-sanitize-vr4320
393 // start-sanitize-vr5400
394 *vr5400:
395 // end-sanitize-vr5400
396 // start-sanitize-r5900
397 *r5900:
398 // end-sanitize-r5900
399 *r3900:
400 // start-sanitize-tx19
401 *tx19:
402 // end-sanitize-tx19
403 {
404 address_word offset = EXTEND16 (OFFSET) << 2;
405 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
406 DELAY_SLOT (NIA + offset);
407 else
408 NULLIFY_NEXT_INSTRUCTION ();
409 }
410
411
412
413 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
414 "bgez r<RS>, <OFFSET>"
415 *mipsI,mipsII,mipsIII,mipsIV:
416 *vr5000:
417 // start-sanitize-vr4320
418 *vr4320:
419 // end-sanitize-vr4320
420 // start-sanitize-vr5400
421 *vr5400:
422 // end-sanitize-vr5400
423 // start-sanitize-r5900
424 *r5900:
425 // end-sanitize-r5900
426 *r3900:
427 // start-sanitize-tx19
428 *tx19:
429 // end-sanitize-tx19
430 {
431 address_word offset = EXTEND16 (OFFSET) << 2;
432 if ((signed_word) GPR[RS] >= 0)
433 DELAY_SLOT (NIA + offset);
434 }
435
436
437
438 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
439 "bgezal r<RS>, <OFFSET>"
440 *mipsI,mipsII,mipsIII,mipsIV:
441 *vr5000:
442 // start-sanitize-vr4320
443 *vr4320:
444 // end-sanitize-vr4320
445 // start-sanitize-vr5400
446 *vr5400:
447 // end-sanitize-vr5400
448 // start-sanitize-r5900
449 *r5900:
450 // end-sanitize-r5900
451 *r3900:
452 // start-sanitize-tx19
453 *tx19:
454 // end-sanitize-tx19
455 {
456 address_word offset = EXTEND16 (OFFSET) << 2;
457 RA = (CIA + 8);
458 if ((signed_word) GPR[RS] >= 0)
459 DELAY_SLOT (NIA + offset);
460 }
461
462
463
464 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
465 "bgezall r<RS>, <OFFSET>"
466 *mipsII:
467 *mipsIII:
468 *mipsIV:
469 *vr5000:
470 // start-sanitize-vr4320
471 *vr4320:
472 // end-sanitize-vr4320
473 // start-sanitize-vr5400
474 *vr5400:
475 // end-sanitize-vr5400
476 // start-sanitize-r5900
477 *r5900:
478 // end-sanitize-r5900
479 *r3900:
480 // start-sanitize-tx19
481 *tx19:
482 // end-sanitize-tx19
483 {
484 address_word offset = EXTEND16 (OFFSET) << 2;
485 RA = (CIA + 8);
486 /* NOTE: The branch occurs AFTER the next instruction has been
487 executed */
488 if ((signed_word) GPR[RS] >= 0)
489 DELAY_SLOT (NIA + offset);
490 else
491 NULLIFY_NEXT_INSTRUCTION ();
492 }
493
494
495
496 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
497 "bgezl r<RS>, <OFFSET>"
498 *mipsII:
499 *mipsIII:
500 *mipsIV:
501 *vr5000:
502 // start-sanitize-vr4320
503 *vr4320:
504 // end-sanitize-vr4320
505 // start-sanitize-vr5400
506 *vr5400:
507 // end-sanitize-vr5400
508 // start-sanitize-r5900
509 *r5900:
510 // end-sanitize-r5900
511 *r3900:
512 // start-sanitize-tx19
513 *tx19:
514 // end-sanitize-tx19
515 {
516 address_word offset = EXTEND16 (OFFSET) << 2;
517 if ((signed_word) GPR[RS] >= 0)
518 DELAY_SLOT (NIA + offset);
519 else
520 NULLIFY_NEXT_INSTRUCTION ();
521 }
522
523
524
525 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
526 "bgtz r<RS>, <OFFSET>"
527 *mipsI,mipsII,mipsIII,mipsIV:
528 *vr5000:
529 // start-sanitize-vr4320
530 *vr4320:
531 // end-sanitize-vr4320
532 // start-sanitize-vr5400
533 *vr5400:
534 // end-sanitize-vr5400
535 // start-sanitize-r5900
536 *r5900:
537 // end-sanitize-r5900
538 *r3900:
539 // start-sanitize-tx19
540 *tx19:
541 // end-sanitize-tx19
542 {
543 address_word offset = EXTEND16 (OFFSET) << 2;
544 if ((signed_word) GPR[RS] > 0)
545 DELAY_SLOT (NIA + offset);
546 }
547
548
549
550 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
551 "bgtzl r<RS>, <OFFSET>"
552 *mipsII:
553 *mipsIII:
554 *mipsIV:
555 *vr5000:
556 // start-sanitize-vr4320
557 *vr4320:
558 // end-sanitize-vr4320
559 // start-sanitize-vr5400
560 *vr5400:
561 // end-sanitize-vr5400
562 // start-sanitize-r5900
563 *r5900:
564 // end-sanitize-r5900
565 *r3900:
566 // start-sanitize-tx19
567 *tx19:
568 // end-sanitize-tx19
569 {
570 address_word offset = EXTEND16 (OFFSET) << 2;
571 /* NOTE: The branch occurs AFTER the next instruction has been
572 executed */
573 if ((signed_word) GPR[RS] > 0)
574 DELAY_SLOT (NIA + offset);
575 else
576 NULLIFY_NEXT_INSTRUCTION ();
577 }
578
579
580
581 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
582 "blez r<RS>, <OFFSET>"
583 *mipsI,mipsII,mipsIII,mipsIV:
584 *vr5000:
585 // start-sanitize-vr4320
586 *vr4320:
587 // end-sanitize-vr4320
588 // start-sanitize-vr5400
589 *vr5400:
590 // end-sanitize-vr5400
591 // start-sanitize-r5900
592 *r5900:
593 // end-sanitize-r5900
594 *r3900:
595 // start-sanitize-tx19
596 *tx19:
597 // end-sanitize-tx19
598 {
599 address_word offset = EXTEND16 (OFFSET) << 2;
600 /* NOTE: The branch occurs AFTER the next instruction has been
601 executed */
602 if ((signed_word) GPR[RS] <= 0)
603 DELAY_SLOT (NIA + offset);
604 }
605
606
607
608 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
609 "bgezl r<RS>, <OFFSET>"
610 *mipsII:
611 *mipsIII:
612 *mipsIV:
613 *vr5000:
614 // start-sanitize-vr4320
615 *vr4320:
616 // end-sanitize-vr4320
617 // start-sanitize-vr5400
618 *vr5400:
619 // end-sanitize-vr5400
620 // start-sanitize-r5900
621 *r5900:
622 // end-sanitize-r5900
623 *r3900:
624 // start-sanitize-tx19
625 *tx19:
626 // end-sanitize-tx19
627 {
628 address_word offset = EXTEND16 (OFFSET) << 2;
629 if ((signed_word) GPR[RS] <= 0)
630 DELAY_SLOT (NIA + offset);
631 else
632 NULLIFY_NEXT_INSTRUCTION ();
633 }
634
635
636
637 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
638 "bltz r<RS>, <OFFSET>"
639 *mipsI,mipsII,mipsIII,mipsIV:
640 *vr5000:
641 // start-sanitize-vr4320
642 *vr4320:
643 // end-sanitize-vr4320
644 // start-sanitize-vr5400
645 *vr5400:
646 // end-sanitize-vr5400
647 // start-sanitize-r5900
648 *r5900:
649 // end-sanitize-r5900
650 *r3900:
651 // start-sanitize-tx19
652 *tx19:
653 // end-sanitize-tx19
654 {
655 address_word offset = EXTEND16 (OFFSET) << 2;
656 if ((signed_word) GPR[RS] < 0)
657 DELAY_SLOT (NIA + offset);
658 }
659
660
661
662 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
663 "bltzal r<RS>, <OFFSET>"
664 *mipsI,mipsII,mipsIII,mipsIV:
665 *vr5000:
666 // start-sanitize-vr4320
667 *vr4320:
668 // end-sanitize-vr4320
669 // start-sanitize-vr5400
670 *vr5400:
671 // end-sanitize-vr5400
672 // start-sanitize-r5900
673 *r5900:
674 // end-sanitize-r5900
675 *r3900:
676 // start-sanitize-tx19
677 *tx19:
678 // end-sanitize-tx19
679 {
680 address_word offset = EXTEND16 (OFFSET) << 2;
681 RA = (CIA + 8);
682 /* NOTE: The branch occurs AFTER the next instruction has been
683 executed */
684 if ((signed_word) GPR[RS] < 0)
685 DELAY_SLOT (NIA + offset);
686 }
687
688
689
690 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
691 "bltzall r<RS>, <OFFSET>"
692 *mipsII:
693 *mipsIII:
694 *mipsIV:
695 *vr5000:
696 // start-sanitize-vr4320
697 *vr4320:
698 // end-sanitize-vr4320
699 // start-sanitize-vr5400
700 *vr5400:
701 // end-sanitize-vr5400
702 // start-sanitize-r5900
703 *r5900:
704 // end-sanitize-r5900
705 *r3900:
706 // start-sanitize-tx19
707 *tx19:
708 // end-sanitize-tx19
709 {
710 address_word offset = EXTEND16 (OFFSET) << 2;
711 RA = (CIA + 8);
712 if ((signed_word) GPR[RS] < 0)
713 DELAY_SLOT (NIA + offset);
714 else
715 NULLIFY_NEXT_INSTRUCTION ();
716 }
717
718
719
720 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
721 "bltzl r<RS>, <OFFSET>"
722 *mipsII:
723 *mipsIII:
724 *mipsIV:
725 *vr5000:
726 // start-sanitize-vr4320
727 *vr4320:
728 // end-sanitize-vr4320
729 // start-sanitize-vr5400
730 *vr5400:
731 // end-sanitize-vr5400
732 // start-sanitize-r5900
733 *r5900:
734 // end-sanitize-r5900
735 *r3900:
736 // start-sanitize-tx19
737 *tx19:
738 // end-sanitize-tx19
739 {
740 address_word offset = EXTEND16 (OFFSET) << 2;
741 /* NOTE: The branch occurs AFTER the next instruction has been
742 executed */
743 if ((signed_word) GPR[RS] < 0)
744 DELAY_SLOT (NIA + offset);
745 else
746 NULLIFY_NEXT_INSTRUCTION ();
747 }
748
749
750
751 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
752 "bne r<RS>, r<RT>, <OFFSET>"
753 *mipsI,mipsII,mipsIII,mipsIV:
754 *vr5000:
755 // start-sanitize-vr4320
756 *vr4320:
757 // end-sanitize-vr4320
758 // start-sanitize-vr5400
759 *vr5400:
760 // end-sanitize-vr5400
761 // start-sanitize-r5900
762 *r5900:
763 // end-sanitize-r5900
764 *r3900:
765 // start-sanitize-tx19
766 *tx19:
767 // end-sanitize-tx19
768 {
769 address_word offset = EXTEND16 (OFFSET) << 2;
770 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
771 DELAY_SLOT (NIA + offset);
772 }
773
774
775
776 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
777 "bnel r<RS>, r<RT>, <OFFSET>"
778 *mipsII:
779 *mipsIII:
780 *mipsIV:
781 *vr5000:
782 // start-sanitize-vr4320
783 *vr4320:
784 // end-sanitize-vr4320
785 // start-sanitize-vr5400
786 *vr5400:
787 // end-sanitize-vr5400
788 // start-sanitize-r5900
789 *r5900:
790 // end-sanitize-r5900
791 *r3900:
792 // start-sanitize-tx19
793 *tx19:
794 // end-sanitize-tx19
795 {
796 address_word offset = EXTEND16 (OFFSET) << 2;
797 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
798 DELAY_SLOT (NIA + offset);
799 else
800 NULLIFY_NEXT_INSTRUCTION ();
801 }
802
803
804
805 000000,20.CODE,001101:SPECIAL:32::BREAK
806 "break"
807 *mipsI,mipsII,mipsIII,mipsIV:
808 *vr5000:
809 // start-sanitize-vr4320
810 *vr4320:
811 // end-sanitize-vr4320
812 // start-sanitize-vr5400
813 *vr5400:
814 // end-sanitize-vr5400
815 // start-sanitize-r5900
816 *r5900:
817 // end-sanitize-r5900
818 *r3900:
819 // start-sanitize-tx19
820 *tx19:
821 // end-sanitize-tx19
822 {
823 SignalException(BreakPoint, instruction_0);
824 }
825
826
827
828 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
829 "cop<ZZ> <COP_FUN>"
830 *mipsI,mipsII,mipsIII,mipsIV:
831 // start-sanitize-r5900
832 *r5900:
833 // end-sanitize-r5900
834 *r3900:
835 // start-sanitize-tx19
836 *tx19:
837 // end-sanitize-tx19
838 {
839 DecodeCoproc (instruction_0);
840 }
841
842
843
844 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
845 "dadd r<RD>, r<RS>, r<RT>"
846 *mipsIII:
847 *mipsIV:
848 *vr5000:
849 // start-sanitize-vr4320
850 *vr4320:
851 // end-sanitize-vr4320
852 // start-sanitize-vr5400
853 *vr5400:
854 // end-sanitize-vr5400
855 // start-sanitize-r5900
856 *r5900:
857 // end-sanitize-r5900
858 // start-sanitize-tx19
859 *tx19:
860 // end-sanitize-tx19
861 {
862 /* this check's for overflow */
863 ALU64_BEGIN (GPR[RS]);
864 ALU64_ADD (GPR[RT]);
865 ALU64_END (GPR[RD]);
866 }
867
868
869
870 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
871 "daddi r<RT>, r<RS>, <IMMEDIATE>"
872 *mipsIII:
873 *mipsIV:
874 *vr5000:
875 // start-sanitize-vr4320
876 *vr4320:
877 // end-sanitize-vr4320
878 // start-sanitize-vr5400
879 *vr5400:
880 // end-sanitize-vr5400
881 // start-sanitize-r5900
882 *r5900:
883 // end-sanitize-r5900
884 // start-sanitize-tx19
885 *tx19:
886 // end-sanitize-tx19
887 {
888 ALU64_BEGIN (GPR[RS]);
889 ALU64_ADD (EXTEND16 (IMMEDIATE));
890 ALU64_END (GPR[RT]);
891 }
892
893
894
895 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
896 {
897 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
898 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
899 TRACE_ALU_RESULT (GPR[rt]);
900 }
901
902 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
903 "daddu r<RT>, r<RS>, <IMMEDIATE>"
904 *mipsIII:
905 *mipsIV:
906 *vr5000:
907 // start-sanitize-vr4320
908 *vr4320:
909 // end-sanitize-vr4320
910 // start-sanitize-vr5400
911 *vr5400:
912 // end-sanitize-vr5400
913 // start-sanitize-r5900
914 *r5900:
915 // end-sanitize-r5900
916 // start-sanitize-tx19
917 *tx19:
918 // end-sanitize-tx19
919 {
920 do_daddiu (SD_, RS, RT, IMMEDIATE);
921 }
922
923
924
925 :function:::void:do_daddu:int rs, int rt, int rd
926 {
927 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
928 GPR[rd] = GPR[rs] + GPR[rt];
929 TRACE_ALU_RESULT (GPR[rd]);
930 }
931
932 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
933 "daddu r<RD>, r<RS>, r<RT>"
934 *mipsIII:
935 *mipsIV:
936 *vr5000:
937 // start-sanitize-vr4320
938 *vr4320:
939 // end-sanitize-vr4320
940 // start-sanitize-vr5400
941 *vr5400:
942 // end-sanitize-vr5400
943 // start-sanitize-r5900
944 *r5900:
945 // end-sanitize-r5900
946 // start-sanitize-tx19
947 *tx19:
948 // end-sanitize-tx19
949 {
950 do_daddu (SD_, RS, RT, RD);
951 }
952
953
954
955 :function:64::void:do_ddiv:int rs, int rt
956 {
957 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
958 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
959 {
960 signed64 n = GPR[rs];
961 signed64 d = GPR[rt];
962 if (d == 0)
963 {
964 LO = SIGNED64 (0x8000000000000000);
965 HI = 0;
966 }
967 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
968 {
969 LO = SIGNED64 (0x8000000000000000);
970 HI = 0;
971 }
972 else
973 {
974 LO = (n / d);
975 HI = (n % d);
976 }
977 }
978 TRACE_ALU_RESULT2 (HI, LO);
979 }
980
981 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
982 "ddiv r<RS>, r<RT>"
983 *mipsIII:
984 *mipsIV:
985 *vr5000:
986 // start-sanitize-vr4320
987 *vr4320:
988 // end-sanitize-vr4320
989 // start-sanitize-vr5400
990 *vr5400:
991 // end-sanitize-vr5400
992 // start-sanitize-r5900
993 *r5900:
994 // end-sanitize-r5900
995 // start-sanitize-tx19
996 *tx19:
997 // end-sanitize-tx19
998 {
999 do_ddiv (SD_, RS, RT);
1000 }
1001
1002
1003
1004 :function:64::void:do_ddivu:int rs, int rt
1005 {
1006 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
1007 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1008 {
1009 unsigned64 n = GPR[rs];
1010 unsigned64 d = GPR[rt];
1011 if (d == 0)
1012 {
1013 LO = SIGNED64 (0x8000000000000000);
1014 HI = 0;
1015 }
1016 else
1017 {
1018 LO = (n / d);
1019 HI = (n % d);
1020 }
1021 }
1022 TRACE_ALU_RESULT2 (HI, LO);
1023 }
1024
1025 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1026 "ddivu r<RS>, r<RT>"
1027 *mipsIII:
1028 *mipsIV:
1029 *vr5000:
1030 // start-sanitize-vr4320
1031 *vr4320:
1032 // end-sanitize-vr4320
1033 // start-sanitize-vr5400
1034 *vr5400:
1035 // end-sanitize-vr5400
1036 // start-sanitize-tx19
1037 *tx19:
1038 // end-sanitize-tx19
1039 {
1040 do_ddivu (SD_, RS, RT);
1041 }
1042
1043
1044
1045 :function:::void:do_div:int rs, int rt
1046 {
1047 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
1048 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1049 {
1050 signed32 n = GPR[rs];
1051 signed32 d = GPR[rt];
1052 if (d == 0)
1053 {
1054 LO = EXTEND32 (0x80000000);
1055 HI = EXTEND32 (0);
1056 }
1057 else if (n == SIGNED32 (0x80000000) && d == -1)
1058 {
1059 LO = EXTEND32 (0x80000000);
1060 HI = EXTEND32 (0);
1061 }
1062 else
1063 {
1064 LO = EXTEND32 (n / d);
1065 HI = EXTEND32 (n % d);
1066 }
1067 }
1068 TRACE_ALU_RESULT2 (HI, LO);
1069 }
1070
1071 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1072 "div r<RS>, r<RT>"
1073 *mipsI,mipsII,mipsIII,mipsIV:
1074 *vr5000:
1075 // start-sanitize-vr4320
1076 *vr4320:
1077 // end-sanitize-vr4320
1078 // start-sanitize-vr5400
1079 *vr5400:
1080 // end-sanitize-vr5400
1081 // start-sanitize-r5900
1082 *r5900:
1083 // end-sanitize-r5900
1084 *r3900:
1085 // start-sanitize-tx19
1086 *tx19:
1087 // end-sanitize-tx19
1088 {
1089 do_div (SD_, RS, RT);
1090 }
1091
1092
1093
1094 :function:::void:do_divu:int rs, int rt
1095 {
1096 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
1097 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1098 {
1099 unsigned32 n = GPR[rs];
1100 unsigned32 d = GPR[rt];
1101 if (d == 0)
1102 {
1103 LO = EXTEND32 (0x80000000);
1104 HI = EXTEND32 (0);
1105 }
1106 else
1107 {
1108 LO = EXTEND32 (n / d);
1109 HI = EXTEND32 (n % d);
1110 }
1111 }
1112 TRACE_ALU_RESULT2 (HI, LO);
1113 }
1114
1115 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1116 "divu r<RS>, r<RT>"
1117 *mipsI,mipsII,mipsIII,mipsIV:
1118 *vr5000:
1119 // start-sanitize-vr4320
1120 *vr4320:
1121 // end-sanitize-vr4320
1122 // start-sanitize-vr5400
1123 *vr5400:
1124 // end-sanitize-vr5400
1125 // start-sanitize-r5900
1126 *r5900:
1127 // end-sanitize-r5900
1128 *r3900:
1129 // start-sanitize-tx19
1130 *tx19:
1131 // end-sanitize-tx19
1132 {
1133 do_divu (SD_, RS, RT);
1134 }
1135
1136
1137
1138 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1139 {
1140 unsigned64 lo;
1141 unsigned64 hi;
1142 unsigned64 m00;
1143 unsigned64 m01;
1144 unsigned64 m10;
1145 unsigned64 m11;
1146 unsigned64 mid;
1147 int sign;
1148 unsigned64 op1 = GPR[rs];
1149 unsigned64 op2 = GPR[rt];
1150 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
1151 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1152 /* make signed multiply unsigned */
1153 sign = 0;
1154 if (signed_p)
1155 {
1156 if (op1 < 0)
1157 {
1158 op1 = - op1;
1159 ++sign;
1160 }
1161 if (op2 < 0)
1162 {
1163 op2 = - op2;
1164 ++sign;
1165 }
1166 }
1167 /* multuply out the 4 sub products */
1168 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1169 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1170 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1171 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1172 /* add the products */
1173 mid = ((unsigned64) VH4_8 (m00)
1174 + (unsigned64) VL4_8 (m10)
1175 + (unsigned64) VL4_8 (m01));
1176 lo = U8_4 (mid, m00);
1177 hi = (m11
1178 + (unsigned64) VH4_8 (mid)
1179 + (unsigned64) VH4_8 (m01)
1180 + (unsigned64) VH4_8 (m10));
1181 /* fix the sign */
1182 if (sign & 1)
1183 {
1184 lo = -lo;
1185 if (lo == 0)
1186 hi = -hi;
1187 else
1188 hi = -hi - 1;
1189 }
1190 /* save the result HI/LO (and a gpr) */
1191 LO = lo;
1192 HI = hi;
1193 if (rd != 0)
1194 GPR[rd] = lo;
1195 TRACE_ALU_RESULT2 (HI, LO);
1196 }
1197
1198 :function:::void:do_dmult:int rs, int rt, int rd
1199 {
1200 do_dmultx (SD_, rs, rt, rd, 1);
1201 }
1202
1203 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1204 "dmult r<RS>, r<RT>"
1205 *mipsIII,mipsIV:
1206 // start-sanitize-tx19
1207 *tx19:
1208 // end-sanitize-tx19
1209 // start-sanitize-vr4320
1210 *vr4320:
1211 // end-sanitize-vr4320
1212 {
1213 do_dmult (SD_, RS, RT, 0);
1214 }
1215
1216 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1217 "dmult r<RS>, r<RT>":RD == 0
1218 "dmult r<RD>, r<RS>, r<RT>"
1219 *vr5000:
1220 // start-sanitize-vr5400
1221 *vr5400:
1222 // end-sanitize-vr5400
1223 {
1224 do_dmult (SD_, RS, RT, RD);
1225 }
1226
1227
1228
1229 :function:::void:do_dmultu:int rs, int rt, int rd
1230 {
1231 do_dmultx (SD_, rs, rt, rd, 0);
1232 }
1233
1234 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1235 "dmultu r<RS>, r<RT>"
1236 *mipsIII,mipsIV:
1237 // start-sanitize-tx19
1238 *tx19:
1239 // end-sanitize-tx19
1240 // start-sanitize-vr4320
1241 *vr4320:
1242 // end-sanitize-vr4320
1243 {
1244 do_dmultu (SD_, RS, RT, 0);
1245 }
1246
1247 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1248 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1249 "dmultu r<RS>, r<RT>"
1250 *vr5000:
1251 // start-sanitize-vr5400
1252 *vr5400:
1253 // end-sanitize-vr5400
1254 {
1255 do_dmultu (SD_, RS, RT, RD);
1256 }
1257
1258
1259
1260 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1261 "dsll r<RD>, r<RT>, <SHIFT>"
1262 *mipsIII:
1263 *mipsIV:
1264 *vr5000:
1265 // start-sanitize-vr4320
1266 *vr4320:
1267 // end-sanitize-vr4320
1268 // start-sanitize-vr5400
1269 *vr5400:
1270 // end-sanitize-vr5400
1271 // start-sanitize-r5900
1272 *r5900:
1273 // end-sanitize-r5900
1274 // start-sanitize-tx19
1275 *tx19:
1276 // end-sanitize-tx19
1277 {
1278 int s = SHIFT;
1279 GPR[RD] = GPR[RT] << s;
1280 }
1281
1282
1283 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1284 "dsll32 r<RD>, r<RT>, <SHIFT>"
1285 *mipsIII:
1286 *mipsIV:
1287 *vr5000:
1288 // start-sanitize-vr4320
1289 *vr4320:
1290 // end-sanitize-vr4320
1291 // start-sanitize-vr5400
1292 *vr5400:
1293 // end-sanitize-vr5400
1294 // start-sanitize-r5900
1295 *r5900:
1296 // end-sanitize-r5900
1297 // start-sanitize-tx19
1298 *tx19:
1299 // end-sanitize-tx19
1300 {
1301 int s = 32 + SHIFT;
1302 GPR[RD] = GPR[RT] << s;
1303 }
1304
1305
1306
1307 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1308 "dsllv r<RD>, r<RT>, r<RS>"
1309 *mipsIII:
1310 *mipsIV:
1311 *vr5000:
1312 // start-sanitize-vr4320
1313 *vr4320:
1314 // end-sanitize-vr4320
1315 // start-sanitize-vr5400
1316 *vr5400:
1317 // end-sanitize-vr5400
1318 // start-sanitize-r5900
1319 *r5900:
1320 // end-sanitize-r5900
1321 // start-sanitize-tx19
1322 *tx19:
1323 // end-sanitize-tx19
1324 {
1325 int s = MASKED64 (GPR[RS], 5, 0);
1326 GPR[RD] = GPR[RT] << s;
1327 }
1328
1329
1330
1331 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1332 "dsra r<RD>, r<RT>, <SHIFT>"
1333 *mipsIII:
1334 *mipsIV:
1335 *vr5000:
1336 // start-sanitize-vr4320
1337 *vr4320:
1338 // end-sanitize-vr4320
1339 // start-sanitize-vr5400
1340 *vr5400:
1341 // end-sanitize-vr5400
1342 // start-sanitize-r5900
1343 *r5900:
1344 // end-sanitize-r5900
1345 // start-sanitize-tx19
1346 *tx19:
1347 // end-sanitize-tx19
1348 {
1349 int s = SHIFT;
1350 GPR[RD] = ((signed64) GPR[RT]) >> s;
1351 }
1352
1353
1354 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1355 "dsra32 r<RT>, r<RD>, <SHIFT>"
1356 *mipsIII:
1357 *mipsIV:
1358 *vr5000:
1359 // start-sanitize-vr4320
1360 *vr4320:
1361 // end-sanitize-vr4320
1362 // start-sanitize-vr5400
1363 *vr5400:
1364 // end-sanitize-vr5400
1365 // start-sanitize-r5900
1366 *r5900:
1367 // end-sanitize-r5900
1368 // start-sanitize-tx19
1369 *tx19:
1370 // end-sanitize-tx19
1371 {
1372 int s = 32 + SHIFT;
1373 GPR[RD] = ((signed64) GPR[RT]) >> s;
1374 }
1375
1376
1377 :function:::void:do_dsrav:int rs, int rt, int rd
1378 {
1379 int s = MASKED64 (GPR[rs], 5, 0);
1380 TRACE_ALU_INPUT2 (GPR[rt], s);
1381 GPR[rd] = ((signed64) GPR[rt]) >> s;
1382 TRACE_ALU_RESULT (GPR[rd]);
1383 }
1384
1385 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1386 "dsra32 r<RT>, r<RD>, r<RS>"
1387 *mipsIII:
1388 *mipsIV:
1389 *vr5000:
1390 // start-sanitize-vr4320
1391 *vr4320:
1392 // end-sanitize-vr4320
1393 // start-sanitize-vr5400
1394 *vr5400:
1395 // end-sanitize-vr5400
1396 // start-sanitize-r5900
1397 *r5900:
1398 // end-sanitize-r5900
1399 // start-sanitize-tx19
1400 *tx19:
1401 // end-sanitize-tx19
1402 {
1403 do_dsrav (SD_, RS, RT, RD);
1404 }
1405
1406
1407 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1408 "dsrl r<RD>, r<RT>, <SHIFT>"
1409 *mipsIII:
1410 *mipsIV:
1411 *vr5000:
1412 // start-sanitize-vr4320
1413 *vr4320:
1414 // end-sanitize-vr4320
1415 // start-sanitize-vr5400
1416 *vr5400:
1417 // end-sanitize-vr5400
1418 // start-sanitize-r5900
1419 *r5900:
1420 // end-sanitize-r5900
1421 // start-sanitize-tx19
1422 *tx19:
1423 // end-sanitize-tx19
1424 {
1425 int s = SHIFT;
1426 GPR[RD] = (unsigned64) GPR[RT] >> s;
1427 }
1428
1429
1430 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1431 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1432 *mipsIII:
1433 *mipsIV:
1434 *vr5000:
1435 // start-sanitize-vr4320
1436 *vr4320:
1437 // end-sanitize-vr4320
1438 // start-sanitize-vr5400
1439 *vr5400:
1440 // end-sanitize-vr5400
1441 // start-sanitize-r5900
1442 *r5900:
1443 // end-sanitize-r5900
1444 // start-sanitize-tx19
1445 *tx19:
1446 // end-sanitize-tx19
1447 {
1448 int s = 32 + SHIFT;
1449 GPR[RD] = (unsigned64) GPR[RT] >> s;
1450 }
1451
1452
1453 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1454 "dsrl32 r<RD>, r<RT>, r<RS>"
1455 *mipsIII:
1456 *mipsIV:
1457 *vr5000:
1458 // start-sanitize-vr4320
1459 *vr4320:
1460 // end-sanitize-vr4320
1461 // start-sanitize-vr5400
1462 *vr5400:
1463 // end-sanitize-vr5400
1464 // start-sanitize-r5900
1465 *r5900:
1466 // end-sanitize-r5900
1467 // start-sanitize-tx19
1468 *tx19:
1469 // end-sanitize-tx19
1470 {
1471 int s = MASKED64 (GPR[RS], 5, 0);
1472 GPR[RD] = (unsigned64) GPR[RT] >> s;
1473 }
1474
1475
1476 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1477 "dsub r<RD>, r<RS>, r<RT>"
1478 *mipsIII:
1479 *mipsIV:
1480 *vr5000:
1481 // start-sanitize-vr4320
1482 *vr4320:
1483 // end-sanitize-vr4320
1484 // start-sanitize-vr5400
1485 *vr5400:
1486 // end-sanitize-vr5400
1487 // start-sanitize-r5900
1488 *r5900:
1489 // end-sanitize-r5900
1490 // start-sanitize-tx19
1491 *tx19:
1492 // end-sanitize-tx19
1493 {
1494 ALU64_BEGIN (GPR[RS]);
1495 ALU64_SUB (GPR[RT]);
1496 ALU64_END (GPR[RD]);
1497 }
1498
1499
1500 :function:::void:do_dsubu:int rs, int rt, int rd
1501 {
1502 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1503 GPR[rd] = GPR[rs] - GPR[rt];
1504 TRACE_ALU_RESULT (GPR[rd]);
1505 }
1506
1507 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1508 "dsubu r<RD>, r<RS>, r<RT>"
1509 *mipsIII:
1510 *mipsIV:
1511 *vr5000:
1512 // start-sanitize-vr4320
1513 *vr4320:
1514 // end-sanitize-vr4320
1515 // start-sanitize-vr5400
1516 *vr5400:
1517 // end-sanitize-vr5400
1518 // start-sanitize-r5900
1519 *r5900:
1520 // end-sanitize-r5900
1521 // start-sanitize-tx19
1522 *tx19:
1523 // end-sanitize-tx19
1524 {
1525 do_dsubu (SD_, RS, RT, RD);
1526 }
1527
1528
1529 000010,26.INSTR_INDEX:NORMAL:32::J
1530 "j <INSTR_INDEX>"
1531 *mipsI,mipsII,mipsIII,mipsIV:
1532 *vr5000:
1533 // start-sanitize-vr4320
1534 *vr4320:
1535 // end-sanitize-vr4320
1536 // start-sanitize-vr5400
1537 *vr5400:
1538 // end-sanitize-vr5400
1539 // start-sanitize-r5900
1540 *r5900:
1541 // end-sanitize-r5900
1542 *r3900:
1543 // start-sanitize-tx19
1544 *tx19:
1545 // end-sanitize-tx19
1546 {
1547 /* NOTE: The region used is that of the delay slot NIA and NOT the
1548 current instruction */
1549 address_word region = (NIA & MASK (63, 28));
1550 DELAY_SLOT (region | (INSTR_INDEX << 2));
1551 }
1552
1553
1554 000011,26.INSTR_INDEX:NORMAL:32::JAL
1555 "jal <INSTR_INDEX>"
1556 *mipsI,mipsII,mipsIII,mipsIV:
1557 *vr5000:
1558 // start-sanitize-vr4320
1559 *vr4320:
1560 // end-sanitize-vr4320
1561 // start-sanitize-vr5400
1562 *vr5400:
1563 // end-sanitize-vr5400
1564 // start-sanitize-r5900
1565 *r5900:
1566 // end-sanitize-r5900
1567 *r3900:
1568 // start-sanitize-tx19
1569 *tx19:
1570 // end-sanitize-tx19
1571 {
1572 /* NOTE: The region used is that of the delay slot and NOT the
1573 current instruction */
1574 address_word region = (NIA & MASK (63, 28));
1575 GPR[31] = CIA + 8;
1576 DELAY_SLOT (region | (INSTR_INDEX << 2));
1577 }
1578
1579
1580 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1581 "jalr r<RS>":RD == 31
1582 "jalr r<RD>, r<RS>"
1583 *mipsI,mipsII,mipsIII,mipsIV:
1584 *vr5000:
1585 // start-sanitize-vr4320
1586 *vr4320:
1587 // end-sanitize-vr4320
1588 // start-sanitize-vr5400
1589 *vr5400:
1590 // end-sanitize-vr5400
1591 // start-sanitize-r5900
1592 *r5900:
1593 // end-sanitize-r5900
1594 *r3900:
1595 // start-sanitize-tx19
1596 *tx19:
1597 // end-sanitize-tx19
1598 {
1599 address_word temp = GPR[RS];
1600 GPR[RD] = CIA + 8;
1601 DELAY_SLOT (temp);
1602 }
1603
1604
1605 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1606 "jr r<RS>"
1607 *mipsI,mipsII,mipsIII,mipsIV:
1608 *vr5000:
1609 // start-sanitize-vr4320
1610 *vr4320:
1611 // end-sanitize-vr4320
1612 // start-sanitize-vr5400
1613 *vr5400:
1614 // end-sanitize-vr5400
1615 // start-sanitize-r5900
1616 *r5900:
1617 // end-sanitize-r5900
1618 *r3900:
1619 // start-sanitize-tx19
1620 *tx19:
1621 // end-sanitize-tx19
1622 {
1623 DELAY_SLOT (GPR[RS]);
1624 }
1625
1626
1627 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1628 {
1629 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1630 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1631 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1632 unsigned int byte;
1633 address_word paddr;
1634 int uncached;
1635 unsigned64 memval;
1636 address_word vaddr;
1637
1638 vaddr = base + offset;
1639 if ((vaddr & access) != 0)
1640 SignalExceptionAddressLoad ();
1641 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1642 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1643 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1644 byte = ((vaddr & mask) ^ bigendiancpu);
1645 return (memval >> (8 * byte));
1646 }
1647
1648
1649 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1650 "lb r<RT>, <OFFSET>(r<BASE>)"
1651 *mipsI,mipsII,mipsIII,mipsIV:
1652 *vr5000:
1653 // start-sanitize-vr4320
1654 *vr4320:
1655 // end-sanitize-vr4320
1656 // start-sanitize-vr5400
1657 *vr5400:
1658 // end-sanitize-vr5400
1659 // start-sanitize-r5900
1660 *r5900:
1661 // end-sanitize-r5900
1662 *r3900:
1663 // start-sanitize-tx19
1664 *tx19:
1665 // end-sanitize-tx19
1666 {
1667 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1668 }
1669
1670
1671 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1672 "lbu r<RT>, <OFFSET>(r<BASE>)"
1673 *mipsI,mipsII,mipsIII,mipsIV:
1674 *vr5000:
1675 // start-sanitize-vr4320
1676 *vr4320:
1677 // end-sanitize-vr4320
1678 // start-sanitize-vr5400
1679 *vr5400:
1680 // end-sanitize-vr5400
1681 // start-sanitize-r5900
1682 *r5900:
1683 // end-sanitize-r5900
1684 *r3900:
1685 // start-sanitize-tx19
1686 *tx19:
1687 // end-sanitize-tx19
1688 {
1689 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1690 }
1691
1692
1693 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1694 "ld r<RT>, <OFFSET>(r<BASE>)"
1695 *mipsIII:
1696 *mipsIV:
1697 *vr5000:
1698 // start-sanitize-vr4320
1699 *vr4320:
1700 // end-sanitize-vr4320
1701 // start-sanitize-vr5400
1702 *vr5400:
1703 // end-sanitize-vr5400
1704 // start-sanitize-r5900
1705 *r5900:
1706 // end-sanitize-r5900
1707 // start-sanitize-tx19
1708 *tx19:
1709 // end-sanitize-tx19
1710 {
1711 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1712 }
1713
1714
1715 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1716 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1717 *mipsII:
1718 *mipsIII:
1719 *mipsIV:
1720 *vr5000:
1721 // start-sanitize-vr4320
1722 *vr4320:
1723 // end-sanitize-vr4320
1724 // start-sanitize-vr5400
1725 *vr5400:
1726 // end-sanitize-vr5400
1727 *r3900:
1728 // start-sanitize-tx19
1729 *tx19:
1730 // end-sanitize-tx19
1731 {
1732 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1733 }
1734
1735
1736
1737
1738 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1739 "ldl r<RT>, <OFFSET>(r<BASE>)"
1740 *mipsIII:
1741 *mipsIV:
1742 *vr5000:
1743 // start-sanitize-vr4320
1744 *vr4320:
1745 // end-sanitize-vr4320
1746 // start-sanitize-vr5400
1747 *vr5400:
1748 // end-sanitize-vr5400
1749 // start-sanitize-r5900
1750 *r5900:
1751 // end-sanitize-r5900
1752 // start-sanitize-tx19
1753 *tx19:
1754 // end-sanitize-tx19
1755 {
1756 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1757 }
1758
1759
1760 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1761 "ldr r<RT>, <OFFSET>(r<BASE>)"
1762 *mipsIII:
1763 *mipsIV:
1764 *vr5000:
1765 // start-sanitize-vr4320
1766 *vr4320:
1767 // end-sanitize-vr4320
1768 // start-sanitize-vr5400
1769 *vr5400:
1770 // end-sanitize-vr5400
1771 // start-sanitize-r5900
1772 *r5900:
1773 // end-sanitize-r5900
1774 // start-sanitize-tx19
1775 *tx19:
1776 // end-sanitize-tx19
1777 {
1778 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1779 }
1780
1781
1782 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1783 "lh r<RT>, <OFFSET>(r<BASE>)"
1784 *mipsI,mipsII,mipsIII,mipsIV:
1785 *vr5000:
1786 // start-sanitize-vr4320
1787 *vr4320:
1788 // end-sanitize-vr4320
1789 // start-sanitize-vr5400
1790 *vr5400:
1791 // end-sanitize-vr5400
1792 // start-sanitize-r5900
1793 *r5900:
1794 // end-sanitize-r5900
1795 *r3900:
1796 // start-sanitize-tx19
1797 *tx19:
1798 // end-sanitize-tx19
1799 {
1800 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1801 }
1802
1803
1804 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1805 "lhu r<RT>, <OFFSET>(r<BASE>)"
1806 *mipsI,mipsII,mipsIII,mipsIV:
1807 *vr5000:
1808 // start-sanitize-vr4320
1809 *vr4320:
1810 // end-sanitize-vr4320
1811 // start-sanitize-vr5400
1812 *vr5400:
1813 // end-sanitize-vr5400
1814 // start-sanitize-r5900
1815 *r5900:
1816 // end-sanitize-r5900
1817 *r3900:
1818 // start-sanitize-tx19
1819 *tx19:
1820 // end-sanitize-tx19
1821 {
1822 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1823 }
1824
1825
1826 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1827 "ll r<RT>, <OFFSET>(r<BASE>)"
1828 *mipsII:
1829 *mipsIII:
1830 *mipsIV:
1831 *vr5000:
1832 // start-sanitize-vr4320
1833 *vr4320:
1834 // end-sanitize-vr4320
1835 // start-sanitize-vr5400
1836 *vr5400:
1837 // end-sanitize-vr5400
1838 // start-sanitize-r5900
1839 *r5900:
1840 // end-sanitize-r5900
1841 // start-sanitize-tx19
1842 *tx19:
1843 // end-sanitize-tx19
1844 {
1845 unsigned32 instruction = instruction_0;
1846 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1847 int destreg = ((instruction >> 16) & 0x0000001F);
1848 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1849 {
1850 address_word vaddr = ((unsigned64)op1 + offset);
1851 address_word paddr;
1852 int uncached;
1853 if ((vaddr & 3) != 0)
1854 SignalExceptionAddressLoad();
1855 else
1856 {
1857 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1858 {
1859 unsigned64 memval = 0;
1860 unsigned64 memval1 = 0;
1861 unsigned64 mask = 0x7;
1862 unsigned int shift = 2;
1863 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1864 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1865 unsigned int byte;
1866 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1867 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1868 byte = ((vaddr & mask) ^ (bigend << shift));
1869 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1870 LLBIT = 1;
1871 }
1872 }
1873 }
1874 }
1875
1876
1877 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1878 "lld r<RT>, <OFFSET>(r<BASE>)"
1879 *mipsIII:
1880 *mipsIV:
1881 *vr5000:
1882 // start-sanitize-vr4320
1883 *vr4320:
1884 // end-sanitize-vr4320
1885 // start-sanitize-vr5400
1886 *vr5400:
1887 // end-sanitize-vr5400
1888 // start-sanitize-r5900
1889 *r5900:
1890 // end-sanitize-r5900
1891 // start-sanitize-tx19
1892 *tx19:
1893 // end-sanitize-tx19
1894 {
1895 unsigned32 instruction = instruction_0;
1896 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1897 int destreg = ((instruction >> 16) & 0x0000001F);
1898 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1899 {
1900 address_word vaddr = ((unsigned64)op1 + offset);
1901 address_word paddr;
1902 int uncached;
1903 if ((vaddr & 7) != 0)
1904 SignalExceptionAddressLoad();
1905 else
1906 {
1907 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1908 {
1909 unsigned64 memval = 0;
1910 unsigned64 memval1 = 0;
1911 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1912 GPR[destreg] = memval;
1913 LLBIT = 1;
1914 }
1915 }
1916 }
1917 }
1918
1919
1920 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1921 "lui r<RT>, <IMMEDIATE>"
1922 *mipsI,mipsII,mipsIII,mipsIV:
1923 *vr5000:
1924 // start-sanitize-vr4320
1925 *vr4320:
1926 // end-sanitize-vr4320
1927 // start-sanitize-vr5400
1928 *vr5400:
1929 // end-sanitize-vr5400
1930 // start-sanitize-r5900
1931 *r5900:
1932 // end-sanitize-r5900
1933 *r3900:
1934 // start-sanitize-tx19
1935 *tx19:
1936 // end-sanitize-tx19
1937 {
1938 TRACE_ALU_INPUT1 (IMMEDIATE);
1939 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1940 TRACE_ALU_RESULT (GPR[RT]);
1941 }
1942
1943
1944 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1945 "lw r<RT>, <OFFSET>(r<BASE>)"
1946 *mipsI,mipsII,mipsIII,mipsIV:
1947 *vr5000:
1948 // start-sanitize-vr4320
1949 *vr4320:
1950 // end-sanitize-vr4320
1951 // start-sanitize-vr5400
1952 *vr5400:
1953 // end-sanitize-vr5400
1954 // start-sanitize-r5900
1955 *r5900:
1956 // end-sanitize-r5900
1957 *r3900:
1958 // start-sanitize-tx19
1959 *tx19:
1960 // end-sanitize-tx19
1961 {
1962 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1963 }
1964
1965
1966 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1967 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1968 *mipsI,mipsII,mipsIII,mipsIV:
1969 *vr5000:
1970 // start-sanitize-vr4320
1971 *vr4320:
1972 // end-sanitize-vr4320
1973 // start-sanitize-vr5400
1974 *vr5400:
1975 // end-sanitize-vr5400
1976 // start-sanitize-r5900
1977 *r5900:
1978 // end-sanitize-r5900
1979 *r3900:
1980 // start-sanitize-tx19
1981 *tx19:
1982 // end-sanitize-tx19
1983 {
1984 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1985 }
1986
1987
1988 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1989 {
1990 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1991 address_word reverseendian = (ReverseEndian ? -1 : 0);
1992 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1993 unsigned int byte;
1994 address_word paddr;
1995 int uncached;
1996 unsigned64 memval;
1997 address_word vaddr;
1998
1999 vaddr = base + offset;
2000 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2001 paddr = (paddr ^ (reverseendian & mask));
2002 if (BigEndianMem == 0)
2003 paddr = paddr & ~access;
2004 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2005 LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
2006 /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
2007 (long) vaddr, byte, (long) paddr, (long) memval); */
2008 if ((byte & ~access) == 0)
2009 {
2010 int bits = 8 * (access - byte);
2011 unsigned_word screen = LSMASK (bits - 1, 0);
2012 rt &= screen;
2013 rt |= ((memval << bits) & ~screen);
2014 }
2015 else
2016 {
2017 unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
2018 rt &= screen;
2019 rt |= ((memval >> (8 * (mask - byte))) & ~screen);
2020 }
2021 return rt;
2022 }
2023
2024
2025 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2026 "lwl r<RT>, <OFFSET>(r<BASE>)"
2027 *mipsI,mipsII,mipsIII,mipsIV:
2028 *vr5000:
2029 // start-sanitize-vr4320
2030 *vr4320:
2031 // end-sanitize-vr4320
2032 // start-sanitize-vr5400
2033 *vr5400:
2034 // end-sanitize-vr5400
2035 // start-sanitize-r5900
2036 *r5900:
2037 // end-sanitize-r5900
2038 *r3900:
2039 // start-sanitize-tx19
2040 *tx19:
2041 // end-sanitize-tx19
2042 {
2043 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2044 }
2045
2046
2047 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2048 {
2049 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2050 address_word reverseendian = (ReverseEndian ? -1 : 0);
2051 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2052 unsigned int byte;
2053 address_word paddr;
2054 int uncached;
2055 unsigned64 memval;
2056 address_word vaddr;
2057
2058 vaddr = base + offset;
2059 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2060 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2061 paddr = (paddr ^ (reverseendian & mask));
2062 if (BigEndianMem != 0)
2063 paddr = paddr & ~access;
2064 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2065 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2066 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2067 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2068 (long) paddr, byte, (long) paddr, (long) memval); */
2069 {
2070 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2071 rt &= ~screen;
2072 rt |= (memval >> (8 * byte)) & screen;
2073 }
2074 return rt;
2075 }
2076
2077
2078 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2079 "lwr r<RT>, <OFFSET>(r<BASE>)"
2080 *mipsI,mipsII,mipsIII,mipsIV:
2081 *vr5000:
2082 // start-sanitize-vr4320
2083 *vr4320:
2084 // end-sanitize-vr4320
2085 // start-sanitize-vr5400
2086 *vr5400:
2087 // end-sanitize-vr5400
2088 // start-sanitize-r5900
2089 *r5900:
2090 // end-sanitize-r5900
2091 *r3900:
2092 // start-sanitize-tx19
2093 *tx19:
2094 // end-sanitize-tx19
2095 {
2096 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2097 }
2098
2099
2100 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2101 "lwu r<RT>, <OFFSET>(r<BASE>)"
2102 *mipsIII:
2103 *mipsIV:
2104 *vr5000:
2105 // start-sanitize-vr4320
2106 *vr4320:
2107 // end-sanitize-vr4320
2108 // start-sanitize-vr5400
2109 *vr5400:
2110 // end-sanitize-vr5400
2111 // start-sanitize-r5900
2112 *r5900:
2113 // end-sanitize-r5900
2114 // start-sanitize-tx19
2115 *tx19:
2116 // end-sanitize-tx19
2117 {
2118 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2119 }
2120
2121
2122 :function:::void:do_mfhi:int rd
2123 {
2124 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2125 TRACE_ALU_INPUT1 (HI);
2126 GPR[rd] = HI;
2127 TRACE_ALU_RESULT (GPR[rd]);
2128 }
2129
2130 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2131 "mfhi r<RD>"
2132 *mipsI,mipsII,mipsIII,mipsIV:
2133 *vr5000:
2134 // start-sanitize-vr4320
2135 *vr4320:
2136 // end-sanitize-vr4320
2137 // start-sanitize-vr5400
2138 *vr5400:
2139 // end-sanitize-vr5400
2140 // start-sanitize-r5900
2141 *r5900:
2142 // end-sanitize-r5900
2143 *r3900:
2144 // start-sanitize-tx19
2145 *tx19:
2146 // end-sanitize-tx19
2147 {
2148 do_mfhi (SD_, RD);
2149 }
2150
2151
2152
2153 :function:::void:do_mflo:int rd
2154 {
2155 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2156 TRACE_ALU_INPUT1 (LO);
2157 GPR[rd] = LO;
2158 TRACE_ALU_RESULT (GPR[rd]);
2159 }
2160
2161 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2162 "mflo r<RD>"
2163 *mipsI,mipsII,mipsIII,mipsIV:
2164 *vr5000:
2165 // start-sanitize-vr4320
2166 *vr4320:
2167 // end-sanitize-vr4320
2168 // start-sanitize-vr5400
2169 *vr5400:
2170 // end-sanitize-vr5400
2171 // start-sanitize-r5900
2172 *r5900:
2173 // end-sanitize-r5900
2174 *r3900:
2175 // start-sanitize-tx19
2176 *tx19:
2177 // end-sanitize-tx19
2178 {
2179 do_mflo (SD_, RD);
2180 }
2181
2182
2183
2184 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2185 "movn r<RD>, r<RS>, r<RT>"
2186 *mipsIV:
2187 *vr5000:
2188 // start-sanitize-vr4320
2189 *vr4320:
2190 // end-sanitize-vr4320
2191 // start-sanitize-vr5400
2192 *vr5400:
2193 // end-sanitize-vr5400
2194 // start-sanitize-r5900
2195 *r5900:
2196 // end-sanitize-r5900
2197 {
2198 if (GPR[RT] != 0)
2199 GPR[RD] = GPR[RS];
2200 }
2201
2202
2203
2204 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2205 "movz r<RD>, r<RS>, r<RT>"
2206 *mipsIV:
2207 *vr5000:
2208 // start-sanitize-vr4320
2209 *vr4320:
2210 // end-sanitize-vr4320
2211 // start-sanitize-vr5400
2212 *vr5400:
2213 // end-sanitize-vr5400
2214 // start-sanitize-r5900
2215 *r5900:
2216 // end-sanitize-r5900
2217 {
2218 if (GPR[RT] == 0)
2219 GPR[RD] = GPR[RS];
2220 }
2221
2222
2223
2224 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2225 "mthi r<RS>"
2226 *mipsI,mipsII,mipsIII,mipsIV:
2227 *vr5000:
2228 // start-sanitize-vr4320
2229 *vr4320:
2230 // end-sanitize-vr4320
2231 // start-sanitize-vr5400
2232 *vr5400:
2233 // end-sanitize-vr5400
2234 // start-sanitize-r5900
2235 *r5900:
2236 // end-sanitize-r5900
2237 *r3900:
2238 // start-sanitize-tx19
2239 *tx19:
2240 // end-sanitize-tx19
2241 {
2242 check_mt_hilo (SD_, HIHISTORY);
2243 HI = GPR[RS];
2244 }
2245
2246
2247
2248 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2249 "mtlo r<RS>"
2250 *mipsI,mipsII,mipsIII,mipsIV:
2251 *vr5000:
2252 // start-sanitize-vr4320
2253 *vr4320:
2254 // end-sanitize-vr4320
2255 // start-sanitize-vr5400
2256 *vr5400:
2257 // end-sanitize-vr5400
2258 // start-sanitize-r5900
2259 *r5900:
2260 // end-sanitize-r5900
2261 *r3900:
2262 // start-sanitize-tx19
2263 *tx19:
2264 // end-sanitize-tx19
2265 {
2266 check_mt_hilo (SD_, LOHISTORY);
2267 LO = GPR[RS];
2268 }
2269
2270
2271
2272 :function:::void:do_mult:int rs, int rt, int rd
2273 {
2274 signed64 prod;
2275 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
2276 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2277 prod = (((signed64)(signed32) GPR[rs])
2278 * ((signed64)(signed32) GPR[rt]));
2279 LO = EXTEND32 (VL4_8 (prod));
2280 HI = EXTEND32 (VH4_8 (prod));
2281 if (rd != 0)
2282 GPR[rd] = LO;
2283 TRACE_ALU_RESULT2 (HI, LO);
2284 }
2285
2286 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2287 "mult r<RS>, r<RT>"
2288 *mipsI,mipsII,mipsIII,mipsIV:
2289 // start-sanitize-vr4320
2290 *vr4320:
2291 // end-sanitize-vr4320
2292 {
2293 do_mult (SD_, RS, RT, 0);
2294 }
2295
2296
2297 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2298 "mult r<RD>, r<RS>, r<RT>"
2299 *vr5000:
2300 // start-sanitize-vr5400
2301 *vr5400:
2302 // end-sanitize-vr5400
2303 // start-sanitize-r5900
2304 *r5900:
2305 // end-sanitize-r5900
2306 *r3900:
2307 // start-sanitize-tx19
2308 *tx19:
2309 // end-sanitize-tx19
2310 {
2311 do_mult (SD_, RS, RT, RD);
2312 }
2313
2314
2315 :function:::void:do_multu:int rs, int rt, int rd
2316 {
2317 unsigned64 prod;
2318 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
2319 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2320 prod = (((unsigned64)(unsigned32) GPR[rs])
2321 * ((unsigned64)(unsigned32) GPR[rt]));
2322 LO = EXTEND32 (VL4_8 (prod));
2323 HI = EXTEND32 (VH4_8 (prod));
2324 if (rd != 0)
2325 GPR[rd] = LO;
2326 TRACE_ALU_RESULT2 (HI, LO);
2327 }
2328
2329 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2330 "multu r<RS>, r<RT>"
2331 *mipsI,mipsII,mipsIII,mipsIV:
2332 // start-sanitize-vr4320
2333 *vr4320:
2334 // end-sanitize-vr4320
2335 {
2336 do_multu (SD_, RS, RT, 0);
2337 }
2338
2339 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2340 "multu r<RD>, r<RS>, r<RT>"
2341 *vr5000:
2342 // start-sanitize-vr5400
2343 *vr5400:
2344 // end-sanitize-vr5400
2345 // start-sanitize-r5900
2346 *r5900:
2347 // end-sanitize-r5900
2348 *r3900:
2349 // start-sanitize-tx19
2350 *tx19:
2351 // end-sanitize-tx19
2352 {
2353 do_multu (SD_, RS, RT, 0);
2354 }
2355
2356
2357 :function:::void:do_nor:int rs, int rt, int rd
2358 {
2359 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2360 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2361 TRACE_ALU_RESULT (GPR[rd]);
2362 }
2363
2364 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2365 "nor r<RD>, r<RS>, r<RT>"
2366 *mipsI,mipsII,mipsIII,mipsIV:
2367 *vr5000:
2368 // start-sanitize-vr4320
2369 *vr4320:
2370 // end-sanitize-vr4320
2371 // start-sanitize-vr5400
2372 *vr5400:
2373 // end-sanitize-vr5400
2374 // start-sanitize-r5900
2375 *r5900:
2376 // end-sanitize-r5900
2377 *r3900:
2378 // start-sanitize-tx19
2379 *tx19:
2380 // end-sanitize-tx19
2381 {
2382 do_nor (SD_, RS, RT, RD);
2383 }
2384
2385
2386 :function:::void:do_or:int rs, int rt, int rd
2387 {
2388 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2389 GPR[rd] = (GPR[rs] | GPR[rt]);
2390 TRACE_ALU_RESULT (GPR[rd]);
2391 }
2392
2393 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2394 "or r<RD>, r<RS>, r<RT>"
2395 *mipsI,mipsII,mipsIII,mipsIV:
2396 *vr5000:
2397 // start-sanitize-vr4320
2398 *vr4320:
2399 // end-sanitize-vr4320
2400 // start-sanitize-vr5400
2401 *vr5400:
2402 // end-sanitize-vr5400
2403 // start-sanitize-r5900
2404 *r5900:
2405 // end-sanitize-r5900
2406 *r3900:
2407 // start-sanitize-tx19
2408 *tx19:
2409 // end-sanitize-tx19
2410 {
2411 do_or (SD_, RS, RT, RD);
2412 }
2413
2414
2415
2416 :function:::void:do_ori:int rs, int rt, unsigned immediate
2417 {
2418 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2419 GPR[rt] = (GPR[rs] | immediate);
2420 TRACE_ALU_RESULT (GPR[rt]);
2421 }
2422
2423 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2424 "ori r<RT>, r<RS>, <IMMEDIATE>"
2425 *mipsI,mipsII,mipsIII,mipsIV:
2426 *vr5000:
2427 // start-sanitize-vr4320
2428 *vr4320:
2429 // end-sanitize-vr4320
2430 // start-sanitize-vr5400
2431 *vr5400:
2432 // end-sanitize-vr5400
2433 // start-sanitize-r5900
2434 *r5900:
2435 // end-sanitize-r5900
2436 *r3900:
2437 // start-sanitize-tx19
2438 *tx19:
2439 // end-sanitize-tx19
2440 {
2441 do_ori (SD_, RS, RT, IMMEDIATE);
2442 }
2443
2444
2445 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2446 *mipsIV:
2447 *vr5000:
2448 // start-sanitize-vr4320
2449 *vr4320:
2450 // end-sanitize-vr4320
2451 // start-sanitize-vr5400
2452 *vr5400:
2453 // end-sanitize-vr5400
2454 // start-sanitize-r5900
2455 *r5900:
2456 // end-sanitize-r5900
2457 {
2458 unsigned32 instruction = instruction_0;
2459 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2460 int hint = ((instruction >> 16) & 0x0000001F);
2461 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2462 {
2463 address_word vaddr = ((unsigned64)op1 + offset);
2464 address_word paddr;
2465 int uncached;
2466 {
2467 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2468 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2469 }
2470 }
2471 }
2472
2473 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2474 {
2475 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2476 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2477 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2478 unsigned int byte;
2479 address_word paddr;
2480 int uncached;
2481 unsigned64 memval;
2482 address_word vaddr;
2483
2484 vaddr = base + offset;
2485 if ((vaddr & access) != 0)
2486 SignalExceptionAddressStore ();
2487 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2488 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2489 byte = ((vaddr & mask) ^ bigendiancpu);
2490 memval = (word << (8 * byte));
2491 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2492 }
2493
2494
2495 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2496 "sb r<RT>, <OFFSET>(r<BASE>)"
2497 *mipsI,mipsII,mipsIII,mipsIV:
2498 *vr5000:
2499 // start-sanitize-vr4320
2500 *vr4320:
2501 // end-sanitize-vr4320
2502 // start-sanitize-vr5400
2503 *vr5400:
2504 // end-sanitize-vr5400
2505 // start-sanitize-r5900
2506 *r5900:
2507 // end-sanitize-r5900
2508 *r3900:
2509 // start-sanitize-tx19
2510 *tx19:
2511 // end-sanitize-tx19
2512 {
2513 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2514 }
2515
2516
2517 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2518 "sc r<RT>, <OFFSET>(r<BASE>)"
2519 *mipsII:
2520 *mipsIII:
2521 *mipsIV:
2522 *vr5000:
2523 // start-sanitize-vr4320
2524 *vr4320:
2525 // end-sanitize-vr4320
2526 // start-sanitize-vr5400
2527 *vr5400:
2528 // end-sanitize-vr5400
2529 // start-sanitize-r5900
2530 *r5900:
2531 // end-sanitize-r5900
2532 // start-sanitize-tx19
2533 *tx19:
2534 // end-sanitize-tx19
2535 {
2536 unsigned32 instruction = instruction_0;
2537 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2538 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2539 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2540 {
2541 address_word vaddr = ((unsigned64)op1 + offset);
2542 address_word paddr;
2543 int uncached;
2544 if ((vaddr & 3) != 0)
2545 SignalExceptionAddressStore();
2546 else
2547 {
2548 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2549 {
2550 unsigned64 memval = 0;
2551 unsigned64 memval1 = 0;
2552 unsigned64 mask = 0x7;
2553 unsigned int byte;
2554 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2555 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2556 memval = ((unsigned64) op2 << (8 * byte));
2557 if (LLBIT)
2558 {
2559 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2560 }
2561 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2562 }
2563 }
2564 }
2565 }
2566
2567
2568 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2569 "scd r<RT>, <OFFSET>(r<BASE>)"
2570 *mipsIII:
2571 *mipsIV:
2572 *vr5000:
2573 // start-sanitize-vr4320
2574 *vr4320:
2575 // end-sanitize-vr4320
2576 // start-sanitize-vr5400
2577 *vr5400:
2578 // end-sanitize-vr5400
2579 // start-sanitize-r5900
2580 *r5900:
2581 // end-sanitize-r5900
2582 // start-sanitize-tx19
2583 *tx19:
2584 // end-sanitize-tx19
2585 {
2586 unsigned32 instruction = instruction_0;
2587 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2588 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2589 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2590 {
2591 address_word vaddr = ((unsigned64)op1 + offset);
2592 address_word paddr;
2593 int uncached;
2594 if ((vaddr & 7) != 0)
2595 SignalExceptionAddressStore();
2596 else
2597 {
2598 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2599 {
2600 unsigned64 memval = 0;
2601 unsigned64 memval1 = 0;
2602 memval = op2;
2603 if (LLBIT)
2604 {
2605 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2606 }
2607 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2608 }
2609 }
2610 }
2611 }
2612
2613
2614 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2615 "sd r<RT>, <OFFSET>(r<BASE>)"
2616 *mipsIII:
2617 *mipsIV:
2618 *vr5000:
2619 // start-sanitize-vr4320
2620 *vr4320:
2621 // end-sanitize-vr4320
2622 // start-sanitize-vr5400
2623 *vr5400:
2624 // end-sanitize-vr5400
2625 // start-sanitize-r5900
2626 *r5900:
2627 // end-sanitize-r5900
2628 // start-sanitize-tx19
2629 *tx19:
2630 // end-sanitize-tx19
2631 {
2632 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2633 }
2634
2635
2636 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2637 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2638 *mipsII:
2639 *mipsIII:
2640 *mipsIV:
2641 *vr5000:
2642 // start-sanitize-vr4320
2643 *vr4320:
2644 // end-sanitize-vr4320
2645 // start-sanitize-vr5400
2646 *vr5400:
2647 // end-sanitize-vr5400
2648 // start-sanitize-r5900
2649 *r5900:
2650 // end-sanitize-r5900
2651 // start-sanitize-tx19
2652 *tx19:
2653 // end-sanitize-tx19
2654 {
2655 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2656 }
2657
2658
2659 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2660 "sdl r<RT>, <OFFSET>(r<BASE>)"
2661 *mipsIII:
2662 *mipsIV:
2663 *vr5000:
2664 // start-sanitize-vr4320
2665 *vr4320:
2666 // end-sanitize-vr4320
2667 // start-sanitize-vr5400
2668 *vr5400:
2669 // end-sanitize-vr5400
2670 // start-sanitize-r5900
2671 *r5900:
2672 // end-sanitize-r5900
2673 // start-sanitize-tx19
2674 *tx19:
2675 // end-sanitize-tx19
2676 {
2677 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2678 }
2679
2680
2681 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2682 "sdr r<RT>, <OFFSET>(r<BASE>)"
2683 *mipsIII:
2684 *mipsIV:
2685 *vr5000:
2686 // start-sanitize-vr4320
2687 *vr4320:
2688 // end-sanitize-vr4320
2689 // start-sanitize-vr5400
2690 *vr5400:
2691 // end-sanitize-vr5400
2692 // start-sanitize-r5900
2693 *r5900:
2694 // end-sanitize-r5900
2695 // start-sanitize-tx19
2696 *tx19:
2697 // end-sanitize-tx19
2698 {
2699 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2700 }
2701
2702
2703 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2704 "sh r<RT>, <OFFSET>(r<BASE>)"
2705 *mipsI,mipsII,mipsIII,mipsIV:
2706 *vr5000:
2707 // start-sanitize-vr4320
2708 *vr4320:
2709 // end-sanitize-vr4320
2710 // start-sanitize-vr5400
2711 *vr5400:
2712 // end-sanitize-vr5400
2713 // start-sanitize-r5900
2714 *r5900:
2715 // end-sanitize-r5900
2716 *r3900:
2717 // start-sanitize-tx19
2718 *tx19:
2719 // end-sanitize-tx19
2720 {
2721 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2722 }
2723
2724
2725 :function:::void:do_sll:int rt, int rd, int shift
2726 {
2727 unsigned32 temp = (GPR[rt] << shift);
2728 TRACE_ALU_INPUT2 (GPR[rt], shift);
2729 GPR[rd] = EXTEND32 (temp);
2730 TRACE_ALU_RESULT (GPR[rd]);
2731 }
2732
2733 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2734 "sll r<RD>, r<RT>, <SHIFT>"
2735 *mipsI,mipsII,mipsIII,mipsIV:
2736 *vr5000:
2737 // start-sanitize-vr4320
2738 *vr4320:
2739 // end-sanitize-vr4320
2740 // start-sanitize-vr5400
2741 *vr5400:
2742 // end-sanitize-vr5400
2743 // start-sanitize-r5900
2744 *r5900:
2745 // end-sanitize-r5900
2746 *r3900:
2747 // start-sanitize-tx19
2748 *tx19:
2749 // end-sanitize-tx19
2750 {
2751 do_sll (SD_, RT, RD, SHIFT);
2752 }
2753
2754
2755 :function:::void:do_sllv:int rs, int rt, int rd
2756 {
2757 int s = MASKED (GPR[rs], 4, 0);
2758 unsigned32 temp = (GPR[rt] << s);
2759 TRACE_ALU_INPUT2 (GPR[rt], s);
2760 GPR[rd] = EXTEND32 (temp);
2761 TRACE_ALU_RESULT (GPR[rd]);
2762 }
2763
2764 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2765 "sllv r<RD>, r<RT>, r<RS>"
2766 *mipsI,mipsII,mipsIII,mipsIV:
2767 *vr5000:
2768 // start-sanitize-vr4320
2769 *vr4320:
2770 // end-sanitize-vr4320
2771 // start-sanitize-vr5400
2772 *vr5400:
2773 // end-sanitize-vr5400
2774 // start-sanitize-r5900
2775 *r5900:
2776 // end-sanitize-r5900
2777 *r3900:
2778 // start-sanitize-tx19
2779 *tx19:
2780 // end-sanitize-tx19
2781 {
2782 do_sllv (SD_, RS, RT, RD);
2783 }
2784
2785
2786 :function:::void:do_slt:int rs, int rt, int rd
2787 {
2788 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2789 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2790 TRACE_ALU_RESULT (GPR[rd]);
2791 }
2792
2793 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2794 "slt r<RD>, r<RS>, r<RT>"
2795 *mipsI,mipsII,mipsIII,mipsIV:
2796 *vr5000:
2797 // start-sanitize-vr4320
2798 *vr4320:
2799 // end-sanitize-vr4320
2800 // start-sanitize-vr5400
2801 *vr5400:
2802 // end-sanitize-vr5400
2803 // start-sanitize-r5900
2804 *r5900:
2805 // end-sanitize-r5900
2806 *r3900:
2807 // start-sanitize-tx19
2808 *tx19:
2809 // end-sanitize-tx19
2810 {
2811 do_slt (SD_, RS, RT, RD);
2812 }
2813
2814
2815 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2816 {
2817 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2818 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2819 TRACE_ALU_RESULT (GPR[rt]);
2820 }
2821
2822 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2823 "slti r<RT>, r<RS>, <IMMEDIATE>"
2824 *mipsI,mipsII,mipsIII,mipsIV:
2825 *vr5000:
2826 // start-sanitize-vr4320
2827 *vr4320:
2828 // end-sanitize-vr4320
2829 // start-sanitize-vr5400
2830 *vr5400:
2831 // end-sanitize-vr5400
2832 // start-sanitize-r5900
2833 *r5900:
2834 // end-sanitize-r5900
2835 *r3900:
2836 // start-sanitize-tx19
2837 *tx19:
2838 // end-sanitize-tx19
2839 {
2840 do_slti (SD_, RS, RT, IMMEDIATE);
2841 }
2842
2843
2844 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2845 {
2846 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2847 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2848 TRACE_ALU_RESULT (GPR[rt]);
2849 }
2850
2851 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2852 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2853 *mipsI,mipsII,mipsIII,mipsIV:
2854 *vr5000:
2855 // start-sanitize-vr4320
2856 *vr4320:
2857 // end-sanitize-vr4320
2858 // start-sanitize-vr5400
2859 *vr5400:
2860 // end-sanitize-vr5400
2861 // start-sanitize-r5900
2862 *r5900:
2863 // end-sanitize-r5900
2864 *r3900:
2865 // start-sanitize-tx19
2866 *tx19:
2867 // end-sanitize-tx19
2868 {
2869 do_sltiu (SD_, RS, RT, IMMEDIATE);
2870 }
2871
2872
2873
2874 :function:::void:do_sltu:int rs, int rt, int rd
2875 {
2876 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2877 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2878 TRACE_ALU_RESULT (GPR[rd]);
2879 }
2880
2881 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2882 "sltu r<RD>, r<RS>, r<RT>"
2883 *mipsI,mipsII,mipsIII,mipsIV:
2884 *vr5000:
2885 // start-sanitize-vr4320
2886 *vr4320:
2887 // end-sanitize-vr4320
2888 // start-sanitize-vr5400
2889 *vr5400:
2890 // end-sanitize-vr5400
2891 // start-sanitize-r5900
2892 *r5900:
2893 // end-sanitize-r5900
2894 *r3900:
2895 // start-sanitize-tx19
2896 *tx19:
2897 // end-sanitize-tx19
2898 {
2899 do_sltu (SD_, RS, RT, RD);
2900 }
2901
2902
2903 :function:::void:do_sra:int rt, int rd, int shift
2904 {
2905 signed32 temp = (signed32) GPR[rt] >> shift;
2906 TRACE_ALU_INPUT2 (GPR[rt], shift);
2907 GPR[rd] = EXTEND32 (temp);
2908 TRACE_ALU_RESULT (GPR[rd]);
2909 }
2910
2911 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2912 "sra r<RD>, r<RT>, <SHIFT>"
2913 *mipsI,mipsII,mipsIII,mipsIV:
2914 *vr5000:
2915 // start-sanitize-vr4320
2916 *vr4320:
2917 // end-sanitize-vr4320
2918 // start-sanitize-vr5400
2919 *vr5400:
2920 // end-sanitize-vr5400
2921 // start-sanitize-r5900
2922 *r5900:
2923 // end-sanitize-r5900
2924 *r3900:
2925 // start-sanitize-tx19
2926 *tx19:
2927 // end-sanitize-tx19
2928 {
2929 do_sra (SD_, RT, RD, SHIFT);
2930 }
2931
2932
2933
2934 :function:::void:do_srav:int rs, int rt, int rd
2935 {
2936 int s = MASKED (GPR[rs], 4, 0);
2937 signed32 temp = (signed32) GPR[rt] >> s;
2938 TRACE_ALU_INPUT2 (GPR[rt], s);
2939 GPR[rd] = EXTEND32 (temp);
2940 TRACE_ALU_RESULT (GPR[rd]);
2941 }
2942
2943 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2944 "srav r<RD>, r<RT>, r<RS>"
2945 *mipsI,mipsII,mipsIII,mipsIV:
2946 *vr5000:
2947 // start-sanitize-vr4320
2948 *vr4320:
2949 // end-sanitize-vr4320
2950 // start-sanitize-vr5400
2951 *vr5400:
2952 // end-sanitize-vr5400
2953 // start-sanitize-r5900
2954 *r5900:
2955 // end-sanitize-r5900
2956 *r3900:
2957 // start-sanitize-tx19
2958 *tx19:
2959 // end-sanitize-tx19
2960 {
2961 do_srav (SD_, RS, RT, RD);
2962 }
2963
2964
2965
2966 :function:::void:do_srl:int rt, int rd, int shift
2967 {
2968 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2969 TRACE_ALU_INPUT2 (GPR[rt], shift);
2970 GPR[rd] = EXTEND32 (temp);
2971 TRACE_ALU_RESULT (GPR[rd]);
2972 }
2973
2974 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2975 "srl r<RD>, r<RT>, <SHIFT>"
2976 *mipsI,mipsII,mipsIII,mipsIV:
2977 *vr5000:
2978 // start-sanitize-vr4320
2979 *vr4320:
2980 // end-sanitize-vr4320
2981 // start-sanitize-vr5400
2982 *vr5400:
2983 // end-sanitize-vr5400
2984 // start-sanitize-r5900
2985 *r5900:
2986 // end-sanitize-r5900
2987 *r3900:
2988 // start-sanitize-tx19
2989 *tx19:
2990 // end-sanitize-tx19
2991 {
2992 do_srl (SD_, RT, RD, SHIFT);
2993 }
2994
2995
2996 :function:::void:do_srlv:int rs, int rt, int rd
2997 {
2998 int s = MASKED (GPR[rs], 4, 0);
2999 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3000 TRACE_ALU_INPUT2 (GPR[rt], s);
3001 GPR[rd] = EXTEND32 (temp);
3002 TRACE_ALU_RESULT (GPR[rd]);
3003 }
3004
3005 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3006 "srlv r<RD>, r<RT>, r<RS>"
3007 *mipsI,mipsII,mipsIII,mipsIV:
3008 *vr5000:
3009 // start-sanitize-vr4320
3010 *vr4320:
3011 // end-sanitize-vr4320
3012 // start-sanitize-vr5400
3013 *vr5400:
3014 // end-sanitize-vr5400
3015 // start-sanitize-r5900
3016 *r5900:
3017 // end-sanitize-r5900
3018 *r3900:
3019 // start-sanitize-tx19
3020 *tx19:
3021 // end-sanitize-tx19
3022 {
3023 do_srlv (SD_, RS, RT, RD);
3024 }
3025
3026
3027 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3028 "sub r<RD>, r<RS>, r<RT>"
3029 *mipsI,mipsII,mipsIII,mipsIV:
3030 *vr5000:
3031 // start-sanitize-vr4320
3032 *vr4320:
3033 // end-sanitize-vr4320
3034 // start-sanitize-vr5400
3035 *vr5400:
3036 // end-sanitize-vr5400
3037 // start-sanitize-r5900
3038 *r5900:
3039 // end-sanitize-r5900
3040 *r3900:
3041 // start-sanitize-tx19
3042 *tx19:
3043 // end-sanitize-tx19
3044 {
3045 ALU32_BEGIN (GPR[RS]);
3046 ALU32_SUB (GPR[RT]);
3047 ALU32_END (GPR[RD]);
3048 }
3049
3050
3051 :function:::void:do_subu:int rs, int rt, int rd
3052 {
3053 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3054 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3055 TRACE_ALU_RESULT (GPR[rd]);
3056 }
3057
3058 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3059 "subu r<RD>, r<RS>, r<RT>"
3060 *mipsI,mipsII,mipsIII,mipsIV:
3061 *vr5000:
3062 // start-sanitize-vr4320
3063 *vr4320:
3064 // end-sanitize-vr4320
3065 // start-sanitize-vr5400
3066 *vr5400:
3067 // end-sanitize-vr5400
3068 // start-sanitize-r5900
3069 *r5900:
3070 // end-sanitize-r5900
3071 *r3900:
3072 // start-sanitize-tx19
3073 *tx19:
3074 // end-sanitize-tx19
3075 {
3076 do_subu (SD_, RS, RT, RD);
3077 }
3078
3079
3080 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3081 "sw r<RT>, <OFFSET>(r<BASE>)"
3082 *mipsI,mipsII,mipsIII,mipsIV:
3083 // start-sanitize-tx19
3084 *tx19:
3085 // end-sanitize-tx19
3086 *r3900:
3087 // start-sanitize-vr4320
3088 *vr4320:
3089 // end-sanitize-vr4320
3090 *vr5000:
3091 // start-sanitize-vr5400
3092 *vr5400:
3093 // end-sanitize-vr5400
3094 // start-sanitize-r5900
3095 *r5900:
3096 // end-sanitize-r5900
3097 {
3098 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3099 }
3100
3101
3102 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3103 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3104 *mipsI,mipsII,mipsIII,mipsIV:
3105 *vr5000:
3106 // start-sanitize-vr4320
3107 *vr4320:
3108 // end-sanitize-vr4320
3109 // start-sanitize-vr5400
3110 *vr5400:
3111 // end-sanitize-vr5400
3112 *r3900:
3113 // start-sanitize-tx19
3114 *tx19:
3115 // end-sanitize-tx19
3116 {
3117 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3118 }
3119
3120
3121
3122 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3123 {
3124 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3125 address_word reverseendian = (ReverseEndian ? -1 : 0);
3126 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3127 unsigned int byte;
3128 address_word paddr;
3129 int uncached;
3130 unsigned64 memval;
3131 address_word vaddr;
3132
3133 vaddr = base + offset;
3134 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3135 paddr = (paddr ^ (reverseendian & mask));
3136 if (BigEndianMem == 0)
3137 paddr = paddr & ~access;
3138 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3139 if ((byte & ~access) == 0)
3140 memval = (rt >> (8 * (access - byte)));
3141 else
3142 memval = (rt << (8 * (mask - byte)));
3143 StoreMemory (uncached, byte & access, memval, NULL, paddr, vaddr, isREAL);
3144 }
3145
3146
3147 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3148 "swl r<RT>, <OFFSET>(r<BASE>)"
3149 *mipsI,mipsII,mipsIII,mipsIV:
3150 *vr5000:
3151 // start-sanitize-vr4320
3152 *vr4320:
3153 // end-sanitize-vr4320
3154 // start-sanitize-vr5400
3155 *vr5400:
3156 // end-sanitize-vr5400
3157 // start-sanitize-r5900
3158 *r5900:
3159 // end-sanitize-r5900
3160 *r3900:
3161 // start-sanitize-tx19
3162 *tx19:
3163 // end-sanitize-tx19
3164 {
3165 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3166 }
3167
3168
3169 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3170 {
3171 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3172 address_word reverseendian = (ReverseEndian ? -1 : 0);
3173 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3174 unsigned int byte;
3175 address_word paddr;
3176 int uncached;
3177 unsigned64 memval;
3178 address_word vaddr;
3179
3180 vaddr = base + offset;
3181 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3182 paddr = (paddr ^ (reverseendian & mask));
3183 if (BigEndianMem != 0)
3184 paddr &= ~access;
3185 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3186 memval = (rt << (byte * 8));
3187 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3188 }
3189
3190 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3191 "swr r<RT>, <OFFSET>(r<BASE>)"
3192 *mipsI,mipsII,mipsIII,mipsIV:
3193 *vr5000:
3194 // start-sanitize-vr4320
3195 *vr4320:
3196 // end-sanitize-vr4320
3197 // start-sanitize-vr5400
3198 *vr5400:
3199 // end-sanitize-vr5400
3200 // start-sanitize-r5900
3201 *r5900:
3202 // end-sanitize-r5900
3203 *r3900:
3204 // start-sanitize-tx19
3205 *tx19:
3206 // end-sanitize-tx19
3207 {
3208 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3209 }
3210
3211
3212 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3213 "sync":STYPE == 0
3214 "sync <STYPE>"
3215 *mipsII:
3216 *mipsIII:
3217 *mipsIV:
3218 *vr5000:
3219 // start-sanitize-vr4320
3220 *vr4320:
3221 // end-sanitize-vr4320
3222 // start-sanitize-vr5400
3223 *vr5400:
3224 // end-sanitize-vr5400
3225 // start-sanitize-r5900
3226 *r5900:
3227 // end-sanitize-r5900
3228 *r3900:
3229 // start-sanitize-tx19
3230 *tx19:
3231 // end-sanitize-tx19
3232 {
3233 SyncOperation (STYPE);
3234 }
3235
3236
3237 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3238 "syscall <CODE>"
3239 *mipsI,mipsII,mipsIII,mipsIV:
3240 *vr5000:
3241 // start-sanitize-vr4320
3242 *vr4320:
3243 // end-sanitize-vr4320
3244 // start-sanitize-vr5400
3245 *vr5400:
3246 // end-sanitize-vr5400
3247 // start-sanitize-r5900
3248 *r5900:
3249 // end-sanitize-r5900
3250 *r3900:
3251 // start-sanitize-tx19
3252 *tx19:
3253 // end-sanitize-tx19
3254 {
3255 SignalException(SystemCall, instruction_0);
3256 }
3257
3258
3259 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3260 "teq r<RS>, r<RT>"
3261 *mipsII:
3262 *mipsIII:
3263 *mipsIV:
3264 *vr5000:
3265 // start-sanitize-vr4320
3266 *vr4320:
3267 // end-sanitize-vr4320
3268 // start-sanitize-vr5400
3269 *vr5400:
3270 // end-sanitize-vr5400
3271 // start-sanitize-r5900
3272 *r5900:
3273 // end-sanitize-r5900
3274 // start-sanitize-tx19
3275 *tx19:
3276 // end-sanitize-tx19
3277 {
3278 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3279 SignalException(Trap, instruction_0);
3280 }
3281
3282
3283 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3284 "teqi r<RS>, <IMMEDIATE>"
3285 *mipsII:
3286 *mipsIII:
3287 *mipsIV:
3288 *vr5000:
3289 // start-sanitize-vr4320
3290 *vr4320:
3291 // end-sanitize-vr4320
3292 // start-sanitize-vr5400
3293 *vr5400:
3294 // end-sanitize-vr5400
3295 // start-sanitize-r5900
3296 *r5900:
3297 // end-sanitize-r5900
3298 // start-sanitize-tx19
3299 *tx19:
3300 // end-sanitize-tx19
3301 {
3302 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3303 SignalException(Trap, instruction_0);
3304 }
3305
3306
3307 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3308 "tge r<RS>, r<RT>"
3309 *mipsII:
3310 *mipsIII:
3311 *mipsIV:
3312 *vr5000:
3313 // start-sanitize-vr4320
3314 *vr4320:
3315 // end-sanitize-vr4320
3316 // start-sanitize-vr5400
3317 *vr5400:
3318 // end-sanitize-vr5400
3319 // start-sanitize-r5900
3320 *r5900:
3321 // end-sanitize-r5900
3322 // start-sanitize-tx19
3323 *tx19:
3324 // end-sanitize-tx19
3325 {
3326 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3327 SignalException(Trap, instruction_0);
3328 }
3329
3330
3331 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3332 "tgei r<RS>, <IMMEDIATE>"
3333 *mipsII:
3334 *mipsIII:
3335 *mipsIV:
3336 *vr5000:
3337 // start-sanitize-vr4320
3338 *vr4320:
3339 // end-sanitize-vr4320
3340 // start-sanitize-vr5400
3341 *vr5400:
3342 // end-sanitize-vr5400
3343 // start-sanitize-r5900
3344 *r5900:
3345 // end-sanitize-r5900
3346 // start-sanitize-tx19
3347 *tx19:
3348 // end-sanitize-tx19
3349 {
3350 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3351 SignalException(Trap, instruction_0);
3352 }
3353
3354
3355 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3356 "tgeiu r<RS>, <IMMEDIATE>"
3357 *mipsII:
3358 *mipsIII:
3359 *mipsIV:
3360 *vr5000:
3361 // start-sanitize-vr4320
3362 *vr4320:
3363 // end-sanitize-vr4320
3364 // start-sanitize-vr5400
3365 *vr5400:
3366 // end-sanitize-vr5400
3367 // start-sanitize-r5900
3368 *r5900:
3369 // end-sanitize-r5900
3370 // start-sanitize-tx19
3371 *tx19:
3372 // end-sanitize-tx19
3373 {
3374 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3375 SignalException(Trap, instruction_0);
3376 }
3377
3378
3379 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3380 "tgeu r<RS>, r<RT>"
3381 *mipsII:
3382 *mipsIII:
3383 *mipsIV:
3384 *vr5000:
3385 // start-sanitize-vr4320
3386 *vr4320:
3387 // end-sanitize-vr4320
3388 // start-sanitize-vr5400
3389 *vr5400:
3390 // end-sanitize-vr5400
3391 // start-sanitize-r5900
3392 *r5900:
3393 // end-sanitize-r5900
3394 // start-sanitize-tx19
3395 *tx19:
3396 // end-sanitize-tx19
3397 {
3398 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3399 SignalException(Trap, instruction_0);
3400 }
3401
3402
3403 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3404 "tlt r<RS>, r<RT>"
3405 *mipsII:
3406 *mipsIII:
3407 *mipsIV:
3408 *vr5000:
3409 // start-sanitize-vr4320
3410 *vr4320:
3411 // end-sanitize-vr4320
3412 // start-sanitize-vr5400
3413 *vr5400:
3414 // end-sanitize-vr5400
3415 // start-sanitize-r5900
3416 *r5900:
3417 // end-sanitize-r5900
3418 // start-sanitize-tx19
3419 *tx19:
3420 // end-sanitize-tx19
3421 {
3422 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3423 SignalException(Trap, instruction_0);
3424 }
3425
3426
3427 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3428 "tlti r<RS>, <IMMEDIATE>"
3429 *mipsII:
3430 *mipsIII:
3431 *mipsIV:
3432 *vr5000:
3433 // start-sanitize-vr4320
3434 *vr4320:
3435 // end-sanitize-vr4320
3436 // start-sanitize-vr5400
3437 *vr5400:
3438 // end-sanitize-vr5400
3439 // start-sanitize-r5900
3440 *r5900:
3441 // end-sanitize-r5900
3442 // start-sanitize-tx19
3443 *tx19:
3444 // end-sanitize-tx19
3445 {
3446 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3447 SignalException(Trap, instruction_0);
3448 }
3449
3450
3451 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3452 "tltiu r<RS>, <IMMEDIATE>"
3453 *mipsII:
3454 *mipsIII:
3455 *mipsIV:
3456 *vr5000:
3457 // start-sanitize-vr4320
3458 *vr4320:
3459 // end-sanitize-vr4320
3460 // start-sanitize-vr5400
3461 *vr5400:
3462 // end-sanitize-vr5400
3463 // start-sanitize-r5900
3464 *r5900:
3465 // end-sanitize-r5900
3466 // start-sanitize-tx19
3467 *tx19:
3468 // end-sanitize-tx19
3469 {
3470 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3471 SignalException(Trap, instruction_0);
3472 }
3473
3474
3475 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3476 "tltu r<RS>, r<RT>"
3477 *mipsII:
3478 *mipsIII:
3479 *mipsIV:
3480 *vr5000:
3481 // start-sanitize-vr4320
3482 *vr4320:
3483 // end-sanitize-vr4320
3484 // start-sanitize-vr5400
3485 *vr5400:
3486 // end-sanitize-vr5400
3487 // start-sanitize-r5900
3488 *r5900:
3489 // end-sanitize-r5900
3490 // start-sanitize-tx19
3491 *tx19:
3492 // end-sanitize-tx19
3493 {
3494 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3495 SignalException(Trap, instruction_0);
3496 }
3497
3498
3499 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3500 "tne r<RS>, r<RT>"
3501 *mipsII:
3502 *mipsIII:
3503 *mipsIV:
3504 *vr5000:
3505 // start-sanitize-vr4320
3506 *vr4320:
3507 // end-sanitize-vr4320
3508 // start-sanitize-vr5400
3509 *vr5400:
3510 // end-sanitize-vr5400
3511 // start-sanitize-r5900
3512 *r5900:
3513 // end-sanitize-r5900
3514 // start-sanitize-tx19
3515 *tx19:
3516 // end-sanitize-tx19
3517 {
3518 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3519 SignalException(Trap, instruction_0);
3520 }
3521
3522
3523 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3524 "tne r<RS>, <IMMEDIATE>"
3525 *mipsII:
3526 *mipsIII:
3527 *mipsIV:
3528 *vr5000:
3529 // start-sanitize-vr4320
3530 *vr4320:
3531 // end-sanitize-vr4320
3532 // start-sanitize-vr5400
3533 *vr5400:
3534 // end-sanitize-vr5400
3535 // start-sanitize-r5900
3536 *r5900:
3537 // end-sanitize-r5900
3538 // start-sanitize-tx19
3539 *tx19:
3540 // end-sanitize-tx19
3541 {
3542 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3543 SignalException(Trap, instruction_0);
3544 }
3545
3546
3547 :function:::void:do_xor:int rs, int rt, int rd
3548 {
3549 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3550 GPR[rd] = GPR[rs] ^ GPR[rt];
3551 TRACE_ALU_RESULT (GPR[rd]);
3552 }
3553
3554 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3555 "xor r<RD>, r<RS>, r<RT>"
3556 *mipsI,mipsII,mipsIII,mipsIV:
3557 *vr5000:
3558 // start-sanitize-vr4320
3559 *vr4320:
3560 // end-sanitize-vr4320
3561 // start-sanitize-vr5400
3562 *vr5400:
3563 // end-sanitize-vr5400
3564 // start-sanitize-r5900
3565 *r5900:
3566 // end-sanitize-r5900
3567 *r3900:
3568 // start-sanitize-tx19
3569 *tx19:
3570 // end-sanitize-tx19
3571 {
3572 do_xor (SD_, RS, RT, RD);
3573 }
3574
3575
3576 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3577 {
3578 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3579 GPR[rt] = GPR[rs] ^ immediate;
3580 TRACE_ALU_RESULT (GPR[rt]);
3581 }
3582
3583 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3584 "xori r<RT>, r<RS>, <IMMEDIATE>"
3585 *mipsI,mipsII,mipsIII,mipsIV:
3586 *vr5000:
3587 // start-sanitize-vr4320
3588 *vr4320:
3589 // end-sanitize-vr4320
3590 // start-sanitize-vr5400
3591 *vr5400:
3592 // end-sanitize-vr5400
3593 // start-sanitize-r5900
3594 *r5900:
3595 // end-sanitize-r5900
3596 *r3900:
3597 // start-sanitize-tx19
3598 *tx19:
3599 // end-sanitize-tx19
3600 {
3601 do_xori (SD_, RS, RT, IMMEDIATE);
3602 }
3603
3604 \f
3605 //
3606 // MIPS Architecture:
3607 //
3608 // FPU Instruction Set (COP1 & COP1X)
3609 //
3610
3611
3612 :%s::::FMT:int fmt
3613 {
3614 switch (fmt)
3615 {
3616 case fmt_single: return "s";
3617 case fmt_double: return "d";
3618 case fmt_word: return "w";
3619 case fmt_long: return "l";
3620 default: return "?";
3621 }
3622 }
3623
3624 :%s::::X:int x
3625 {
3626 switch (x)
3627 {
3628 case 0: return "f";
3629 case 1: return "t";
3630 default: return "?";
3631 }
3632 }
3633
3634 :%s::::TF:int tf
3635 {
3636 if (tf)
3637 return "t";
3638 else
3639 return "f";
3640 }
3641
3642 :%s::::ND:int nd
3643 {
3644 if (nd)
3645 return "l";
3646 else
3647 return "";
3648 }
3649
3650 :%s::::COND:int cond
3651 {
3652 switch (cond)
3653 {
3654 case 00: return "f";
3655 case 01: return "un";
3656 case 02: return "eq";
3657 case 03: return "ueq";
3658 case 04: return "olt";
3659 case 05: return "ult";
3660 case 06: return "ole";
3661 case 07: return "ule";
3662 case 010: return "sf";
3663 case 011: return "ngle";
3664 case 012: return "seq";
3665 case 013: return "ngl";
3666 case 014: return "lt";
3667 case 015: return "nge";
3668 case 016: return "le";
3669 case 017: return "ngt";
3670 default: return "?";
3671 }
3672 }
3673
3674
3675 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3676 "abs.%s<FMT> f<FD>, f<FS>"
3677 *mipsI,mipsII,mipsIII,mipsIV:
3678 *vr5000:
3679 // start-sanitize-vr4320
3680 *vr4320:
3681 // end-sanitize-vr4320
3682 // start-sanitize-vr5400
3683 *vr5400:
3684 // end-sanitize-vr5400
3685 *r3900:
3686 // start-sanitize-tx19
3687 *tx19:
3688 // end-sanitize-tx19
3689 {
3690 unsigned32 instruction = instruction_0;
3691 int destreg = ((instruction >> 6) & 0x0000001F);
3692 int fs = ((instruction >> 11) & 0x0000001F);
3693 int format = ((instruction >> 21) & 0x00000007);
3694 {
3695 if ((format != fmt_single) && (format != fmt_double))
3696 SignalException(ReservedInstruction,instruction);
3697 else
3698 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3699 }
3700 }
3701
3702
3703
3704 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3705 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3706 *mipsI,mipsII,mipsIII,mipsIV:
3707 *vr5000:
3708 // start-sanitize-vr4320
3709 *vr4320:
3710 // end-sanitize-vr4320
3711 // start-sanitize-vr5400
3712 *vr5400:
3713 // end-sanitize-vr5400
3714 *r3900:
3715 // start-sanitize-tx19
3716 *tx19:
3717 // end-sanitize-tx19
3718 {
3719 unsigned32 instruction = instruction_0;
3720 int destreg = ((instruction >> 6) & 0x0000001F);
3721 int fs = ((instruction >> 11) & 0x0000001F);
3722 int ft = ((instruction >> 16) & 0x0000001F);
3723 int format = ((instruction >> 21) & 0x00000007);
3724 {
3725 if ((format != fmt_single) && (format != fmt_double))
3726 SignalException(ReservedInstruction, instruction);
3727 else
3728 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3729 }
3730 }
3731
3732
3733
3734 // BC1F
3735 // BC1FL
3736 // BC1T
3737 // BC1TL
3738
3739 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3740 "bc1%s<TF>%s<ND> <OFFSET>"
3741 *mipsI,mipsII,mipsIII:
3742 // start-sanitize-r5900
3743 *r5900:
3744 // end-sanitize-r5900
3745 {
3746 TRACE_BRANCH_INPUT (PREVCOC1());
3747 if (PREVCOC1() == TF)
3748 {
3749 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3750 TRACE_BRANCH_RESULT (dest);
3751 DELAY_SLOT (dest);
3752 }
3753 else if (ND)
3754 {
3755 TRACE_BRANCH_RESULT (0);
3756 NULLIFY_NEXT_INSTRUCTION ();
3757 }
3758 else
3759 {
3760 TRACE_BRANCH_RESULT (NIA);
3761 }
3762 }
3763
3764 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3765 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3766 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3767 *mipsIV:
3768 *vr5000:
3769 // start-sanitize-vr4320
3770 *vr4320:
3771 // end-sanitize-vr4320
3772 // start-sanitize-vr5400
3773 *vr5400:
3774 // end-sanitize-vr5400
3775 *r3900:
3776 // start-sanitize-tx19
3777 *tx19:
3778 // end-sanitize-tx19
3779 {
3780 if (GETFCC(CC) == TF)
3781 {
3782 DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3783 }
3784 else if (ND)
3785 {
3786 NULLIFY_NEXT_INSTRUCTION ();
3787 }
3788 }
3789
3790
3791
3792 // C.EQ.S
3793 // C.EQ.D
3794 // ...
3795
3796 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3797 {
3798 if ((fmt != fmt_single) && (fmt != fmt_double))
3799 SignalException (ReservedInstruction, insn);
3800 else
3801 {
3802 int less;
3803 int equal;
3804 int unordered;
3805 int condition;
3806 unsigned64 ofs = ValueFPR (fs, fmt);
3807 unsigned64 oft = ValueFPR (ft, fmt);
3808 if (NaN (ofs, fmt) || NaN (oft, fmt))
3809 {
3810 if (FCSR & FP_ENABLE (IO))
3811 {
3812 FCSR |= FP_CAUSE (IO);
3813 SignalExceptionFPE ();
3814 }
3815 less = 0;
3816 equal = 0;
3817 unordered = 1;
3818 }
3819 else
3820 {
3821 less = Less (ofs, oft, fmt);
3822 equal = Equal (ofs, oft, fmt);
3823 unordered = 0;
3824 }
3825 condition = (((cond & (1 << 2)) && less)
3826 || ((cond & (1 << 1)) && equal)
3827 || ((cond & (1 << 0)) && unordered));
3828 SETFCC (cc, condition);
3829 }
3830 }
3831
3832 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3833 *mipsI,mipsII,mipsIII:
3834 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3835 {
3836 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3837 }
3838
3839 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3840 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3841 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3842 *mipsIV:
3843 *vr5000:
3844 // start-sanitize-vr4320
3845 *vr4320:
3846 // end-sanitize-vr4320
3847 // start-sanitize-vr5400
3848 *vr5400:
3849 // end-sanitize-vr5400
3850 *r3900:
3851 // start-sanitize-tx19
3852 *tx19:
3853 // end-sanitize-tx19
3854 {
3855 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3856 }
3857
3858
3859 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3860 "ceil.l.%s<FMT> f<FD>, f<FS>"
3861 *mipsIII:
3862 *mipsIV:
3863 *vr5000:
3864 // start-sanitize-vr4320
3865 *vr4320:
3866 // end-sanitize-vr4320
3867 // start-sanitize-vr5400
3868 *vr5400:
3869 // end-sanitize-vr5400
3870 // start-sanitize-r5900
3871 *r5900:
3872 // end-sanitize-r5900
3873 *r3900:
3874 // start-sanitize-tx19
3875 *tx19:
3876 // end-sanitize-tx19
3877 {
3878 unsigned32 instruction = instruction_0;
3879 int destreg = ((instruction >> 6) & 0x0000001F);
3880 int fs = ((instruction >> 11) & 0x0000001F);
3881 int format = ((instruction >> 21) & 0x00000007);
3882 {
3883 if ((format != fmt_single) && (format != fmt_double))
3884 SignalException(ReservedInstruction,instruction);
3885 else
3886 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3887 }
3888 }
3889
3890
3891 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3892 *mipsII:
3893 *mipsIII:
3894 *mipsIV:
3895 *vr5000:
3896 // start-sanitize-vr4320
3897 *vr4320:
3898 // end-sanitize-vr4320
3899 // start-sanitize-vr5400
3900 *vr5400:
3901 // end-sanitize-vr5400
3902 // start-sanitize-r5900
3903 *r5900:
3904 // end-sanitize-r5900
3905 *r3900:
3906 // start-sanitize-tx19
3907 *tx19:
3908 // end-sanitize-tx19
3909 {
3910 unsigned32 instruction = instruction_0;
3911 int destreg = ((instruction >> 6) & 0x0000001F);
3912 int fs = ((instruction >> 11) & 0x0000001F);
3913 int format = ((instruction >> 21) & 0x00000007);
3914 {
3915 if ((format != fmt_single) && (format != fmt_double))
3916 SignalException(ReservedInstruction,instruction);
3917 else
3918 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3919 }
3920 }
3921
3922
3923 // CFC1
3924 // CTC1
3925 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3926 "c%s<X>c1 r<RT>, f<FS>"
3927 *mipsI:
3928 *mipsII:
3929 *mipsIII:
3930 {
3931 if (X)
3932 {
3933 if (FS == 0)
3934 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3935 else if (FS == 31)
3936 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
3937 /* else NOP */
3938 PENDING_FILL(COCIDX,0); /* special case */
3939 }
3940 else
3941 { /* control from */
3942 if (FS == 0)
3943 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3944 else if (FS == 31)
3945 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3946 /* else NOP */
3947 }
3948 }
3949 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3950 "c%s<X>c1 r<RT>, f<FS>"
3951 *mipsIV:
3952 *vr5000:
3953 // start-sanitize-vr4320
3954 *vr4320:
3955 // end-sanitize-vr4320
3956 // start-sanitize-vr5400
3957 *vr5400:
3958 // end-sanitize-vr5400
3959 *r3900:
3960 // start-sanitize-tx19
3961 *tx19:
3962 // end-sanitize-tx19
3963 {
3964 if (X)
3965 {
3966 /* control to */
3967 TRACE_ALU_INPUT1 (GPR[RT]);
3968 if (FS == 0)
3969 {
3970 FCR0 = VL4_8(GPR[RT]);
3971 TRACE_ALU_RESULT (FCR0);
3972 }
3973 else if (FS == 31)
3974 {
3975 FCR31 = VL4_8(GPR[RT]);
3976 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3977 TRACE_ALU_RESULT (FCR31);
3978 }
3979 else
3980 {
3981 TRACE_ALU_RESULT0 ();
3982 }
3983 /* else NOP */
3984 }
3985 else
3986 { /* control from */
3987 if (FS == 0)
3988 {
3989 TRACE_ALU_INPUT1 (FCR0);
3990 GPR[RT] = SIGNEXTEND (FCR0, 32);
3991 }
3992 else if (FS == 31)
3993 {
3994 TRACE_ALU_INPUT1 (FCR31);
3995 GPR[RT] = SIGNEXTEND (FCR31, 32);
3996 }
3997 TRACE_ALU_RESULT (GPR[RT]);
3998 /* else NOP */
3999 }
4000 }
4001
4002
4003 //
4004 // FIXME: Does not correctly differentiate between mips*
4005 //
4006 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4007 "cvt.d.%s<FMT> f<FD>, f<FS>"
4008 *mipsI,mipsII,mipsIII,mipsIV:
4009 *vr5000:
4010 // start-sanitize-vr4320
4011 *vr4320:
4012 // end-sanitize-vr4320
4013 // start-sanitize-vr5400
4014 *vr5400:
4015 // end-sanitize-vr5400
4016 *r3900:
4017 // start-sanitize-tx19
4018 *tx19:
4019 // end-sanitize-tx19
4020 {
4021 unsigned32 instruction = instruction_0;
4022 int destreg = ((instruction >> 6) & 0x0000001F);
4023 int fs = ((instruction >> 11) & 0x0000001F);
4024 int format = ((instruction >> 21) & 0x00000007);
4025 {
4026 if ((format == fmt_double) | 0)
4027 SignalException(ReservedInstruction,instruction);
4028 else
4029 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4030 }
4031 }
4032
4033
4034 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4035 "cvt.l.%s<FMT> f<FD>, f<FS>"
4036 *mipsIII:
4037 *mipsIV:
4038 *vr5000:
4039 // start-sanitize-vr4320
4040 *vr4320:
4041 // end-sanitize-vr4320
4042 // start-sanitize-vr5400
4043 *vr5400:
4044 // end-sanitize-vr5400
4045 *r3900:
4046 // start-sanitize-tx19
4047 *tx19:
4048 // end-sanitize-tx19
4049 {
4050 unsigned32 instruction = instruction_0;
4051 int destreg = ((instruction >> 6) & 0x0000001F);
4052 int fs = ((instruction >> 11) & 0x0000001F);
4053 int format = ((instruction >> 21) & 0x00000007);
4054 {
4055 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4056 SignalException(ReservedInstruction,instruction);
4057 else
4058 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4059 }
4060 }
4061
4062
4063 //
4064 // FIXME: Does not correctly differentiate between mips*
4065 //
4066 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4067 "cvt.s.%s<FMT> f<FD>, f<FS>"
4068 *mipsI,mipsII,mipsIII,mipsIV:
4069 *vr5000:
4070 // start-sanitize-vr4320
4071 *vr4320:
4072 // end-sanitize-vr4320
4073 // start-sanitize-vr5400
4074 *vr5400:
4075 // end-sanitize-vr5400
4076 *r3900:
4077 // start-sanitize-tx19
4078 *tx19:
4079 // end-sanitize-tx19
4080 {
4081 unsigned32 instruction = instruction_0;
4082 int destreg = ((instruction >> 6) & 0x0000001F);
4083 int fs = ((instruction >> 11) & 0x0000001F);
4084 int format = ((instruction >> 21) & 0x00000007);
4085 {
4086 if ((format == fmt_single) | 0)
4087 SignalException(ReservedInstruction,instruction);
4088 else
4089 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4090 }
4091 }
4092
4093
4094 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4095 "cvt.w.%s<FMT> f<FD>, f<FS>"
4096 *mipsI,mipsII,mipsIII,mipsIV:
4097 *vr5000:
4098 // start-sanitize-vr4320
4099 *vr4320:
4100 // end-sanitize-vr4320
4101 // start-sanitize-vr5400
4102 *vr5400:
4103 // end-sanitize-vr5400
4104 *r3900:
4105 // start-sanitize-tx19
4106 *tx19:
4107 // end-sanitize-tx19
4108 {
4109 unsigned32 instruction = instruction_0;
4110 int destreg = ((instruction >> 6) & 0x0000001F);
4111 int fs = ((instruction >> 11) & 0x0000001F);
4112 int format = ((instruction >> 21) & 0x00000007);
4113 {
4114 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4115 SignalException(ReservedInstruction,instruction);
4116 else
4117 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4118 }
4119 }
4120
4121
4122 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4123 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4124 *mipsI,mipsII,mipsIII,mipsIV:
4125 *vr5000:
4126 // start-sanitize-vr4320
4127 *vr4320:
4128 // end-sanitize-vr4320
4129 // start-sanitize-vr5400
4130 *vr5400:
4131 // end-sanitize-vr5400
4132 *r3900:
4133 // start-sanitize-tx19
4134 *tx19:
4135 // end-sanitize-tx19
4136 {
4137 unsigned32 instruction = instruction_0;
4138 int destreg = ((instruction >> 6) & 0x0000001F);
4139 int fs = ((instruction >> 11) & 0x0000001F);
4140 int ft = ((instruction >> 16) & 0x0000001F);
4141 int format = ((instruction >> 21) & 0x00000007);
4142 {
4143 if ((format != fmt_single) && (format != fmt_double))
4144 SignalException(ReservedInstruction,instruction);
4145 else
4146 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4147 }
4148 }
4149
4150
4151 // DMFC1
4152 // DMTC1
4153 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4154 "dm%s<X>c1 r<RT>, f<FS>"
4155 *mipsIII:
4156 {
4157 if (X)
4158 {
4159 if (SizeFGR() == 64)
4160 PENDING_FILL((FS + FGRIDX),GPR[RT]);
4161 else if ((FS & 0x1) == 0)
4162 {
4163 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4164 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4165 }
4166 }
4167 else
4168 {
4169 if (SizeFGR() == 64)
4170 PENDING_FILL(RT,FGR[FS]);
4171 else if ((FS & 0x1) == 0)
4172 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4173 else
4174 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4175 }
4176 }
4177 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4178 "dm%s<X>c1 r<RT>, f<FS>"
4179 *mipsIV:
4180 *vr5000:
4181 // start-sanitize-vr4320
4182 *vr4320:
4183 // end-sanitize-vr4320
4184 // start-sanitize-vr5400
4185 *vr5400:
4186 // end-sanitize-vr5400
4187 // start-sanitize-r5900
4188 *r5900:
4189 // end-sanitize-r5900
4190 *r3900:
4191 // start-sanitize-tx19
4192 *tx19:
4193 // end-sanitize-tx19
4194 {
4195 if (X)
4196 {
4197 if (SizeFGR() == 64)
4198 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4199 else if ((FS & 0x1) == 0)
4200 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4201 }
4202 else
4203 {
4204 if (SizeFGR() == 64)
4205 GPR[RT] = FGR[FS];
4206 else if ((FS & 0x1) == 0)
4207 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4208 else
4209 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4210 }
4211 }
4212
4213
4214 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4215 "floor.l.%s<FMT> f<FD>, f<FS>"
4216 *mipsIII:
4217 *mipsIV:
4218 *vr5000:
4219 // start-sanitize-vr4320
4220 *vr4320:
4221 // end-sanitize-vr4320
4222 // start-sanitize-vr5400
4223 *vr5400:
4224 // end-sanitize-vr5400
4225 // start-sanitize-r5900
4226 *r5900:
4227 // end-sanitize-r5900
4228 *r3900:
4229 // start-sanitize-tx19
4230 *tx19:
4231 // end-sanitize-tx19
4232 {
4233 unsigned32 instruction = instruction_0;
4234 int destreg = ((instruction >> 6) & 0x0000001F);
4235 int fs = ((instruction >> 11) & 0x0000001F);
4236 int format = ((instruction >> 21) & 0x00000007);
4237 {
4238 if ((format != fmt_single) && (format != fmt_double))
4239 SignalException(ReservedInstruction,instruction);
4240 else
4241 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4242 }
4243 }
4244
4245
4246 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4247 "floor.w.%s<FMT> f<FD>, f<FS>"
4248 *mipsII:
4249 *mipsIII:
4250 *mipsIV:
4251 *vr5000:
4252 // start-sanitize-vr4320
4253 *vr4320:
4254 // end-sanitize-vr4320
4255 // start-sanitize-vr5400
4256 *vr5400:
4257 // end-sanitize-vr5400
4258 // start-sanitize-r5900
4259 *r5900:
4260 // end-sanitize-r5900
4261 *r3900:
4262 // start-sanitize-tx19
4263 *tx19:
4264 // end-sanitize-tx19
4265 {
4266 unsigned32 instruction = instruction_0;
4267 int destreg = ((instruction >> 6) & 0x0000001F);
4268 int fs = ((instruction >> 11) & 0x0000001F);
4269 int format = ((instruction >> 21) & 0x00000007);
4270 {
4271 if ((format != fmt_single) && (format != fmt_double))
4272 SignalException(ReservedInstruction,instruction);
4273 else
4274 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4275 }
4276 }
4277
4278
4279 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4280 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4281 *mipsII:
4282 *mipsIII:
4283 *mipsIV:
4284 *vr5000:
4285 // start-sanitize-vr4320
4286 *vr4320:
4287 // end-sanitize-vr4320
4288 // start-sanitize-vr5400
4289 *vr5400:
4290 // end-sanitize-vr5400
4291 *r3900:
4292 // start-sanitize-tx19
4293 *tx19:
4294 // end-sanitize-tx19
4295 {
4296 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4297 }
4298
4299
4300 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4301 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4302 *mipsIV:
4303 *vr5000:
4304 // start-sanitize-vr4320
4305 *vr4320:
4306 // end-sanitize-vr4320
4307 // start-sanitize-vr5400
4308 *vr5400:
4309 // end-sanitize-vr5400
4310 {
4311 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4312 }
4313
4314
4315
4316 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4317 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4318 *mipsI,mipsII,mipsIII,mipsIV:
4319 *vr5000:
4320 // start-sanitize-vr4320
4321 *vr4320:
4322 // end-sanitize-vr4320
4323 // start-sanitize-vr5400
4324 *vr5400:
4325 // end-sanitize-vr5400
4326 // start-sanitize-r5900
4327 *r5900:
4328 // end-sanitize-r5900
4329 *r3900:
4330 // start-sanitize-tx19
4331 *tx19:
4332 // end-sanitize-tx19
4333 {
4334 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4335 }
4336
4337
4338 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4339 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4340 *mipsIV:
4341 *vr5000:
4342 // start-sanitize-vr4320
4343 *vr4320:
4344 // end-sanitize-vr4320
4345 // start-sanitize-vr5400
4346 *vr5400:
4347 // end-sanitize-vr5400
4348 {
4349 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4350 }
4351
4352
4353
4354 //
4355 // FIXME: Not correct for mips*
4356 //
4357 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4358 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4359 *mipsIV:
4360 *vr5000:
4361 // start-sanitize-vr4320
4362 *vr4320:
4363 // end-sanitize-vr4320
4364 // start-sanitize-vr5400
4365 *vr5400:
4366 // end-sanitize-vr5400
4367 {
4368 unsigned32 instruction = instruction_0;
4369 int destreg = ((instruction >> 6) & 0x0000001F);
4370 int fs = ((instruction >> 11) & 0x0000001F);
4371 int ft = ((instruction >> 16) & 0x0000001F);
4372 int fr = ((instruction >> 21) & 0x0000001F);
4373 {
4374 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4375 }
4376 }
4377
4378
4379 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4380 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4381 *mipsIV:
4382 *vr5000:
4383 // start-sanitize-vr4320
4384 *vr4320:
4385 // end-sanitize-vr4320
4386 // start-sanitize-vr5400
4387 *vr5400:
4388 // end-sanitize-vr5400
4389 {
4390 unsigned32 instruction = instruction_0;
4391 int destreg = ((instruction >> 6) & 0x0000001F);
4392 int fs = ((instruction >> 11) & 0x0000001F);
4393 int ft = ((instruction >> 16) & 0x0000001F);
4394 int fr = ((instruction >> 21) & 0x0000001F);
4395 {
4396 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4397 }
4398 }
4399
4400
4401 // MFC1
4402 // MTC1
4403 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4404 "m%s<X>c1 r<RT>, f<FS>"
4405 *mipsI:
4406 *mipsII:
4407 *mipsIII:
4408 {
4409 if (X)
4410 { /*MTC1*/
4411 if (SizeFGR() == 64)
4412 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4413 else
4414 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4415 }
4416 else /*MFC1*/
4417 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4418 }
4419 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4420 "m%s<X>c1 r<RT>, f<FS>"
4421 *mipsIV:
4422 *vr5000:
4423 // start-sanitize-vr4320
4424 *vr4320:
4425 // end-sanitize-vr4320
4426 // start-sanitize-vr5400
4427 *vr5400:
4428 // end-sanitize-vr5400
4429 *r3900:
4430 // start-sanitize-tx19
4431 *tx19:
4432 // end-sanitize-tx19
4433 {
4434 if (X)
4435 /*MTC1*/
4436 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4437 else /*MFC1*/
4438 GPR[RT] = SIGNEXTEND(FGR[FS],32);
4439 }
4440
4441
4442 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4443 "mov.%s<FMT> f<FD>, f<FS>"
4444 *mipsI,mipsII,mipsIII,mipsIV:
4445 *vr5000:
4446 // start-sanitize-vr4320
4447 *vr4320:
4448 // end-sanitize-vr4320
4449 // start-sanitize-vr5400
4450 *vr5400:
4451 // end-sanitize-vr5400
4452 *r3900:
4453 // start-sanitize-tx19
4454 *tx19:
4455 // end-sanitize-tx19
4456 {
4457 unsigned32 instruction = instruction_0;
4458 int destreg = ((instruction >> 6) & 0x0000001F);
4459 int fs = ((instruction >> 11) & 0x0000001F);
4460 int format = ((instruction >> 21) & 0x00000007);
4461 {
4462 StoreFPR(destreg,format,ValueFPR(fs,format));
4463 }
4464 }
4465
4466
4467 // MOVF
4468 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4469 "mov%s<TF> r<RD>, r<RS>, <CC>"
4470 *mipsIV:
4471 *vr5000:
4472 // start-sanitize-vr4320
4473 *vr4320:
4474 // end-sanitize-vr4320
4475 // start-sanitize-vr5400
4476 *vr5400:
4477 // end-sanitize-vr5400
4478 // start-sanitize-r5900
4479 *r5900:
4480 // end-sanitize-r5900
4481 {
4482 if (GETFCC(CC) == TF)
4483 GPR[RD] = GPR[RS];
4484 }
4485
4486
4487 // MOVF.fmt
4488 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4489 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4490 *mipsIV:
4491 *vr5000:
4492 // start-sanitize-vr4320
4493 *vr4320:
4494 // end-sanitize-vr4320
4495 // start-sanitize-vr5400
4496 *vr5400:
4497 // end-sanitize-vr5400
4498 // start-sanitize-r5900
4499 *r5900:
4500 // end-sanitize-r5900
4501 {
4502 unsigned32 instruction = instruction_0;
4503 int format = ((instruction >> 21) & 0x00000007);
4504 {
4505 if (GETFCC(CC) == TF)
4506 StoreFPR (FD, format, ValueFPR (FS, format));
4507 else
4508 StoreFPR (FD, format, ValueFPR (FD, format));
4509 }
4510 }
4511
4512
4513 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4514 *mipsIV:
4515 *vr5000:
4516 // start-sanitize-vr4320
4517 *vr4320:
4518 // end-sanitize-vr4320
4519 // start-sanitize-vr5400
4520 *vr5400:
4521 // end-sanitize-vr5400
4522 // start-sanitize-r5900
4523 *r5900:
4524 // end-sanitize-r5900
4525 {
4526 unsigned32 instruction = instruction_0;
4527 int destreg = ((instruction >> 6) & 0x0000001F);
4528 int fs = ((instruction >> 11) & 0x0000001F);
4529 int format = ((instruction >> 21) & 0x00000007);
4530 {
4531 StoreFPR(destreg,format,ValueFPR(fs,format));
4532 }
4533 }
4534
4535
4536 // MOVT see MOVtf
4537
4538
4539 // MOVT.fmt see MOVtf.fmt
4540
4541
4542
4543 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4544 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4545 *mipsIV:
4546 *vr5000:
4547 // start-sanitize-vr4320
4548 *vr4320:
4549 // end-sanitize-vr4320
4550 // start-sanitize-vr5400
4551 *vr5400:
4552 // end-sanitize-vr5400
4553 // start-sanitize-r5900
4554 *r5900:
4555 // end-sanitize-r5900
4556 {
4557 unsigned32 instruction = instruction_0;
4558 int destreg = ((instruction >> 6) & 0x0000001F);
4559 int fs = ((instruction >> 11) & 0x0000001F);
4560 int format = ((instruction >> 21) & 0x00000007);
4561 {
4562 StoreFPR(destreg,format,ValueFPR(fs,format));
4563 }
4564 }
4565
4566
4567 // MSUB.fmt
4568 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4569 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4570 *mipsIV:
4571 *vr5000:
4572 // start-sanitize-vr4320
4573 *vr4320:
4574 // end-sanitize-vr4320
4575 // start-sanitize-vr5400
4576 *vr5400:
4577 // end-sanitize-vr5400
4578 // start-sanitize-r5900
4579 *r5900:
4580 // end-sanitize-r5900
4581 {
4582 unsigned32 instruction = instruction_0;
4583 int destreg = ((instruction >> 6) & 0x0000001F);
4584 int fs = ((instruction >> 11) & 0x0000001F);
4585 int ft = ((instruction >> 16) & 0x0000001F);
4586 int fr = ((instruction >> 21) & 0x0000001F);
4587 {
4588 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4589 }
4590 }
4591
4592
4593 // MSUB.fmt
4594 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4595 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4596 *mipsIV:
4597 *vr5000:
4598 // start-sanitize-vr4320
4599 *vr4320:
4600 // end-sanitize-vr4320
4601 // start-sanitize-vr5400
4602 *vr5400:
4603 // end-sanitize-vr5400
4604 // start-sanitize-r5900
4605 *r5900:
4606 // end-sanitize-r5900
4607 {
4608 unsigned32 instruction = instruction_0;
4609 int destreg = ((instruction >> 6) & 0x0000001F);
4610 int fs = ((instruction >> 11) & 0x0000001F);
4611 int ft = ((instruction >> 16) & 0x0000001F);
4612 int fr = ((instruction >> 21) & 0x0000001F);
4613 {
4614 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4615 }
4616 }
4617
4618
4619 // MTC1 see MxC1
4620
4621
4622 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4623 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4624 *mipsI,mipsII,mipsIII,mipsIV:
4625 *vr5000:
4626 // start-sanitize-vr4320
4627 *vr4320:
4628 // end-sanitize-vr4320
4629 // start-sanitize-vr5400
4630 *vr5400:
4631 // end-sanitize-vr5400
4632 *r3900:
4633 // start-sanitize-tx19
4634 *tx19:
4635 // end-sanitize-tx19
4636 {
4637 unsigned32 instruction = instruction_0;
4638 int destreg = ((instruction >> 6) & 0x0000001F);
4639 int fs = ((instruction >> 11) & 0x0000001F);
4640 int ft = ((instruction >> 16) & 0x0000001F);
4641 int format = ((instruction >> 21) & 0x00000007);
4642 {
4643 if ((format != fmt_single) && (format != fmt_double))
4644 SignalException(ReservedInstruction,instruction);
4645 else
4646 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4647 }
4648 }
4649
4650
4651 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4652 "neg.%s<FMT> f<FD>, f<FS>"
4653 *mipsI,mipsII,mipsIII,mipsIV:
4654 *vr5000:
4655 // start-sanitize-vr4320
4656 *vr4320:
4657 // end-sanitize-vr4320
4658 // start-sanitize-vr5400
4659 *vr5400:
4660 // end-sanitize-vr5400
4661 *r3900:
4662 // start-sanitize-tx19
4663 *tx19:
4664 // end-sanitize-tx19
4665 {
4666 unsigned32 instruction = instruction_0;
4667 int destreg = ((instruction >> 6) & 0x0000001F);
4668 int fs = ((instruction >> 11) & 0x0000001F);
4669 int format = ((instruction >> 21) & 0x00000007);
4670 {
4671 if ((format != fmt_single) && (format != fmt_double))
4672 SignalException(ReservedInstruction,instruction);
4673 else
4674 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4675 }
4676 }
4677
4678
4679 // NMADD.fmt
4680 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4681 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4682 *mipsIV:
4683 *vr5000:
4684 // start-sanitize-vr4320
4685 *vr4320:
4686 // end-sanitize-vr4320
4687 // start-sanitize-vr5400
4688 *vr5400:
4689 // end-sanitize-vr5400
4690 {
4691 unsigned32 instruction = instruction_0;
4692 int destreg = ((instruction >> 6) & 0x0000001F);
4693 int fs = ((instruction >> 11) & 0x0000001F);
4694 int ft = ((instruction >> 16) & 0x0000001F);
4695 int fr = ((instruction >> 21) & 0x0000001F);
4696 {
4697 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4698 }
4699 }
4700
4701
4702 // NMADD.fmt
4703 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4704 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4705 *mipsIV:
4706 *vr5000:
4707 // start-sanitize-vr4320
4708 *vr4320:
4709 // end-sanitize-vr4320
4710 // start-sanitize-vr5400
4711 *vr5400:
4712 // end-sanitize-vr5400
4713 {
4714 unsigned32 instruction = instruction_0;
4715 int destreg = ((instruction >> 6) & 0x0000001F);
4716 int fs = ((instruction >> 11) & 0x0000001F);
4717 int ft = ((instruction >> 16) & 0x0000001F);
4718 int fr = ((instruction >> 21) & 0x0000001F);
4719 {
4720 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4721 }
4722 }
4723
4724
4725 // NMSUB.fmt
4726 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4727 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4728 *mipsIV:
4729 *vr5000:
4730 // start-sanitize-vr4320
4731 *vr4320:
4732 // end-sanitize-vr4320
4733 // start-sanitize-vr5400
4734 *vr5400:
4735 // end-sanitize-vr5400
4736 {
4737 unsigned32 instruction = instruction_0;
4738 int destreg = ((instruction >> 6) & 0x0000001F);
4739 int fs = ((instruction >> 11) & 0x0000001F);
4740 int ft = ((instruction >> 16) & 0x0000001F);
4741 int fr = ((instruction >> 21) & 0x0000001F);
4742 {
4743 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4744 }
4745 }
4746
4747
4748 // NMSUB.fmt
4749 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4750 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4751 *mipsIV:
4752 *vr5000:
4753 // start-sanitize-vr4320
4754 *vr4320:
4755 // end-sanitize-vr4320
4756 // start-sanitize-vr5400
4757 *vr5400:
4758 // end-sanitize-vr5400
4759 {
4760 unsigned32 instruction = instruction_0;
4761 int destreg = ((instruction >> 6) & 0x0000001F);
4762 int fs = ((instruction >> 11) & 0x0000001F);
4763 int ft = ((instruction >> 16) & 0x0000001F);
4764 int fr = ((instruction >> 21) & 0x0000001F);
4765 {
4766 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4767 }
4768 }
4769
4770
4771 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4772 "prefx <HINT>, r<INDEX>(r<BASE>)"
4773 *mipsIV:
4774 *vr5000:
4775 // start-sanitize-vr4320
4776 *vr4320:
4777 // end-sanitize-vr4320
4778 // start-sanitize-vr5400
4779 *vr5400:
4780 // end-sanitize-vr5400
4781 {
4782 unsigned32 instruction = instruction_0;
4783 int fs = ((instruction >> 11) & 0x0000001F);
4784 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4785 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4786 {
4787 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4788 address_word paddr;
4789 int uncached;
4790 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4791 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4792 }
4793 }
4794
4795 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4796 *mipsIV:
4797 "recip.%s<FMT> f<FD>, f<FS>"
4798 *vr5000:
4799 // start-sanitize-vr4320
4800 *vr4320:
4801 // end-sanitize-vr4320
4802 // start-sanitize-vr5400
4803 *vr5400:
4804 // end-sanitize-vr5400
4805 {
4806 unsigned32 instruction = instruction_0;
4807 int destreg = ((instruction >> 6) & 0x0000001F);
4808 int fs = ((instruction >> 11) & 0x0000001F);
4809 int format = ((instruction >> 21) & 0x00000007);
4810 {
4811 if ((format != fmt_single) && (format != fmt_double))
4812 SignalException(ReservedInstruction,instruction);
4813 else
4814 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4815 }
4816 }
4817
4818
4819 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4820 "round.l.%s<FMT> f<FD>, f<FS>"
4821 *mipsIII:
4822 *mipsIV:
4823 *vr5000:
4824 // start-sanitize-vr4320
4825 *vr4320:
4826 // end-sanitize-vr4320
4827 // start-sanitize-vr5400
4828 *vr5400:
4829 // end-sanitize-vr5400
4830 // start-sanitize-r5900
4831 *r5900:
4832 // end-sanitize-r5900
4833 *r3900:
4834 // start-sanitize-tx19
4835 *tx19:
4836 // end-sanitize-tx19
4837 {
4838 unsigned32 instruction = instruction_0;
4839 int destreg = ((instruction >> 6) & 0x0000001F);
4840 int fs = ((instruction >> 11) & 0x0000001F);
4841 int format = ((instruction >> 21) & 0x00000007);
4842 {
4843 if ((format != fmt_single) && (format != fmt_double))
4844 SignalException(ReservedInstruction,instruction);
4845 else
4846 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4847 }
4848 }
4849
4850
4851 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4852 "round.w.%s<FMT> f<FD>, f<FS>"
4853 *mipsII:
4854 *mipsIII:
4855 *mipsIV:
4856 *vr5000:
4857 // start-sanitize-vr4320
4858 *vr4320:
4859 // end-sanitize-vr4320
4860 // start-sanitize-vr5400
4861 *vr5400:
4862 // end-sanitize-vr5400
4863 // start-sanitize-r5900
4864 *r5900:
4865 // end-sanitize-r5900
4866 *r3900:
4867 // start-sanitize-tx19
4868 *tx19:
4869 // end-sanitize-tx19
4870 {
4871 unsigned32 instruction = instruction_0;
4872 int destreg = ((instruction >> 6) & 0x0000001F);
4873 int fs = ((instruction >> 11) & 0x0000001F);
4874 int format = ((instruction >> 21) & 0x00000007);
4875 {
4876 if ((format != fmt_single) && (format != fmt_double))
4877 SignalException(ReservedInstruction,instruction);
4878 else
4879 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4880 }
4881 }
4882
4883
4884 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4885 *mipsIV:
4886 "rsqrt.%s<FMT> f<FD>, f<FS>"
4887 *vr5000:
4888 // start-sanitize-vr4320
4889 *vr4320:
4890 // end-sanitize-vr4320
4891 // start-sanitize-vr5400
4892 *vr5400:
4893 // end-sanitize-vr5400
4894 {
4895 unsigned32 instruction = instruction_0;
4896 int destreg = ((instruction >> 6) & 0x0000001F);
4897 int fs = ((instruction >> 11) & 0x0000001F);
4898 int format = ((instruction >> 21) & 0x00000007);
4899 {
4900 if ((format != fmt_single) && (format != fmt_double))
4901 SignalException(ReservedInstruction,instruction);
4902 else
4903 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4904 }
4905 }
4906
4907
4908 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4909 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4910 *mipsII:
4911 *mipsIII:
4912 *mipsIV:
4913 *vr5000:
4914 // start-sanitize-vr4320
4915 *vr4320:
4916 // end-sanitize-vr4320
4917 // start-sanitize-vr5400
4918 *vr5400:
4919 // end-sanitize-vr5400
4920 *r3900:
4921 // start-sanitize-tx19
4922 *tx19:
4923 // end-sanitize-tx19
4924 {
4925 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4926 }
4927
4928
4929 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
4930 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
4931 *mipsIV:
4932 *vr5000:
4933 // start-sanitize-vr4320
4934 *vr4320:
4935 // end-sanitize-vr4320
4936 // start-sanitize-vr5400
4937 *vr5400:
4938 // end-sanitize-vr5400
4939 {
4940 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4941 }
4942
4943
4944 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4945 "sqrt.%s<FMT> f<FD>, f<FS>"
4946 *mipsII:
4947 *mipsIII:
4948 *mipsIV:
4949 *vr5000:
4950 // start-sanitize-vr4320
4951 *vr4320:
4952 // end-sanitize-vr4320
4953 // start-sanitize-vr5400
4954 *vr5400:
4955 // end-sanitize-vr5400
4956 *r3900:
4957 // start-sanitize-tx19
4958 *tx19:
4959 // end-sanitize-tx19
4960 {
4961 unsigned32 instruction = instruction_0;
4962 int destreg = ((instruction >> 6) & 0x0000001F);
4963 int fs = ((instruction >> 11) & 0x0000001F);
4964 int format = ((instruction >> 21) & 0x00000007);
4965 {
4966 if ((format != fmt_single) && (format != fmt_double))
4967 SignalException(ReservedInstruction,instruction);
4968 else
4969 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4970 }
4971 }
4972
4973
4974 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4975 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4976 *mipsI,mipsII,mipsIII,mipsIV:
4977 *vr5000:
4978 // start-sanitize-vr4320
4979 *vr4320:
4980 // end-sanitize-vr4320
4981 // start-sanitize-vr5400
4982 *vr5400:
4983 // end-sanitize-vr5400
4984 *r3900:
4985 // start-sanitize-tx19
4986 *tx19:
4987 // end-sanitize-tx19
4988 {
4989 unsigned32 instruction = instruction_0;
4990 int destreg = ((instruction >> 6) & 0x0000001F);
4991 int fs = ((instruction >> 11) & 0x0000001F);
4992 int ft = ((instruction >> 16) & 0x0000001F);
4993 int format = ((instruction >> 21) & 0x00000007);
4994 {
4995 if ((format != fmt_single) && (format != fmt_double))
4996 SignalException(ReservedInstruction,instruction);
4997 else
4998 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4999 }
5000 }
5001
5002
5003
5004 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5005 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5006 *mipsI,mipsII,mipsIII,mipsIV:
5007 *vr5000:
5008 // start-sanitize-vr4320
5009 *vr4320:
5010 // end-sanitize-vr4320
5011 // start-sanitize-vr5400
5012 *vr5400:
5013 // end-sanitize-vr5400
5014 // start-sanitize-r5900
5015 *r5900:
5016 // end-sanitize-r5900
5017 *r3900:
5018 // start-sanitize-tx19
5019 *tx19:
5020 // end-sanitize-tx19
5021 {
5022 unsigned32 instruction = instruction_0;
5023 signed_word offset = EXTEND16 (OFFSET);
5024 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5025 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5026 {
5027 address_word vaddr = ((uword64)op1 + offset);
5028 address_word paddr;
5029 int uncached;
5030 if ((vaddr & 3) != 0)
5031 SignalExceptionAddressStore();
5032 else
5033 {
5034 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5035 {
5036 uword64 memval = 0;
5037 uword64 memval1 = 0;
5038 uword64 mask = 0x7;
5039 unsigned int byte;
5040 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5041 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5042 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5043 {
5044 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5045 }
5046 }
5047 }
5048 }
5049 }
5050
5051
5052 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5053 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5054 *mipsIV:
5055 *vr5000:
5056 // start-sanitize-vr4320
5057 *vr4320:
5058 // end-sanitize-vr4320
5059 // start-sanitize-vr5400
5060 *vr5400:
5061 // end-sanitize-vr5400
5062 {
5063 unsigned32 instruction = instruction_0;
5064 int fs = ((instruction >> 11) & 0x0000001F);
5065 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5066 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5067 {
5068 address_word vaddr = ((unsigned64)op1 + op2);
5069 address_word paddr;
5070 int uncached;
5071 if ((vaddr & 3) != 0)
5072 SignalExceptionAddressStore();
5073 else
5074 {
5075 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5076 {
5077 unsigned64 memval = 0;
5078 unsigned64 memval1 = 0;
5079 unsigned64 mask = 0x7;
5080 unsigned int byte;
5081 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5082 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5083 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5084 {
5085 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5086 }
5087 }
5088 }
5089 }
5090 }
5091
5092
5093 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5094 "trunc.l.%s<FMT> f<FD>, f<FS>"
5095 *mipsIII:
5096 *mipsIV:
5097 *vr5000:
5098 // start-sanitize-vr4320
5099 *vr4320:
5100 // end-sanitize-vr4320
5101 // start-sanitize-vr5400
5102 *vr5400:
5103 // end-sanitize-vr5400
5104 // start-sanitize-r5900
5105 *r5900:
5106 // end-sanitize-r5900
5107 *r3900:
5108 // start-sanitize-tx19
5109 *tx19:
5110 // end-sanitize-tx19
5111 {
5112 unsigned32 instruction = instruction_0;
5113 int destreg = ((instruction >> 6) & 0x0000001F);
5114 int fs = ((instruction >> 11) & 0x0000001F);
5115 int format = ((instruction >> 21) & 0x00000007);
5116 {
5117 if ((format != fmt_single) && (format != fmt_double))
5118 SignalException(ReservedInstruction,instruction);
5119 else
5120 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5121 }
5122 }
5123
5124
5125 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5126 "trunc.w.%s<FMT> f<FD>, f<FS>"
5127 *mipsII:
5128 *mipsIII:
5129 *mipsIV:
5130 *vr5000:
5131 // start-sanitize-vr4320
5132 *vr4320:
5133 // end-sanitize-vr4320
5134 // start-sanitize-vr5400
5135 *vr5400:
5136 // end-sanitize-vr5400
5137 // start-sanitize-r5900
5138 *r5900:
5139 // end-sanitize-r5900
5140 *r3900:
5141 // start-sanitize-tx19
5142 *tx19:
5143 // end-sanitize-tx19
5144 {
5145 unsigned32 instruction = instruction_0;
5146 int destreg = ((instruction >> 6) & 0x0000001F);
5147 int fs = ((instruction >> 11) & 0x0000001F);
5148 int format = ((instruction >> 21) & 0x00000007);
5149 {
5150 if ((format != fmt_single) && (format != fmt_double))
5151 SignalException(ReservedInstruction,instruction);
5152 else
5153 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5154 }
5155 }
5156
5157 \f
5158 //
5159 // MIPS Architecture:
5160 //
5161 // System Control Instruction Set (COP0)
5162 //
5163
5164
5165 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5166 "bc0f <OFFSET>"
5167 *mipsI,mipsII,mipsIII,mipsIV:
5168 *vr5000:
5169 // start-sanitize-vr4320
5170 *vr4320:
5171 // end-sanitize-vr4320
5172 // start-sanitize-vr5400
5173 *vr5400:
5174 // end-sanitize-vr5400
5175 // start-sanitize-r5900
5176 *r5900:
5177 // end-sanitize-r5900
5178
5179
5180 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5181 "bc0fl <OFFSET>"
5182 *mipsI,mipsII,mipsIII,mipsIV:
5183 *vr5000:
5184 // start-sanitize-vr4320
5185 *vr4320:
5186 // end-sanitize-vr4320
5187 // start-sanitize-vr5400
5188 *vr5400:
5189 // end-sanitize-vr5400
5190 // start-sanitize-r5900
5191 *r5900:
5192 // end-sanitize-r5900
5193
5194
5195 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5196 "bc0t <OFFSET>"
5197 *mipsI,mipsII,mipsIII,mipsIV:
5198 // start-sanitize-r5900
5199 *r5900:
5200 // end-sanitize-r5900
5201
5202
5203
5204 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5205 "bc0tl <OFFSET>"
5206 *mipsI,mipsII,mipsIII,mipsIV:
5207 *vr5000:
5208 // start-sanitize-vr4320
5209 *vr4320:
5210 // end-sanitize-vr4320
5211 // start-sanitize-vr5400
5212 *vr5400:
5213 // end-sanitize-vr5400
5214 // start-sanitize-r5900
5215 *r5900:
5216 // end-sanitize-r5900
5217
5218
5219 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5220 *mipsIII:
5221 *mipsIV:
5222 *vr5000:
5223 // start-sanitize-vr4320
5224 *vr4320:
5225 // end-sanitize-vr4320
5226 // start-sanitize-vr5400
5227 *vr5400:
5228 // end-sanitize-vr5400
5229 // start-sanitize-r5900
5230 *r5900:
5231 // end-sanitize-r5900
5232 *r3900:
5233 // start-sanitize-tx19
5234 *tx19:
5235 // end-sanitize-tx19
5236 {
5237 unsigned32 instruction = instruction_0;
5238 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5239 int hint = ((instruction >> 16) & 0x0000001F);
5240 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5241 {
5242 address_word vaddr = (op1 + offset);
5243 address_word paddr;
5244 int uncached;
5245 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5246 CacheOp(hint,vaddr,paddr,instruction);
5247 }
5248 }
5249
5250
5251 010000,10000,000000000000000,111001:COP0:32::DI
5252 "di"
5253 *mipsI,mipsII,mipsIII,mipsIV:
5254 *vr5000:
5255 // start-sanitize-vr4320
5256 *vr4320:
5257 // end-sanitize-vr4320
5258 // start-sanitize-vr5400
5259 *vr5400:
5260 // end-sanitize-vr5400
5261 // start-sanitize-r5900
5262 *r5900:
5263 // end-sanitize-r5900
5264
5265
5266 010000,10000,000000000000000,111000:COP0:32::EI
5267 "ei"
5268 *mipsI,mipsII,mipsIII,mipsIV:
5269 *vr5000:
5270 // start-sanitize-vr4320
5271 *vr4320:
5272 // end-sanitize-vr4320
5273 // start-sanitize-vr5400
5274 *vr5400:
5275 // end-sanitize-vr5400
5276 // start-sanitize-r5900
5277 *r5900:
5278 // end-sanitize-r5900
5279
5280
5281 010000,10000,000000000000000,011000:COP0:32::ERET
5282 "eret"
5283 *mipsIII:
5284 *mipsIV:
5285 *vr5000:
5286 // start-sanitize-vr4320
5287 *vr4320:
5288 // end-sanitize-vr4320
5289 // start-sanitize-vr5400
5290 *vr5400:
5291 // end-sanitize-vr5400
5292 // start-sanitize-r5900
5293 *r5900:
5294 // end-sanitize-r5900
5295 {
5296 if (SR & status_ERL)
5297 {
5298 /* Oops, not yet available */
5299 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5300 NIA = EPC;
5301 SR &= ~status_ERL;
5302 }
5303 else
5304 {
5305 NIA = EPC;
5306 SR &= ~status_EXL;
5307 }
5308 }
5309
5310
5311 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5312 "mfc0 r<RT>, r<RD> # <REGX>"
5313 *mipsI,mipsII,mipsIII,mipsIV:
5314 *vr5000:
5315 // start-sanitize-vr4320
5316 *vr4320:
5317 // end-sanitize-vr4320
5318 // start-sanitize-vr5400
5319 *vr5400:
5320 // end-sanitize-vr5400
5321 // start-sanitize-r5900
5322 *r5900:
5323 // end-sanitize-r5900
5324 {
5325 TRACE_ALU_INPUT0 ();
5326 DecodeCoproc (instruction_0);
5327 TRACE_ALU_RESULT (GPR[RT]);
5328 }
5329
5330 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5331 "mtc0 r<RT>, r<RD> # <REGX>"
5332 *mipsI,mipsII,mipsIII,mipsIV:
5333 // start-sanitize-tx19
5334 *tx19:
5335 // end-sanitize-tx19
5336 *r3900:
5337 // start-sanitize-vr4320
5338 *vr4320:
5339 // end-sanitize-vr4320
5340 *vr5000:
5341 // start-sanitize-vr5400
5342 *vr5400:
5343 // end-sanitize-vr5400
5344 // start-sanitize-r5900
5345 *r5900:
5346 // end-sanitize-r5900
5347 {
5348 DecodeCoproc (instruction_0);
5349 }
5350
5351
5352 010000,10000,000000000000000,001000:COP0:32::TLBP
5353 "tlbp"
5354 *mipsI,mipsII,mipsIII,mipsIV:
5355 *vr5000:
5356 // start-sanitize-vr4320
5357 *vr4320:
5358 // end-sanitize-vr4320
5359 // start-sanitize-vr5400
5360 *vr5400:
5361 // end-sanitize-vr5400
5362 // start-sanitize-r5900
5363 *r5900:
5364 // end-sanitize-r5900
5365
5366
5367 010000,10000,000000000000000,000001:COP0:32::TLBR
5368 "tlbr"
5369 *mipsI,mipsII,mipsIII,mipsIV:
5370 *vr5000:
5371 // start-sanitize-vr4320
5372 *vr4320:
5373 // end-sanitize-vr4320
5374 // start-sanitize-vr5400
5375 *vr5400:
5376 // end-sanitize-vr5400
5377 // start-sanitize-r5900
5378 *r5900:
5379 // end-sanitize-r5900
5380
5381
5382 010000,10000,000000000000000,000010:COP0:32::TLBWI
5383 "tlbwi"
5384 *mipsI,mipsII,mipsIII,mipsIV:
5385 *vr5000:
5386 // start-sanitize-vr4320
5387 *vr4320:
5388 // end-sanitize-vr4320
5389 // start-sanitize-vr5400
5390 *vr5400:
5391 // end-sanitize-vr5400
5392 // start-sanitize-r5900
5393 *r5900:
5394 // end-sanitize-r5900
5395
5396
5397 010000,10000,000000000000000,000110:COP0:32::TLBWR
5398 "tlbwr"
5399 *mipsI,mipsII,mipsIII,mipsIV:
5400 *vr5000:
5401 // start-sanitize-vr4320
5402 *vr4320:
5403 // end-sanitize-vr4320
5404 // start-sanitize-vr5400
5405 *vr5400:
5406 // end-sanitize-vr5400
5407 // start-sanitize-r5900
5408 *r5900:
5409 // end-sanitize-r5900
5410
5411 \f
5412 :include:::m16.igen
5413 // start-sanitize-vr4320
5414 :include::vr4320:vr4320.igen
5415 // end-sanitize-vr4320
5416 // start-sanitize-vr5400
5417 :include::vr5400:vr5400.igen
5418 :include:64,f::mdmx.igen
5419 // end-sanitize-vr5400
5420 // start-sanitize-r5900
5421 :include::r5900:r5900.igen
5422 // end-sanitize-r5900
5423 :include:::tx.igen
5424 \f
5425 // start-sanitize-cygnus-never
5426
5427 // // FIXME FIXME FIXME What is this instruction?
5428 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5429 // *mipsI:
5430 // *mipsII:
5431 // *mipsIII:
5432 // *mipsIV:
5433 // // start-sanitize-r5900
5434 // *r5900:
5435 // // end-sanitize-r5900
5436 // *r3900:
5437 // // start-sanitize-tx19
5438 // *tx19:
5439 // // end-sanitize-tx19
5440 // {
5441 // unsigned32 instruction = instruction_0;
5442 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5443 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5444 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5445 // {
5446 // if (CoProcPresent(3))
5447 // SignalException(CoProcessorUnusable);
5448 // else
5449 // SignalException(ReservedInstruction,instruction);
5450 // }
5451 // }
5452
5453 // end-sanitize-cygnus-never
5454 // start-sanitize-cygnus-never
5455
5456 // // FIXME FIXME FIXME What is this?
5457 // 11100,******,00001:RR:16::SDBBP
5458 // *mips16:
5459 // {
5460 // unsigned32 instruction = instruction_0;
5461 // if (have_extendval)
5462 // SignalException (ReservedInstruction, instruction);
5463 // {
5464 // SignalException(DebugBreakPoint,instruction);
5465 // }
5466 // }
5467
5468 // end-sanitize-cygnus-never
5469 // start-sanitize-cygnus-never
5470
5471 // // FIXME FIXME FIXME What is this?
5472 // 000000,********************,001110:SPECIAL:32::SDBBP
5473 // *r3900:
5474 // {
5475 // unsigned32 instruction = instruction_0;
5476 // {
5477 // SignalException(DebugBreakPoint,instruction);
5478 // }
5479 // }
5480
5481 // end-sanitize-cygnus-never
5482 // start-sanitize-cygnus-never
5483
5484 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5485 // // isn't yet reconized by this simulator.
5486 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5487 // *vr4100:
5488 // {
5489 // unsigned32 instruction = instruction_0;
5490 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5491 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5492 // {
5493 // CHECKHILO("Multiply-Add");
5494 // {
5495 // unsigned64 temp = (op1 * op2);
5496 // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5497 // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5498 // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5499 // }
5500 // }
5501 // }
5502
5503 // end-sanitize-cygnus-never
5504 // start-sanitize-cygnus-never
5505
5506 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5507 // // isn't yet reconized by this simulator.
5508 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5509 // *vr4100:
5510 // {
5511 // unsigned32 instruction = instruction_0;
5512 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5513 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5514 // {
5515 // CHECKHILO("Multiply-Add");
5516 // {
5517 // unsigned64 temp = (op1 * op2);
5518 // LO = LO + temp;
5519 // }
5520 // }
5521 // }
5522
5523 // end-sanitize-cygnus-never
This page took 0.141657 seconds and 4 git commands to generate.