4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator
34 :model:::mipsI:mips3000:
35 :model:::mipsII:mips6000:
36 :model:::mipsIII:mips4000:
37 :model:::mipsIV:mips8000:
38 :model:::mips16:mips16:
39 // start-sanitize-r5900
40 :model:::r5900:mips5900:
42 :model:::r3900:mips3900:
43 // start-sanitize-tx19
46 // start-sanitize-vr4320
47 :model:::vr4320:mips4320:
48 // end-sanitize-vr4320
49 // start-sanitize-vr5400
50 :model:::vr5400:mips5400:
52 // end-sanitize-vr5400
53 :model:::vr5000:mips5000:
57 // Pseudo instructions known by IGEN
60 SignalException (ReservedInstruction, 0);
64 // Pseudo instructions known by interp.c
65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
69 SignalException (ReservedInstruction, instruction_0);
76 // Simulate a 32 bit delayslot instruction
79 :function:::address_word:delayslot32:address_word target
81 instruction_word delay_insn;
82 sim_events_slip (SD, 1);
84 CIA = CIA + 4; /* NOTE not mips16 */
85 STATE |= simDELAYSLOT;
86 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
87 idecode_issue (CPU_, delay_insn, (CIA));
88 STATE &= ~simDELAYSLOT;
92 :function:::address_word:nullify_next_insn32:
94 sim_events_slip (SD, 1);
95 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
103 // Check that an access to a HI/LO register meets timing requirements
105 // The following requirements exist:
107 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
108 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
109 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
110 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
113 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
115 if (history->mf.timestamp + 3 > time)
117 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
118 itable[MY_INDEX].name,
120 (long) history->mf.cia);
126 :function:::int:check_mt_hilo:hilo_history *history
128 signed64 time = sim_events_time (SD);
129 int ok = check_mf_cycles (SD_, history, time, "MT");
130 history->mt.timestamp = time;
131 history->mt.cia = CIA;
135 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
137 signed64 time = sim_events_time (SD);
140 && peer->mt.timestamp > history->op.timestamp
141 && history->mf.timestamp < history->op.timestamp)
143 /* The peer has been written to since the last OP yet we have
145 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
146 itable[MY_INDEX].name,
148 (long) history->op.cia,
149 (long) peer->mt.cia);
152 history->mf.timestamp = time;
153 history->mf.cia = CIA;
157 :function:::int:check_op_hilo:hilo_history *hi, hilo_history *lo
158 *mipsI,mipsII,mipsIII,mipsIV:
160 // start-sanitize-vr4320
162 // end-sanitize-vr4320
163 // start-sanitize-vr5400
165 // end-sanitize-vr5400
167 // start-sanitize-tx19
170 // start-sanitize-r5900
172 // end-sanitize-r5900
174 signed64 time = sim_events_time (SD);
175 int ok = (check_mf_cycles (SD_, hi, time, "OP")
176 && check_mf_cycles (SD_, lo, time, "OP"));
177 hi->op.timestamp = time;
178 lo->op.timestamp = time;
187 // Mips Architecture:
189 // CPU Instruction Set (mipsI - mipsIV)
194 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
195 "add r<RD>, r<RS>, r<RT>"
196 *mipsI,mipsII,mipsIII,mipsIV:
198 // start-sanitize-vr4320
200 // end-sanitize-vr4320
201 // start-sanitize-vr5400
203 // end-sanitize-vr5400
204 // start-sanitize-r5900
206 // end-sanitize-r5900
208 // start-sanitize-tx19
212 ALU32_BEGIN (GPR[RS]);
219 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
220 "addi r<RT>, r<RS>, IMMEDIATE"
221 *mipsI,mipsII,mipsIII,mipsIV:
223 // start-sanitize-vr4320
225 // end-sanitize-vr4320
226 // start-sanitize-vr5400
228 // end-sanitize-vr5400
229 // start-sanitize-r5900
231 // end-sanitize-r5900
233 // start-sanitize-tx19
237 ALU32_BEGIN (GPR[RS]);
238 ALU32_ADD (EXTEND16 (IMMEDIATE));
244 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
246 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
247 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
248 TRACE_ALU_RESULT (GPR[rt]);
251 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
252 "addiu r<RT>, r<RS>, <IMMEDIATE>"
253 *mipsI,mipsII,mipsIII,mipsIV:
255 // start-sanitize-vr4320
257 // end-sanitize-vr4320
258 // start-sanitize-vr5400
260 // end-sanitize-vr5400
261 // start-sanitize-r5900
263 // end-sanitize-r5900
265 // start-sanitize-tx19
269 do_addiu (SD_, RS, RT, IMMEDIATE);
274 :function:::void:do_addu:int rs, int rt, int rd
276 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
277 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
278 TRACE_ALU_RESULT (GPR[rd]);
281 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
282 "addu r<RD>, r<RS>, r<RT>"
283 *mipsI,mipsII,mipsIII,mipsIV:
285 // start-sanitize-vr4320
287 // end-sanitize-vr4320
288 // start-sanitize-vr5400
290 // end-sanitize-vr5400
291 // start-sanitize-r5900
293 // end-sanitize-r5900
295 // start-sanitize-tx19
299 do_addu (SD_, RS, RT, RD);
304 :function:::void:do_and:int rs, int rt, int rd
306 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
307 GPR[rd] = GPR[rs] & GPR[rt];
308 TRACE_ALU_RESULT (GPR[rd]);
311 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
312 "and r<RD>, r<RS>, r<RT>"
313 *mipsI,mipsII,mipsIII,mipsIV:
315 // start-sanitize-vr4320
317 // end-sanitize-vr4320
318 // start-sanitize-vr5400
320 // end-sanitize-vr5400
321 // start-sanitize-r5900
323 // end-sanitize-r5900
325 // start-sanitize-tx19
329 do_and (SD_, RS, RT, RD);
334 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
335 "and r<RT>, r<RS>, <IMMEDIATE>"
336 *mipsI,mipsII,mipsIII,mipsIV:
338 // start-sanitize-vr4320
340 // end-sanitize-vr4320
341 // start-sanitize-vr5400
343 // end-sanitize-vr5400
344 // start-sanitize-r5900
346 // end-sanitize-r5900
348 // start-sanitize-tx19
352 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
353 GPR[RT] = GPR[RS] & IMMEDIATE;
354 TRACE_ALU_RESULT (GPR[RT]);
359 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
360 "beq r<RS>, r<RT>, <OFFSET>"
361 *mipsI,mipsII,mipsIII,mipsIV:
363 // start-sanitize-vr4320
365 // end-sanitize-vr4320
366 // start-sanitize-vr5400
368 // end-sanitize-vr5400
369 // start-sanitize-r5900
371 // end-sanitize-r5900
373 // start-sanitize-tx19
377 address_word offset = EXTEND16 (OFFSET) << 2;
378 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
379 DELAY_SLOT (NIA + offset);
384 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
385 "beql r<RS>, r<RT>, <OFFSET>"
390 // start-sanitize-vr4320
392 // end-sanitize-vr4320
393 // start-sanitize-vr5400
395 // end-sanitize-vr5400
396 // start-sanitize-r5900
398 // end-sanitize-r5900
400 // start-sanitize-tx19
404 address_word offset = EXTEND16 (OFFSET) << 2;
405 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
406 DELAY_SLOT (NIA + offset);
408 NULLIFY_NEXT_INSTRUCTION ();
413 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
414 "bgez r<RS>, <OFFSET>"
415 *mipsI,mipsII,mipsIII,mipsIV:
417 // start-sanitize-vr4320
419 // end-sanitize-vr4320
420 // start-sanitize-vr5400
422 // end-sanitize-vr5400
423 // start-sanitize-r5900
425 // end-sanitize-r5900
427 // start-sanitize-tx19
431 address_word offset = EXTEND16 (OFFSET) << 2;
432 if ((signed_word) GPR[RS] >= 0)
433 DELAY_SLOT (NIA + offset);
438 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
439 "bgezal r<RS>, <OFFSET>"
440 *mipsI,mipsII,mipsIII,mipsIV:
442 // start-sanitize-vr4320
444 // end-sanitize-vr4320
445 // start-sanitize-vr5400
447 // end-sanitize-vr5400
448 // start-sanitize-r5900
450 // end-sanitize-r5900
452 // start-sanitize-tx19
456 address_word offset = EXTEND16 (OFFSET) << 2;
458 if ((signed_word) GPR[RS] >= 0)
459 DELAY_SLOT (NIA + offset);
464 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
465 "bgezall r<RS>, <OFFSET>"
470 // start-sanitize-vr4320
472 // end-sanitize-vr4320
473 // start-sanitize-vr5400
475 // end-sanitize-vr5400
476 // start-sanitize-r5900
478 // end-sanitize-r5900
480 // start-sanitize-tx19
484 address_word offset = EXTEND16 (OFFSET) << 2;
486 /* NOTE: The branch occurs AFTER the next instruction has been
488 if ((signed_word) GPR[RS] >= 0)
489 DELAY_SLOT (NIA + offset);
491 NULLIFY_NEXT_INSTRUCTION ();
496 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
497 "bgezl r<RS>, <OFFSET>"
502 // start-sanitize-vr4320
504 // end-sanitize-vr4320
505 // start-sanitize-vr5400
507 // end-sanitize-vr5400
508 // start-sanitize-r5900
510 // end-sanitize-r5900
512 // start-sanitize-tx19
516 address_word offset = EXTEND16 (OFFSET) << 2;
517 if ((signed_word) GPR[RS] >= 0)
518 DELAY_SLOT (NIA + offset);
520 NULLIFY_NEXT_INSTRUCTION ();
525 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
526 "bgtz r<RS>, <OFFSET>"
527 *mipsI,mipsII,mipsIII,mipsIV:
529 // start-sanitize-vr4320
531 // end-sanitize-vr4320
532 // start-sanitize-vr5400
534 // end-sanitize-vr5400
535 // start-sanitize-r5900
537 // end-sanitize-r5900
539 // start-sanitize-tx19
543 address_word offset = EXTEND16 (OFFSET) << 2;
544 if ((signed_word) GPR[RS] > 0)
545 DELAY_SLOT (NIA + offset);
550 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
551 "bgtzl r<RS>, <OFFSET>"
556 // start-sanitize-vr4320
558 // end-sanitize-vr4320
559 // start-sanitize-vr5400
561 // end-sanitize-vr5400
562 // start-sanitize-r5900
564 // end-sanitize-r5900
566 // start-sanitize-tx19
570 address_word offset = EXTEND16 (OFFSET) << 2;
571 /* NOTE: The branch occurs AFTER the next instruction has been
573 if ((signed_word) GPR[RS] > 0)
574 DELAY_SLOT (NIA + offset);
576 NULLIFY_NEXT_INSTRUCTION ();
581 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
582 "blez r<RS>, <OFFSET>"
583 *mipsI,mipsII,mipsIII,mipsIV:
585 // start-sanitize-vr4320
587 // end-sanitize-vr4320
588 // start-sanitize-vr5400
590 // end-sanitize-vr5400
591 // start-sanitize-r5900
593 // end-sanitize-r5900
595 // start-sanitize-tx19
599 address_word offset = EXTEND16 (OFFSET) << 2;
600 /* NOTE: The branch occurs AFTER the next instruction has been
602 if ((signed_word) GPR[RS] <= 0)
603 DELAY_SLOT (NIA + offset);
608 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
609 "bgezl r<RS>, <OFFSET>"
614 // start-sanitize-vr4320
616 // end-sanitize-vr4320
617 // start-sanitize-vr5400
619 // end-sanitize-vr5400
620 // start-sanitize-r5900
622 // end-sanitize-r5900
624 // start-sanitize-tx19
628 address_word offset = EXTEND16 (OFFSET) << 2;
629 if ((signed_word) GPR[RS] <= 0)
630 DELAY_SLOT (NIA + offset);
632 NULLIFY_NEXT_INSTRUCTION ();
637 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
638 "bltz r<RS>, <OFFSET>"
639 *mipsI,mipsII,mipsIII,mipsIV:
641 // start-sanitize-vr4320
643 // end-sanitize-vr4320
644 // start-sanitize-vr5400
646 // end-sanitize-vr5400
647 // start-sanitize-r5900
649 // end-sanitize-r5900
651 // start-sanitize-tx19
655 address_word offset = EXTEND16 (OFFSET) << 2;
656 if ((signed_word) GPR[RS] < 0)
657 DELAY_SLOT (NIA + offset);
662 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
663 "bltzal r<RS>, <OFFSET>"
664 *mipsI,mipsII,mipsIII,mipsIV:
666 // start-sanitize-vr4320
668 // end-sanitize-vr4320
669 // start-sanitize-vr5400
671 // end-sanitize-vr5400
672 // start-sanitize-r5900
674 // end-sanitize-r5900
676 // start-sanitize-tx19
680 address_word offset = EXTEND16 (OFFSET) << 2;
682 /* NOTE: The branch occurs AFTER the next instruction has been
684 if ((signed_word) GPR[RS] < 0)
685 DELAY_SLOT (NIA + offset);
690 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
691 "bltzall r<RS>, <OFFSET>"
696 // start-sanitize-vr4320
698 // end-sanitize-vr4320
699 // start-sanitize-vr5400
701 // end-sanitize-vr5400
702 // start-sanitize-r5900
704 // end-sanitize-r5900
706 // start-sanitize-tx19
710 address_word offset = EXTEND16 (OFFSET) << 2;
712 if ((signed_word) GPR[RS] < 0)
713 DELAY_SLOT (NIA + offset);
715 NULLIFY_NEXT_INSTRUCTION ();
720 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
721 "bltzl r<RS>, <OFFSET>"
726 // start-sanitize-vr4320
728 // end-sanitize-vr4320
729 // start-sanitize-vr5400
731 // end-sanitize-vr5400
732 // start-sanitize-r5900
734 // end-sanitize-r5900
736 // start-sanitize-tx19
740 address_word offset = EXTEND16 (OFFSET) << 2;
741 /* NOTE: The branch occurs AFTER the next instruction has been
743 if ((signed_word) GPR[RS] < 0)
744 DELAY_SLOT (NIA + offset);
746 NULLIFY_NEXT_INSTRUCTION ();
751 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
752 "bne r<RS>, r<RT>, <OFFSET>"
753 *mipsI,mipsII,mipsIII,mipsIV:
755 // start-sanitize-vr4320
757 // end-sanitize-vr4320
758 // start-sanitize-vr5400
760 // end-sanitize-vr5400
761 // start-sanitize-r5900
763 // end-sanitize-r5900
765 // start-sanitize-tx19
769 address_word offset = EXTEND16 (OFFSET) << 2;
770 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
771 DELAY_SLOT (NIA + offset);
776 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
777 "bnel r<RS>, r<RT>, <OFFSET>"
782 // start-sanitize-vr4320
784 // end-sanitize-vr4320
785 // start-sanitize-vr5400
787 // end-sanitize-vr5400
788 // start-sanitize-r5900
790 // end-sanitize-r5900
792 // start-sanitize-tx19
796 address_word offset = EXTEND16 (OFFSET) << 2;
797 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
798 DELAY_SLOT (NIA + offset);
800 NULLIFY_NEXT_INSTRUCTION ();
805 000000,20.CODE,001101:SPECIAL:32::BREAK
807 *mipsI,mipsII,mipsIII,mipsIV:
809 // start-sanitize-vr4320
811 // end-sanitize-vr4320
812 // start-sanitize-vr5400
814 // end-sanitize-vr5400
815 // start-sanitize-r5900
817 // end-sanitize-r5900
819 // start-sanitize-tx19
823 SignalException(BreakPoint, instruction_0);
828 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
830 *mipsI,mipsII,mipsIII,mipsIV:
831 // start-sanitize-r5900
833 // end-sanitize-r5900
835 // start-sanitize-tx19
839 DecodeCoproc (instruction_0);
844 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
845 "dadd r<RD>, r<RS>, r<RT>"
849 // start-sanitize-vr4320
851 // end-sanitize-vr4320
852 // start-sanitize-vr5400
854 // end-sanitize-vr5400
855 // start-sanitize-r5900
857 // end-sanitize-r5900
858 // start-sanitize-tx19
862 /* this check's for overflow */
863 ALU64_BEGIN (GPR[RS]);
870 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
871 "daddi r<RT>, r<RS>, <IMMEDIATE>"
875 // start-sanitize-vr4320
877 // end-sanitize-vr4320
878 // start-sanitize-vr5400
880 // end-sanitize-vr5400
881 // start-sanitize-r5900
883 // end-sanitize-r5900
884 // start-sanitize-tx19
888 ALU64_BEGIN (GPR[RS]);
889 ALU64_ADD (EXTEND16 (IMMEDIATE));
895 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
897 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
898 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
899 TRACE_ALU_RESULT (GPR[rt]);
902 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
903 "daddu r<RT>, r<RS>, <IMMEDIATE>"
907 // start-sanitize-vr4320
909 // end-sanitize-vr4320
910 // start-sanitize-vr5400
912 // end-sanitize-vr5400
913 // start-sanitize-r5900
915 // end-sanitize-r5900
916 // start-sanitize-tx19
920 do_daddiu (SD_, RS, RT, IMMEDIATE);
925 :function:::void:do_daddu:int rs, int rt, int rd
927 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
928 GPR[rd] = GPR[rs] + GPR[rt];
929 TRACE_ALU_RESULT (GPR[rd]);
932 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
933 "daddu r<RD>, r<RS>, r<RT>"
937 // start-sanitize-vr4320
939 // end-sanitize-vr4320
940 // start-sanitize-vr5400
942 // end-sanitize-vr5400
943 // start-sanitize-r5900
945 // end-sanitize-r5900
946 // start-sanitize-tx19
950 do_daddu (SD_, RS, RT, RD);
955 :function:64::void:do_ddiv:int rs, int rt
957 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
958 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
960 signed64 n = GPR[rs];
961 signed64 d = GPR[rt];
964 LO = SIGNED64 (0x8000000000000000);
967 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
969 LO = SIGNED64 (0x8000000000000000);
978 TRACE_ALU_RESULT2 (HI, LO);
981 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
986 // start-sanitize-vr4320
988 // end-sanitize-vr4320
989 // start-sanitize-vr5400
991 // end-sanitize-vr5400
992 // start-sanitize-r5900
994 // end-sanitize-r5900
995 // start-sanitize-tx19
999 do_ddiv (SD_, RS, RT);
1004 :function:64::void:do_ddivu:int rs, int rt
1006 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
1007 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1009 unsigned64 n = GPR[rs];
1010 unsigned64 d = GPR[rt];
1013 LO = SIGNED64 (0x8000000000000000);
1022 TRACE_ALU_RESULT2 (HI, LO);
1025 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1026 "ddivu r<RS>, r<RT>"
1030 // start-sanitize-vr4320
1032 // end-sanitize-vr4320
1033 // start-sanitize-vr5400
1035 // end-sanitize-vr5400
1036 // start-sanitize-tx19
1038 // end-sanitize-tx19
1040 do_ddivu (SD_, RS, RT);
1045 :function:::void:do_div:int rs, int rt
1047 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
1048 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1050 signed32 n = GPR[rs];
1051 signed32 d = GPR[rt];
1054 LO = EXTEND32 (0x80000000);
1057 else if (n == SIGNED32 (0x80000000) && d == -1)
1059 LO = EXTEND32 (0x80000000);
1064 LO = EXTEND32 (n / d);
1065 HI = EXTEND32 (n % d);
1068 TRACE_ALU_RESULT2 (HI, LO);
1071 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1073 *mipsI,mipsII,mipsIII,mipsIV:
1075 // start-sanitize-vr4320
1077 // end-sanitize-vr4320
1078 // start-sanitize-vr5400
1080 // end-sanitize-vr5400
1081 // start-sanitize-r5900
1083 // end-sanitize-r5900
1085 // start-sanitize-tx19
1087 // end-sanitize-tx19
1089 do_div (SD_, RS, RT);
1094 :function:::void:do_divu:int rs, int rt
1096 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
1097 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1099 unsigned32 n = GPR[rs];
1100 unsigned32 d = GPR[rt];
1103 LO = EXTEND32 (0x80000000);
1108 LO = EXTEND32 (n / d);
1109 HI = EXTEND32 (n % d);
1112 TRACE_ALU_RESULT2 (HI, LO);
1115 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1117 *mipsI,mipsII,mipsIII,mipsIV:
1119 // start-sanitize-vr4320
1121 // end-sanitize-vr4320
1122 // start-sanitize-vr5400
1124 // end-sanitize-vr5400
1125 // start-sanitize-r5900
1127 // end-sanitize-r5900
1129 // start-sanitize-tx19
1131 // end-sanitize-tx19
1133 do_divu (SD_, RS, RT);
1138 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1148 unsigned64 op1 = GPR[rs];
1149 unsigned64 op2 = GPR[rt];
1150 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
1151 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1152 /* make signed multiply unsigned */
1167 /* multuply out the 4 sub products */
1168 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1169 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1170 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1171 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1172 /* add the products */
1173 mid = ((unsigned64) VH4_8 (m00)
1174 + (unsigned64) VL4_8 (m10)
1175 + (unsigned64) VL4_8 (m01));
1176 lo = U8_4 (mid, m00);
1178 + (unsigned64) VH4_8 (mid)
1179 + (unsigned64) VH4_8 (m01)
1180 + (unsigned64) VH4_8 (m10));
1190 /* save the result HI/LO (and a gpr) */
1195 TRACE_ALU_RESULT2 (HI, LO);
1198 :function:::void:do_dmult:int rs, int rt, int rd
1200 do_dmultx (SD_, rs, rt, rd, 1);
1203 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1204 "dmult r<RS>, r<RT>"
1206 // start-sanitize-tx19
1208 // end-sanitize-tx19
1209 // start-sanitize-vr4320
1211 // end-sanitize-vr4320
1213 do_dmult (SD_, RS, RT, 0);
1216 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1217 "dmult r<RS>, r<RT>":RD == 0
1218 "dmult r<RD>, r<RS>, r<RT>"
1220 // start-sanitize-vr5400
1222 // end-sanitize-vr5400
1224 do_dmult (SD_, RS, RT, RD);
1229 :function:::void:do_dmultu:int rs, int rt, int rd
1231 do_dmultx (SD_, rs, rt, rd, 0);
1234 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1235 "dmultu r<RS>, r<RT>"
1237 // start-sanitize-tx19
1239 // end-sanitize-tx19
1240 // start-sanitize-vr4320
1242 // end-sanitize-vr4320
1244 do_dmultu (SD_, RS, RT, 0);
1247 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1248 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1249 "dmultu r<RS>, r<RT>"
1251 // start-sanitize-vr5400
1253 // end-sanitize-vr5400
1255 do_dmultu (SD_, RS, RT, RD);
1260 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1261 "dsll r<RD>, r<RT>, <SHIFT>"
1265 // start-sanitize-vr4320
1267 // end-sanitize-vr4320
1268 // start-sanitize-vr5400
1270 // end-sanitize-vr5400
1271 // start-sanitize-r5900
1273 // end-sanitize-r5900
1274 // start-sanitize-tx19
1276 // end-sanitize-tx19
1279 GPR[RD] = GPR[RT] << s;
1283 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1284 "dsll32 r<RD>, r<RT>, <SHIFT>"
1288 // start-sanitize-vr4320
1290 // end-sanitize-vr4320
1291 // start-sanitize-vr5400
1293 // end-sanitize-vr5400
1294 // start-sanitize-r5900
1296 // end-sanitize-r5900
1297 // start-sanitize-tx19
1299 // end-sanitize-tx19
1302 GPR[RD] = GPR[RT] << s;
1307 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1308 "dsllv r<RD>, r<RT>, r<RS>"
1312 // start-sanitize-vr4320
1314 // end-sanitize-vr4320
1315 // start-sanitize-vr5400
1317 // end-sanitize-vr5400
1318 // start-sanitize-r5900
1320 // end-sanitize-r5900
1321 // start-sanitize-tx19
1323 // end-sanitize-tx19
1325 int s = MASKED64 (GPR[RS], 5, 0);
1326 GPR[RD] = GPR[RT] << s;
1331 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1332 "dsra r<RD>, r<RT>, <SHIFT>"
1336 // start-sanitize-vr4320
1338 // end-sanitize-vr4320
1339 // start-sanitize-vr5400
1341 // end-sanitize-vr5400
1342 // start-sanitize-r5900
1344 // end-sanitize-r5900
1345 // start-sanitize-tx19
1347 // end-sanitize-tx19
1350 GPR[RD] = ((signed64) GPR[RT]) >> s;
1354 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1355 "dsra32 r<RT>, r<RD>, <SHIFT>"
1359 // start-sanitize-vr4320
1361 // end-sanitize-vr4320
1362 // start-sanitize-vr5400
1364 // end-sanitize-vr5400
1365 // start-sanitize-r5900
1367 // end-sanitize-r5900
1368 // start-sanitize-tx19
1370 // end-sanitize-tx19
1373 GPR[RD] = ((signed64) GPR[RT]) >> s;
1377 :function:::void:do_dsrav:int rs, int rt, int rd
1379 int s = MASKED64 (GPR[rs], 5, 0);
1380 TRACE_ALU_INPUT2 (GPR[rt], s);
1381 GPR[rd] = ((signed64) GPR[rt]) >> s;
1382 TRACE_ALU_RESULT (GPR[rd]);
1385 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1386 "dsra32 r<RT>, r<RD>, r<RS>"
1390 // start-sanitize-vr4320
1392 // end-sanitize-vr4320
1393 // start-sanitize-vr5400
1395 // end-sanitize-vr5400
1396 // start-sanitize-r5900
1398 // end-sanitize-r5900
1399 // start-sanitize-tx19
1401 // end-sanitize-tx19
1403 do_dsrav (SD_, RS, RT, RD);
1407 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1408 "dsrl r<RD>, r<RT>, <SHIFT>"
1412 // start-sanitize-vr4320
1414 // end-sanitize-vr4320
1415 // start-sanitize-vr5400
1417 // end-sanitize-vr5400
1418 // start-sanitize-r5900
1420 // end-sanitize-r5900
1421 // start-sanitize-tx19
1423 // end-sanitize-tx19
1426 GPR[RD] = (unsigned64) GPR[RT] >> s;
1430 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1431 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1435 // start-sanitize-vr4320
1437 // end-sanitize-vr4320
1438 // start-sanitize-vr5400
1440 // end-sanitize-vr5400
1441 // start-sanitize-r5900
1443 // end-sanitize-r5900
1444 // start-sanitize-tx19
1446 // end-sanitize-tx19
1449 GPR[RD] = (unsigned64) GPR[RT] >> s;
1453 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1454 "dsrl32 r<RD>, r<RT>, r<RS>"
1458 // start-sanitize-vr4320
1460 // end-sanitize-vr4320
1461 // start-sanitize-vr5400
1463 // end-sanitize-vr5400
1464 // start-sanitize-r5900
1466 // end-sanitize-r5900
1467 // start-sanitize-tx19
1469 // end-sanitize-tx19
1471 int s = MASKED64 (GPR[RS], 5, 0);
1472 GPR[RD] = (unsigned64) GPR[RT] >> s;
1476 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1477 "dsub r<RD>, r<RS>, r<RT>"
1481 // start-sanitize-vr4320
1483 // end-sanitize-vr4320
1484 // start-sanitize-vr5400
1486 // end-sanitize-vr5400
1487 // start-sanitize-r5900
1489 // end-sanitize-r5900
1490 // start-sanitize-tx19
1492 // end-sanitize-tx19
1494 ALU64_BEGIN (GPR[RS]);
1495 ALU64_SUB (GPR[RT]);
1496 ALU64_END (GPR[RD]);
1500 :function:::void:do_dsubu:int rs, int rt, int rd
1502 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1503 GPR[rd] = GPR[rs] - GPR[rt];
1504 TRACE_ALU_RESULT (GPR[rd]);
1507 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1508 "dsubu r<RD>, r<RS>, r<RT>"
1512 // start-sanitize-vr4320
1514 // end-sanitize-vr4320
1515 // start-sanitize-vr5400
1517 // end-sanitize-vr5400
1518 // start-sanitize-r5900
1520 // end-sanitize-r5900
1521 // start-sanitize-tx19
1523 // end-sanitize-tx19
1525 do_dsubu (SD_, RS, RT, RD);
1529 000010,26.INSTR_INDEX:NORMAL:32::J
1531 *mipsI,mipsII,mipsIII,mipsIV:
1533 // start-sanitize-vr4320
1535 // end-sanitize-vr4320
1536 // start-sanitize-vr5400
1538 // end-sanitize-vr5400
1539 // start-sanitize-r5900
1541 // end-sanitize-r5900
1543 // start-sanitize-tx19
1545 // end-sanitize-tx19
1547 /* NOTE: The region used is that of the delay slot NIA and NOT the
1548 current instruction */
1549 address_word region = (NIA & MASK (63, 28));
1550 DELAY_SLOT (region | (INSTR_INDEX << 2));
1554 000011,26.INSTR_INDEX:NORMAL:32::JAL
1556 *mipsI,mipsII,mipsIII,mipsIV:
1558 // start-sanitize-vr4320
1560 // end-sanitize-vr4320
1561 // start-sanitize-vr5400
1563 // end-sanitize-vr5400
1564 // start-sanitize-r5900
1566 // end-sanitize-r5900
1568 // start-sanitize-tx19
1570 // end-sanitize-tx19
1572 /* NOTE: The region used is that of the delay slot and NOT the
1573 current instruction */
1574 address_word region = (NIA & MASK (63, 28));
1576 DELAY_SLOT (region | (INSTR_INDEX << 2));
1580 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1581 "jalr r<RS>":RD == 31
1583 *mipsI,mipsII,mipsIII,mipsIV:
1585 // start-sanitize-vr4320
1587 // end-sanitize-vr4320
1588 // start-sanitize-vr5400
1590 // end-sanitize-vr5400
1591 // start-sanitize-r5900
1593 // end-sanitize-r5900
1595 // start-sanitize-tx19
1597 // end-sanitize-tx19
1599 address_word temp = GPR[RS];
1605 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1607 *mipsI,mipsII,mipsIII,mipsIV:
1609 // start-sanitize-vr4320
1611 // end-sanitize-vr4320
1612 // start-sanitize-vr5400
1614 // end-sanitize-vr5400
1615 // start-sanitize-r5900
1617 // end-sanitize-r5900
1619 // start-sanitize-tx19
1621 // end-sanitize-tx19
1623 DELAY_SLOT (GPR[RS]);
1627 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1629 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1630 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1631 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1638 vaddr = base + offset;
1639 if ((vaddr & access) != 0)
1640 SignalExceptionAddressLoad ();
1641 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1642 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1643 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1644 byte = ((vaddr & mask) ^ bigendiancpu);
1645 return (memval >> (8 * byte));
1649 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1650 "lb r<RT>, <OFFSET>(r<BASE>)"
1651 *mipsI,mipsII,mipsIII,mipsIV:
1653 // start-sanitize-vr4320
1655 // end-sanitize-vr4320
1656 // start-sanitize-vr5400
1658 // end-sanitize-vr5400
1659 // start-sanitize-r5900
1661 // end-sanitize-r5900
1663 // start-sanitize-tx19
1665 // end-sanitize-tx19
1667 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1671 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1672 "lbu r<RT>, <OFFSET>(r<BASE>)"
1673 *mipsI,mipsII,mipsIII,mipsIV:
1675 // start-sanitize-vr4320
1677 // end-sanitize-vr4320
1678 // start-sanitize-vr5400
1680 // end-sanitize-vr5400
1681 // start-sanitize-r5900
1683 // end-sanitize-r5900
1685 // start-sanitize-tx19
1687 // end-sanitize-tx19
1689 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1693 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1694 "ld r<RT>, <OFFSET>(r<BASE>)"
1698 // start-sanitize-vr4320
1700 // end-sanitize-vr4320
1701 // start-sanitize-vr5400
1703 // end-sanitize-vr5400
1704 // start-sanitize-r5900
1706 // end-sanitize-r5900
1707 // start-sanitize-tx19
1709 // end-sanitize-tx19
1711 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1715 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1716 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1721 // start-sanitize-vr4320
1723 // end-sanitize-vr4320
1724 // start-sanitize-vr5400
1726 // end-sanitize-vr5400
1728 // start-sanitize-tx19
1730 // end-sanitize-tx19
1732 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1738 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1739 "ldl r<RT>, <OFFSET>(r<BASE>)"
1743 // start-sanitize-vr4320
1745 // end-sanitize-vr4320
1746 // start-sanitize-vr5400
1748 // end-sanitize-vr5400
1749 // start-sanitize-r5900
1751 // end-sanitize-r5900
1752 // start-sanitize-tx19
1754 // end-sanitize-tx19
1756 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1760 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1761 "ldr r<RT>, <OFFSET>(r<BASE>)"
1765 // start-sanitize-vr4320
1767 // end-sanitize-vr4320
1768 // start-sanitize-vr5400
1770 // end-sanitize-vr5400
1771 // start-sanitize-r5900
1773 // end-sanitize-r5900
1774 // start-sanitize-tx19
1776 // end-sanitize-tx19
1778 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1782 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1783 "lh r<RT>, <OFFSET>(r<BASE>)"
1784 *mipsI,mipsII,mipsIII,mipsIV:
1786 // start-sanitize-vr4320
1788 // end-sanitize-vr4320
1789 // start-sanitize-vr5400
1791 // end-sanitize-vr5400
1792 // start-sanitize-r5900
1794 // end-sanitize-r5900
1796 // start-sanitize-tx19
1798 // end-sanitize-tx19
1800 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1804 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1805 "lhu r<RT>, <OFFSET>(r<BASE>)"
1806 *mipsI,mipsII,mipsIII,mipsIV:
1808 // start-sanitize-vr4320
1810 // end-sanitize-vr4320
1811 // start-sanitize-vr5400
1813 // end-sanitize-vr5400
1814 // start-sanitize-r5900
1816 // end-sanitize-r5900
1818 // start-sanitize-tx19
1820 // end-sanitize-tx19
1822 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1826 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1827 "ll r<RT>, <OFFSET>(r<BASE>)"
1832 // start-sanitize-vr4320
1834 // end-sanitize-vr4320
1835 // start-sanitize-vr5400
1837 // end-sanitize-vr5400
1838 // start-sanitize-r5900
1840 // end-sanitize-r5900
1841 // start-sanitize-tx19
1843 // end-sanitize-tx19
1845 unsigned32 instruction = instruction_0;
1846 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1847 int destreg = ((instruction >> 16) & 0x0000001F);
1848 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1850 address_word vaddr = ((unsigned64)op1 + offset);
1853 if ((vaddr & 3) != 0)
1854 SignalExceptionAddressLoad();
1857 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1859 unsigned64 memval = 0;
1860 unsigned64 memval1 = 0;
1861 unsigned64 mask = 0x7;
1862 unsigned int shift = 2;
1863 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1864 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1866 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1867 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1868 byte = ((vaddr & mask) ^ (bigend << shift));
1869 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1877 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1878 "lld r<RT>, <OFFSET>(r<BASE>)"
1882 // start-sanitize-vr4320
1884 // end-sanitize-vr4320
1885 // start-sanitize-vr5400
1887 // end-sanitize-vr5400
1888 // start-sanitize-r5900
1890 // end-sanitize-r5900
1891 // start-sanitize-tx19
1893 // end-sanitize-tx19
1895 unsigned32 instruction = instruction_0;
1896 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1897 int destreg = ((instruction >> 16) & 0x0000001F);
1898 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1900 address_word vaddr = ((unsigned64)op1 + offset);
1903 if ((vaddr & 7) != 0)
1904 SignalExceptionAddressLoad();
1907 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1909 unsigned64 memval = 0;
1910 unsigned64 memval1 = 0;
1911 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1912 GPR[destreg] = memval;
1920 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1921 "lui r<RT>, <IMMEDIATE>"
1922 *mipsI,mipsII,mipsIII,mipsIV:
1924 // start-sanitize-vr4320
1926 // end-sanitize-vr4320
1927 // start-sanitize-vr5400
1929 // end-sanitize-vr5400
1930 // start-sanitize-r5900
1932 // end-sanitize-r5900
1934 // start-sanitize-tx19
1936 // end-sanitize-tx19
1938 TRACE_ALU_INPUT1 (IMMEDIATE);
1939 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1940 TRACE_ALU_RESULT (GPR[RT]);
1944 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1945 "lw r<RT>, <OFFSET>(r<BASE>)"
1946 *mipsI,mipsII,mipsIII,mipsIV:
1948 // start-sanitize-vr4320
1950 // end-sanitize-vr4320
1951 // start-sanitize-vr5400
1953 // end-sanitize-vr5400
1954 // start-sanitize-r5900
1956 // end-sanitize-r5900
1958 // start-sanitize-tx19
1960 // end-sanitize-tx19
1962 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1966 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1967 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1968 *mipsI,mipsII,mipsIII,mipsIV:
1970 // start-sanitize-vr4320
1972 // end-sanitize-vr4320
1973 // start-sanitize-vr5400
1975 // end-sanitize-vr5400
1976 // start-sanitize-r5900
1978 // end-sanitize-r5900
1980 // start-sanitize-tx19
1982 // end-sanitize-tx19
1984 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1988 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1990 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1991 address_word reverseendian = (ReverseEndian ? -1 : 0);
1992 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1999 vaddr = base + offset;
2000 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2001 paddr = (paddr ^ (reverseendian & mask));
2002 if (BigEndianMem == 0)
2003 paddr = paddr & ~access;
2004 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2005 LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
2006 /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
2007 (long) vaddr, byte, (long) paddr, (long) memval); */
2008 if ((byte & ~access) == 0)
2010 int bits = 8 * (access - byte);
2011 unsigned_word screen = LSMASK (bits - 1, 0);
2013 rt |= ((memval << bits) & ~screen);
2017 unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
2019 rt |= ((memval >> (8 * (mask - byte))) & ~screen);
2025 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2026 "lwl r<RT>, <OFFSET>(r<BASE>)"
2027 *mipsI,mipsII,mipsIII,mipsIV:
2029 // start-sanitize-vr4320
2031 // end-sanitize-vr4320
2032 // start-sanitize-vr5400
2034 // end-sanitize-vr5400
2035 // start-sanitize-r5900
2037 // end-sanitize-r5900
2039 // start-sanitize-tx19
2041 // end-sanitize-tx19
2043 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2047 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2049 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2050 address_word reverseendian = (ReverseEndian ? -1 : 0);
2051 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2058 vaddr = base + offset;
2059 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2060 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2061 paddr = (paddr ^ (reverseendian & mask));
2062 if (BigEndianMem != 0)
2063 paddr = paddr & ~access;
2064 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2065 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2066 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2067 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2068 (long) paddr, byte, (long) paddr, (long) memval); */
2070 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2072 rt |= (memval >> (8 * byte)) & screen;
2078 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2079 "lwr r<RT>, <OFFSET>(r<BASE>)"
2080 *mipsI,mipsII,mipsIII,mipsIV:
2082 // start-sanitize-vr4320
2084 // end-sanitize-vr4320
2085 // start-sanitize-vr5400
2087 // end-sanitize-vr5400
2088 // start-sanitize-r5900
2090 // end-sanitize-r5900
2092 // start-sanitize-tx19
2094 // end-sanitize-tx19
2096 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2100 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2101 "lwu r<RT>, <OFFSET>(r<BASE>)"
2105 // start-sanitize-vr4320
2107 // end-sanitize-vr4320
2108 // start-sanitize-vr5400
2110 // end-sanitize-vr5400
2111 // start-sanitize-r5900
2113 // end-sanitize-r5900
2114 // start-sanitize-tx19
2116 // end-sanitize-tx19
2118 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2122 :function:::void:do_mfhi:int rd
2124 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2125 TRACE_ALU_INPUT1 (HI);
2127 TRACE_ALU_RESULT (GPR[rd]);
2130 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2132 *mipsI,mipsII,mipsIII,mipsIV:
2134 // start-sanitize-vr4320
2136 // end-sanitize-vr4320
2137 // start-sanitize-vr5400
2139 // end-sanitize-vr5400
2140 // start-sanitize-r5900
2142 // end-sanitize-r5900
2144 // start-sanitize-tx19
2146 // end-sanitize-tx19
2153 :function:::void:do_mflo:int rd
2155 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2156 TRACE_ALU_INPUT1 (LO);
2158 TRACE_ALU_RESULT (GPR[rd]);
2161 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2163 *mipsI,mipsII,mipsIII,mipsIV:
2165 // start-sanitize-vr4320
2167 // end-sanitize-vr4320
2168 // start-sanitize-vr5400
2170 // end-sanitize-vr5400
2171 // start-sanitize-r5900
2173 // end-sanitize-r5900
2175 // start-sanitize-tx19
2177 // end-sanitize-tx19
2184 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2185 "movn r<RD>, r<RS>, r<RT>"
2188 // start-sanitize-vr4320
2190 // end-sanitize-vr4320
2191 // start-sanitize-vr5400
2193 // end-sanitize-vr5400
2194 // start-sanitize-r5900
2196 // end-sanitize-r5900
2204 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2205 "movz r<RD>, r<RS>, r<RT>"
2208 // start-sanitize-vr4320
2210 // end-sanitize-vr4320
2211 // start-sanitize-vr5400
2213 // end-sanitize-vr5400
2214 // start-sanitize-r5900
2216 // end-sanitize-r5900
2224 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2226 *mipsI,mipsII,mipsIII,mipsIV:
2228 // start-sanitize-vr4320
2230 // end-sanitize-vr4320
2231 // start-sanitize-vr5400
2233 // end-sanitize-vr5400
2234 // start-sanitize-r5900
2236 // end-sanitize-r5900
2238 // start-sanitize-tx19
2240 // end-sanitize-tx19
2242 check_mt_hilo (SD_, HIHISTORY);
2248 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2250 *mipsI,mipsII,mipsIII,mipsIV:
2252 // start-sanitize-vr4320
2254 // end-sanitize-vr4320
2255 // start-sanitize-vr5400
2257 // end-sanitize-vr5400
2258 // start-sanitize-r5900
2260 // end-sanitize-r5900
2262 // start-sanitize-tx19
2264 // end-sanitize-tx19
2266 check_mt_hilo (SD_, LOHISTORY);
2272 :function:::void:do_mult:int rs, int rt, int rd
2275 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
2276 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2277 prod = (((signed64)(signed32) GPR[rs])
2278 * ((signed64)(signed32) GPR[rt]));
2279 LO = EXTEND32 (VL4_8 (prod));
2280 HI = EXTEND32 (VH4_8 (prod));
2283 TRACE_ALU_RESULT2 (HI, LO);
2286 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2288 *mipsI,mipsII,mipsIII,mipsIV:
2289 // start-sanitize-vr4320
2291 // end-sanitize-vr4320
2293 do_mult (SD_, RS, RT, 0);
2297 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2298 "mult r<RD>, r<RS>, r<RT>"
2300 // start-sanitize-vr5400
2302 // end-sanitize-vr5400
2303 // start-sanitize-r5900
2305 // end-sanitize-r5900
2307 // start-sanitize-tx19
2309 // end-sanitize-tx19
2311 do_mult (SD_, RS, RT, RD);
2315 :function:::void:do_multu:int rs, int rt, int rd
2318 check_op_hilo (SD_, HIHISTORY, LOHISTORY);
2319 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2320 prod = (((unsigned64)(unsigned32) GPR[rs])
2321 * ((unsigned64)(unsigned32) GPR[rt]));
2322 LO = EXTEND32 (VL4_8 (prod));
2323 HI = EXTEND32 (VH4_8 (prod));
2326 TRACE_ALU_RESULT2 (HI, LO);
2329 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2330 "multu r<RS>, r<RT>"
2331 *mipsI,mipsII,mipsIII,mipsIV:
2332 // start-sanitize-vr4320
2334 // end-sanitize-vr4320
2336 do_multu (SD_, RS, RT, 0);
2339 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2340 "multu r<RD>, r<RS>, r<RT>"
2342 // start-sanitize-vr5400
2344 // end-sanitize-vr5400
2345 // start-sanitize-r5900
2347 // end-sanitize-r5900
2349 // start-sanitize-tx19
2351 // end-sanitize-tx19
2353 do_multu (SD_, RS, RT, 0);
2357 :function:::void:do_nor:int rs, int rt, int rd
2359 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2360 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2361 TRACE_ALU_RESULT (GPR[rd]);
2364 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2365 "nor r<RD>, r<RS>, r<RT>"
2366 *mipsI,mipsII,mipsIII,mipsIV:
2368 // start-sanitize-vr4320
2370 // end-sanitize-vr4320
2371 // start-sanitize-vr5400
2373 // end-sanitize-vr5400
2374 // start-sanitize-r5900
2376 // end-sanitize-r5900
2378 // start-sanitize-tx19
2380 // end-sanitize-tx19
2382 do_nor (SD_, RS, RT, RD);
2386 :function:::void:do_or:int rs, int rt, int rd
2388 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2389 GPR[rd] = (GPR[rs] | GPR[rt]);
2390 TRACE_ALU_RESULT (GPR[rd]);
2393 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2394 "or r<RD>, r<RS>, r<RT>"
2395 *mipsI,mipsII,mipsIII,mipsIV:
2397 // start-sanitize-vr4320
2399 // end-sanitize-vr4320
2400 // start-sanitize-vr5400
2402 // end-sanitize-vr5400
2403 // start-sanitize-r5900
2405 // end-sanitize-r5900
2407 // start-sanitize-tx19
2409 // end-sanitize-tx19
2411 do_or (SD_, RS, RT, RD);
2416 :function:::void:do_ori:int rs, int rt, unsigned immediate
2418 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2419 GPR[rt] = (GPR[rs] | immediate);
2420 TRACE_ALU_RESULT (GPR[rt]);
2423 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2424 "ori r<RT>, r<RS>, <IMMEDIATE>"
2425 *mipsI,mipsII,mipsIII,mipsIV:
2427 // start-sanitize-vr4320
2429 // end-sanitize-vr4320
2430 // start-sanitize-vr5400
2432 // end-sanitize-vr5400
2433 // start-sanitize-r5900
2435 // end-sanitize-r5900
2437 // start-sanitize-tx19
2439 // end-sanitize-tx19
2441 do_ori (SD_, RS, RT, IMMEDIATE);
2445 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2448 // start-sanitize-vr4320
2450 // end-sanitize-vr4320
2451 // start-sanitize-vr5400
2453 // end-sanitize-vr5400
2454 // start-sanitize-r5900
2456 // end-sanitize-r5900
2458 unsigned32 instruction = instruction_0;
2459 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2460 int hint = ((instruction >> 16) & 0x0000001F);
2461 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2463 address_word vaddr = ((unsigned64)op1 + offset);
2467 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2468 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2473 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2475 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2476 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2477 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2484 vaddr = base + offset;
2485 if ((vaddr & access) != 0)
2486 SignalExceptionAddressStore ();
2487 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2488 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2489 byte = ((vaddr & mask) ^ bigendiancpu);
2490 memval = (word << (8 * byte));
2491 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2495 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2496 "sb r<RT>, <OFFSET>(r<BASE>)"
2497 *mipsI,mipsII,mipsIII,mipsIV:
2499 // start-sanitize-vr4320
2501 // end-sanitize-vr4320
2502 // start-sanitize-vr5400
2504 // end-sanitize-vr5400
2505 // start-sanitize-r5900
2507 // end-sanitize-r5900
2509 // start-sanitize-tx19
2511 // end-sanitize-tx19
2513 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2517 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2518 "sc r<RT>, <OFFSET>(r<BASE>)"
2523 // start-sanitize-vr4320
2525 // end-sanitize-vr4320
2526 // start-sanitize-vr5400
2528 // end-sanitize-vr5400
2529 // start-sanitize-r5900
2531 // end-sanitize-r5900
2532 // start-sanitize-tx19
2534 // end-sanitize-tx19
2536 unsigned32 instruction = instruction_0;
2537 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2538 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2539 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2541 address_word vaddr = ((unsigned64)op1 + offset);
2544 if ((vaddr & 3) != 0)
2545 SignalExceptionAddressStore();
2548 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2550 unsigned64 memval = 0;
2551 unsigned64 memval1 = 0;
2552 unsigned64 mask = 0x7;
2554 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2555 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2556 memval = ((unsigned64) op2 << (8 * byte));
2559 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2561 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2568 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2569 "scd r<RT>, <OFFSET>(r<BASE>)"
2573 // start-sanitize-vr4320
2575 // end-sanitize-vr4320
2576 // start-sanitize-vr5400
2578 // end-sanitize-vr5400
2579 // start-sanitize-r5900
2581 // end-sanitize-r5900
2582 // start-sanitize-tx19
2584 // end-sanitize-tx19
2586 unsigned32 instruction = instruction_0;
2587 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2588 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2589 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2591 address_word vaddr = ((unsigned64)op1 + offset);
2594 if ((vaddr & 7) != 0)
2595 SignalExceptionAddressStore();
2598 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2600 unsigned64 memval = 0;
2601 unsigned64 memval1 = 0;
2605 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2607 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2614 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2615 "sd r<RT>, <OFFSET>(r<BASE>)"
2619 // start-sanitize-vr4320
2621 // end-sanitize-vr4320
2622 // start-sanitize-vr5400
2624 // end-sanitize-vr5400
2625 // start-sanitize-r5900
2627 // end-sanitize-r5900
2628 // start-sanitize-tx19
2630 // end-sanitize-tx19
2632 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2636 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2637 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2642 // start-sanitize-vr4320
2644 // end-sanitize-vr4320
2645 // start-sanitize-vr5400
2647 // end-sanitize-vr5400
2648 // start-sanitize-r5900
2650 // end-sanitize-r5900
2651 // start-sanitize-tx19
2653 // end-sanitize-tx19
2655 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2659 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2660 "sdl r<RT>, <OFFSET>(r<BASE>)"
2664 // start-sanitize-vr4320
2666 // end-sanitize-vr4320
2667 // start-sanitize-vr5400
2669 // end-sanitize-vr5400
2670 // start-sanitize-r5900
2672 // end-sanitize-r5900
2673 // start-sanitize-tx19
2675 // end-sanitize-tx19
2677 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2681 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2682 "sdr r<RT>, <OFFSET>(r<BASE>)"
2686 // start-sanitize-vr4320
2688 // end-sanitize-vr4320
2689 // start-sanitize-vr5400
2691 // end-sanitize-vr5400
2692 // start-sanitize-r5900
2694 // end-sanitize-r5900
2695 // start-sanitize-tx19
2697 // end-sanitize-tx19
2699 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2703 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2704 "sh r<RT>, <OFFSET>(r<BASE>)"
2705 *mipsI,mipsII,mipsIII,mipsIV:
2707 // start-sanitize-vr4320
2709 // end-sanitize-vr4320
2710 // start-sanitize-vr5400
2712 // end-sanitize-vr5400
2713 // start-sanitize-r5900
2715 // end-sanitize-r5900
2717 // start-sanitize-tx19
2719 // end-sanitize-tx19
2721 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2725 :function:::void:do_sll:int rt, int rd, int shift
2727 unsigned32 temp = (GPR[rt] << shift);
2728 TRACE_ALU_INPUT2 (GPR[rt], shift);
2729 GPR[rd] = EXTEND32 (temp);
2730 TRACE_ALU_RESULT (GPR[rd]);
2733 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2734 "sll r<RD>, r<RT>, <SHIFT>"
2735 *mipsI,mipsII,mipsIII,mipsIV:
2737 // start-sanitize-vr4320
2739 // end-sanitize-vr4320
2740 // start-sanitize-vr5400
2742 // end-sanitize-vr5400
2743 // start-sanitize-r5900
2745 // end-sanitize-r5900
2747 // start-sanitize-tx19
2749 // end-sanitize-tx19
2751 do_sll (SD_, RT, RD, SHIFT);
2755 :function:::void:do_sllv:int rs, int rt, int rd
2757 int s = MASKED (GPR[rs], 4, 0);
2758 unsigned32 temp = (GPR[rt] << s);
2759 TRACE_ALU_INPUT2 (GPR[rt], s);
2760 GPR[rd] = EXTEND32 (temp);
2761 TRACE_ALU_RESULT (GPR[rd]);
2764 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2765 "sllv r<RD>, r<RT>, r<RS>"
2766 *mipsI,mipsII,mipsIII,mipsIV:
2768 // start-sanitize-vr4320
2770 // end-sanitize-vr4320
2771 // start-sanitize-vr5400
2773 // end-sanitize-vr5400
2774 // start-sanitize-r5900
2776 // end-sanitize-r5900
2778 // start-sanitize-tx19
2780 // end-sanitize-tx19
2782 do_sllv (SD_, RS, RT, RD);
2786 :function:::void:do_slt:int rs, int rt, int rd
2788 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2789 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2790 TRACE_ALU_RESULT (GPR[rd]);
2793 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2794 "slt r<RD>, r<RS>, r<RT>"
2795 *mipsI,mipsII,mipsIII,mipsIV:
2797 // start-sanitize-vr4320
2799 // end-sanitize-vr4320
2800 // start-sanitize-vr5400
2802 // end-sanitize-vr5400
2803 // start-sanitize-r5900
2805 // end-sanitize-r5900
2807 // start-sanitize-tx19
2809 // end-sanitize-tx19
2811 do_slt (SD_, RS, RT, RD);
2815 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2817 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2818 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2819 TRACE_ALU_RESULT (GPR[rt]);
2822 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2823 "slti r<RT>, r<RS>, <IMMEDIATE>"
2824 *mipsI,mipsII,mipsIII,mipsIV:
2826 // start-sanitize-vr4320
2828 // end-sanitize-vr4320
2829 // start-sanitize-vr5400
2831 // end-sanitize-vr5400
2832 // start-sanitize-r5900
2834 // end-sanitize-r5900
2836 // start-sanitize-tx19
2838 // end-sanitize-tx19
2840 do_slti (SD_, RS, RT, IMMEDIATE);
2844 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2846 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2847 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2848 TRACE_ALU_RESULT (GPR[rt]);
2851 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2852 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2853 *mipsI,mipsII,mipsIII,mipsIV:
2855 // start-sanitize-vr4320
2857 // end-sanitize-vr4320
2858 // start-sanitize-vr5400
2860 // end-sanitize-vr5400
2861 // start-sanitize-r5900
2863 // end-sanitize-r5900
2865 // start-sanitize-tx19
2867 // end-sanitize-tx19
2869 do_sltiu (SD_, RS, RT, IMMEDIATE);
2874 :function:::void:do_sltu:int rs, int rt, int rd
2876 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2877 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2878 TRACE_ALU_RESULT (GPR[rd]);
2881 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2882 "sltu r<RD>, r<RS>, r<RT>"
2883 *mipsI,mipsII,mipsIII,mipsIV:
2885 // start-sanitize-vr4320
2887 // end-sanitize-vr4320
2888 // start-sanitize-vr5400
2890 // end-sanitize-vr5400
2891 // start-sanitize-r5900
2893 // end-sanitize-r5900
2895 // start-sanitize-tx19
2897 // end-sanitize-tx19
2899 do_sltu (SD_, RS, RT, RD);
2903 :function:::void:do_sra:int rt, int rd, int shift
2905 signed32 temp = (signed32) GPR[rt] >> shift;
2906 TRACE_ALU_INPUT2 (GPR[rt], shift);
2907 GPR[rd] = EXTEND32 (temp);
2908 TRACE_ALU_RESULT (GPR[rd]);
2911 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2912 "sra r<RD>, r<RT>, <SHIFT>"
2913 *mipsI,mipsII,mipsIII,mipsIV:
2915 // start-sanitize-vr4320
2917 // end-sanitize-vr4320
2918 // start-sanitize-vr5400
2920 // end-sanitize-vr5400
2921 // start-sanitize-r5900
2923 // end-sanitize-r5900
2925 // start-sanitize-tx19
2927 // end-sanitize-tx19
2929 do_sra (SD_, RT, RD, SHIFT);
2934 :function:::void:do_srav:int rs, int rt, int rd
2936 int s = MASKED (GPR[rs], 4, 0);
2937 signed32 temp = (signed32) GPR[rt] >> s;
2938 TRACE_ALU_INPUT2 (GPR[rt], s);
2939 GPR[rd] = EXTEND32 (temp);
2940 TRACE_ALU_RESULT (GPR[rd]);
2943 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2944 "srav r<RD>, r<RT>, r<RS>"
2945 *mipsI,mipsII,mipsIII,mipsIV:
2947 // start-sanitize-vr4320
2949 // end-sanitize-vr4320
2950 // start-sanitize-vr5400
2952 // end-sanitize-vr5400
2953 // start-sanitize-r5900
2955 // end-sanitize-r5900
2957 // start-sanitize-tx19
2959 // end-sanitize-tx19
2961 do_srav (SD_, RS, RT, RD);
2966 :function:::void:do_srl:int rt, int rd, int shift
2968 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2969 TRACE_ALU_INPUT2 (GPR[rt], shift);
2970 GPR[rd] = EXTEND32 (temp);
2971 TRACE_ALU_RESULT (GPR[rd]);
2974 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2975 "srl r<RD>, r<RT>, <SHIFT>"
2976 *mipsI,mipsII,mipsIII,mipsIV:
2978 // start-sanitize-vr4320
2980 // end-sanitize-vr4320
2981 // start-sanitize-vr5400
2983 // end-sanitize-vr5400
2984 // start-sanitize-r5900
2986 // end-sanitize-r5900
2988 // start-sanitize-tx19
2990 // end-sanitize-tx19
2992 do_srl (SD_, RT, RD, SHIFT);
2996 :function:::void:do_srlv:int rs, int rt, int rd
2998 int s = MASKED (GPR[rs], 4, 0);
2999 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3000 TRACE_ALU_INPUT2 (GPR[rt], s);
3001 GPR[rd] = EXTEND32 (temp);
3002 TRACE_ALU_RESULT (GPR[rd]);
3005 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3006 "srlv r<RD>, r<RT>, r<RS>"
3007 *mipsI,mipsII,mipsIII,mipsIV:
3009 // start-sanitize-vr4320
3011 // end-sanitize-vr4320
3012 // start-sanitize-vr5400
3014 // end-sanitize-vr5400
3015 // start-sanitize-r5900
3017 // end-sanitize-r5900
3019 // start-sanitize-tx19
3021 // end-sanitize-tx19
3023 do_srlv (SD_, RS, RT, RD);
3027 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3028 "sub r<RD>, r<RS>, r<RT>"
3029 *mipsI,mipsII,mipsIII,mipsIV:
3031 // start-sanitize-vr4320
3033 // end-sanitize-vr4320
3034 // start-sanitize-vr5400
3036 // end-sanitize-vr5400
3037 // start-sanitize-r5900
3039 // end-sanitize-r5900
3041 // start-sanitize-tx19
3043 // end-sanitize-tx19
3045 ALU32_BEGIN (GPR[RS]);
3046 ALU32_SUB (GPR[RT]);
3047 ALU32_END (GPR[RD]);
3051 :function:::void:do_subu:int rs, int rt, int rd
3053 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3054 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3055 TRACE_ALU_RESULT (GPR[rd]);
3058 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3059 "subu r<RD>, r<RS>, r<RT>"
3060 *mipsI,mipsII,mipsIII,mipsIV:
3062 // start-sanitize-vr4320
3064 // end-sanitize-vr4320
3065 // start-sanitize-vr5400
3067 // end-sanitize-vr5400
3068 // start-sanitize-r5900
3070 // end-sanitize-r5900
3072 // start-sanitize-tx19
3074 // end-sanitize-tx19
3076 do_subu (SD_, RS, RT, RD);
3080 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3081 "sw r<RT>, <OFFSET>(r<BASE>)"
3082 *mipsI,mipsII,mipsIII,mipsIV:
3083 // start-sanitize-tx19
3085 // end-sanitize-tx19
3087 // start-sanitize-vr4320
3089 // end-sanitize-vr4320
3091 // start-sanitize-vr5400
3093 // end-sanitize-vr5400
3094 // start-sanitize-r5900
3096 // end-sanitize-r5900
3098 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3102 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3103 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3104 *mipsI,mipsII,mipsIII,mipsIV:
3106 // start-sanitize-vr4320
3108 // end-sanitize-vr4320
3109 // start-sanitize-vr5400
3111 // end-sanitize-vr5400
3113 // start-sanitize-tx19
3115 // end-sanitize-tx19
3117 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3122 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3124 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3125 address_word reverseendian = (ReverseEndian ? -1 : 0);
3126 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3133 vaddr = base + offset;
3134 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3135 paddr = (paddr ^ (reverseendian & mask));
3136 if (BigEndianMem == 0)
3137 paddr = paddr & ~access;
3138 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3139 if ((byte & ~access) == 0)
3140 memval = (rt >> (8 * (access - byte)));
3142 memval = (rt << (8 * (mask - byte)));
3143 StoreMemory (uncached, byte & access, memval, NULL, paddr, vaddr, isREAL);
3147 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3148 "swl r<RT>, <OFFSET>(r<BASE>)"
3149 *mipsI,mipsII,mipsIII,mipsIV:
3151 // start-sanitize-vr4320
3153 // end-sanitize-vr4320
3154 // start-sanitize-vr5400
3156 // end-sanitize-vr5400
3157 // start-sanitize-r5900
3159 // end-sanitize-r5900
3161 // start-sanitize-tx19
3163 // end-sanitize-tx19
3165 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3169 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3171 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3172 address_word reverseendian = (ReverseEndian ? -1 : 0);
3173 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3180 vaddr = base + offset;
3181 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3182 paddr = (paddr ^ (reverseendian & mask));
3183 if (BigEndianMem != 0)
3185 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3186 memval = (rt << (byte * 8));
3187 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3190 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3191 "swr r<RT>, <OFFSET>(r<BASE>)"
3192 *mipsI,mipsII,mipsIII,mipsIV:
3194 // start-sanitize-vr4320
3196 // end-sanitize-vr4320
3197 // start-sanitize-vr5400
3199 // end-sanitize-vr5400
3200 // start-sanitize-r5900
3202 // end-sanitize-r5900
3204 // start-sanitize-tx19
3206 // end-sanitize-tx19
3208 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3212 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3219 // start-sanitize-vr4320
3221 // end-sanitize-vr4320
3222 // start-sanitize-vr5400
3224 // end-sanitize-vr5400
3225 // start-sanitize-r5900
3227 // end-sanitize-r5900
3229 // start-sanitize-tx19
3231 // end-sanitize-tx19
3233 SyncOperation (STYPE);
3237 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3239 *mipsI,mipsII,mipsIII,mipsIV:
3241 // start-sanitize-vr4320
3243 // end-sanitize-vr4320
3244 // start-sanitize-vr5400
3246 // end-sanitize-vr5400
3247 // start-sanitize-r5900
3249 // end-sanitize-r5900
3251 // start-sanitize-tx19
3253 // end-sanitize-tx19
3255 SignalException(SystemCall, instruction_0);
3259 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3265 // start-sanitize-vr4320
3267 // end-sanitize-vr4320
3268 // start-sanitize-vr5400
3270 // end-sanitize-vr5400
3271 // start-sanitize-r5900
3273 // end-sanitize-r5900
3274 // start-sanitize-tx19
3276 // end-sanitize-tx19
3278 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3279 SignalException(Trap, instruction_0);
3283 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3284 "teqi r<RS>, <IMMEDIATE>"
3289 // start-sanitize-vr4320
3291 // end-sanitize-vr4320
3292 // start-sanitize-vr5400
3294 // end-sanitize-vr5400
3295 // start-sanitize-r5900
3297 // end-sanitize-r5900
3298 // start-sanitize-tx19
3300 // end-sanitize-tx19
3302 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3303 SignalException(Trap, instruction_0);
3307 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3313 // start-sanitize-vr4320
3315 // end-sanitize-vr4320
3316 // start-sanitize-vr5400
3318 // end-sanitize-vr5400
3319 // start-sanitize-r5900
3321 // end-sanitize-r5900
3322 // start-sanitize-tx19
3324 // end-sanitize-tx19
3326 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3327 SignalException(Trap, instruction_0);
3331 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3332 "tgei r<RS>, <IMMEDIATE>"
3337 // start-sanitize-vr4320
3339 // end-sanitize-vr4320
3340 // start-sanitize-vr5400
3342 // end-sanitize-vr5400
3343 // start-sanitize-r5900
3345 // end-sanitize-r5900
3346 // start-sanitize-tx19
3348 // end-sanitize-tx19
3350 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3351 SignalException(Trap, instruction_0);
3355 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3356 "tgeiu r<RS>, <IMMEDIATE>"
3361 // start-sanitize-vr4320
3363 // end-sanitize-vr4320
3364 // start-sanitize-vr5400
3366 // end-sanitize-vr5400
3367 // start-sanitize-r5900
3369 // end-sanitize-r5900
3370 // start-sanitize-tx19
3372 // end-sanitize-tx19
3374 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3375 SignalException(Trap, instruction_0);
3379 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3385 // start-sanitize-vr4320
3387 // end-sanitize-vr4320
3388 // start-sanitize-vr5400
3390 // end-sanitize-vr5400
3391 // start-sanitize-r5900
3393 // end-sanitize-r5900
3394 // start-sanitize-tx19
3396 // end-sanitize-tx19
3398 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3399 SignalException(Trap, instruction_0);
3403 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3409 // start-sanitize-vr4320
3411 // end-sanitize-vr4320
3412 // start-sanitize-vr5400
3414 // end-sanitize-vr5400
3415 // start-sanitize-r5900
3417 // end-sanitize-r5900
3418 // start-sanitize-tx19
3420 // end-sanitize-tx19
3422 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3423 SignalException(Trap, instruction_0);
3427 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3428 "tlti r<RS>, <IMMEDIATE>"
3433 // start-sanitize-vr4320
3435 // end-sanitize-vr4320
3436 // start-sanitize-vr5400
3438 // end-sanitize-vr5400
3439 // start-sanitize-r5900
3441 // end-sanitize-r5900
3442 // start-sanitize-tx19
3444 // end-sanitize-tx19
3446 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3447 SignalException(Trap, instruction_0);
3451 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3452 "tltiu r<RS>, <IMMEDIATE>"
3457 // start-sanitize-vr4320
3459 // end-sanitize-vr4320
3460 // start-sanitize-vr5400
3462 // end-sanitize-vr5400
3463 // start-sanitize-r5900
3465 // end-sanitize-r5900
3466 // start-sanitize-tx19
3468 // end-sanitize-tx19
3470 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3471 SignalException(Trap, instruction_0);
3475 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3481 // start-sanitize-vr4320
3483 // end-sanitize-vr4320
3484 // start-sanitize-vr5400
3486 // end-sanitize-vr5400
3487 // start-sanitize-r5900
3489 // end-sanitize-r5900
3490 // start-sanitize-tx19
3492 // end-sanitize-tx19
3494 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3495 SignalException(Trap, instruction_0);
3499 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3505 // start-sanitize-vr4320
3507 // end-sanitize-vr4320
3508 // start-sanitize-vr5400
3510 // end-sanitize-vr5400
3511 // start-sanitize-r5900
3513 // end-sanitize-r5900
3514 // start-sanitize-tx19
3516 // end-sanitize-tx19
3518 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3519 SignalException(Trap, instruction_0);
3523 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3524 "tne r<RS>, <IMMEDIATE>"
3529 // start-sanitize-vr4320
3531 // end-sanitize-vr4320
3532 // start-sanitize-vr5400
3534 // end-sanitize-vr5400
3535 // start-sanitize-r5900
3537 // end-sanitize-r5900
3538 // start-sanitize-tx19
3540 // end-sanitize-tx19
3542 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3543 SignalException(Trap, instruction_0);
3547 :function:::void:do_xor:int rs, int rt, int rd
3549 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3550 GPR[rd] = GPR[rs] ^ GPR[rt];
3551 TRACE_ALU_RESULT (GPR[rd]);
3554 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3555 "xor r<RD>, r<RS>, r<RT>"
3556 *mipsI,mipsII,mipsIII,mipsIV:
3558 // start-sanitize-vr4320
3560 // end-sanitize-vr4320
3561 // start-sanitize-vr5400
3563 // end-sanitize-vr5400
3564 // start-sanitize-r5900
3566 // end-sanitize-r5900
3568 // start-sanitize-tx19
3570 // end-sanitize-tx19
3572 do_xor (SD_, RS, RT, RD);
3576 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3578 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3579 GPR[rt] = GPR[rs] ^ immediate;
3580 TRACE_ALU_RESULT (GPR[rt]);
3583 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3584 "xori r<RT>, r<RS>, <IMMEDIATE>"
3585 *mipsI,mipsII,mipsIII,mipsIV:
3587 // start-sanitize-vr4320
3589 // end-sanitize-vr4320
3590 // start-sanitize-vr5400
3592 // end-sanitize-vr5400
3593 // start-sanitize-r5900
3595 // end-sanitize-r5900
3597 // start-sanitize-tx19
3599 // end-sanitize-tx19
3601 do_xori (SD_, RS, RT, IMMEDIATE);
3606 // MIPS Architecture:
3608 // FPU Instruction Set (COP1 & COP1X)
3616 case fmt_single: return "s";
3617 case fmt_double: return "d";
3618 case fmt_word: return "w";
3619 case fmt_long: return "l";
3620 default: return "?";
3630 default: return "?";
3650 :%s::::COND:int cond
3654 case 00: return "f";
3655 case 01: return "un";
3656 case 02: return "eq";
3657 case 03: return "ueq";
3658 case 04: return "olt";
3659 case 05: return "ult";
3660 case 06: return "ole";
3661 case 07: return "ule";
3662 case 010: return "sf";
3663 case 011: return "ngle";
3664 case 012: return "seq";
3665 case 013: return "ngl";
3666 case 014: return "lt";
3667 case 015: return "nge";
3668 case 016: return "le";
3669 case 017: return "ngt";
3670 default: return "?";
3675 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3676 "abs.%s<FMT> f<FD>, f<FS>"
3677 *mipsI,mipsII,mipsIII,mipsIV:
3679 // start-sanitize-vr4320
3681 // end-sanitize-vr4320
3682 // start-sanitize-vr5400
3684 // end-sanitize-vr5400
3686 // start-sanitize-tx19
3688 // end-sanitize-tx19
3690 unsigned32 instruction = instruction_0;
3691 int destreg = ((instruction >> 6) & 0x0000001F);
3692 int fs = ((instruction >> 11) & 0x0000001F);
3693 int format = ((instruction >> 21) & 0x00000007);
3695 if ((format != fmt_single) && (format != fmt_double))
3696 SignalException(ReservedInstruction,instruction);
3698 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3704 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3705 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3706 *mipsI,mipsII,mipsIII,mipsIV:
3708 // start-sanitize-vr4320
3710 // end-sanitize-vr4320
3711 // start-sanitize-vr5400
3713 // end-sanitize-vr5400
3715 // start-sanitize-tx19
3717 // end-sanitize-tx19
3719 unsigned32 instruction = instruction_0;
3720 int destreg = ((instruction >> 6) & 0x0000001F);
3721 int fs = ((instruction >> 11) & 0x0000001F);
3722 int ft = ((instruction >> 16) & 0x0000001F);
3723 int format = ((instruction >> 21) & 0x00000007);
3725 if ((format != fmt_single) && (format != fmt_double))
3726 SignalException(ReservedInstruction, instruction);
3728 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3739 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3740 "bc1%s<TF>%s<ND> <OFFSET>"
3741 *mipsI,mipsII,mipsIII:
3742 // start-sanitize-r5900
3744 // end-sanitize-r5900
3746 TRACE_BRANCH_INPUT (PREVCOC1());
3747 if (PREVCOC1() == TF)
3749 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3750 TRACE_BRANCH_RESULT (dest);
3755 TRACE_BRANCH_RESULT (0);
3756 NULLIFY_NEXT_INSTRUCTION ();
3760 TRACE_BRANCH_RESULT (NIA);
3764 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3765 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3766 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3769 // start-sanitize-vr4320
3771 // end-sanitize-vr4320
3772 // start-sanitize-vr5400
3774 // end-sanitize-vr5400
3776 // start-sanitize-tx19
3778 // end-sanitize-tx19
3780 if (GETFCC(CC) == TF)
3782 DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3786 NULLIFY_NEXT_INSTRUCTION ();
3796 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3798 if ((fmt != fmt_single) && (fmt != fmt_double))
3799 SignalException (ReservedInstruction, insn);
3806 unsigned64 ofs = ValueFPR (fs, fmt);
3807 unsigned64 oft = ValueFPR (ft, fmt);
3808 if (NaN (ofs, fmt) || NaN (oft, fmt))
3810 if (FCSR & FP_ENABLE (IO))
3812 FCSR |= FP_CAUSE (IO);
3813 SignalExceptionFPE ();
3821 less = Less (ofs, oft, fmt);
3822 equal = Equal (ofs, oft, fmt);
3825 condition = (((cond & (1 << 2)) && less)
3826 || ((cond & (1 << 1)) && equal)
3827 || ((cond & (1 << 0)) && unordered));
3828 SETFCC (cc, condition);
3832 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3833 *mipsI,mipsII,mipsIII:
3834 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3836 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3839 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3840 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3841 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3844 // start-sanitize-vr4320
3846 // end-sanitize-vr4320
3847 // start-sanitize-vr5400
3849 // end-sanitize-vr5400
3851 // start-sanitize-tx19
3853 // end-sanitize-tx19
3855 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3859 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3860 "ceil.l.%s<FMT> f<FD>, f<FS>"
3864 // start-sanitize-vr4320
3866 // end-sanitize-vr4320
3867 // start-sanitize-vr5400
3869 // end-sanitize-vr5400
3870 // start-sanitize-r5900
3872 // end-sanitize-r5900
3874 // start-sanitize-tx19
3876 // end-sanitize-tx19
3878 unsigned32 instruction = instruction_0;
3879 int destreg = ((instruction >> 6) & 0x0000001F);
3880 int fs = ((instruction >> 11) & 0x0000001F);
3881 int format = ((instruction >> 21) & 0x00000007);
3883 if ((format != fmt_single) && (format != fmt_double))
3884 SignalException(ReservedInstruction,instruction);
3886 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3891 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3896 // start-sanitize-vr4320
3898 // end-sanitize-vr4320
3899 // start-sanitize-vr5400
3901 // end-sanitize-vr5400
3902 // start-sanitize-r5900
3904 // end-sanitize-r5900
3906 // start-sanitize-tx19
3908 // end-sanitize-tx19
3910 unsigned32 instruction = instruction_0;
3911 int destreg = ((instruction >> 6) & 0x0000001F);
3912 int fs = ((instruction >> 11) & 0x0000001F);
3913 int format = ((instruction >> 21) & 0x00000007);
3915 if ((format != fmt_single) && (format != fmt_double))
3916 SignalException(ReservedInstruction,instruction);
3918 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3925 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3926 "c%s<X>c1 r<RT>, f<FS>"
3934 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3936 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
3938 PENDING_FILL(COCIDX,0); /* special case */
3941 { /* control from */
3943 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3945 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3949 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3950 "c%s<X>c1 r<RT>, f<FS>"
3953 // start-sanitize-vr4320
3955 // end-sanitize-vr4320
3956 // start-sanitize-vr5400
3958 // end-sanitize-vr5400
3960 // start-sanitize-tx19
3962 // end-sanitize-tx19
3967 TRACE_ALU_INPUT1 (GPR[RT]);
3970 FCR0 = VL4_8(GPR[RT]);
3971 TRACE_ALU_RESULT (FCR0);
3975 FCR31 = VL4_8(GPR[RT]);
3976 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3977 TRACE_ALU_RESULT (FCR31);
3981 TRACE_ALU_RESULT0 ();
3986 { /* control from */
3989 TRACE_ALU_INPUT1 (FCR0);
3990 GPR[RT] = SIGNEXTEND (FCR0, 32);
3994 TRACE_ALU_INPUT1 (FCR31);
3995 GPR[RT] = SIGNEXTEND (FCR31, 32);
3997 TRACE_ALU_RESULT (GPR[RT]);
4004 // FIXME: Does not correctly differentiate between mips*
4006 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4007 "cvt.d.%s<FMT> f<FD>, f<FS>"
4008 *mipsI,mipsII,mipsIII,mipsIV:
4010 // start-sanitize-vr4320
4012 // end-sanitize-vr4320
4013 // start-sanitize-vr5400
4015 // end-sanitize-vr5400
4017 // start-sanitize-tx19
4019 // end-sanitize-tx19
4021 unsigned32 instruction = instruction_0;
4022 int destreg = ((instruction >> 6) & 0x0000001F);
4023 int fs = ((instruction >> 11) & 0x0000001F);
4024 int format = ((instruction >> 21) & 0x00000007);
4026 if ((format == fmt_double) | 0)
4027 SignalException(ReservedInstruction,instruction);
4029 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4034 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4035 "cvt.l.%s<FMT> f<FD>, f<FS>"
4039 // start-sanitize-vr4320
4041 // end-sanitize-vr4320
4042 // start-sanitize-vr5400
4044 // end-sanitize-vr5400
4046 // start-sanitize-tx19
4048 // end-sanitize-tx19
4050 unsigned32 instruction = instruction_0;
4051 int destreg = ((instruction >> 6) & 0x0000001F);
4052 int fs = ((instruction >> 11) & 0x0000001F);
4053 int format = ((instruction >> 21) & 0x00000007);
4055 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4056 SignalException(ReservedInstruction,instruction);
4058 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4064 // FIXME: Does not correctly differentiate between mips*
4066 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4067 "cvt.s.%s<FMT> f<FD>, f<FS>"
4068 *mipsI,mipsII,mipsIII,mipsIV:
4070 // start-sanitize-vr4320
4072 // end-sanitize-vr4320
4073 // start-sanitize-vr5400
4075 // end-sanitize-vr5400
4077 // start-sanitize-tx19
4079 // end-sanitize-tx19
4081 unsigned32 instruction = instruction_0;
4082 int destreg = ((instruction >> 6) & 0x0000001F);
4083 int fs = ((instruction >> 11) & 0x0000001F);
4084 int format = ((instruction >> 21) & 0x00000007);
4086 if ((format == fmt_single) | 0)
4087 SignalException(ReservedInstruction,instruction);
4089 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4094 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4095 "cvt.w.%s<FMT> f<FD>, f<FS>"
4096 *mipsI,mipsII,mipsIII,mipsIV:
4098 // start-sanitize-vr4320
4100 // end-sanitize-vr4320
4101 // start-sanitize-vr5400
4103 // end-sanitize-vr5400
4105 // start-sanitize-tx19
4107 // end-sanitize-tx19
4109 unsigned32 instruction = instruction_0;
4110 int destreg = ((instruction >> 6) & 0x0000001F);
4111 int fs = ((instruction >> 11) & 0x0000001F);
4112 int format = ((instruction >> 21) & 0x00000007);
4114 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4115 SignalException(ReservedInstruction,instruction);
4117 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4122 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4123 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4124 *mipsI,mipsII,mipsIII,mipsIV:
4126 // start-sanitize-vr4320
4128 // end-sanitize-vr4320
4129 // start-sanitize-vr5400
4131 // end-sanitize-vr5400
4133 // start-sanitize-tx19
4135 // end-sanitize-tx19
4137 unsigned32 instruction = instruction_0;
4138 int destreg = ((instruction >> 6) & 0x0000001F);
4139 int fs = ((instruction >> 11) & 0x0000001F);
4140 int ft = ((instruction >> 16) & 0x0000001F);
4141 int format = ((instruction >> 21) & 0x00000007);
4143 if ((format != fmt_single) && (format != fmt_double))
4144 SignalException(ReservedInstruction,instruction);
4146 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4153 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4154 "dm%s<X>c1 r<RT>, f<FS>"
4159 if (SizeFGR() == 64)
4160 PENDING_FILL((FS + FGRIDX),GPR[RT]);
4161 else if ((FS & 0x1) == 0)
4163 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4164 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4169 if (SizeFGR() == 64)
4170 PENDING_FILL(RT,FGR[FS]);
4171 else if ((FS & 0x1) == 0)
4172 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4174 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4177 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4178 "dm%s<X>c1 r<RT>, f<FS>"
4181 // start-sanitize-vr4320
4183 // end-sanitize-vr4320
4184 // start-sanitize-vr5400
4186 // end-sanitize-vr5400
4187 // start-sanitize-r5900
4189 // end-sanitize-r5900
4191 // start-sanitize-tx19
4193 // end-sanitize-tx19
4197 if (SizeFGR() == 64)
4198 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4199 else if ((FS & 0x1) == 0)
4200 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4204 if (SizeFGR() == 64)
4206 else if ((FS & 0x1) == 0)
4207 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4209 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4214 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4215 "floor.l.%s<FMT> f<FD>, f<FS>"
4219 // start-sanitize-vr4320
4221 // end-sanitize-vr4320
4222 // start-sanitize-vr5400
4224 // end-sanitize-vr5400
4225 // start-sanitize-r5900
4227 // end-sanitize-r5900
4229 // start-sanitize-tx19
4231 // end-sanitize-tx19
4233 unsigned32 instruction = instruction_0;
4234 int destreg = ((instruction >> 6) & 0x0000001F);
4235 int fs = ((instruction >> 11) & 0x0000001F);
4236 int format = ((instruction >> 21) & 0x00000007);
4238 if ((format != fmt_single) && (format != fmt_double))
4239 SignalException(ReservedInstruction,instruction);
4241 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4246 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4247 "floor.w.%s<FMT> f<FD>, f<FS>"
4252 // start-sanitize-vr4320
4254 // end-sanitize-vr4320
4255 // start-sanitize-vr5400
4257 // end-sanitize-vr5400
4258 // start-sanitize-r5900
4260 // end-sanitize-r5900
4262 // start-sanitize-tx19
4264 // end-sanitize-tx19
4266 unsigned32 instruction = instruction_0;
4267 int destreg = ((instruction >> 6) & 0x0000001F);
4268 int fs = ((instruction >> 11) & 0x0000001F);
4269 int format = ((instruction >> 21) & 0x00000007);
4271 if ((format != fmt_single) && (format != fmt_double))
4272 SignalException(ReservedInstruction,instruction);
4274 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4279 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4280 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4285 // start-sanitize-vr4320
4287 // end-sanitize-vr4320
4288 // start-sanitize-vr5400
4290 // end-sanitize-vr5400
4292 // start-sanitize-tx19
4294 // end-sanitize-tx19
4296 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4300 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4301 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4304 // start-sanitize-vr4320
4306 // end-sanitize-vr4320
4307 // start-sanitize-vr5400
4309 // end-sanitize-vr5400
4311 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4316 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4317 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4318 *mipsI,mipsII,mipsIII,mipsIV:
4320 // start-sanitize-vr4320
4322 // end-sanitize-vr4320
4323 // start-sanitize-vr5400
4325 // end-sanitize-vr5400
4326 // start-sanitize-r5900
4328 // end-sanitize-r5900
4330 // start-sanitize-tx19
4332 // end-sanitize-tx19
4334 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4338 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4339 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4342 // start-sanitize-vr4320
4344 // end-sanitize-vr4320
4345 // start-sanitize-vr5400
4347 // end-sanitize-vr5400
4349 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4355 // FIXME: Not correct for mips*
4357 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4358 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4361 // start-sanitize-vr4320
4363 // end-sanitize-vr4320
4364 // start-sanitize-vr5400
4366 // end-sanitize-vr5400
4368 unsigned32 instruction = instruction_0;
4369 int destreg = ((instruction >> 6) & 0x0000001F);
4370 int fs = ((instruction >> 11) & 0x0000001F);
4371 int ft = ((instruction >> 16) & 0x0000001F);
4372 int fr = ((instruction >> 21) & 0x0000001F);
4374 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4379 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4380 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4383 // start-sanitize-vr4320
4385 // end-sanitize-vr4320
4386 // start-sanitize-vr5400
4388 // end-sanitize-vr5400
4390 unsigned32 instruction = instruction_0;
4391 int destreg = ((instruction >> 6) & 0x0000001F);
4392 int fs = ((instruction >> 11) & 0x0000001F);
4393 int ft = ((instruction >> 16) & 0x0000001F);
4394 int fr = ((instruction >> 21) & 0x0000001F);
4396 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4403 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4404 "m%s<X>c1 r<RT>, f<FS>"
4411 if (SizeFGR() == 64)
4412 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4414 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4417 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4419 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4420 "m%s<X>c1 r<RT>, f<FS>"
4423 // start-sanitize-vr4320
4425 // end-sanitize-vr4320
4426 // start-sanitize-vr5400
4428 // end-sanitize-vr5400
4430 // start-sanitize-tx19
4432 // end-sanitize-tx19
4436 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4438 GPR[RT] = SIGNEXTEND(FGR[FS],32);
4442 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4443 "mov.%s<FMT> f<FD>, f<FS>"
4444 *mipsI,mipsII,mipsIII,mipsIV:
4446 // start-sanitize-vr4320
4448 // end-sanitize-vr4320
4449 // start-sanitize-vr5400
4451 // end-sanitize-vr5400
4453 // start-sanitize-tx19
4455 // end-sanitize-tx19
4457 unsigned32 instruction = instruction_0;
4458 int destreg = ((instruction >> 6) & 0x0000001F);
4459 int fs = ((instruction >> 11) & 0x0000001F);
4460 int format = ((instruction >> 21) & 0x00000007);
4462 StoreFPR(destreg,format,ValueFPR(fs,format));
4468 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4469 "mov%s<TF> r<RD>, r<RS>, <CC>"
4472 // start-sanitize-vr4320
4474 // end-sanitize-vr4320
4475 // start-sanitize-vr5400
4477 // end-sanitize-vr5400
4478 // start-sanitize-r5900
4480 // end-sanitize-r5900
4482 if (GETFCC(CC) == TF)
4488 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4489 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4492 // start-sanitize-vr4320
4494 // end-sanitize-vr4320
4495 // start-sanitize-vr5400
4497 // end-sanitize-vr5400
4498 // start-sanitize-r5900
4500 // end-sanitize-r5900
4502 unsigned32 instruction = instruction_0;
4503 int format = ((instruction >> 21) & 0x00000007);
4505 if (GETFCC(CC) == TF)
4506 StoreFPR (FD, format, ValueFPR (FS, format));
4508 StoreFPR (FD, format, ValueFPR (FD, format));
4513 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4516 // start-sanitize-vr4320
4518 // end-sanitize-vr4320
4519 // start-sanitize-vr5400
4521 // end-sanitize-vr5400
4522 // start-sanitize-r5900
4524 // end-sanitize-r5900
4526 unsigned32 instruction = instruction_0;
4527 int destreg = ((instruction >> 6) & 0x0000001F);
4528 int fs = ((instruction >> 11) & 0x0000001F);
4529 int format = ((instruction >> 21) & 0x00000007);
4531 StoreFPR(destreg,format,ValueFPR(fs,format));
4539 // MOVT.fmt see MOVtf.fmt
4543 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4544 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4547 // start-sanitize-vr4320
4549 // end-sanitize-vr4320
4550 // start-sanitize-vr5400
4552 // end-sanitize-vr5400
4553 // start-sanitize-r5900
4555 // end-sanitize-r5900
4557 unsigned32 instruction = instruction_0;
4558 int destreg = ((instruction >> 6) & 0x0000001F);
4559 int fs = ((instruction >> 11) & 0x0000001F);
4560 int format = ((instruction >> 21) & 0x00000007);
4562 StoreFPR(destreg,format,ValueFPR(fs,format));
4568 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4569 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4572 // start-sanitize-vr4320
4574 // end-sanitize-vr4320
4575 // start-sanitize-vr5400
4577 // end-sanitize-vr5400
4578 // start-sanitize-r5900
4580 // end-sanitize-r5900
4582 unsigned32 instruction = instruction_0;
4583 int destreg = ((instruction >> 6) & 0x0000001F);
4584 int fs = ((instruction >> 11) & 0x0000001F);
4585 int ft = ((instruction >> 16) & 0x0000001F);
4586 int fr = ((instruction >> 21) & 0x0000001F);
4588 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4594 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4595 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4598 // start-sanitize-vr4320
4600 // end-sanitize-vr4320
4601 // start-sanitize-vr5400
4603 // end-sanitize-vr5400
4604 // start-sanitize-r5900
4606 // end-sanitize-r5900
4608 unsigned32 instruction = instruction_0;
4609 int destreg = ((instruction >> 6) & 0x0000001F);
4610 int fs = ((instruction >> 11) & 0x0000001F);
4611 int ft = ((instruction >> 16) & 0x0000001F);
4612 int fr = ((instruction >> 21) & 0x0000001F);
4614 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4622 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4623 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4624 *mipsI,mipsII,mipsIII,mipsIV:
4626 // start-sanitize-vr4320
4628 // end-sanitize-vr4320
4629 // start-sanitize-vr5400
4631 // end-sanitize-vr5400
4633 // start-sanitize-tx19
4635 // end-sanitize-tx19
4637 unsigned32 instruction = instruction_0;
4638 int destreg = ((instruction >> 6) & 0x0000001F);
4639 int fs = ((instruction >> 11) & 0x0000001F);
4640 int ft = ((instruction >> 16) & 0x0000001F);
4641 int format = ((instruction >> 21) & 0x00000007);
4643 if ((format != fmt_single) && (format != fmt_double))
4644 SignalException(ReservedInstruction,instruction);
4646 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4651 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4652 "neg.%s<FMT> f<FD>, f<FS>"
4653 *mipsI,mipsII,mipsIII,mipsIV:
4655 // start-sanitize-vr4320
4657 // end-sanitize-vr4320
4658 // start-sanitize-vr5400
4660 // end-sanitize-vr5400
4662 // start-sanitize-tx19
4664 // end-sanitize-tx19
4666 unsigned32 instruction = instruction_0;
4667 int destreg = ((instruction >> 6) & 0x0000001F);
4668 int fs = ((instruction >> 11) & 0x0000001F);
4669 int format = ((instruction >> 21) & 0x00000007);
4671 if ((format != fmt_single) && (format != fmt_double))
4672 SignalException(ReservedInstruction,instruction);
4674 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4680 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4681 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4684 // start-sanitize-vr4320
4686 // end-sanitize-vr4320
4687 // start-sanitize-vr5400
4689 // end-sanitize-vr5400
4691 unsigned32 instruction = instruction_0;
4692 int destreg = ((instruction >> 6) & 0x0000001F);
4693 int fs = ((instruction >> 11) & 0x0000001F);
4694 int ft = ((instruction >> 16) & 0x0000001F);
4695 int fr = ((instruction >> 21) & 0x0000001F);
4697 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4703 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4704 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4707 // start-sanitize-vr4320
4709 // end-sanitize-vr4320
4710 // start-sanitize-vr5400
4712 // end-sanitize-vr5400
4714 unsigned32 instruction = instruction_0;
4715 int destreg = ((instruction >> 6) & 0x0000001F);
4716 int fs = ((instruction >> 11) & 0x0000001F);
4717 int ft = ((instruction >> 16) & 0x0000001F);
4718 int fr = ((instruction >> 21) & 0x0000001F);
4720 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4726 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4727 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4730 // start-sanitize-vr4320
4732 // end-sanitize-vr4320
4733 // start-sanitize-vr5400
4735 // end-sanitize-vr5400
4737 unsigned32 instruction = instruction_0;
4738 int destreg = ((instruction >> 6) & 0x0000001F);
4739 int fs = ((instruction >> 11) & 0x0000001F);
4740 int ft = ((instruction >> 16) & 0x0000001F);
4741 int fr = ((instruction >> 21) & 0x0000001F);
4743 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4749 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4750 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4753 // start-sanitize-vr4320
4755 // end-sanitize-vr4320
4756 // start-sanitize-vr5400
4758 // end-sanitize-vr5400
4760 unsigned32 instruction = instruction_0;
4761 int destreg = ((instruction >> 6) & 0x0000001F);
4762 int fs = ((instruction >> 11) & 0x0000001F);
4763 int ft = ((instruction >> 16) & 0x0000001F);
4764 int fr = ((instruction >> 21) & 0x0000001F);
4766 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4771 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4772 "prefx <HINT>, r<INDEX>(r<BASE>)"
4775 // start-sanitize-vr4320
4777 // end-sanitize-vr4320
4778 // start-sanitize-vr5400
4780 // end-sanitize-vr5400
4782 unsigned32 instruction = instruction_0;
4783 int fs = ((instruction >> 11) & 0x0000001F);
4784 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4785 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4787 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4790 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4791 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4795 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4797 "recip.%s<FMT> f<FD>, f<FS>"
4799 // start-sanitize-vr4320
4801 // end-sanitize-vr4320
4802 // start-sanitize-vr5400
4804 // end-sanitize-vr5400
4806 unsigned32 instruction = instruction_0;
4807 int destreg = ((instruction >> 6) & 0x0000001F);
4808 int fs = ((instruction >> 11) & 0x0000001F);
4809 int format = ((instruction >> 21) & 0x00000007);
4811 if ((format != fmt_single) && (format != fmt_double))
4812 SignalException(ReservedInstruction,instruction);
4814 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4819 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4820 "round.l.%s<FMT> f<FD>, f<FS>"
4824 // start-sanitize-vr4320
4826 // end-sanitize-vr4320
4827 // start-sanitize-vr5400
4829 // end-sanitize-vr5400
4830 // start-sanitize-r5900
4832 // end-sanitize-r5900
4834 // start-sanitize-tx19
4836 // end-sanitize-tx19
4838 unsigned32 instruction = instruction_0;
4839 int destreg = ((instruction >> 6) & 0x0000001F);
4840 int fs = ((instruction >> 11) & 0x0000001F);
4841 int format = ((instruction >> 21) & 0x00000007);
4843 if ((format != fmt_single) && (format != fmt_double))
4844 SignalException(ReservedInstruction,instruction);
4846 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4851 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4852 "round.w.%s<FMT> f<FD>, f<FS>"
4857 // start-sanitize-vr4320
4859 // end-sanitize-vr4320
4860 // start-sanitize-vr5400
4862 // end-sanitize-vr5400
4863 // start-sanitize-r5900
4865 // end-sanitize-r5900
4867 // start-sanitize-tx19
4869 // end-sanitize-tx19
4871 unsigned32 instruction = instruction_0;
4872 int destreg = ((instruction >> 6) & 0x0000001F);
4873 int fs = ((instruction >> 11) & 0x0000001F);
4874 int format = ((instruction >> 21) & 0x00000007);
4876 if ((format != fmt_single) && (format != fmt_double))
4877 SignalException(ReservedInstruction,instruction);
4879 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4884 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4886 "rsqrt.%s<FMT> f<FD>, f<FS>"
4888 // start-sanitize-vr4320
4890 // end-sanitize-vr4320
4891 // start-sanitize-vr5400
4893 // end-sanitize-vr5400
4895 unsigned32 instruction = instruction_0;
4896 int destreg = ((instruction >> 6) & 0x0000001F);
4897 int fs = ((instruction >> 11) & 0x0000001F);
4898 int format = ((instruction >> 21) & 0x00000007);
4900 if ((format != fmt_single) && (format != fmt_double))
4901 SignalException(ReservedInstruction,instruction);
4903 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4908 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4909 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4914 // start-sanitize-vr4320
4916 // end-sanitize-vr4320
4917 // start-sanitize-vr5400
4919 // end-sanitize-vr5400
4921 // start-sanitize-tx19
4923 // end-sanitize-tx19
4925 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4929 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
4930 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
4933 // start-sanitize-vr4320
4935 // end-sanitize-vr4320
4936 // start-sanitize-vr5400
4938 // end-sanitize-vr5400
4940 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4944 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4945 "sqrt.%s<FMT> f<FD>, f<FS>"
4950 // start-sanitize-vr4320
4952 // end-sanitize-vr4320
4953 // start-sanitize-vr5400
4955 // end-sanitize-vr5400
4957 // start-sanitize-tx19
4959 // end-sanitize-tx19
4961 unsigned32 instruction = instruction_0;
4962 int destreg = ((instruction >> 6) & 0x0000001F);
4963 int fs = ((instruction >> 11) & 0x0000001F);
4964 int format = ((instruction >> 21) & 0x00000007);
4966 if ((format != fmt_single) && (format != fmt_double))
4967 SignalException(ReservedInstruction,instruction);
4969 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4974 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4975 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4976 *mipsI,mipsII,mipsIII,mipsIV:
4978 // start-sanitize-vr4320
4980 // end-sanitize-vr4320
4981 // start-sanitize-vr5400
4983 // end-sanitize-vr5400
4985 // start-sanitize-tx19
4987 // end-sanitize-tx19
4989 unsigned32 instruction = instruction_0;
4990 int destreg = ((instruction >> 6) & 0x0000001F);
4991 int fs = ((instruction >> 11) & 0x0000001F);
4992 int ft = ((instruction >> 16) & 0x0000001F);
4993 int format = ((instruction >> 21) & 0x00000007);
4995 if ((format != fmt_single) && (format != fmt_double))
4996 SignalException(ReservedInstruction,instruction);
4998 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5004 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5005 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5006 *mipsI,mipsII,mipsIII,mipsIV:
5008 // start-sanitize-vr4320
5010 // end-sanitize-vr4320
5011 // start-sanitize-vr5400
5013 // end-sanitize-vr5400
5014 // start-sanitize-r5900
5016 // end-sanitize-r5900
5018 // start-sanitize-tx19
5020 // end-sanitize-tx19
5022 unsigned32 instruction = instruction_0;
5023 signed_word offset = EXTEND16 (OFFSET);
5024 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5025 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5027 address_word vaddr = ((uword64)op1 + offset);
5030 if ((vaddr & 3) != 0)
5031 SignalExceptionAddressStore();
5034 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5037 uword64 memval1 = 0;
5040 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5041 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5042 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5044 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5052 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5053 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5056 // start-sanitize-vr4320
5058 // end-sanitize-vr4320
5059 // start-sanitize-vr5400
5061 // end-sanitize-vr5400
5063 unsigned32 instruction = instruction_0;
5064 int fs = ((instruction >> 11) & 0x0000001F);
5065 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5066 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5068 address_word vaddr = ((unsigned64)op1 + op2);
5071 if ((vaddr & 3) != 0)
5072 SignalExceptionAddressStore();
5075 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5077 unsigned64 memval = 0;
5078 unsigned64 memval1 = 0;
5079 unsigned64 mask = 0x7;
5081 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5082 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5083 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5085 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5093 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5094 "trunc.l.%s<FMT> f<FD>, f<FS>"
5098 // start-sanitize-vr4320
5100 // end-sanitize-vr4320
5101 // start-sanitize-vr5400
5103 // end-sanitize-vr5400
5104 // start-sanitize-r5900
5106 // end-sanitize-r5900
5108 // start-sanitize-tx19
5110 // end-sanitize-tx19
5112 unsigned32 instruction = instruction_0;
5113 int destreg = ((instruction >> 6) & 0x0000001F);
5114 int fs = ((instruction >> 11) & 0x0000001F);
5115 int format = ((instruction >> 21) & 0x00000007);
5117 if ((format != fmt_single) && (format != fmt_double))
5118 SignalException(ReservedInstruction,instruction);
5120 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5125 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5126 "trunc.w.%s<FMT> f<FD>, f<FS>"
5131 // start-sanitize-vr4320
5133 // end-sanitize-vr4320
5134 // start-sanitize-vr5400
5136 // end-sanitize-vr5400
5137 // start-sanitize-r5900
5139 // end-sanitize-r5900
5141 // start-sanitize-tx19
5143 // end-sanitize-tx19
5145 unsigned32 instruction = instruction_0;
5146 int destreg = ((instruction >> 6) & 0x0000001F);
5147 int fs = ((instruction >> 11) & 0x0000001F);
5148 int format = ((instruction >> 21) & 0x00000007);
5150 if ((format != fmt_single) && (format != fmt_double))
5151 SignalException(ReservedInstruction,instruction);
5153 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5159 // MIPS Architecture:
5161 // System Control Instruction Set (COP0)
5165 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5167 *mipsI,mipsII,mipsIII,mipsIV:
5169 // start-sanitize-vr4320
5171 // end-sanitize-vr4320
5172 // start-sanitize-vr5400
5174 // end-sanitize-vr5400
5175 // start-sanitize-r5900
5177 // end-sanitize-r5900
5180 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5182 *mipsI,mipsII,mipsIII,mipsIV:
5184 // start-sanitize-vr4320
5186 // end-sanitize-vr4320
5187 // start-sanitize-vr5400
5189 // end-sanitize-vr5400
5190 // start-sanitize-r5900
5192 // end-sanitize-r5900
5195 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5197 *mipsI,mipsII,mipsIII,mipsIV:
5198 // start-sanitize-r5900
5200 // end-sanitize-r5900
5204 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5206 *mipsI,mipsII,mipsIII,mipsIV:
5208 // start-sanitize-vr4320
5210 // end-sanitize-vr4320
5211 // start-sanitize-vr5400
5213 // end-sanitize-vr5400
5214 // start-sanitize-r5900
5216 // end-sanitize-r5900
5219 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5223 // start-sanitize-vr4320
5225 // end-sanitize-vr4320
5226 // start-sanitize-vr5400
5228 // end-sanitize-vr5400
5229 // start-sanitize-r5900
5231 // end-sanitize-r5900
5233 // start-sanitize-tx19
5235 // end-sanitize-tx19
5237 unsigned32 instruction = instruction_0;
5238 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5239 int hint = ((instruction >> 16) & 0x0000001F);
5240 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5242 address_word vaddr = (op1 + offset);
5245 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5246 CacheOp(hint,vaddr,paddr,instruction);
5251 010000,10000,000000000000000,111001:COP0:32::DI
5253 *mipsI,mipsII,mipsIII,mipsIV:
5255 // start-sanitize-vr4320
5257 // end-sanitize-vr4320
5258 // start-sanitize-vr5400
5260 // end-sanitize-vr5400
5261 // start-sanitize-r5900
5263 // end-sanitize-r5900
5266 010000,10000,000000000000000,111000:COP0:32::EI
5268 *mipsI,mipsII,mipsIII,mipsIV:
5270 // start-sanitize-vr4320
5272 // end-sanitize-vr4320
5273 // start-sanitize-vr5400
5275 // end-sanitize-vr5400
5276 // start-sanitize-r5900
5278 // end-sanitize-r5900
5281 010000,10000,000000000000000,011000:COP0:32::ERET
5286 // start-sanitize-vr4320
5288 // end-sanitize-vr4320
5289 // start-sanitize-vr5400
5291 // end-sanitize-vr5400
5292 // start-sanitize-r5900
5294 // end-sanitize-r5900
5296 if (SR & status_ERL)
5298 /* Oops, not yet available */
5299 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5311 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5312 "mfc0 r<RT>, r<RD> # <REGX>"
5313 *mipsI,mipsII,mipsIII,mipsIV:
5315 // start-sanitize-vr4320
5317 // end-sanitize-vr4320
5318 // start-sanitize-vr5400
5320 // end-sanitize-vr5400
5321 // start-sanitize-r5900
5323 // end-sanitize-r5900
5325 TRACE_ALU_INPUT0 ();
5326 DecodeCoproc (instruction_0);
5327 TRACE_ALU_RESULT (GPR[RT]);
5330 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5331 "mtc0 r<RT>, r<RD> # <REGX>"
5332 *mipsI,mipsII,mipsIII,mipsIV:
5333 // start-sanitize-tx19
5335 // end-sanitize-tx19
5337 // start-sanitize-vr4320
5339 // end-sanitize-vr4320
5341 // start-sanitize-vr5400
5343 // end-sanitize-vr5400
5344 // start-sanitize-r5900
5346 // end-sanitize-r5900
5348 DecodeCoproc (instruction_0);
5352 010000,10000,000000000000000,001000:COP0:32::TLBP
5354 *mipsI,mipsII,mipsIII,mipsIV:
5356 // start-sanitize-vr4320
5358 // end-sanitize-vr4320
5359 // start-sanitize-vr5400
5361 // end-sanitize-vr5400
5362 // start-sanitize-r5900
5364 // end-sanitize-r5900
5367 010000,10000,000000000000000,000001:COP0:32::TLBR
5369 *mipsI,mipsII,mipsIII,mipsIV:
5371 // start-sanitize-vr4320
5373 // end-sanitize-vr4320
5374 // start-sanitize-vr5400
5376 // end-sanitize-vr5400
5377 // start-sanitize-r5900
5379 // end-sanitize-r5900
5382 010000,10000,000000000000000,000010:COP0:32::TLBWI
5384 *mipsI,mipsII,mipsIII,mipsIV:
5386 // start-sanitize-vr4320
5388 // end-sanitize-vr4320
5389 // start-sanitize-vr5400
5391 // end-sanitize-vr5400
5392 // start-sanitize-r5900
5394 // end-sanitize-r5900
5397 010000,10000,000000000000000,000110:COP0:32::TLBWR
5399 *mipsI,mipsII,mipsIII,mipsIV:
5401 // start-sanitize-vr4320
5403 // end-sanitize-vr4320
5404 // start-sanitize-vr5400
5406 // end-sanitize-vr5400
5407 // start-sanitize-r5900
5409 // end-sanitize-r5900
5413 // start-sanitize-vr4320
5414 :include::vr4320:vr4320.igen
5415 // end-sanitize-vr4320
5416 // start-sanitize-vr5400
5417 :include::vr5400:vr5400.igen
5418 :include:64,f::mdmx.igen
5419 // end-sanitize-vr5400
5420 // start-sanitize-r5900
5421 :include::r5900:r5900.igen
5422 // end-sanitize-r5900
5425 // start-sanitize-cygnus-never
5427 // // FIXME FIXME FIXME What is this instruction?
5428 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5433 // // start-sanitize-r5900
5435 // // end-sanitize-r5900
5437 // // start-sanitize-tx19
5439 // // end-sanitize-tx19
5441 // unsigned32 instruction = instruction_0;
5442 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5443 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5444 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5446 // if (CoProcPresent(3))
5447 // SignalException(CoProcessorUnusable);
5449 // SignalException(ReservedInstruction,instruction);
5453 // end-sanitize-cygnus-never
5454 // start-sanitize-cygnus-never
5456 // // FIXME FIXME FIXME What is this?
5457 // 11100,******,00001:RR:16::SDBBP
5460 // unsigned32 instruction = instruction_0;
5461 // if (have_extendval)
5462 // SignalException (ReservedInstruction, instruction);
5464 // SignalException(DebugBreakPoint,instruction);
5468 // end-sanitize-cygnus-never
5469 // start-sanitize-cygnus-never
5471 // // FIXME FIXME FIXME What is this?
5472 // 000000,********************,001110:SPECIAL:32::SDBBP
5475 // unsigned32 instruction = instruction_0;
5477 // SignalException(DebugBreakPoint,instruction);
5481 // end-sanitize-cygnus-never
5482 // start-sanitize-cygnus-never
5484 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5485 // // isn't yet reconized by this simulator.
5486 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5489 // unsigned32 instruction = instruction_0;
5490 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5491 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5493 // CHECKHILO("Multiply-Add");
5495 // unsigned64 temp = (op1 * op2);
5496 // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5497 // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5498 // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5503 // end-sanitize-cygnus-never
5504 // start-sanitize-cygnus-never
5506 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5507 // // isn't yet reconized by this simulator.
5508 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5511 // unsigned32 instruction = instruction_0;
5512 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5513 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5515 // CHECKHILO("Multiply-Add");
5517 // unsigned64 temp = (op1 * op2);
5523 // end-sanitize-cygnus-never