sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips32r2:mipsisa32r2:
  49 :model:::mips64:mipsisa64:
  50 :model:::mips64r2:mipsisa64r2:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr4120:mips4120:
  61 :model:::vr5000:mips5000:
  62 :model:::vr5400:mips5400:
  63 :model:::vr5500:mips5500:
  64 :model:::r3900:mips3900:                // tx.igen
  65
  66 //  MIPS Application Specific Extensions (ASEs)
  67 //
  68 //  Instructions for the ASEs are in separate .igen files.
  69 //  ASEs add instructions on to a base ISA.
  70 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  71 :model:::mips3d:mips3d:                 // mips3d.igen
  72 :model:::mdmx:mdmx:                     // mdmx.igen
  73
  74 //  Vendor Extensions
  75 //
  76 //  Instructions specific to these extensions are in separate .igen files.
  77 //  Extensions add instructions on to a base ISA.
  78 :model:::sb1:sb1:                       // sb1.igen
  79
  80
  81 // Pseudo instructions known by IGEN
  82 :internal::::illegal:
  83 {
  84   SignalException (ReservedInstruction, 0);
  85 }
  86
  87
  88 // Pseudo instructions known by interp.c
  89 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  90 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  91 "rsvd <OP>"
  92 {
  93   SignalException (ReservedInstruction, instruction_0);
  94 }
  95
  96
  97
  98 // Helper:
  99 //
 100 // Simulate a 32 bit delayslot instruction
 101 //
 102
 103 :function:::address_word:delayslot32:address_word target
 104 {
 105   instruction_word delay_insn;
 106   sim_events_slip (SD, 1);
 107   DSPC = CIA;
 108   CIA = CIA + 4; /* NOTE not mips16 */
 109   STATE |= simDELAYSLOT;
 110   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 111   ENGINE_ISSUE_PREFIX_HOOK();
 112   idecode_issue (CPU_, delay_insn, (CIA));
 113   STATE &= ~simDELAYSLOT;
 114   return target;
 115 }
 116
 117 :function:::address_word:nullify_next_insn32:
 118 {
 119   sim_events_slip (SD, 1);
 120   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 121   return CIA + 8;
 122 }
 123
 124
 125 // Helper:
 126 //
 127 // Calculate an effective address given a base and an offset.
 128 //
 129
 130 :function:::address_word:loadstore_ea:address_word base, address_word offset
 131 *mipsI:
 132 *mipsII:
 133 *mipsIII:
 134 *mipsIV:
 135 *mipsV:
 136 *mips32:
 137 *mips32r2:
 138 *vr4100:
 139 *vr5000:
 140 *r3900:
 141 {
 142   return base + offset;
 143 }
 144
 145 :function:::address_word:loadstore_ea:address_word base, address_word offset
 146 *mips64:
 147 *mips64r2:
 148 {
 149 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 150   /* If in user mode and UX is not set, use 32-bit compatibility effective
 151      address computations as defined in the MIPS64 Architecture for
 152      Programmers Volume III, Revision 0.95, section 4.9.  */
 153   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 154       == (ksu_user << status_KSU_shift))
 155     return (address_word)((signed32)base + (signed32)offset);
 156 #endif
 157   return base + offset;
 158 }
 159
 160
 161 // Helper:
 162 //
 163 // Check that a 32-bit register value is properly sign-extended.
 164 // (See NotWordValue in ISA spec.)
 165 //
 166
 167 :function:::int:not_word_value:unsigned_word value
 168 *mipsI:
 169 *mipsII:
 170 *mipsIII:
 171 *mipsIV:
 172 *mipsV:
 173 *vr4100:
 174 *vr5000:
 175 *r3900:
 176 {
 177   /* For historical simulator compatibility (until documentation is
 178      found that makes these operations unpredictable on some of these
 179      architectures), this check never returns true.  */
 180   return 0;
 181 }
 182
 183 :function:::int:not_word_value:unsigned_word value
 184 *mips32:
 185 *mips32r2:
 186 {
 187   /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
 188   return 0;
 189 }
 190
 191 :function:::int:not_word_value:unsigned_word value
 192 *mips64:
 193 *mips64r2:
 194 {
 195   return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
 196 }
 197
 198
 199 // Helper:
 200 //
 201 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 202 // theoretically portable code which invokes non-portable behaviour from
 203 // running with no indication of the portability issue.
 204 // (See definition of UNPREDICTABLE in ISA spec.)
 205 //
 206
 207 :function:::void:unpredictable:
 208 *mipsI:
 209 *mipsII:
 210 *mipsIII:
 211 *mipsIV:
 212 *mipsV:
 213 *vr4100:
 214 *vr5000:
 215 *r3900:
 216 {
 217 }
 218
 219 :function:::void:unpredictable:
 220 *mips32:
 221 *mips32r2:
 222 *mips64:
 223 *mips64r2:
 224 {
 225   unpredictable_action (CPU, CIA);
 226 }
 227
 228
 229 // Helpers:
 230 //
 231 // Check that an access to a HI/LO register meets timing requirements
 232 //
 233 // In all MIPS ISAs,
 234 //
 235 //      OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
 236 //      makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
 237 //
 238 // The following restrictions exist for MIPS I - MIPS III:
 239 //
 240 //      MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
 241 //      in between makes MF UNPREDICTABLE. (2)
 242 //
 243 //      MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
 244 //      in between makes MF UNPREDICTABLE. (3)
 245 //
 246 // On the r3900, restriction (2) is not present, and restriction (3) is not
 247 // present for multiplication.
 248 //
 249 // Unfortunately, there seems to be some confusion about whether the last
 250 // two restrictions should apply to "MIPS IV" as well.  One edition of
 251 // the MIPS IV ISA says they do, but references in later ISA documents
 252 // suggest they don't.
 253 //
 254 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
 255 // these restrictions, while others, like the VR5500, don't.  To accomodate
 256 // such differences, the MIPS IV and MIPS V version of these helper functions
 257 // use auxillary routines to determine whether the restriction applies.
 258
 259 // check_mf_cycles:
 260 //
 261 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
 262 // to check for restrictions (2) and (3) above.
 263 //
 264 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 265 {
 266   if (history->mf.timestamp + 3 > time)
 267     {
 268       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 269                         itable[MY_INDEX].name,
 270                         new, (long) CIA,
 271                         (long) history->mf.cia);
 272       return 0;
 273     }
 274   return 1;
 275 }
 276
 277
 278 // check_mt_hilo:
 279 //
 280 // Check for restriction (2) above (for ISAs/processors that have it),
 281 // and record timestamps for restriction (1) above.
 282 //
 283 :function:::int:check_mt_hilo:hilo_history *history
 284 *mipsI:
 285 *mipsII:
 286 *mipsIII:
 287 *vr4100:
 288 *vr5000:
 289 {
 290   signed64 time = sim_events_time (SD);
 291   int ok = check_mf_cycles (SD_, history, time, "MT");
 292   history->mt.timestamp = time;
 293   history->mt.cia = CIA;
 294   return ok;
 295 }
 296
 297 :function:::int:check_mt_hilo:hilo_history *history
 298 *mipsIV:
 299 *mipsV:
 300 {
 301   signed64 time = sim_events_time (SD);
 302   int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
 303             || check_mf_cycles (SD_, history, time, "MT"));
 304   history->mt.timestamp = time;
 305   history->mt.cia = CIA;
 306   return ok;
 307 }
 308
 309 :function:::int:check_mt_hilo:hilo_history *history
 310 *mips32:
 311 *mips32r2:
 312 *mips64:
 313 *mips64r2:
 314 *r3900:
 315 {
 316   signed64 time = sim_events_time (SD);
 317   history->mt.timestamp = time;
 318   history->mt.cia = CIA;
 319   return 1;
 320 }
 321
 322
 323 // check_mf_hilo:
 324 //
 325 // Check for restriction (1) above, and record timestamps for
 326 // restriction (2) and (3) above.
 327 //
 328 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 329 *mipsI:
 330 *mipsII:
 331 *mipsIII:
 332 *mipsIV:
 333 *mipsV:
 334 *mips32:
 335 *mips32r2:
 336 *mips64:
 337 *mips64r2:
 338 *vr4100:
 339 *vr5000:
 340 *r3900:
 341 {
 342   signed64 time = sim_events_time (SD);
 343   int ok = 1;
 344   if (peer != NULL
 345       && peer->mt.timestamp > history->op.timestamp
 346       && history->mt.timestamp < history->op.timestamp
 347       && ! (history->mf.timestamp > history->op.timestamp
 348             && history->mf.timestamp < peer->mt.timestamp)
 349       && ! (peer->mf.timestamp > history->op.timestamp
 350             && peer->mf.timestamp < peer->mt.timestamp))
 351     {
 352       /* The peer has been written to since the last OP yet we have
 353          not */
 354       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 355                         itable[MY_INDEX].name,
 356                         (long) CIA,
 357                         (long) history->op.cia,
 358                         (long) peer->mt.cia);
 359       ok = 0;
 360     }
 361   history->mf.timestamp = time;
 362   history->mf.cia = CIA;
 363   return ok;
 364 }
 365
 366
 367
 368 // check_mult_hilo:
 369 //
 370 // Check for restriction (3) above (for ISAs/processors that have it)
 371 // for MULT ops, and record timestamps for restriction (1) above.
 372 //
 373 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 374 *mipsI:
 375 *mipsII:
 376 *mipsIII:
 377 *vr4100:
 378 *vr5000:
 379 {
 380   signed64 time = sim_events_time (SD);
 381   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 382             && check_mf_cycles (SD_, lo, time, "OP"));
 383   hi->op.timestamp = time;
 384   lo->op.timestamp = time;
 385   hi->op.cia = CIA;
 386   lo->op.cia = CIA;
 387   return ok;
 388 }
 389
 390 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 391 *mipsIV:
 392 *mipsV:
 393 {
 394   signed64 time = sim_events_time (SD);
 395   int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
 396             || (check_mf_cycles (SD_, hi, time, "OP")
 397                 && check_mf_cycles (SD_, lo, time, "OP")));
 398   hi->op.timestamp = time;
 399   lo->op.timestamp = time;
 400   hi->op.cia = CIA;
 401   lo->op.cia = CIA;
 402   return ok;
 403 }
 404
 405 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 406 *mips32:
 407 *mips32r2:
 408 *mips64:
 409 *mips64r2:
 410 *r3900:
 411 {
 412   /* FIXME: could record the fact that a stall occured if we want */
 413   signed64 time = sim_events_time (SD);
 414   hi->op.timestamp = time;
 415   lo->op.timestamp = time;
 416   hi->op.cia = CIA;
 417   lo->op.cia = CIA;
 418   return 1;
 419 }
 420
 421
 422 // check_div_hilo:
 423 //
 424 // Check for restriction (3) above (for ISAs/processors that have it)
 425 // for DIV ops, and record timestamps for restriction (1) above.
 426 //
 427 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 428 *mipsI:
 429 *mipsII:
 430 *mipsIII:
 431 *vr4100:
 432 *vr5000:
 433 *r3900:
 434 {
 435   signed64 time = sim_events_time (SD);
 436   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 437             && check_mf_cycles (SD_, lo, time, "OP"));
 438   hi->op.timestamp = time;
 439   lo->op.timestamp = time;
 440   hi->op.cia = CIA;
 441   lo->op.cia = CIA;
 442   return ok;
 443 }
 444
 445 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 446 *mipsIV:
 447 *mipsV:
 448 {
 449   signed64 time = sim_events_time (SD);
 450   int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
 451             || (check_mf_cycles (SD_, hi, time, "OP")
 452                 && check_mf_cycles (SD_, lo, time, "OP")));
 453   hi->op.timestamp = time;
 454   lo->op.timestamp = time;
 455   hi->op.cia = CIA;
 456   lo->op.cia = CIA;
 457   return ok;
 458 }
 459
 460 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 461 *mips32:
 462 *mips32r2:
 463 *mips64:
 464 *mips64r2:
 465 {
 466   signed64 time = sim_events_time (SD);
 467   hi->op.timestamp = time;
 468   lo->op.timestamp = time;
 469   hi->op.cia = CIA;
 470   lo->op.cia = CIA;
 471   return 1;
 472 }
 473
 474
 475 // Helper:
 476 //
 477 // Check that the 64-bit instruction can currently be used, and signal
 478 // a ReservedInstruction exception if not.
 479 //
 480
 481 :function:::void:check_u64:instruction_word insn
 482 *mipsIII:
 483 *mipsIV:
 484 *mipsV:
 485 *vr4100:
 486 *vr5000:
 487 *vr5400:
 488 *vr5500:
 489 {
 490   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 491 }
 492
 493 :function:::void:check_u64:instruction_word insn
 494 *mips64:
 495 *mips64r2:
 496 {
 497 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 498   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 499     SignalException (ReservedInstruction, insn);
 500 #endif
 501 }
 502
 503
 504
 505 //
 506 // MIPS Architecture:
 507 //
 508 //        CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
 509 //
 510
 511
 512
 513 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 514 "add r<RD>, r<RS>, r<RT>"
 515 *mipsI:
 516 *mipsII:
 517 *mipsIII:
 518 *mipsIV:
 519 *mipsV:
 520 *mips32:
 521 *mips32r2:
 522 *mips64:
 523 *mips64r2:
 524 *vr4100:
 525 *vr5000:
 526 *r3900:
 527 {
 528   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 529     Unpredictable ();
 530   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 531   {
 532     ALU32_BEGIN (GPR[RS]);
 533     ALU32_ADD (GPR[RT]);
 534     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 535   }
 536   TRACE_ALU_RESULT (GPR[RD]);
 537 }
 538
 539
 540
 541 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 542 "addi r<RT>, r<RS>, <IMMEDIATE>"
 543 *mipsI:
 544 *mipsII:
 545 *mipsIII:
 546 *mipsIV:
 547 *mipsV:
 548 *mips32:
 549 *mips32r2:
 550 *mips64:
 551 *mips64r2:
 552 *vr4100:
 553 *vr5000:
 554 *r3900:
 555 {
 556   if (NotWordValue (GPR[RS]))
 557     Unpredictable ();
 558   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 559   {
 560     ALU32_BEGIN (GPR[RS]);
 561     ALU32_ADD (EXTEND16 (IMMEDIATE));
 562     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 563   }
 564   TRACE_ALU_RESULT (GPR[RT]);
 565 }
 566
 567
 568
 569 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 570 {
 571   if (NotWordValue (GPR[rs]))
 572     Unpredictable ();
 573   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 574   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 575   TRACE_ALU_RESULT (GPR[rt]);
 576 }
 577
 578 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 579 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 580 *mipsI:
 581 *mipsII:
 582 *mipsIII:
 583 *mipsIV:
 584 *mipsV:
 585 *mips32:
 586 *mips32r2:
 587 *mips64:
 588 *mips64r2:
 589 *vr4100:
 590 *vr5000:
 591 *r3900:
 592 {
 593   do_addiu (SD_, RS, RT, IMMEDIATE);
 594 }
 595
 596
 597
 598 :function:::void:do_addu:int rs, int rt, int rd
 599 {
 600   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 601     Unpredictable ();
 602   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 603   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 604   TRACE_ALU_RESULT (GPR[rd]);
 605 }
 606
 607 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 608 "addu r<RD>, r<RS>, r<RT>"
 609 *mipsI:
 610 *mipsII:
 611 *mipsIII:
 612 *mipsIV:
 613 *mipsV:
 614 *mips32:
 615 *mips32r2:
 616 *mips64:
 617 *mips64r2:
 618 *vr4100:
 619 *vr5000:
 620 *r3900:
 621 {
 622   do_addu (SD_, RS, RT, RD);
 623 }
 624
 625
 626
 627 :function:::void:do_and:int rs, int rt, int rd
 628 {
 629   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 630   GPR[rd] = GPR[rs] & GPR[rt];
 631   TRACE_ALU_RESULT (GPR[rd]);
 632 }
 633
 634 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 635 "and r<RD>, r<RS>, r<RT>"
 636 *mipsI:
 637 *mipsII:
 638 *mipsIII:
 639 *mipsIV:
 640 *mipsV:
 641 *mips32:
 642 *mips32r2:
 643 *mips64:
 644 *mips64r2:
 645 *vr4100:
 646 *vr5000:
 647 *r3900:
 648 {
 649   do_and (SD_, RS, RT, RD);
 650 }
 651
 652
 653
 654 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 655 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 656 *mipsI:
 657 *mipsII:
 658 *mipsIII:
 659 *mipsIV:
 660 *mipsV:
 661 *mips32:
 662 *mips32r2:
 663 *mips64:
 664 *mips64r2:
 665 *vr4100:
 666 *vr5000:
 667 *r3900:
 668 {
 669   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 670   GPR[RT] = GPR[RS] & IMMEDIATE;
 671   TRACE_ALU_RESULT (GPR[RT]);
 672 }
 673
 674
 675
 676 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 677 "beq r<RS>, r<RT>, <OFFSET>"
 678 *mipsI:
 679 *mipsII:
 680 *mipsIII:
 681 *mipsIV:
 682 *mipsV:
 683 *mips32:
 684 *mips32r2:
 685 *mips64:
 686 *mips64r2:
 687 *vr4100:
 688 *vr5000:
 689 *r3900:
 690 {
 691   address_word offset = EXTEND16 (OFFSET) << 2;
 692   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 693     {
 694       DELAY_SLOT (NIA + offset);
 695     }
 696 }
 697
 698
 699
 700 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 701 "beql r<RS>, r<RT>, <OFFSET>"
 702 *mipsII:
 703 *mipsIII:
 704 *mipsIV:
 705 *mipsV:
 706 *mips32:
 707 *mips32r2:
 708 *mips64:
 709 *mips64r2:
 710 *vr4100:
 711 *vr5000:
 712 *r3900:
 713 {
 714   address_word offset = EXTEND16 (OFFSET) << 2;
 715   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 716     {
 717       DELAY_SLOT (NIA + offset);
 718     }
 719   else
 720     NULLIFY_NEXT_INSTRUCTION ();
 721 }
 722
 723
 724
 725 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 726 "bgez r<RS>, <OFFSET>"
 727 *mipsI:
 728 *mipsII:
 729 *mipsIII:
 730 *mipsIV:
 731 *mipsV:
 732 *mips32:
 733 *mips32r2:
 734 *mips64:
 735 *mips64r2:
 736 *vr4100:
 737 *vr5000:
 738 *r3900:
 739 {
 740   address_word offset = EXTEND16 (OFFSET) << 2;
 741   if ((signed_word) GPR[RS] >= 0)
 742     {
 743       DELAY_SLOT (NIA + offset);
 744     }
 745 }
 746
 747
 748
 749 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 750 "bgezal r<RS>, <OFFSET>"
 751 *mipsI:
 752 *mipsII:
 753 *mipsIII:
 754 *mipsIV:
 755 *mipsV:
 756 *mips32:
 757 *mips32r2:
 758 *mips64:
 759 *mips64r2:
 760 *vr4100:
 761 *vr5000:
 762 *r3900:
 763 {
 764   address_word offset = EXTEND16 (OFFSET) << 2;
 765   if (RS == 31)
 766     Unpredictable ();
 767   RA = (CIA + 8);
 768   if ((signed_word) GPR[RS] >= 0)
 769     {
 770       DELAY_SLOT (NIA + offset);
 771     }
 772 }
 773
 774
 775
 776 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 777 "bgezall r<RS>, <OFFSET>"
 778 *mipsII:
 779 *mipsIII:
 780 *mipsIV:
 781 *mipsV:
 782 *mips32:
 783 *mips32r2:
 784 *mips64:
 785 *mips64r2:
 786 *vr4100:
 787 *vr5000:
 788 *r3900:
 789 {
 790   address_word offset = EXTEND16 (OFFSET) << 2;
 791   if (RS == 31)
 792     Unpredictable ();
 793   RA = (CIA + 8);
 794   /* NOTE: The branch occurs AFTER the next instruction has been
 795      executed */
 796   if ((signed_word) GPR[RS] >= 0)
 797     {
 798       DELAY_SLOT (NIA + offset);
 799     }
 800   else
 801     NULLIFY_NEXT_INSTRUCTION ();
 802 }
 803
 804
 805
 806 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 807 "bgezl r<RS>, <OFFSET>"
 808 *mipsII:
 809 *mipsIII:
 810 *mipsIV:
 811 *mipsV:
 812 *mips32:
 813 *mips32r2:
 814 *mips64:
 815 *mips64r2:
 816 *vr4100:
 817 *vr5000:
 818 *r3900:
 819 {
 820   address_word offset = EXTEND16 (OFFSET) << 2;
 821   if ((signed_word) GPR[RS] >= 0)
 822     {
 823       DELAY_SLOT (NIA + offset);
 824     }
 825   else
 826     NULLIFY_NEXT_INSTRUCTION ();
 827 }
 828
 829
 830
 831 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 832 "bgtz r<RS>, <OFFSET>"
 833 *mipsI:
 834 *mipsII:
 835 *mipsIII:
 836 *mipsIV:
 837 *mipsV:
 838 *mips32:
 839 *mips32r2:
 840 *mips64:
 841 *mips64r2:
 842 *vr4100:
 843 *vr5000:
 844 *r3900:
 845 {
 846   address_word offset = EXTEND16 (OFFSET) << 2;
 847   if ((signed_word) GPR[RS] > 0)
 848     {
 849       DELAY_SLOT (NIA + offset);
 850     }
 851 }
 852
 853
 854
 855 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 856 "bgtzl r<RS>, <OFFSET>"
 857 *mipsII:
 858 *mipsIII:
 859 *mipsIV:
 860 *mipsV:
 861 *mips32:
 862 *mips32r2:
 863 *mips64:
 864 *mips64r2:
 865 *vr4100:
 866 *vr5000:
 867 *r3900:
 868 {
 869   address_word offset = EXTEND16 (OFFSET) << 2;
 870   /* NOTE: The branch occurs AFTER the next instruction has been
 871      executed */
 872   if ((signed_word) GPR[RS] > 0)
 873     {
 874       DELAY_SLOT (NIA + offset);
 875     }
 876   else
 877     NULLIFY_NEXT_INSTRUCTION ();
 878 }
 879
 880
 881
 882 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 883 "blez r<RS>, <OFFSET>"
 884 *mipsI:
 885 *mipsII:
 886 *mipsIII:
 887 *mipsIV:
 888 *mipsV:
 889 *mips32:
 890 *mips32r2:
 891 *mips64:
 892 *mips64r2:
 893 *vr4100:
 894 *vr5000:
 895 *r3900:
 896 {
 897   address_word offset = EXTEND16 (OFFSET) << 2;
 898   /* NOTE: The branch occurs AFTER the next instruction has been
 899      executed */
 900   if ((signed_word) GPR[RS] <= 0)
 901     {
 902       DELAY_SLOT (NIA + offset);
 903     }
 904 }
 905
 906
 907
 908 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 909 "bgezl r<RS>, <OFFSET>"
 910 *mipsII:
 911 *mipsIII:
 912 *mipsIV:
 913 *mipsV:
 914 *mips32:
 915 *mips32r2:
 916 *mips64:
 917 *mips64r2:
 918 *vr4100:
 919 *vr5000:
 920 *r3900:
 921 {
 922   address_word offset = EXTEND16 (OFFSET) << 2;
 923   if ((signed_word) GPR[RS] <= 0)
 924     {
 925       DELAY_SLOT (NIA + offset);
 926     }
 927   else
 928     NULLIFY_NEXT_INSTRUCTION ();
 929 }
 930
 931
 932
 933 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 934 "bltz r<RS>, <OFFSET>"
 935 *mipsI:
 936 *mipsII:
 937 *mipsIII:
 938 *mipsIV:
 939 *mipsV:
 940 *mips32:
 941 *mips32r2:
 942 *mips64:
 943 *mips64r2:
 944 *vr4100:
 945 *vr5000:
 946 *r3900:
 947 {
 948   address_word offset = EXTEND16 (OFFSET) << 2;
 949   if ((signed_word) GPR[RS] < 0)
 950     {
 951       DELAY_SLOT (NIA + offset);
 952     }
 953 }
 954
 955
 956
 957 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 958 "bltzal r<RS>, <OFFSET>"
 959 *mipsI:
 960 *mipsII:
 961 *mipsIII:
 962 *mipsIV:
 963 *mipsV:
 964 *mips32:
 965 *mips32r2:
 966 *mips64:
 967 *mips64r2:
 968 *vr4100:
 969 *vr5000:
 970 *r3900:
 971 {
 972   address_word offset = EXTEND16 (OFFSET) << 2;
 973   if (RS == 31)
 974     Unpredictable ();
 975   RA = (CIA + 8);
 976   /* NOTE: The branch occurs AFTER the next instruction has been
 977      executed */
 978   if ((signed_word) GPR[RS] < 0)
 979     {
 980       DELAY_SLOT (NIA + offset);
 981     }
 982 }
 983
 984
 985
 986 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 987 "bltzall r<RS>, <OFFSET>"
 988 *mipsII:
 989 *mipsIII:
 990 *mipsIV:
 991 *mipsV:
 992 *mips32:
 993 *mips32r2:
 994 *mips64:
 995 *mips64r2:
 996 *vr4100:
 997 *vr5000:
 998 *r3900:
 999 {
1000   address_word offset = EXTEND16 (OFFSET) << 2;
1001   if (RS == 31)
1002     Unpredictable ();
1003   RA = (CIA + 8);
1004   if ((signed_word) GPR[RS] < 0)
1005     {
1006       DELAY_SLOT (NIA + offset);
1007     }
1008   else
1009     NULLIFY_NEXT_INSTRUCTION ();
1010 }
1011
1012
1013
1014 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1015 "bltzl r<RS>, <OFFSET>"
1016 *mipsII:
1017 *mipsIII:
1018 *mipsIV:
1019 *mipsV:
1020 *mips32:
1021 *mips32r2:
1022 *mips64:
1023 *mips64r2:
1024 *vr4100:
1025 *vr5000:
1026 *r3900:
1027 {
1028   address_word offset = EXTEND16 (OFFSET) << 2;
1029   /* NOTE: The branch occurs AFTER the next instruction has been
1030      executed */
1031   if ((signed_word) GPR[RS] < 0)
1032     {
1033       DELAY_SLOT (NIA + offset);
1034     }
1035   else
1036     NULLIFY_NEXT_INSTRUCTION ();
1037 }
1038
1039
1040
1041 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1042 "bne r<RS>, r<RT>, <OFFSET>"
1043 *mipsI:
1044 *mipsII:
1045 *mipsIII:
1046 *mipsIV:
1047 *mipsV:
1048 *mips32:
1049 *mips32r2:
1050 *mips64:
1051 *mips64r2:
1052 *vr4100:
1053 *vr5000:
1054 *r3900:
1055 {
1056   address_word offset = EXTEND16 (OFFSET) << 2;
1057   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1058     {
1059       DELAY_SLOT (NIA + offset);
1060     }
1061 }
1062
1063
1064
1065 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1066 "bnel r<RS>, r<RT>, <OFFSET>"
1067 *mipsII:
1068 *mipsIII:
1069 *mipsIV:
1070 *mipsV:
1071 *mips32:
1072 *mips32r2:
1073 *mips64:
1074 *mips64r2:
1075 *vr4100:
1076 *vr5000:
1077 *r3900:
1078 {
1079   address_word offset = EXTEND16 (OFFSET) << 2;
1080   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1081     {
1082       DELAY_SLOT (NIA + offset);
1083     }
1084   else
1085     NULLIFY_NEXT_INSTRUCTION ();
1086 }
1087
1088
1089
1090 000000,20.CODE,001101:SPECIAL:32::BREAK
1091 "break %#lx<CODE>"
1092 *mipsI:
1093 *mipsII:
1094 *mipsIII:
1095 *mipsIV:
1096 *mipsV:
1097 *mips32:
1098 *mips32r2:
1099 *mips64:
1100 *mips64r2:
1101 *vr4100:
1102 *vr5000:
1103 *r3900:
1104 {
1105   /* Check for some break instruction which are reserved for use by the simulator.  */
1106   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1107   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1108       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1109     {
1110       sim_engine_halt (SD, CPU, NULL, cia,
1111                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1112     }
1113   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1114            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1115     {
1116       if (STATE & simDELAYSLOT)
1117         PC = cia - 4; /* reference the branch instruction */
1118       else
1119         PC = cia;
1120       SignalException (BreakPoint, instruction_0);
1121     }
1122
1123   else
1124     {
1125       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1126          the exception. */
1127       SignalException (BreakPoint, instruction_0);
1128     }
1129 }
1130
1131
1132
1133 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1134 "clo r<RD>, r<RS>"
1135 *mips32:
1136 *mips32r2:
1137 *mips64:
1138 *mips64r2:
1139 *vr5500:
1140 {
1141   unsigned32 temp = GPR[RS];
1142   unsigned32 i, mask;
1143   if (RT != RD)
1144     Unpredictable ();
1145   if (NotWordValue (GPR[RS]))
1146     Unpredictable ();
1147   TRACE_ALU_INPUT1 (GPR[RS]);
1148   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1149     {
1150       if ((temp & mask) == 0)
1151         break;
1152       mask >>= 1;
1153     }
1154   GPR[RD] = EXTEND32 (i);
1155   TRACE_ALU_RESULT (GPR[RD]);
1156 }
1157
1158
1159
1160 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1161 "clz r<RD>, r<RS>"
1162 *mips32:
1163 *mips32r2:
1164 *mips64:
1165 *mips64r2:
1166 *vr5500:
1167 {
1168   unsigned32 temp = GPR[RS];
1169   unsigned32 i, mask;
1170   if (RT != RD)
1171     Unpredictable ();
1172   if (NotWordValue (GPR[RS]))
1173     Unpredictable ();
1174   TRACE_ALU_INPUT1 (GPR[RS]);
1175   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1176     {
1177       if ((temp & mask) != 0)
1178         break;
1179       mask >>= 1;
1180     }
1181   GPR[RD] = EXTEND32 (i);
1182   TRACE_ALU_RESULT (GPR[RD]);
1183 }
1184
1185
1186
1187 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1188 "dadd r<RD>, r<RS>, r<RT>"
1189 *mipsIII:
1190 *mipsIV:
1191 *mipsV:
1192 *mips64:
1193 *mips64r2:
1194 *vr4100:
1195 *vr5000:
1196 {
1197   check_u64 (SD_, instruction_0);
1198   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1199   {
1200     ALU64_BEGIN (GPR[RS]);
1201     ALU64_ADD (GPR[RT]);
1202     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1203   }
1204   TRACE_ALU_RESULT (GPR[RD]);
1205 }
1206
1207
1208
1209 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1210 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1211 *mipsIII:
1212 *mipsIV:
1213 *mipsV:
1214 *mips64:
1215 *mips64r2:
1216 *vr4100:
1217 *vr5000:
1218 {
1219   check_u64 (SD_, instruction_0);
1220   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1221   {
1222     ALU64_BEGIN (GPR[RS]);
1223     ALU64_ADD (EXTEND16 (IMMEDIATE));
1224     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1225   }
1226   TRACE_ALU_RESULT (GPR[RT]);
1227 }
1228
1229
1230
1231 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1232 {
1233   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1234   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1235   TRACE_ALU_RESULT (GPR[rt]);
1236 }
1237
1238 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1239 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1240 *mipsIII:
1241 *mipsIV:
1242 *mipsV:
1243 *mips64:
1244 *mips64r2:
1245 *vr4100:
1246 *vr5000:
1247 {
1248   check_u64 (SD_, instruction_0);
1249   do_daddiu (SD_, RS, RT, IMMEDIATE);
1250 }
1251
1252
1253
1254 :function:::void:do_daddu:int rs, int rt, int rd
1255 {
1256   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1257   GPR[rd] = GPR[rs] + GPR[rt];
1258   TRACE_ALU_RESULT (GPR[rd]);
1259 }
1260
1261 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1262 "daddu r<RD>, r<RS>, r<RT>"
1263 *mipsIII:
1264 *mipsIV:
1265 *mipsV:
1266 *mips64:
1267 *mips64r2:
1268 *vr4100:
1269 *vr5000:
1270 {
1271   check_u64 (SD_, instruction_0);
1272   do_daddu (SD_, RS, RT, RD);
1273 }
1274
1275
1276
1277 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1278 "dclo r<RD>, r<RS>"
1279 *mips64:
1280 *mips64r2:
1281 *vr5500:
1282 {
1283   unsigned64 temp = GPR[RS];
1284   unsigned32 i;
1285   unsigned64 mask;
1286   check_u64 (SD_, instruction_0);
1287   if (RT != RD)
1288     Unpredictable ();
1289   TRACE_ALU_INPUT1 (GPR[RS]);
1290   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1291     {
1292       if ((temp & mask) == 0)
1293         break;
1294       mask >>= 1;
1295     }
1296   GPR[RD] = EXTEND32 (i);
1297   TRACE_ALU_RESULT (GPR[RD]);
1298 }
1299
1300
1301
1302 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1303 "dclz r<RD>, r<RS>"
1304 *mips64:
1305 *mips64r2:
1306 *vr5500:
1307 {
1308   unsigned64 temp = GPR[RS];
1309   unsigned32 i;
1310   unsigned64 mask;
1311   check_u64 (SD_, instruction_0);
1312   if (RT != RD)
1313     Unpredictable ();
1314   TRACE_ALU_INPUT1 (GPR[RS]);
1315   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1316     {
1317       if ((temp & mask) != 0)
1318         break;
1319       mask >>= 1;
1320     }
1321   GPR[RD] = EXTEND32 (i);
1322   TRACE_ALU_RESULT (GPR[RD]);
1323 }
1324
1325
1326
1327 :function:::void:do_ddiv:int rs, int rt
1328 {
1329   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1330   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1331   {
1332     signed64 n = GPR[rs];
1333     signed64 d = GPR[rt];
1334     signed64 hi;
1335     signed64 lo;
1336     if (d == 0)
1337       {
1338         lo = SIGNED64 (0x8000000000000000);
1339         hi = 0;
1340       }
1341     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1342       {
1343         lo = SIGNED64 (0x8000000000000000);
1344         hi = 0;
1345       }
1346     else
1347       {
1348         lo = (n / d);
1349         hi = (n % d);
1350       }
1351     HI = hi;
1352     LO = lo;
1353   }
1354   TRACE_ALU_RESULT2 (HI, LO);
1355 }
1356
1357 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1358 "ddiv r<RS>, r<RT>"
1359 *mipsIII:
1360 *mipsIV:
1361 *mipsV:
1362 *mips64:
1363 *mips64r2:
1364 *vr4100:
1365 *vr5000:
1366 {
1367   check_u64 (SD_, instruction_0);
1368   do_ddiv (SD_, RS, RT);
1369 }
1370
1371
1372
1373 :function:::void:do_ddivu:int rs, int rt
1374 {
1375   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1376   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1377   {
1378     unsigned64 n = GPR[rs];
1379     unsigned64 d = GPR[rt];
1380     unsigned64 hi;
1381     unsigned64 lo;
1382     if (d == 0)
1383       {
1384         lo = SIGNED64 (0x8000000000000000);
1385         hi = 0;
1386       }
1387     else
1388       {
1389         lo = (n / d);
1390         hi = (n % d);
1391       }
1392     HI = hi;
1393     LO = lo;
1394   }
1395   TRACE_ALU_RESULT2 (HI, LO);
1396 }
1397
1398 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1399 "ddivu r<RS>, r<RT>"
1400 *mipsIII:
1401 *mipsIV:
1402 *mipsV:
1403 *mips64:
1404 *mips64r2:
1405 *vr4100:
1406 *vr5000:
1407 {
1408   check_u64 (SD_, instruction_0);
1409   do_ddivu (SD_, RS, RT);
1410 }
1411
1412 :function:::void:do_div:int rs, int rt
1413 {
1414   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1415   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1416   {
1417     signed32 n = GPR[rs];
1418     signed32 d = GPR[rt];
1419     if (d == 0)
1420       {
1421         LO = EXTEND32 (0x80000000);
1422         HI = EXTEND32 (0);
1423       }
1424     else if (n == SIGNED32 (0x80000000) && d == -1)
1425       {
1426         LO = EXTEND32 (0x80000000);
1427         HI = EXTEND32 (0);
1428       }
1429     else
1430       {
1431         LO = EXTEND32 (n / d);
1432         HI = EXTEND32 (n % d);
1433       }
1434   }
1435   TRACE_ALU_RESULT2 (HI, LO);
1436 }
1437
1438 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1439 "div r<RS>, r<RT>"
1440 *mipsI:
1441 *mipsII:
1442 *mipsIII:
1443 *mipsIV:
1444 *mipsV:
1445 *mips32:
1446 *mips32r2:
1447 *mips64:
1448 *mips64r2:
1449 *vr4100:
1450 *vr5000:
1451 *r3900:
1452 {
1453   do_div (SD_, RS, RT);
1454 }
1455
1456
1457
1458 :function:::void:do_divu:int rs, int rt
1459 {
1460   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1461   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1462   {
1463     unsigned32 n = GPR[rs];
1464     unsigned32 d = GPR[rt];
1465     if (d == 0)
1466       {
1467         LO = EXTEND32 (0x80000000);
1468         HI = EXTEND32 (0);
1469       }
1470     else
1471       {
1472         LO = EXTEND32 (n / d);
1473         HI = EXTEND32 (n % d);
1474       }
1475   }
1476   TRACE_ALU_RESULT2 (HI, LO);
1477 }
1478
1479 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1480 "divu r<RS>, r<RT>"
1481 *mipsI:
1482 *mipsII:
1483 *mipsIII:
1484 *mipsIV:
1485 *mipsV:
1486 *mips32:
1487 *mips32r2:
1488 *mips64:
1489 *mips64r2:
1490 *vr4100:
1491 *vr5000:
1492 *r3900:
1493 {
1494   do_divu (SD_, RS, RT);
1495 }
1496
1497
1498 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1499 {
1500   unsigned64 lo;
1501   unsigned64 hi;
1502   unsigned64 m00;
1503   unsigned64 m01;
1504   unsigned64 m10;
1505   unsigned64 m11;
1506   unsigned64 mid;
1507   int sign;
1508   unsigned64 op1 = GPR[rs];
1509   unsigned64 op2 = GPR[rt];
1510   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1511   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1512   /* make signed multiply unsigned */
1513   sign = 0;
1514   if (signed_p)
1515     {
1516       if ((signed64) op1 < 0)
1517         {
1518           op1 = - op1;
1519           ++sign;
1520         }
1521       if ((signed64) op2 < 0)
1522         {
1523           op2 = - op2;
1524           ++sign;
1525         }
1526     }
1527   /* multiply out the 4 sub products */
1528   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1529   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1530   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1531   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1532   /* add the products */
1533   mid = ((unsigned64) VH4_8 (m00)
1534          + (unsigned64) VL4_8 (m10)
1535          + (unsigned64) VL4_8 (m01));
1536   lo = U8_4 (mid, m00);
1537   hi = (m11
1538         + (unsigned64) VH4_8 (mid)
1539         + (unsigned64) VH4_8 (m01)
1540         + (unsigned64) VH4_8 (m10));
1541   /* fix the sign */
1542   if (sign & 1)
1543     {
1544       lo = -lo;
1545       if (lo == 0)
1546         hi = -hi;
1547       else
1548         hi = -hi - 1;
1549     }
1550   /* save the result HI/LO (and a gpr) */
1551   LO = lo;
1552   HI = hi;
1553   if (rd != 0)
1554     GPR[rd] = lo;
1555   TRACE_ALU_RESULT2 (HI, LO);
1556 }
1557
1558 :function:::void:do_dmult:int rs, int rt, int rd
1559 {
1560   do_dmultx (SD_, rs, rt, rd, 1);
1561 }
1562
1563 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1564 "dmult r<RS>, r<RT>"
1565 *mipsIII:
1566 *mipsIV:
1567 *mipsV:
1568 *mips64:
1569 *mips64r2:
1570 *vr4100:
1571 {
1572   check_u64 (SD_, instruction_0);
1573   do_dmult (SD_, RS, RT, 0);
1574 }
1575
1576 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1577 "dmult r<RS>, r<RT>":RD == 0
1578 "dmult r<RD>, r<RS>, r<RT>"
1579 *vr5000:
1580 {
1581   check_u64 (SD_, instruction_0);
1582   do_dmult (SD_, RS, RT, RD);
1583 }
1584
1585
1586
1587 :function:::void:do_dmultu:int rs, int rt, int rd
1588 {
1589   do_dmultx (SD_, rs, rt, rd, 0);
1590 }
1591
1592 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1593 "dmultu r<RS>, r<RT>"
1594 *mipsIII:
1595 *mipsIV:
1596 *mipsV:
1597 *mips64:
1598 *mips64r2:
1599 *vr4100:
1600 {
1601   check_u64 (SD_, instruction_0);
1602   do_dmultu (SD_, RS, RT, 0);
1603 }
1604
1605 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1606 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1607 "dmultu r<RS>, r<RT>"
1608 *vr5000:
1609 {
1610   check_u64 (SD_, instruction_0);
1611   do_dmultu (SD_, RS, RT, RD);
1612 }
1613
1614
1615 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1616 {
1617   unsigned64 result;
1618
1619   y &= 63;
1620   TRACE_ALU_INPUT2 (x, y);
1621   result = ROTR64 (x, y);
1622   TRACE_ALU_RESULT (result);
1623   return result;
1624 }
1625
1626 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1627 "dror r<RD>, r<RT>, <SHIFT>"
1628 *mips64r2:
1629 *vr5400:
1630 *vr5500:
1631 {
1632   check_u64 (SD_, instruction_0);
1633   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1634 }
1635
1636 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1637 "dror32 r<RD>, r<RT>, <SHIFT>"
1638 *mips64r2:
1639 *vr5400:
1640 *vr5500:
1641 {
1642   check_u64 (SD_, instruction_0);
1643   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1644 }
1645
1646 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1647 "drorv r<RD>, r<RT>, r<RS>"
1648 *mips64r2:
1649 *vr5400:
1650 *vr5500:
1651 {
1652   check_u64 (SD_, instruction_0);
1653   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1654 }
1655
1656
1657 :function:::void:do_dsll:int rt, int rd, int shift
1658 {
1659   TRACE_ALU_INPUT2 (GPR[rt], shift);
1660   GPR[rd] = GPR[rt] << shift;
1661   TRACE_ALU_RESULT (GPR[rd]);
1662 }
1663
1664 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1665 "dsll r<RD>, r<RT>, <SHIFT>"
1666 *mipsIII:
1667 *mipsIV:
1668 *mipsV:
1669 *mips64:
1670 *mips64r2:
1671 *vr4100:
1672 *vr5000:
1673 {
1674   check_u64 (SD_, instruction_0);
1675   do_dsll (SD_, RT, RD, SHIFT);
1676 }
1677
1678
1679 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1680 "dsll32 r<RD>, r<RT>, <SHIFT>"
1681 *mipsIII:
1682 *mipsIV:
1683 *mipsV:
1684 *mips64:
1685 *mips64r2:
1686 *vr4100:
1687 *vr5000:
1688 {
1689   int s = 32 + SHIFT;
1690   check_u64 (SD_, instruction_0);
1691   TRACE_ALU_INPUT2 (GPR[RT], s);
1692   GPR[RD] = GPR[RT] << s;
1693   TRACE_ALU_RESULT (GPR[RD]);
1694 }
1695
1696 :function:::void:do_dsllv:int rs, int rt, int rd
1697 {
1698   int s = MASKED64 (GPR[rs], 5, 0);
1699   TRACE_ALU_INPUT2 (GPR[rt], s);
1700   GPR[rd] = GPR[rt] << s;
1701   TRACE_ALU_RESULT (GPR[rd]);
1702 }
1703
1704 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1705 "dsllv r<RD>, r<RT>, r<RS>"
1706 *mipsIII:
1707 *mipsIV:
1708 *mipsV:
1709 *mips64:
1710 *mips64r2:
1711 *vr4100:
1712 *vr5000:
1713 {
1714   check_u64 (SD_, instruction_0);
1715   do_dsllv (SD_, RS, RT, RD);
1716 }
1717
1718 :function:::void:do_dsra:int rt, int rd, int shift
1719 {
1720   TRACE_ALU_INPUT2 (GPR[rt], shift);
1721   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1722   TRACE_ALU_RESULT (GPR[rd]);
1723 }
1724
1725
1726 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1727 "dsra r<RD>, r<RT>, <SHIFT>"
1728 *mipsIII:
1729 *mipsIV:
1730 *mipsV:
1731 *mips64:
1732 *mips64r2:
1733 *vr4100:
1734 *vr5000:
1735 {
1736   check_u64 (SD_, instruction_0);
1737   do_dsra (SD_, RT, RD, SHIFT);
1738 }
1739
1740
1741 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1742 "dsra32 r<RD>, r<RT>, <SHIFT>"
1743 *mipsIII:
1744 *mipsIV:
1745 *mipsV:
1746 *mips64:
1747 *mips64r2:
1748 *vr4100:
1749 *vr5000:
1750 {
1751   int s = 32 + SHIFT;
1752   check_u64 (SD_, instruction_0);
1753   TRACE_ALU_INPUT2 (GPR[RT], s);
1754   GPR[RD] = ((signed64) GPR[RT]) >> s;
1755   TRACE_ALU_RESULT (GPR[RD]);
1756 }
1757
1758
1759 :function:::void:do_dsrav:int rs, int rt, int rd
1760 {
1761   int s = MASKED64 (GPR[rs], 5, 0);
1762   TRACE_ALU_INPUT2 (GPR[rt], s);
1763   GPR[rd] = ((signed64) GPR[rt]) >> s;
1764   TRACE_ALU_RESULT (GPR[rd]);
1765 }
1766
1767 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1768 "dsrav r<RD>, r<RT>, r<RS>"
1769 *mipsIII:
1770 *mipsIV:
1771 *mipsV:
1772 *mips64:
1773 *mips64r2:
1774 *vr4100:
1775 *vr5000:
1776 {
1777   check_u64 (SD_, instruction_0);
1778   do_dsrav (SD_, RS, RT, RD);
1779 }
1780
1781 :function:::void:do_dsrl:int rt, int rd, int shift
1782 {
1783   TRACE_ALU_INPUT2 (GPR[rt], shift);
1784   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1785   TRACE_ALU_RESULT (GPR[rd]);
1786 }
1787
1788
1789 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1790 "dsrl r<RD>, r<RT>, <SHIFT>"
1791 *mipsIII:
1792 *mipsIV:
1793 *mipsV:
1794 *mips64:
1795 *mips64r2:
1796 *vr4100:
1797 *vr5000:
1798 {
1799   check_u64 (SD_, instruction_0);
1800   do_dsrl (SD_, RT, RD, SHIFT);
1801 }
1802
1803
1804 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1805 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1806 *mipsIII:
1807 *mipsIV:
1808 *mipsV:
1809 *mips64:
1810 *mips64r2:
1811 *vr4100:
1812 *vr5000:
1813 {
1814   int s = 32 + SHIFT;
1815   check_u64 (SD_, instruction_0);
1816   TRACE_ALU_INPUT2 (GPR[RT], s);
1817   GPR[RD] = (unsigned64) GPR[RT] >> s;
1818   TRACE_ALU_RESULT (GPR[RD]);
1819 }
1820
1821
1822 :function:::void:do_dsrlv:int rs, int rt, int rd
1823 {
1824   int s = MASKED64 (GPR[rs], 5, 0);
1825   TRACE_ALU_INPUT2 (GPR[rt], s);
1826   GPR[rd] = (unsigned64) GPR[rt] >> s;
1827   TRACE_ALU_RESULT (GPR[rd]);
1828 }
1829
1830
1831
1832 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1833 "dsrlv r<RD>, r<RT>, r<RS>"
1834 *mipsIII:
1835 *mipsIV:
1836 *mipsV:
1837 *mips64:
1838 *mips64r2:
1839 *vr4100:
1840 *vr5000:
1841 {
1842   check_u64 (SD_, instruction_0);
1843   do_dsrlv (SD_, RS, RT, RD);
1844 }
1845
1846
1847 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1848 "dsub r<RD>, r<RS>, r<RT>"
1849 *mipsIII:
1850 *mipsIV:
1851 *mipsV:
1852 *mips64:
1853 *mips64r2:
1854 *vr4100:
1855 *vr5000:
1856 {
1857   check_u64 (SD_, instruction_0);
1858   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1859   {
1860     ALU64_BEGIN (GPR[RS]);
1861     ALU64_SUB (GPR[RT]);
1862     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1863   }
1864   TRACE_ALU_RESULT (GPR[RD]);
1865 }
1866
1867
1868 :function:::void:do_dsubu:int rs, int rt, int rd
1869 {
1870   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1871   GPR[rd] = GPR[rs] - GPR[rt];
1872   TRACE_ALU_RESULT (GPR[rd]);
1873 }
1874
1875 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1876 "dsubu r<RD>, r<RS>, r<RT>"
1877 *mipsIII:
1878 *mipsIV:
1879 *mipsV:
1880 *mips64:
1881 *mips64r2:
1882 *vr4100:
1883 *vr5000:
1884 {
1885   check_u64 (SD_, instruction_0);
1886   do_dsubu (SD_, RS, RT, RD);
1887 }
1888
1889
1890 000010,26.INSTR_INDEX:NORMAL:32::J
1891 "j <INSTR_INDEX>"
1892 *mipsI:
1893 *mipsII:
1894 *mipsIII:
1895 *mipsIV:
1896 *mipsV:
1897 *mips32:
1898 *mips32r2:
1899 *mips64:
1900 *mips64r2:
1901 *vr4100:
1902 *vr5000:
1903 *r3900:
1904 {
1905   /* NOTE: The region used is that of the delay slot NIA and NOT the
1906      current instruction */
1907   address_word region = (NIA & MASK (63, 28));
1908   DELAY_SLOT (region | (INSTR_INDEX << 2));
1909 }
1910
1911
1912 000011,26.INSTR_INDEX:NORMAL:32::JAL
1913 "jal <INSTR_INDEX>"
1914 *mipsI:
1915 *mipsII:
1916 *mipsIII:
1917 *mipsIV:
1918 *mipsV:
1919 *mips32:
1920 *mips32r2:
1921 *mips64:
1922 *mips64r2:
1923 *vr4100:
1924 *vr5000:
1925 *r3900:
1926 {
1927   /* NOTE: The region used is that of the delay slot and NOT the
1928      current instruction */
1929   address_word region = (NIA & MASK (63, 28));
1930   GPR[31] = CIA + 8;
1931   DELAY_SLOT (region | (INSTR_INDEX << 2));
1932 }
1933
1934 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1935 "jalr r<RS>":RD == 31
1936 "jalr r<RD>, r<RS>"
1937 *mipsI:
1938 *mipsII:
1939 *mipsIII:
1940 *mipsIV:
1941 *mipsV:
1942 *mips32:
1943 *mips32r2:
1944 *mips64:
1945 *mips64r2:
1946 *vr4100:
1947 *vr5000:
1948 *r3900:
1949 {
1950   address_word temp = GPR[RS];
1951   GPR[RD] = CIA + 8;
1952   DELAY_SLOT (temp);
1953 }
1954
1955
1956 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1957 "jr r<RS>"
1958 *mipsI:
1959 *mipsII:
1960 *mipsIII:
1961 *mipsIV:
1962 *mipsV:
1963 *mips32:
1964 *mips32r2:
1965 *mips64:
1966 *mips64r2:
1967 *vr4100:
1968 *vr5000:
1969 *r3900:
1970 {
1971   DELAY_SLOT (GPR[RS]);
1972 }
1973
1974
1975 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1976 {
1977   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1978   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1979   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1980   unsigned int byte;
1981   address_word paddr;
1982   int uncached;
1983   unsigned64 memval;
1984   address_word vaddr;
1985
1986   vaddr = loadstore_ea (SD_, base, offset);
1987   if ((vaddr & access) != 0)
1988     {
1989       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1990     }
1991   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1992   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1993   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1994   byte = ((vaddr & mask) ^ bigendiancpu);
1995   return (memval >> (8 * byte));
1996 }
1997
1998 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1999 {
2000   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2001   address_word reverseendian = (ReverseEndian ? -1 : 0);
2002   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2003   unsigned int byte;
2004   unsigned int word;
2005   address_word paddr;
2006   int uncached;
2007   unsigned64 memval;
2008   address_word vaddr;
2009   int nr_lhs_bits;
2010   int nr_rhs_bits;
2011   unsigned_word lhs_mask;
2012   unsigned_word temp;
2013
2014   vaddr = loadstore_ea (SD_, base, offset);
2015   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2016   paddr = (paddr ^ (reverseendian & mask));
2017   if (BigEndianMem == 0)
2018     paddr = paddr & ~access;
2019
2020   /* compute where within the word/mem we are */
2021   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2022   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2023   nr_lhs_bits = 8 * byte + 8;
2024   nr_rhs_bits = 8 * access - 8 * byte;
2025   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2026
2027   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2028            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2029            (long) ((unsigned64) paddr >> 32), (long) paddr,
2030            word, byte, nr_lhs_bits, nr_rhs_bits); */
2031
2032   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2033   if (word == 0)
2034     {
2035       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2036       temp = (memval << nr_rhs_bits);
2037     }
2038   else
2039     {
2040       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2041       temp = (memval >> nr_lhs_bits);
2042     }
2043   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2044   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2045
2046   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2047            (long) ((unsigned64) memval >> 32), (long) memval,
2048            (long) ((unsigned64) temp >> 32), (long) temp,
2049            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2050            (long) (rt >> 32), (long) rt); */
2051   return rt;
2052 }
2053
2054 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2055 {
2056   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2057   address_word reverseendian = (ReverseEndian ? -1 : 0);
2058   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2059   unsigned int byte;
2060   address_word paddr;
2061   int uncached;
2062   unsigned64 memval;
2063   address_word vaddr;
2064
2065   vaddr = loadstore_ea (SD_, base, offset);
2066   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2067   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2068   paddr = (paddr ^ (reverseendian & mask));
2069   if (BigEndianMem != 0)
2070     paddr = paddr & ~access;
2071   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2072   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2073   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2074   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2075      (long) paddr, byte, (long) paddr, (long) memval); */
2076   {
2077     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2078     rt &= ~screen;
2079     rt |= (memval >> (8 * byte)) & screen;
2080   }
2081   return rt;
2082 }
2083
2084
2085 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2086 "lb r<RT>, <OFFSET>(r<BASE>)"
2087 *mipsI:
2088 *mipsII:
2089 *mipsIII:
2090 *mipsIV:
2091 *mipsV:
2092 *mips32:
2093 *mips32r2:
2094 *mips64:
2095 *mips64r2:
2096 *vr4100:
2097 *vr5000:
2098 *r3900:
2099 {
2100   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2101 }
2102
2103
2104 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2105 "lbu r<RT>, <OFFSET>(r<BASE>)"
2106 *mipsI:
2107 *mipsII:
2108 *mipsIII:
2109 *mipsIV:
2110 *mipsV:
2111 *mips32:
2112 *mips32r2:
2113 *mips64:
2114 *mips64r2:
2115 *vr4100:
2116 *vr5000:
2117 *r3900:
2118 {
2119   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2120 }
2121
2122
2123 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2124 "ld r<RT>, <OFFSET>(r<BASE>)"
2125 *mipsIII:
2126 *mipsIV:
2127 *mipsV:
2128 *mips64:
2129 *mips64r2:
2130 *vr4100:
2131 *vr5000:
2132 {
2133   check_u64 (SD_, instruction_0);
2134   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2135 }
2136
2137
2138 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2139 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2140 *mipsII:
2141 *mipsIII:
2142 *mipsIV:
2143 *mipsV:
2144 *mips32:
2145 *mips32r2:
2146 *mips64:
2147 *mips64r2:
2148 *vr4100:
2149 *vr5000:
2150 *r3900:
2151 {
2152   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2153 }
2154
2155
2156
2157
2158 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2159 "ldl r<RT>, <OFFSET>(r<BASE>)"
2160 *mipsIII:
2161 *mipsIV:
2162 *mipsV:
2163 *mips64:
2164 *mips64r2:
2165 *vr4100:
2166 *vr5000:
2167 {
2168   check_u64 (SD_, instruction_0);
2169   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2170 }
2171
2172
2173 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2174 "ldr r<RT>, <OFFSET>(r<BASE>)"
2175 *mipsIII:
2176 *mipsIV:
2177 *mipsV:
2178 *mips64:
2179 *mips64r2:
2180 *vr4100:
2181 *vr5000:
2182 {
2183   check_u64 (SD_, instruction_0);
2184   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2185 }
2186
2187
2188 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2189 "lh r<RT>, <OFFSET>(r<BASE>)"
2190 *mipsI:
2191 *mipsII:
2192 *mipsIII:
2193 *mipsIV:
2194 *mipsV:
2195 *mips32:
2196 *mips32r2:
2197 *mips64:
2198 *mips64r2:
2199 *vr4100:
2200 *vr5000:
2201 *r3900:
2202 {
2203   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2204 }
2205
2206
2207 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2208 "lhu r<RT>, <OFFSET>(r<BASE>)"
2209 *mipsI:
2210 *mipsII:
2211 *mipsIII:
2212 *mipsIV:
2213 *mipsV:
2214 *mips32:
2215 *mips32r2:
2216 *mips64:
2217 *mips64r2:
2218 *vr4100:
2219 *vr5000:
2220 *r3900:
2221 {
2222   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2223 }
2224
2225
2226 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2227 "ll r<RT>, <OFFSET>(r<BASE>)"
2228 *mipsII:
2229 *mipsIII:
2230 *mipsIV:
2231 *mipsV:
2232 *mips32:
2233 *mips32r2:
2234 *mips64:
2235 *mips64r2:
2236 *vr4100:
2237 *vr5000:
2238 {
2239   address_word base = GPR[BASE];
2240   address_word offset = EXTEND16 (OFFSET);
2241   {
2242     address_word vaddr = loadstore_ea (SD_, base, offset);
2243     address_word paddr;
2244     int uncached;
2245     if ((vaddr & 3) != 0)
2246       {
2247         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2248       }
2249     else
2250       {
2251         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2252           {
2253             unsigned64 memval = 0;
2254             unsigned64 memval1 = 0;
2255             unsigned64 mask = 0x7;
2256             unsigned int shift = 2;
2257             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2258             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2259             unsigned int byte;
2260             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2261             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2262             byte = ((vaddr & mask) ^ (bigend << shift));
2263             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2264             LLBIT = 1;
2265           }
2266       }
2267   }
2268 }
2269
2270
2271 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2272 "lld r<RT>, <OFFSET>(r<BASE>)"
2273 *mipsIII:
2274 *mipsIV:
2275 *mipsV:
2276 *mips64:
2277 *mips64r2:
2278 *vr4100:
2279 *vr5000:
2280 {
2281   address_word base = GPR[BASE];
2282   address_word offset = EXTEND16 (OFFSET);
2283   check_u64 (SD_, instruction_0);
2284   {
2285     address_word vaddr = loadstore_ea (SD_, base, offset);
2286     address_word paddr;
2287     int uncached;
2288     if ((vaddr & 7) != 0)
2289       {
2290         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2291       }
2292     else
2293       {
2294         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2295           {
2296             unsigned64 memval = 0;
2297             unsigned64 memval1 = 0;
2298             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2299             GPR[RT] = memval;
2300             LLBIT = 1;
2301           }
2302       }
2303   }
2304 }
2305
2306
2307 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2308 "lui r<RT>, %#lx<IMMEDIATE>"
2309 *mipsI:
2310 *mipsII:
2311 *mipsIII:
2312 *mipsIV:
2313 *mipsV:
2314 *mips32:
2315 *mips32r2:
2316 *mips64:
2317 *mips64r2:
2318 *vr4100:
2319 *vr5000:
2320 *r3900:
2321 {
2322   TRACE_ALU_INPUT1 (IMMEDIATE);
2323   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2324   TRACE_ALU_RESULT (GPR[RT]);
2325 }
2326
2327
2328 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2329 "lw r<RT>, <OFFSET>(r<BASE>)"
2330 *mipsI:
2331 *mipsII:
2332 *mipsIII:
2333 *mipsIV:
2334 *mipsV:
2335 *mips32:
2336 *mips32r2:
2337 *mips64:
2338 *mips64r2:
2339 *vr4100:
2340 *vr5000:
2341 *r3900:
2342 {
2343   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2344 }
2345
2346
2347 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2348 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2349 *mipsI:
2350 *mipsII:
2351 *mipsIII:
2352 *mipsIV:
2353 *mipsV:
2354 *mips32:
2355 *mips32r2:
2356 *mips64:
2357 *mips64r2:
2358 *vr4100:
2359 *vr5000:
2360 *r3900:
2361 {
2362   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2363 }
2364
2365
2366 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2367 "lwl r<RT>, <OFFSET>(r<BASE>)"
2368 *mipsI:
2369 *mipsII:
2370 *mipsIII:
2371 *mipsIV:
2372 *mipsV:
2373 *mips32:
2374 *mips32r2:
2375 *mips64:
2376 *mips64r2:
2377 *vr4100:
2378 *vr5000:
2379 *r3900:
2380 {
2381   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2382 }
2383
2384
2385 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2386 "lwr r<RT>, <OFFSET>(r<BASE>)"
2387 *mipsI:
2388 *mipsII:
2389 *mipsIII:
2390 *mipsIV:
2391 *mipsV:
2392 *mips32:
2393 *mips32r2:
2394 *mips64:
2395 *mips64r2:
2396 *vr4100:
2397 *vr5000:
2398 *r3900:
2399 {
2400   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2401 }
2402
2403
2404 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2405 "lwu r<RT>, <OFFSET>(r<BASE>)"
2406 *mipsIII:
2407 *mipsIV:
2408 *mipsV:
2409 *mips64:
2410 *mips64r2:
2411 *vr4100:
2412 *vr5000:
2413 {
2414   check_u64 (SD_, instruction_0);
2415   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2416 }
2417
2418
2419
2420 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2421 "madd r<RS>, r<RT>"
2422 *mips32:
2423 *mips32r2:
2424 *mips64:
2425 *mips64r2:
2426 *vr5500:
2427 {
2428   signed64 temp;
2429   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2430   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2431     Unpredictable ();
2432   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2433   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2434           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2435   LO = EXTEND32 (temp);
2436   HI = EXTEND32 (VH4_8 (temp));
2437   TRACE_ALU_RESULT2 (HI, LO);
2438 }
2439
2440
2441
2442 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2443 "maddu r<RS>, r<RT>"
2444 *mips32:
2445 *mips32r2:
2446 *mips64:
2447 *mips64r2:
2448 *vr5500:
2449 {
2450   unsigned64 temp;
2451   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2452   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2453     Unpredictable ();
2454   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2455   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2456           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2457   LO = EXTEND32 (temp);
2458   HI = EXTEND32 (VH4_8 (temp));
2459   TRACE_ALU_RESULT2 (HI, LO);
2460 }
2461
2462
2463 :function:::void:do_mfhi:int rd
2464 {
2465   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2466   TRACE_ALU_INPUT1 (HI);
2467   GPR[rd] = HI;
2468   TRACE_ALU_RESULT (GPR[rd]);
2469 }
2470
2471 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2472 "mfhi r<RD>"
2473 *mipsI:
2474 *mipsII:
2475 *mipsIII:
2476 *mipsIV:
2477 *mipsV:
2478 *mips32:
2479 *mips32r2:
2480 *mips64:
2481 *mips64r2:
2482 *vr4100:
2483 *vr5000:
2484 *r3900:
2485 {
2486   do_mfhi (SD_, RD);
2487 }
2488
2489
2490
2491 :function:::void:do_mflo:int rd
2492 {
2493   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2494   TRACE_ALU_INPUT1 (LO);
2495   GPR[rd] = LO;
2496   TRACE_ALU_RESULT (GPR[rd]);
2497 }
2498
2499 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2500 "mflo r<RD>"
2501 *mipsI:
2502 *mipsII:
2503 *mipsIII:
2504 *mipsIV:
2505 *mipsV:
2506 *mips32:
2507 *mips32r2:
2508 *mips64:
2509 *mips64r2:
2510 *vr4100:
2511 *vr5000:
2512 *r3900:
2513 {
2514   do_mflo (SD_, RD);
2515 }
2516
2517
2518
2519 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2520 "movn r<RD>, r<RS>, r<RT>"
2521 *mipsIV:
2522 *mipsV:
2523 *mips32:
2524 *mips32r2:
2525 *mips64:
2526 *mips64r2:
2527 *vr5000:
2528 {
2529   if (GPR[RT] != 0)
2530     {
2531       GPR[RD] = GPR[RS];
2532       TRACE_ALU_RESULT (GPR[RD]);
2533     }
2534 }
2535
2536
2537
2538 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2539 "movz r<RD>, r<RS>, r<RT>"
2540 *mipsIV:
2541 *mipsV:
2542 *mips32:
2543 *mips32r2:
2544 *mips64:
2545 *mips64r2:
2546 *vr5000:
2547 {
2548   if (GPR[RT] == 0)
2549     {
2550       GPR[RD] = GPR[RS];
2551       TRACE_ALU_RESULT (GPR[RD]);
2552     }
2553 }
2554
2555
2556
2557 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2558 "msub r<RS>, r<RT>"
2559 *mips32:
2560 *mips32r2:
2561 *mips64:
2562 *mips64r2:
2563 *vr5500:
2564 {
2565   signed64 temp;
2566   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2567   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2568     Unpredictable ();
2569   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2570   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2571           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2572   LO = EXTEND32 (temp);
2573   HI = EXTEND32 (VH4_8 (temp));
2574   TRACE_ALU_RESULT2 (HI, LO);
2575 }
2576
2577
2578
2579 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2580 "msubu r<RS>, r<RT>"
2581 *mips32:
2582 *mips32r2:
2583 *mips64:
2584 *mips64r2:
2585 *vr5500:
2586 {
2587   unsigned64 temp;
2588   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2589   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2590     Unpredictable ();
2591   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2592   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2593           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2594   LO = EXTEND32 (temp);
2595   HI = EXTEND32 (VH4_8 (temp));
2596   TRACE_ALU_RESULT2 (HI, LO);
2597 }
2598
2599
2600
2601 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2602 "mthi r<RS>"
2603 *mipsI:
2604 *mipsII:
2605 *mipsIII:
2606 *mipsIV:
2607 *mipsV:
2608 *mips32:
2609 *mips32r2:
2610 *mips64:
2611 *mips64r2:
2612 *vr4100:
2613 *vr5000:
2614 *r3900:
2615 {
2616   check_mt_hilo (SD_, HIHISTORY);
2617   HI = GPR[RS];
2618 }
2619
2620
2621
2622 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2623 "mtlo r<RS>"
2624 *mipsI:
2625 *mipsII:
2626 *mipsIII:
2627 *mipsIV:
2628 *mipsV:
2629 *mips32:
2630 *mips32r2:
2631 *mips64:
2632 *mips64r2:
2633 *vr4100:
2634 *vr5000:
2635 *r3900:
2636 {
2637   check_mt_hilo (SD_, LOHISTORY);
2638   LO = GPR[RS];
2639 }
2640
2641
2642
2643 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2644 "mul r<RD>, r<RS>, r<RT>"
2645 *mips32:
2646 *mips32r2:
2647 *mips64:
2648 *mips64r2:
2649 *vr5500:
2650 {
2651   signed64 prod;
2652   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2653     Unpredictable ();
2654   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2655   prod = (((signed64)(signed32) GPR[RS])
2656           * ((signed64)(signed32) GPR[RT]));
2657   GPR[RD] = EXTEND32 (VL4_8 (prod));
2658   TRACE_ALU_RESULT (GPR[RD]);
2659 }
2660
2661
2662
2663 :function:::void:do_mult:int rs, int rt, int rd
2664 {
2665   signed64 prod;
2666   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2667   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2668     Unpredictable ();
2669   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2670   prod = (((signed64)(signed32) GPR[rs])
2671           * ((signed64)(signed32) GPR[rt]));
2672   LO = EXTEND32 (VL4_8 (prod));
2673   HI = EXTEND32 (VH4_8 (prod));
2674   if (rd != 0)
2675     GPR[rd] = LO;
2676   TRACE_ALU_RESULT2 (HI, LO);
2677 }
2678
2679 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2680 "mult r<RS>, r<RT>"
2681 *mipsI:
2682 *mipsII:
2683 *mipsIII:
2684 *mipsIV:
2685 *mipsV:
2686 *mips32:
2687 *mips32r2:
2688 *mips64:
2689 *mips64r2:
2690 *vr4100:
2691 {
2692   do_mult (SD_, RS, RT, 0);
2693 }
2694
2695
2696 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2697 "mult r<RS>, r<RT>":RD == 0
2698 "mult r<RD>, r<RS>, r<RT>"
2699 *vr5000:
2700 *r3900:
2701 {
2702   do_mult (SD_, RS, RT, RD);
2703 }
2704
2705
2706 :function:::void:do_multu:int rs, int rt, int rd
2707 {
2708   unsigned64 prod;
2709   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2710   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2711     Unpredictable ();
2712   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2713   prod = (((unsigned64)(unsigned32) GPR[rs])
2714           * ((unsigned64)(unsigned32) GPR[rt]));
2715   LO = EXTEND32 (VL4_8 (prod));
2716   HI = EXTEND32 (VH4_8 (prod));
2717   if (rd != 0)
2718     GPR[rd] = LO;
2719   TRACE_ALU_RESULT2 (HI, LO);
2720 }
2721
2722 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2723 "multu r<RS>, r<RT>"
2724 *mipsI:
2725 *mipsII:
2726 *mipsIII:
2727 *mipsIV:
2728 *mipsV:
2729 *mips32:
2730 *mips32r2:
2731 *mips64:
2732 *mips64r2:
2733 *vr4100:
2734 {
2735   do_multu (SD_, RS, RT, 0);
2736 }
2737
2738 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2739 "multu r<RS>, r<RT>":RD == 0
2740 "multu r<RD>, r<RS>, r<RT>"
2741 *vr5000:
2742 *r3900:
2743 {
2744   do_multu (SD_, RS, RT, RD);
2745 }
2746
2747
2748 :function:::void:do_nor:int rs, int rt, int rd
2749 {
2750   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2751   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2752   TRACE_ALU_RESULT (GPR[rd]);
2753 }
2754
2755 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2756 "nor r<RD>, r<RS>, r<RT>"
2757 *mipsI:
2758 *mipsII:
2759 *mipsIII:
2760 *mipsIV:
2761 *mipsV:
2762 *mips32:
2763 *mips32r2:
2764 *mips64:
2765 *mips64r2:
2766 *vr4100:
2767 *vr5000:
2768 *r3900:
2769 {
2770   do_nor (SD_, RS, RT, RD);
2771 }
2772
2773
2774 :function:::void:do_or:int rs, int rt, int rd
2775 {
2776   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2777   GPR[rd] = (GPR[rs] | GPR[rt]);
2778   TRACE_ALU_RESULT (GPR[rd]);
2779 }
2780
2781 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2782 "or r<RD>, r<RS>, r<RT>"
2783 *mipsI:
2784 *mipsII:
2785 *mipsIII:
2786 *mipsIV:
2787 *mipsV:
2788 *mips32:
2789 *mips32r2:
2790 *mips64:
2791 *mips64r2:
2792 *vr4100:
2793 *vr5000:
2794 *r3900:
2795 {
2796   do_or (SD_, RS, RT, RD);
2797 }
2798
2799
2800
2801 :function:::void:do_ori:int rs, int rt, unsigned immediate
2802 {
2803   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2804   GPR[rt] = (GPR[rs] | immediate);
2805   TRACE_ALU_RESULT (GPR[rt]);
2806 }
2807
2808 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2809 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2810 *mipsI:
2811 *mipsII:
2812 *mipsIII:
2813 *mipsIV:
2814 *mipsV:
2815 *mips32:
2816 *mips32r2:
2817 *mips64:
2818 *mips64r2:
2819 *vr4100:
2820 *vr5000:
2821 *r3900:
2822 {
2823   do_ori (SD_, RS, RT, IMMEDIATE);
2824 }
2825
2826
2827 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2828 "pref <HINT>, <OFFSET>(r<BASE>)"
2829 *mipsIV:
2830 *mipsV:
2831 *mips32:
2832 *mips32r2:
2833 *mips64:
2834 *mips64r2:
2835 *vr5000:
2836 {
2837   address_word base = GPR[BASE];
2838   address_word offset = EXTEND16 (OFFSET);
2839   {
2840     address_word vaddr = loadstore_ea (SD_, base, offset);
2841     address_word paddr;
2842     int uncached;
2843     {
2844       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2845         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2846     }
2847   }
2848 }
2849
2850
2851 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
2852 {
2853   unsigned64 result;
2854
2855   y &= 31;
2856   TRACE_ALU_INPUT2 (x, y);
2857   result = EXTEND32 (ROTR32 (x, y));
2858   TRACE_ALU_RESULT (result);
2859   return result;
2860 }
2861
2862 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
2863 "ror r<RD>, r<RT>, <SHIFT>"
2864 *mips32r2:
2865 *mips64r2:
2866 *vr5400:
2867 *vr5500:
2868 {
2869   GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
2870 }
2871
2872 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
2873 "rorv r<RD>, r<RT>, r<RS>"
2874 *mips32r2:
2875 *mips64r2:
2876 *vr5400:
2877 *vr5500:
2878 {
2879   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
2880 }
2881
2882
2883 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2884 {
2885   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2886   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2887   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2888   unsigned int byte;
2889   address_word paddr;
2890   int uncached;
2891   unsigned64 memval;
2892   address_word vaddr;
2893
2894   vaddr = loadstore_ea (SD_, base, offset);
2895   if ((vaddr & access) != 0)
2896     {
2897       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2898     }
2899   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2900   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2901   byte = ((vaddr & mask) ^ bigendiancpu);
2902   memval = (word << (8 * byte));
2903   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2904 }
2905
2906 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2907 {
2908   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2909   address_word reverseendian = (ReverseEndian ? -1 : 0);
2910   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2911   unsigned int byte;
2912   unsigned int word;
2913   address_word paddr;
2914   int uncached;
2915   unsigned64 memval;
2916   address_word vaddr;
2917   int nr_lhs_bits;
2918   int nr_rhs_bits;
2919
2920   vaddr = loadstore_ea (SD_, base, offset);
2921   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2922   paddr = (paddr ^ (reverseendian & mask));
2923   if (BigEndianMem == 0)
2924     paddr = paddr & ~access;
2925
2926   /* compute where within the word/mem we are */
2927   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2928   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2929   nr_lhs_bits = 8 * byte + 8;
2930   nr_rhs_bits = 8 * access - 8 * byte;
2931   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2932   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2933            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2934            (long) ((unsigned64) paddr >> 32), (long) paddr,
2935            word, byte, nr_lhs_bits, nr_rhs_bits); */
2936
2937   if (word == 0)
2938     {
2939       memval = (rt >> nr_rhs_bits);
2940     }
2941   else
2942     {
2943       memval = (rt << nr_lhs_bits);
2944     }
2945   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2946            (long) ((unsigned64) rt >> 32), (long) rt,
2947            (long) ((unsigned64) memval >> 32), (long) memval); */
2948   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2949 }
2950
2951 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2952 {
2953   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2954   address_word reverseendian = (ReverseEndian ? -1 : 0);
2955   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2956   unsigned int byte;
2957   address_word paddr;
2958   int uncached;
2959   unsigned64 memval;
2960   address_word vaddr;
2961
2962   vaddr = loadstore_ea (SD_, base, offset);
2963   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2964   paddr = (paddr ^ (reverseendian & mask));
2965   if (BigEndianMem != 0)
2966     paddr &= ~access;
2967   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2968   memval = (rt << (byte * 8));
2969   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2970 }
2971
2972
2973 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2974 "sb r<RT>, <OFFSET>(r<BASE>)"
2975 *mipsI:
2976 *mipsII:
2977 *mipsIII:
2978 *mipsIV:
2979 *mipsV:
2980 *mips32:
2981 *mips32r2:
2982 *mips64:
2983 *mips64r2:
2984 *vr4100:
2985 *vr5000:
2986 *r3900:
2987 {
2988   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2989 }
2990
2991
2992 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2993 "sc r<RT>, <OFFSET>(r<BASE>)"
2994 *mipsII:
2995 *mipsIII:
2996 *mipsIV:
2997 *mipsV:
2998 *mips32:
2999 *mips32r2:
3000 *mips64:
3001 *mips64r2:
3002 *vr4100:
3003 *vr5000:
3004 {
3005   unsigned32 instruction = instruction_0;
3006   address_word base = GPR[BASE];
3007   address_word offset = EXTEND16 (OFFSET);
3008   {
3009     address_word vaddr = loadstore_ea (SD_, base, offset);
3010     address_word paddr;
3011     int uncached;
3012     if ((vaddr & 3) != 0)
3013       {
3014         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3015       }
3016     else
3017       {
3018         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3019           {
3020             unsigned64 memval = 0;
3021             unsigned64 memval1 = 0;
3022             unsigned64 mask = 0x7;
3023             unsigned int byte;
3024             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3025             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3026             memval = ((unsigned64) GPR[RT] << (8 * byte));
3027             if (LLBIT)
3028               {
3029                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3030               }
3031             GPR[RT] = LLBIT;
3032           }
3033       }
3034   }
3035 }
3036
3037
3038 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3039 "scd r<RT>, <OFFSET>(r<BASE>)"
3040 *mipsIII:
3041 *mipsIV:
3042 *mipsV:
3043 *mips64:
3044 *mips64r2:
3045 *vr4100:
3046 *vr5000:
3047 {
3048   address_word base = GPR[BASE];
3049   address_word offset = EXTEND16 (OFFSET);
3050   check_u64 (SD_, instruction_0);
3051   {
3052     address_word vaddr = loadstore_ea (SD_, base, offset);
3053     address_word paddr;
3054     int uncached;
3055     if ((vaddr & 7) != 0)
3056       {
3057         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3058       }
3059     else
3060       {
3061         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3062           {
3063             unsigned64 memval = 0;
3064             unsigned64 memval1 = 0;
3065             memval = GPR[RT];
3066             if (LLBIT)
3067               {
3068                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3069               }
3070             GPR[RT] = LLBIT;
3071           }
3072       }
3073   }
3074 }
3075
3076
3077 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3078 "sd r<RT>, <OFFSET>(r<BASE>)"
3079 *mipsIII:
3080 *mipsIV:
3081 *mipsV:
3082 *mips64:
3083 *mips64r2:
3084 *vr4100:
3085 *vr5000:
3086 {
3087   check_u64 (SD_, instruction_0);
3088   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3089 }
3090
3091
3092 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3093 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3094 *mipsII:
3095 *mipsIII:
3096 *mipsIV:
3097 *mipsV:
3098 *mips32:
3099 *mips32r2:
3100 *mips64:
3101 *mips64r2:
3102 *vr4100:
3103 *vr5000:
3104 {
3105   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3106 }
3107
3108
3109 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3110 "sdl r<RT>, <OFFSET>(r<BASE>)"
3111 *mipsIII:
3112 *mipsIV:
3113 *mipsV:
3114 *mips64:
3115 *mips64r2:
3116 *vr4100:
3117 *vr5000:
3118 {
3119   check_u64 (SD_, instruction_0);
3120   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3121 }
3122
3123
3124 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3125 "sdr r<RT>, <OFFSET>(r<BASE>)"
3126 *mipsIII:
3127 *mipsIV:
3128 *mipsV:
3129 *mips64:
3130 *mips64r2:
3131 *vr4100:
3132 *vr5000:
3133 {
3134   check_u64 (SD_, instruction_0);
3135   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3136 }
3137
3138
3139
3140 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3141 "sh r<RT>, <OFFSET>(r<BASE>)"
3142 *mipsI:
3143 *mipsII:
3144 *mipsIII:
3145 *mipsIV:
3146 *mipsV:
3147 *mips32:
3148 *mips32r2:
3149 *mips64:
3150 *mips64r2:
3151 *vr4100:
3152 *vr5000:
3153 *r3900:
3154 {
3155   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3156 }
3157
3158
3159 :function:::void:do_sll:int rt, int rd, int shift
3160 {
3161   unsigned32 temp = (GPR[rt] << shift);
3162   TRACE_ALU_INPUT2 (GPR[rt], shift);
3163   GPR[rd] = EXTEND32 (temp);
3164   TRACE_ALU_RESULT (GPR[rd]);
3165 }
3166
3167 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
3168 "nop":RD == 0 && RT == 0 && SHIFT == 0
3169 "sll r<RD>, r<RT>, <SHIFT>"
3170 *mipsI:
3171 *mipsII:
3172 *mipsIII:
3173 *mipsIV:
3174 *mipsV:
3175 *vr4100:
3176 *vr5000:
3177 *r3900:
3178 {
3179   /* Skip shift for NOP, so that there won't be lots of extraneous
3180      trace output.  */
3181   if (RD != 0 || RT != 0 || SHIFT != 0)
3182     do_sll (SD_, RT, RD, SHIFT);
3183 }
3184
3185 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3186 "nop":RD == 0 && RT == 0 && SHIFT == 0
3187 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
3188 "sll r<RD>, r<RT>, <SHIFT>"
3189 *mips32:
3190 *mips32r2:
3191 *mips64:
3192 *mips64r2:
3193 {
3194   /* Skip shift for NOP and SSNOP, so that there won't be lots of
3195      extraneous trace output.  */
3196   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3197     do_sll (SD_, RT, RD, SHIFT);
3198 }
3199
3200
3201 :function:::void:do_sllv:int rs, int rt, int rd
3202 {
3203   int s = MASKED (GPR[rs], 4, 0);
3204   unsigned32 temp = (GPR[rt] << s);
3205   TRACE_ALU_INPUT2 (GPR[rt], s);
3206   GPR[rd] = EXTEND32 (temp);
3207   TRACE_ALU_RESULT (GPR[rd]);
3208 }
3209
3210 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
3211 "sllv r<RD>, r<RT>, r<RS>"
3212 *mipsI:
3213 *mipsII:
3214 *mipsIII:
3215 *mipsIV:
3216 *mipsV:
3217 *mips32:
3218 *mips32r2:
3219 *mips64:
3220 *mips64r2:
3221 *vr4100:
3222 *vr5000:
3223 *r3900:
3224 {
3225   do_sllv (SD_, RS, RT, RD);
3226 }
3227
3228
3229 :function:::void:do_slt:int rs, int rt, int rd
3230 {
3231   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3232   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3233   TRACE_ALU_RESULT (GPR[rd]);
3234 }
3235
3236 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
3237 "slt r<RD>, r<RS>, r<RT>"
3238 *mipsI:
3239 *mipsII:
3240 *mipsIII:
3241 *mipsIV:
3242 *mipsV:
3243 *mips32:
3244 *mips32r2:
3245 *mips64:
3246 *mips64r2:
3247 *vr4100:
3248 *vr5000:
3249 *r3900:
3250 {
3251   do_slt (SD_, RS, RT, RD);
3252 }
3253
3254
3255 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3256 {
3257   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3258   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3259   TRACE_ALU_RESULT (GPR[rt]);
3260 }
3261
3262 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3263 "slti r<RT>, r<RS>, <IMMEDIATE>"
3264 *mipsI:
3265 *mipsII:
3266 *mipsIII:
3267 *mipsIV:
3268 *mipsV:
3269 *mips32:
3270 *mips32r2:
3271 *mips64:
3272 *mips64r2:
3273 *vr4100:
3274 *vr5000:
3275 *r3900:
3276 {
3277   do_slti (SD_, RS, RT, IMMEDIATE);
3278 }
3279
3280
3281 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3282 {
3283   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3284   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3285   TRACE_ALU_RESULT (GPR[rt]);
3286 }
3287
3288 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3289 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3290 *mipsI:
3291 *mipsII:
3292 *mipsIII:
3293 *mipsIV:
3294 *mipsV:
3295 *mips32:
3296 *mips32r2:
3297 *mips64:
3298 *mips64r2:
3299 *vr4100:
3300 *vr5000:
3301 *r3900:
3302 {
3303   do_sltiu (SD_, RS, RT, IMMEDIATE);
3304 }
3305
3306
3307
3308 :function:::void:do_sltu:int rs, int rt, int rd
3309 {
3310   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3311   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3312   TRACE_ALU_RESULT (GPR[rd]);
3313 }
3314
3315 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3316 "sltu r<RD>, r<RS>, r<RT>"
3317 *mipsI:
3318 *mipsII:
3319 *mipsIII:
3320 *mipsIV:
3321 *mipsV:
3322 *mips32:
3323 *mips32r2:
3324 *mips64:
3325 *mips64r2:
3326 *vr4100:
3327 *vr5000:
3328 *r3900:
3329 {
3330   do_sltu (SD_, RS, RT, RD);
3331 }
3332
3333
3334 :function:::void:do_sra:int rt, int rd, int shift
3335 {
3336   signed32 temp = (signed32) GPR[rt] >> shift;
3337   if (NotWordValue (GPR[rt]))
3338     Unpredictable ();
3339   TRACE_ALU_INPUT2 (GPR[rt], shift);
3340   GPR[rd] = EXTEND32 (temp);
3341   TRACE_ALU_RESULT (GPR[rd]);
3342 }
3343
3344 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3345 "sra r<RD>, r<RT>, <SHIFT>"
3346 *mipsI:
3347 *mipsII:
3348 *mipsIII:
3349 *mipsIV:
3350 *mipsV:
3351 *mips32:
3352 *mips32r2:
3353 *mips64:
3354 *mips64r2:
3355 *vr4100:
3356 *vr5000:
3357 *r3900:
3358 {
3359   do_sra (SD_, RT, RD, SHIFT);
3360 }
3361
3362
3363
3364 :function:::void:do_srav:int rs, int rt, int rd
3365 {
3366   int s = MASKED (GPR[rs], 4, 0);
3367   signed32 temp = (signed32) GPR[rt] >> s;
3368   if (NotWordValue (GPR[rt]))
3369     Unpredictable ();
3370   TRACE_ALU_INPUT2 (GPR[rt], s);
3371   GPR[rd] = EXTEND32 (temp);
3372   TRACE_ALU_RESULT (GPR[rd]);
3373 }
3374
3375 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3376 "srav r<RD>, r<RT>, r<RS>"
3377 *mipsI:
3378 *mipsII:
3379 *mipsIII:
3380 *mipsIV:
3381 *mipsV:
3382 *mips32:
3383 *mips32r2:
3384 *mips64:
3385 *mips64r2:
3386 *vr4100:
3387 *vr5000:
3388 *r3900:
3389 {
3390   do_srav (SD_, RS, RT, RD);
3391 }
3392
3393
3394
3395 :function:::void:do_srl:int rt, int rd, int shift
3396 {
3397   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3398   if (NotWordValue (GPR[rt]))
3399     Unpredictable ();
3400   TRACE_ALU_INPUT2 (GPR[rt], shift);
3401   GPR[rd] = EXTEND32 (temp);
3402   TRACE_ALU_RESULT (GPR[rd]);
3403 }
3404
3405 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3406 "srl r<RD>, r<RT>, <SHIFT>"
3407 *mipsI:
3408 *mipsII:
3409 *mipsIII:
3410 *mipsIV:
3411 *mipsV:
3412 *mips32:
3413 *mips32r2:
3414 *mips64:
3415 *mips64r2:
3416 *vr4100:
3417 *vr5000:
3418 *r3900:
3419 {
3420   do_srl (SD_, RT, RD, SHIFT);
3421 }
3422
3423
3424 :function:::void:do_srlv:int rs, int rt, int rd
3425 {
3426   int s = MASKED (GPR[rs], 4, 0);
3427   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3428   if (NotWordValue (GPR[rt]))
3429     Unpredictable ();
3430   TRACE_ALU_INPUT2 (GPR[rt], s);
3431   GPR[rd] = EXTEND32 (temp);
3432   TRACE_ALU_RESULT (GPR[rd]);
3433 }
3434
3435 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3436 "srlv r<RD>, r<RT>, r<RS>"
3437 *mipsI:
3438 *mipsII:
3439 *mipsIII:
3440 *mipsIV:
3441 *mipsV:
3442 *mips32:
3443 *mips32r2:
3444 *mips64:
3445 *mips64r2:
3446 *vr4100:
3447 *vr5000:
3448 *r3900:
3449 {
3450   do_srlv (SD_, RS, RT, RD);
3451 }
3452
3453
3454 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3455 "sub r<RD>, r<RS>, r<RT>"
3456 *mipsI:
3457 *mipsII:
3458 *mipsIII:
3459 *mipsIV:
3460 *mipsV:
3461 *mips32:
3462 *mips32r2:
3463 *mips64:
3464 *mips64r2:
3465 *vr4100:
3466 *vr5000:
3467 *r3900:
3468 {
3469   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3470     Unpredictable ();
3471   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3472   {
3473     ALU32_BEGIN (GPR[RS]);
3474     ALU32_SUB (GPR[RT]);
3475     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3476   }
3477   TRACE_ALU_RESULT (GPR[RD]);
3478 }
3479
3480
3481 :function:::void:do_subu:int rs, int rt, int rd
3482 {
3483   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3484     Unpredictable ();
3485   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3486   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3487   TRACE_ALU_RESULT (GPR[rd]);
3488 }
3489
3490 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3491 "subu r<RD>, r<RS>, r<RT>"
3492 *mipsI:
3493 *mipsII:
3494 *mipsIII:
3495 *mipsIV:
3496 *mipsV:
3497 *mips32:
3498 *mips32r2:
3499 *mips64:
3500 *mips64r2:
3501 *vr4100:
3502 *vr5000:
3503 *r3900:
3504 {
3505   do_subu (SD_, RS, RT, RD);
3506 }
3507
3508
3509 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3510 "sw r<RT>, <OFFSET>(r<BASE>)"
3511 *mipsI:
3512 *mipsII:
3513 *mipsIII:
3514 *mipsIV:
3515 *mipsV:
3516 *mips32:
3517 *mips32r2:
3518 *mips64:
3519 *mips64r2:
3520 *vr4100:
3521 *r3900:
3522 *vr5000:
3523 {
3524   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3525 }
3526
3527
3528 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3529 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3530 *mipsI:
3531 *mipsII:
3532 *mipsIII:
3533 *mipsIV:
3534 *mipsV:
3535 *mips32:
3536 *mips32r2:
3537 *mips64:
3538 *mips64r2:
3539 *vr4100:
3540 *vr5000:
3541 *r3900:
3542 {
3543   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3544 }
3545
3546
3547 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3548 "swl r<RT>, <OFFSET>(r<BASE>)"
3549 *mipsI:
3550 *mipsII:
3551 *mipsIII:
3552 *mipsIV:
3553 *mipsV:
3554 *mips32:
3555 *mips32r2:
3556 *mips64:
3557 *mips64r2:
3558 *vr4100:
3559 *vr5000:
3560 *r3900:
3561 {
3562   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3563 }
3564
3565
3566 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3567 "swr r<RT>, <OFFSET>(r<BASE>)"
3568 *mipsI:
3569 *mipsII:
3570 *mipsIII:
3571 *mipsIV:
3572 *mipsV:
3573 *mips32:
3574 *mips32r2:
3575 *mips64:
3576 *mips64r2:
3577 *vr4100:
3578 *vr5000:
3579 *r3900:
3580 {
3581   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3582 }
3583
3584
3585 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3586 "sync":STYPE == 0
3587 "sync <STYPE>"
3588 *mipsII:
3589 *mipsIII:
3590 *mipsIV:
3591 *mipsV:
3592 *mips32:
3593 *mips32r2:
3594 *mips64:
3595 *mips64r2:
3596 *vr4100:
3597 *vr5000:
3598 *r3900:
3599 {
3600   SyncOperation (STYPE);
3601 }
3602
3603
3604 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3605 "syscall %#lx<CODE>"
3606 *mipsI:
3607 *mipsII:
3608 *mipsIII:
3609 *mipsIV:
3610 *mipsV:
3611 *mips32:
3612 *mips32r2:
3613 *mips64:
3614 *mips64r2:
3615 *vr4100:
3616 *vr5000:
3617 *r3900:
3618 {
3619   SignalException (SystemCall, instruction_0);
3620 }
3621
3622
3623 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3624 "teq r<RS>, r<RT>"
3625 *mipsII:
3626 *mipsIII:
3627 *mipsIV:
3628 *mipsV:
3629 *mips32:
3630 *mips32r2:
3631 *mips64:
3632 *mips64r2:
3633 *vr4100:
3634 *vr5000:
3635 {
3636   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3637     SignalException (Trap, instruction_0);
3638 }
3639
3640
3641 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3642 "teqi r<RS>, <IMMEDIATE>"
3643 *mipsII:
3644 *mipsIII:
3645 *mipsIV:
3646 *mipsV:
3647 *mips32:
3648 *mips32r2:
3649 *mips64:
3650 *mips64r2:
3651 *vr4100:
3652 *vr5000:
3653 {
3654   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3655     SignalException (Trap, instruction_0);
3656 }
3657
3658
3659 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3660 "tge r<RS>, r<RT>"
3661 *mipsII:
3662 *mipsIII:
3663 *mipsIV:
3664 *mipsV:
3665 *mips32:
3666 *mips32r2:
3667 *mips64:
3668 *mips64r2:
3669 *vr4100:
3670 *vr5000:
3671 {
3672   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3673     SignalException (Trap, instruction_0);
3674 }
3675
3676
3677 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3678 "tgei r<RS>, <IMMEDIATE>"
3679 *mipsII:
3680 *mipsIII:
3681 *mipsIV:
3682 *mipsV:
3683 *mips32:
3684 *mips32r2:
3685 *mips64:
3686 *mips64r2:
3687 *vr4100:
3688 *vr5000:
3689 {
3690   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3691     SignalException (Trap, instruction_0);
3692 }
3693
3694
3695 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3696 "tgeiu r<RS>, <IMMEDIATE>"
3697 *mipsII:
3698 *mipsIII:
3699 *mipsIV:
3700 *mipsV:
3701 *mips32:
3702 *mips32r2:
3703 *mips64:
3704 *mips64r2:
3705 *vr4100:
3706 *vr5000:
3707 {
3708   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3709     SignalException (Trap, instruction_0);
3710 }
3711
3712
3713 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3714 "tgeu r<RS>, r<RT>"
3715 *mipsII:
3716 *mipsIII:
3717 *mipsIV:
3718 *mipsV:
3719 *mips32:
3720 *mips32r2:
3721 *mips64:
3722 *mips64r2:
3723 *vr4100:
3724 *vr5000:
3725 {
3726   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3727     SignalException (Trap, instruction_0);
3728 }
3729
3730
3731 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3732 "tlt r<RS>, r<RT>"
3733 *mipsII:
3734 *mipsIII:
3735 *mipsIV:
3736 *mipsV:
3737 *mips32:
3738 *mips32r2:
3739 *mips64:
3740 *mips64r2:
3741 *vr4100:
3742 *vr5000:
3743 {
3744   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3745     SignalException (Trap, instruction_0);
3746 }
3747
3748
3749 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3750 "tlti r<RS>, <IMMEDIATE>"
3751 *mipsII:
3752 *mipsIII:
3753 *mipsIV:
3754 *mipsV:
3755 *mips32:
3756 *mips32r2:
3757 *mips64:
3758 *mips64r2:
3759 *vr4100:
3760 *vr5000:
3761 {
3762   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3763     SignalException (Trap, instruction_0);
3764 }
3765
3766
3767 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3768 "tltiu r<RS>, <IMMEDIATE>"
3769 *mipsII:
3770 *mipsIII:
3771 *mipsIV:
3772 *mipsV:
3773 *mips32:
3774 *mips32r2:
3775 *mips64:
3776 *mips64r2:
3777 *vr4100:
3778 *vr5000:
3779 {
3780   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3781     SignalException (Trap, instruction_0);
3782 }
3783
3784
3785 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3786 "tltu r<RS>, r<RT>"
3787 *mipsII:
3788 *mipsIII:
3789 *mipsIV:
3790 *mipsV:
3791 *mips32:
3792 *mips32r2:
3793 *mips64:
3794 *mips64r2:
3795 *vr4100:
3796 *vr5000:
3797 {
3798   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3799     SignalException (Trap, instruction_0);
3800 }
3801
3802
3803 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3804 "tne r<RS>, r<RT>"
3805 *mipsII:
3806 *mipsIII:
3807 *mipsIV:
3808 *mipsV:
3809 *mips32:
3810 *mips32r2:
3811 *mips64:
3812 *mips64r2:
3813 *vr4100:
3814 *vr5000:
3815 {
3816   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3817     SignalException (Trap, instruction_0);
3818 }
3819
3820
3821 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3822 "tnei r<RS>, <IMMEDIATE>"
3823 *mipsII:
3824 *mipsIII:
3825 *mipsIV:
3826 *mipsV:
3827 *mips32:
3828 *mips32r2:
3829 *mips64:
3830 *mips64r2:
3831 *vr4100:
3832 *vr5000:
3833 {
3834   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3835     SignalException (Trap, instruction_0);
3836 }
3837
3838
3839 :function:::void:do_xor:int rs, int rt, int rd
3840 {
3841   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3842   GPR[rd] = GPR[rs] ^ GPR[rt];
3843   TRACE_ALU_RESULT (GPR[rd]);
3844 }
3845
3846 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3847 "xor r<RD>, r<RS>, r<RT>"
3848 *mipsI:
3849 *mipsII:
3850 *mipsIII:
3851 *mipsIV:
3852 *mipsV:
3853 *mips32:
3854 *mips32r2:
3855 *mips64:
3856 *mips64r2:
3857 *vr4100:
3858 *vr5000:
3859 *r3900:
3860 {
3861   do_xor (SD_, RS, RT, RD);
3862 }
3863
3864
3865 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3866 {
3867   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3868   GPR[rt] = GPR[rs] ^ immediate;
3869   TRACE_ALU_RESULT (GPR[rt]);
3870 }
3871
3872 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3873 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3874 *mipsI:
3875 *mipsII:
3876 *mipsIII:
3877 *mipsIV:
3878 *mipsV:
3879 *mips32:
3880 *mips32r2:
3881 *mips64:
3882 *mips64r2:
3883 *vr4100:
3884 *vr5000:
3885 *r3900:
3886 {
3887   do_xori (SD_, RS, RT, IMMEDIATE);
3888 }
3889
3890 \f
3891 //
3892 // MIPS Architecture:
3893 //
3894 //        FPU Instruction Set (COP1 & COP1X)
3895 //
3896
3897
3898 :%s::::FMT:int fmt
3899 {
3900   switch (fmt)
3901     {
3902     case fmt_single: return "s";
3903     case fmt_double: return "d";
3904     case fmt_word: return "w";
3905     case fmt_long: return "l";
3906     case fmt_ps: return "ps";
3907     default: return "?";
3908     }
3909 }
3910
3911 :%s::::TF:int tf
3912 {
3913   if (tf)
3914     return "t";
3915   else
3916     return "f";
3917 }
3918
3919 :%s::::ND:int nd
3920 {
3921   if (nd)
3922     return "l";
3923   else
3924     return "";
3925 }
3926
3927 :%s::::COND:int cond
3928 {
3929   switch (cond)
3930     {
3931     case 00: return "f";
3932     case 01: return "un";
3933     case 02: return "eq";
3934     case 03: return "ueq";
3935     case 04: return "olt";
3936     case 05: return "ult";
3937     case 06: return "ole";
3938     case 07: return "ule";
3939     case 010: return "sf";
3940     case 011: return "ngle";
3941     case 012: return "seq";
3942     case 013: return "ngl";
3943     case 014: return "lt";
3944     case 015: return "nge";
3945     case 016: return "le";
3946     case 017: return "ngt";
3947     default: return "?";
3948     }
3949 }
3950
3951
3952 // Helpers:
3953 //
3954 // Check that the given FPU format is usable, and signal a
3955 // ReservedInstruction exception if not.
3956 //
3957
3958 // check_fmt_p checks that the format is single, double, or paired single.
3959 :function:::void:check_fmt_p:int fmt, instruction_word insn
3960 *mipsI:
3961 *mipsII:
3962 *mipsIII:
3963 *mipsIV:
3964 *mips32:
3965 *mips32r2:
3966 *vr4100:
3967 *vr5000:
3968 *r3900:
3969 {
3970   /* None of these ISAs support Paired Single, so just fall back to
3971      the single/double check.  */
3972   if ((fmt != fmt_single) && (fmt != fmt_double))
3973     SignalException (ReservedInstruction, insn);
3974 }
3975
3976 :function:::void:check_fmt_p:int fmt, instruction_word insn
3977 *mipsV:
3978 *mips64:
3979 *mips64r2:
3980 {
3981   if ((fmt != fmt_single) && (fmt != fmt_double)
3982       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3983     SignalException (ReservedInstruction, insn);
3984 }
3985
3986
3987 // Helper:
3988 //
3989 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3990 // exception if not.
3991 //
3992
3993 :function:::void:check_fpu:
3994 *mipsI:
3995 *mipsII:
3996 *mipsIII:
3997 *mipsIV:
3998 *mipsV:
3999 *mips32:
4000 *mips32r2:
4001 *mips64:
4002 *mips64r2:
4003 *vr4100:
4004 *vr5000:
4005 *r3900:
4006 {
4007   if (! COP_Usable (1))
4008     SignalExceptionCoProcessorUnusable (1);
4009 }
4010
4011
4012 // Helper:
4013 //
4014 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
4015 // or MIPS32.  do_load cannot be used instead because it returns an
4016 // unsigned_word, which is limited to the size of the machine's registers.
4017 //
4018
4019 :function:::unsigned64:do_load_double:address_word base, address_word offset
4020 *mipsII:
4021 *mips32:
4022 *mips32r2:
4023 {
4024   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4025   address_word vaddr;
4026   address_word paddr;
4027   int uncached;
4028   unsigned64 memval;
4029   unsigned64 v;
4030
4031   vaddr = loadstore_ea (SD_, base, offset);
4032   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4033     {
4034       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4035                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4036                        sim_core_unaligned_signal);
4037     }
4038   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4039                       isREAL);
4040   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4041               isDATA, isREAL);
4042   v = (unsigned64)memval;
4043   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4044               isDATA, isREAL);
4045   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4046 }
4047
4048
4049 // Helper:
4050 //
4051 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4052 // or MIPS32.  do_load cannot be used instead because it returns an
4053 // unsigned_word, which is limited to the size of the machine's registers.
4054 //
4055
4056 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4057 *mipsII:
4058 *mips32:
4059 *mips32r2:
4060 {
4061   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4062   address_word vaddr;
4063   address_word paddr;
4064   int uncached;
4065   unsigned64 memval;
4066
4067   vaddr = loadstore_ea (SD_, base, offset);
4068   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4069     {
4070       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4071                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4072                        sim_core_unaligned_signal);
4073     }
4074   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4075                       isREAL);
4076   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4077   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4078                isREAL);
4079   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4080   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4081                isREAL);
4082 }
4083
4084
4085 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4086 "abs.%s<FMT> f<FD>, f<FS>"
4087 *mipsI:
4088 *mipsII:
4089 *mipsIII:
4090 *mipsIV:
4091 *mipsV:
4092 *mips32:
4093 *mips32r2:
4094 *mips64:
4095 *mips64r2:
4096 *vr4100:
4097 *vr5000:
4098 *r3900:
4099 {
4100   int fmt = FMT;
4101   check_fpu (SD_);
4102   check_fmt_p (SD_, fmt, instruction_0);
4103   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
4104 }
4105
4106
4107
4108 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4109 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4110 *mipsI:
4111 *mipsII:
4112 *mipsIII:
4113 *mipsIV:
4114 *mipsV:
4115 *mips32:
4116 *mips32r2:
4117 *mips64:
4118 *mips64r2:
4119 *vr4100:
4120 *vr5000:
4121 *r3900:
4122 {
4123   int fmt = FMT;
4124   check_fpu (SD_);
4125   check_fmt_p (SD_, fmt, instruction_0);
4126   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4127 }
4128
4129
4130 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
4131 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4132 *mipsV:
4133 *mips64:
4134 *mips64r2:
4135 {
4136   unsigned64 fs;
4137   unsigned64 ft;
4138   unsigned64 fd;
4139   check_fpu (SD_);
4140   check_u64 (SD_, instruction_0);
4141   fs = ValueFPR (FS, fmt_ps);
4142   if ((GPR[RS] & 0x3) != 0)
4143     Unpredictable ();
4144   if ((GPR[RS] & 0x4) == 0)
4145     fd = fs;
4146   else
4147     {
4148       ft = ValueFPR (FT, fmt_ps);
4149       if (BigEndianCPU)
4150         fd = PackPS (PSLower (fs), PSUpper (ft));
4151       else
4152         fd = PackPS (PSLower (ft), PSUpper (fs));
4153     }
4154   StoreFPR (FD, fmt_ps, fd);
4155 }
4156
4157
4158 // BC1F
4159 // BC1FL
4160 // BC1T
4161 // BC1TL
4162
4163 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4164 "bc1%s<TF>%s<ND> <OFFSET>"
4165 *mipsI:
4166 *mipsII:
4167 *mipsIII:
4168 {
4169   check_fpu (SD_);
4170   TRACE_BRANCH_INPUT (PREVCOC1());
4171   if (PREVCOC1() == TF)
4172     {
4173       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4174       TRACE_BRANCH_RESULT (dest);
4175       DELAY_SLOT (dest);
4176     }
4177   else if (ND)
4178     {
4179       TRACE_BRANCH_RESULT (0);
4180       NULLIFY_NEXT_INSTRUCTION ();
4181     }
4182   else
4183     {
4184       TRACE_BRANCH_RESULT (NIA);
4185     }
4186 }
4187
4188 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4189 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4190 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4191 *mipsIV:
4192 *mipsV:
4193 *mips32:
4194 *mips32r2:
4195 *mips64:
4196 *mips64r2:
4197 #*vr4100:
4198 *vr5000:
4199 *r3900:
4200 {
4201   check_fpu (SD_);
4202   if (GETFCC(CC) == TF)
4203     {
4204       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4205       DELAY_SLOT (dest);
4206     }
4207   else if (ND)
4208     {
4209       NULLIFY_NEXT_INSTRUCTION ();
4210     }
4211 }
4212
4213
4214 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
4215 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4216 *mipsI:
4217 *mipsII:
4218 *mipsIII:
4219 {
4220   int fmt = FMT;
4221   check_fpu (SD_);
4222   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4223   TRACE_ALU_RESULT (ValueFCR (31));
4224 }
4225
4226 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
4227 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4228 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4229 *mipsIV:
4230 *mipsV:
4231 *mips32:
4232 *mips32r2:
4233 *mips64:
4234 *mips64r2:
4235 *vr4100:
4236 *vr5000:
4237 *r3900:
4238 {
4239   int fmt = FMT;
4240   check_fpu (SD_);
4241   check_fmt_p (SD_, fmt, instruction_0);
4242   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4243   TRACE_ALU_RESULT (ValueFCR (31));
4244 }
4245
4246
4247 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
4248 "ceil.l.%s<FMT> f<FD>, f<FS>"
4249 *mipsIII:
4250 *mipsIV:
4251 *mipsV:
4252 *mips64:
4253 *mips64r2:
4254 *vr4100:
4255 *vr5000:
4256 *r3900:
4257 {
4258   int fmt = FMT;
4259   check_fpu (SD_);
4260   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4261             fmt_long));
4262 }
4263
4264
4265 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
4266 "ceil.w.%s<FMT> f<FD>, f<FS>"
4267 *mipsII:
4268 *mipsIII:
4269 *mipsIV:
4270 *mipsV:
4271 *mips32:
4272 *mips32r2:
4273 *mips64:
4274 *mips64r2:
4275 *vr4100:
4276 *vr5000:
4277 *r3900:
4278 {
4279   int fmt = FMT;
4280   check_fpu (SD_);
4281   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4282             fmt_word));
4283 }
4284
4285
4286 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4287 "cfc1 r<RT>, f<FS>"
4288 *mipsI:
4289 *mipsII:
4290 *mipsIII:
4291 {
4292   check_fpu (SD_);
4293   if (FS == 0)
4294     PENDING_FILL (RT, EXTEND32 (FCR0));
4295   else if (FS == 31)
4296     PENDING_FILL (RT, EXTEND32 (FCR31));
4297   /* else NOP */
4298 }
4299
4300 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4301 "cfc1 r<RT>, f<FS>"
4302 *mipsIV:
4303 *vr4100:
4304 *vr5000:
4305 *r3900:
4306 {
4307   check_fpu (SD_);
4308   if (FS == 0 || FS == 31)
4309     {
4310       unsigned_word  fcr = ValueFCR (FS);
4311       TRACE_ALU_INPUT1 (fcr);
4312       GPR[RT] = fcr;
4313     }
4314   /* else NOP */
4315   TRACE_ALU_RESULT (GPR[RT]);
4316 }
4317
4318 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4319 "cfc1 r<RT>, f<FS>"
4320 *mipsV:
4321 *mips32:
4322 *mips32r2:
4323 *mips64:
4324 *mips64r2:
4325 {
4326   check_fpu (SD_);
4327   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4328     {
4329       unsigned_word  fcr = ValueFCR (FS);
4330       TRACE_ALU_INPUT1 (fcr);
4331       GPR[RT] = fcr;
4332     }
4333   /* else NOP */
4334   TRACE_ALU_RESULT (GPR[RT]);
4335 }
4336
4337 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4338 "ctc1 r<RT>, f<FS>"
4339 *mipsI:
4340 *mipsII:
4341 *mipsIII:
4342 {
4343   check_fpu (SD_);
4344   if (FS == 31)
4345     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4346   /* else NOP */
4347 }
4348
4349 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4350 "ctc1 r<RT>, f<FS>"
4351 *mipsIV:
4352 *vr4100:
4353 *vr5000:
4354 *r3900:
4355 {
4356   check_fpu (SD_);
4357   TRACE_ALU_INPUT1 (GPR[RT]);
4358   if (FS == 31)
4359     StoreFCR (FS, GPR[RT]);
4360   /* else NOP */
4361 }
4362
4363 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4364 "ctc1 r<RT>, f<FS>"
4365 *mipsV:
4366 *mips32:
4367 *mips32r2:
4368 *mips64:
4369 *mips64r2:
4370 {
4371   check_fpu (SD_);
4372   TRACE_ALU_INPUT1 (GPR[RT]);
4373   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4374       StoreFCR (FS, GPR[RT]);
4375   /* else NOP */
4376 }
4377
4378
4379 //
4380 // FIXME: Does not correctly differentiate between mips*
4381 //
4382 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4383 "cvt.d.%s<FMT> f<FD>, f<FS>"
4384 *mipsI:
4385 *mipsII:
4386 *mipsIII:
4387 *mipsIV:
4388 *mipsV:
4389 *mips32:
4390 *mips32r2:
4391 *mips64:
4392 *mips64r2:
4393 *vr4100:
4394 *vr5000:
4395 *r3900:
4396 {
4397   int fmt = FMT;
4398   check_fpu (SD_);
4399   if ((fmt == fmt_double) | 0)
4400     SignalException (ReservedInstruction, instruction_0);
4401   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4402             fmt_double));
4403 }
4404
4405
4406 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4407 "cvt.l.%s<FMT> f<FD>, f<FS>"
4408 *mipsIII:
4409 *mipsIV:
4410 *mipsV:
4411 *mips64:
4412 *mips64r2:
4413 *vr4100:
4414 *vr5000:
4415 *r3900:
4416 {
4417   int fmt = FMT;
4418   check_fpu (SD_);
4419   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4420     SignalException (ReservedInstruction, instruction_0);
4421   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4422             fmt_long));
4423 }
4424
4425
4426 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4427 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4428 *mipsV:
4429 *mips64:
4430 *mips64r2:
4431 {
4432   check_fpu (SD_);
4433   check_u64 (SD_, instruction_0);
4434   StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4435                                 ValueFPR (FT, fmt_single)));
4436 }
4437
4438
4439 //
4440 // FIXME: Does not correctly differentiate between mips*
4441 //
4442 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4443 "cvt.s.%s<FMT> f<FD>, f<FS>"
4444 *mipsI:
4445 *mipsII:
4446 *mipsIII:
4447 *mipsIV:
4448 *mipsV:
4449 *mips32:
4450 *mips32r2:
4451 *mips64:
4452 *mips64r2:
4453 *vr4100:
4454 *vr5000:
4455 *r3900:
4456 {
4457   int fmt = FMT;
4458   check_fpu (SD_);
4459   if ((fmt == fmt_single) | 0)
4460     SignalException (ReservedInstruction, instruction_0);
4461   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4462             fmt_single));
4463 }
4464
4465
4466 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4467 "cvt.s.pl f<FD>, f<FS>"
4468 *mipsV:
4469 *mips64:
4470 *mips64r2:
4471 {
4472   check_fpu (SD_);
4473   check_u64 (SD_, instruction_0);
4474   StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4475 }
4476
4477
4478 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4479 "cvt.s.pu f<FD>, f<FS>"
4480 *mipsV:
4481 *mips64:
4482 *mips64r2:
4483 {
4484   check_fpu (SD_);
4485   check_u64 (SD_, instruction_0);
4486   StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4487 }
4488
4489
4490 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4491 "cvt.w.%s<FMT> f<FD>, f<FS>"
4492 *mipsI:
4493 *mipsII:
4494 *mipsIII:
4495 *mipsIV:
4496 *mipsV:
4497 *mips32:
4498 *mips32r2:
4499 *mips64:
4500 *mips64r2:
4501 *vr4100:
4502 *vr5000:
4503 *r3900:
4504 {
4505   int fmt = FMT;
4506   check_fpu (SD_);
4507   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4508     SignalException (ReservedInstruction, instruction_0);
4509   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4510             fmt_word));
4511 }
4512
4513
4514 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4515 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4516 *mipsI:
4517 *mipsII:
4518 *mipsIII:
4519 *mipsIV:
4520 *mipsV:
4521 *mips32:
4522 *mips32r2:
4523 *mips64:
4524 *mips64r2:
4525 *vr4100:
4526 *vr5000:
4527 *r3900:
4528 {
4529   int fmt = FMT;
4530   check_fpu (SD_);
4531   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4532 }
4533
4534
4535 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4536 "dmfc1 r<RT>, f<FS>"
4537 *mipsIII:
4538 {
4539   unsigned64 v;
4540   check_fpu (SD_);
4541   check_u64 (SD_, instruction_0);
4542   if (SizeFGR () == 64)
4543     v = FGR[FS];
4544   else if ((FS & 0x1) == 0)
4545     v = SET64HI (FGR[FS+1]) | FGR[FS];
4546   else
4547     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4548   PENDING_FILL (RT, v);
4549   TRACE_ALU_RESULT (v);
4550 }
4551
4552 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4553 "dmfc1 r<RT>, f<FS>"
4554 *mipsIV:
4555 *mipsV:
4556 *mips64:
4557 *mips64r2:
4558 *vr4100:
4559 *vr5000:
4560 *r3900:
4561 {
4562   check_fpu (SD_);
4563   check_u64 (SD_, instruction_0);
4564   if (SizeFGR () == 64)
4565     GPR[RT] = FGR[FS];
4566   else if ((FS & 0x1) == 0)
4567     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4568   else
4569     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4570   TRACE_ALU_RESULT (GPR[RT]);
4571 }
4572
4573
4574 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4575 "dmtc1 r<RT>, f<FS>"
4576 *mipsIII:
4577 {
4578   unsigned64 v;
4579   check_fpu (SD_);
4580   check_u64 (SD_, instruction_0);
4581   if (SizeFGR () == 64)
4582     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4583   else if ((FS & 0x1) == 0)
4584     {
4585       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4586       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4587     }
4588   else
4589     Unpredictable ();
4590   TRACE_FP_RESULT (GPR[RT]);
4591 }
4592
4593 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4594 "dmtc1 r<RT>, f<FS>"
4595 *mipsIV:
4596 *mipsV:
4597 *mips64:
4598 *mips64r2:
4599 *vr4100:
4600 *vr5000:
4601 *r3900:
4602 {
4603   check_fpu (SD_);
4604   check_u64 (SD_, instruction_0);
4605   if (SizeFGR () == 64)
4606     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4607   else if ((FS & 0x1) == 0)
4608     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4609   else
4610     Unpredictable ();
4611 }
4612
4613
4614 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4615 "floor.l.%s<FMT> f<FD>, f<FS>"
4616 *mipsIII:
4617 *mipsIV:
4618 *mipsV:
4619 *mips64:
4620 *mips64r2:
4621 *vr4100:
4622 *vr5000:
4623 *r3900:
4624 {
4625   int fmt = FMT;
4626   check_fpu (SD_);
4627   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4628             fmt_long));
4629 }
4630
4631
4632 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4633 "floor.w.%s<FMT> f<FD>, f<FS>"
4634 *mipsII:
4635 *mipsIII:
4636 *mipsIV:
4637 *mipsV:
4638 *mips32:
4639 *mips32r2:
4640 *mips64:
4641 *mips64r2:
4642 *vr4100:
4643 *vr5000:
4644 *r3900:
4645 {
4646   int fmt = FMT;
4647   check_fpu (SD_);
4648   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4649             fmt_word));
4650 }
4651
4652
4653 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4654 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4655 *mipsII:
4656 *mips32:
4657 *mips32r2:
4658 {
4659   check_fpu (SD_);
4660   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4661 }
4662
4663
4664 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4665 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4666 *mipsIII:
4667 *mipsIV:
4668 *mipsV:
4669 *mips64:
4670 *mips64r2:
4671 *vr4100:
4672 *vr5000:
4673 *r3900:
4674 {
4675   check_fpu (SD_);
4676   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4677 }
4678
4679
4680 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4681 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4682 *mipsIV:
4683 *mipsV:
4684 *mips64:
4685 *mips64r2:
4686 *vr5000:
4687 {
4688   check_fpu (SD_);
4689   check_u64 (SD_, instruction_0);
4690   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4691 }
4692
4693
4694 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4695 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4696 *mipsV:
4697 *mips64:
4698 *mips64r2:
4699 {
4700   address_word base = GPR[BASE];
4701   address_word index = GPR[INDEX];
4702   address_word vaddr = base + index;
4703   check_fpu (SD_);
4704   check_u64 (SD_, instruction_0);
4705   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
4706   if ((vaddr & 0x7) != 0)
4707     index -= (vaddr & 0x7);
4708   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4709 }
4710
4711
4712 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4713 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4714 *mipsI:
4715 *mipsII:
4716 *mipsIII:
4717 *mipsIV:
4718 *mipsV:
4719 *mips32:
4720 *mips32r2:
4721 *mips64:
4722 *mips64r2:
4723 *vr4100:
4724 *vr5000:
4725 *r3900:
4726 {
4727   check_fpu (SD_);
4728   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4729 }
4730
4731
4732 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4733 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4734 *mipsIV:
4735 *mipsV:
4736 *mips64:
4737 *mips64r2:
4738 *vr5000:
4739 {
4740   check_fpu (SD_);
4741   check_u64 (SD_, instruction_0);
4742   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4743 }
4744
4745
4746
4747 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
4748 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4749 *mipsIV:
4750 *mipsV:
4751 *mips64:
4752 *mips64r2:
4753 *vr5000:
4754 {
4755   int fmt = FMT;
4756   check_fpu (SD_);
4757   check_u64 (SD_, instruction_0);
4758   check_fmt_p (SD_, fmt, instruction_0);
4759   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4760                                   ValueFPR (FR, fmt), fmt));
4761 }
4762
4763
4764 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4765 "mfc1 r<RT>, f<FS>"
4766 *mipsI:
4767 *mipsII:
4768 *mipsIII:
4769 {
4770   unsigned64 v;
4771   check_fpu (SD_);
4772   v = EXTEND32 (FGR[FS]);
4773   PENDING_FILL (RT, v);
4774   TRACE_ALU_RESULT (v);
4775 }
4776
4777 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4778 "mfc1 r<RT>, f<FS>"
4779 *mipsIV:
4780 *mipsV:
4781 *mips32:
4782 *mips32r2:
4783 *mips64:
4784 *mips64r2:
4785 *vr4100:
4786 *vr5000:
4787 *r3900:
4788 {
4789   check_fpu (SD_);
4790   GPR[RT] = EXTEND32 (FGR[FS]);
4791   TRACE_ALU_RESULT (GPR[RT]);
4792 }
4793
4794
4795 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4796 "mov.%s<FMT> f<FD>, f<FS>"
4797 *mipsI:
4798 *mipsII:
4799 *mipsIII:
4800 *mipsIV:
4801 *mipsV:
4802 *mips32:
4803 *mips32r2:
4804 *mips64:
4805 *mips64r2:
4806 *vr4100:
4807 *vr5000:
4808 *r3900:
4809 {
4810   int fmt = FMT;
4811   check_fpu (SD_);
4812   check_fmt_p (SD_, fmt, instruction_0);
4813   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4814 }
4815
4816
4817 // MOVF
4818 // MOVT
4819 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4820 "mov%s<TF> r<RD>, r<RS>, <CC>"
4821 *mipsIV:
4822 *mipsV:
4823 *mips32:
4824 *mips32r2:
4825 *mips64:
4826 *mips64r2:
4827 *vr5000:
4828 {
4829   check_fpu (SD_);
4830   if (GETFCC(CC) == TF)
4831     GPR[RD] = GPR[RS];
4832 }
4833
4834
4835 // MOVF.fmt
4836 // MOVT.fmt
4837 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4838 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4839 *mipsIV:
4840 *mipsV:
4841 *mips32:
4842 *mips32r2:
4843 *mips64:
4844 *mips64r2:
4845 *vr5000:
4846 {
4847   int fmt = FMT;
4848   check_fpu (SD_);
4849   if (fmt != fmt_ps)
4850     {
4851       if (GETFCC(CC) == TF)
4852         StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4853       else
4854         StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
4855     }
4856   else
4857     {
4858       unsigned64 fd;
4859       fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4860                                       fmt_ps)),
4861                    PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4862                                       fmt_ps)));
4863       StoreFPR (FD, fmt_ps, fd);
4864     }
4865 }
4866
4867
4868 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4869 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4870 *mipsIV:
4871 *mipsV:
4872 *mips32:
4873 *mips32r2:
4874 *mips64:
4875 *mips64r2:
4876 *vr5000:
4877 {
4878   check_fpu (SD_);
4879   if (GPR[RT] != 0)
4880     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4881   else
4882     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4883 }
4884
4885
4886 // MOVT see MOVtf
4887
4888
4889 // MOVT.fmt see MOVtf.fmt
4890
4891
4892
4893 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4894 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4895 *mipsIV:
4896 *mipsV:
4897 *mips32:
4898 *mips32r2:
4899 *mips64:
4900 *mips64r2:
4901 *vr5000:
4902 {
4903   check_fpu (SD_);
4904   if (GPR[RT] == 0)
4905     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4906   else
4907     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4908 }
4909
4910
4911 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
4912 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4913 *mipsIV:
4914 *mipsV:
4915 *mips64:
4916 *mips64r2:
4917 *vr5000:
4918 {
4919   int fmt = FMT;
4920   check_fpu (SD_);
4921   check_u64 (SD_, instruction_0);
4922   check_fmt_p (SD_, fmt, instruction_0);
4923   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4924                                   ValueFPR (FR, fmt), fmt));
4925 }
4926
4927
4928 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4929 "mtc1 r<RT>, f<FS>"
4930 *mipsI:
4931 *mipsII:
4932 *mipsIII:
4933 {
4934   check_fpu (SD_);
4935   if (SizeFGR () == 64)
4936     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4937   else
4938     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4939   TRACE_FP_RESULT (GPR[RT]);
4940 }
4941
4942 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4943 "mtc1 r<RT>, f<FS>"
4944 *mipsIV:
4945 *mipsV:
4946 *mips32:
4947 *mips32r2:
4948 *mips64:
4949 *mips64r2:
4950 *vr4100:
4951 *vr5000:
4952 *r3900:
4953 {
4954   check_fpu (SD_);
4955   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4956 }
4957
4958
4959 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4960 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4961 *mipsI:
4962 *mipsII:
4963 *mipsIII:
4964 *mipsIV:
4965 *mipsV:
4966 *mips32:
4967 *mips32r2:
4968 *mips64:
4969 *mips64r2:
4970 *vr4100:
4971 *vr5000:
4972 *r3900:
4973 {
4974   int fmt = FMT;
4975   check_fpu (SD_);
4976   check_fmt_p (SD_, fmt, instruction_0);
4977   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4978 }
4979
4980
4981 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4982 "neg.%s<FMT> f<FD>, f<FS>"
4983 *mipsI:
4984 *mipsII:
4985 *mipsIII:
4986 *mipsIV:
4987 *mipsV:
4988 *mips32:
4989 *mips32r2:
4990 *mips64:
4991 *mips64r2:
4992 *vr4100:
4993 *vr5000:
4994 *r3900:
4995 {
4996   int fmt = FMT;
4997   check_fpu (SD_);
4998   check_fmt_p (SD_, fmt, instruction_0);
4999   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
5000 }
5001
5002
5003 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
5004 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5005 *mipsIV:
5006 *mipsV:
5007 *mips64:
5008 *mips64r2:
5009 *vr5000:
5010 {
5011   int fmt = FMT;
5012   check_fpu (SD_);
5013   check_u64 (SD_, instruction_0);
5014   check_fmt_p (SD_, fmt, instruction_0);
5015   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5016                                      ValueFPR (FR, fmt), fmt));
5017 }
5018
5019
5020 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
5021 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5022 *mipsIV:
5023 *mipsV:
5024 *mips64:
5025 *mips64r2:
5026 *vr5000:
5027 {
5028   int fmt = FMT;
5029   check_fpu (SD_);
5030   check_u64 (SD_, instruction_0);
5031   check_fmt_p (SD_, fmt, instruction_0);
5032   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5033                                      ValueFPR (FR, fmt), fmt));
5034 }
5035
5036
5037 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
5038 "pll.ps f<FD>, f<FS>, f<FT>"
5039 *mipsV:
5040 *mips64:
5041 *mips64r2:
5042 {
5043   check_fpu (SD_);
5044   check_u64 (SD_, instruction_0);
5045   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5046                                 PSLower (ValueFPR (FT, fmt_ps))));
5047 }
5048
5049
5050 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
5051 "plu.ps f<FD>, f<FS>, f<FT>"
5052 *mipsV:
5053 *mips64:
5054 *mips64r2:
5055 {
5056   check_fpu (SD_);
5057   check_u64 (SD_, instruction_0);
5058   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5059                                 PSUpper (ValueFPR (FT, fmt_ps))));
5060 }
5061
5062
5063 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
5064 "prefx <HINT>, r<INDEX>(r<BASE>)"
5065 *mipsIV:
5066 *mipsV:
5067 *mips64:
5068 *mips64r2:
5069 *vr5000:
5070 {
5071   address_word base = GPR[BASE];
5072   address_word index = GPR[INDEX];
5073   {
5074     address_word vaddr = loadstore_ea (SD_, base, index);
5075     address_word paddr;
5076     int uncached;
5077     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5078       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
5079   }
5080 }
5081
5082
5083 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
5084 "pul.ps f<FD>, f<FS>, f<FT>"
5085 *mipsV:
5086 *mips64:
5087 *mips64r2:
5088 {
5089   check_fpu (SD_);
5090   check_u64 (SD_, instruction_0);
5091   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5092                                 PSLower (ValueFPR (FT, fmt_ps))));
5093 }
5094
5095
5096 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
5097 "puu.ps f<FD>, f<FS>, f<FT>"
5098 *mipsV:
5099 *mips64:
5100 *mips64r2:
5101 {
5102   check_fpu (SD_);
5103   check_u64 (SD_, instruction_0);
5104   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5105                                 PSUpper (ValueFPR (FT, fmt_ps))));
5106 }
5107
5108
5109 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
5110 "recip.%s<FMT> f<FD>, f<FS>"
5111 *mipsIV:
5112 *mipsV:
5113 *mips64:
5114 *mips64r2:
5115 *vr5000:
5116 {
5117   int fmt = FMT;
5118   check_fpu (SD_);
5119   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
5120 }
5121
5122
5123 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
5124 "round.l.%s<FMT> f<FD>, f<FS>"
5125 *mipsIII:
5126 *mipsIV:
5127 *mipsV:
5128 *mips64:
5129 *mips64r2:
5130 *vr4100:
5131 *vr5000:
5132 *r3900:
5133 {
5134   int fmt = FMT;
5135   check_fpu (SD_);
5136   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5137             fmt_long));
5138 }
5139
5140
5141 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
5142 "round.w.%s<FMT> f<FD>, f<FS>"
5143 *mipsII:
5144 *mipsIII:
5145 *mipsIV:
5146 *mipsV:
5147 *mips32:
5148 *mips32r2:
5149 *mips64:
5150 *mips64r2:
5151 *vr4100:
5152 *vr5000:
5153 *r3900:
5154 {
5155   int fmt = FMT;
5156   check_fpu (SD_);
5157   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5158             fmt_word));
5159 }
5160
5161
5162 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
5163 "rsqrt.%s<FMT> f<FD>, f<FS>"
5164 *mipsIV:
5165 *mipsV:
5166 *mips64:
5167 *mips64r2:
5168 *vr5000:
5169 {
5170   int fmt = FMT;
5171   check_fpu (SD_);
5172   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
5173 }
5174
5175
5176 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
5177 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5178 *mipsII:
5179 *mips32:
5180 *mips32r2:
5181 {
5182   check_fpu (SD_);
5183   do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5184 }
5185
5186
5187 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5188 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5189 *mipsIII:
5190 *mipsIV:
5191 *mipsV:
5192 *mips64:
5193 *mips64r2:
5194 *vr4100:
5195 *vr5000:
5196 *r3900:
5197 {
5198   check_fpu (SD_);
5199   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5200 }
5201
5202
5203 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
5204 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5205 *mipsIV:
5206 *mipsV:
5207 *mips64:
5208 *mips64r2:
5209 *vr5000:
5210 {
5211   check_fpu (SD_);
5212   check_u64 (SD_, instruction_0);
5213   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5214 }
5215
5216
5217 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5218 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5219 *mipsV:
5220 *mips64:
5221 *mips64r2:
5222 {
5223   unsigned64 v;
5224   address_word base = GPR[BASE];
5225   address_word index = GPR[INDEX];
5226   address_word vaddr = base + index;
5227   check_fpu (SD_);
5228   check_u64 (SD_, instruction_0);
5229   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
5230   if ((vaddr & 0x7) != 0)
5231     index -= (vaddr & 0x7);
5232   do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5233 }
5234
5235
5236 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
5237 "sqrt.%s<FMT> f<FD>, f<FS>"
5238 *mipsII:
5239 *mipsIII:
5240 *mipsIV:
5241 *mipsV:
5242 *mips32:
5243 *mips32r2:
5244 *mips64:
5245 *mips64r2:
5246 *vr4100:
5247 *vr5000:
5248 *r3900:
5249 {
5250   int fmt = FMT;
5251   check_fpu (SD_);
5252   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
5253 }
5254
5255
5256 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
5257 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5258 *mipsI:
5259 *mipsII:
5260 *mipsIII:
5261 *mipsIV:
5262 *mipsV:
5263 *mips32:
5264 *mips32r2:
5265 *mips64:
5266 *mips64r2:
5267 *vr4100:
5268 *vr5000:
5269 *r3900:
5270 {
5271   int fmt = FMT;
5272   check_fpu (SD_);
5273   check_fmt_p (SD_, fmt, instruction_0);
5274   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5275 }
5276
5277
5278
5279 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
5280 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5281 *mipsI:
5282 *mipsII:
5283 *mipsIII:
5284 *mipsIV:
5285 *mipsV:
5286 *mips32:
5287 *mips32r2:
5288 *mips64:
5289 *mips64r2:
5290 *vr4100:
5291 *vr5000:
5292 *r3900:
5293 {
5294   address_word base = GPR[BASE];
5295   address_word offset = EXTEND16 (OFFSET);
5296   check_fpu (SD_);
5297   {
5298     address_word vaddr = loadstore_ea (SD_, base, offset);
5299     address_word paddr;
5300     int uncached;
5301     if ((vaddr & 3) != 0)
5302       {
5303         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5304       }
5305     else
5306       {
5307         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5308           {
5309             uword64 memval = 0;
5310             uword64 memval1 = 0;
5311             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5312             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5313             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5314             unsigned int byte;
5315             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5316             byte = ((vaddr & mask) ^ bigendiancpu);
5317             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
5318             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5319           }
5320       }
5321   }
5322 }
5323
5324
5325 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
5326 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5327 *mipsIV:
5328 *mipsV:
5329 *mips64:
5330 *mips64r2:
5331 *vr5000:
5332 {
5333
5334   address_word base = GPR[BASE];
5335   address_word index = GPR[INDEX];
5336   check_fpu (SD_);
5337   check_u64 (SD_, instruction_0);
5338   {
5339    address_word vaddr = loadstore_ea (SD_, base, index);
5340    address_word paddr;
5341    int uncached;
5342    if ((vaddr & 3) != 0)
5343      {
5344        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5345      }
5346    else
5347    {
5348     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5349     {
5350      unsigned64 memval = 0;
5351      unsigned64 memval1 = 0;
5352      unsigned64 mask = 0x7;
5353      unsigned int byte;
5354      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5355      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5356      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
5357       {
5358        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5359       }
5360     }
5361    }
5362   }
5363 }
5364
5365
5366 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
5367 "trunc.l.%s<FMT> f<FD>, f<FS>"
5368 *mipsIII:
5369 *mipsIV:
5370 *mipsV:
5371 *mips64:
5372 *mips64r2:
5373 *vr4100:
5374 *vr5000:
5375 *r3900:
5376 {
5377   int fmt = FMT;
5378   check_fpu (SD_);
5379   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5380             fmt_long));
5381 }
5382
5383
5384 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
5385 "trunc.w.%s<FMT> f<FD>, f<FS>"
5386 *mipsII:
5387 *mipsIII:
5388 *mipsIV:
5389 *mipsV:
5390 *mips32:
5391 *mips32r2:
5392 *mips64:
5393 *mips64r2:
5394 *vr4100:
5395 *vr5000:
5396 *r3900:
5397 {
5398   int fmt = FMT;
5399   check_fpu (SD_);
5400   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5401             fmt_word));
5402 }
5403
5404 \f
5405 //
5406 // MIPS Architecture:
5407 //
5408 //        System Control Instruction Set (COP0)
5409 //
5410
5411
5412 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5413 "bc0f <OFFSET>"
5414 *mipsI:
5415 *mipsII:
5416 *mipsIII:
5417 *mipsIV:
5418 *mipsV:
5419 *mips32:
5420 *mips32r2:
5421 *mips64:
5422 *mips64r2:
5423 *vr4100:
5424 *vr5000:
5425
5426 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5427 "bc0f <OFFSET>"
5428 // stub needed for eCos as tx39 hardware bug workaround
5429 *r3900:
5430 {
5431   /* do nothing */
5432 }
5433
5434
5435 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5436 "bc0fl <OFFSET>"
5437 *mipsI:
5438 *mipsII:
5439 *mipsIII:
5440 *mipsIV:
5441 *mipsV:
5442 *mips32:
5443 *mips32r2:
5444 *mips64:
5445 *mips64r2:
5446 *vr4100:
5447 *vr5000:
5448
5449
5450 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5451 "bc0t <OFFSET>"
5452 *mipsI:
5453 *mipsII:
5454 *mipsIII:
5455 *mipsIV:
5456 *mipsV:
5457 *mips32:
5458 *mips32r2:
5459 *mips64:
5460 *mips64r2:
5461 *vr4100:
5462
5463
5464 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5465 "bc0tl <OFFSET>"
5466 *mipsI:
5467 *mipsII:
5468 *mipsIII:
5469 *mipsIV:
5470 *mipsV:
5471 *mips32:
5472 *mips32r2:
5473 *mips64:
5474 *mips64r2:
5475 *vr4100:
5476 *vr5000:
5477
5478
5479 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5480 "cache <OP>, <OFFSET>(r<BASE>)"
5481 *mipsIII:
5482 *mipsIV:
5483 *mipsV:
5484 *mips32:
5485 *mips32r2:
5486 *mips64:
5487 *mips64r2:
5488 *vr4100:
5489 *vr5000:
5490 *r3900:
5491 {
5492   address_word base = GPR[BASE];
5493   address_word offset = EXTEND16 (OFFSET);
5494   {
5495     address_word vaddr = loadstore_ea (SD_, base, offset);
5496     address_word paddr;
5497     int uncached;
5498     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5499       CacheOp(OP,vaddr,paddr,instruction_0);
5500   }
5501 }
5502
5503
5504 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5505 "dmfc0 r<RT>, r<RD>"
5506 *mipsIII:
5507 *mipsIV:
5508 *mipsV:
5509 *mips64:
5510 *mips64r2:
5511 {
5512   check_u64 (SD_, instruction_0);
5513   DecodeCoproc (instruction_0);
5514 }
5515
5516
5517 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5518 "dmtc0 r<RT>, r<RD>"
5519 *mipsIII:
5520 *mipsIV:
5521 *mipsV:
5522 *mips64:
5523 *mips64r2:
5524 {
5525   check_u64 (SD_, instruction_0);
5526   DecodeCoproc (instruction_0);
5527 }
5528
5529
5530 010000,1,0000000000000000000,011000:COP0:32::ERET
5531 "eret"
5532 *mipsIII:
5533 *mipsIV:
5534 *mipsV:
5535 *mips32:
5536 *mips32r2:
5537 *mips64:
5538 *mips64r2:
5539 *vr4100:
5540 *vr5000:
5541 {
5542   if (SR & status_ERL)
5543     {
5544       /* Oops, not yet available */
5545       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5546       NIA = EPC;
5547       SR &= ~status_ERL;
5548     }
5549   else
5550     {
5551       NIA = EPC;
5552       SR &= ~status_EXL;
5553     }
5554 }
5555
5556
5557 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5558 "mfc0 r<RT>, r<RD> # <REGX>"
5559 *mipsI:
5560 *mipsII:
5561 *mipsIII:
5562 *mipsIV:
5563 *mipsV:
5564 *mips32:
5565 *mips32r2:
5566 *mips64:
5567 *mips64r2:
5568 *vr4100:
5569 *vr5000:
5570 *r3900:
5571 {
5572   TRACE_ALU_INPUT0 ();
5573   DecodeCoproc (instruction_0);
5574   TRACE_ALU_RESULT (GPR[RT]);
5575 }
5576
5577 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5578 "mtc0 r<RT>, r<RD> # <REGX>"
5579 *mipsI:
5580 *mipsII:
5581 *mipsIII:
5582 *mipsIV:
5583 *mipsV:
5584 *mips32:
5585 *mips32r2:
5586 *mips64:
5587 *mips64r2:
5588 *vr4100:
5589 *vr5000:
5590 *r3900:
5591 {
5592   DecodeCoproc (instruction_0);
5593 }
5594
5595
5596 010000,1,0000000000000000000,010000:COP0:32::RFE
5597 "rfe"
5598 *mipsI:
5599 *mipsII:
5600 *mipsIII:
5601 *mipsIV:
5602 *mipsV:
5603 *vr4100:
5604 *vr5000:
5605 *r3900:
5606 {
5607   DecodeCoproc (instruction_0);
5608 }
5609
5610
5611 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5612 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5613 *mipsI:
5614 *mipsII:
5615 *mipsIII:
5616 *mipsIV:
5617 *mipsV:
5618 *mips32:
5619 *mips32r2:
5620 *mips64:
5621 *mips64r2:
5622 *vr4100:
5623 *r3900:
5624 {
5625   DecodeCoproc (instruction_0);
5626 }
5627
5628
5629
5630 010000,1,0000000000000000000,001000:COP0:32::TLBP
5631 "tlbp"
5632 *mipsI:
5633 *mipsII:
5634 *mipsIII:
5635 *mipsIV:
5636 *mipsV:
5637 *mips32:
5638 *mips32r2:
5639 *mips64:
5640 *mips64r2:
5641 *vr4100:
5642 *vr5000:
5643
5644
5645 010000,1,0000000000000000000,000001:COP0:32::TLBR
5646 "tlbr"
5647 *mipsI:
5648 *mipsII:
5649 *mipsIII:
5650 *mipsIV:
5651 *mipsV:
5652 *mips32:
5653 *mips32r2:
5654 *mips64:
5655 *mips64r2:
5656 *vr4100:
5657 *vr5000:
5658
5659
5660 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5661 "tlbwi"
5662 *mipsI:
5663 *mipsII:
5664 *mipsIII:
5665 *mipsIV:
5666 *mipsV:
5667 *mips32:
5668 *mips32r2:
5669 *mips64:
5670 *mips64r2:
5671 *vr4100:
5672 *vr5000:
5673
5674
5675 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5676 "tlbwr"
5677 *mipsI:
5678 *mipsII:
5679 *mipsIII:
5680 *mipsIV:
5681 *mipsV:
5682 *mips32:
5683 *mips32r2:
5684 *mips64:
5685 *mips64r2:
5686 *vr4100:
5687 *vr5000:
5688
5689
5690 :include:::mips3264r2.igen
5691 :include:::m16.igen
5692 :include:::mdmx.igen
5693 :include:::mips3d.igen
5694 :include:::sb1.igen
5695 :include:::tx.igen
5696 :include:::vr.igen
5697