4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator are defined below.
35 // When placing models in the instruction descriptions, please place
36 // them one per line, in the order given here.
40 // Instructions and related functions for these models are included in
42 :model:::mipsI:mips3000:
43 :model:::mipsII:mips6000:
44 :model:::mipsIII:mips4000:
45 :model:::mipsIV:mips8000:
46 :model:::mipsV:mipsisaV:
47 :model:::mips32:mipsisa32:
48 :model:::mips32r2:mipsisa32r2:
49 :model:::mips64:mipsisa64:
50 :model:::mips64r2:mipsisa64r2:
54 // Standard MIPS ISA instructions used for these models are listed here,
55 // as are functions needed by those standard instructions. Instructions
56 // which are model-dependent and which are not in the standard MIPS ISAs
57 // (or which pre-date or use different encodings than the standard
58 // instructions) are (for the most part) in separate .igen files.
59 :model:::vr4100:mips4100: // vr.igen
60 :model:::vr4120:mips4120:
61 :model:::vr5000:mips5000:
62 :model:::vr5400:mips5400:
63 :model:::vr5500:mips5500:
64 :model:::r3900:mips3900: // tx.igen
66 // MIPS Application Specific Extensions (ASEs)
68 // Instructions for the ASEs are in separate .igen files.
69 // ASEs add instructions on to a base ISA.
70 :model:::mips16:mips16: // m16.igen (and m16.dc)
71 :model:::mips16e:mips16e: // m16e.igen
72 :model:::mips3d:mips3d: // mips3d.igen
73 :model:::mdmx:mdmx: // mdmx.igen
74 :model:::dsp:dsp: // dsp.igen
75 :model:::dsp2:dsp2: // dsp2.igen
76 :model:::smartmips:smartmips: // smartmips.igen
80 // Instructions specific to these extensions are in separate .igen files.
81 // Extensions add instructions on to a base ISA.
82 :model:::sb1:sb1: // sb1.igen
85 // Pseudo instructions known by IGEN
88 SignalException (ReservedInstruction, 0);
92 // Pseudo instructions known by interp.c
93 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
94 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
97 SignalException (ReservedInstruction, instruction_0);
104 // Simulate a 32 bit delayslot instruction
107 :function:::address_word:delayslot32:address_word target
109 instruction_word delay_insn;
110 sim_events_slip (SD, 1);
112 CIA = CIA + 4; /* NOTE not mips16 */
113 STATE |= simDELAYSLOT;
114 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
115 ENGINE_ISSUE_PREFIX_HOOK();
116 idecode_issue (CPU_, delay_insn, (CIA));
117 STATE &= ~simDELAYSLOT;
121 :function:::address_word:nullify_next_insn32:
123 sim_events_slip (SD, 1);
124 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
131 // Calculate an effective address given a base and an offset.
134 :function:::address_word:loadstore_ea:address_word base, address_word offset
146 return base + offset;
149 :function:::address_word:loadstore_ea:address_word base, address_word offset
153 #if 0 /* XXX FIXME: enable this only after some additional testing. */
154 /* If in user mode and UX is not set, use 32-bit compatibility effective
155 address computations as defined in the MIPS64 Architecture for
156 Programmers Volume III, Revision 0.95, section 4.9. */
157 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
158 == (ksu_user << status_KSU_shift))
159 return (address_word)((signed32)base + (signed32)offset);
161 return base + offset;
167 // Check that a 32-bit register value is properly sign-extended.
168 // (See NotWordValue in ISA spec.)
171 :function:::int:not_word_value:unsigned_word value
185 #if WITH_TARGET_WORD_BITSIZE == 64
186 return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
194 // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
195 // theoretically portable code which invokes non-portable behaviour from
196 // running with no indication of the portability issue.
197 // (See definition of UNPREDICTABLE in ISA spec.)
200 :function:::void:unpredictable:
212 :function:::void:unpredictable:
218 unpredictable_action (CPU, CIA);
224 // Check that an access to a HI/LO register meets timing requirements
228 // OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
229 // makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
231 // The following restrictions exist for MIPS I - MIPS III:
233 // MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
234 // in between makes MF UNPREDICTABLE. (2)
236 // MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
237 // in between makes MF UNPREDICTABLE. (3)
239 // On the r3900, restriction (2) is not present, and restriction (3) is not
240 // present for multiplication.
242 // Unfortunately, there seems to be some confusion about whether the last
243 // two restrictions should apply to "MIPS IV" as well. One edition of
244 // the MIPS IV ISA says they do, but references in later ISA documents
245 // suggest they don't.
247 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
248 // these restrictions, while others, like the VR5500, don't. To accomodate
249 // such differences, the MIPS IV and MIPS V version of these helper functions
250 // use auxillary routines to determine whether the restriction applies.
254 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
255 // to check for restrictions (2) and (3) above.
257 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
259 if (history->mf.timestamp + 3 > time)
261 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
262 itable[MY_INDEX].name,
264 (long) history->mf.cia);
273 // Check for restriction (2) above (for ISAs/processors that have it),
274 // and record timestamps for restriction (1) above.
276 :function:::int:check_mt_hilo:hilo_history *history
283 signed64 time = sim_events_time (SD);
284 int ok = check_mf_cycles (SD_, history, time, "MT");
285 history->mt.timestamp = time;
286 history->mt.cia = CIA;
290 :function:::int:check_mt_hilo:hilo_history *history
294 signed64 time = sim_events_time (SD);
295 int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
296 || check_mf_cycles (SD_, history, time, "MT"));
297 history->mt.timestamp = time;
298 history->mt.cia = CIA;
302 :function:::int:check_mt_hilo:hilo_history *history
309 signed64 time = sim_events_time (SD);
310 history->mt.timestamp = time;
311 history->mt.cia = CIA;
318 // Check for restriction (1) above, and record timestamps for
319 // restriction (2) and (3) above.
321 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
335 signed64 time = sim_events_time (SD);
338 && peer->mt.timestamp > history->op.timestamp
339 && history->mt.timestamp < history->op.timestamp
340 && ! (history->mf.timestamp > history->op.timestamp
341 && history->mf.timestamp < peer->mt.timestamp)
342 && ! (peer->mf.timestamp > history->op.timestamp
343 && peer->mf.timestamp < peer->mt.timestamp))
345 /* The peer has been written to since the last OP yet we have
347 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
348 itable[MY_INDEX].name,
350 (long) history->op.cia,
351 (long) peer->mt.cia);
354 history->mf.timestamp = time;
355 history->mf.cia = CIA;
363 // Check for restriction (3) above (for ISAs/processors that have it)
364 // for MULT ops, and record timestamps for restriction (1) above.
366 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
373 signed64 time = sim_events_time (SD);
374 int ok = (check_mf_cycles (SD_, hi, time, "OP")
375 && check_mf_cycles (SD_, lo, time, "OP"));
376 hi->op.timestamp = time;
377 lo->op.timestamp = time;
383 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
387 signed64 time = sim_events_time (SD);
388 int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
389 || (check_mf_cycles (SD_, hi, time, "OP")
390 && check_mf_cycles (SD_, lo, time, "OP")));
391 hi->op.timestamp = time;
392 lo->op.timestamp = time;
398 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
405 /* FIXME: could record the fact that a stall occured if we want */
406 signed64 time = sim_events_time (SD);
407 hi->op.timestamp = time;
408 lo->op.timestamp = time;
417 // Check for restriction (3) above (for ISAs/processors that have it)
418 // for DIV ops, and record timestamps for restriction (1) above.
420 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
428 signed64 time = sim_events_time (SD);
429 int ok = (check_mf_cycles (SD_, hi, time, "OP")
430 && check_mf_cycles (SD_, lo, time, "OP"));
431 hi->op.timestamp = time;
432 lo->op.timestamp = time;
438 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
442 signed64 time = sim_events_time (SD);
443 int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
444 || (check_mf_cycles (SD_, hi, time, "OP")
445 && check_mf_cycles (SD_, lo, time, "OP")));
446 hi->op.timestamp = time;
447 lo->op.timestamp = time;
453 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
459 signed64 time = sim_events_time (SD);
460 hi->op.timestamp = time;
461 lo->op.timestamp = time;
470 // Check that the 64-bit instruction can currently be used, and signal
471 // a ReservedInstruction exception if not.
474 :function:::void:check_u64:instruction_word insn
483 // The check should be similar to mips64 for any with PX/UX bit equivalents.
486 :function:::void:check_u64:instruction_word insn
491 #if 0 /* XXX FIXME: enable this only after some additional testing. */
492 if (UserMode && (SR & (status_UX|status_PX)) == 0)
493 SignalException (ReservedInstruction, insn);
500 // MIPS Architecture:
502 // CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
507 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
508 "add r<RD>, r<RS>, r<RT>"
522 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
524 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
526 ALU32_BEGIN (GPR[RS]);
528 ALU32_END (GPR[RD]); /* This checks for overflow. */
530 TRACE_ALU_RESULT (GPR[RD]);
535 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
536 "addi r<RT>, r<RS>, <IMMEDIATE>"
550 if (NotWordValue (GPR[RS]))
552 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
554 ALU32_BEGIN (GPR[RS]);
555 ALU32_ADD (EXTEND16 (IMMEDIATE));
556 ALU32_END (GPR[RT]); /* This checks for overflow. */
558 TRACE_ALU_RESULT (GPR[RT]);
563 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
565 if (NotWordValue (GPR[rs]))
567 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
568 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
569 TRACE_ALU_RESULT (GPR[rt]);
572 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
573 "addiu r<RT>, r<RS>, <IMMEDIATE>"
587 do_addiu (SD_, RS, RT, IMMEDIATE);
592 :function:::void:do_addu:int rs, int rt, int rd
594 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
596 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
597 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
598 TRACE_ALU_RESULT (GPR[rd]);
601 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
602 "addu r<RD>, r<RS>, r<RT>"
616 do_addu (SD_, RS, RT, RD);
621 :function:::void:do_and:int rs, int rt, int rd
623 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
624 GPR[rd] = GPR[rs] & GPR[rt];
625 TRACE_ALU_RESULT (GPR[rd]);
628 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
629 "and r<RD>, r<RS>, r<RT>"
643 do_and (SD_, RS, RT, RD);
648 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
649 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
663 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
664 GPR[RT] = GPR[RS] & IMMEDIATE;
665 TRACE_ALU_RESULT (GPR[RT]);
670 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
671 "beq r<RS>, r<RT>, <OFFSET>"
685 address_word offset = EXTEND16 (OFFSET) << 2;
686 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
688 DELAY_SLOT (NIA + offset);
694 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
695 "beql r<RS>, r<RT>, <OFFSET>"
708 address_word offset = EXTEND16 (OFFSET) << 2;
709 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
711 DELAY_SLOT (NIA + offset);
714 NULLIFY_NEXT_INSTRUCTION ();
719 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
720 "bgez r<RS>, <OFFSET>"
734 address_word offset = EXTEND16 (OFFSET) << 2;
735 if ((signed_word) GPR[RS] >= 0)
737 DELAY_SLOT (NIA + offset);
743 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
744 "bgezal r<RS>, <OFFSET>"
758 address_word offset = EXTEND16 (OFFSET) << 2;
762 if ((signed_word) GPR[RS] >= 0)
764 DELAY_SLOT (NIA + offset);
770 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
771 "bgezall r<RS>, <OFFSET>"
784 address_word offset = EXTEND16 (OFFSET) << 2;
788 /* NOTE: The branch occurs AFTER the next instruction has been
790 if ((signed_word) GPR[RS] >= 0)
792 DELAY_SLOT (NIA + offset);
795 NULLIFY_NEXT_INSTRUCTION ();
800 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
801 "bgezl r<RS>, <OFFSET>"
814 address_word offset = EXTEND16 (OFFSET) << 2;
815 if ((signed_word) GPR[RS] >= 0)
817 DELAY_SLOT (NIA + offset);
820 NULLIFY_NEXT_INSTRUCTION ();
825 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
826 "bgtz r<RS>, <OFFSET>"
840 address_word offset = EXTEND16 (OFFSET) << 2;
841 if ((signed_word) GPR[RS] > 0)
843 DELAY_SLOT (NIA + offset);
849 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
850 "bgtzl r<RS>, <OFFSET>"
863 address_word offset = EXTEND16 (OFFSET) << 2;
864 /* NOTE: The branch occurs AFTER the next instruction has been
866 if ((signed_word) GPR[RS] > 0)
868 DELAY_SLOT (NIA + offset);
871 NULLIFY_NEXT_INSTRUCTION ();
876 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
877 "blez r<RS>, <OFFSET>"
891 address_word offset = EXTEND16 (OFFSET) << 2;
892 /* NOTE: The branch occurs AFTER the next instruction has been
894 if ((signed_word) GPR[RS] <= 0)
896 DELAY_SLOT (NIA + offset);
902 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
903 "bgezl r<RS>, <OFFSET>"
916 address_word offset = EXTEND16 (OFFSET) << 2;
917 if ((signed_word) GPR[RS] <= 0)
919 DELAY_SLOT (NIA + offset);
922 NULLIFY_NEXT_INSTRUCTION ();
927 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
928 "bltz r<RS>, <OFFSET>"
942 address_word offset = EXTEND16 (OFFSET) << 2;
943 if ((signed_word) GPR[RS] < 0)
945 DELAY_SLOT (NIA + offset);
951 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
952 "bltzal r<RS>, <OFFSET>"
966 address_word offset = EXTEND16 (OFFSET) << 2;
970 /* NOTE: The branch occurs AFTER the next instruction has been
972 if ((signed_word) GPR[RS] < 0)
974 DELAY_SLOT (NIA + offset);
980 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
981 "bltzall r<RS>, <OFFSET>"
994 address_word offset = EXTEND16 (OFFSET) << 2;
998 if ((signed_word) GPR[RS] < 0)
1000 DELAY_SLOT (NIA + offset);
1003 NULLIFY_NEXT_INSTRUCTION ();
1008 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1009 "bltzl r<RS>, <OFFSET>"
1022 address_word offset = EXTEND16 (OFFSET) << 2;
1023 /* NOTE: The branch occurs AFTER the next instruction has been
1025 if ((signed_word) GPR[RS] < 0)
1027 DELAY_SLOT (NIA + offset);
1030 NULLIFY_NEXT_INSTRUCTION ();
1035 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1036 "bne r<RS>, r<RT>, <OFFSET>"
1050 address_word offset = EXTEND16 (OFFSET) << 2;
1051 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1053 DELAY_SLOT (NIA + offset);
1059 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1060 "bnel r<RS>, r<RT>, <OFFSET>"
1073 address_word offset = EXTEND16 (OFFSET) << 2;
1074 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1076 DELAY_SLOT (NIA + offset);
1079 NULLIFY_NEXT_INSTRUCTION ();
1084 000000,20.CODE,001101:SPECIAL:32::BREAK
1099 /* Check for some break instruction which are reserved for use by the simulator. */
1100 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1101 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1102 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1104 sim_engine_halt (SD, CPU, NULL, cia,
1105 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1107 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1108 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1110 if (STATE & simDELAYSLOT)
1111 PC = cia - 4; /* reference the branch instruction */
1114 SignalException (BreakPoint, instruction_0);
1119 /* If we get this far, we're not an instruction reserved by the sim. Raise
1121 SignalException (BreakPoint, instruction_0);
1127 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1135 unsigned32 temp = GPR[RS];
1139 if (NotWordValue (GPR[RS]))
1141 TRACE_ALU_INPUT1 (GPR[RS]);
1142 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1144 if ((temp & mask) == 0)
1148 GPR[RD] = EXTEND32 (i);
1149 TRACE_ALU_RESULT (GPR[RD]);
1154 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1162 unsigned32 temp = GPR[RS];
1166 if (NotWordValue (GPR[RS]))
1168 TRACE_ALU_INPUT1 (GPR[RS]);
1169 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1171 if ((temp & mask) != 0)
1175 GPR[RD] = EXTEND32 (i);
1176 TRACE_ALU_RESULT (GPR[RD]);
1181 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1182 "dadd r<RD>, r<RS>, r<RT>"
1191 check_u64 (SD_, instruction_0);
1192 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1194 ALU64_BEGIN (GPR[RS]);
1195 ALU64_ADD (GPR[RT]);
1196 ALU64_END (GPR[RD]); /* This checks for overflow. */
1198 TRACE_ALU_RESULT (GPR[RD]);
1203 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1204 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1213 check_u64 (SD_, instruction_0);
1214 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1216 ALU64_BEGIN (GPR[RS]);
1217 ALU64_ADD (EXTEND16 (IMMEDIATE));
1218 ALU64_END (GPR[RT]); /* This checks for overflow. */
1220 TRACE_ALU_RESULT (GPR[RT]);
1225 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1227 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1228 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1229 TRACE_ALU_RESULT (GPR[rt]);
1232 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1233 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1242 check_u64 (SD_, instruction_0);
1243 do_daddiu (SD_, RS, RT, IMMEDIATE);
1248 :function:::void:do_daddu:int rs, int rt, int rd
1250 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1251 GPR[rd] = GPR[rs] + GPR[rt];
1252 TRACE_ALU_RESULT (GPR[rd]);
1255 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1256 "daddu r<RD>, r<RS>, r<RT>"
1265 check_u64 (SD_, instruction_0);
1266 do_daddu (SD_, RS, RT, RD);
1271 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1277 unsigned64 temp = GPR[RS];
1280 check_u64 (SD_, instruction_0);
1283 TRACE_ALU_INPUT1 (GPR[RS]);
1284 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1286 if ((temp & mask) == 0)
1290 GPR[RD] = EXTEND32 (i);
1291 TRACE_ALU_RESULT (GPR[RD]);
1296 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1302 unsigned64 temp = GPR[RS];
1305 check_u64 (SD_, instruction_0);
1308 TRACE_ALU_INPUT1 (GPR[RS]);
1309 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1311 if ((temp & mask) != 0)
1315 GPR[RD] = EXTEND32 (i);
1316 TRACE_ALU_RESULT (GPR[RD]);
1321 :function:::void:do_ddiv:int rs, int rt
1323 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1324 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1326 signed64 n = GPR[rs];
1327 signed64 d = GPR[rt];
1332 lo = SIGNED64 (0x8000000000000000);
1335 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1337 lo = SIGNED64 (0x8000000000000000);
1348 TRACE_ALU_RESULT2 (HI, LO);
1351 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1361 check_u64 (SD_, instruction_0);
1362 do_ddiv (SD_, RS, RT);
1367 :function:::void:do_ddivu:int rs, int rt
1369 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1370 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1372 unsigned64 n = GPR[rs];
1373 unsigned64 d = GPR[rt];
1378 lo = SIGNED64 (0x8000000000000000);
1389 TRACE_ALU_RESULT2 (HI, LO);
1392 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1393 "ddivu r<RS>, r<RT>"
1402 check_u64 (SD_, instruction_0);
1403 do_ddivu (SD_, RS, RT);
1406 :function:::void:do_div:int rs, int rt
1408 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1409 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1411 signed32 n = GPR[rs];
1412 signed32 d = GPR[rt];
1415 LO = EXTEND32 (0x80000000);
1418 else if (n == SIGNED32 (0x80000000) && d == -1)
1420 LO = EXTEND32 (0x80000000);
1425 LO = EXTEND32 (n / d);
1426 HI = EXTEND32 (n % d);
1429 TRACE_ALU_RESULT2 (HI, LO);
1432 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1447 do_div (SD_, RS, RT);
1452 :function:::void:do_divu:int rs, int rt
1454 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1455 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1457 unsigned32 n = GPR[rs];
1458 unsigned32 d = GPR[rt];
1461 LO = EXTEND32 (0x80000000);
1466 LO = EXTEND32 (n / d);
1467 HI = EXTEND32 (n % d);
1470 TRACE_ALU_RESULT2 (HI, LO);
1473 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1488 do_divu (SD_, RS, RT);
1492 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1502 unsigned64 op1 = GPR[rs];
1503 unsigned64 op2 = GPR[rt];
1504 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1505 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1506 /* make signed multiply unsigned */
1510 if ((signed64) op1 < 0)
1515 if ((signed64) op2 < 0)
1521 /* multiply out the 4 sub products */
1522 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1523 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1524 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1525 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1526 /* add the products */
1527 mid = ((unsigned64) VH4_8 (m00)
1528 + (unsigned64) VL4_8 (m10)
1529 + (unsigned64) VL4_8 (m01));
1530 lo = U8_4 (mid, m00);
1532 + (unsigned64) VH4_8 (mid)
1533 + (unsigned64) VH4_8 (m01)
1534 + (unsigned64) VH4_8 (m10));
1544 /* save the result HI/LO (and a gpr) */
1549 TRACE_ALU_RESULT2 (HI, LO);
1552 :function:::void:do_dmult:int rs, int rt, int rd
1554 do_dmultx (SD_, rs, rt, rd, 1);
1557 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1558 "dmult r<RS>, r<RT>"
1566 check_u64 (SD_, instruction_0);
1567 do_dmult (SD_, RS, RT, 0);
1570 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1571 "dmult r<RS>, r<RT>":RD == 0
1572 "dmult r<RD>, r<RS>, r<RT>"
1575 check_u64 (SD_, instruction_0);
1576 do_dmult (SD_, RS, RT, RD);
1581 :function:::void:do_dmultu:int rs, int rt, int rd
1583 do_dmultx (SD_, rs, rt, rd, 0);
1586 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1587 "dmultu r<RS>, r<RT>"
1595 check_u64 (SD_, instruction_0);
1596 do_dmultu (SD_, RS, RT, 0);
1599 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1600 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1601 "dmultu r<RS>, r<RT>"
1604 check_u64 (SD_, instruction_0);
1605 do_dmultu (SD_, RS, RT, RD);
1609 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1614 TRACE_ALU_INPUT2 (x, y);
1615 result = ROTR64 (x, y);
1616 TRACE_ALU_RESULT (result);
1620 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1621 "dror r<RD>, r<RT>, <SHIFT>"
1626 check_u64 (SD_, instruction_0);
1627 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1630 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1631 "dror32 r<RD>, r<RT>, <SHIFT>"
1636 check_u64 (SD_, instruction_0);
1637 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1640 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1641 "drorv r<RD>, r<RT>, r<RS>"
1646 check_u64 (SD_, instruction_0);
1647 GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1651 :function:::void:do_dsll:int rt, int rd, int shift
1653 TRACE_ALU_INPUT2 (GPR[rt], shift);
1654 GPR[rd] = GPR[rt] << shift;
1655 TRACE_ALU_RESULT (GPR[rd]);
1658 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1659 "dsll r<RD>, r<RT>, <SHIFT>"
1668 check_u64 (SD_, instruction_0);
1669 do_dsll (SD_, RT, RD, SHIFT);
1673 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1674 "dsll32 r<RD>, r<RT>, <SHIFT>"
1684 check_u64 (SD_, instruction_0);
1685 TRACE_ALU_INPUT2 (GPR[RT], s);
1686 GPR[RD] = GPR[RT] << s;
1687 TRACE_ALU_RESULT (GPR[RD]);
1690 :function:::void:do_dsllv:int rs, int rt, int rd
1692 int s = MASKED64 (GPR[rs], 5, 0);
1693 TRACE_ALU_INPUT2 (GPR[rt], s);
1694 GPR[rd] = GPR[rt] << s;
1695 TRACE_ALU_RESULT (GPR[rd]);
1698 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1699 "dsllv r<RD>, r<RT>, r<RS>"
1708 check_u64 (SD_, instruction_0);
1709 do_dsllv (SD_, RS, RT, RD);
1712 :function:::void:do_dsra:int rt, int rd, int shift
1714 TRACE_ALU_INPUT2 (GPR[rt], shift);
1715 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1716 TRACE_ALU_RESULT (GPR[rd]);
1720 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1721 "dsra r<RD>, r<RT>, <SHIFT>"
1730 check_u64 (SD_, instruction_0);
1731 do_dsra (SD_, RT, RD, SHIFT);
1735 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1736 "dsra32 r<RD>, r<RT>, <SHIFT>"
1746 check_u64 (SD_, instruction_0);
1747 TRACE_ALU_INPUT2 (GPR[RT], s);
1748 GPR[RD] = ((signed64) GPR[RT]) >> s;
1749 TRACE_ALU_RESULT (GPR[RD]);
1753 :function:::void:do_dsrav:int rs, int rt, int rd
1755 int s = MASKED64 (GPR[rs], 5, 0);
1756 TRACE_ALU_INPUT2 (GPR[rt], s);
1757 GPR[rd] = ((signed64) GPR[rt]) >> s;
1758 TRACE_ALU_RESULT (GPR[rd]);
1761 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1762 "dsrav r<RD>, r<RT>, r<RS>"
1771 check_u64 (SD_, instruction_0);
1772 do_dsrav (SD_, RS, RT, RD);
1775 :function:::void:do_dsrl:int rt, int rd, int shift
1777 TRACE_ALU_INPUT2 (GPR[rt], shift);
1778 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1779 TRACE_ALU_RESULT (GPR[rd]);
1783 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1784 "dsrl r<RD>, r<RT>, <SHIFT>"
1793 check_u64 (SD_, instruction_0);
1794 do_dsrl (SD_, RT, RD, SHIFT);
1798 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1799 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1809 check_u64 (SD_, instruction_0);
1810 TRACE_ALU_INPUT2 (GPR[RT], s);
1811 GPR[RD] = (unsigned64) GPR[RT] >> s;
1812 TRACE_ALU_RESULT (GPR[RD]);
1816 :function:::void:do_dsrlv:int rs, int rt, int rd
1818 int s = MASKED64 (GPR[rs], 5, 0);
1819 TRACE_ALU_INPUT2 (GPR[rt], s);
1820 GPR[rd] = (unsigned64) GPR[rt] >> s;
1821 TRACE_ALU_RESULT (GPR[rd]);
1826 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1827 "dsrlv r<RD>, r<RT>, r<RS>"
1836 check_u64 (SD_, instruction_0);
1837 do_dsrlv (SD_, RS, RT, RD);
1841 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1842 "dsub r<RD>, r<RS>, r<RT>"
1851 check_u64 (SD_, instruction_0);
1852 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1854 ALU64_BEGIN (GPR[RS]);
1855 ALU64_SUB (GPR[RT]);
1856 ALU64_END (GPR[RD]); /* This checks for overflow. */
1858 TRACE_ALU_RESULT (GPR[RD]);
1862 :function:::void:do_dsubu:int rs, int rt, int rd
1864 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1865 GPR[rd] = GPR[rs] - GPR[rt];
1866 TRACE_ALU_RESULT (GPR[rd]);
1869 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1870 "dsubu r<RD>, r<RS>, r<RT>"
1879 check_u64 (SD_, instruction_0);
1880 do_dsubu (SD_, RS, RT, RD);
1884 000010,26.INSTR_INDEX:NORMAL:32::J
1899 /* NOTE: The region used is that of the delay slot NIA and NOT the
1900 current instruction */
1901 address_word region = (NIA & MASK (63, 28));
1902 DELAY_SLOT (region | (INSTR_INDEX << 2));
1906 000011,26.INSTR_INDEX:NORMAL:32::JAL
1921 /* NOTE: The region used is that of the delay slot and NOT the
1922 current instruction */
1923 address_word region = (NIA & MASK (63, 28));
1925 DELAY_SLOT (region | (INSTR_INDEX << 2));
1928 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1929 "jalr r<RS>":RD == 31
1944 address_word temp = GPR[RS];
1949 000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
1950 "jalr.hb r<RS>":RD == 31
1951 "jalr.hb r<RD>, r<RS>"
1955 address_word temp = GPR[RS];
1960 000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
1975 DELAY_SLOT (GPR[RS]);
1978 000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
1983 DELAY_SLOT (GPR[RS]);
1986 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1988 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1989 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1990 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1997 vaddr = loadstore_ea (SD_, base, offset);
1998 if ((vaddr & access) != 0)
2000 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
2002 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2003 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2004 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
2005 byte = ((vaddr & mask) ^ bigendiancpu);
2006 return (memval >> (8 * byte));
2009 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2011 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2012 address_word reverseendian = (ReverseEndian ? -1 : 0);
2013 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2022 unsigned_word lhs_mask;
2025 vaddr = loadstore_ea (SD_, base, offset);
2026 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2027 paddr = (paddr ^ (reverseendian & mask));
2028 if (BigEndianMem == 0)
2029 paddr = paddr & ~access;
2031 /* compute where within the word/mem we are */
2032 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2033 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2034 nr_lhs_bits = 8 * byte + 8;
2035 nr_rhs_bits = 8 * access - 8 * byte;
2036 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2038 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2039 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2040 (long) ((unsigned64) paddr >> 32), (long) paddr,
2041 word, byte, nr_lhs_bits, nr_rhs_bits); */
2043 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2046 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2047 temp = (memval << nr_rhs_bits);
2051 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2052 temp = (memval >> nr_lhs_bits);
2054 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2055 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2057 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2058 (long) ((unsigned64) memval >> 32), (long) memval,
2059 (long) ((unsigned64) temp >> 32), (long) temp,
2060 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2061 (long) (rt >> 32), (long) rt); */
2065 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2067 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2068 address_word reverseendian = (ReverseEndian ? -1 : 0);
2069 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2076 vaddr = loadstore_ea (SD_, base, offset);
2077 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2078 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2079 paddr = (paddr ^ (reverseendian & mask));
2080 if (BigEndianMem != 0)
2081 paddr = paddr & ~access;
2082 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2083 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2084 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2085 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2086 (long) paddr, byte, (long) paddr, (long) memval); */
2088 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2090 rt |= (memval >> (8 * byte)) & screen;
2096 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2097 "lb r<RT>, <OFFSET>(r<BASE>)"
2111 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2115 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2116 "lbu r<RT>, <OFFSET>(r<BASE>)"
2130 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2134 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2135 "ld r<RT>, <OFFSET>(r<BASE>)"
2144 check_u64 (SD_, instruction_0);
2145 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2149 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2150 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2163 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2169 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2170 "ldl r<RT>, <OFFSET>(r<BASE>)"
2179 check_u64 (SD_, instruction_0);
2180 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2184 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2185 "ldr r<RT>, <OFFSET>(r<BASE>)"
2194 check_u64 (SD_, instruction_0);
2195 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2199 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2200 "lh r<RT>, <OFFSET>(r<BASE>)"
2214 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2218 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2219 "lhu r<RT>, <OFFSET>(r<BASE>)"
2233 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2237 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2238 "ll r<RT>, <OFFSET>(r<BASE>)"
2250 address_word base = GPR[BASE];
2251 address_word offset = EXTEND16 (OFFSET);
2253 address_word vaddr = loadstore_ea (SD_, base, offset);
2256 if ((vaddr & 3) != 0)
2258 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2262 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2264 unsigned64 memval = 0;
2265 unsigned64 memval1 = 0;
2266 unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2267 unsigned int shift = 2;
2268 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2269 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2271 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2272 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2273 byte = ((vaddr & mask) ^ (bigend << shift));
2274 GPR[RT] = EXTEND32 (memval >> (8 * byte));
2282 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2283 "lld r<RT>, <OFFSET>(r<BASE>)"
2292 address_word base = GPR[BASE];
2293 address_word offset = EXTEND16 (OFFSET);
2294 check_u64 (SD_, instruction_0);
2296 address_word vaddr = loadstore_ea (SD_, base, offset);
2299 if ((vaddr & 7) != 0)
2301 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2305 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2307 unsigned64 memval = 0;
2308 unsigned64 memval1 = 0;
2309 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2318 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2319 "lui r<RT>, %#lx<IMMEDIATE>"
2333 TRACE_ALU_INPUT1 (IMMEDIATE);
2334 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2335 TRACE_ALU_RESULT (GPR[RT]);
2339 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2340 "lw r<RT>, <OFFSET>(r<BASE>)"
2354 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2358 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2359 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2373 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2377 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2378 "lwl r<RT>, <OFFSET>(r<BASE>)"
2392 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2396 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2397 "lwr r<RT>, <OFFSET>(r<BASE>)"
2411 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2415 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2416 "lwu r<RT>, <OFFSET>(r<BASE>)"
2425 check_u64 (SD_, instruction_0);
2426 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2431 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2438 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2439 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2441 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2442 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2443 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2444 LO = EXTEND32 (temp);
2445 HI = EXTEND32 (VH4_8 (temp));
2446 TRACE_ALU_RESULT2 (HI, LO);
2450 011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
2451 "madd r<RS>, r<RT>":AC == 0
2452 "madd ac<AC>, r<RS>, r<RT>"
2459 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2460 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2462 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2463 temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2464 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2465 DSPLO(AC) = EXTEND32 (temp);
2466 DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2468 TRACE_ALU_RESULT2 (HI, LO);
2472 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2473 "maddu r<RS>, r<RT>"
2479 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2480 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2482 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2483 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2484 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2485 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
2486 LO = EXTEND32 (temp);
2487 HI = EXTEND32 (VH4_8 (temp));
2488 TRACE_ALU_RESULT2 (HI, LO);
2492 011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
2493 "maddu r<RS>, r<RT>":AC == 0
2494 "maddu ac<AC>, r<RS>, r<RT>"
2501 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2502 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2504 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2505 temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2506 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2508 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
2509 DSPLO(AC) = EXTEND32 (temp);
2510 DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2512 TRACE_ALU_RESULT2 (HI, LO);
2516 :function:::void:do_mfhi:int rd
2518 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2519 TRACE_ALU_INPUT1 (HI);
2521 TRACE_ALU_RESULT (GPR[rd]);
2524 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2541 000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
2542 "mfhi r<RD>":AC == 0
2543 "mfhi r<RD>, ac<AC>"
2551 GPR[RD] = DSPHI(AC);
2555 :function:::void:do_mflo:int rd
2557 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2558 TRACE_ALU_INPUT1 (LO);
2560 TRACE_ALU_RESULT (GPR[rd]);
2563 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2580 000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
2581 "mflo r<RD>":AC == 0
2582 "mflo r<RD>, ac<AC>"
2590 GPR[RD] = DSPLO(AC);
2594 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2595 "movn r<RD>, r<RS>, r<RT>"
2607 TRACE_ALU_RESULT (GPR[RD]);
2613 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2614 "movz r<RD>, r<RS>, r<RT>"
2626 TRACE_ALU_RESULT (GPR[RD]);
2632 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2639 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2640 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2642 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2643 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2644 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2645 LO = EXTEND32 (temp);
2646 HI = EXTEND32 (VH4_8 (temp));
2647 TRACE_ALU_RESULT2 (HI, LO);
2651 011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
2652 "msub r<RS>, r<RT>":AC == 0
2653 "msub ac<AC>, r<RS>, r<RT>"
2660 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2661 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2663 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2664 temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2665 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2666 DSPLO(AC) = EXTEND32 (temp);
2667 DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2669 TRACE_ALU_RESULT2 (HI, LO);
2673 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2674 "msubu r<RS>, r<RT>"
2680 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2681 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2683 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2684 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2685 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2686 LO = EXTEND32 (temp);
2687 HI = EXTEND32 (VH4_8 (temp));
2688 TRACE_ALU_RESULT2 (HI, LO);
2692 011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
2693 "msubu r<RS>, r<RT>":AC == 0
2694 "msubu ac<AC>, r<RS>, r<RT>"
2701 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2702 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2704 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2705 temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2706 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2707 DSPLO(AC) = EXTEND32 (temp);
2708 DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2710 TRACE_ALU_RESULT2 (HI, LO);
2714 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2727 check_mt_hilo (SD_, HIHISTORY);
2732 000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
2733 "mthi r<RS>":AC == 0
2734 "mthi r<RS>, ac<AC>"
2740 check_mt_hilo (SD_, HIHISTORY);
2741 DSPHI(AC) = GPR[RS];
2745 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2758 check_mt_hilo (SD_, LOHISTORY);
2763 000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
2764 "mtlo r<RS>":AC == 0
2765 "mtlo r<RS>, ac<AC>"
2771 check_mt_hilo (SD_, LOHISTORY);
2772 DSPLO(AC) = GPR[RS];
2776 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2777 "mul r<RD>, r<RS>, r<RT>"
2785 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2787 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2788 prod = (((signed64)(signed32) GPR[RS])
2789 * ((signed64)(signed32) GPR[RT]));
2790 GPR[RD] = EXTEND32 (VL4_8 (prod));
2791 TRACE_ALU_RESULT (GPR[RD]);
2796 :function:::void:do_mult:int rs, int rt, int rd
2799 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2800 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2802 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2803 prod = (((signed64)(signed32) GPR[rs])
2804 * ((signed64)(signed32) GPR[rt]));
2805 LO = EXTEND32 (VL4_8 (prod));
2806 HI = EXTEND32 (VH4_8 (prod));
2807 ACX = 0; /* SmartMIPS */
2810 TRACE_ALU_RESULT2 (HI, LO);
2813 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2824 do_mult (SD_, RS, RT, 0);
2828 000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
2829 "mult r<RS>, r<RT>":AC == 0
2830 "mult ac<AC>, r<RS>, r<RT>"
2837 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2838 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2840 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2841 prod = ((signed64)(signed32) GPR[RS])
2842 * ((signed64)(signed32) GPR[RT]);
2843 DSPLO(AC) = EXTEND32 (VL4_8 (prod));
2844 DSPHI(AC) = EXTEND32 (VH4_8 (prod));
2847 ACX = 0; /* SmartMIPS */
2848 TRACE_ALU_RESULT2 (HI, LO);
2853 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2854 "mult r<RS>, r<RT>":RD == 0
2855 "mult r<RD>, r<RS>, r<RT>"
2859 do_mult (SD_, RS, RT, RD);
2863 :function:::void:do_multu:int rs, int rt, int rd
2866 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2867 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2869 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2870 prod = (((unsigned64)(unsigned32) GPR[rs])
2871 * ((unsigned64)(unsigned32) GPR[rt]));
2872 LO = EXTEND32 (VL4_8 (prod));
2873 HI = EXTEND32 (VH4_8 (prod));
2876 TRACE_ALU_RESULT2 (HI, LO);
2879 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2880 "multu r<RS>, r<RT>"
2890 do_multu (SD_, RS, RT, 0);
2894 000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
2895 "multu r<RS>, r<RT>":AC == 0
2896 "multu r<RS>, r<RT>"
2903 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2904 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2906 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2907 prod = ((unsigned64)(unsigned32) GPR[RS])
2908 * ((unsigned64)(unsigned32) GPR[RT]);
2909 DSPLO(AC) = EXTEND32 (VL4_8 (prod));
2910 DSPHI(AC) = EXTEND32 (VH4_8 (prod));
2912 TRACE_ALU_RESULT2 (HI, LO);
2916 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2917 "multu r<RS>, r<RT>":RD == 0
2918 "multu r<RD>, r<RS>, r<RT>"
2922 do_multu (SD_, RS, RT, RD);
2926 :function:::void:do_nor:int rs, int rt, int rd
2928 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2929 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2930 TRACE_ALU_RESULT (GPR[rd]);
2933 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2934 "nor r<RD>, r<RS>, r<RT>"
2948 do_nor (SD_, RS, RT, RD);
2952 :function:::void:do_or:int rs, int rt, int rd
2954 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2955 GPR[rd] = (GPR[rs] | GPR[rt]);
2956 TRACE_ALU_RESULT (GPR[rd]);
2959 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2960 "or r<RD>, r<RS>, r<RT>"
2974 do_or (SD_, RS, RT, RD);
2979 :function:::void:do_ori:int rs, int rt, unsigned immediate
2981 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2982 GPR[rt] = (GPR[rs] | immediate);
2983 TRACE_ALU_RESULT (GPR[rt]);
2986 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2987 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3001 do_ori (SD_, RS, RT, IMMEDIATE);
3005 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
3006 "pref <HINT>, <OFFSET>(r<BASE>)"
3015 address_word base = GPR[BASE];
3016 address_word offset = EXTEND16 (OFFSET);
3018 address_word vaddr = loadstore_ea (SD_, base, offset);
3022 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3023 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
3029 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
3034 TRACE_ALU_INPUT2 (x, y);
3035 result = EXTEND32 (ROTR32 (x, y));
3036 TRACE_ALU_RESULT (result);
3040 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
3041 "ror r<RD>, r<RT>, <SHIFT>"
3048 GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
3051 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
3052 "rorv r<RD>, r<RT>, r<RS>"
3059 GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
3063 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
3065 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3066 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3067 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3074 vaddr = loadstore_ea (SD_, base, offset);
3075 if ((vaddr & access) != 0)
3077 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
3079 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3080 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3081 byte = ((vaddr & mask) ^ bigendiancpu);
3082 memval = (word << (8 * byte));
3083 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
3086 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3088 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3089 address_word reverseendian = (ReverseEndian ? -1 : 0);
3090 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3100 vaddr = loadstore_ea (SD_, base, offset);
3101 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3102 paddr = (paddr ^ (reverseendian & mask));
3103 if (BigEndianMem == 0)
3104 paddr = paddr & ~access;
3106 /* compute where within the word/mem we are */
3107 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3108 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3109 nr_lhs_bits = 8 * byte + 8;
3110 nr_rhs_bits = 8 * access - 8 * byte;
3111 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3112 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3113 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3114 (long) ((unsigned64) paddr >> 32), (long) paddr,
3115 word, byte, nr_lhs_bits, nr_rhs_bits); */
3119 memval = (rt >> nr_rhs_bits);
3123 memval = (rt << nr_lhs_bits);
3125 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3126 (long) ((unsigned64) rt >> 32), (long) rt,
3127 (long) ((unsigned64) memval >> 32), (long) memval); */
3128 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3131 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3133 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3134 address_word reverseendian = (ReverseEndian ? -1 : 0);
3135 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3142 vaddr = loadstore_ea (SD_, base, offset);
3143 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3144 paddr = (paddr ^ (reverseendian & mask));
3145 if (BigEndianMem != 0)
3147 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3148 memval = (rt << (byte * 8));
3149 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3153 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
3154 "sb r<RT>, <OFFSET>(r<BASE>)"
3168 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3172 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
3173 "sc r<RT>, <OFFSET>(r<BASE>)"
3185 unsigned32 instruction = instruction_0;
3186 address_word base = GPR[BASE];
3187 address_word offset = EXTEND16 (OFFSET);
3189 address_word vaddr = loadstore_ea (SD_, base, offset);
3192 if ((vaddr & 3) != 0)
3194 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3198 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3200 unsigned64 memval = 0;
3201 unsigned64 memval1 = 0;
3202 unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3203 address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
3204 address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
3206 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3207 byte = ((vaddr & mask) ^ bigendiancpu);
3208 memval = ((unsigned64) GPR[RT] << (8 * byte));
3211 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3220 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3221 "scd r<RT>, <OFFSET>(r<BASE>)"
3230 address_word base = GPR[BASE];
3231 address_word offset = EXTEND16 (OFFSET);
3232 check_u64 (SD_, instruction_0);
3234 address_word vaddr = loadstore_ea (SD_, base, offset);
3237 if ((vaddr & 7) != 0)
3239 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3243 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3245 unsigned64 memval = 0;
3246 unsigned64 memval1 = 0;
3250 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3259 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3260 "sd r<RT>, <OFFSET>(r<BASE>)"
3269 check_u64 (SD_, instruction_0);
3270 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3274 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3275 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3287 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3291 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3292 "sdl r<RT>, <OFFSET>(r<BASE>)"
3301 check_u64 (SD_, instruction_0);
3302 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3306 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3307 "sdr r<RT>, <OFFSET>(r<BASE>)"
3316 check_u64 (SD_, instruction_0);
3317 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3322 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3323 "sh r<RT>, <OFFSET>(r<BASE>)"
3337 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3341 :function:::void:do_sll:int rt, int rd, int shift
3343 unsigned32 temp = (GPR[rt] << shift);
3344 TRACE_ALU_INPUT2 (GPR[rt], shift);
3345 GPR[rd] = EXTEND32 (temp);
3346 TRACE_ALU_RESULT (GPR[rd]);
3349 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
3350 "nop":RD == 0 && RT == 0 && SHIFT == 0
3351 "sll r<RD>, r<RT>, <SHIFT>"
3361 /* Skip shift for NOP, so that there won't be lots of extraneous
3363 if (RD != 0 || RT != 0 || SHIFT != 0)
3364 do_sll (SD_, RT, RD, SHIFT);
3367 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3368 "nop":RD == 0 && RT == 0 && SHIFT == 0
3369 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
3370 "sll r<RD>, r<RT>, <SHIFT>"
3376 /* Skip shift for NOP and SSNOP, so that there won't be lots of
3377 extraneous trace output. */
3378 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3379 do_sll (SD_, RT, RD, SHIFT);
3383 :function:::void:do_sllv:int rs, int rt, int rd
3385 int s = MASKED (GPR[rs], 4, 0);
3386 unsigned32 temp = (GPR[rt] << s);
3387 TRACE_ALU_INPUT2 (GPR[rt], s);
3388 GPR[rd] = EXTEND32 (temp);
3389 TRACE_ALU_RESULT (GPR[rd]);
3392 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
3393 "sllv r<RD>, r<RT>, r<RS>"
3407 do_sllv (SD_, RS, RT, RD);
3411 :function:::void:do_slt:int rs, int rt, int rd
3413 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3414 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3415 TRACE_ALU_RESULT (GPR[rd]);
3418 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
3419 "slt r<RD>, r<RS>, r<RT>"
3433 do_slt (SD_, RS, RT, RD);
3437 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3439 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3440 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3441 TRACE_ALU_RESULT (GPR[rt]);
3444 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3445 "slti r<RT>, r<RS>, <IMMEDIATE>"
3459 do_slti (SD_, RS, RT, IMMEDIATE);
3463 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3465 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3466 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3467 TRACE_ALU_RESULT (GPR[rt]);
3470 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3471 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3485 do_sltiu (SD_, RS, RT, IMMEDIATE);
3490 :function:::void:do_sltu:int rs, int rt, int rd
3492 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3493 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3494 TRACE_ALU_RESULT (GPR[rd]);
3497 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3498 "sltu r<RD>, r<RS>, r<RT>"
3512 do_sltu (SD_, RS, RT, RD);
3516 :function:::void:do_sra:int rt, int rd, int shift
3518 signed32 temp = (signed32) GPR[rt] >> shift;
3519 if (NotWordValue (GPR[rt]))
3521 TRACE_ALU_INPUT2 (GPR[rt], shift);
3522 GPR[rd] = EXTEND32 (temp);
3523 TRACE_ALU_RESULT (GPR[rd]);
3526 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3527 "sra r<RD>, r<RT>, <SHIFT>"
3541 do_sra (SD_, RT, RD, SHIFT);
3546 :function:::void:do_srav:int rs, int rt, int rd
3548 int s = MASKED (GPR[rs], 4, 0);
3549 signed32 temp = (signed32) GPR[rt] >> s;
3550 if (NotWordValue (GPR[rt]))
3552 TRACE_ALU_INPUT2 (GPR[rt], s);
3553 GPR[rd] = EXTEND32 (temp);
3554 TRACE_ALU_RESULT (GPR[rd]);
3557 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3558 "srav r<RD>, r<RT>, r<RS>"
3572 do_srav (SD_, RS, RT, RD);
3577 :function:::void:do_srl:int rt, int rd, int shift
3579 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3580 if (NotWordValue (GPR[rt]))
3582 TRACE_ALU_INPUT2 (GPR[rt], shift);
3583 GPR[rd] = EXTEND32 (temp);
3584 TRACE_ALU_RESULT (GPR[rd]);
3587 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3588 "srl r<RD>, r<RT>, <SHIFT>"
3602 do_srl (SD_, RT, RD, SHIFT);
3606 :function:::void:do_srlv:int rs, int rt, int rd
3608 int s = MASKED (GPR[rs], 4, 0);
3609 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3610 if (NotWordValue (GPR[rt]))
3612 TRACE_ALU_INPUT2 (GPR[rt], s);
3613 GPR[rd] = EXTEND32 (temp);
3614 TRACE_ALU_RESULT (GPR[rd]);
3617 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3618 "srlv r<RD>, r<RT>, r<RS>"
3632 do_srlv (SD_, RS, RT, RD);
3636 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3637 "sub r<RD>, r<RS>, r<RT>"
3651 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3653 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3655 ALU32_BEGIN (GPR[RS]);
3656 ALU32_SUB (GPR[RT]);
3657 ALU32_END (GPR[RD]); /* This checks for overflow. */
3659 TRACE_ALU_RESULT (GPR[RD]);
3663 :function:::void:do_subu:int rs, int rt, int rd
3665 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3667 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3668 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3669 TRACE_ALU_RESULT (GPR[rd]);
3672 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3673 "subu r<RD>, r<RS>, r<RT>"
3687 do_subu (SD_, RS, RT, RD);
3691 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3692 "sw r<RT>, <OFFSET>(r<BASE>)"
3706 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3710 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3711 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3725 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3729 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3730 "swl r<RT>, <OFFSET>(r<BASE>)"
3744 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3748 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3749 "swr r<RT>, <OFFSET>(r<BASE>)"
3763 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3767 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3782 SyncOperation (STYPE);
3786 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3787 "syscall %#lx<CODE>"
3801 SignalException (SystemCall, instruction_0);
3805 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3818 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3819 SignalException (Trap, instruction_0);
3823 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3824 "teqi r<RS>, <IMMEDIATE>"
3836 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3837 SignalException (Trap, instruction_0);
3841 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3854 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3855 SignalException (Trap, instruction_0);
3859 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3860 "tgei r<RS>, <IMMEDIATE>"
3872 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3873 SignalException (Trap, instruction_0);
3877 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3878 "tgeiu r<RS>, <IMMEDIATE>"
3890 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3891 SignalException (Trap, instruction_0);
3895 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3908 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3909 SignalException (Trap, instruction_0);
3913 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3926 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3927 SignalException (Trap, instruction_0);
3931 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3932 "tlti r<RS>, <IMMEDIATE>"
3944 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3945 SignalException (Trap, instruction_0);
3949 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3950 "tltiu r<RS>, <IMMEDIATE>"
3962 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3963 SignalException (Trap, instruction_0);
3967 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3980 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3981 SignalException (Trap, instruction_0);
3985 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3998 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3999 SignalException (Trap, instruction_0);
4003 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
4004 "tnei r<RS>, <IMMEDIATE>"
4016 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
4017 SignalException (Trap, instruction_0);
4021 :function:::void:do_xor:int rs, int rt, int rd
4023 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4024 GPR[rd] = GPR[rs] ^ GPR[rt];
4025 TRACE_ALU_RESULT (GPR[rd]);
4028 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
4029 "xor r<RD>, r<RS>, r<RT>"
4043 do_xor (SD_, RS, RT, RD);
4047 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
4049 TRACE_ALU_INPUT2 (GPR[rs], immediate);
4050 GPR[rt] = GPR[rs] ^ immediate;
4051 TRACE_ALU_RESULT (GPR[rt]);
4054 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
4055 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
4069 do_xori (SD_, RS, RT, IMMEDIATE);
4074 // MIPS Architecture:
4076 // FPU Instruction Set (COP1 & COP1X)
4084 case fmt_single: return "s";
4085 case fmt_double: return "d";
4086 case fmt_word: return "w";
4087 case fmt_long: return "l";
4088 case fmt_ps: return "ps";
4089 default: return "?";
4109 :%s::::COND:int cond
4113 case 00: return "f";
4114 case 01: return "un";
4115 case 02: return "eq";
4116 case 03: return "ueq";
4117 case 04: return "olt";
4118 case 05: return "ult";
4119 case 06: return "ole";
4120 case 07: return "ule";
4121 case 010: return "sf";
4122 case 011: return "ngle";
4123 case 012: return "seq";
4124 case 013: return "ngl";
4125 case 014: return "lt";
4126 case 015: return "nge";
4127 case 016: return "le";
4128 case 017: return "ngt";
4129 default: return "?";
4136 // Check that the given FPU format is usable, and signal a
4137 // ReservedInstruction exception if not.
4140 // check_fmt_p checks that the format is single, double, or paired single.
4141 :function:::void:check_fmt_p:int fmt, instruction_word insn
4151 /* None of these ISAs support Paired Single, so just fall back to
4152 the single/double check. */
4153 if ((fmt != fmt_single) && (fmt != fmt_double))
4154 SignalException (ReservedInstruction, insn);
4157 :function:::void:check_fmt_p:int fmt, instruction_word insn
4160 if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
4161 SignalException (ReservedInstruction, insn);
4164 :function:::void:check_fmt_p:int fmt, instruction_word insn
4169 if ((fmt != fmt_single) && (fmt != fmt_double)
4170 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
4171 SignalException (ReservedInstruction, insn);
4177 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
4178 // exception if not.
4181 :function:::void:check_fpu:
4195 if (! COP_Usable (1))
4196 SignalExceptionCoProcessorUnusable (1);
4202 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
4203 // or MIPS32. do_load cannot be used instead because it returns an
4204 // unsigned_word, which is limited to the size of the machine's registers.
4207 :function:::unsigned64:do_load_double:address_word base, address_word offset
4212 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4219 vaddr = loadstore_ea (SD_, base, offset);
4220 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4222 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4223 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4224 sim_core_unaligned_signal);
4226 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4228 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4230 v = (unsigned64)memval;
4231 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4233 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4239 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4240 // or MIPS32. do_load cannot be used instead because it returns an
4241 // unsigned_word, which is limited to the size of the machine's registers.
4244 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4249 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4255 vaddr = loadstore_ea (SD_, base, offset);
4256 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4258 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4259 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4260 sim_core_unaligned_signal);
4262 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4264 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4265 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4267 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4268 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4273 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4274 "abs.%s<FMT> f<FD>, f<FS>"
4290 check_fmt_p (SD_, fmt, instruction_0);
4291 StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
4296 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4297 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4313 check_fmt_p (SD_, fmt, instruction_0);
4314 StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4318 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
4319 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4329 check_u64 (SD_, instruction_0);
4330 fs = ValueFPR (FS, fmt_ps);
4331 if ((GPR[RS] & 0x3) != 0)
4333 if ((GPR[RS] & 0x4) == 0)
4337 ft = ValueFPR (FT, fmt_ps);
4339 fd = PackPS (PSLower (fs), PSUpper (ft));
4341 fd = PackPS (PSLower (ft), PSUpper (fs));
4343 StoreFPR (FD, fmt_ps, fd);
4352 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4353 "bc1%s<TF>%s<ND> <OFFSET>"
4359 TRACE_BRANCH_INPUT (PREVCOC1());
4360 if (PREVCOC1() == TF)
4362 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4363 TRACE_BRANCH_RESULT (dest);
4368 TRACE_BRANCH_RESULT (0);
4369 NULLIFY_NEXT_INSTRUCTION ();
4373 TRACE_BRANCH_RESULT (NIA);
4377 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4378 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4379 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4391 if (GETFCC(CC) == TF)
4393 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4398 NULLIFY_NEXT_INSTRUCTION ();
4403 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
4404 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4411 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4412 TRACE_ALU_RESULT (ValueFCR (31));
4415 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
4416 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4417 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4430 check_fmt_p (SD_, fmt, instruction_0);
4431 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4432 TRACE_ALU_RESULT (ValueFCR (31));
4436 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
4437 "ceil.l.%s<FMT> f<FD>, f<FS>"
4450 StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4455 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
4456 "ceil.w.%s<FMT> f<FD>, f<FS>"
4471 StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4476 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4484 PENDING_FILL (RT, EXTEND32 (FCR0));
4486 PENDING_FILL (RT, EXTEND32 (FCR31));
4490 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4498 if (FS == 0 || FS == 31)
4500 unsigned_word fcr = ValueFCR (FS);
4501 TRACE_ALU_INPUT1 (fcr);
4505 TRACE_ALU_RESULT (GPR[RT]);
4508 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4517 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4519 unsigned_word fcr = ValueFCR (FS);
4520 TRACE_ALU_INPUT1 (fcr);
4524 TRACE_ALU_RESULT (GPR[RT]);
4527 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4535 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4539 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4547 TRACE_ALU_INPUT1 (GPR[RT]);
4549 StoreFCR (FS, GPR[RT]);
4553 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4562 TRACE_ALU_INPUT1 (GPR[RT]);
4563 if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4564 StoreFCR (FS, GPR[RT]);
4570 // FIXME: Does not correctly differentiate between mips*
4572 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4573 "cvt.d.%s<FMT> f<FD>, f<FS>"
4589 if ((fmt == fmt_double) | 0)
4590 SignalException (ReservedInstruction, instruction_0);
4591 StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4596 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
4597 "cvt.l.%s<FMT> f<FD>, f<FS>"
4610 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4611 SignalException (ReservedInstruction, instruction_0);
4612 StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4617 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
4618 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4625 check_u64 (SD_, instruction_0);
4626 StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4627 ValueFPR (FT, fmt_single)));
4632 // FIXME: Does not correctly differentiate between mips*
4634 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4635 "cvt.s.%s<FMT> f<FD>, f<FS>"
4651 if ((fmt == fmt_single) | 0)
4652 SignalException (ReservedInstruction, instruction_0);
4653 StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4658 010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
4659 "cvt.s.pl f<FD>, f<FS>"
4666 check_u64 (SD_, instruction_0);
4667 StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4671 010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
4672 "cvt.s.pu f<FD>, f<FS>"
4679 check_u64 (SD_, instruction_0);
4680 StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4684 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4685 "cvt.w.%s<FMT> f<FD>, f<FS>"
4701 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4702 SignalException (ReservedInstruction, instruction_0);
4703 StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4708 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4709 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4725 StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4729 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4730 "dmfc1 r<RT>, f<FS>"
4735 check_u64 (SD_, instruction_0);
4736 if (SizeFGR () == 64)
4738 else if ((FS & 0x1) == 0)
4739 v = SET64HI (FGR[FS+1]) | FGR[FS];
4741 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4742 PENDING_FILL (RT, v);
4743 TRACE_ALU_RESULT (v);
4746 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4747 "dmfc1 r<RT>, f<FS>"
4757 check_u64 (SD_, instruction_0);
4758 if (SizeFGR () == 64)
4760 else if ((FS & 0x1) == 0)
4761 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4763 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4764 TRACE_ALU_RESULT (GPR[RT]);
4768 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4769 "dmtc1 r<RT>, f<FS>"
4774 check_u64 (SD_, instruction_0);
4775 if (SizeFGR () == 64)
4776 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4777 else if ((FS & 0x1) == 0)
4779 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4780 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4784 TRACE_FP_RESULT (GPR[RT]);
4787 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4788 "dmtc1 r<RT>, f<FS>"
4798 check_u64 (SD_, instruction_0);
4799 if (SizeFGR () == 64)
4800 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4801 else if ((FS & 0x1) == 0)
4802 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4808 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
4809 "floor.l.%s<FMT> f<FD>, f<FS>"
4822 StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4827 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4828 "floor.w.%s<FMT> f<FD>, f<FS>"
4843 StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4848 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4849 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4855 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4859 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4860 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4871 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4875 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
4876 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4880 COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
4884 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4885 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4893 check_u64 (SD_, instruction_0);
4894 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4898 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
4899 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4902 address_word base = GPR[BASE];
4903 address_word index = GPR[INDEX];
4904 address_word vaddr = base + index;
4906 if (SizeFGR () != 64)
4908 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
4909 if ((vaddr & 0x7) != 0)
4910 index -= (vaddr & 0x7);
4911 COP_LD (1, FD, do_load_double (SD_, base, index));
4915 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4916 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4921 address_word base = GPR[BASE];
4922 address_word index = GPR[INDEX];
4923 address_word vaddr = base + index;
4925 check_u64 (SD_, instruction_0);
4926 if (SizeFGR () != 64)
4928 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
4929 if ((vaddr & 0x7) != 0)
4930 index -= (vaddr & 0x7);
4931 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4935 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4936 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4951 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4955 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
4956 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4965 check_u64 (SD_, instruction_0);
4966 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4971 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
4972 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4982 check_u64 (SD_, instruction_0);
4983 check_fmt_p (SD_, fmt, instruction_0);
4984 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4985 ValueFPR (FR, fmt), fmt));
4989 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4997 v = EXTEND32 (FGR[FS]);
4998 PENDING_FILL (RT, v);
4999 TRACE_ALU_RESULT (v);
5002 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
5015 GPR[RT] = EXTEND32 (FGR[FS]);
5016 TRACE_ALU_RESULT (GPR[RT]);
5020 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
5021 "mov.%s<FMT> f<FD>, f<FS>"
5037 check_fmt_p (SD_, fmt, instruction_0);
5038 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
5044 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
5045 "mov%s<TF> r<RD>, r<RS>, <CC>"
5055 if (GETFCC(CC) == TF)
5062 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
5063 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
5076 if (GETFCC(CC) == TF)
5077 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
5079 StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
5084 fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
5086 PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
5088 StoreFPR (FD, fmt_ps, fd);
5093 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
5094 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
5105 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
5107 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
5114 // MOVT.fmt see MOVtf.fmt
5118 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
5119 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5130 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
5132 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
5136 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
5137 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5147 check_u64 (SD_, instruction_0);
5148 check_fmt_p (SD_, fmt, instruction_0);
5149 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5150 ValueFPR (FR, fmt), fmt));
5154 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
5161 if (SizeFGR () == 64)
5162 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
5164 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
5165 TRACE_FP_RESULT (GPR[RT]);
5168 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
5181 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
5185 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
5186 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
5202 check_fmt_p (SD_, fmt, instruction_0);
5203 StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5207 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
5208 "neg.%s<FMT> f<FD>, f<FS>"
5224 check_fmt_p (SD_, fmt, instruction_0);
5225 StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
5229 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
5230 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5240 check_u64 (SD_, instruction_0);
5241 check_fmt_p (SD_, fmt, instruction_0);
5242 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5243 ValueFPR (FR, fmt), fmt));
5247 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
5248 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5258 check_u64 (SD_, instruction_0);
5259 check_fmt_p (SD_, fmt, instruction_0);
5260 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5261 ValueFPR (FR, fmt), fmt));
5265 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
5266 "pll.ps f<FD>, f<FS>, f<FT>"
5273 check_u64 (SD_, instruction_0);
5274 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5275 PSLower (ValueFPR (FT, fmt_ps))));
5279 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
5280 "plu.ps f<FD>, f<FS>, f<FT>"
5287 check_u64 (SD_, instruction_0);
5288 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5289 PSUpper (ValueFPR (FT, fmt_ps))));
5293 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
5294 "prefx <HINT>, r<INDEX>(r<BASE>)"
5302 address_word base = GPR[BASE];
5303 address_word index = GPR[INDEX];
5305 address_word vaddr = loadstore_ea (SD_, base, index);
5308 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5309 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
5314 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
5315 "pul.ps f<FD>, f<FS>, f<FT>"
5322 check_u64 (SD_, instruction_0);
5323 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5324 PSLower (ValueFPR (FT, fmt_ps))));
5328 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
5329 "puu.ps f<FD>, f<FS>, f<FT>"
5336 check_u64 (SD_, instruction_0);
5337 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5338 PSUpper (ValueFPR (FT, fmt_ps))));
5342 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
5343 "recip.%s<FMT> f<FD>, f<FS>"
5353 StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
5357 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
5358 "round.l.%s<FMT> f<FD>, f<FS>"
5371 StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5376 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
5377 "round.w.%s<FMT> f<FD>, f<FS>"
5392 StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5397 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
5398 "rsqrt.%s<FMT> f<FD>, f<FS>"
5408 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
5412 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
5413 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5419 do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5423 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5424 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5435 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5439 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
5440 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5444 do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5448 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
5449 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5457 check_u64 (SD_, instruction_0);
5458 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5462 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
5463 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5466 address_word base = GPR[BASE];
5467 address_word index = GPR[INDEX];
5468 address_word vaddr = base + index;
5470 if (SizeFGR () != 64)
5472 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
5473 if ((vaddr & 0x7) != 0)
5474 index -= (vaddr & 0x7);
5475 do_store_double (SD_, base, index, COP_SD (1, FS));
5479 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5480 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5485 address_word base = GPR[BASE];
5486 address_word index = GPR[INDEX];
5487 address_word vaddr = base + index;
5489 check_u64 (SD_, instruction_0);
5490 if (SizeFGR () != 64)
5492 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
5493 if ((vaddr & 0x7) != 0)
5494 index -= (vaddr & 0x7);
5495 do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5499 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
5500 "sqrt.%s<FMT> f<FD>, f<FS>"
5515 StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
5519 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
5520 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5536 check_fmt_p (SD_, fmt, instruction_0);
5537 StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5542 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
5543 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5557 address_word base = GPR[BASE];
5558 address_word offset = EXTEND16 (OFFSET);
5561 address_word vaddr = loadstore_ea (SD_, base, offset);
5564 if ((vaddr & 3) != 0)
5566 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5570 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5573 uword64 memval1 = 0;
5574 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5575 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5576 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5578 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5579 byte = ((vaddr & mask) ^ bigendiancpu);
5580 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
5581 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5588 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
5589 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5598 address_word base = GPR[BASE];
5599 address_word index = GPR[INDEX];
5601 check_u64 (SD_, instruction_0);
5603 address_word vaddr = loadstore_ea (SD_, base, index);
5606 if ((vaddr & 3) != 0)
5608 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5612 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5614 unsigned64 memval = 0;
5615 unsigned64 memval1 = 0;
5616 unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5617 address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
5618 address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
5620 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5621 byte = ((vaddr & mask) ^ bigendiancpu);
5622 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
5624 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5632 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
5633 "trunc.l.%s<FMT> f<FD>, f<FS>"
5646 StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5651 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
5652 "trunc.w.%s<FMT> f<FD>, f<FS>"
5667 StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5673 // MIPS Architecture:
5675 // System Control Instruction Set (COP0)
5679 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5693 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5695 // stub needed for eCos as tx39 hardware bug workaround
5702 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5717 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5731 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5746 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5747 "cache <OP>, <OFFSET>(r<BASE>)"
5759 address_word base = GPR[BASE];
5760 address_word offset = EXTEND16 (OFFSET);
5762 address_word vaddr = loadstore_ea (SD_, base, offset);
5765 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5766 CacheOp(OP,vaddr,paddr,instruction_0);
5771 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5772 "dmfc0 r<RT>, r<RD>"
5779 check_u64 (SD_, instruction_0);
5780 DecodeCoproc (instruction_0);
5784 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5785 "dmtc0 r<RT>, r<RD>"
5792 check_u64 (SD_, instruction_0);
5793 DecodeCoproc (instruction_0);
5797 010000,1,0000000000000000000,011000:COP0:32::ERET
5809 if (SR & status_ERL)
5811 /* Oops, not yet available */
5812 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5824 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5825 "mfc0 r<RT>, r<RD> # <REGX>"
5839 TRACE_ALU_INPUT0 ();
5840 DecodeCoproc (instruction_0);
5841 TRACE_ALU_RESULT (GPR[RT]);
5844 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5845 "mtc0 r<RT>, r<RD> # <REGX>"
5859 DecodeCoproc (instruction_0);
5863 010000,1,0000000000000000000,010000:COP0:32::RFE
5874 DecodeCoproc (instruction_0);
5878 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5879 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5892 DecodeCoproc (instruction_0);
5897 010000,1,0000000000000000000,001000:COP0:32::TLBP
5912 010000,1,0000000000000000000,000001:COP0:32::TLBR
5927 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5942 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5957 :include:::mips3264r2.igen
5959 :include:::m16e.igen
5960 :include:::mdmx.igen
5961 :include:::mips3d.igen
5966 :include:::dsp2.igen
5967 :include:::smartmips.igen