sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 // start-sanitize-vr4320
  47 :model:::vr4320:mips4320:
  48 // end-sanitize-vr4320
  49 // start-sanitize-vr5400
  50 :model:::vr5400:mips5400:
  51 :model:::mdmx:mdmx:
  52 // end-sanitize-vr5400
  53 :model:::vr5000:mips5000:
  54
  55
  56
  57 // Pseudo instructions known by IGEN
  58 :internal::::illegal:
  59 {
  60   SignalException (ReservedInstruction, 0);
  61 }
  62
  63
  64 // Pseudo instructions known by interp.c
  65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  67 "rsvd <OP>"
  68 {
  69   SignalException (ReservedInstruction, instruction_0);
  70 }
  71
  72
  73
  74 //
  75 // Mips Architecture:
  76 //
  77 //        CPU Instruction Set (mipsI - mipsIV)
  78 //
  79
  80
  81 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
  82 "add r<RD>, r<RS>, r<RT>"
  83 *mipsI,mipsII,mipsIII,mipsIV:
  84 *vr5000:
  85 // start-sanitize-vr4320
  86 *vr4320:
  87 // end-sanitize-vr4320
  88 // start-sanitize-vr5400
  89 *vr5400:
  90 // end-sanitize-vr5400
  91 // start-sanitize-r5900
  92 *r5900:
  93 // end-sanitize-r5900
  94 *r3900:
  95 // start-sanitize-tx19
  96 *tx19:
  97 // end-sanitize-tx19
  98 {
  99   ALU32_BEGIN (GPR[RS]);
 100   ALU32_ADD (GPR[RT]);
 101   ALU32_END (GPR[RD]);
 102 }
 103
 104
 105 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 106 "addi r<RT>, r<RS>, IMMEDIATE"
 107 *mipsI,mipsII,mipsIII,mipsIV:
 108 *vr5000:
 109 // start-sanitize-vr4320
 110 *vr4320:
 111 // end-sanitize-vr4320
 112 // start-sanitize-vr5400
 113 *vr5400:
 114 // end-sanitize-vr5400
 115 // start-sanitize-r5900
 116 *r5900:
 117 // end-sanitize-r5900
 118 *r3900:
 119 // start-sanitize-tx19
 120 *tx19:
 121 // end-sanitize-tx19
 122 {
 123   ALU32_BEGIN (GPR[RS]);
 124   ALU32_ADD (EXTEND16 (IMMEDIATE));
 125   ALU32_END (GPR[RT]);
 126 }
 127
 128
 129 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 130 "add r<RT>, r<RS>, <IMMEDIATE>"
 131 *mipsI,mipsII,mipsIII,mipsIV:
 132 *vr5000:
 133 // start-sanitize-vr4320
 134 *vr4320:
 135 // end-sanitize-vr4320
 136 // start-sanitize-vr5400
 137 *vr5400:
 138 // end-sanitize-vr5400
 139 // start-sanitize-r5900
 140 *r5900:
 141 // end-sanitize-r5900
 142 *r3900:
 143 // start-sanitize-tx19
 144 *tx19:
 145 // end-sanitize-tx19
 146 {
 147   signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
 148   GPR[RT] = EXTEND32 (temp);
 149 }
 150
 151
 152 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 153 *mipsI,mipsII,mipsIII,mipsIV:
 154 *vr5000:
 155 // start-sanitize-vr4320
 156 *vr4320:
 157 // end-sanitize-vr4320
 158 // start-sanitize-vr5400
 159 *vr5400:
 160 // end-sanitize-vr5400
 161 // start-sanitize-r5900
 162 *r5900:
 163 // end-sanitize-r5900
 164 *r3900:
 165 // start-sanitize-tx19
 166 *tx19:
 167 // end-sanitize-tx19
 168 {
 169   signed32 temp = GPR[RS] + GPR[RT];
 170   GPR[RD] = EXTEND32 (temp);
 171 }
 172
 173
 174 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 175 "and r<RD>, r<RS>, r<RT>"
 176 *mipsI,mipsII,mipsIII,mipsIV:
 177 *vr5000:
 178 // start-sanitize-vr4320
 179 *vr4320:
 180 // end-sanitize-vr4320
 181 // start-sanitize-vr5400
 182 *vr5400:
 183 // end-sanitize-vr5400
 184 // start-sanitize-r5900
 185 *r5900:
 186 // end-sanitize-r5900
 187 *r3900:
 188 // start-sanitize-tx19
 189 *tx19:
 190 // end-sanitize-tx19
 191 {
 192   GPR[RD] = GPR[RS] & GPR[RT];
 193 }
 194
 195
 196 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 197 "and r<RT>, r<RS>, <IMMEDIATE>"
 198 *mipsI,mipsII,mipsIII,mipsIV:
 199 *vr5000:
 200 // start-sanitize-vr4320
 201 *vr4320:
 202 // end-sanitize-vr4320
 203 // start-sanitize-vr5400
 204 *vr5400:
 205 // end-sanitize-vr5400
 206 // start-sanitize-r5900
 207 *r5900:
 208 // end-sanitize-r5900
 209 *r3900:
 210 // start-sanitize-tx19
 211 *tx19:
 212 // end-sanitize-tx19
 213 {
 214   GPR[RT] = GPR[RS] & IMMEDIATE;
 215 }
 216
 217
 218 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 219 "beq r<RS>, r<RT>, <OFFSET>"
 220 *mipsI,mipsII,mipsIII,mipsIV:
 221 *vr5000:
 222 // start-sanitize-vr4320
 223 *vr4320:
 224 // end-sanitize-vr4320
 225 // start-sanitize-vr5400
 226 *vr5400:
 227 // end-sanitize-vr5400
 228 // start-sanitize-r5900
 229 *r5900:
 230 // end-sanitize-r5900
 231 *r3900:
 232 // start-sanitize-tx19
 233 *tx19:
 234 // end-sanitize-tx19
 235 {
 236   address_word offset = EXTEND16 (OFFSET) << 2;
 237   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 238     DELAY_SLOT (NIA + offset);
 239 }
 240
 241
 242 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 243 "beql r<RS>, r<RT>, <OFFSET>"
 244 *mipsII:
 245 *mipsIII:
 246 *mipsIV:
 247 *vr5000:
 248 // start-sanitize-vr4320
 249 *vr4320:
 250 // end-sanitize-vr4320
 251 // start-sanitize-vr5400
 252 *vr5400:
 253 // end-sanitize-vr5400
 254 // start-sanitize-r5900
 255 *r5900:
 256 // end-sanitize-r5900
 257 *r3900:
 258 // start-sanitize-tx19
 259 *tx19:
 260 // end-sanitize-tx19
 261 {
 262   address_word offset = EXTEND16 (OFFSET) << 2;
 263   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 264     DELAY_SLOT (NIA + offset);
 265   else
 266     NULLIFY_NEXT_INSTRUCTION ();
 267 }
 268
 269
 270 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 271 "bgez r<RS>, <OFFSET>"
 272 *mipsI,mipsII,mipsIII,mipsIV:
 273 *vr5000:
 274 // start-sanitize-vr4320
 275 *vr4320:
 276 // end-sanitize-vr4320
 277 // start-sanitize-vr5400
 278 *vr5400:
 279 // end-sanitize-vr5400
 280 // start-sanitize-r5900
 281 *r5900:
 282 // end-sanitize-r5900
 283 *r3900:
 284 // start-sanitize-tx19
 285 *tx19:
 286 // end-sanitize-tx19
 287 {
 288   address_word offset = EXTEND16 (OFFSET) << 2;
 289   if ((signed_word) GPR[RS] >= 0)
 290     DELAY_SLOT (NIA + offset);
 291 }
 292
 293
 294 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 295 "bgezal r<RS>, <OFFSET>"
 296 *mipsI,mipsII,mipsIII,mipsIV:
 297 *vr5000:
 298 // start-sanitize-vr4320
 299 *vr4320:
 300 // end-sanitize-vr4320
 301 // start-sanitize-vr5400
 302 *vr5400:
 303 // end-sanitize-vr5400
 304 // start-sanitize-r5900
 305 *r5900:
 306 // end-sanitize-r5900
 307 *r3900:
 308 // start-sanitize-tx19
 309 *tx19:
 310 // end-sanitize-tx19
 311 {
 312   address_word offset = EXTEND16 (OFFSET) << 2;
 313   RA = (CIA + 8);
 314   if ((signed_word) GPR[RS] >= 0)
 315     DELAY_SLOT (NIA + offset);
 316 }
 317
 318
 319 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 320 "bgezall r<RS>, <OFFSET>"
 321 *mipsII:
 322 *mipsIII:
 323 *mipsIV:
 324 *vr5000:
 325 // start-sanitize-vr4320
 326 *vr4320:
 327 // end-sanitize-vr4320
 328 // start-sanitize-vr5400
 329 *vr5400:
 330 // end-sanitize-vr5400
 331 // start-sanitize-r5900
 332 *r5900:
 333 // end-sanitize-r5900
 334 *r3900:
 335 // start-sanitize-tx19
 336 *tx19:
 337 // end-sanitize-tx19
 338 {
 339   address_word offset = EXTEND16 (OFFSET) << 2;
 340   RA = (CIA + 8);
 341   /* NOTE: The branch occurs AFTER the next instruction has been
 342      executed */
 343   if ((signed_word) GPR[RS] >= 0)
 344     DELAY_SLOT (NIA + offset);
 345   else
 346     NULLIFY_NEXT_INSTRUCTION ();
 347 }
 348
 349
 350 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 351 "bgezl r<RS>, <OFFSET>"
 352 *mipsII:
 353 *mipsIII:
 354 *mipsIV:
 355 *vr5000:
 356 // start-sanitize-vr4320
 357 *vr4320:
 358 // end-sanitize-vr4320
 359 // start-sanitize-vr5400
 360 *vr5400:
 361 // end-sanitize-vr5400
 362 // start-sanitize-r5900
 363 *r5900:
 364 // end-sanitize-r5900
 365 *r3900:
 366 // start-sanitize-tx19
 367 *tx19:
 368 // end-sanitize-tx19
 369 {
 370   address_word offset = EXTEND16 (OFFSET) << 2;
 371   if ((signed_word) GPR[RS] >= 0)
 372     DELAY_SLOT (NIA + offset);
 373   else
 374     NULLIFY_NEXT_INSTRUCTION ();
 375 }
 376
 377
 378 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 379 "bgtz r<RS>, <OFFSET>"
 380 *mipsI,mipsII,mipsIII,mipsIV:
 381 *vr5000:
 382 // start-sanitize-vr4320
 383 *vr4320:
 384 // end-sanitize-vr4320
 385 // start-sanitize-vr5400
 386 *vr5400:
 387 // end-sanitize-vr5400
 388 // start-sanitize-r5900
 389 *r5900:
 390 // end-sanitize-r5900
 391 *r3900:
 392 // start-sanitize-tx19
 393 *tx19:
 394 // end-sanitize-tx19
 395 {
 396   address_word offset = EXTEND16 (OFFSET) << 2;
 397   if ((signed_word) GPR[RS] > 0)
 398     DELAY_SLOT (NIA + offset);
 399 }
 400
 401
 402 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 403 "bgtzl r<RS>, <OFFSET>"
 404 *mipsII:
 405 *mipsIII:
 406 *mipsIV:
 407 *vr5000:
 408 // start-sanitize-vr4320
 409 *vr4320:
 410 // end-sanitize-vr4320
 411 // start-sanitize-vr5400
 412 *vr5400:
 413 // end-sanitize-vr5400
 414 // start-sanitize-r5900
 415 *r5900:
 416 // end-sanitize-r5900
 417 *r3900:
 418 // start-sanitize-tx19
 419 *tx19:
 420 // end-sanitize-tx19
 421 {
 422   address_word offset = EXTEND16 (OFFSET) << 2;
 423   /* NOTE: The branch occurs AFTER the next instruction has been
 424      executed */
 425   if ((signed_word) GPR[RS] > 0)
 426     DELAY_SLOT (NIA + offset);
 427   else
 428     NULLIFY_NEXT_INSTRUCTION ();
 429 }
 430
 431
 432 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 433 "blez r<RS>, <OFFSET>"
 434 *mipsI,mipsII,mipsIII,mipsIV:
 435 *vr5000:
 436 // start-sanitize-vr4320
 437 *vr4320:
 438 // end-sanitize-vr4320
 439 // start-sanitize-vr5400
 440 *vr5400:
 441 // end-sanitize-vr5400
 442 // start-sanitize-r5900
 443 *r5900:
 444 // end-sanitize-r5900
 445 *r3900:
 446 // start-sanitize-tx19
 447 *tx19:
 448 // end-sanitize-tx19
 449 {
 450   address_word offset = EXTEND16 (OFFSET) << 2;
 451   /* NOTE: The branch occurs AFTER the next instruction has been
 452      executed */
 453   if ((signed_word) GPR[RS] <= 0)
 454     DELAY_SLOT (NIA + offset);
 455 }
 456
 457
 458 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 459 "bgezl r<RS>, <OFFSET>"
 460 *mipsII:
 461 *mipsIII:
 462 *mipsIV:
 463 *vr5000:
 464 // start-sanitize-vr4320
 465 *vr4320:
 466 // end-sanitize-vr4320
 467 // start-sanitize-vr5400
 468 *vr5400:
 469 // end-sanitize-vr5400
 470 // start-sanitize-r5900
 471 *r5900:
 472 // end-sanitize-r5900
 473 *r3900:
 474 // start-sanitize-tx19
 475 *tx19:
 476 // end-sanitize-tx19
 477 {
 478   address_word offset = EXTEND16 (OFFSET) << 2;
 479   if ((signed_word) GPR[RS] <= 0)
 480     DELAY_SLOT (NIA + offset);
 481   else
 482     NULLIFY_NEXT_INSTRUCTION ();
 483 }
 484
 485
 486 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 487 "bltz r<RS>, <OFFSET>"
 488 *mipsI,mipsII,mipsIII,mipsIV:
 489 *vr5000:
 490 // start-sanitize-vr4320
 491 *vr4320:
 492 // end-sanitize-vr4320
 493 // start-sanitize-vr5400
 494 *vr5400:
 495 // end-sanitize-vr5400
 496 // start-sanitize-r5900
 497 *r5900:
 498 // end-sanitize-r5900
 499 *r3900:
 500 // start-sanitize-tx19
 501 *tx19:
 502 // end-sanitize-tx19
 503 {
 504   address_word offset = EXTEND16 (OFFSET) << 2;
 505   if ((signed_word) GPR[RS] < 0)
 506     DELAY_SLOT (NIA + offset);
 507 }
 508
 509
 510 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 511 "bltzal r<RS>, <OFFSET>"
 512 *mipsI,mipsII,mipsIII,mipsIV:
 513 *vr5000:
 514 // start-sanitize-vr4320
 515 *vr4320:
 516 // end-sanitize-vr4320
 517 // start-sanitize-vr5400
 518 *vr5400:
 519 // end-sanitize-vr5400
 520 // start-sanitize-r5900
 521 *r5900:
 522 // end-sanitize-r5900
 523 *r3900:
 524 // start-sanitize-tx19
 525 *tx19:
 526 // end-sanitize-tx19
 527 {
 528   address_word offset = EXTEND16 (OFFSET) << 2;
 529   RA = (CIA + 8);
 530   /* NOTE: The branch occurs AFTER the next instruction has been
 531      executed */
 532   if ((signed_word) GPR[RS] < 0)
 533     DELAY_SLOT (NIA + offset);
 534 }
 535
 536
 537 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 538 "bltzall r<RS>, <OFFSET>"
 539 *mipsII:
 540 *mipsIII:
 541 *mipsIV:
 542 *vr5000:
 543 // start-sanitize-vr4320
 544 *vr4320:
 545 // end-sanitize-vr4320
 546 // start-sanitize-vr5400
 547 *vr5400:
 548 // end-sanitize-vr5400
 549 // start-sanitize-r5900
 550 *r5900:
 551 // end-sanitize-r5900
 552 *r3900:
 553 // start-sanitize-tx19
 554 *tx19:
 555 // end-sanitize-tx19
 556 {
 557   address_word offset = EXTEND16 (OFFSET) << 2;
 558   RA = (CIA + 8);
 559   if ((signed_word) GPR[RS] < 0)
 560     DELAY_SLOT (NIA + offset);
 561   else
 562     NULLIFY_NEXT_INSTRUCTION ();
 563 }
 564
 565
 566 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 567 "bltzl r<RS>, <OFFSET>"
 568 *mipsII:
 569 *mipsIII:
 570 *mipsIV:
 571 *vr5000:
 572 // start-sanitize-vr4320
 573 *vr4320:
 574 // end-sanitize-vr4320
 575 // start-sanitize-vr5400
 576 *vr5400:
 577 // end-sanitize-vr5400
 578 // start-sanitize-r5900
 579 *r5900:
 580 // end-sanitize-r5900
 581 *r3900:
 582 // start-sanitize-tx19
 583 *tx19:
 584 // end-sanitize-tx19
 585 {
 586   address_word offset = EXTEND16 (OFFSET) << 2;
 587   /* NOTE: The branch occurs AFTER the next instruction has been
 588      executed */
 589   if ((signed_word) GPR[RS] < 0)
 590     DELAY_SLOT (NIA + offset);
 591   else
 592     NULLIFY_NEXT_INSTRUCTION ();
 593 }
 594
 595
 596 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 597 "bne r<RS>, r<RT>, <OFFSET>"
 598 *mipsI,mipsII,mipsIII,mipsIV:
 599 *vr5000:
 600 // start-sanitize-vr4320
 601 *vr4320:
 602 // end-sanitize-vr4320
 603 // start-sanitize-vr5400
 604 *vr5400:
 605 // end-sanitize-vr5400
 606 // start-sanitize-r5900
 607 *r5900:
 608 // end-sanitize-r5900
 609 *r3900:
 610 // start-sanitize-tx19
 611 *tx19:
 612 // end-sanitize-tx19
 613 {
 614   address_word offset = EXTEND16 (OFFSET) << 2;
 615   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 616     DELAY_SLOT (NIA + offset);
 617 }
 618
 619
 620 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 621 "bnel r<RS>, r<RT>, <OFFSET>"
 622 *mipsII:
 623 *mipsIII:
 624 *mipsIV:
 625 *vr5000:
 626 // start-sanitize-vr4320
 627 *vr4320:
 628 // end-sanitize-vr4320
 629 // start-sanitize-vr5400
 630 *vr5400:
 631 // end-sanitize-vr5400
 632 // start-sanitize-r5900
 633 *r5900:
 634 // end-sanitize-r5900
 635 *r3900:
 636 // start-sanitize-tx19
 637 *tx19:
 638 // end-sanitize-tx19
 639 {
 640   address_word offset = EXTEND16 (OFFSET) << 2;
 641   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 642     DELAY_SLOT (NIA + offset);
 643   else
 644     NULLIFY_NEXT_INSTRUCTION ();
 645 }
 646
 647
 648 000000,20.CODE,001101:SPECIAL:32::BREAK
 649 "break"
 650 *mipsI,mipsII,mipsIII,mipsIV:
 651 *vr5000:
 652 // start-sanitize-vr4320
 653 *vr4320:
 654 // end-sanitize-vr4320
 655 // start-sanitize-vr5400
 656 *vr5400:
 657 // end-sanitize-vr5400
 658 // start-sanitize-r5900
 659 *r5900:
 660 // end-sanitize-r5900
 661 *r3900:
 662 // start-sanitize-tx19
 663 *tx19:
 664 // end-sanitize-tx19
 665 {
 666   SignalException(BreakPoint, instruction_0);
 667 }
 668
 669
 670 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 671 "cop<ZZ> <COP_FUN>"
 672 *mipsI,mipsII,mipsIII,mipsIV:
 673 // start-sanitize-r5900
 674 *r5900:
 675 // end-sanitize-r5900
 676 *r3900:
 677 // start-sanitize-tx19
 678 *tx19:
 679 // end-sanitize-tx19
 680 {
 681   DecodeCoproc (instruction_0);
 682 }
 683
 684
 685 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 686 "dadd r<RD>, r<RS>, r<RT>"
 687 *mipsIII:
 688 *mipsIV:
 689 *vr5000:
 690 // start-sanitize-vr4320
 691 *vr4320:
 692 // end-sanitize-vr4320
 693 // start-sanitize-vr5400
 694 *vr5400:
 695 // end-sanitize-vr5400
 696 // start-sanitize-r5900
 697 *r5900:
 698 // end-sanitize-r5900
 699 *r3900:
 700 // start-sanitize-tx19
 701 *tx19:
 702 // end-sanitize-tx19
 703 {
 704   /* this check's for overflow */
 705   ALU64_BEGIN (GPR[RS]);
 706   ALU64_ADD (GPR[RT]);
 707   ALU64_END (GPR[RD]);
 708 }
 709
 710
 711 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 712 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 713 *mipsIII:
 714 *mipsIV:
 715 *vr5000:
 716 // start-sanitize-vr4320
 717 *vr4320:
 718 // end-sanitize-vr4320
 719 // start-sanitize-vr5400
 720 *vr5400:
 721 // end-sanitize-vr5400
 722 // start-sanitize-r5900
 723 *r5900:
 724 // end-sanitize-r5900
 725 *r3900:
 726 // start-sanitize-tx19
 727 *tx19:
 728 // end-sanitize-tx19
 729 {
 730   ALU64_BEGIN (GPR[RS]);
 731   ALU64_ADD (EXTEND16 (IMMEDIATE));
 732   ALU64_END (GPR[RT]);
 733 }
 734
 735
 736 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 737 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 738 *mipsIII:
 739 *mipsIV:
 740 *vr5000:
 741 // start-sanitize-vr4320
 742 *vr4320:
 743 // end-sanitize-vr4320
 744 // start-sanitize-vr5400
 745 *vr5400:
 746 // end-sanitize-vr5400
 747 // start-sanitize-r5900
 748 *r5900:
 749 // end-sanitize-r5900
 750 *r3900:
 751 // start-sanitize-tx19
 752 *tx19:
 753 // end-sanitize-tx19
 754 {
 755   GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
 756 }
 757
 758
 759 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 760 "daddu r<RD>, r<RS>, r<RT>"
 761 *mipsIII:
 762 *mipsIV:
 763 *vr5000:
 764 // start-sanitize-vr4320
 765 *vr4320:
 766 // end-sanitize-vr4320
 767 // start-sanitize-vr5400
 768 *vr5400:
 769 // end-sanitize-vr5400
 770 // start-sanitize-r5900
 771 *r5900:
 772 // end-sanitize-r5900
 773 *r3900:
 774 // start-sanitize-tx19
 775 *tx19:
 776 // end-sanitize-tx19
 777 {
 778   GPR[RD] = GPR[RS] + GPR[RT];
 779 }
 780
 781
 782 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 783 "ddiv r<RS>, r<RT>"
 784 *mipsIII:
 785 *mipsIV:
 786 *vr5000:
 787 // start-sanitize-vr4320
 788 *vr4320:
 789 // end-sanitize-vr4320
 790 // start-sanitize-vr5400
 791 *vr5400:
 792 // end-sanitize-vr5400
 793 // start-sanitize-r5900
 794 *r5900:
 795 // end-sanitize-r5900
 796 *r3900:
 797 // start-sanitize-tx19
 798 *tx19:
 799 // end-sanitize-tx19
 800 {
 801   CHECKHILO ("Division");
 802   {
 803     signed64 n = GPR[RS];
 804     signed64 d = GPR[RT];
 805     if (d == 0)
 806       {
 807         LO = SIGNED64 (0x8000000000000000);
 808         HI = 0;
 809       }
 810     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 811       {
 812         LO = SIGNED64 (0x8000000000000000);
 813         HI = 0;
 814       }
 815     else
 816       {
 817         LO = (n / d);
 818         HI = (n % d);
 819       }
 820   }
 821 }
 822
 823
 824
 825 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 826 "ddivu r<RS>, r<RT>"
 827 *mipsIII:
 828 *mipsIV:
 829 *r3900:
 830 *vr5000:
 831 // start-sanitize-vr4320
 832 *vr4320:
 833 // end-sanitize-vr4320
 834 // start-sanitize-vr5400
 835 *vr5400:
 836 // end-sanitize-vr5400
 837 // start-sanitize-tx19
 838 *tx19:
 839 // end-sanitize-tx19
 840 {
 841   CHECKHILO ("Division");
 842   {
 843     unsigned64 n = GPR[RS];
 844     unsigned64 d = GPR[RT];
 845     if (d == 0)
 846       {
 847         LO = SIGNED64 (0x8000000000000000);
 848         HI = 0;
 849       }
 850     else
 851       {
 852         LO = (n / d);
 853         HI = (n % d);
 854       }
 855   }
 856 }
 857
 858
 859 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 860 "div r<RS>, r<RT>"
 861 *mipsI,mipsII,mipsIII,mipsIV:
 862 *vr5000:
 863 // start-sanitize-vr4320
 864 *vr4320:
 865 // end-sanitize-vr4320
 866 // start-sanitize-vr5400
 867 *vr5400:
 868 // end-sanitize-vr5400
 869 // start-sanitize-r5900
 870 *r5900:
 871 // end-sanitize-r5900
 872 *r3900:
 873 // start-sanitize-tx19
 874 *tx19:
 875 // end-sanitize-tx19
 876 {
 877   CHECKHILO("Division");
 878   {
 879     signed32 n = GPR[RS];
 880     signed32 d = GPR[RT];
 881     if (d == 0)
 882       {
 883         LO = EXTEND32 (0x80000000);
 884         HI = EXTEND32 (0);
 885       }
 886     else if (n == SIGNED32 (0x80000000) && d == -1)
 887       {
 888         LO = EXTEND32 (0x80000000);
 889         HI = EXTEND32 (0);
 890       }
 891     else
 892       {
 893         LO = EXTEND32 (n / d);
 894         HI = EXTEND32 (n % d);
 895       }
 896   }
 897 }
 898
 899
 900 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 901 "divu r<RS>, r<RT>"
 902 *mipsI,mipsII,mipsIII,mipsIV:
 903 *vr5000:
 904 // start-sanitize-vr4320
 905 *vr4320:
 906 // end-sanitize-vr4320
 907 // start-sanitize-vr5400
 908 *vr5400:
 909 // end-sanitize-vr5400
 910 // start-sanitize-r5900
 911 *r5900:
 912 // end-sanitize-r5900
 913 *r3900:
 914 // start-sanitize-tx19
 915 *tx19:
 916 // end-sanitize-tx19
 917 {
 918   CHECKHILO ("Division");
 919   {
 920     unsigned32 n = GPR[RS];
 921     unsigned32 d = GPR[RT];
 922     if (d == 0)
 923       {
 924         LO = EXTEND32 (0x80000000);
 925         HI = EXTEND32 (0);
 926       }
 927    else
 928      {
 929        LO = EXTEND32 (n / d);
 930        HI = EXTEND32 (n % d);
 931      }
 932   }
 933 }
 934
 935
 936 :function:::void:do_dmult:int rs, int rt, int rd, int signed_p
 937 {
 938   unsigned64 lo;
 939   unsigned64 hi;
 940   unsigned64 m00;
 941   unsigned64 m01;
 942   unsigned64 m10;
 943   unsigned64 m11;
 944   unsigned64 mid;
 945   int sign;
 946   unsigned64 op1 = GPR[rs];
 947   unsigned64 op2 = GPR[rt];
 948   CHECKHILO ("Multiplication");
 949   /* make signed multiply unsigned */
 950   sign = 0;
 951   if (signed_p)
 952     {
 953       if (op1 < 0)
 954         {
 955           op1 = - op1;
 956           ++sign;
 957         }
 958       if (op2 < 0)
 959         {
 960           op2 = - op2;
 961           ++sign;
 962         }
 963     }
 964   /* multuply out the 4 sub products */
 965   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
 966   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
 967   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
 968   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
 969   /* add the products */
 970   mid = ((unsigned64) VH4_8 (m00)
 971          + (unsigned64) VL4_8 (m10)
 972          + (unsigned64) VL4_8 (m01));
 973   lo = U8_4 (mid, m00);
 974   hi = (m11
 975         + (unsigned64) VH4_8 (mid)
 976         + (unsigned64) VH4_8 (m01)
 977         + (unsigned64) VH4_8 (m10));
 978   /* fix the sign */
 979   if (sign & 1)
 980     {
 981       lo = -lo;
 982       if (lo == 0)
 983         hi = -hi;
 984       else
 985         hi = -hi - 1;
 986     }
 987   /* save the result HI/LO (and a gpr) */
 988   LO = lo;
 989   HI = hi;
 990   if (rd != 0)
 991     GPR[rd] = lo;
 992 }
 993
 994
 995 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 996 "dmult r<RS>, r<RT>"
 997 *mipsIII,mipsIV:
 998 *r3900:
 999 // start-sanitize-tx19
1000 *tx19:
1001 // end-sanitize-tx19
1002 // start-sanitize-vr4320
1003 *vr4320:
1004 // end-sanitize-vr4320
1005 {
1006   do_dmult (SD_, RS, RT, 0, 1);
1007 }
1008
1009 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1010 "dmult r<RS>, r<RT>":RD == 0
1011 "dmult r<RD>, r<RS>, r<RT>"
1012 *vr5000:
1013 // start-sanitize-vr5400
1014 *vr5400:
1015 // end-sanitize-vr5400
1016 {
1017   do_dmult (SD_, RS, RT, RD, 1);
1018 }
1019
1020
1021
1022 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1023 "dmultu r<RS>, r<RT>"
1024 *mipsIII,mipsIV:
1025 *r3900:
1026 // start-sanitize-tx19
1027 *tx19:
1028 // end-sanitize-tx19
1029 // start-sanitize-vr4320
1030 *vr4320:
1031 // end-sanitize-vr4320
1032 {
1033   do_dmult (SD_, RS, RT, 0, 0);
1034 }
1035
1036 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1037 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1038 "dmultu r<RS>, r<RT>"
1039 *vr5000:
1040 // start-sanitize-vr5400
1041 *vr5400:
1042 // end-sanitize-vr5400
1043 {
1044   do_dmult (SD_, RS, RT, RD, 0);
1045 }
1046
1047
1048
1049 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1050 "dsll r<RD>, r<RT>, <SHIFT>"
1051 *mipsIII:
1052 *mipsIV:
1053 *vr5000:
1054 // start-sanitize-vr4320
1055 *vr4320:
1056 // end-sanitize-vr4320
1057 // start-sanitize-vr5400
1058 *vr5400:
1059 // end-sanitize-vr5400
1060 // start-sanitize-r5900
1061 *r5900:
1062 // end-sanitize-r5900
1063 *r3900:
1064 // start-sanitize-tx19
1065 *tx19:
1066 // end-sanitize-tx19
1067 {
1068   int s = SHIFT;
1069   GPR[RD] = GPR[RT] << s;
1070 }
1071
1072
1073 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1074 "dsll32 r<RD>, r<RT>, <SHIFT>"
1075 *mipsIII:
1076 *mipsIV:
1077 *vr5000:
1078 // start-sanitize-vr4320
1079 *vr4320:
1080 // end-sanitize-vr4320
1081 // start-sanitize-vr5400
1082 *vr5400:
1083 // end-sanitize-vr5400
1084 // start-sanitize-r5900
1085 *r5900:
1086 // end-sanitize-r5900
1087 *r3900:
1088 // start-sanitize-tx19
1089 *tx19:
1090 // end-sanitize-tx19
1091 {
1092   int s = 32 + SHIFT;
1093   GPR[RD] = GPR[RT] << s;
1094 }
1095
1096
1097 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1098 "dsllv r<RD>, r<RT>, r<RS>"
1099 *mipsIII:
1100 *mipsIV:
1101 *vr5000:
1102 // start-sanitize-vr4320
1103 *vr4320:
1104 // end-sanitize-vr4320
1105 // start-sanitize-vr5400
1106 *vr5400:
1107 // end-sanitize-vr5400
1108 // start-sanitize-r5900
1109 *r5900:
1110 // end-sanitize-r5900
1111 *r3900:
1112 // start-sanitize-tx19
1113 *tx19:
1114 // end-sanitize-tx19
1115 {
1116   int s = MASKED64 (GPR[RS], 5, 0);
1117   GPR[RD] = GPR[RT] << s;
1118 }
1119
1120
1121 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1122 "dsra r<RD>, r<RT>, <SHIFT>"
1123 *mipsIII:
1124 *mipsIV:
1125 *vr5000:
1126 // start-sanitize-vr4320
1127 *vr4320:
1128 // end-sanitize-vr4320
1129 // start-sanitize-vr5400
1130 *vr5400:
1131 // end-sanitize-vr5400
1132 // start-sanitize-r5900
1133 *r5900:
1134 // end-sanitize-r5900
1135 *r3900:
1136 // start-sanitize-tx19
1137 *tx19:
1138 // end-sanitize-tx19
1139 {
1140   int s = SHIFT;
1141   GPR[RD] = ((signed64) GPR[RT]) >> s;
1142 }
1143
1144
1145 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1146 "dsra32 r<RT>, r<RD>, <SHIFT>"
1147 *mipsIII:
1148 *mipsIV:
1149 *vr5000:
1150 // start-sanitize-vr4320
1151 *vr4320:
1152 // end-sanitize-vr4320
1153 // start-sanitize-vr5400
1154 *vr5400:
1155 // end-sanitize-vr5400
1156 // start-sanitize-r5900
1157 *r5900:
1158 // end-sanitize-r5900
1159 *r3900:
1160 // start-sanitize-tx19
1161 *tx19:
1162 // end-sanitize-tx19
1163 {
1164   int s = 32 + SHIFT;
1165   GPR[RD] = ((signed64) GPR[RT]) >> s;
1166 }
1167
1168
1169 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1170 "dsra32 r<RT>, r<RD>, r<RS>"
1171 *mipsIII:
1172 *mipsIV:
1173 *vr5000:
1174 // start-sanitize-vr4320
1175 *vr4320:
1176 // end-sanitize-vr4320
1177 // start-sanitize-vr5400
1178 *vr5400:
1179 // end-sanitize-vr5400
1180 // start-sanitize-r5900
1181 *r5900:
1182 // end-sanitize-r5900
1183 *r3900:
1184 // start-sanitize-tx19
1185 *tx19:
1186 // end-sanitize-tx19
1187 {
1188   int s = MASKED64 (GPR[RS], 5, 0);
1189   GPR[RD] = ((signed64) GPR[RT]) >> s;
1190 }
1191
1192
1193 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1194 "dsrav r<RD>, r<RT>, <SHIFT>"
1195 *mipsIII:
1196 *mipsIV:
1197 *vr5000:
1198 // start-sanitize-vr4320
1199 *vr4320:
1200 // end-sanitize-vr4320
1201 // start-sanitize-vr5400
1202 *vr5400:
1203 // end-sanitize-vr5400
1204 // start-sanitize-r5900
1205 *r5900:
1206 // end-sanitize-r5900
1207 *r3900:
1208 // start-sanitize-tx19
1209 *tx19:
1210 // end-sanitize-tx19
1211 {
1212   int s = SHIFT;
1213   GPR[RD] = (unsigned64) GPR[RT] >> s;
1214 }
1215
1216
1217 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1218 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1219 *mipsIII:
1220 *mipsIV:
1221 *vr5000:
1222 // start-sanitize-vr4320
1223 *vr4320:
1224 // end-sanitize-vr4320
1225 // start-sanitize-vr5400
1226 *vr5400:
1227 // end-sanitize-vr5400
1228 // start-sanitize-r5900
1229 *r5900:
1230 // end-sanitize-r5900
1231 *r3900:
1232 // start-sanitize-tx19
1233 *tx19:
1234 // end-sanitize-tx19
1235 {
1236   int s = 32 + SHIFT;
1237   GPR[RD] = (unsigned64) GPR[RT] >> s;
1238 }
1239
1240
1241 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1242 "dsrl32 r<RD>, r<RT>, r<RS>"
1243 *mipsIII:
1244 *mipsIV:
1245 *vr5000:
1246 // start-sanitize-vr4320
1247 *vr4320:
1248 // end-sanitize-vr4320
1249 // start-sanitize-vr5400
1250 *vr5400:
1251 // end-sanitize-vr5400
1252 // start-sanitize-r5900
1253 *r5900:
1254 // end-sanitize-r5900
1255 *r3900:
1256 // start-sanitize-tx19
1257 *tx19:
1258 // end-sanitize-tx19
1259 {
1260   int s = MASKED64 (GPR[RS], 5, 0);
1261   GPR[RD] = (unsigned64) GPR[RT] >> s;
1262 }
1263
1264
1265 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1266 "dsub r<RD>, r<RS>, r<RT>"
1267 *mipsIII:
1268 *mipsIV:
1269 *vr5000:
1270 // start-sanitize-vr4320
1271 *vr4320:
1272 // end-sanitize-vr4320
1273 // start-sanitize-vr5400
1274 *vr5400:
1275 // end-sanitize-vr5400
1276 // start-sanitize-r5900
1277 *r5900:
1278 // end-sanitize-r5900
1279 *r3900:
1280 // start-sanitize-tx19
1281 *tx19:
1282 // end-sanitize-tx19
1283 {
1284   ALU64_BEGIN (GPR[RS]);
1285   ALU64_SUB (GPR[RT]);
1286   ALU64_END (GPR[RD]);
1287 }
1288
1289
1290 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1291 "dsubu r<RD>, r<RS>, r<RT>"
1292 *mipsIII:
1293 *mipsIV:
1294 *vr5000:
1295 // start-sanitize-vr4320
1296 *vr4320:
1297 // end-sanitize-vr4320
1298 // start-sanitize-vr5400
1299 *vr5400:
1300 // end-sanitize-vr5400
1301 // start-sanitize-r5900
1302 *r5900:
1303 // end-sanitize-r5900
1304 *r3900:
1305 // start-sanitize-tx19
1306 *tx19:
1307 // end-sanitize-tx19
1308 {
1309   GPR[RD] = GPR[RS] - GPR[RT];
1310 }
1311
1312
1313 000010,26.INSTR_INDEX:NORMAL:32::J
1314 "j <INSTR_INDEX>"
1315 *mipsI,mipsII,mipsIII,mipsIV:
1316 *vr5000:
1317 // start-sanitize-vr4320
1318 *vr4320:
1319 // end-sanitize-vr4320
1320 // start-sanitize-vr5400
1321 *vr5400:
1322 // end-sanitize-vr5400
1323 // start-sanitize-r5900
1324 *r5900:
1325 // end-sanitize-r5900
1326 *r3900:
1327 // start-sanitize-tx19
1328 *tx19:
1329 // end-sanitize-tx19
1330 {
1331   /* NOTE: The region used is that of the delay slot NIA and NOT the
1332      current instruction */
1333   address_word region = (NIA & MASK (63, 28));
1334   DELAY_SLOT (region | (INSTR_INDEX << 2));
1335 }
1336
1337
1338 000011,26.INSTR_INDEX:NORMAL:32::JAL
1339 "jal <INSTR_INDEX>"
1340 *mipsI,mipsII,mipsIII,mipsIV:
1341 *vr5000:
1342 // start-sanitize-vr4320
1343 *vr4320:
1344 // end-sanitize-vr4320
1345 // start-sanitize-vr5400
1346 *vr5400:
1347 // end-sanitize-vr5400
1348 // start-sanitize-r5900
1349 *r5900:
1350 // end-sanitize-r5900
1351 *r3900:
1352 // start-sanitize-tx19
1353 *tx19:
1354 // end-sanitize-tx19
1355 {
1356   /* NOTE: The region used is that of the delay slot and NOT the
1357      current instruction */
1358   address_word region = (NIA & MASK (63, 28));
1359   GPR[31] = CIA + 8;
1360   DELAY_SLOT (region | (INSTR_INDEX << 2));
1361 }
1362
1363
1364 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1365 "jalr r<RS>":RD == 31
1366 "jalr r<RD>, r<RS>"
1367 *mipsI,mipsII,mipsIII,mipsIV:
1368 *vr5000:
1369 // start-sanitize-vr4320
1370 *vr4320:
1371 // end-sanitize-vr4320
1372 // start-sanitize-vr5400
1373 *vr5400:
1374 // end-sanitize-vr5400
1375 // start-sanitize-r5900
1376 *r5900:
1377 // end-sanitize-r5900
1378 *r3900:
1379 // start-sanitize-tx19
1380 *tx19:
1381 // end-sanitize-tx19
1382 {
1383   address_word temp = GPR[RS];
1384   GPR[RD] = CIA + 8;
1385   DELAY_SLOT (temp);
1386 }
1387
1388
1389 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1390 "jr r<RS>"
1391 *mipsI,mipsII,mipsIII,mipsIV:
1392 *vr5000:
1393 // start-sanitize-vr4320
1394 *vr4320:
1395 // end-sanitize-vr4320
1396 // start-sanitize-vr5400
1397 *vr5400:
1398 // end-sanitize-vr5400
1399 // start-sanitize-r5900
1400 *r5900:
1401 // end-sanitize-r5900
1402 *r3900:
1403 // start-sanitize-tx19
1404 *tx19:
1405 // end-sanitize-tx19
1406 {
1407   DELAY_SLOT (GPR[RS]);
1408 }
1409
1410
1411 :function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset
1412 {
1413   address_word vaddr = offset + gpr_base;
1414   address_word paddr;
1415   int uncached;
1416   if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1417     {
1418       unsigned64 memval = 0;
1419       address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1420       unsigned int reverse = (ReverseEndian ? mask : 0);
1421       unsigned int bigend = (BigEndianCPU ? mask : 0);
1422       unsigned int byte;
1423       paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1424       LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL);
1425       byte = ((vaddr & mask) ^ bigend);
1426       GPR[rt] = EXTEND8 ((memval >> (8 * byte)));
1427     }
1428 }
1429
1430 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1431 "lb r<RT>, <OFFSET>(r<BASE>)"
1432 *mipsI,mipsII,mipsIII,mipsIV:
1433 *vr5000:
1434 // start-sanitize-vr4320
1435 *vr4320:
1436 // end-sanitize-vr4320
1437 // start-sanitize-vr5400
1438 *vr5400:
1439 // end-sanitize-vr5400
1440 // start-sanitize-r5900
1441 *r5900:
1442 // end-sanitize-r5900
1443 *r3900:
1444 // start-sanitize-tx19
1445 *tx19:
1446 // end-sanitize-tx19
1447 {
1448   do_load_byte (SD_, GPR[BASE], RT, OFFSET);
1449 #if 0
1450   unsigned32 instruction = instruction_0;
1451   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1452   int destreg = ((instruction >> 16) & 0x0000001F);
1453   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1454   {
1455     address_word vaddr = ((uword64)op1 + offset);
1456     address_word paddr;
1457     int uncached;
1458     {
1459       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1460         {
1461           uword64 memval = 0;
1462           uword64 memval1 = 0;
1463           uword64 mask = 0x7;
1464           unsigned int shift = 0;
1465           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1466           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1467           unsigned int byte;
1468           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1469           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1470           byte = ((vaddr & mask) ^ (bigend << shift));
1471           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1472         }
1473     }
1474   }
1475 #endif
1476 }
1477
1478
1479 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1480 "lbu r<RT>, <OFFSET>(r<BASE>)"
1481 *mipsI,mipsII,mipsIII,mipsIV:
1482 *vr5000:
1483 // start-sanitize-vr4320
1484 *vr4320:
1485 // end-sanitize-vr4320
1486 // start-sanitize-vr5400
1487 *vr5400:
1488 // end-sanitize-vr5400
1489 // start-sanitize-r5900
1490 *r5900:
1491 // end-sanitize-r5900
1492 *r3900:
1493 // start-sanitize-tx19
1494 *tx19:
1495 // end-sanitize-tx19
1496 {
1497   unsigned32 instruction = instruction_0;
1498   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1499   int destreg = ((instruction >> 16) & 0x0000001F);
1500   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1501   {
1502     address_word vaddr = ((unsigned64)op1 + offset);
1503     address_word paddr;
1504     int uncached;
1505     {
1506       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1507         {
1508           unsigned64 memval = 0;
1509           unsigned64 memval1 = 0;
1510           unsigned64 mask = 0x7;
1511           unsigned int shift = 0;
1512           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1513           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1514           unsigned int byte;
1515           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1516           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1517           byte = ((vaddr & mask) ^ (bigend << shift));
1518           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1519         }
1520     }
1521   }
1522 }
1523
1524
1525 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1526 "ld r<RT>, <OFFSET>(r<BASE>)"
1527 *mipsIII:
1528 *mipsIV:
1529 *vr5000:
1530 // start-sanitize-vr4320
1531 *vr4320:
1532 // end-sanitize-vr4320
1533 // start-sanitize-vr5400
1534 *vr5400:
1535 // end-sanitize-vr5400
1536 // start-sanitize-r5900
1537 *r5900:
1538 // end-sanitize-r5900
1539 *r3900:
1540 // start-sanitize-tx19
1541 *tx19:
1542 // end-sanitize-tx19
1543 {
1544   unsigned32 instruction = instruction_0;
1545   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1546   int destreg = ((instruction >> 16) & 0x0000001F);
1547   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1548   {
1549     address_word vaddr = ((unsigned64)op1 + offset);
1550     address_word paddr;
1551     int uncached;
1552     if ((vaddr & 7) != 0)
1553       SignalExceptionAddressLoad();
1554     else
1555       {
1556         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1557           {
1558             unsigned64 memval = 0;
1559             unsigned64 memval1 = 0;
1560             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1561             GPR[destreg] = memval;
1562           }
1563       }
1564   }
1565 }
1566
1567
1568 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1569 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1570 *mipsII:
1571 *mipsIII:
1572 *mipsIV:
1573 *vr5000:
1574 // start-sanitize-vr4320
1575 *vr4320:
1576 // end-sanitize-vr4320
1577 // start-sanitize-vr5400
1578 *vr5400:
1579 // end-sanitize-vr5400
1580 *r3900:
1581 // start-sanitize-tx19
1582 *tx19:
1583 // end-sanitize-tx19
1584 {
1585   unsigned32 instruction = instruction_0;
1586   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1587   int destreg = ((instruction >> 16) & 0x0000001F);
1588   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1589   {
1590     address_word vaddr = ((unsigned64)op1 + offset);
1591     address_word paddr;
1592     int uncached;
1593     if ((vaddr & 7) != 0)
1594       SignalExceptionAddressLoad();
1595     else
1596       {
1597         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1598           {
1599             unsigned64 memval = 0;
1600             unsigned64 memval1 = 0;
1601             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1602             COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1603           }
1604       }
1605   }
1606 }
1607
1608
1609 // start-sanitize-sky
1610 110110,5.BASE,5.RT,16.OFFSET:NORMAL:64::LQC2
1611 "lqc2 r<RT>, <OFFSET>(r<BASE>)"
1612 *r5900:
1613 {
1614   unsigned32 instruction = instruction_0;
1615   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1616   int destreg = ((instruction >> 16) & 0x0000001F);
1617   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1618   {
1619     address_word vaddr = ((unsigned64)op1 + offset);
1620     address_word paddr;
1621     int uncached;
1622     if ((vaddr & 0x0f) != 0)
1623       SignalExceptionAddressLoad();
1624     else
1625       {
1626         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1627           {
1628             unsigned64 memval = 0;
1629             unsigned64 memval1 = 0;
1630             unsigned128 qw = U16_8(memval, memval1); /* XXX: check order */
1631             /* XXX: block on VU0 pipeline if necessary */
1632             LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
1633             COP_LQ(((instruction >> 26) & 0x3),destreg,qw);;
1634           }
1635       }
1636   }
1637 }
1638 // end-sanitize-sky
1639
1640
1641 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1642 "ldl r<RT>, <OFFSET>(r<BASE>)"
1643 *mipsIII:
1644 *mipsIV:
1645 *vr5000:
1646 // start-sanitize-vr4320
1647 *vr4320:
1648 // end-sanitize-vr4320
1649 // start-sanitize-vr5400
1650 *vr5400:
1651 // end-sanitize-vr5400
1652 // start-sanitize-r5900
1653 *r5900:
1654 // end-sanitize-r5900
1655 *r3900:
1656 // start-sanitize-tx19
1657 *tx19:
1658 // end-sanitize-tx19
1659 {
1660   unsigned32 instruction = instruction_0;
1661   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1662   int destreg = ((instruction >> 16) & 0x0000001F);
1663   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1664   {
1665     address_word vaddr = ((unsigned64)op1 + offset);
1666     address_word paddr;
1667     int uncached;
1668     {
1669       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1670         {
1671           unsigned64 memval = 0;
1672           unsigned64 memval1 = 0;
1673           unsigned64 mask = 7;
1674           unsigned int reverse = (ReverseEndian ? mask : 0);
1675           unsigned int bigend = (BigEndianCPU ? mask : 0);
1676           int byte;
1677           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1678           byte = ((vaddr & mask) ^ bigend);
1679           if (!BigEndianMem)
1680             paddr &= ~mask;
1681           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1682           GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1683         }
1684     }
1685   }
1686 }
1687
1688
1689 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1690 "ldr r<RT>, <OFFSET>(r<BASE>)"
1691 *mipsIII:
1692 *mipsIV:
1693 *vr5000:
1694 // start-sanitize-vr4320
1695 *vr4320:
1696 // end-sanitize-vr4320
1697 // start-sanitize-vr5400
1698 *vr5400:
1699 // end-sanitize-vr5400
1700 // start-sanitize-r5900
1701 *r5900:
1702 // end-sanitize-r5900
1703 *r3900:
1704 // start-sanitize-tx19
1705 *tx19:
1706 // end-sanitize-tx19
1707 {
1708   unsigned32 instruction = instruction_0;
1709   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1710   int destreg = ((instruction >> 16) & 0x0000001F);
1711   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1712   {
1713     address_word vaddr = ((unsigned64)op1 + offset);
1714     address_word paddr;
1715     int uncached;
1716     {
1717       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1718         {
1719           unsigned64 memval = 0;
1720           unsigned64 memval1 = 0;
1721           unsigned64 mask = 7;
1722           unsigned int reverse = (ReverseEndian ? mask : 0);
1723           unsigned int bigend = (BigEndianCPU ? mask : 0);
1724           int byte;
1725           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1726           byte = ((vaddr & mask) ^ bigend);
1727           if (BigEndianMem)
1728             paddr &= ~mask;
1729           LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1730           {
1731             unsigned64 srcmask;
1732             if (byte == 0)
1733               srcmask = 0;
1734             else
1735               srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1736             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1737           }
1738         }
1739     }
1740   }
1741 }
1742
1743
1744 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1745 "lh r<RT>, <OFFSET>(r<BASE>)"
1746 *mipsI,mipsII,mipsIII,mipsIV:
1747 *vr5000:
1748 // start-sanitize-vr4320
1749 *vr4320:
1750 // end-sanitize-vr4320
1751 // start-sanitize-vr5400
1752 *vr5400:
1753 // end-sanitize-vr5400
1754 // start-sanitize-r5900
1755 *r5900:
1756 // end-sanitize-r5900
1757 *r3900:
1758 // start-sanitize-tx19
1759 *tx19:
1760 // end-sanitize-tx19
1761 {
1762   unsigned32 instruction = instruction_0;
1763   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1764   int destreg = ((instruction >> 16) & 0x0000001F);
1765   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1766   {
1767     address_word vaddr = ((unsigned64)op1 + offset);
1768     address_word paddr;
1769     int uncached;
1770     if ((vaddr & 1) != 0)
1771       SignalExceptionAddressLoad();
1772     else
1773       {
1774         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1775           {
1776             unsigned64 memval = 0;
1777             unsigned64 memval1 = 0;
1778             unsigned64 mask = 0x7;
1779             unsigned int shift = 1;
1780             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1781             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1782             unsigned int byte;
1783             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1784             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1785             byte = ((vaddr & mask) ^ (bigend << shift));
1786             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1787           }
1788       }
1789   }
1790 }
1791
1792
1793 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1794 "lhu r<RT>, <OFFSET>(r<BASE>)"
1795 *mipsI,mipsII,mipsIII,mipsIV:
1796 *vr5000:
1797 // start-sanitize-vr4320
1798 *vr4320:
1799 // end-sanitize-vr4320
1800 // start-sanitize-vr5400
1801 *vr5400:
1802 // end-sanitize-vr5400
1803 // start-sanitize-r5900
1804 *r5900:
1805 // end-sanitize-r5900
1806 *r3900:
1807 // start-sanitize-tx19
1808 *tx19:
1809 // end-sanitize-tx19
1810 {
1811   unsigned32 instruction = instruction_0;
1812   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1813   int destreg = ((instruction >> 16) & 0x0000001F);
1814   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1815   {
1816     address_word vaddr = ((unsigned64)op1 + offset);
1817     address_word paddr;
1818     int uncached;
1819     if ((vaddr & 1) != 0)
1820       SignalExceptionAddressLoad();
1821     else
1822       {
1823         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1824           {
1825             unsigned64 memval = 0;
1826             unsigned64 memval1 = 0;
1827             unsigned64 mask = 0x7;
1828             unsigned int shift = 1;
1829             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1830             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1831             unsigned int byte;
1832             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1833             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1834             byte = ((vaddr & mask) ^ (bigend << shift));
1835             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1836           }
1837       }
1838   }
1839 }
1840
1841
1842 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1843 "ll r<RT>, <OFFSET>(r<BASE>)"
1844 *mipsII:
1845 *mipsIII:
1846 *mipsIV:
1847 *vr5000:
1848 // start-sanitize-vr4320
1849 *vr4320:
1850 // end-sanitize-vr4320
1851 // start-sanitize-vr5400
1852 *vr5400:
1853 // end-sanitize-vr5400
1854 // start-sanitize-r5900
1855 *r5900:
1856 // end-sanitize-r5900
1857 *r3900:
1858 // start-sanitize-tx19
1859 *tx19:
1860 // end-sanitize-tx19
1861 {
1862   unsigned32 instruction = instruction_0;
1863   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1864   int destreg = ((instruction >> 16) & 0x0000001F);
1865   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1866   {
1867     address_word vaddr = ((unsigned64)op1 + offset);
1868     address_word paddr;
1869     int uncached;
1870     if ((vaddr & 3) != 0)
1871       SignalExceptionAddressLoad();
1872     else
1873       {
1874         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1875           {
1876             unsigned64 memval = 0;
1877             unsigned64 memval1 = 0;
1878             unsigned64 mask = 0x7;
1879             unsigned int shift = 2;
1880             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1881             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1882             unsigned int byte;
1883             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1884             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1885             byte = ((vaddr & mask) ^ (bigend << shift));
1886             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1887             LLBIT = 1;
1888           }
1889       }
1890   }
1891 }
1892
1893
1894 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1895 "lld r<RT>, <OFFSET>(r<BASE>)"
1896 *mipsIII:
1897 *mipsIV:
1898 *vr5000:
1899 // start-sanitize-vr4320
1900 *vr4320:
1901 // end-sanitize-vr4320
1902 // start-sanitize-vr5400
1903 *vr5400:
1904 // end-sanitize-vr5400
1905 // start-sanitize-r5900
1906 *r5900:
1907 // end-sanitize-r5900
1908 *r3900:
1909 // start-sanitize-tx19
1910 *tx19:
1911 // end-sanitize-tx19
1912 {
1913   unsigned32 instruction = instruction_0;
1914   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1915   int destreg = ((instruction >> 16) & 0x0000001F);
1916   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1917   {
1918     address_word vaddr = ((unsigned64)op1 + offset);
1919     address_word paddr;
1920     int uncached;
1921     if ((vaddr & 7) != 0)
1922       SignalExceptionAddressLoad();
1923     else
1924       {
1925         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1926           {
1927             unsigned64 memval = 0;
1928             unsigned64 memval1 = 0;
1929             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1930             GPR[destreg] = memval;
1931             LLBIT = 1;
1932           }
1933       }
1934   }
1935 }
1936
1937
1938 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1939 "lui r<RT>, <IMMEDIATE>"
1940 *mipsI,mipsII,mipsIII,mipsIV:
1941 *vr5000:
1942 // start-sanitize-vr4320
1943 *vr4320:
1944 // end-sanitize-vr4320
1945 // start-sanitize-vr5400
1946 *vr5400:
1947 // end-sanitize-vr5400
1948 // start-sanitize-r5900
1949 *r5900:
1950 // end-sanitize-r5900
1951 *r3900:
1952 // start-sanitize-tx19
1953 *tx19:
1954 // end-sanitize-tx19
1955 {
1956   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1957 }
1958
1959
1960 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1961 "lw r<RT>, <OFFSET>(r<BASE>)"
1962 *mipsI,mipsII,mipsIII,mipsIV:
1963 *vr5000:
1964 // start-sanitize-vr4320
1965 *vr4320:
1966 // end-sanitize-vr4320
1967 // start-sanitize-vr5400
1968 *vr5400:
1969 // end-sanitize-vr5400
1970 // start-sanitize-r5900
1971 *r5900:
1972 // end-sanitize-r5900
1973 *r3900:
1974 // start-sanitize-tx19
1975 *tx19:
1976 // end-sanitize-tx19
1977 {
1978   unsigned32 instruction = instruction_0;
1979   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1980   int destreg = ((instruction >> 16) & 0x0000001F);
1981   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1982   {
1983     address_word vaddr = ((unsigned64)op1 + offset);
1984     address_word paddr;
1985     int uncached;
1986     if ((vaddr & 3) != 0)
1987       SignalExceptionAddressLoad();
1988     else
1989       {
1990         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1991           {
1992             unsigned64 memval = 0;
1993             unsigned64 memval1 = 0;
1994             unsigned64 mask = 0x7;
1995             unsigned int shift = 2;
1996             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1997             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1998             unsigned int byte;
1999             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2000             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2001             byte = ((vaddr & mask) ^ (bigend << shift));
2002             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2003           }
2004       }
2005   }
2006 }
2007
2008
2009 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2010 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2011 *mipsI,mipsII,mipsIII,mipsIV:
2012 *vr5000:
2013 // start-sanitize-vr4320
2014 *vr4320:
2015 // end-sanitize-vr4320
2016 // start-sanitize-vr5400
2017 *vr5400:
2018 // end-sanitize-vr5400
2019 // start-sanitize-r5900
2020 *r5900:
2021 // end-sanitize-r5900
2022 *r3900:
2023 // start-sanitize-tx19
2024 *tx19:
2025 // end-sanitize-tx19
2026 {
2027   unsigned32 instruction = instruction_0;
2028   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2029   int destreg = ((instruction >> 16) & 0x0000001F);
2030   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2031   {
2032     address_word vaddr = ((unsigned64)op1 + offset);
2033     address_word paddr;
2034     int uncached;
2035     if ((vaddr & 3) != 0)
2036       SignalExceptionAddressLoad();
2037     else
2038       {
2039         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2040           {
2041             unsigned64 memval = 0;
2042             unsigned64 memval1 = 0;
2043             unsigned64 mask = 0x7;
2044             unsigned int shift = 2;
2045             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2046             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2047             unsigned int byte;
2048             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2049             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2050             byte = ((vaddr & mask) ^ (bigend << shift));
2051             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
2052           }
2053       }
2054   }
2055 }
2056
2057
2058 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2059 "lwl r<RT>, <OFFSET>(r<BASE>)"
2060 *mipsI,mipsII,mipsIII,mipsIV:
2061 *vr5000:
2062 // start-sanitize-vr4320
2063 *vr4320:
2064 // end-sanitize-vr4320
2065 // start-sanitize-vr5400
2066 *vr5400:
2067 // end-sanitize-vr5400
2068 // start-sanitize-r5900
2069 *r5900:
2070 // end-sanitize-r5900
2071 *r3900:
2072 // start-sanitize-tx19
2073 *tx19:
2074 // end-sanitize-tx19
2075 {
2076   unsigned32 instruction = instruction_0;
2077   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2078   int destreg = ((instruction >> 16) & 0x0000001F);
2079   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2080   {
2081     address_word vaddr = ((unsigned64)op1 + offset);
2082     address_word paddr;
2083     int uncached;
2084     {
2085       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2086         {
2087           unsigned64 memval = 0;
2088           unsigned64 memval1 = 0;
2089           unsigned64 mask = 3;
2090           unsigned int reverse = (ReverseEndian ? mask : 0);
2091           unsigned int bigend = (BigEndianCPU ? mask : 0);
2092           int byte;
2093           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2094           byte = ((vaddr & mask) ^ bigend);
2095           if (!BigEndianMem)
2096             paddr &= ~mask;
2097           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
2098           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2099             memval >>= 32;
2100           }
2101           GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
2102           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
2103         }
2104     }
2105   }
2106 }
2107
2108
2109 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2110 "lwr r<RT>, <OFFSET>(r<BASE>)"
2111 *mipsI,mipsII,mipsIII,mipsIV:
2112 *vr5000:
2113 // start-sanitize-vr4320
2114 *vr4320:
2115 // end-sanitize-vr4320
2116 // start-sanitize-vr5400
2117 *vr5400:
2118 // end-sanitize-vr5400
2119 // start-sanitize-r5900
2120 *r5900:
2121 // end-sanitize-r5900
2122 *r3900:
2123 // start-sanitize-tx19
2124 *tx19:
2125 // end-sanitize-tx19
2126 {
2127   unsigned32 instruction = instruction_0;
2128   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2129   int destreg = ((instruction >> 16) & 0x0000001F);
2130   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2131   {
2132     address_word vaddr = ((unsigned64)op1 + offset);
2133     address_word paddr;
2134     int uncached;
2135     {
2136       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2137         {
2138           unsigned64 memval = 0;
2139           unsigned64 memval1 = 0;
2140           unsigned64 mask = 3;
2141           unsigned int reverse = (ReverseEndian ? mask : 0);
2142           unsigned int bigend = (BigEndianCPU ? mask : 0);
2143           int byte;
2144           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2145           byte = ((vaddr & mask) ^ bigend);
2146           if (BigEndianMem)
2147             paddr &= ~mask;
2148           LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
2149           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2150             memval >>= 32;
2151           }
2152           {
2153             unsigned64 srcmask;
2154             if (byte == 0)
2155               srcmask = 0;
2156             else
2157               srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
2158             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
2159           }
2160           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
2161         }
2162     }
2163   }
2164 }
2165
2166
2167 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2168 "lwu r<RT>, <OFFSET>(r<BASE>)"
2169 *mipsIII:
2170 *mipsIV:
2171 *vr5000:
2172 // start-sanitize-vr4320
2173 *vr4320:
2174 // end-sanitize-vr4320
2175 // start-sanitize-vr5400
2176 *vr5400:
2177 // end-sanitize-vr5400
2178 // start-sanitize-r5900
2179 *r5900:
2180 // end-sanitize-r5900
2181 *r3900:
2182 // start-sanitize-tx19
2183 *tx19:
2184 // end-sanitize-tx19
2185 {
2186   unsigned32 instruction = instruction_0;
2187   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2188   int destreg = ((instruction >> 16) & 0x0000001F);
2189   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2190   {
2191     address_word vaddr = ((unsigned64)op1 + offset);
2192     address_word paddr;
2193     int uncached;
2194     if ((vaddr & 3) != 0)
2195       SignalExceptionAddressLoad();
2196     else
2197       {
2198         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2199           {
2200             unsigned64 memval = 0;
2201             unsigned64 memval1 = 0;
2202             unsigned64 mask = 0x7;
2203             unsigned int shift = 2;
2204             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2205             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2206             unsigned int byte;
2207             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2208             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2209             byte = ((vaddr & mask) ^ (bigend << shift));
2210             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
2211           }
2212       }
2213   }
2214 }
2215
2216
2217 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2218 "mfhi r<RD>"
2219 *mipsI,mipsII,mipsIII,mipsIV:
2220 *vr5000:
2221 // start-sanitize-vr4320
2222 *vr4320:
2223 // end-sanitize-vr4320
2224 // start-sanitize-vr5400
2225 *vr5400:
2226 // end-sanitize-vr5400
2227 // start-sanitize-r5900
2228 *r5900:
2229 // end-sanitize-r5900
2230 *r3900:
2231 // start-sanitize-tx19
2232 *tx19:
2233 // end-sanitize-tx19
2234 {
2235   GPR[RD] = HI;
2236 #if 0
2237   HIACCESS = 3;
2238 #endif
2239 }
2240
2241
2242 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2243 "mflo r<RD>"
2244 *mipsI,mipsII,mipsIII,mipsIV:
2245 *vr5000:
2246 // start-sanitize-vr4320
2247 *vr4320:
2248 // end-sanitize-vr4320
2249 // start-sanitize-vr5400
2250 *vr5400:
2251 // end-sanitize-vr5400
2252 // start-sanitize-r5900
2253 *r5900:
2254 // end-sanitize-r5900
2255 *r3900:
2256 // start-sanitize-tx19
2257 *tx19:
2258 // end-sanitize-tx19
2259 {
2260   GPR[RD] = LO;
2261 #if 0
2262   LOACCESS = 3; /* 3rd instruction will be safe */
2263 #endif
2264 }
2265
2266
2267 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2268 "movn r<RD>, r<RS>, r<RT>"
2269 *mipsIV:
2270 *vr5000:
2271 // start-sanitize-vr4320
2272 *vr4320:
2273 // end-sanitize-vr4320
2274 // start-sanitize-vr5400
2275 *vr5400:
2276 // end-sanitize-vr5400
2277 // start-sanitize-r5900
2278 *r5900:
2279 // end-sanitize-r5900
2280 {
2281   if (GPR[RT] != 0)
2282     GPR[RD] = GPR[RS];
2283 }
2284
2285
2286 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2287 "movz r<RD>, r<RS>, r<RT>"
2288 *mipsIV:
2289 *vr5000:
2290 // start-sanitize-vr4320
2291 *vr4320:
2292 // end-sanitize-vr4320
2293 // start-sanitize-vr5400
2294 *vr5400:
2295 // end-sanitize-vr5400
2296 // start-sanitize-r5900
2297 *r5900:
2298 // end-sanitize-r5900
2299 {
2300   if (GPR[RT] == 0)
2301     GPR[RD] = GPR[RS];
2302 }
2303
2304
2305 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2306 "mthi r<RS>"
2307 *mipsI,mipsII,mipsIII,mipsIV:
2308 *vr5000:
2309 // start-sanitize-vr4320
2310 *vr4320:
2311 // end-sanitize-vr4320
2312 // start-sanitize-vr5400
2313 *vr5400:
2314 // end-sanitize-vr5400
2315 // start-sanitize-r5900
2316 *r5900:
2317 // end-sanitize-r5900
2318 *r3900:
2319 // start-sanitize-tx19
2320 *tx19:
2321 // end-sanitize-tx19
2322 {
2323 #if 0
2324   if (HIACCESS != 0)
2325     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2326 #endif
2327   HI = GPR[RS];
2328 #if 0
2329   HIACCESS = 3; /* 3rd instruction will be safe */
2330 #endif
2331 }
2332
2333
2334 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2335 "mtlo r<RS>"
2336 *mipsI,mipsII,mipsIII,mipsIV:
2337 *vr5000:
2338 // start-sanitize-vr4320
2339 *vr4320:
2340 // end-sanitize-vr4320
2341 // start-sanitize-vr5400
2342 *vr5400:
2343 // end-sanitize-vr5400
2344 // start-sanitize-r5900
2345 *r5900:
2346 // end-sanitize-r5900
2347 *r3900:
2348 // start-sanitize-tx19
2349 *tx19:
2350 // end-sanitize-tx19
2351 {
2352 #if 0
2353   if (LOACCESS != 0)
2354     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2355 #endif
2356   LO = GPR[RS];
2357 #if 0
2358   LOACCESS = 3; /* 3rd instruction will be safe */
2359 #endif
2360 }
2361
2362
2363 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2364 "mult r<RS>, r<RT>"
2365 *mipsI,mipsII,mipsIII,mipsIV:
2366 // start-sanitize-vr4320
2367 *vr4320:
2368 // end-sanitize-vr4320
2369 {
2370   signed64 prod;
2371   CHECKHILO ("Multiplication");
2372   prod = (((signed64)(signed32) GPR[RS])
2373           * ((signed64)(signed32) GPR[RT]));
2374   LO = EXTEND32 (VL4_8 (prod));
2375   HI = EXTEND32 (VH4_8 (prod));
2376 }
2377
2378
2379 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2380 "mult r<RD>, r<RS>, r<RT>"
2381 *vr5000:
2382 // start-sanitize-vr5400
2383 *vr5400:
2384 // end-sanitize-vr5400
2385 // start-sanitize-r5900
2386 *r5900:
2387 // end-sanitize-r5900
2388 *r3900:
2389 // start-sanitize-tx19
2390 *tx19:
2391 // end-sanitize-tx19
2392 {
2393   signed64 prod;
2394   CHECKHILO ("Multiplication");
2395   prod = (((signed64)(signed32) GPR[RS])
2396           * ((signed64)(signed32) GPR[RT]));
2397   LO = EXTEND32 (VL4_8 (prod));
2398   HI = EXTEND32 (VH4_8 (prod));
2399   if (RD != 0)
2400     GPR[RD] = LO;
2401 }
2402
2403
2404 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2405 "multu r<RS>, r<RT>"
2406 *mipsI,mipsII,mipsIII,mipsIV:
2407 // start-sanitize-vr4320
2408 *vr4320:
2409 // end-sanitize-vr4320
2410 {
2411   unsigned64 prod;
2412   CHECKHILO ("Multiplication");
2413   prod = (((unsigned64)(unsigned32) GPR[RS])
2414           * ((unsigned64)(unsigned32) GPR[RT]));
2415   LO = EXTEND32 (VL4_8 (prod));
2416   HI = EXTEND32 (VH4_8 (prod));
2417 }
2418 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2419 "multu r<RD>, r<RS>, r<RT>"
2420 *vr5000:
2421 // start-sanitize-vr5400
2422 *vr5400:
2423 // end-sanitize-vr5400
2424 // start-sanitize-r5900
2425 *r5900:
2426 // end-sanitize-r5900
2427 *r3900:
2428 // start-sanitize-tx19
2429 *tx19:
2430 // end-sanitize-tx19
2431 {
2432   unsigned64 prod;
2433   CHECKHILO ("Multiplication");
2434   prod = (((unsigned64)(unsigned32) GPR[RS])
2435           * ((unsigned64)(unsigned32) GPR[RT]));
2436   LO = EXTEND32 (VL4_8 (prod));
2437   HI = EXTEND32 (VH4_8 (prod));
2438   if (RD != 0)
2439     GPR[RD] = LO;
2440 }
2441
2442
2443 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2444 "nor r<RD>, r<RS>, r<RT>"
2445 *mipsI,mipsII,mipsIII,mipsIV:
2446 *vr5000:
2447 // start-sanitize-vr4320
2448 *vr4320:
2449 // end-sanitize-vr4320
2450 // start-sanitize-vr5400
2451 *vr5400:
2452 // end-sanitize-vr5400
2453 // start-sanitize-r5900
2454 *r5900:
2455 // end-sanitize-r5900
2456 *r3900:
2457 // start-sanitize-tx19
2458 *tx19:
2459 // end-sanitize-tx19
2460 {
2461   GPR[RD] = ~ (GPR[RS] | GPR[RT]);
2462 }
2463
2464
2465 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2466 "or r<RD>, r<RS>, r<RT>"
2467 *mipsI,mipsII,mipsIII,mipsIV:
2468 *vr5000:
2469 // start-sanitize-vr4320
2470 *vr4320:
2471 // end-sanitize-vr4320
2472 // start-sanitize-vr5400
2473 *vr5400:
2474 // end-sanitize-vr5400
2475 // start-sanitize-r5900
2476 *r5900:
2477 // end-sanitize-r5900
2478 *r3900:
2479 // start-sanitize-tx19
2480 *tx19:
2481 // end-sanitize-tx19
2482 {
2483   GPR[RD] = (GPR[RS] | GPR[RT]);
2484 }
2485
2486
2487 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2488 "ori r<RT>, r<RS>, <IMMEDIATE>"
2489 *mipsI,mipsII,mipsIII,mipsIV:
2490 *vr5000:
2491 // start-sanitize-vr4320
2492 *vr4320:
2493 // end-sanitize-vr4320
2494 // start-sanitize-vr5400
2495 *vr5400:
2496 // end-sanitize-vr5400
2497 // start-sanitize-r5900
2498 *r5900:
2499 // end-sanitize-r5900
2500 *r3900:
2501 // start-sanitize-tx19
2502 *tx19:
2503 // end-sanitize-tx19
2504 {
2505   GPR[RT] = (GPR[RS] | IMMEDIATE);
2506 }
2507
2508
2509 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2510 *mipsIV:
2511 *vr5000:
2512 // start-sanitize-vr4320
2513 *vr4320:
2514 // end-sanitize-vr4320
2515 // start-sanitize-vr5400
2516 *vr5400:
2517 // end-sanitize-vr5400
2518 // start-sanitize-r5900
2519 *r5900:
2520 // end-sanitize-r5900
2521 {
2522   unsigned32 instruction = instruction_0;
2523   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2524   int hint = ((instruction >> 16) & 0x0000001F);
2525   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2526   {
2527     address_word vaddr = ((unsigned64)op1 + offset);
2528     address_word paddr;
2529     int uncached;
2530     {
2531       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2532         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2533     }
2534   }
2535 }
2536
2537 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2538 "sb r<RT>, <OFFSET>(r<BASE>)"
2539 *mipsI,mipsII,mipsIII,mipsIV:
2540 *vr5000:
2541 // start-sanitize-vr4320
2542 *vr4320:
2543 // end-sanitize-vr4320
2544 // start-sanitize-vr5400
2545 *vr5400:
2546 // end-sanitize-vr5400
2547 // start-sanitize-r5900
2548 *r5900:
2549 // end-sanitize-r5900
2550 *r3900:
2551 // start-sanitize-tx19
2552 *tx19:
2553 // end-sanitize-tx19
2554 {
2555   unsigned32 instruction = instruction_0;
2556   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2557   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2558   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2559   {
2560     address_word vaddr = ((unsigned64)op1 + offset);
2561     address_word paddr;
2562     int uncached;
2563     {
2564       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2565         {
2566           unsigned64 memval = 0;
2567           unsigned64 memval1 = 0;
2568           unsigned64 mask = 0x7;
2569           unsigned int shift = 0;
2570           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2571           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2572           unsigned int byte;
2573           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2574           byte = ((vaddr & mask) ^ (bigend << shift));
2575           memval = ((unsigned64) op2 << (8 * byte));
2576           {
2577             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2578           }
2579         }
2580     }
2581   }
2582 }
2583
2584
2585 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2586 "sc r<RT>, <OFFSET>(r<BASE>)"
2587 *mipsII:
2588 *mipsIII:
2589 *mipsIV:
2590 *vr5000:
2591 // start-sanitize-vr4320
2592 *vr4320:
2593 // end-sanitize-vr4320
2594 // start-sanitize-vr5400
2595 *vr5400:
2596 // end-sanitize-vr5400
2597 // start-sanitize-r5900
2598 *r5900:
2599 // end-sanitize-r5900
2600 *r3900:
2601 // start-sanitize-tx19
2602 *tx19:
2603 // end-sanitize-tx19
2604 {
2605   unsigned32 instruction = instruction_0;
2606   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2607   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2608   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2609   {
2610     address_word vaddr = ((unsigned64)op1 + offset);
2611     address_word paddr;
2612     int uncached;
2613     if ((vaddr & 3) != 0)
2614       SignalExceptionAddressStore();
2615     else
2616       {
2617         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2618           {
2619             unsigned64 memval = 0;
2620             unsigned64 memval1 = 0;
2621             unsigned64 mask = 0x7;
2622             unsigned int byte;
2623             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2624             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2625             memval = ((unsigned64) op2 << (8 * byte));
2626             if (LLBIT)
2627               {
2628                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2629               }
2630             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2631           }
2632       }
2633   }
2634 }
2635
2636
2637 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2638 "scd r<RT>, <OFFSET>(r<BASE>)"
2639 *mipsIII:
2640 *mipsIV:
2641 *vr5000:
2642 // start-sanitize-vr4320
2643 *vr4320:
2644 // end-sanitize-vr4320
2645 // start-sanitize-vr5400
2646 *vr5400:
2647 // end-sanitize-vr5400
2648 // start-sanitize-r5900
2649 *r5900:
2650 // end-sanitize-r5900
2651 *r3900:
2652 // start-sanitize-tx19
2653 *tx19:
2654 // end-sanitize-tx19
2655 {
2656   unsigned32 instruction = instruction_0;
2657   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2658   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2659   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2660   {
2661     address_word vaddr = ((unsigned64)op1 + offset);
2662     address_word paddr;
2663     int uncached;
2664     if ((vaddr & 7) != 0)
2665       SignalExceptionAddressStore();
2666     else
2667       {
2668         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2669           {
2670             unsigned64 memval = 0;
2671             unsigned64 memval1 = 0;
2672             memval = op2;
2673             if (LLBIT)
2674               {
2675                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2676               }
2677             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2678           }
2679       }
2680   }
2681 }
2682
2683
2684 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2685 "sd r<RT>, <OFFSET>(r<BASE>)"
2686 *mipsIII:
2687 *mipsIV:
2688 *vr5000:
2689 // start-sanitize-vr4320
2690 *vr4320:
2691 // end-sanitize-vr4320
2692 // start-sanitize-vr5400
2693 *vr5400:
2694 // end-sanitize-vr5400
2695 // start-sanitize-r5900
2696 *r5900:
2697 // end-sanitize-r5900
2698 *r3900:
2699 // start-sanitize-tx19
2700 *tx19:
2701 // end-sanitize-tx19
2702 {
2703   unsigned32 instruction = instruction_0;
2704   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2705   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2706   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2707   {
2708     address_word vaddr = ((unsigned64)op1 + offset);
2709     address_word paddr;
2710     int uncached;
2711     if ((vaddr & 7) != 0)
2712       SignalExceptionAddressStore();
2713     else
2714       {
2715         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2716           {
2717             unsigned64 memval = 0;
2718             unsigned64 memval1 = 0;
2719             memval = op2;
2720             {
2721               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2722             }
2723           }
2724       }
2725   }
2726 }
2727
2728
2729 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2730 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2731 *mipsII:
2732 *mipsIII:
2733 *mipsIV:
2734 *vr5000:
2735 // start-sanitize-vr4320
2736 *vr4320:
2737 // end-sanitize-vr4320
2738 // start-sanitize-vr5400
2739 *vr5400:
2740 // end-sanitize-vr5400
2741 // start-sanitize-r5900
2742 *r5900:
2743 // end-sanitize-r5900
2744 *r3900:
2745 // start-sanitize-tx19
2746 *tx19:
2747 // end-sanitize-tx19
2748 {
2749   unsigned32 instruction = instruction_0;
2750   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2751   int destreg = ((instruction >> 16) & 0x0000001F);
2752   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2753   {
2754     address_word vaddr = ((unsigned64)op1 + offset);
2755     address_word paddr;
2756     int uncached;
2757     if ((vaddr & 7) != 0)
2758       SignalExceptionAddressStore();
2759     else
2760       {
2761         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2762           {
2763             unsigned64 memval = 0;
2764             unsigned64 memval1 = 0;
2765             memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2766             {
2767               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2768             }
2769           }
2770       }
2771   }
2772 }
2773
2774
2775 // start-sanitize-sky
2776 111010,5.BASE,5.RT,16.OFFSET:NORMAL:64::SQC2
2777 "sqc2 r<RT>, <OFFSET>(r<BASE>)"
2778 *r5900:
2779 {
2780   unsigned32 instruction = instruction_0;
2781   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2782   int destreg = ((instruction >> 16) & 0x0000001F);
2783   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2784   {
2785     address_word vaddr = ((unsigned64)op1 + offset);
2786     address_word paddr;
2787     int uncached;
2788     if ((vaddr & 0x0f) != 0)
2789       SignalExceptionAddressStore();
2790     else
2791       {
2792         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2793           {
2794             unsigned128 qw;
2795             unsigned64 memval0 = 0;
2796             unsigned64 memval1 = 0;
2797             qw = COP_SQ(((instruction >> 26) & 0x3),destreg);
2798             memval0 = *A8_16(& qw, 0);
2799             memval1 = *A8_16(& qw, 1);
2800             {
2801               StoreMemory(uncached,AccessLength_WORD,memval0,memval1,paddr,vaddr,isREAL);
2802             }
2803           }
2804       }
2805   }
2806 }
2807 // end-sanitize-sky
2808
2809
2810
2811 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2812 "sdl r<RT>, <OFFSET>(r<BASE>)"
2813 *mipsIII:
2814 *mipsIV:
2815 *vr5000:
2816 // start-sanitize-vr4320
2817 *vr4320:
2818 // end-sanitize-vr4320
2819 // start-sanitize-vr5400
2820 *vr5400:
2821 // end-sanitize-vr5400
2822 // start-sanitize-r5900
2823 *r5900:
2824 // end-sanitize-r5900
2825 *r3900:
2826 // start-sanitize-tx19
2827 *tx19:
2828 // end-sanitize-tx19
2829 {
2830   unsigned32 instruction = instruction_0;
2831   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2832   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2833   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2834   {
2835     address_word vaddr = ((unsigned64)op1 + offset);
2836     address_word paddr;
2837     int uncached;
2838     {
2839       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2840         {
2841           unsigned64 memval = 0;
2842           unsigned64 memval1 = 0;
2843           unsigned64 mask = 7;
2844           unsigned int reverse = (ReverseEndian ? mask : 0);
2845           unsigned int bigend = (BigEndianCPU ? mask : 0);
2846           int byte;
2847           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2848           byte = ((vaddr & mask) ^ bigend);
2849           if (!BigEndianMem)
2850             paddr &= ~mask;
2851           memval = (op2 >> (8 * (7 - byte)));
2852           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2853         }
2854     }
2855   }
2856 }
2857
2858
2859 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2860 "sdr r<RT>, <OFFSET>(r<BASE>)"
2861 *mipsIII:
2862 *mipsIV:
2863 *vr5000:
2864 // start-sanitize-vr4320
2865 *vr4320:
2866 // end-sanitize-vr4320
2867 // start-sanitize-vr5400
2868 *vr5400:
2869 // end-sanitize-vr5400
2870 // start-sanitize-r5900
2871 *r5900:
2872 // end-sanitize-r5900
2873 *r3900:
2874 // start-sanitize-tx19
2875 *tx19:
2876 // end-sanitize-tx19
2877 {
2878   address_word paddr;
2879   int uncached;
2880   unsigned64 memval;
2881   unsigned64 mask = 7;
2882   unsigned int reverse = (ReverseEndian ? mask : 0);
2883   unsigned int bigend = (BigEndianCPU ? mask : 0);
2884   int byte;
2885   address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
2886   AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
2887   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2888   if (BigEndianMem)
2889     paddr &= ~mask;
2890   byte = ((vaddr & mask) ^ bigend);
2891   memval = (GPR[RT] << (byte * 8));
2892   StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,0,paddr,vaddr,isREAL);
2893 }
2894
2895
2896 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2897 "sh r<RT>, <OFFSET>(r<BASE>)"
2898 *mipsI,mipsII,mipsIII,mipsIV:
2899 *vr5000:
2900 // start-sanitize-vr4320
2901 *vr4320:
2902 // end-sanitize-vr4320
2903 // start-sanitize-vr5400
2904 *vr5400:
2905 // end-sanitize-vr5400
2906 // start-sanitize-r5900
2907 *r5900:
2908 // end-sanitize-r5900
2909 *r3900:
2910 // start-sanitize-tx19
2911 *tx19:
2912 // end-sanitize-tx19
2913 {
2914   unsigned32 instruction = instruction_0;
2915   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2916   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2917   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2918   {
2919     address_word vaddr = ((unsigned64)op1 + offset);
2920     address_word paddr;
2921     int uncached;
2922     if ((vaddr & 1) != 0)
2923       SignalExceptionAddressStore();
2924     else
2925       {
2926         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2927           {
2928             unsigned64 memval = 0;
2929             unsigned64 memval1 = 0;
2930             unsigned64 mask = 0x7;
2931             unsigned int shift = 1;
2932             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2933             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2934             unsigned int byte;
2935             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2936             byte = ((vaddr & mask) ^ (bigend << shift));
2937             memval = ((unsigned64) op2 << (8 * byte));
2938             {
2939               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2940             }
2941           }
2942       }
2943   }
2944 }
2945
2946
2947 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2948 "sll r<RD>, r<RT>, <SHIFT>"
2949 *mipsI,mipsII,mipsIII,mipsIV:
2950 *vr5000:
2951 // start-sanitize-vr4320
2952 *vr4320:
2953 // end-sanitize-vr4320
2954 // start-sanitize-vr5400
2955 *vr5400:
2956 // end-sanitize-vr5400
2957 // start-sanitize-r5900
2958 *r5900:
2959 // end-sanitize-r5900
2960 *r3900:
2961 // start-sanitize-tx19
2962 *tx19:
2963 // end-sanitize-tx19
2964 {
2965   int s = SHIFT;
2966   unsigned32 temp = (GPR[RT] << s);
2967   GPR[RD] = EXTEND32 (temp);
2968 }
2969
2970
2971 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2972 "sllv r<RD>, r<RT>, r<RS>"
2973 *mipsI,mipsII,mipsIII,mipsIV:
2974 *vr5000:
2975 // start-sanitize-vr4320
2976 *vr4320:
2977 // end-sanitize-vr4320
2978 // start-sanitize-vr5400
2979 *vr5400:
2980 // end-sanitize-vr5400
2981 // start-sanitize-r5900
2982 *r5900:
2983 // end-sanitize-r5900
2984 *r3900:
2985 // start-sanitize-tx19
2986 *tx19:
2987 // end-sanitize-tx19
2988 {
2989   int s = MASKED (GPR[RS], 4, 0);
2990   unsigned32 temp = (GPR[RT] << s);
2991   GPR[RD] = EXTEND32 (temp);
2992 }
2993
2994
2995 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2996 "slt r<RD>, r<RS>, r<RT>"
2997 *mipsI,mipsII,mipsIII,mipsIV:
2998 *vr5000:
2999 // start-sanitize-vr4320
3000 *vr4320:
3001 // end-sanitize-vr4320
3002 // start-sanitize-vr5400
3003 *vr5400:
3004 // end-sanitize-vr5400
3005 // start-sanitize-r5900
3006 *r5900:
3007 // end-sanitize-r5900
3008 *r3900:
3009 // start-sanitize-tx19
3010 *tx19:
3011 // end-sanitize-tx19
3012 {
3013   GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
3014 }
3015
3016
3017 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3018 "slti r<RT>, r<RS>, <IMMEDIATE>"
3019 *mipsI,mipsII,mipsIII,mipsIV:
3020 *vr5000:
3021 // start-sanitize-vr4320
3022 *vr4320:
3023 // end-sanitize-vr4320
3024 // start-sanitize-vr5400
3025 *vr5400:
3026 // end-sanitize-vr5400
3027 // start-sanitize-r5900
3028 *r5900:
3029 // end-sanitize-r5900
3030 *r3900:
3031 // start-sanitize-tx19
3032 *tx19:
3033 // end-sanitize-tx19
3034 {
3035   GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
3036 }
3037
3038
3039 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3040 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3041 *mipsI,mipsII,mipsIII,mipsIV:
3042 *vr5000:
3043 // start-sanitize-vr4320
3044 *vr4320:
3045 // end-sanitize-vr4320
3046 // start-sanitize-vr5400
3047 *vr5400:
3048 // end-sanitize-vr5400
3049 // start-sanitize-r5900
3050 *r5900:
3051 // end-sanitize-r5900
3052 *r3900:
3053 // start-sanitize-tx19
3054 *tx19:
3055 // end-sanitize-tx19
3056 {
3057   GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
3058 }
3059
3060 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3061 "sltu r<RD>, r<RS>, r<RT>"
3062 *mipsI,mipsII,mipsIII,mipsIV:
3063 *vr5000:
3064 // start-sanitize-vr4320
3065 *vr4320:
3066 // end-sanitize-vr4320
3067 // start-sanitize-vr5400
3068 *vr5400:
3069 // end-sanitize-vr5400
3070 // start-sanitize-r5900
3071 *r5900:
3072 // end-sanitize-r5900
3073 *r3900:
3074 // start-sanitize-tx19
3075 *tx19:
3076 // end-sanitize-tx19
3077 {
3078   GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
3079 }
3080
3081
3082 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3083 "sra r<RD>, r<RT>, <SHIFT>"
3084 *mipsI,mipsII,mipsIII,mipsIV:
3085 *vr5000:
3086 // start-sanitize-vr4320
3087 *vr4320:
3088 // end-sanitize-vr4320
3089 // start-sanitize-vr5400
3090 *vr5400:
3091 // end-sanitize-vr5400
3092 // start-sanitize-r5900
3093 *r5900:
3094 // end-sanitize-r5900
3095 *r3900:
3096 // start-sanitize-tx19
3097 *tx19:
3098 // end-sanitize-tx19
3099 {
3100   int s = SHIFT;
3101   signed32 temp = (signed32) GPR[RT] >> s;
3102   GPR[RD] = EXTEND32 (temp);
3103 }
3104
3105
3106 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3107 "srav r<RD>, r<RT>, r<RS>"
3108 *mipsI,mipsII,mipsIII,mipsIV:
3109 *vr5000:
3110 // start-sanitize-vr4320
3111 *vr4320:
3112 // end-sanitize-vr4320
3113 // start-sanitize-vr5400
3114 *vr5400:
3115 // end-sanitize-vr5400
3116 // start-sanitize-r5900
3117 *r5900:
3118 // end-sanitize-r5900
3119 *r3900:
3120 // start-sanitize-tx19
3121 *tx19:
3122 // end-sanitize-tx19
3123 {
3124   int s = MASKED (GPR[RS], 4, 0);
3125   signed32 temp = (signed32) GPR[RT] >> s;
3126   GPR[RD] = EXTEND32 (temp);
3127 }
3128
3129
3130 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3131 "srl r<RD>, r<RT>, <SHIFT>"
3132 *mipsI,mipsII,mipsIII,mipsIV:
3133 *vr5000:
3134 // start-sanitize-vr4320
3135 *vr4320:
3136 // end-sanitize-vr4320
3137 // start-sanitize-vr5400
3138 *vr5400:
3139 // end-sanitize-vr5400
3140 // start-sanitize-r5900
3141 *r5900:
3142 // end-sanitize-r5900
3143 *r3900:
3144 // start-sanitize-tx19
3145 *tx19:
3146 // end-sanitize-tx19
3147 {
3148   int s = SHIFT;
3149   unsigned32 temp = (unsigned32) GPR[RT] >> s;
3150   GPR[RD] = EXTEND32 (temp);
3151 }
3152
3153
3154 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3155 "srlv r<RD>, r<RT>, r<RS>"
3156 *mipsI,mipsII,mipsIII,mipsIV:
3157 *vr5000:
3158 // start-sanitize-vr4320
3159 *vr4320:
3160 // end-sanitize-vr4320
3161 // start-sanitize-vr5400
3162 *vr5400:
3163 // end-sanitize-vr5400
3164 // start-sanitize-r5900
3165 *r5900:
3166 // end-sanitize-r5900
3167 *r3900:
3168 // start-sanitize-tx19
3169 *tx19:
3170 // end-sanitize-tx19
3171 {
3172   int s = MASKED (GPR[RS], 4, 0);
3173   unsigned32 temp = (unsigned32) GPR[RT] >> s;
3174   GPR[RD] = EXTEND32 (temp);
3175 }
3176
3177
3178 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3179 "sub r<RD>, r<RS>, r<RT>"
3180 *mipsI,mipsII,mipsIII,mipsIV:
3181 *vr5000:
3182 // start-sanitize-vr4320
3183 *vr4320:
3184 // end-sanitize-vr4320
3185 // start-sanitize-vr5400
3186 *vr5400:
3187 // end-sanitize-vr5400
3188 // start-sanitize-r5900
3189 *r5900:
3190 // end-sanitize-r5900
3191 *r3900:
3192 // start-sanitize-tx19
3193 *tx19:
3194 // end-sanitize-tx19
3195 {
3196   ALU32_BEGIN (GPR[RS]);
3197   ALU32_SUB (GPR[RT]);
3198   ALU32_END (GPR[RD]);
3199 }
3200
3201
3202 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3203 "subu r<RD>, r<RS>, r<RT>"
3204 *mipsI,mipsII,mipsIII,mipsIV:
3205 *vr5000:
3206 // start-sanitize-vr4320
3207 *vr4320:
3208 // end-sanitize-vr4320
3209 // start-sanitize-vr5400
3210 *vr5400:
3211 // end-sanitize-vr5400
3212 // start-sanitize-r5900
3213 *r5900:
3214 // end-sanitize-r5900
3215 *r3900:
3216 // start-sanitize-tx19
3217 *tx19:
3218 // end-sanitize-tx19
3219 {
3220   GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
3221 }
3222
3223
3224 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3225 "sw r<RT>, <OFFSET>(r<BASE>)"
3226 *mipsI,mipsII,mipsIII,mipsIV:
3227 *vr5000:
3228 // start-sanitize-vr4320
3229 *vr4320:
3230 // end-sanitize-vr4320
3231 // start-sanitize-vr5400
3232 *vr5400:
3233 // end-sanitize-vr5400
3234 // start-sanitize-r5900
3235 *r5900:
3236 // end-sanitize-r5900
3237 *r3900:
3238 // start-sanitize-tx19
3239 *tx19:
3240 // end-sanitize-tx19
3241 {
3242   unsigned32 instruction = instruction_0;
3243   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3244   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3245   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3246   {
3247     address_word vaddr = ((unsigned64)op1 + offset);
3248     address_word paddr;
3249     int uncached;
3250     if ((vaddr & 3) != 0)
3251       SignalExceptionAddressStore();
3252     else
3253       {
3254         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3255           {
3256             unsigned64 memval = 0;
3257             unsigned64 memval1 = 0;
3258             unsigned64 mask = 0x7;
3259             unsigned int byte;
3260             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3261             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3262             memval = ((unsigned64) op2 << (8 * byte));
3263             {
3264               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3265             }
3266           }
3267       }
3268   }
3269 }
3270
3271
3272 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3273 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3274 *mipsI,mipsII,mipsIII,mipsIV:
3275 *vr5000:
3276 // start-sanitize-vr4320
3277 *vr4320:
3278 // end-sanitize-vr4320
3279 // start-sanitize-vr5400
3280 *vr5400:
3281 // end-sanitize-vr5400
3282 *r3900:
3283 // start-sanitize-tx19
3284 *tx19:
3285 // end-sanitize-tx19
3286 {
3287   unsigned32 instruction = instruction_0;
3288   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3289   int destreg = ((instruction >> 16) & 0x0000001F);
3290   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3291   {
3292     address_word vaddr = ((unsigned64)op1 + offset);
3293     address_word paddr;
3294     int uncached;
3295     if ((vaddr & 3) != 0)
3296       SignalExceptionAddressStore();
3297     else
3298       {
3299         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3300           {
3301             unsigned64 memval = 0;
3302             unsigned64 memval1 = 0;
3303             unsigned64 mask = 0x7;
3304             unsigned int byte;
3305             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3306             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3307             memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
3308             {
3309               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3310             }
3311           }
3312       }
3313   }
3314 }
3315
3316
3317 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3318 "swl r<RT>, <OFFSET>(r<BASE>)"
3319 *mipsI,mipsII,mipsIII,mipsIV:
3320 *vr5000:
3321 // start-sanitize-vr4320
3322 *vr4320:
3323 // end-sanitize-vr4320
3324 // start-sanitize-vr5400
3325 *vr5400:
3326 // end-sanitize-vr5400
3327 // start-sanitize-r5900
3328 *r5900:
3329 // end-sanitize-r5900
3330 *r3900:
3331 // start-sanitize-tx19
3332 *tx19:
3333 // end-sanitize-tx19
3334 {
3335   unsigned32 instruction = instruction_0;
3336   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3337   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3338   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3339   {
3340     address_word vaddr = ((unsigned64)op1 + offset);
3341     address_word paddr;
3342     int uncached;
3343     {
3344       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3345         {
3346           unsigned64 memval = 0;
3347           unsigned64 memval1 = 0;
3348           unsigned64 mask = 3;
3349           unsigned int reverse = (ReverseEndian ? mask : 0);
3350           unsigned int bigend = (BigEndianCPU ? mask : 0);
3351           int byte;
3352           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3353           byte = ((vaddr & mask) ^ bigend);
3354           if (!BigEndianMem)
3355             paddr &= ~mask;
3356           memval = (op2 >> (8 * (3 - byte)));
3357           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3358             memval <<= 32;
3359           }
3360           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
3361         }
3362     }
3363   }
3364 }
3365
3366
3367 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3368 "swr r<RT>, <OFFSET>(r<BASE>)"
3369 *mipsI,mipsII,mipsIII,mipsIV:
3370 *vr5000:
3371 // start-sanitize-vr4320
3372 *vr4320:
3373 // end-sanitize-vr4320
3374 // start-sanitize-vr5400
3375 *vr5400:
3376 // end-sanitize-vr5400
3377 // start-sanitize-r5900
3378 *r5900:
3379 // end-sanitize-r5900
3380 *r3900:
3381 // start-sanitize-tx19
3382 *tx19:
3383 // end-sanitize-tx19
3384 {
3385   unsigned64 memval = 0;
3386   unsigned64 mask = 3;
3387   unsigned int reverse = (ReverseEndian ? mask : 0);
3388   unsigned int bigend = (BigEndianCPU ? mask : 0);
3389   int byte;
3390   address_word paddr;
3391   int uncached;
3392   address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
3393   AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
3394   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3395   if (BigEndianMem)
3396     paddr &= ~mask;
3397   byte = ((vaddr & mask) ^ bigend);
3398   memval = (GPR[RT] << (byte * 8));
3399   if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2))
3400     memval <<= 32;
3401   StoreMemory(uncached,(AccessLength_WORD - byte),memval,0,paddr,vaddr,isREAL);
3402 }
3403
3404
3405 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3406 "sync":STYPE == 0
3407 "sync <STYPE>"
3408 *mipsII:
3409 *mipsIII:
3410 *mipsIV:
3411 *vr5000:
3412 // start-sanitize-vr4320
3413 *vr4320:
3414 // end-sanitize-vr4320
3415 // start-sanitize-vr5400
3416 *vr5400:
3417 // end-sanitize-vr5400
3418 // start-sanitize-r5900
3419 *r5900:
3420 // end-sanitize-r5900
3421 *r3900:
3422 // start-sanitize-tx19
3423 *tx19:
3424 // end-sanitize-tx19
3425 {
3426   SyncOperation (STYPE);
3427 }
3428
3429
3430 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3431 "syscall <CODE>"
3432 *mipsI,mipsII,mipsIII,mipsIV:
3433 *vr5000:
3434 // start-sanitize-vr4320
3435 *vr4320:
3436 // end-sanitize-vr4320
3437 // start-sanitize-vr5400
3438 *vr5400:
3439 // end-sanitize-vr5400
3440 // start-sanitize-r5900
3441 *r5900:
3442 // end-sanitize-r5900
3443 *r3900:
3444 // start-sanitize-tx19
3445 *tx19:
3446 // end-sanitize-tx19
3447 {
3448   SignalException(SystemCall, instruction_0);
3449 }
3450
3451
3452 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3453 "teq r<RS>, r<RT>"
3454 *mipsII:
3455 *mipsIII:
3456 *mipsIV:
3457 *vr5000:
3458 // start-sanitize-vr4320
3459 *vr4320:
3460 // end-sanitize-vr4320
3461 // start-sanitize-vr5400
3462 *vr5400:
3463 // end-sanitize-vr5400
3464 // start-sanitize-r5900
3465 *r5900:
3466 // end-sanitize-r5900
3467 *r3900:
3468 // start-sanitize-tx19
3469 *tx19:
3470 // end-sanitize-tx19
3471 {
3472   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3473     SignalException(Trap, instruction_0);
3474 }
3475
3476
3477 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3478 "teqi r<RS>, <IMMEDIATE>"
3479 *mipsII:
3480 *mipsIII:
3481 *mipsIV:
3482 *vr5000:
3483 // start-sanitize-vr4320
3484 *vr4320:
3485 // end-sanitize-vr4320
3486 // start-sanitize-vr5400
3487 *vr5400:
3488 // end-sanitize-vr5400
3489 // start-sanitize-r5900
3490 *r5900:
3491 // end-sanitize-r5900
3492 *r3900:
3493 // start-sanitize-tx19
3494 *tx19:
3495 // end-sanitize-tx19
3496 {
3497   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3498     SignalException(Trap, instruction_0);
3499 }
3500
3501
3502 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3503 "tge r<RS>, r<RT>"
3504 *mipsII:
3505 *mipsIII:
3506 *mipsIV:
3507 *vr5000:
3508 // start-sanitize-vr4320
3509 *vr4320:
3510 // end-sanitize-vr4320
3511 // start-sanitize-vr5400
3512 *vr5400:
3513 // end-sanitize-vr5400
3514 // start-sanitize-r5900
3515 *r5900:
3516 // end-sanitize-r5900
3517 *r3900:
3518 // start-sanitize-tx19
3519 *tx19:
3520 // end-sanitize-tx19
3521 {
3522   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3523     SignalException(Trap, instruction_0);
3524 }
3525
3526
3527 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3528 "tgei r<RS>, <IMMEDIATE>"
3529 *mipsII:
3530 *mipsIII:
3531 *mipsIV:
3532 *vr5000:
3533 // start-sanitize-vr4320
3534 *vr4320:
3535 // end-sanitize-vr4320
3536 // start-sanitize-vr5400
3537 *vr5400:
3538 // end-sanitize-vr5400
3539 // start-sanitize-r5900
3540 *r5900:
3541 // end-sanitize-r5900
3542 *r3900:
3543 // start-sanitize-tx19
3544 *tx19:
3545 // end-sanitize-tx19
3546 {
3547   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3548     SignalException(Trap, instruction_0);
3549 }
3550
3551
3552 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3553 "tgeiu r<RS>, <IMMEDIATE>"
3554 *mipsII:
3555 *mipsIII:
3556 *mipsIV:
3557 *vr5000:
3558 // start-sanitize-vr4320
3559 *vr4320:
3560 // end-sanitize-vr4320
3561 // start-sanitize-vr5400
3562 *vr5400:
3563 // end-sanitize-vr5400
3564 // start-sanitize-r5900
3565 *r5900:
3566 // end-sanitize-r5900
3567 *r3900:
3568 // start-sanitize-tx19
3569 *tx19:
3570 // end-sanitize-tx19
3571 {
3572   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3573     SignalException(Trap, instruction_0);
3574 }
3575
3576
3577 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3578 "tgeu r<RS>, r<RT>"
3579 *mipsII:
3580 *mipsIII:
3581 *mipsIV:
3582 *vr5000:
3583 // start-sanitize-vr4320
3584 *vr4320:
3585 // end-sanitize-vr4320
3586 // start-sanitize-vr5400
3587 *vr5400:
3588 // end-sanitize-vr5400
3589 // start-sanitize-r5900
3590 *r5900:
3591 // end-sanitize-r5900
3592 *r3900:
3593 // start-sanitize-tx19
3594 *tx19:
3595 // end-sanitize-tx19
3596 {
3597   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3598     SignalException(Trap, instruction_0);
3599 }
3600
3601
3602 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3603 "tlt r<RS>, r<RT>"
3604 *mipsII:
3605 *mipsIII:
3606 *mipsIV:
3607 *vr5000:
3608 // start-sanitize-vr4320
3609 *vr4320:
3610 // end-sanitize-vr4320
3611 // start-sanitize-vr5400
3612 *vr5400:
3613 // end-sanitize-vr5400
3614 // start-sanitize-r5900
3615 *r5900:
3616 // end-sanitize-r5900
3617 *r3900:
3618 // start-sanitize-tx19
3619 *tx19:
3620 // end-sanitize-tx19
3621 {
3622   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3623     SignalException(Trap, instruction_0);
3624 }
3625
3626
3627 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3628 "tlti r<RS>, <IMMEDIATE>"
3629 *mipsII:
3630 *mipsIII:
3631 *mipsIV:
3632 *vr5000:
3633 // start-sanitize-vr4320
3634 *vr4320:
3635 // end-sanitize-vr4320
3636 // start-sanitize-vr5400
3637 *vr5400:
3638 // end-sanitize-vr5400
3639 // start-sanitize-r5900
3640 *r5900:
3641 // end-sanitize-r5900
3642 *r3900:
3643 // start-sanitize-tx19
3644 *tx19:
3645 // end-sanitize-tx19
3646 {
3647   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3648     SignalException(Trap, instruction_0);
3649 }
3650
3651
3652 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3653 "tltiu r<RS>, <IMMEDIATE>"
3654 *mipsII:
3655 *mipsIII:
3656 *mipsIV:
3657 *vr5000:
3658 // start-sanitize-vr4320
3659 *vr4320:
3660 // end-sanitize-vr4320
3661 // start-sanitize-vr5400
3662 *vr5400:
3663 // end-sanitize-vr5400
3664 // start-sanitize-r5900
3665 *r5900:
3666 // end-sanitize-r5900
3667 *r3900:
3668 // start-sanitize-tx19
3669 *tx19:
3670 // end-sanitize-tx19
3671 {
3672   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3673     SignalException(Trap, instruction_0);
3674 }
3675
3676
3677 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3678 "tltu r<RS>, r<RT>"
3679 *mipsII:
3680 *mipsIII:
3681 *mipsIV:
3682 *vr5000:
3683 // start-sanitize-vr4320
3684 *vr4320:
3685 // end-sanitize-vr4320
3686 // start-sanitize-vr5400
3687 *vr5400:
3688 // end-sanitize-vr5400
3689 // start-sanitize-r5900
3690 *r5900:
3691 // end-sanitize-r5900
3692 *r3900:
3693 // start-sanitize-tx19
3694 *tx19:
3695 // end-sanitize-tx19
3696 {
3697   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3698     SignalException(Trap, instruction_0);
3699 }
3700
3701
3702 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3703 "tne r<RS>, r<RT>"
3704 *mipsII:
3705 *mipsIII:
3706 *mipsIV:
3707 *vr5000:
3708 // start-sanitize-vr4320
3709 *vr4320:
3710 // end-sanitize-vr4320
3711 // start-sanitize-vr5400
3712 *vr5400:
3713 // end-sanitize-vr5400
3714 // start-sanitize-r5900
3715 *r5900:
3716 // end-sanitize-r5900
3717 *r3900:
3718 // start-sanitize-tx19
3719 *tx19:
3720 // end-sanitize-tx19
3721 {
3722   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3723     SignalException(Trap, instruction_0);
3724 }
3725
3726
3727 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3728 "tne r<RS>, <IMMEDIATE>"
3729 *mipsII:
3730 *mipsIII:
3731 *mipsIV:
3732 *vr5000:
3733 // start-sanitize-vr4320
3734 *vr4320:
3735 // end-sanitize-vr4320
3736 // start-sanitize-vr5400
3737 *vr5400:
3738 // end-sanitize-vr5400
3739 // start-sanitize-r5900
3740 *r5900:
3741 // end-sanitize-r5900
3742 *r3900:
3743 // start-sanitize-tx19
3744 *tx19:
3745 // end-sanitize-tx19
3746 {
3747   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3748     SignalException(Trap, instruction_0);
3749 }
3750
3751
3752 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3753 "xor r<RD>, r<RS>, r<RT>"
3754 *mipsI,mipsII,mipsIII,mipsIV:
3755 *vr5000:
3756 // start-sanitize-vr4320
3757 *vr4320:
3758 // end-sanitize-vr4320
3759 // start-sanitize-vr5400
3760 *vr5400:
3761 // end-sanitize-vr5400
3762 // start-sanitize-r5900
3763 *r5900:
3764 // end-sanitize-r5900
3765 *r3900:
3766 // start-sanitize-tx19
3767 *tx19:
3768 // end-sanitize-tx19
3769 {
3770   GPR[RD] = GPR[RS] ^ GPR[RT];
3771 }
3772
3773
3774 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3775 "xori r<RT>, r<RS>, <IMMEDIATE>"
3776 *mipsI,mipsII,mipsIII,mipsIV:
3777 *vr5000:
3778 // start-sanitize-vr4320
3779 *vr4320:
3780 // end-sanitize-vr4320
3781 // start-sanitize-vr5400
3782 *vr5400:
3783 // end-sanitize-vr5400
3784 // start-sanitize-r5900
3785 *r5900:
3786 // end-sanitize-r5900
3787 *r3900:
3788 // start-sanitize-tx19
3789 *tx19:
3790 // end-sanitize-tx19
3791 {
3792   GPR[RT] = GPR[RS] ^ IMMEDIATE;
3793 }
3794
3795 \f
3796 //
3797 // MIPS Architecture:
3798 //
3799 //        FPU Instruction Set (COP1 & COP1X)
3800 //
3801
3802
3803 :%s::::FMT:int fmt
3804 {
3805   switch (fmt)
3806     {
3807     case fmt_single: return "s";
3808     case fmt_double: return "d";
3809     case fmt_word: return "w";
3810     case fmt_long: return "l";
3811     default: return "?";
3812     }
3813 }
3814
3815 :%s::::X:int x
3816 {
3817   switch (x)
3818     {
3819     case 0: return "f";
3820     case 1: return "t";
3821     default: return "?";
3822     }
3823 }
3824
3825 :%s::::TF:int tf
3826 {
3827   if (tf)
3828     return "t";
3829   else
3830     return "f";
3831 }
3832
3833 :%s::::ND:int nd
3834 {
3835   if (nd)
3836     return "l";
3837   else
3838     return "";
3839 }
3840
3841 :%s::::COND:int cond
3842 {
3843   switch (cond)
3844     {
3845     case 00: return "f";
3846     case 01: return "un";
3847     case 02: return "eq";
3848     case 03: return "ueq";
3849     case 04: return "olt";
3850     case 05: return "ult";
3851     case 06: return "ole";
3852     case 07: return "ule";
3853     case 010: return "sf";
3854     case 011: return "ngle";
3855     case 012: return "seq";
3856     case 013: return "ngl";
3857     case 014: return "lt";
3858     case 015: return "nge";
3859     case 016: return "le";
3860     case 017: return "ngt";
3861     default: return "?";
3862     }
3863 }
3864
3865
3866 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3867 "abs.%s<FMT> f<FD>, f<FS>"
3868 *mipsI,mipsII,mipsIII,mipsIV:
3869 *vr5000:
3870 // start-sanitize-vr4320
3871 *vr4320:
3872 // end-sanitize-vr4320
3873 // start-sanitize-vr5400
3874 *vr5400:
3875 // end-sanitize-vr5400
3876 *r3900:
3877 // start-sanitize-tx19
3878 *tx19:
3879 // end-sanitize-tx19
3880 {
3881   unsigned32 instruction = instruction_0;
3882   int destreg = ((instruction >> 6) & 0x0000001F);
3883   int fs = ((instruction >> 11) & 0x0000001F);
3884   int format = ((instruction >> 21) & 0x00000007);
3885   {
3886     if ((format != fmt_single) && (format != fmt_double))
3887       SignalException(ReservedInstruction,instruction);
3888     else
3889       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3890   }
3891 }
3892
3893
3894
3895 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3896 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3897 *mipsI,mipsII,mipsIII,mipsIV:
3898 *vr5000:
3899 // start-sanitize-vr4320
3900 *vr4320:
3901 // end-sanitize-vr4320
3902 // start-sanitize-vr5400
3903 *vr5400:
3904 // end-sanitize-vr5400
3905 *r3900:
3906 // start-sanitize-tx19
3907 *tx19:
3908 // end-sanitize-tx19
3909 {
3910   unsigned32 instruction = instruction_0;
3911   int destreg = ((instruction >> 6) & 0x0000001F);
3912   int fs = ((instruction >> 11) & 0x0000001F);
3913   int ft = ((instruction >> 16) & 0x0000001F);
3914   int format = ((instruction >> 21) & 0x00000007);
3915   {
3916     if ((format != fmt_single) && (format != fmt_double))
3917       SignalException(ReservedInstruction, instruction);
3918     else
3919       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3920   }
3921 }
3922
3923
3924
3925 // BC1F
3926 // BC1FL
3927 // BC1T
3928 // BC1TL
3929
3930 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3931 "bc1%s<TF>%s<ND> <OFFSET>"
3932 *mipsI,mipsII,mipsIII:
3933 // start-sanitize-r5900
3934 *r5900:
3935 // end-sanitize-r5900
3936 {
3937   TRACE_BRANCH_INPUT (PREVCOC1());
3938   if (PREVCOC1() == TF)
3939     {
3940       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3941       TRACE_BRANCH_RESULT (dest);
3942       DELAY_SLOT (dest);
3943     }
3944   else if (ND)
3945     {
3946       TRACE_BRANCH_RESULT (0);
3947       NULLIFY_NEXT_INSTRUCTION ();
3948     }
3949   else
3950     {
3951       TRACE_BRANCH_RESULT (NIA);
3952     }
3953 }
3954
3955 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3956 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3957 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3958 *mipsIV:
3959 *vr5000:
3960 // start-sanitize-vr4320
3961 *vr4320:
3962 // end-sanitize-vr4320
3963 // start-sanitize-vr5400
3964 *vr5400:
3965 // end-sanitize-vr5400
3966 *r3900:
3967 // start-sanitize-tx19
3968 *tx19:
3969 // end-sanitize-tx19
3970 {
3971   if (GETFCC(CC) == TF)
3972     {
3973       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3974     }
3975   else if (ND)
3976     {
3977       NULLIFY_NEXT_INSTRUCTION ();
3978     }
3979 }
3980
3981
3982
3983 // C.EQ.S
3984 // C.EQ.D
3985 // ...
3986
3987 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3988 {
3989   if ((fmt != fmt_single) && (fmt != fmt_double))
3990     SignalException (ReservedInstruction, insn);
3991   else
3992     {
3993       int less;
3994       int equal;
3995       int unordered;
3996       int condition;
3997       unsigned64 ofs = ValueFPR (fs, fmt);
3998       unsigned64 oft = ValueFPR (ft, fmt);
3999       if (NaN (ofs, fmt) || NaN (oft, fmt))
4000         {
4001           if (FCSR & FP_ENABLE (IO))
4002             {
4003               FCSR |= FP_CAUSE (IO);
4004               SignalExceptionFPE ();
4005             }
4006           less = 0;
4007           equal = 0;
4008           unordered = 1;
4009         }
4010       else
4011         {
4012           less = Less (ofs, oft, fmt);
4013           equal = Equal (ofs, oft, fmt);
4014           unordered = 0;
4015         }
4016       condition = (((cond & (1 << 2)) && less)
4017                    || ((cond & (1 << 1)) && equal)
4018                    || ((cond & (1 << 0)) && unordered));
4019       SETFCC (cc, condition);
4020     }
4021 }
4022
4023 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4024 *mipsI,mipsII,mipsIII:
4025 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
4026 {
4027   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4028 }
4029
4030 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4031 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4032 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4033 *mipsIV:
4034 *vr5000:
4035 // start-sanitize-vr4320
4036 *vr4320:
4037 // end-sanitize-vr4320
4038 // start-sanitize-vr5400
4039 *vr5400:
4040 // end-sanitize-vr5400
4041 *r3900:
4042 // start-sanitize-tx19
4043 *tx19:
4044 // end-sanitize-tx19
4045 {
4046   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4047 }
4048
4049
4050 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4051 "ceil.l.%s<FMT> f<FD>, f<FS>"
4052 *mipsIII:
4053 *mipsIV:
4054 *vr5000:
4055 // start-sanitize-vr4320
4056 *vr4320:
4057 // end-sanitize-vr4320
4058 // start-sanitize-vr5400
4059 *vr5400:
4060 // end-sanitize-vr5400
4061 // start-sanitize-r5900
4062 *r5900:
4063 // end-sanitize-r5900
4064 *r3900:
4065 // start-sanitize-tx19
4066 *tx19:
4067 // end-sanitize-tx19
4068 {
4069   unsigned32 instruction = instruction_0;
4070   int destreg = ((instruction >> 6) & 0x0000001F);
4071   int fs = ((instruction >> 11) & 0x0000001F);
4072   int format = ((instruction >> 21) & 0x00000007);
4073   {
4074     if ((format != fmt_single) && (format != fmt_double))
4075       SignalException(ReservedInstruction,instruction);
4076     else
4077       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4078   }
4079 }
4080
4081
4082 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4083 *mipsII:
4084 *mipsIII:
4085 *mipsIV:
4086 *vr5000:
4087 // start-sanitize-vr4320
4088 *vr4320:
4089 // end-sanitize-vr4320
4090 // start-sanitize-vr5400
4091 *vr5400:
4092 // end-sanitize-vr5400
4093 // start-sanitize-r5900
4094 *r5900:
4095 // end-sanitize-r5900
4096 *r3900:
4097 // start-sanitize-tx19
4098 *tx19:
4099 // end-sanitize-tx19
4100 {
4101   unsigned32 instruction = instruction_0;
4102   int destreg = ((instruction >> 6) & 0x0000001F);
4103   int fs = ((instruction >> 11) & 0x0000001F);
4104   int format = ((instruction >> 21) & 0x00000007);
4105   {
4106   if ((format != fmt_single) && (format != fmt_double))
4107    SignalException(ReservedInstruction,instruction);
4108   else
4109    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4110   }
4111 }
4112
4113
4114 // CFC1
4115 // CTC1
4116 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4117 "c%s<X>c1 r<RT>, f<FS>"
4118 *mipsI:
4119 *mipsII:
4120 *mipsIII:
4121 {
4122   if (X)
4123     {
4124       if (FS == 0)
4125         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4126       else if (FS == 31)
4127         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4128       /* else NOP */
4129       PENDING_FILL(COCIDX,0); /* special case */
4130     }
4131   else
4132     { /* control from */
4133       if (FS == 0)
4134         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4135       else if (FS == 31)
4136         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4137       /* else NOP */
4138     }
4139 }
4140 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4141 "c%s<X>c1 r<RT>, f<FS>"
4142 *mipsIV:
4143 *vr5000:
4144 // start-sanitize-vr4320
4145 *vr4320:
4146 // end-sanitize-vr4320
4147 // start-sanitize-vr5400
4148 *vr5400:
4149 // end-sanitize-vr5400
4150 // start-sanitize-r5900
4151 *r5900:
4152 // end-sanitize-r5900
4153 *r3900:
4154 // start-sanitize-tx19
4155 *tx19:
4156 // end-sanitize-tx19
4157 {
4158   if (X)
4159     {
4160       /* control to */
4161       TRACE_ALU_INPUT1 (GPR[RT]);
4162       if (FS == 0)
4163         {
4164           FCR0 = VL4_8(GPR[RT]);
4165           TRACE_ALU_RESULT (FCR0);
4166         }
4167       else if (FS == 31)
4168         {
4169           FCR31 = VL4_8(GPR[RT]);
4170           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4171           TRACE_ALU_RESULT (FCR31);
4172         }
4173       else
4174         {
4175           TRACE_ALU_RESULT0 ();
4176         }
4177       /* else NOP */
4178     }
4179   else
4180     { /* control from */
4181       if (FS == 0)
4182         {
4183           TRACE_ALU_INPUT1 (FCR0);
4184           GPR[RT] = SIGNEXTEND (FCR0, 32);
4185         }
4186       else if (FS == 31)
4187         {
4188           TRACE_ALU_INPUT1 (FCR31);
4189           GPR[RT] = SIGNEXTEND (FCR31, 32);
4190         }
4191       TRACE_ALU_RESULT (GPR[RT]);
4192       /* else NOP */
4193     }
4194 }
4195
4196
4197 //
4198 // FIXME: Does not correctly differentiate between mips*
4199 //
4200 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4201 "cvt.d.%s<FMT> f<FD>, f<FS>"
4202 *mipsI,mipsII,mipsIII,mipsIV:
4203 *vr5000:
4204 // start-sanitize-vr4320
4205 *vr4320:
4206 // end-sanitize-vr4320
4207 // start-sanitize-vr5400
4208 *vr5400:
4209 // end-sanitize-vr5400
4210 *r3900:
4211 // start-sanitize-tx19
4212 *tx19:
4213 // end-sanitize-tx19
4214 {
4215   unsigned32 instruction = instruction_0;
4216   int destreg = ((instruction >> 6) & 0x0000001F);
4217   int fs = ((instruction >> 11) & 0x0000001F);
4218   int format = ((instruction >> 21) & 0x00000007);
4219   {
4220     if ((format == fmt_double) | 0)
4221       SignalException(ReservedInstruction,instruction);
4222     else
4223       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4224   }
4225 }
4226
4227
4228 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4229 "cvt.l.%s<FMT> f<FD>, f<FS>"
4230 *mipsIII:
4231 *mipsIV:
4232 *vr5000:
4233 // start-sanitize-vr4320
4234 *vr4320:
4235 // end-sanitize-vr4320
4236 // start-sanitize-vr5400
4237 *vr5400:
4238 // end-sanitize-vr5400
4239 *r3900:
4240 // start-sanitize-tx19
4241 *tx19:
4242 // end-sanitize-tx19
4243 {
4244   unsigned32 instruction = instruction_0;
4245   int destreg = ((instruction >> 6) & 0x0000001F);
4246   int fs = ((instruction >> 11) & 0x0000001F);
4247   int format = ((instruction >> 21) & 0x00000007);
4248   {
4249     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4250       SignalException(ReservedInstruction,instruction);
4251     else
4252       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4253   }
4254 }
4255
4256
4257 //
4258 // FIXME: Does not correctly differentiate between mips*
4259 //
4260 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4261 "cvt.s.%s<FMT> f<FD>, f<FS>"
4262 *mipsI,mipsII,mipsIII,mipsIV:
4263 *vr5000:
4264 // start-sanitize-vr4320
4265 *vr4320:
4266 // end-sanitize-vr4320
4267 // start-sanitize-vr5400
4268 *vr5400:
4269 // end-sanitize-vr5400
4270 *r3900:
4271 // start-sanitize-tx19
4272 *tx19:
4273 // end-sanitize-tx19
4274 {
4275   unsigned32 instruction = instruction_0;
4276   int destreg = ((instruction >> 6) & 0x0000001F);
4277   int fs = ((instruction >> 11) & 0x0000001F);
4278   int format = ((instruction >> 21) & 0x00000007);
4279   {
4280     if ((format == fmt_single) | 0)
4281       SignalException(ReservedInstruction,instruction);
4282     else
4283       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4284   }
4285 }
4286
4287
4288 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4289 "cvt.w.%s<FMT> f<FD>, f<FS>"
4290 *mipsI,mipsII,mipsIII,mipsIV:
4291 *vr5000:
4292 // start-sanitize-vr4320
4293 *vr4320:
4294 // end-sanitize-vr4320
4295 // start-sanitize-vr5400
4296 *vr5400:
4297 // end-sanitize-vr5400
4298 *r3900:
4299 // start-sanitize-tx19
4300 *tx19:
4301 // end-sanitize-tx19
4302 {
4303   unsigned32 instruction = instruction_0;
4304   int destreg = ((instruction >> 6) & 0x0000001F);
4305   int fs = ((instruction >> 11) & 0x0000001F);
4306   int format = ((instruction >> 21) & 0x00000007);
4307   {
4308     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4309       SignalException(ReservedInstruction,instruction);
4310     else
4311       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4312   }
4313 }
4314
4315
4316 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4317 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4318 *mipsI,mipsII,mipsIII,mipsIV:
4319 *vr5000:
4320 // start-sanitize-vr4320
4321 *vr4320:
4322 // end-sanitize-vr4320
4323 // start-sanitize-vr5400
4324 *vr5400:
4325 // end-sanitize-vr5400
4326 *r3900:
4327 // start-sanitize-tx19
4328 *tx19:
4329 // end-sanitize-tx19
4330 {
4331   unsigned32 instruction = instruction_0;
4332   int destreg = ((instruction >> 6) & 0x0000001F);
4333   int fs = ((instruction >> 11) & 0x0000001F);
4334   int ft = ((instruction >> 16) & 0x0000001F);
4335   int format = ((instruction >> 21) & 0x00000007);
4336   {
4337     if ((format != fmt_single) && (format != fmt_double))
4338       SignalException(ReservedInstruction,instruction);
4339     else
4340       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4341   }
4342 }
4343
4344
4345 // DMFC1
4346 // DMTC1
4347 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4348 "dm%s<X>c1 r<RT>, f<FS>"
4349 *mipsIII:
4350 {
4351   if (X)
4352     {
4353       if (SizeFGR() == 64)
4354         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4355       else if ((FS & 0x1) == 0)
4356         {
4357           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4358           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4359         }
4360     }
4361   else
4362     {
4363       if (SizeFGR() == 64)
4364         PENDING_FILL(RT,FGR[FS]);
4365       else if ((FS & 0x1) == 0)
4366         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4367       else
4368         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4369     }
4370 }
4371 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4372 "dm%s<X>c1 r<RT>, f<FS>"
4373 *mipsIV:
4374 *vr5000:
4375 // start-sanitize-vr4320
4376 *vr4320:
4377 // end-sanitize-vr4320
4378 // start-sanitize-vr5400
4379 *vr5400:
4380 // end-sanitize-vr5400
4381 // start-sanitize-r5900
4382 *r5900:
4383 // end-sanitize-r5900
4384 *r3900:
4385 // start-sanitize-tx19
4386 *tx19:
4387 // end-sanitize-tx19
4388 {
4389   if (X)
4390     {
4391       if (SizeFGR() == 64)
4392         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4393       else if ((FS & 0x1) == 0)
4394         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4395     }
4396   else
4397     {
4398       if (SizeFGR() == 64)
4399         GPR[RT] = FGR[FS];
4400       else if ((FS & 0x1) == 0)
4401         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4402       else
4403         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4404     }
4405 }
4406
4407
4408 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4409 "floor.l.%s<FMT> f<FD>, f<FS>"
4410 *mipsIII:
4411 *mipsIV:
4412 *vr5000:
4413 // start-sanitize-vr4320
4414 *vr4320:
4415 // end-sanitize-vr4320
4416 // start-sanitize-vr5400
4417 *vr5400:
4418 // end-sanitize-vr5400
4419 // start-sanitize-r5900
4420 *r5900:
4421 // end-sanitize-r5900
4422 *r3900:
4423 // start-sanitize-tx19
4424 *tx19:
4425 // end-sanitize-tx19
4426 {
4427   unsigned32 instruction = instruction_0;
4428   int destreg = ((instruction >> 6) & 0x0000001F);
4429   int fs = ((instruction >> 11) & 0x0000001F);
4430   int format = ((instruction >> 21) & 0x00000007);
4431   {
4432     if ((format != fmt_single) && (format != fmt_double))
4433       SignalException(ReservedInstruction,instruction);
4434     else
4435       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4436   }
4437 }
4438
4439
4440 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4441 "floor.w.%s<FMT> f<FD>, f<FS>"
4442 *mipsII:
4443 *mipsIII:
4444 *mipsIV:
4445 *vr5000:
4446 // start-sanitize-vr4320
4447 *vr4320:
4448 // end-sanitize-vr4320
4449 // start-sanitize-vr5400
4450 *vr5400:
4451 // end-sanitize-vr5400
4452 // start-sanitize-r5900
4453 *r5900:
4454 // end-sanitize-r5900
4455 *r3900:
4456 // start-sanitize-tx19
4457 *tx19:
4458 // end-sanitize-tx19
4459 {
4460   unsigned32 instruction = instruction_0;
4461   int destreg = ((instruction >> 6) & 0x0000001F);
4462   int fs = ((instruction >> 11) & 0x0000001F);
4463   int format = ((instruction >> 21) & 0x00000007);
4464   {
4465     if ((format != fmt_single) && (format != fmt_double))
4466       SignalException(ReservedInstruction,instruction);
4467     else
4468       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4469   }
4470 }
4471
4472
4473 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4474 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4475 *mipsII:
4476 *mipsIII:
4477 *mipsIV:
4478 *vr5000:
4479 // start-sanitize-vr4320
4480 *vr4320:
4481 // end-sanitize-vr4320
4482 // start-sanitize-vr5400
4483 *vr5400:
4484 // end-sanitize-vr5400
4485 *r3900:
4486 // start-sanitize-tx19
4487 *tx19:
4488 // end-sanitize-tx19
4489 {
4490   address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
4491   address_word paddr;
4492   int uncached;
4493   if ((vaddr & 7) != 0)
4494     SignalExceptionAddressLoad();
4495   else
4496     {
4497       unsigned64 memval;
4498       AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
4499       LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4500       COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
4501     }
4502 }
4503
4504
4505 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4506 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4507 *mipsIV:
4508 *vr5000:
4509 // start-sanitize-vr4320
4510 *vr4320:
4511 // end-sanitize-vr4320
4512 // start-sanitize-vr5400
4513 *vr5400:
4514 // end-sanitize-vr5400
4515 {
4516   unsigned32 instruction = instruction_0;
4517   int destreg = ((instruction >> 6) & 0x0000001F);
4518   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4519   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4520   {
4521     address_word vaddr = ((unsigned64)op1 + op2);
4522     address_word paddr;
4523     int uncached;
4524     if ((vaddr & 7) != 0)
4525       SignalExceptionAddressLoad();
4526     else
4527       {
4528         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4529           {
4530             unsigned64 memval = 0;
4531             unsigned64 memval1 = 0;
4532             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4533             COP_LD(1,destreg,memval);;
4534           }
4535       }
4536   }
4537 }
4538
4539
4540
4541 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4542 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4543 *mipsI,mipsII,mipsIII,mipsIV:
4544 *vr5000:
4545 // start-sanitize-vr4320
4546 *vr4320:
4547 // end-sanitize-vr4320
4548 // start-sanitize-vr5400
4549 *vr5400:
4550 // end-sanitize-vr5400
4551 // start-sanitize-r5900
4552 *r5900:
4553 // end-sanitize-r5900
4554 *r3900:
4555 // start-sanitize-tx19
4556 *tx19:
4557 // end-sanitize-tx19
4558 {
4559   unsigned32 instruction = instruction_0;
4560   signed_word offset = EXTEND16 (OFFSET);
4561   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4562   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4563   {
4564     address_word vaddr = ((uword64)op1 + offset);
4565     address_word paddr;
4566     int uncached;
4567     if ((vaddr & 3) != 0)
4568       SignalExceptionAddressLoad();
4569     else
4570       {
4571         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4572           {
4573             uword64 memval = 0;
4574             uword64 memval1 = 0;
4575             uword64 mask = 0x7;
4576             unsigned int shift = 2;
4577             unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
4578             unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
4579             unsigned int byte UNUSED;
4580             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4581             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4582             byte = ((vaddr & mask) ^ (bigend << shift));
4583             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4584           }
4585       }
4586   }
4587 }
4588
4589
4590 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4591 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4592 *mipsIV:
4593 *vr5000:
4594 // start-sanitize-vr4320
4595 *vr4320:
4596 // end-sanitize-vr4320
4597 // start-sanitize-vr5400
4598 *vr5400:
4599 // end-sanitize-vr5400
4600 {
4601   unsigned32 instruction = instruction_0;
4602   int destreg = ((instruction >> 6) & 0x0000001F);
4603   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4604   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4605   {
4606    address_word vaddr = ((unsigned64)op1 + op2);
4607    address_word paddr;
4608    int uncached;
4609    if ((vaddr & 3) != 0)
4610     SignalExceptionAddressLoad();
4611    else
4612    {
4613     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4614     {
4615      unsigned64 memval = 0;
4616      unsigned64 memval1 = 0;
4617      unsigned64 mask = 0x7;
4618      unsigned int shift = 2;
4619      unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4620      unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4621      unsigned int byte;
4622      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4623      LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4624      byte = ((vaddr & mask) ^ (bigend << shift));
4625      COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4626     }
4627    }
4628   }
4629 }
4630
4631
4632
4633 //
4634 // FIXME: Not correct for mips*
4635 //
4636 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4637 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4638 *mipsIV:
4639 *vr5000:
4640 // start-sanitize-vr4320
4641 *vr4320:
4642 // end-sanitize-vr4320
4643 // start-sanitize-vr5400
4644 *vr5400:
4645 // end-sanitize-vr5400
4646 {
4647   unsigned32 instruction = instruction_0;
4648   int destreg = ((instruction >> 6) & 0x0000001F);
4649   int fs = ((instruction >> 11) & 0x0000001F);
4650   int ft = ((instruction >> 16) & 0x0000001F);
4651   int fr = ((instruction >> 21) & 0x0000001F);
4652   {
4653     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4654   }
4655 }
4656
4657
4658 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4659 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4660 *mipsIV:
4661 *vr5000:
4662 // start-sanitize-vr4320
4663 *vr4320:
4664 // end-sanitize-vr4320
4665 // start-sanitize-vr5400
4666 *vr5400:
4667 // end-sanitize-vr5400
4668 {
4669   unsigned32 instruction = instruction_0;
4670   int destreg = ((instruction >> 6) & 0x0000001F);
4671   int fs = ((instruction >> 11) & 0x0000001F);
4672   int ft = ((instruction >> 16) & 0x0000001F);
4673   int fr = ((instruction >> 21) & 0x0000001F);
4674   {
4675     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4676   }
4677 }
4678
4679
4680 // MFC1
4681 // MTC1
4682 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4683 "m%s<X>c1 r<RT>, f<FS>"
4684 *mipsI:
4685 *mipsII:
4686 *mipsIII:
4687 {
4688   if (X)
4689     { /*MTC1*/
4690       if (SizeFGR() == 64)
4691         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4692       else
4693         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4694     }
4695   else /*MFC1*/
4696     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4697 }
4698 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4699 "m%s<X>c1 r<RT>, f<FS>"
4700 *mipsIV:
4701 *vr5000:
4702 // start-sanitize-vr4320
4703 *vr4320:
4704 // end-sanitize-vr4320
4705 // start-sanitize-vr5400
4706 *vr5400:
4707 // end-sanitize-vr5400
4708 *r3900:
4709 // start-sanitize-tx19
4710 *tx19:
4711 // end-sanitize-tx19
4712 {
4713   if (X)
4714     /*MTC1*/
4715     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4716   else /*MFC1*/
4717     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4718 }
4719
4720
4721 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4722 "mov.%s<FMT> f<FD>, f<FS>"
4723 *mipsI,mipsII,mipsIII,mipsIV:
4724 *vr5000:
4725 // start-sanitize-vr4320
4726 *vr4320:
4727 // end-sanitize-vr4320
4728 // start-sanitize-vr5400
4729 *vr5400:
4730 // end-sanitize-vr5400
4731 *r3900:
4732 // start-sanitize-tx19
4733 *tx19:
4734 // end-sanitize-tx19
4735 {
4736   unsigned32 instruction = instruction_0;
4737   int destreg = ((instruction >> 6) & 0x0000001F);
4738   int fs = ((instruction >> 11) & 0x0000001F);
4739   int format = ((instruction >> 21) & 0x00000007);
4740   {
4741     StoreFPR(destreg,format,ValueFPR(fs,format));
4742   }
4743 }
4744
4745
4746 // MOVF
4747 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4748 "mov%s<TF> r<RD>, r<RS>, <CC>"
4749 *mipsIV:
4750 *vr5000:
4751 // start-sanitize-vr4320
4752 *vr4320:
4753 // end-sanitize-vr4320
4754 // start-sanitize-vr5400
4755 *vr5400:
4756 // end-sanitize-vr5400
4757 // start-sanitize-r5900
4758 *r5900:
4759 // end-sanitize-r5900
4760 {
4761   if (GETFCC(CC) == TF)
4762     GPR[RD] = GPR[RS];
4763 }
4764
4765
4766 // MOVF.fmt
4767 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4768 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4769 *mipsIV:
4770 *vr5000:
4771 // start-sanitize-vr4320
4772 *vr4320:
4773 // end-sanitize-vr4320
4774 // start-sanitize-vr5400
4775 *vr5400:
4776 // end-sanitize-vr5400
4777 // start-sanitize-r5900
4778 *r5900:
4779 // end-sanitize-r5900
4780 {
4781   unsigned32 instruction = instruction_0;
4782   int format = ((instruction >> 21) & 0x00000007);
4783   {
4784    if (GETFCC(CC) == TF)
4785      StoreFPR (FD, format, ValueFPR (FS, format));
4786    else
4787      StoreFPR (FD, format, ValueFPR (FD, format));
4788   }
4789 }
4790
4791
4792 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4793 *mipsIV:
4794 *vr5000:
4795 // start-sanitize-vr4320
4796 *vr4320:
4797 // end-sanitize-vr4320
4798 // start-sanitize-vr5400
4799 *vr5400:
4800 // end-sanitize-vr5400
4801 // start-sanitize-r5900
4802 *r5900:
4803 // end-sanitize-r5900
4804 {
4805   unsigned32 instruction = instruction_0;
4806   int destreg = ((instruction >> 6) & 0x0000001F);
4807   int fs = ((instruction >> 11) & 0x0000001F);
4808   int format = ((instruction >> 21) & 0x00000007);
4809   {
4810     StoreFPR(destreg,format,ValueFPR(fs,format));
4811   }
4812 }
4813
4814
4815 // MOVT see MOVtf
4816
4817
4818 // MOVT.fmt see MOVtf.fmt
4819
4820
4821
4822 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4823 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4824 *mipsIV:
4825 *vr5000:
4826 // start-sanitize-vr4320
4827 *vr4320:
4828 // end-sanitize-vr4320
4829 // start-sanitize-vr5400
4830 *vr5400:
4831 // end-sanitize-vr5400
4832 // start-sanitize-r5900
4833 *r5900:
4834 // end-sanitize-r5900
4835 {
4836   unsigned32 instruction = instruction_0;
4837   int destreg = ((instruction >> 6) & 0x0000001F);
4838   int fs = ((instruction >> 11) & 0x0000001F);
4839   int format = ((instruction >> 21) & 0x00000007);
4840   {
4841    StoreFPR(destreg,format,ValueFPR(fs,format));
4842   }
4843 }
4844
4845
4846 // MSUB.fmt
4847 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4848 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4849 *mipsIV:
4850 *vr5000:
4851 // start-sanitize-vr4320
4852 *vr4320:
4853 // end-sanitize-vr4320
4854 // start-sanitize-vr5400
4855 *vr5400:
4856 // end-sanitize-vr5400
4857 // start-sanitize-r5900
4858 *r5900:
4859 // end-sanitize-r5900
4860 {
4861   unsigned32 instruction = instruction_0;
4862   int destreg = ((instruction >> 6) & 0x0000001F);
4863   int fs = ((instruction >> 11) & 0x0000001F);
4864   int ft = ((instruction >> 16) & 0x0000001F);
4865   int fr = ((instruction >> 21) & 0x0000001F);
4866   {
4867     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4868   }
4869 }
4870
4871
4872 // MSUB.fmt
4873 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4874 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4875 *mipsIV:
4876 *vr5000:
4877 // start-sanitize-vr4320
4878 *vr4320:
4879 // end-sanitize-vr4320
4880 // start-sanitize-vr5400
4881 *vr5400:
4882 // end-sanitize-vr5400
4883 // start-sanitize-r5900
4884 *r5900:
4885 // end-sanitize-r5900
4886 {
4887   unsigned32 instruction = instruction_0;
4888   int destreg = ((instruction >> 6) & 0x0000001F);
4889   int fs = ((instruction >> 11) & 0x0000001F);
4890   int ft = ((instruction >> 16) & 0x0000001F);
4891   int fr = ((instruction >> 21) & 0x0000001F);
4892   {
4893    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4894   }
4895 }
4896
4897
4898 // MTC1 see MxC1
4899
4900
4901 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4902 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4903 *mipsI,mipsII,mipsIII,mipsIV:
4904 *vr5000:
4905 // start-sanitize-vr4320
4906 *vr4320:
4907 // end-sanitize-vr4320
4908 // start-sanitize-vr5400
4909 *vr5400:
4910 // end-sanitize-vr5400
4911 *r3900:
4912 // start-sanitize-tx19
4913 *tx19:
4914 // end-sanitize-tx19
4915 {
4916   unsigned32 instruction = instruction_0;
4917   int destreg = ((instruction >> 6) & 0x0000001F);
4918   int fs = ((instruction >> 11) & 0x0000001F);
4919   int ft = ((instruction >> 16) & 0x0000001F);
4920   int format = ((instruction >> 21) & 0x00000007);
4921   {
4922     if ((format != fmt_single) && (format != fmt_double))
4923       SignalException(ReservedInstruction,instruction);
4924     else
4925       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4926   }
4927 }
4928
4929
4930 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4931 "neg.%s<FMT> f<FD>, f<FS>"
4932 *mipsI,mipsII,mipsIII,mipsIV:
4933 *vr5000:
4934 // start-sanitize-vr4320
4935 *vr4320:
4936 // end-sanitize-vr4320
4937 // start-sanitize-vr5400
4938 *vr5400:
4939 // end-sanitize-vr5400
4940 *r3900:
4941 // start-sanitize-tx19
4942 *tx19:
4943 // end-sanitize-tx19
4944 {
4945   unsigned32 instruction = instruction_0;
4946   int destreg = ((instruction >> 6) & 0x0000001F);
4947   int fs = ((instruction >> 11) & 0x0000001F);
4948   int format = ((instruction >> 21) & 0x00000007);
4949   {
4950     if ((format != fmt_single) && (format != fmt_double))
4951       SignalException(ReservedInstruction,instruction);
4952     else
4953       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4954   }
4955 }
4956
4957
4958 // NMADD.fmt
4959 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4960 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4961 *mipsIV:
4962 *vr5000:
4963 // start-sanitize-vr4320
4964 *vr4320:
4965 // end-sanitize-vr4320
4966 // start-sanitize-vr5400
4967 *vr5400:
4968 // end-sanitize-vr5400
4969 {
4970   unsigned32 instruction = instruction_0;
4971   int destreg = ((instruction >> 6) & 0x0000001F);
4972   int fs = ((instruction >> 11) & 0x0000001F);
4973   int ft = ((instruction >> 16) & 0x0000001F);
4974   int fr = ((instruction >> 21) & 0x0000001F);
4975   {
4976    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4977   }
4978 }
4979
4980
4981 // NMADD.fmt
4982 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4983 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4984 *mipsIV:
4985 *vr5000:
4986 // start-sanitize-vr4320
4987 *vr4320:
4988 // end-sanitize-vr4320
4989 // start-sanitize-vr5400
4990 *vr5400:
4991 // end-sanitize-vr5400
4992 {
4993   unsigned32 instruction = instruction_0;
4994   int destreg = ((instruction >> 6) & 0x0000001F);
4995   int fs = ((instruction >> 11) & 0x0000001F);
4996   int ft = ((instruction >> 16) & 0x0000001F);
4997   int fr = ((instruction >> 21) & 0x0000001F);
4998   {
4999    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5000   }
5001 }
5002
5003
5004 // NMSUB.fmt
5005 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5006 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5007 *mipsIV:
5008 *vr5000:
5009 // start-sanitize-vr4320
5010 *vr4320:
5011 // end-sanitize-vr4320
5012 // start-sanitize-vr5400
5013 *vr5400:
5014 // end-sanitize-vr5400
5015 {
5016   unsigned32 instruction = instruction_0;
5017   int destreg = ((instruction >> 6) & 0x0000001F);
5018   int fs = ((instruction >> 11) & 0x0000001F);
5019   int ft = ((instruction >> 16) & 0x0000001F);
5020   int fr = ((instruction >> 21) & 0x0000001F);
5021   {
5022    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5023   }
5024 }
5025
5026
5027 // NMSUB.fmt
5028 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5029 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5030 *mipsIV:
5031 *vr5000:
5032 // start-sanitize-vr4320
5033 *vr4320:
5034 // end-sanitize-vr4320
5035 // start-sanitize-vr5400
5036 *vr5400:
5037 // end-sanitize-vr5400
5038 {
5039   unsigned32 instruction = instruction_0;
5040   int destreg = ((instruction >> 6) & 0x0000001F);
5041   int fs = ((instruction >> 11) & 0x0000001F);
5042   int ft = ((instruction >> 16) & 0x0000001F);
5043   int fr = ((instruction >> 21) & 0x0000001F);
5044   {
5045     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5046   }
5047 }
5048
5049
5050 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5051 "prefx <HINT>, r<INDEX>(r<BASE>)"
5052 *mipsIV:
5053 *vr5000:
5054 // start-sanitize-vr4320
5055 *vr4320:
5056 // end-sanitize-vr4320
5057 // start-sanitize-vr5400
5058 *vr5400:
5059 // end-sanitize-vr5400
5060 {
5061   unsigned32 instruction = instruction_0;
5062   int fs = ((instruction >> 11) & 0x0000001F);
5063   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5064   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5065   {
5066     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5067     address_word paddr;
5068     int uncached;
5069     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5070       Prefetch(uncached,paddr,vaddr,isDATA,fs);
5071   }
5072 }
5073
5074 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5075 *mipsIV:
5076 "recip.%s<FMT> f<FD>, f<FS>"
5077 *vr5000:
5078 // start-sanitize-vr4320
5079 *vr4320:
5080 // end-sanitize-vr4320
5081 // start-sanitize-vr5400
5082 *vr5400:
5083 // end-sanitize-vr5400
5084 {
5085   unsigned32 instruction = instruction_0;
5086   int destreg = ((instruction >> 6) & 0x0000001F);
5087   int fs = ((instruction >> 11) & 0x0000001F);
5088   int format = ((instruction >> 21) & 0x00000007);
5089   {
5090   if ((format != fmt_single) && (format != fmt_double))
5091    SignalException(ReservedInstruction,instruction);
5092   else
5093    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5094   }
5095 }
5096
5097
5098 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5099 "round.l.%s<FMT> f<FD>, f<FS>"
5100 *mipsIII:
5101 *mipsIV:
5102 *vr5000:
5103 // start-sanitize-vr4320
5104 *vr4320:
5105 // end-sanitize-vr4320
5106 // start-sanitize-vr5400
5107 *vr5400:
5108 // end-sanitize-vr5400
5109 // start-sanitize-r5900
5110 *r5900:
5111 // end-sanitize-r5900
5112 *r3900:
5113 // start-sanitize-tx19
5114 *tx19:
5115 // end-sanitize-tx19
5116 {
5117   unsigned32 instruction = instruction_0;
5118   int destreg = ((instruction >> 6) & 0x0000001F);
5119   int fs = ((instruction >> 11) & 0x0000001F);
5120   int format = ((instruction >> 21) & 0x00000007);
5121   {
5122     if ((format != fmt_single) && (format != fmt_double))
5123       SignalException(ReservedInstruction,instruction);
5124     else
5125       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5126   }
5127 }
5128
5129
5130 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5131 "round.w.%s<FMT> f<FD>, f<FS>"
5132 *mipsII:
5133 *mipsIII:
5134 *mipsIV:
5135 *vr5000:
5136 // start-sanitize-vr4320
5137 *vr4320:
5138 // end-sanitize-vr4320
5139 // start-sanitize-vr5400
5140 *vr5400:
5141 // end-sanitize-vr5400
5142 // start-sanitize-r5900
5143 *r5900:
5144 // end-sanitize-r5900
5145 *r3900:
5146 // start-sanitize-tx19
5147 *tx19:
5148 // end-sanitize-tx19
5149 {
5150   unsigned32 instruction = instruction_0;
5151   int destreg = ((instruction >> 6) & 0x0000001F);
5152   int fs = ((instruction >> 11) & 0x0000001F);
5153   int format = ((instruction >> 21) & 0x00000007);
5154   {
5155   if ((format != fmt_single) && (format != fmt_double))
5156    SignalException(ReservedInstruction,instruction);
5157   else
5158    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5159   }
5160 }
5161
5162
5163 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5164 *mipsIV:
5165 "rsqrt.%s<FMT> f<FD>, f<FS>"
5166 *vr5000:
5167 // start-sanitize-vr4320
5168 *vr4320:
5169 // end-sanitize-vr4320
5170 // start-sanitize-vr5400
5171 *vr5400:
5172 // end-sanitize-vr5400
5173 {
5174   unsigned32 instruction = instruction_0;
5175   int destreg = ((instruction >> 6) & 0x0000001F);
5176   int fs = ((instruction >> 11) & 0x0000001F);
5177   int format = ((instruction >> 21) & 0x00000007);
5178   {
5179   if ((format != fmt_single) && (format != fmt_double))
5180    SignalException(ReservedInstruction,instruction);
5181   else
5182    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5183   }
5184 }
5185
5186
5187 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5188 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5189 *mipsII:
5190 *mipsIII:
5191 *mipsIV:
5192 *vr5000:
5193 // start-sanitize-vr4320
5194 *vr4320:
5195 // end-sanitize-vr4320
5196 // start-sanitize-vr5400
5197 *vr5400:
5198 // end-sanitize-vr5400
5199 *r3900:
5200 // start-sanitize-tx19
5201 *tx19:
5202 // end-sanitize-tx19
5203 {
5204   address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
5205   int uncached;
5206   if ((vaddr & 7) != 0)
5207     SignalExceptionAddressStore();
5208   else
5209     {
5210       address_word paddr;
5211       unsigned64 memval;
5212       AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
5213       memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
5214       StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
5215     }
5216 }
5217
5218
5219 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
5220 *mipsIV:
5221 *vr5000:
5222 // start-sanitize-vr4320
5223 *vr4320:
5224 // end-sanitize-vr4320
5225 // start-sanitize-vr5400
5226 *vr5400:
5227 // end-sanitize-vr5400
5228 {
5229   unsigned32 instruction = instruction_0;
5230   int fs = ((instruction >> 11) & 0x0000001F);
5231   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5232   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5233   {
5234     address_word vaddr = ((unsigned64)op1 + op2);
5235     address_word paddr;
5236     int uncached;
5237     if ((vaddr & 7) != 0)
5238       SignalExceptionAddressStore();
5239     else
5240       {
5241         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5242           {
5243             unsigned64 memval = 0;
5244             unsigned64 memval1 = 0;
5245             memval = (unsigned64)COP_SD(1,fs);
5246             {
5247               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5248             }
5249           }
5250       }
5251   }
5252 }
5253
5254
5255 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5256 "sqrt.%s<FMT> f<FD>, f<FS>"
5257 *mipsII:
5258 *mipsIII:
5259 *mipsIV:
5260 *vr5000:
5261 // start-sanitize-vr4320
5262 *vr4320:
5263 // end-sanitize-vr4320
5264 // start-sanitize-vr5400
5265 *vr5400:
5266 // end-sanitize-vr5400
5267 *r3900:
5268 // start-sanitize-tx19
5269 *tx19:
5270 // end-sanitize-tx19
5271 {
5272   unsigned32 instruction = instruction_0;
5273   int destreg = ((instruction >> 6) & 0x0000001F);
5274   int fs = ((instruction >> 11) & 0x0000001F);
5275   int format = ((instruction >> 21) & 0x00000007);
5276   {
5277     if ((format != fmt_single) && (format != fmt_double))
5278       SignalException(ReservedInstruction,instruction);
5279     else
5280       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5281   }
5282 }
5283
5284
5285 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5286 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5287 *mipsI,mipsII,mipsIII,mipsIV:
5288 *vr5000:
5289 // start-sanitize-vr4320
5290 *vr4320:
5291 // end-sanitize-vr4320
5292 // start-sanitize-vr5400
5293 *vr5400:
5294 // end-sanitize-vr5400
5295 *r3900:
5296 // start-sanitize-tx19
5297 *tx19:
5298 // end-sanitize-tx19
5299 {
5300   unsigned32 instruction = instruction_0;
5301   int destreg = ((instruction >> 6) & 0x0000001F);
5302   int fs = ((instruction >> 11) & 0x0000001F);
5303   int ft = ((instruction >> 16) & 0x0000001F);
5304   int format = ((instruction >> 21) & 0x00000007);
5305   {
5306     if ((format != fmt_single) && (format != fmt_double))
5307       SignalException(ReservedInstruction,instruction);
5308     else
5309       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5310   }
5311 }
5312
5313
5314
5315 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5316 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5317 *mipsI,mipsII,mipsIII,mipsIV:
5318 *vr5000:
5319 // start-sanitize-vr4320
5320 *vr4320:
5321 // end-sanitize-vr4320
5322 // start-sanitize-vr5400
5323 *vr5400:
5324 // end-sanitize-vr5400
5325 // start-sanitize-r5900
5326 *r5900:
5327 // end-sanitize-r5900
5328 *r3900:
5329 // start-sanitize-tx19
5330 *tx19:
5331 // end-sanitize-tx19
5332 {
5333   unsigned32 instruction = instruction_0;
5334   signed_word offset = EXTEND16 (OFFSET);
5335   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5336   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5337   {
5338     address_word vaddr = ((uword64)op1 + offset);
5339     address_word paddr;
5340     int uncached;
5341     if ((vaddr & 3) != 0)
5342       SignalExceptionAddressStore();
5343     else
5344       {
5345         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5346           {
5347             uword64 memval = 0;
5348             uword64 memval1 = 0;
5349             uword64 mask = 0x7;
5350             unsigned int byte;
5351             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5352             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5353             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5354             {
5355               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5356             }
5357           }
5358       }
5359   }
5360 }
5361
5362
5363 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5364 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5365 *mipsIV:
5366 *vr5000:
5367 // start-sanitize-vr4320
5368 *vr4320:
5369 // end-sanitize-vr4320
5370 // start-sanitize-vr5400
5371 *vr5400:
5372 // end-sanitize-vr5400
5373 {
5374   unsigned32 instruction = instruction_0;
5375   int fs = ((instruction >> 11) & 0x0000001F);
5376   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5377   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5378   {
5379    address_word vaddr = ((unsigned64)op1 + op2);
5380    address_word paddr;
5381    int uncached;
5382    if ((vaddr & 3) != 0)
5383     SignalExceptionAddressStore();
5384    else
5385    {
5386     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5387     {
5388      unsigned64 memval = 0;
5389      unsigned64 memval1 = 0;
5390      unsigned64 mask = 0x7;
5391      unsigned int byte;
5392      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5393      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5394      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5395       {
5396        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5397       }
5398     }
5399    }
5400   }
5401 }
5402
5403
5404 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5405 "trunc.l.%s<FMT> f<FD>, f<FS>"
5406 *mipsIII:
5407 *mipsIV:
5408 *vr5000:
5409 // start-sanitize-vr4320
5410 *vr4320:
5411 // end-sanitize-vr4320
5412 // start-sanitize-vr5400
5413 *vr5400:
5414 // end-sanitize-vr5400
5415 // start-sanitize-r5900
5416 *r5900:
5417 // end-sanitize-r5900
5418 *r3900:
5419 // start-sanitize-tx19
5420 *tx19:
5421 // end-sanitize-tx19
5422 {
5423   unsigned32 instruction = instruction_0;
5424   int destreg = ((instruction >> 6) & 0x0000001F);
5425   int fs = ((instruction >> 11) & 0x0000001F);
5426   int format = ((instruction >> 21) & 0x00000007);
5427   {
5428   if ((format != fmt_single) && (format != fmt_double))
5429    SignalException(ReservedInstruction,instruction);
5430   else
5431    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5432   }
5433 }
5434
5435
5436 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5437 "trunc.w.%s<FMT> f<FD>, f<FS>"
5438 *mipsII:
5439 *mipsIII:
5440 *mipsIV:
5441 *vr5000:
5442 // start-sanitize-vr4320
5443 *vr4320:
5444 // end-sanitize-vr4320
5445 // start-sanitize-vr5400
5446 *vr5400:
5447 // end-sanitize-vr5400
5448 // start-sanitize-r5900
5449 *r5900:
5450 // end-sanitize-r5900
5451 *r3900:
5452 // start-sanitize-tx19
5453 *tx19:
5454 // end-sanitize-tx19
5455 {
5456   unsigned32 instruction = instruction_0;
5457   int destreg = ((instruction >> 6) & 0x0000001F);
5458   int fs = ((instruction >> 11) & 0x0000001F);
5459   int format = ((instruction >> 21) & 0x00000007);
5460   {
5461   if ((format != fmt_single) && (format != fmt_double))
5462    SignalException(ReservedInstruction,instruction);
5463   else
5464    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5465   }
5466 }
5467
5468 \f
5469 //
5470 // MIPS Architecture:
5471 //
5472 //        System Control Instruction Set (COP0)
5473 //
5474
5475
5476 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5477 "bc0f <OFFSET>"
5478 *mipsI,mipsII,mipsIII,mipsIV:
5479 *vr5000:
5480 // start-sanitize-vr4320
5481 *vr4320:
5482 // end-sanitize-vr4320
5483 // start-sanitize-vr5400
5484 *vr5400:
5485 // end-sanitize-vr5400
5486 // start-sanitize-r5900
5487 *r5900:
5488 // end-sanitize-r5900
5489
5490
5491 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5492 "bc0fl <OFFSET>"
5493 *mipsI,mipsII,mipsIII,mipsIV:
5494 *vr5000:
5495 // start-sanitize-vr4320
5496 *vr4320:
5497 // end-sanitize-vr4320
5498 // start-sanitize-vr5400
5499 *vr5400:
5500 // end-sanitize-vr5400
5501 // start-sanitize-r5900
5502 *r5900:
5503 // end-sanitize-r5900
5504
5505
5506 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5507 "bc0t <OFFSET>"
5508 *mipsI,mipsII,mipsIII,mipsIV:
5509 // start-sanitize-r5900
5510 *r5900:
5511 // end-sanitize-r5900
5512
5513
5514
5515 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5516 "bc0tl <OFFSET>"
5517 *mipsI,mipsII,mipsIII,mipsIV:
5518 *vr5000:
5519 // start-sanitize-vr4320
5520 *vr4320:
5521 // end-sanitize-vr4320
5522 // start-sanitize-vr5400
5523 *vr5400:
5524 // end-sanitize-vr5400
5525 // start-sanitize-r5900
5526 *r5900:
5527 // end-sanitize-r5900
5528
5529
5530 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5531 *mipsIII:
5532 *mipsIV:
5533 *vr5000:
5534 // start-sanitize-vr4320
5535 *vr4320:
5536 // end-sanitize-vr4320
5537 // start-sanitize-vr5400
5538 *vr5400:
5539 // end-sanitize-vr5400
5540 // start-sanitize-r5900
5541 *r5900:
5542 // end-sanitize-r5900
5543 *r3900:
5544 // start-sanitize-tx19
5545 *tx19:
5546 // end-sanitize-tx19
5547 {
5548   unsigned32 instruction = instruction_0;
5549   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5550   int hint = ((instruction >> 16) & 0x0000001F);
5551   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5552   {
5553     address_word vaddr = (op1 + offset);
5554     address_word paddr;
5555     int uncached;
5556     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5557       CacheOp(hint,vaddr,paddr,instruction);
5558   }
5559 }
5560
5561
5562 010000,10000,000000000000000,111001:COP0:32::DI
5563 "di"
5564 *mipsI,mipsII,mipsIII,mipsIV:
5565 *vr5000:
5566 // start-sanitize-vr4320
5567 *vr4320:
5568 // end-sanitize-vr4320
5569 // start-sanitize-vr5400
5570 *vr5400:
5571 // end-sanitize-vr5400
5572 // start-sanitize-r5900
5573 *r5900:
5574 // end-sanitize-r5900
5575
5576
5577 010000,10000,000000000000000,111000:COP0:32::EI
5578 "ei"
5579 *mipsI,mipsII,mipsIII,mipsIV:
5580 *vr5000:
5581 // start-sanitize-vr4320
5582 *vr4320:
5583 // end-sanitize-vr4320
5584 // start-sanitize-vr5400
5585 *vr5400:
5586 // end-sanitize-vr5400
5587 // start-sanitize-r5900
5588 *r5900:
5589 // end-sanitize-r5900
5590
5591
5592 010000,10000,000000000000000,011000:COP0:32::ERET
5593 "eret"
5594 *mipsIII:
5595 *mipsIV:
5596 *vr5000:
5597 // start-sanitize-vr4320
5598 *vr4320:
5599 // end-sanitize-vr4320
5600 // start-sanitize-vr5400
5601 *vr5400:
5602 // end-sanitize-vr5400
5603 // start-sanitize-r5900
5604 *r5900:
5605 // end-sanitize-r5900
5606
5607
5608 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5609 "mfc0 r<RT>, r<RD> # <REGX>"
5610 *mipsI,mipsII,mipsIII,mipsIV:
5611 *vr5000:
5612 // start-sanitize-vr4320
5613 *vr4320:
5614 // end-sanitize-vr4320
5615 // start-sanitize-vr5400
5616 *vr5400:
5617 // end-sanitize-vr5400
5618 // start-sanitize-r5900
5619 *r5900:
5620 // end-sanitize-r5900
5621 {
5622   DecodeCoproc (instruction_0);
5623 }
5624
5625 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5626 "mtc0 r<RT>, r<RD> # <REGX>"
5627 *mipsI,mipsII,mipsIII,mipsIV:
5628 *vr5000:
5629 // start-sanitize-vr4320
5630 *vr4320:
5631 // end-sanitize-vr4320
5632 // start-sanitize-vr5400
5633 *vr5400:
5634 // end-sanitize-vr5400
5635 // start-sanitize-r5900
5636 *r5900:
5637 // end-sanitize-r5900
5638 {
5639   DecodeCoproc (instruction_0);
5640 }
5641
5642
5643 010000,10000,000000000000000,001000:COP0:32::TLBP
5644 "tlbp"
5645 *mipsI,mipsII,mipsIII,mipsIV:
5646 *vr5000:
5647 // start-sanitize-vr4320
5648 *vr4320:
5649 // end-sanitize-vr4320
5650 // start-sanitize-vr5400
5651 *vr5400:
5652 // end-sanitize-vr5400
5653 // start-sanitize-r5900
5654 *r5900:
5655 // end-sanitize-r5900
5656
5657
5658 010000,10000,000000000000000,000001:COP0:32::TLBR
5659 "tlbr"
5660 *mipsI,mipsII,mipsIII,mipsIV:
5661 *vr5000:
5662 // start-sanitize-vr4320
5663 *vr4320:
5664 // end-sanitize-vr4320
5665 // start-sanitize-vr5400
5666 *vr5400:
5667 // end-sanitize-vr5400
5668 // start-sanitize-r5900
5669 *r5900:
5670 // end-sanitize-r5900
5671
5672
5673 010000,10000,000000000000000,000010:COP0:32::TLBWI
5674 "tlbwi"
5675 *mipsI,mipsII,mipsIII,mipsIV:
5676 *vr5000:
5677 // start-sanitize-vr4320
5678 *vr4320:
5679 // end-sanitize-vr4320
5680 // start-sanitize-vr5400
5681 *vr5400:
5682 // end-sanitize-vr5400
5683 // start-sanitize-r5900
5684 *r5900:
5685 // end-sanitize-r5900
5686
5687
5688 010000,10000,000000000000000,000110:COP0:32::TLBWR
5689 "tlbwr"
5690 *mipsI,mipsII,mipsIII,mipsIV:
5691 *vr5000:
5692 // start-sanitize-vr4320
5693 *vr4320:
5694 // end-sanitize-vr4320
5695 // start-sanitize-vr5400
5696 *vr5400:
5697 // end-sanitize-vr5400
5698 // start-sanitize-r5900
5699 *r5900:
5700 // end-sanitize-r5900
5701
5702 \f
5703 :include:16::m16.igen
5704 // start-sanitize-vr4320
5705 :include::vr4320:vr4320.igen
5706 // end-sanitize-vr4320
5707 // start-sanitize-vr5400
5708 :include::vr5400:vr5400.igen
5709 :include:64,f::mdmx.igen
5710 // end-sanitize-vr5400
5711 // start-sanitize-r5900
5712 :include::r5900:r5900.igen
5713 // end-sanitize-r5900
5714 \f
5715 // start-sanitize-cygnus-never
5716
5717 // // FIXME FIXME FIXME What is this instruction?
5718 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5719 // *mipsI:
5720 // *mipsII:
5721 // *mipsIII:
5722 // *mipsIV:
5723 // // start-sanitize-r5900
5724 // *r5900:
5725 // // end-sanitize-r5900
5726 // *r3900:
5727 // // start-sanitize-tx19
5728 // *tx19:
5729 // // end-sanitize-tx19
5730 // {
5731 //   unsigned32 instruction = instruction_0;
5732 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5733 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5734 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5735 //   {
5736 //     if (CoProcPresent(3))
5737 //       SignalException(CoProcessorUnusable);
5738 //     else
5739 //       SignalException(ReservedInstruction,instruction);
5740 //   }
5741 // }
5742
5743 // end-sanitize-cygnus-never
5744 // start-sanitize-cygnus-never
5745
5746 // // FIXME FIXME FIXME What is this?
5747 // 11100,******,00001:RR:16::SDBBP
5748 // *mips16:
5749 // {
5750 //   unsigned32 instruction = instruction_0;
5751 //   if (have_extendval)
5752 //     SignalException (ReservedInstruction, instruction);
5753 //   {
5754 //     SignalException(DebugBreakPoint,instruction);
5755 //   }
5756 // }
5757
5758 // end-sanitize-cygnus-never
5759 // start-sanitize-cygnus-never
5760
5761 // // FIXME FIXME FIXME What is this?
5762 // 000000,********************,001110:SPECIAL:32::SDBBP
5763 // *r3900:
5764 // {
5765 //   unsigned32 instruction = instruction_0;
5766 //   {
5767 //     SignalException(DebugBreakPoint,instruction);
5768 //   }
5769 // }
5770
5771 // end-sanitize-cygnus-never
5772 // start-sanitize-cygnus-never
5773
5774 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5775 // // isn't yet reconized by this simulator.
5776 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5777 // *vr4100:
5778 // {
5779 //   unsigned32 instruction = instruction_0;
5780 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5781 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5782 //   {
5783 //     CHECKHILO("Multiply-Add");
5784 //     {
5785 //       unsigned64 temp = (op1 * op2);
5786 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5787 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5788 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5789 //     }
5790 //   }
5791 // }
5792
5793 // end-sanitize-cygnus-never
5794 // start-sanitize-cygnus-never
5795
5796 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5797 // // isn't yet reconized by this simulator.
5798 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5799 // *vr4100:
5800 // {
5801 //   unsigned32 instruction = instruction_0;
5802 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5803 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5804 //   {
5805 //     CHECKHILO("Multiply-Add");
5806 //     {
5807 //       unsigned64 temp = (op1 * op2);
5808 //       LO = LO + temp;
5809 //     }
5810 //   }
5811 // }
5812
5813 // end-sanitize-cygnus-never