4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator
34 :model:::mipsI:mips3000:
35 :model:::mipsII:mips6000:
36 :model:::mipsIII:mips4000:
37 :model:::mipsIV:mips8000:
38 :model:::mips16:mips16:
39 // start-sanitize-r5900
40 :model:::r5900:mips5900:
42 :model:::r3900:mips3900:
43 // start-sanitize-tx19
46 // start-sanitize-vr4320
47 :model:::vr4320:mips4320:
48 // end-sanitize-vr4320
49 // start-sanitize-vr5400
50 :model:::vr5400:mips5400:
52 // end-sanitize-vr5400
53 :model:::vr5000:mips5000:
57 // Pseudo instructions known by IGEN
60 SignalException (ReservedInstruction, 0);
64 // Pseudo instructions known by interp.c
65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
69 SignalException (ReservedInstruction, instruction_0);
77 // CPU Instruction Set (mipsI - mipsIV)
81 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
82 "add r<RD>, r<RS>, r<RT>"
83 *mipsI,mipsII,mipsIII,mipsIV:
85 // start-sanitize-vr4320
87 // end-sanitize-vr4320
88 // start-sanitize-vr5400
90 // end-sanitize-vr5400
91 // start-sanitize-r5900
95 // start-sanitize-tx19
99 ALU32_BEGIN (GPR[RS]);
105 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
106 "addi r<RT>, r<RS>, IMMEDIATE"
107 *mipsI,mipsII,mipsIII,mipsIV:
109 // start-sanitize-vr4320
111 // end-sanitize-vr4320
112 // start-sanitize-vr5400
114 // end-sanitize-vr5400
115 // start-sanitize-r5900
117 // end-sanitize-r5900
119 // start-sanitize-tx19
123 ALU32_BEGIN (GPR[RS]);
124 ALU32_ADD (EXTEND16 (IMMEDIATE));
129 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
130 "add r<RT>, r<RS>, <IMMEDIATE>"
131 *mipsI,mipsII,mipsIII,mipsIV:
133 // start-sanitize-vr4320
135 // end-sanitize-vr4320
136 // start-sanitize-vr5400
138 // end-sanitize-vr5400
139 // start-sanitize-r5900
141 // end-sanitize-r5900
143 // start-sanitize-tx19
147 signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
148 GPR[RT] = EXTEND32 (temp);
152 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
153 *mipsI,mipsII,mipsIII,mipsIV:
155 // start-sanitize-vr4320
157 // end-sanitize-vr4320
158 // start-sanitize-vr5400
160 // end-sanitize-vr5400
161 // start-sanitize-r5900
163 // end-sanitize-r5900
165 // start-sanitize-tx19
169 signed32 temp = GPR[RS] + GPR[RT];
170 GPR[RD] = EXTEND32 (temp);
174 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
175 "and r<RD>, r<RS>, r<RT>"
176 *mipsI,mipsII,mipsIII,mipsIV:
178 // start-sanitize-vr4320
180 // end-sanitize-vr4320
181 // start-sanitize-vr5400
183 // end-sanitize-vr5400
184 // start-sanitize-r5900
186 // end-sanitize-r5900
188 // start-sanitize-tx19
192 GPR[RD] = GPR[RS] & GPR[RT];
196 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
197 "and r<RT>, r<RS>, <IMMEDIATE>"
198 *mipsI,mipsII,mipsIII,mipsIV:
200 // start-sanitize-vr4320
202 // end-sanitize-vr4320
203 // start-sanitize-vr5400
205 // end-sanitize-vr5400
206 // start-sanitize-r5900
208 // end-sanitize-r5900
210 // start-sanitize-tx19
214 GPR[RT] = GPR[RS] & IMMEDIATE;
218 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
219 "beq r<RS>, r<RT>, <OFFSET>"
220 *mipsI,mipsII,mipsIII,mipsIV:
222 // start-sanitize-vr4320
224 // end-sanitize-vr4320
225 // start-sanitize-vr5400
227 // end-sanitize-vr5400
228 // start-sanitize-r5900
230 // end-sanitize-r5900
232 // start-sanitize-tx19
236 address_word offset = EXTEND16 (OFFSET) << 2;
237 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
238 DELAY_SLOT (NIA + offset);
242 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
243 "beql r<RS>, r<RT>, <OFFSET>"
248 // start-sanitize-vr4320
250 // end-sanitize-vr4320
251 // start-sanitize-vr5400
253 // end-sanitize-vr5400
254 // start-sanitize-r5900
256 // end-sanitize-r5900
258 // start-sanitize-tx19
262 address_word offset = EXTEND16 (OFFSET) << 2;
263 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
264 DELAY_SLOT (NIA + offset);
266 NULLIFY_NEXT_INSTRUCTION ();
270 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
271 "bgez r<RS>, <OFFSET>"
272 *mipsI,mipsII,mipsIII,mipsIV:
274 // start-sanitize-vr4320
276 // end-sanitize-vr4320
277 // start-sanitize-vr5400
279 // end-sanitize-vr5400
280 // start-sanitize-r5900
282 // end-sanitize-r5900
284 // start-sanitize-tx19
288 address_word offset = EXTEND16 (OFFSET) << 2;
289 if ((signed_word) GPR[RS] >= 0)
290 DELAY_SLOT (NIA + offset);
294 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
295 "bgezal r<RS>, <OFFSET>"
296 *mipsI,mipsII,mipsIII,mipsIV:
298 // start-sanitize-vr4320
300 // end-sanitize-vr4320
301 // start-sanitize-vr5400
303 // end-sanitize-vr5400
304 // start-sanitize-r5900
306 // end-sanitize-r5900
308 // start-sanitize-tx19
312 address_word offset = EXTEND16 (OFFSET) << 2;
314 if ((signed_word) GPR[RS] >= 0)
315 DELAY_SLOT (NIA + offset);
319 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
320 "bgezall r<RS>, <OFFSET>"
325 // start-sanitize-vr4320
327 // end-sanitize-vr4320
328 // start-sanitize-vr5400
330 // end-sanitize-vr5400
331 // start-sanitize-r5900
333 // end-sanitize-r5900
335 // start-sanitize-tx19
339 address_word offset = EXTEND16 (OFFSET) << 2;
341 /* NOTE: The branch occurs AFTER the next instruction has been
343 if ((signed_word) GPR[RS] >= 0)
344 DELAY_SLOT (NIA + offset);
346 NULLIFY_NEXT_INSTRUCTION ();
350 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
351 "bgezl r<RS>, <OFFSET>"
356 // start-sanitize-vr4320
358 // end-sanitize-vr4320
359 // start-sanitize-vr5400
361 // end-sanitize-vr5400
362 // start-sanitize-r5900
364 // end-sanitize-r5900
366 // start-sanitize-tx19
370 address_word offset = EXTEND16 (OFFSET) << 2;
371 if ((signed_word) GPR[RS] >= 0)
372 DELAY_SLOT (NIA + offset);
374 NULLIFY_NEXT_INSTRUCTION ();
378 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
379 "bgtz r<RS>, <OFFSET>"
380 *mipsI,mipsII,mipsIII,mipsIV:
382 // start-sanitize-vr4320
384 // end-sanitize-vr4320
385 // start-sanitize-vr5400
387 // end-sanitize-vr5400
388 // start-sanitize-r5900
390 // end-sanitize-r5900
392 // start-sanitize-tx19
396 address_word offset = EXTEND16 (OFFSET) << 2;
397 if ((signed_word) GPR[RS] > 0)
398 DELAY_SLOT (NIA + offset);
402 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
403 "bgtzl r<RS>, <OFFSET>"
408 // start-sanitize-vr4320
410 // end-sanitize-vr4320
411 // start-sanitize-vr5400
413 // end-sanitize-vr5400
414 // start-sanitize-r5900
416 // end-sanitize-r5900
418 // start-sanitize-tx19
422 address_word offset = EXTEND16 (OFFSET) << 2;
423 /* NOTE: The branch occurs AFTER the next instruction has been
425 if ((signed_word) GPR[RS] > 0)
426 DELAY_SLOT (NIA + offset);
428 NULLIFY_NEXT_INSTRUCTION ();
432 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
433 "blez r<RS>, <OFFSET>"
434 *mipsI,mipsII,mipsIII,mipsIV:
436 // start-sanitize-vr4320
438 // end-sanitize-vr4320
439 // start-sanitize-vr5400
441 // end-sanitize-vr5400
442 // start-sanitize-r5900
444 // end-sanitize-r5900
446 // start-sanitize-tx19
450 address_word offset = EXTEND16 (OFFSET) << 2;
451 /* NOTE: The branch occurs AFTER the next instruction has been
453 if ((signed_word) GPR[RS] <= 0)
454 DELAY_SLOT (NIA + offset);
458 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
459 "bgezl r<RS>, <OFFSET>"
464 // start-sanitize-vr4320
466 // end-sanitize-vr4320
467 // start-sanitize-vr5400
469 // end-sanitize-vr5400
470 // start-sanitize-r5900
472 // end-sanitize-r5900
474 // start-sanitize-tx19
478 address_word offset = EXTEND16 (OFFSET) << 2;
479 if ((signed_word) GPR[RS] <= 0)
480 DELAY_SLOT (NIA + offset);
482 NULLIFY_NEXT_INSTRUCTION ();
486 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
487 "bltz r<RS>, <OFFSET>"
488 *mipsI,mipsII,mipsIII,mipsIV:
490 // start-sanitize-vr4320
492 // end-sanitize-vr4320
493 // start-sanitize-vr5400
495 // end-sanitize-vr5400
496 // start-sanitize-r5900
498 // end-sanitize-r5900
500 // start-sanitize-tx19
504 address_word offset = EXTEND16 (OFFSET) << 2;
505 if ((signed_word) GPR[RS] < 0)
506 DELAY_SLOT (NIA + offset);
510 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
511 "bltzal r<RS>, <OFFSET>"
512 *mipsI,mipsII,mipsIII,mipsIV:
514 // start-sanitize-vr4320
516 // end-sanitize-vr4320
517 // start-sanitize-vr5400
519 // end-sanitize-vr5400
520 // start-sanitize-r5900
522 // end-sanitize-r5900
524 // start-sanitize-tx19
528 address_word offset = EXTEND16 (OFFSET) << 2;
530 /* NOTE: The branch occurs AFTER the next instruction has been
532 if ((signed_word) GPR[RS] < 0)
533 DELAY_SLOT (NIA + offset);
537 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
538 "bltzall r<RS>, <OFFSET>"
543 // start-sanitize-vr4320
545 // end-sanitize-vr4320
546 // start-sanitize-vr5400
548 // end-sanitize-vr5400
549 // start-sanitize-r5900
551 // end-sanitize-r5900
553 // start-sanitize-tx19
557 address_word offset = EXTEND16 (OFFSET) << 2;
559 if ((signed_word) GPR[RS] < 0)
560 DELAY_SLOT (NIA + offset);
562 NULLIFY_NEXT_INSTRUCTION ();
566 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
567 "bltzl r<RS>, <OFFSET>"
572 // start-sanitize-vr4320
574 // end-sanitize-vr4320
575 // start-sanitize-vr5400
577 // end-sanitize-vr5400
578 // start-sanitize-r5900
580 // end-sanitize-r5900
582 // start-sanitize-tx19
586 address_word offset = EXTEND16 (OFFSET) << 2;
587 /* NOTE: The branch occurs AFTER the next instruction has been
589 if ((signed_word) GPR[RS] < 0)
590 DELAY_SLOT (NIA + offset);
592 NULLIFY_NEXT_INSTRUCTION ();
596 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
597 "bne r<RS>, r<RT>, <OFFSET>"
598 *mipsI,mipsII,mipsIII,mipsIV:
600 // start-sanitize-vr4320
602 // end-sanitize-vr4320
603 // start-sanitize-vr5400
605 // end-sanitize-vr5400
606 // start-sanitize-r5900
608 // end-sanitize-r5900
610 // start-sanitize-tx19
614 address_word offset = EXTEND16 (OFFSET) << 2;
615 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
616 DELAY_SLOT (NIA + offset);
620 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
621 "bnel r<RS>, r<RT>, <OFFSET>"
626 // start-sanitize-vr4320
628 // end-sanitize-vr4320
629 // start-sanitize-vr5400
631 // end-sanitize-vr5400
632 // start-sanitize-r5900
634 // end-sanitize-r5900
636 // start-sanitize-tx19
640 address_word offset = EXTEND16 (OFFSET) << 2;
641 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
642 DELAY_SLOT (NIA + offset);
644 NULLIFY_NEXT_INSTRUCTION ();
648 000000,20.CODE,001101:SPECIAL:32::BREAK
650 *mipsI,mipsII,mipsIII,mipsIV:
652 // start-sanitize-vr4320
654 // end-sanitize-vr4320
655 // start-sanitize-vr5400
657 // end-sanitize-vr5400
658 // start-sanitize-r5900
660 // end-sanitize-r5900
662 // start-sanitize-tx19
666 SignalException(BreakPoint, instruction_0);
670 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
672 *mipsI,mipsII,mipsIII,mipsIV:
673 // start-sanitize-r5900
675 // end-sanitize-r5900
677 // start-sanitize-tx19
681 DecodeCoproc (instruction_0);
685 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
686 "dadd r<RD>, r<RS>, r<RT>"
690 // start-sanitize-vr4320
692 // end-sanitize-vr4320
693 // start-sanitize-vr5400
695 // end-sanitize-vr5400
696 // start-sanitize-r5900
698 // end-sanitize-r5900
699 // start-sanitize-tx19
703 /* this check's for overflow */
704 ALU64_BEGIN (GPR[RS]);
710 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
711 "daddi r<RT>, r<RS>, <IMMEDIATE>"
715 // start-sanitize-vr4320
717 // end-sanitize-vr4320
718 // start-sanitize-vr5400
720 // end-sanitize-vr5400
721 // start-sanitize-r5900
723 // end-sanitize-r5900
724 // start-sanitize-tx19
728 ALU64_BEGIN (GPR[RS]);
729 ALU64_ADD (EXTEND16 (IMMEDIATE));
734 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
735 "daddu r<RT>, r<RS>, <IMMEDIATE>"
739 // start-sanitize-vr4320
741 // end-sanitize-vr4320
742 // start-sanitize-vr5400
744 // end-sanitize-vr5400
745 // start-sanitize-r5900
747 // end-sanitize-r5900
748 // start-sanitize-tx19
752 GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
756 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
757 "daddu r<RD>, r<RS>, r<RT>"
761 // start-sanitize-vr4320
763 // end-sanitize-vr4320
764 // start-sanitize-vr5400
766 // end-sanitize-vr5400
767 // start-sanitize-r5900
769 // end-sanitize-r5900
770 // start-sanitize-tx19
774 GPR[RD] = GPR[RS] + GPR[RT];
778 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
783 // start-sanitize-vr4320
785 // end-sanitize-vr4320
786 // start-sanitize-vr5400
788 // end-sanitize-vr5400
789 // start-sanitize-r5900
791 // end-sanitize-r5900
792 // start-sanitize-tx19
796 CHECKHILO ("Division");
798 signed64 n = GPR[RS];
799 signed64 d = GPR[RT];
802 LO = SIGNED64 (0x8000000000000000);
805 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
807 LO = SIGNED64 (0x8000000000000000);
820 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
825 // start-sanitize-vr4320
827 // end-sanitize-vr4320
828 // start-sanitize-vr5400
830 // end-sanitize-vr5400
831 // start-sanitize-tx19
835 CHECKHILO ("Division");
837 unsigned64 n = GPR[RS];
838 unsigned64 d = GPR[RT];
841 LO = SIGNED64 (0x8000000000000000);
853 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
855 *mipsI,mipsII,mipsIII,mipsIV:
857 // start-sanitize-vr4320
859 // end-sanitize-vr4320
860 // start-sanitize-vr5400
862 // end-sanitize-vr5400
863 // start-sanitize-r5900
865 // end-sanitize-r5900
867 // start-sanitize-tx19
871 CHECKHILO("Division");
873 signed32 n = GPR[RS];
874 signed32 d = GPR[RT];
877 LO = EXTEND32 (0x80000000);
880 else if (n == SIGNED32 (0x80000000) && d == -1)
882 LO = EXTEND32 (0x80000000);
887 LO = EXTEND32 (n / d);
888 HI = EXTEND32 (n % d);
894 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
896 *mipsI,mipsII,mipsIII,mipsIV:
898 // start-sanitize-vr4320
900 // end-sanitize-vr4320
901 // start-sanitize-vr5400
903 // end-sanitize-vr5400
904 // start-sanitize-r5900
906 // end-sanitize-r5900
908 // start-sanitize-tx19
912 CHECKHILO ("Division");
914 unsigned32 n = GPR[RS];
915 unsigned32 d = GPR[RT];
918 LO = EXTEND32 (0x80000000);
923 LO = EXTEND32 (n / d);
924 HI = EXTEND32 (n % d);
930 :function:::void:do_dmult:int rs, int rt, int rd, int signed_p
940 unsigned64 op1 = GPR[rs];
941 unsigned64 op2 = GPR[rt];
942 CHECKHILO ("Multiplication");
943 /* make signed multiply unsigned */
958 /* multuply out the 4 sub products */
959 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
960 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
961 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
962 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
963 /* add the products */
964 mid = ((unsigned64) VH4_8 (m00)
965 + (unsigned64) VL4_8 (m10)
966 + (unsigned64) VL4_8 (m01));
967 lo = U8_4 (mid, m00);
969 + (unsigned64) VH4_8 (mid)
970 + (unsigned64) VH4_8 (m01)
971 + (unsigned64) VH4_8 (m10));
981 /* save the result HI/LO (and a gpr) */
989 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
992 // start-sanitize-tx19
995 // start-sanitize-vr4320
997 // end-sanitize-vr4320
999 do_dmult (SD_, RS, RT, 0, 1);
1002 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1003 "dmult r<RS>, r<RT>":RD == 0
1004 "dmult r<RD>, r<RS>, r<RT>"
1006 // start-sanitize-vr5400
1008 // end-sanitize-vr5400
1010 do_dmult (SD_, RS, RT, RD, 1);
1015 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1016 "dmultu r<RS>, r<RT>"
1018 // start-sanitize-tx19
1020 // end-sanitize-tx19
1021 // start-sanitize-vr4320
1023 // end-sanitize-vr4320
1025 do_dmult (SD_, RS, RT, 0, 0);
1028 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1029 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1030 "dmultu r<RS>, r<RT>"
1032 // start-sanitize-vr5400
1034 // end-sanitize-vr5400
1036 do_dmult (SD_, RS, RT, RD, 0);
1041 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1042 "dsll r<RD>, r<RT>, <SHIFT>"
1046 // start-sanitize-vr4320
1048 // end-sanitize-vr4320
1049 // start-sanitize-vr5400
1051 // end-sanitize-vr5400
1052 // start-sanitize-r5900
1054 // end-sanitize-r5900
1055 // start-sanitize-tx19
1057 // end-sanitize-tx19
1060 GPR[RD] = GPR[RT] << s;
1064 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1065 "dsll32 r<RD>, r<RT>, <SHIFT>"
1069 // start-sanitize-vr4320
1071 // end-sanitize-vr4320
1072 // start-sanitize-vr5400
1074 // end-sanitize-vr5400
1075 // start-sanitize-r5900
1077 // end-sanitize-r5900
1078 // start-sanitize-tx19
1080 // end-sanitize-tx19
1083 GPR[RD] = GPR[RT] << s;
1087 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1088 "dsllv r<RD>, r<RT>, r<RS>"
1092 // start-sanitize-vr4320
1094 // end-sanitize-vr4320
1095 // start-sanitize-vr5400
1097 // end-sanitize-vr5400
1098 // start-sanitize-r5900
1100 // end-sanitize-r5900
1101 // start-sanitize-tx19
1103 // end-sanitize-tx19
1105 int s = MASKED64 (GPR[RS], 5, 0);
1106 GPR[RD] = GPR[RT] << s;
1110 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1111 "dsra r<RD>, r<RT>, <SHIFT>"
1115 // start-sanitize-vr4320
1117 // end-sanitize-vr4320
1118 // start-sanitize-vr5400
1120 // end-sanitize-vr5400
1121 // start-sanitize-r5900
1123 // end-sanitize-r5900
1124 // start-sanitize-tx19
1126 // end-sanitize-tx19
1129 GPR[RD] = ((signed64) GPR[RT]) >> s;
1133 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1134 "dsra32 r<RT>, r<RD>, <SHIFT>"
1138 // start-sanitize-vr4320
1140 // end-sanitize-vr4320
1141 // start-sanitize-vr5400
1143 // end-sanitize-vr5400
1144 // start-sanitize-r5900
1146 // end-sanitize-r5900
1147 // start-sanitize-tx19
1149 // end-sanitize-tx19
1152 GPR[RD] = ((signed64) GPR[RT]) >> s;
1156 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1157 "dsra32 r<RT>, r<RD>, r<RS>"
1161 // start-sanitize-vr4320
1163 // end-sanitize-vr4320
1164 // start-sanitize-vr5400
1166 // end-sanitize-vr5400
1167 // start-sanitize-r5900
1169 // end-sanitize-r5900
1170 // start-sanitize-tx19
1172 // end-sanitize-tx19
1174 int s = MASKED64 (GPR[RS], 5, 0);
1175 GPR[RD] = ((signed64) GPR[RT]) >> s;
1179 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1180 "dsrav r<RD>, r<RT>, <SHIFT>"
1184 // start-sanitize-vr4320
1186 // end-sanitize-vr4320
1187 // start-sanitize-vr5400
1189 // end-sanitize-vr5400
1190 // start-sanitize-r5900
1192 // end-sanitize-r5900
1193 // start-sanitize-tx19
1195 // end-sanitize-tx19
1198 GPR[RD] = (unsigned64) GPR[RT] >> s;
1202 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1203 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1207 // start-sanitize-vr4320
1209 // end-sanitize-vr4320
1210 // start-sanitize-vr5400
1212 // end-sanitize-vr5400
1213 // start-sanitize-r5900
1215 // end-sanitize-r5900
1216 // start-sanitize-tx19
1218 // end-sanitize-tx19
1221 GPR[RD] = (unsigned64) GPR[RT] >> s;
1225 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1226 "dsrl32 r<RD>, r<RT>, r<RS>"
1230 // start-sanitize-vr4320
1232 // end-sanitize-vr4320
1233 // start-sanitize-vr5400
1235 // end-sanitize-vr5400
1236 // start-sanitize-r5900
1238 // end-sanitize-r5900
1239 // start-sanitize-tx19
1241 // end-sanitize-tx19
1243 int s = MASKED64 (GPR[RS], 5, 0);
1244 GPR[RD] = (unsigned64) GPR[RT] >> s;
1248 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1249 "dsub r<RD>, r<RS>, r<RT>"
1253 // start-sanitize-vr4320
1255 // end-sanitize-vr4320
1256 // start-sanitize-vr5400
1258 // end-sanitize-vr5400
1259 // start-sanitize-r5900
1261 // end-sanitize-r5900
1262 // start-sanitize-tx19
1264 // end-sanitize-tx19
1266 ALU64_BEGIN (GPR[RS]);
1267 ALU64_SUB (GPR[RT]);
1268 ALU64_END (GPR[RD]);
1272 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1273 "dsubu r<RD>, r<RS>, r<RT>"
1277 // start-sanitize-vr4320
1279 // end-sanitize-vr4320
1280 // start-sanitize-vr5400
1282 // end-sanitize-vr5400
1283 // start-sanitize-r5900
1285 // end-sanitize-r5900
1286 // start-sanitize-tx19
1288 // end-sanitize-tx19
1290 GPR[RD] = GPR[RS] - GPR[RT];
1294 000010,26.INSTR_INDEX:NORMAL:32::J
1296 *mipsI,mipsII,mipsIII,mipsIV:
1298 // start-sanitize-vr4320
1300 // end-sanitize-vr4320
1301 // start-sanitize-vr5400
1303 // end-sanitize-vr5400
1304 // start-sanitize-r5900
1306 // end-sanitize-r5900
1308 // start-sanitize-tx19
1310 // end-sanitize-tx19
1312 /* NOTE: The region used is that of the delay slot NIA and NOT the
1313 current instruction */
1314 address_word region = (NIA & MASK (63, 28));
1315 DELAY_SLOT (region | (INSTR_INDEX << 2));
1319 000011,26.INSTR_INDEX:NORMAL:32::JAL
1321 *mipsI,mipsII,mipsIII,mipsIV:
1323 // start-sanitize-vr4320
1325 // end-sanitize-vr4320
1326 // start-sanitize-vr5400
1328 // end-sanitize-vr5400
1329 // start-sanitize-r5900
1331 // end-sanitize-r5900
1333 // start-sanitize-tx19
1335 // end-sanitize-tx19
1337 /* NOTE: The region used is that of the delay slot and NOT the
1338 current instruction */
1339 address_word region = (NIA & MASK (63, 28));
1341 DELAY_SLOT (region | (INSTR_INDEX << 2));
1345 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1346 "jalr r<RS>":RD == 31
1348 *mipsI,mipsII,mipsIII,mipsIV:
1350 // start-sanitize-vr4320
1352 // end-sanitize-vr4320
1353 // start-sanitize-vr5400
1355 // end-sanitize-vr5400
1356 // start-sanitize-r5900
1358 // end-sanitize-r5900
1360 // start-sanitize-tx19
1362 // end-sanitize-tx19
1364 address_word temp = GPR[RS];
1370 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1372 *mipsI,mipsII,mipsIII,mipsIV:
1374 // start-sanitize-vr4320
1376 // end-sanitize-vr4320
1377 // start-sanitize-vr5400
1379 // end-sanitize-vr5400
1380 // start-sanitize-r5900
1382 // end-sanitize-r5900
1384 // start-sanitize-tx19
1386 // end-sanitize-tx19
1388 DELAY_SLOT (GPR[RS]);
1392 :function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset
1394 address_word vaddr = offset + gpr_base;
1397 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1399 unsigned64 memval = 0;
1400 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1401 unsigned int reverse = (ReverseEndian ? mask : 0);
1402 unsigned int bigend = (BigEndianCPU ? mask : 0);
1404 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1405 LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL);
1406 byte = ((vaddr & mask) ^ bigend);
1407 GPR[rt] = EXTEND8 ((memval >> (8 * byte)));
1411 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1412 "lb r<RT>, <OFFSET>(r<BASE>)"
1413 *mipsI,mipsII,mipsIII,mipsIV:
1415 // start-sanitize-vr4320
1417 // end-sanitize-vr4320
1418 // start-sanitize-vr5400
1420 // end-sanitize-vr5400
1421 // start-sanitize-r5900
1423 // end-sanitize-r5900
1425 // start-sanitize-tx19
1427 // end-sanitize-tx19
1429 do_load_byte (SD_, GPR[BASE], RT, OFFSET);
1431 unsigned32 instruction = instruction_0;
1432 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1433 int destreg = ((instruction >> 16) & 0x0000001F);
1434 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1436 address_word vaddr = ((uword64)op1 + offset);
1440 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1443 uword64 memval1 = 0;
1445 unsigned int shift = 0;
1446 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1447 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1449 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1450 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1451 byte = ((vaddr & mask) ^ (bigend << shift));
1452 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1460 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1461 "lbu r<RT>, <OFFSET>(r<BASE>)"
1462 *mipsI,mipsII,mipsIII,mipsIV:
1464 // start-sanitize-vr4320
1466 // end-sanitize-vr4320
1467 // start-sanitize-vr5400
1469 // end-sanitize-vr5400
1470 // start-sanitize-r5900
1472 // end-sanitize-r5900
1474 // start-sanitize-tx19
1476 // end-sanitize-tx19
1478 unsigned32 instruction = instruction_0;
1479 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1480 int destreg = ((instruction >> 16) & 0x0000001F);
1481 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1483 address_word vaddr = ((unsigned64)op1 + offset);
1487 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1489 unsigned64 memval = 0;
1490 unsigned64 memval1 = 0;
1491 unsigned64 mask = 0x7;
1492 unsigned int shift = 0;
1493 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1494 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1496 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1497 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1498 byte = ((vaddr & mask) ^ (bigend << shift));
1499 GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1506 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1507 "ld r<RT>, <OFFSET>(r<BASE>)"
1511 // start-sanitize-vr4320
1513 // end-sanitize-vr4320
1514 // start-sanitize-vr5400
1516 // end-sanitize-vr5400
1517 // start-sanitize-r5900
1519 // end-sanitize-r5900
1520 // start-sanitize-tx19
1522 // end-sanitize-tx19
1524 unsigned32 instruction = instruction_0;
1525 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1526 int destreg = ((instruction >> 16) & 0x0000001F);
1527 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1529 address_word vaddr = ((unsigned64)op1 + offset);
1532 if ((vaddr & 7) != 0)
1533 SignalExceptionAddressLoad();
1536 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1538 unsigned64 memval = 0;
1539 unsigned64 memval1 = 0;
1540 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1541 GPR[destreg] = memval;
1548 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1549 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1554 // start-sanitize-vr4320
1556 // end-sanitize-vr4320
1557 // start-sanitize-vr5400
1559 // end-sanitize-vr5400
1561 // start-sanitize-tx19
1563 // end-sanitize-tx19
1565 unsigned32 instruction = instruction_0;
1566 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1567 int destreg = ((instruction >> 16) & 0x0000001F);
1568 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1570 address_word vaddr = ((unsigned64)op1 + offset);
1573 if ((vaddr & 7) != 0)
1574 SignalExceptionAddressLoad();
1577 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1579 unsigned64 memval = 0;
1580 unsigned64 memval1 = 0;
1581 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1582 COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1589 // start-sanitize-sky
1590 110110,5.BASE,5.RT,16.OFFSET:NORMAL:64::LQC2
1591 "lqc2 r<RT>, <OFFSET>(r<BASE>)"
1595 unsigned32 instruction = instruction_0;
1596 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1597 int destreg = ((instruction >> 16) & 0x0000001F);
1598 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1600 address_word vaddr = ((unsigned64)op1 + offset);
1603 if ((vaddr & 0x0f) != 0)
1604 SignalExceptionAddressLoad();
1607 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1609 unsigned64 memval = 0;
1610 unsigned64 memval1 = 0;
1611 unsigned128 qw = U16_8(memval, memval1); /* XXX: check order */
1612 /* XXX: block on VU0 pipeline if necessary */
1613 LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
1614 COP_LQ(((instruction >> 26) & 0x3),destreg,qw);;
1618 #endif /* TARGET_SKY */
1623 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1624 "ldl r<RT>, <OFFSET>(r<BASE>)"
1628 // start-sanitize-vr4320
1630 // end-sanitize-vr4320
1631 // start-sanitize-vr5400
1633 // end-sanitize-vr5400
1634 // start-sanitize-r5900
1636 // end-sanitize-r5900
1637 // start-sanitize-tx19
1639 // end-sanitize-tx19
1641 unsigned32 instruction = instruction_0;
1642 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1643 int destreg = ((instruction >> 16) & 0x0000001F);
1644 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1646 address_word vaddr = ((unsigned64)op1 + offset);
1650 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1652 unsigned64 memval = 0;
1653 unsigned64 memval1 = 0;
1654 unsigned64 mask = 7;
1655 unsigned int reverse = (ReverseEndian ? mask : 0);
1656 unsigned int bigend = (BigEndianCPU ? mask : 0);
1658 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1659 byte = ((vaddr & mask) ^ bigend);
1662 LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1663 GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1670 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1671 "ldr r<RT>, <OFFSET>(r<BASE>)"
1675 // start-sanitize-vr4320
1677 // end-sanitize-vr4320
1678 // start-sanitize-vr5400
1680 // end-sanitize-vr5400
1681 // start-sanitize-r5900
1683 // end-sanitize-r5900
1684 // start-sanitize-tx19
1686 // end-sanitize-tx19
1688 unsigned32 instruction = instruction_0;
1689 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1690 int destreg = ((instruction >> 16) & 0x0000001F);
1691 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1693 address_word vaddr = ((unsigned64)op1 + offset);
1697 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1699 unsigned64 memval = 0;
1700 unsigned64 memval1 = 0;
1701 unsigned64 mask = 7;
1702 unsigned int reverse = (ReverseEndian ? mask : 0);
1703 unsigned int bigend = (BigEndianCPU ? mask : 0);
1705 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1706 byte = ((vaddr & mask) ^ bigend);
1709 LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1715 srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1716 GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1724 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1725 "lh r<RT>, <OFFSET>(r<BASE>)"
1726 *mipsI,mipsII,mipsIII,mipsIV:
1728 // start-sanitize-vr4320
1730 // end-sanitize-vr4320
1731 // start-sanitize-vr5400
1733 // end-sanitize-vr5400
1734 // start-sanitize-r5900
1736 // end-sanitize-r5900
1738 // start-sanitize-tx19
1740 // end-sanitize-tx19
1742 unsigned32 instruction = instruction_0;
1743 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1744 int destreg = ((instruction >> 16) & 0x0000001F);
1745 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1747 address_word vaddr = ((unsigned64)op1 + offset);
1750 if ((vaddr & 1) != 0)
1751 SignalExceptionAddressLoad();
1754 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1756 unsigned64 memval = 0;
1757 unsigned64 memval1 = 0;
1758 unsigned64 mask = 0x7;
1759 unsigned int shift = 1;
1760 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1761 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1763 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1764 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1765 byte = ((vaddr & mask) ^ (bigend << shift));
1766 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1773 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1774 "lhu r<RT>, <OFFSET>(r<BASE>)"
1775 *mipsI,mipsII,mipsIII,mipsIV:
1777 // start-sanitize-vr4320
1779 // end-sanitize-vr4320
1780 // start-sanitize-vr5400
1782 // end-sanitize-vr5400
1783 // start-sanitize-r5900
1785 // end-sanitize-r5900
1787 // start-sanitize-tx19
1789 // end-sanitize-tx19
1791 unsigned32 instruction = instruction_0;
1792 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1793 int destreg = ((instruction >> 16) & 0x0000001F);
1794 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1796 address_word vaddr = ((unsigned64)op1 + offset);
1799 if ((vaddr & 1) != 0)
1800 SignalExceptionAddressLoad();
1803 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1805 unsigned64 memval = 0;
1806 unsigned64 memval1 = 0;
1807 unsigned64 mask = 0x7;
1808 unsigned int shift = 1;
1809 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1810 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1812 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1813 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1814 byte = ((vaddr & mask) ^ (bigend << shift));
1815 GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1822 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1823 "ll r<RT>, <OFFSET>(r<BASE>)"
1828 // start-sanitize-vr4320
1830 // end-sanitize-vr4320
1831 // start-sanitize-vr5400
1833 // end-sanitize-vr5400
1834 // start-sanitize-r5900
1836 // end-sanitize-r5900
1837 // start-sanitize-tx19
1839 // end-sanitize-tx19
1841 unsigned32 instruction = instruction_0;
1842 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1843 int destreg = ((instruction >> 16) & 0x0000001F);
1844 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1846 address_word vaddr = ((unsigned64)op1 + offset);
1849 if ((vaddr & 3) != 0)
1850 SignalExceptionAddressLoad();
1853 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1855 unsigned64 memval = 0;
1856 unsigned64 memval1 = 0;
1857 unsigned64 mask = 0x7;
1858 unsigned int shift = 2;
1859 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1860 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1862 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1863 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1864 byte = ((vaddr & mask) ^ (bigend << shift));
1865 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1873 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1874 "lld r<RT>, <OFFSET>(r<BASE>)"
1878 // start-sanitize-vr4320
1880 // end-sanitize-vr4320
1881 // start-sanitize-vr5400
1883 // end-sanitize-vr5400
1884 // start-sanitize-r5900
1886 // end-sanitize-r5900
1887 // start-sanitize-tx19
1889 // end-sanitize-tx19
1891 unsigned32 instruction = instruction_0;
1892 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1893 int destreg = ((instruction >> 16) & 0x0000001F);
1894 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1896 address_word vaddr = ((unsigned64)op1 + offset);
1899 if ((vaddr & 7) != 0)
1900 SignalExceptionAddressLoad();
1903 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1905 unsigned64 memval = 0;
1906 unsigned64 memval1 = 0;
1907 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1908 GPR[destreg] = memval;
1916 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1917 "lui r<RT>, <IMMEDIATE>"
1918 *mipsI,mipsII,mipsIII,mipsIV:
1920 // start-sanitize-vr4320
1922 // end-sanitize-vr4320
1923 // start-sanitize-vr5400
1925 // end-sanitize-vr5400
1926 // start-sanitize-r5900
1928 // end-sanitize-r5900
1930 // start-sanitize-tx19
1932 // end-sanitize-tx19
1934 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1938 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1939 "lw r<RT>, <OFFSET>(r<BASE>)"
1940 *mipsI,mipsII,mipsIII,mipsIV:
1942 // start-sanitize-vr4320
1944 // end-sanitize-vr4320
1945 // start-sanitize-vr5400
1947 // end-sanitize-vr5400
1948 // start-sanitize-r5900
1950 // end-sanitize-r5900
1952 // start-sanitize-tx19
1954 // end-sanitize-tx19
1956 unsigned32 instruction = instruction_0;
1957 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1958 int destreg = ((instruction >> 16) & 0x0000001F);
1959 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1961 address_word vaddr = ((unsigned64)op1 + offset);
1964 if ((vaddr & 3) != 0)
1965 SignalExceptionAddressLoad();
1968 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1970 unsigned64 memval = 0;
1971 unsigned64 memval1 = 0;
1972 unsigned64 mask = 0x7;
1973 unsigned int shift = 2;
1974 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1975 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1977 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1978 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1979 byte = ((vaddr & mask) ^ (bigend << shift));
1980 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1987 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1988 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1989 *mipsI,mipsII,mipsIII,mipsIV:
1991 // start-sanitize-vr4320
1993 // end-sanitize-vr4320
1994 // start-sanitize-vr5400
1996 // end-sanitize-vr5400
1997 // start-sanitize-r5900
1999 // end-sanitize-r5900
2001 // start-sanitize-tx19
2003 // end-sanitize-tx19
2005 unsigned32 instruction = instruction_0;
2006 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2007 int destreg = ((instruction >> 16) & 0x0000001F);
2008 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2010 address_word vaddr = ((unsigned64)op1 + offset);
2013 if ((vaddr & 3) != 0)
2014 SignalExceptionAddressLoad();
2017 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2019 unsigned64 memval = 0;
2020 unsigned64 memval1 = 0;
2021 unsigned64 mask = 0x7;
2022 unsigned int shift = 2;
2023 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2024 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2026 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2027 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2028 byte = ((vaddr & mask) ^ (bigend << shift));
2029 COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
2036 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2037 "lwl r<RT>, <OFFSET>(r<BASE>)"
2038 *mipsI,mipsII,mipsIII,mipsIV:
2040 // start-sanitize-vr4320
2042 // end-sanitize-vr4320
2043 // start-sanitize-vr5400
2045 // end-sanitize-vr5400
2046 // start-sanitize-r5900
2048 // end-sanitize-r5900
2050 // start-sanitize-tx19
2052 // end-sanitize-tx19
2054 unsigned32 instruction = instruction_0;
2055 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2056 int destreg = ((instruction >> 16) & 0x0000001F);
2057 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2059 address_word vaddr = ((unsigned64)op1 + offset);
2063 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2065 unsigned64 memval = 0;
2066 unsigned64 memval1 = 0;
2067 unsigned64 mask = 3;
2068 unsigned int reverse = (ReverseEndian ? mask : 0);
2069 unsigned int bigend = (BigEndianCPU ? mask : 0);
2071 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2072 byte = ((vaddr & mask) ^ bigend);
2075 LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
2076 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2079 GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
2080 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
2087 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2088 "lwr r<RT>, <OFFSET>(r<BASE>)"
2089 *mipsI,mipsII,mipsIII,mipsIV:
2091 // start-sanitize-vr4320
2093 // end-sanitize-vr4320
2094 // start-sanitize-vr5400
2096 // end-sanitize-vr5400
2097 // start-sanitize-r5900
2099 // end-sanitize-r5900
2101 // start-sanitize-tx19
2103 // end-sanitize-tx19
2105 unsigned32 instruction = instruction_0;
2106 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2107 int destreg = ((instruction >> 16) & 0x0000001F);
2108 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2110 address_word vaddr = ((unsigned64)op1 + offset);
2114 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2116 unsigned64 memval = 0;
2117 unsigned64 memval1 = 0;
2118 unsigned64 mask = 3;
2119 unsigned int reverse = (ReverseEndian ? mask : 0);
2120 unsigned int bigend = (BigEndianCPU ? mask : 0);
2122 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2123 byte = ((vaddr & mask) ^ bigend);
2126 LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
2127 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2135 srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
2136 GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
2138 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
2145 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2146 "lwu r<RT>, <OFFSET>(r<BASE>)"
2150 // start-sanitize-vr4320
2152 // end-sanitize-vr4320
2153 // start-sanitize-vr5400
2155 // end-sanitize-vr5400
2156 // start-sanitize-r5900
2158 // end-sanitize-r5900
2159 // start-sanitize-tx19
2161 // end-sanitize-tx19
2163 unsigned32 instruction = instruction_0;
2164 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2165 int destreg = ((instruction >> 16) & 0x0000001F);
2166 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2168 address_word vaddr = ((unsigned64)op1 + offset);
2171 if ((vaddr & 3) != 0)
2172 SignalExceptionAddressLoad();
2175 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2177 unsigned64 memval = 0;
2178 unsigned64 memval1 = 0;
2179 unsigned64 mask = 0x7;
2180 unsigned int shift = 2;
2181 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2182 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2184 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2185 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2186 byte = ((vaddr & mask) ^ (bigend << shift));
2187 GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
2194 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2196 *mipsI,mipsII,mipsIII,mipsIV:
2198 // start-sanitize-vr4320
2200 // end-sanitize-vr4320
2201 // start-sanitize-vr5400
2203 // end-sanitize-vr5400
2204 // start-sanitize-r5900
2206 // end-sanitize-r5900
2208 // start-sanitize-tx19
2210 // end-sanitize-tx19
2219 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2221 *mipsI,mipsII,mipsIII,mipsIV:
2223 // start-sanitize-vr4320
2225 // end-sanitize-vr4320
2226 // start-sanitize-vr5400
2228 // end-sanitize-vr5400
2229 // start-sanitize-r5900
2231 // end-sanitize-r5900
2233 // start-sanitize-tx19
2235 // end-sanitize-tx19
2239 LOACCESS = 3; /* 3rd instruction will be safe */
2244 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2245 "movn r<RD>, r<RS>, r<RT>"
2248 // start-sanitize-vr4320
2250 // end-sanitize-vr4320
2251 // start-sanitize-vr5400
2253 // end-sanitize-vr5400
2254 // start-sanitize-r5900
2256 // end-sanitize-r5900
2263 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2264 "movz r<RD>, r<RS>, r<RT>"
2267 // start-sanitize-vr4320
2269 // end-sanitize-vr4320
2270 // start-sanitize-vr5400
2272 // end-sanitize-vr5400
2273 // start-sanitize-r5900
2275 // end-sanitize-r5900
2282 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2284 *mipsI,mipsII,mipsIII,mipsIV:
2286 // start-sanitize-vr4320
2288 // end-sanitize-vr4320
2289 // start-sanitize-vr5400
2291 // end-sanitize-vr5400
2292 // start-sanitize-r5900
2294 // end-sanitize-r5900
2296 // start-sanitize-tx19
2298 // end-sanitize-tx19
2302 sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2306 HIACCESS = 3; /* 3rd instruction will be safe */
2311 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2313 *mipsI,mipsII,mipsIII,mipsIV:
2315 // start-sanitize-vr4320
2317 // end-sanitize-vr4320
2318 // start-sanitize-vr5400
2320 // end-sanitize-vr5400
2321 // start-sanitize-r5900
2323 // end-sanitize-r5900
2325 // start-sanitize-tx19
2327 // end-sanitize-tx19
2331 sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2335 LOACCESS = 3; /* 3rd instruction will be safe */
2340 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2342 *mipsI,mipsII,mipsIII,mipsIV:
2343 // start-sanitize-vr4320
2345 // end-sanitize-vr4320
2348 CHECKHILO ("Multiplication");
2349 prod = (((signed64)(signed32) GPR[RS])
2350 * ((signed64)(signed32) GPR[RT]));
2351 LO = EXTEND32 (VL4_8 (prod));
2352 HI = EXTEND32 (VH4_8 (prod));
2356 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2357 "mult r<RD>, r<RS>, r<RT>"
2359 // start-sanitize-vr5400
2361 // end-sanitize-vr5400
2362 // start-sanitize-r5900
2364 // end-sanitize-r5900
2366 // start-sanitize-tx19
2368 // end-sanitize-tx19
2371 CHECKHILO ("Multiplication");
2372 prod = (((signed64)(signed32) GPR[RS])
2373 * ((signed64)(signed32) GPR[RT]));
2374 LO = EXTEND32 (VL4_8 (prod));
2375 HI = EXTEND32 (VH4_8 (prod));
2381 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2382 "multu r<RS>, r<RT>"
2383 *mipsI,mipsII,mipsIII,mipsIV:
2384 // start-sanitize-vr4320
2386 // end-sanitize-vr4320
2389 CHECKHILO ("Multiplication");
2390 prod = (((unsigned64)(unsigned32) GPR[RS])
2391 * ((unsigned64)(unsigned32) GPR[RT]));
2392 LO = EXTEND32 (VL4_8 (prod));
2393 HI = EXTEND32 (VH4_8 (prod));
2395 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2396 "multu r<RD>, r<RS>, r<RT>"
2398 // start-sanitize-vr5400
2400 // end-sanitize-vr5400
2401 // start-sanitize-r5900
2403 // end-sanitize-r5900
2405 // start-sanitize-tx19
2407 // end-sanitize-tx19
2410 CHECKHILO ("Multiplication");
2411 prod = (((unsigned64)(unsigned32) GPR[RS])
2412 * ((unsigned64)(unsigned32) GPR[RT]));
2413 LO = EXTEND32 (VL4_8 (prod));
2414 HI = EXTEND32 (VH4_8 (prod));
2420 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2421 "nor r<RD>, r<RS>, r<RT>"
2422 *mipsI,mipsII,mipsIII,mipsIV:
2424 // start-sanitize-vr4320
2426 // end-sanitize-vr4320
2427 // start-sanitize-vr5400
2429 // end-sanitize-vr5400
2430 // start-sanitize-r5900
2432 // end-sanitize-r5900
2434 // start-sanitize-tx19
2436 // end-sanitize-tx19
2438 GPR[RD] = ~ (GPR[RS] | GPR[RT]);
2442 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2443 "or r<RD>, r<RS>, r<RT>"
2444 *mipsI,mipsII,mipsIII,mipsIV:
2446 // start-sanitize-vr4320
2448 // end-sanitize-vr4320
2449 // start-sanitize-vr5400
2451 // end-sanitize-vr5400
2452 // start-sanitize-r5900
2454 // end-sanitize-r5900
2456 // start-sanitize-tx19
2458 // end-sanitize-tx19
2460 GPR[RD] = (GPR[RS] | GPR[RT]);
2464 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2465 "ori r<RT>, r<RS>, <IMMEDIATE>"
2466 *mipsI,mipsII,mipsIII,mipsIV:
2468 // start-sanitize-vr4320
2470 // end-sanitize-vr4320
2471 // start-sanitize-vr5400
2473 // end-sanitize-vr5400
2474 // start-sanitize-r5900
2476 // end-sanitize-r5900
2478 // start-sanitize-tx19
2480 // end-sanitize-tx19
2482 GPR[RT] = (GPR[RS] | IMMEDIATE);
2486 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2489 // start-sanitize-vr4320
2491 // end-sanitize-vr4320
2492 // start-sanitize-vr5400
2494 // end-sanitize-vr5400
2495 // start-sanitize-r5900
2497 // end-sanitize-r5900
2499 unsigned32 instruction = instruction_0;
2500 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2501 int hint = ((instruction >> 16) & 0x0000001F);
2502 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2504 address_word vaddr = ((unsigned64)op1 + offset);
2508 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2509 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2514 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2515 "sb r<RT>, <OFFSET>(r<BASE>)"
2516 *mipsI,mipsII,mipsIII,mipsIV:
2518 // start-sanitize-vr4320
2520 // end-sanitize-vr4320
2521 // start-sanitize-vr5400
2523 // end-sanitize-vr5400
2524 // start-sanitize-r5900
2526 // end-sanitize-r5900
2528 // start-sanitize-tx19
2530 // end-sanitize-tx19
2532 unsigned32 instruction = instruction_0;
2533 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2534 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2535 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2537 address_word vaddr = ((unsigned64)op1 + offset);
2541 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2543 unsigned64 memval = 0;
2544 unsigned64 memval1 = 0;
2545 unsigned64 mask = 0x7;
2546 unsigned int shift = 0;
2547 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2548 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2550 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2551 byte = ((vaddr & mask) ^ (bigend << shift));
2552 memval = ((unsigned64) op2 << (8 * byte));
2554 StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2562 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2563 "sc r<RT>, <OFFSET>(r<BASE>)"
2568 // start-sanitize-vr4320
2570 // end-sanitize-vr4320
2571 // start-sanitize-vr5400
2573 // end-sanitize-vr5400
2574 // start-sanitize-r5900
2576 // end-sanitize-r5900
2577 // start-sanitize-tx19
2579 // end-sanitize-tx19
2581 unsigned32 instruction = instruction_0;
2582 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2583 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2584 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2586 address_word vaddr = ((unsigned64)op1 + offset);
2589 if ((vaddr & 3) != 0)
2590 SignalExceptionAddressStore();
2593 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2595 unsigned64 memval = 0;
2596 unsigned64 memval1 = 0;
2597 unsigned64 mask = 0x7;
2599 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2600 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2601 memval = ((unsigned64) op2 << (8 * byte));
2604 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2606 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2613 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2614 "scd r<RT>, <OFFSET>(r<BASE>)"
2618 // start-sanitize-vr4320
2620 // end-sanitize-vr4320
2621 // start-sanitize-vr5400
2623 // end-sanitize-vr5400
2624 // start-sanitize-r5900
2626 // end-sanitize-r5900
2627 // start-sanitize-tx19
2629 // end-sanitize-tx19
2631 unsigned32 instruction = instruction_0;
2632 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2633 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2634 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2636 address_word vaddr = ((unsigned64)op1 + offset);
2639 if ((vaddr & 7) != 0)
2640 SignalExceptionAddressStore();
2643 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2645 unsigned64 memval = 0;
2646 unsigned64 memval1 = 0;
2650 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2652 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2659 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2660 "sd r<RT>, <OFFSET>(r<BASE>)"
2664 // start-sanitize-vr4320
2666 // end-sanitize-vr4320
2667 // start-sanitize-vr5400
2669 // end-sanitize-vr5400
2670 // start-sanitize-r5900
2672 // end-sanitize-r5900
2673 // start-sanitize-tx19
2675 // end-sanitize-tx19
2677 unsigned32 instruction = instruction_0;
2678 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2679 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2680 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2682 address_word vaddr = ((unsigned64)op1 + offset);
2685 if ((vaddr & 7) != 0)
2686 SignalExceptionAddressStore();
2689 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2691 unsigned64 memval = 0;
2692 unsigned64 memval1 = 0;
2695 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2703 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2704 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2709 // start-sanitize-vr4320
2711 // end-sanitize-vr4320
2712 // start-sanitize-vr5400
2714 // end-sanitize-vr5400
2715 // start-sanitize-r5900
2717 // end-sanitize-r5900
2718 // start-sanitize-tx19
2720 // end-sanitize-tx19
2722 unsigned32 instruction = instruction_0;
2723 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2724 int destreg = ((instruction >> 16) & 0x0000001F);
2725 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2727 address_word vaddr = ((unsigned64)op1 + offset);
2730 if ((vaddr & 7) != 0)
2731 SignalExceptionAddressStore();
2734 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2736 unsigned64 memval = 0;
2737 unsigned64 memval1 = 0;
2738 memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2740 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2748 // start-sanitize-sky
2749 111010,5.BASE,5.RT,16.OFFSET:NORMAL:64::SQC2
2750 "sqc2 r<RT>, <OFFSET>(r<BASE>)"
2754 unsigned32 instruction = instruction_0;
2755 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2756 int destreg = ((instruction >> 16) & 0x0000001F);
2757 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2759 address_word vaddr = ((unsigned64)op1 + offset);
2762 if ((vaddr & 0x0f) != 0)
2763 SignalExceptionAddressStore();
2766 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2769 unsigned64 memval0 = 0;
2770 unsigned64 memval1 = 0;
2771 qw = COP_SQ(((instruction >> 26) & 0x3),destreg);
2772 memval0 = *A8_16(& qw, 0);
2773 memval1 = *A8_16(& qw, 1);
2775 StoreMemory(uncached,AccessLength_WORD,memval0,memval1,paddr,vaddr,isREAL);
2780 #endif /* TARGET_SKY */
2786 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2787 "sdl r<RT>, <OFFSET>(r<BASE>)"
2791 // start-sanitize-vr4320
2793 // end-sanitize-vr4320
2794 // start-sanitize-vr5400
2796 // end-sanitize-vr5400
2797 // start-sanitize-r5900
2799 // end-sanitize-r5900
2800 // start-sanitize-tx19
2802 // end-sanitize-tx19
2804 unsigned32 instruction = instruction_0;
2805 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2806 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2807 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2809 address_word vaddr = ((unsigned64)op1 + offset);
2813 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2815 unsigned64 memval = 0;
2816 unsigned64 memval1 = 0;
2817 unsigned64 mask = 7;
2818 unsigned int reverse = (ReverseEndian ? mask : 0);
2819 unsigned int bigend = (BigEndianCPU ? mask : 0);
2821 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2822 byte = ((vaddr & mask) ^ bigend);
2825 memval = (op2 >> (8 * (7 - byte)));
2826 StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2833 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2834 "sdr r<RT>, <OFFSET>(r<BASE>)"
2838 // start-sanitize-vr4320
2840 // end-sanitize-vr4320
2841 // start-sanitize-vr5400
2843 // end-sanitize-vr5400
2844 // start-sanitize-r5900
2846 // end-sanitize-r5900
2847 // start-sanitize-tx19
2849 // end-sanitize-tx19
2854 unsigned64 mask = 7;
2855 unsigned int reverse = (ReverseEndian ? mask : 0);
2856 unsigned int bigend = (BigEndianCPU ? mask : 0);
2858 address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
2859 AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
2860 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2863 byte = ((vaddr & mask) ^ bigend);
2864 memval = (GPR[RT] << (byte * 8));
2865 StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,0,paddr,vaddr,isREAL);
2869 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2870 "sh r<RT>, <OFFSET>(r<BASE>)"
2871 *mipsI,mipsII,mipsIII,mipsIV:
2873 // start-sanitize-vr4320
2875 // end-sanitize-vr4320
2876 // start-sanitize-vr5400
2878 // end-sanitize-vr5400
2879 // start-sanitize-r5900
2881 // end-sanitize-r5900
2883 // start-sanitize-tx19
2885 // end-sanitize-tx19
2887 unsigned32 instruction = instruction_0;
2888 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2889 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2890 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2892 address_word vaddr = ((unsigned64)op1 + offset);
2895 if ((vaddr & 1) != 0)
2896 SignalExceptionAddressStore();
2899 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2901 unsigned64 memval = 0;
2902 unsigned64 memval1 = 0;
2903 unsigned64 mask = 0x7;
2904 unsigned int shift = 1;
2905 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2906 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2908 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2909 byte = ((vaddr & mask) ^ (bigend << shift));
2910 memval = ((unsigned64) op2 << (8 * byte));
2912 StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2920 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2921 "sll r<RD>, r<RT>, <SHIFT>"
2922 *mipsI,mipsII,mipsIII,mipsIV:
2924 // start-sanitize-vr4320
2926 // end-sanitize-vr4320
2927 // start-sanitize-vr5400
2929 // end-sanitize-vr5400
2930 // start-sanitize-r5900
2932 // end-sanitize-r5900
2934 // start-sanitize-tx19
2936 // end-sanitize-tx19
2939 unsigned32 temp = (GPR[RT] << s);
2940 GPR[RD] = EXTEND32 (temp);
2944 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2945 "sllv r<RD>, r<RT>, r<RS>"
2946 *mipsI,mipsII,mipsIII,mipsIV:
2948 // start-sanitize-vr4320
2950 // end-sanitize-vr4320
2951 // start-sanitize-vr5400
2953 // end-sanitize-vr5400
2954 // start-sanitize-r5900
2956 // end-sanitize-r5900
2958 // start-sanitize-tx19
2960 // end-sanitize-tx19
2962 int s = MASKED (GPR[RS], 4, 0);
2963 unsigned32 temp = (GPR[RT] << s);
2964 GPR[RD] = EXTEND32 (temp);
2968 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2969 "slt r<RD>, r<RS>, r<RT>"
2970 *mipsI,mipsII,mipsIII,mipsIV:
2972 // start-sanitize-vr4320
2974 // end-sanitize-vr4320
2975 // start-sanitize-vr5400
2977 // end-sanitize-vr5400
2978 // start-sanitize-r5900
2980 // end-sanitize-r5900
2982 // start-sanitize-tx19
2984 // end-sanitize-tx19
2986 GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
2990 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2991 "slti r<RT>, r<RS>, <IMMEDIATE>"
2992 *mipsI,mipsII,mipsIII,mipsIV:
2994 // start-sanitize-vr4320
2996 // end-sanitize-vr4320
2997 // start-sanitize-vr5400
2999 // end-sanitize-vr5400
3000 // start-sanitize-r5900
3002 // end-sanitize-r5900
3004 // start-sanitize-tx19
3006 // end-sanitize-tx19
3008 GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
3012 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3013 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3014 *mipsI,mipsII,mipsIII,mipsIV:
3016 // start-sanitize-vr4320
3018 // end-sanitize-vr4320
3019 // start-sanitize-vr5400
3021 // end-sanitize-vr5400
3022 // start-sanitize-r5900
3024 // end-sanitize-r5900
3026 // start-sanitize-tx19
3028 // end-sanitize-tx19
3030 GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
3033 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3034 "sltu r<RD>, r<RS>, r<RT>"
3035 *mipsI,mipsII,mipsIII,mipsIV:
3037 // start-sanitize-vr4320
3039 // end-sanitize-vr4320
3040 // start-sanitize-vr5400
3042 // end-sanitize-vr5400
3043 // start-sanitize-r5900
3045 // end-sanitize-r5900
3047 // start-sanitize-tx19
3049 // end-sanitize-tx19
3051 GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
3055 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3056 "sra r<RD>, r<RT>, <SHIFT>"
3057 *mipsI,mipsII,mipsIII,mipsIV:
3059 // start-sanitize-vr4320
3061 // end-sanitize-vr4320
3062 // start-sanitize-vr5400
3064 // end-sanitize-vr5400
3065 // start-sanitize-r5900
3067 // end-sanitize-r5900
3069 // start-sanitize-tx19
3071 // end-sanitize-tx19
3074 signed32 temp = (signed32) GPR[RT] >> s;
3075 GPR[RD] = EXTEND32 (temp);
3079 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3080 "srav r<RD>, r<RT>, r<RS>"
3081 *mipsI,mipsII,mipsIII,mipsIV:
3083 // start-sanitize-vr4320
3085 // end-sanitize-vr4320
3086 // start-sanitize-vr5400
3088 // end-sanitize-vr5400
3089 // start-sanitize-r5900
3091 // end-sanitize-r5900
3093 // start-sanitize-tx19
3095 // end-sanitize-tx19
3097 int s = MASKED (GPR[RS], 4, 0);
3098 signed32 temp = (signed32) GPR[RT] >> s;
3099 GPR[RD] = EXTEND32 (temp);
3103 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3104 "srl r<RD>, r<RT>, <SHIFT>"
3105 *mipsI,mipsII,mipsIII,mipsIV:
3107 // start-sanitize-vr4320
3109 // end-sanitize-vr4320
3110 // start-sanitize-vr5400
3112 // end-sanitize-vr5400
3113 // start-sanitize-r5900
3115 // end-sanitize-r5900
3117 // start-sanitize-tx19
3119 // end-sanitize-tx19
3122 unsigned32 temp = (unsigned32) GPR[RT] >> s;
3123 GPR[RD] = EXTEND32 (temp);
3127 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3128 "srlv r<RD>, r<RT>, r<RS>"
3129 *mipsI,mipsII,mipsIII,mipsIV:
3131 // start-sanitize-vr4320
3133 // end-sanitize-vr4320
3134 // start-sanitize-vr5400
3136 // end-sanitize-vr5400
3137 // start-sanitize-r5900
3139 // end-sanitize-r5900
3141 // start-sanitize-tx19
3143 // end-sanitize-tx19
3145 int s = MASKED (GPR[RS], 4, 0);
3146 unsigned32 temp = (unsigned32) GPR[RT] >> s;
3147 GPR[RD] = EXTEND32 (temp);
3151 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3152 "sub r<RD>, r<RS>, r<RT>"
3153 *mipsI,mipsII,mipsIII,mipsIV:
3155 // start-sanitize-vr4320
3157 // end-sanitize-vr4320
3158 // start-sanitize-vr5400
3160 // end-sanitize-vr5400
3161 // start-sanitize-r5900
3163 // end-sanitize-r5900
3165 // start-sanitize-tx19
3167 // end-sanitize-tx19
3169 ALU32_BEGIN (GPR[RS]);
3170 ALU32_SUB (GPR[RT]);
3171 ALU32_END (GPR[RD]);
3175 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3176 "subu r<RD>, r<RS>, r<RT>"
3177 *mipsI,mipsII,mipsIII,mipsIV:
3179 // start-sanitize-vr4320
3181 // end-sanitize-vr4320
3182 // start-sanitize-vr5400
3184 // end-sanitize-vr5400
3185 // start-sanitize-r5900
3187 // end-sanitize-r5900
3189 // start-sanitize-tx19
3191 // end-sanitize-tx19
3193 GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
3197 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3198 "sw r<RT>, <OFFSET>(r<BASE>)"
3199 *mipsI,mipsII,mipsIII,mipsIV:
3201 // start-sanitize-vr4320
3203 // end-sanitize-vr4320
3204 // start-sanitize-vr5400
3206 // end-sanitize-vr5400
3207 // start-sanitize-r5900
3209 // end-sanitize-r5900
3211 // start-sanitize-tx19
3213 // end-sanitize-tx19
3215 unsigned32 instruction = instruction_0;
3216 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3217 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3218 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3220 address_word vaddr = ((unsigned64)op1 + offset);
3223 if ((vaddr & 3) != 0)
3224 SignalExceptionAddressStore();
3227 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3229 unsigned64 memval = 0;
3230 unsigned64 memval1 = 0;
3231 unsigned64 mask = 0x7;
3233 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3234 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3235 memval = ((unsigned64) op2 << (8 * byte));
3237 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3245 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3246 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3247 *mipsI,mipsII,mipsIII,mipsIV:
3249 // start-sanitize-vr4320
3251 // end-sanitize-vr4320
3252 // start-sanitize-vr5400
3254 // end-sanitize-vr5400
3256 // start-sanitize-tx19
3258 // end-sanitize-tx19
3260 unsigned32 instruction = instruction_0;
3261 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3262 int destreg = ((instruction >> 16) & 0x0000001F);
3263 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3265 address_word vaddr = ((unsigned64)op1 + offset);
3268 if ((vaddr & 3) != 0)
3269 SignalExceptionAddressStore();
3272 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3274 unsigned64 memval = 0;
3275 unsigned64 memval1 = 0;
3276 unsigned64 mask = 0x7;
3278 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3279 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3280 memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
3282 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3290 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3291 "swl r<RT>, <OFFSET>(r<BASE>)"
3292 *mipsI,mipsII,mipsIII,mipsIV:
3294 // start-sanitize-vr4320
3296 // end-sanitize-vr4320
3297 // start-sanitize-vr5400
3299 // end-sanitize-vr5400
3300 // start-sanitize-r5900
3302 // end-sanitize-r5900
3304 // start-sanitize-tx19
3306 // end-sanitize-tx19
3308 unsigned32 instruction = instruction_0;
3309 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3310 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3311 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3313 address_word vaddr = ((unsigned64)op1 + offset);
3317 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3319 unsigned64 memval = 0;
3320 unsigned64 memval1 = 0;
3321 unsigned64 mask = 3;
3322 unsigned int reverse = (ReverseEndian ? mask : 0);
3323 unsigned int bigend = (BigEndianCPU ? mask : 0);
3325 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3326 byte = ((vaddr & mask) ^ bigend);
3329 memval = (op2 >> (8 * (3 - byte)));
3330 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3333 StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
3340 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3341 "swr r<RT>, <OFFSET>(r<BASE>)"
3342 *mipsI,mipsII,mipsIII,mipsIV:
3344 // start-sanitize-vr4320
3346 // end-sanitize-vr4320
3347 // start-sanitize-vr5400
3349 // end-sanitize-vr5400
3350 // start-sanitize-r5900
3352 // end-sanitize-r5900
3354 // start-sanitize-tx19
3356 // end-sanitize-tx19
3358 unsigned64 memval = 0;
3359 unsigned64 mask = 3;
3360 unsigned int reverse = (ReverseEndian ? mask : 0);
3361 unsigned int bigend = (BigEndianCPU ? mask : 0);
3365 address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
3366 AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
3367 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3370 byte = ((vaddr & mask) ^ bigend);
3371 memval = (GPR[RT] << (byte * 8));
3372 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2))
3374 StoreMemory(uncached,(AccessLength_WORD - byte),memval,0,paddr,vaddr,isREAL);
3378 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3385 // start-sanitize-vr4320
3387 // end-sanitize-vr4320
3388 // start-sanitize-vr5400
3390 // end-sanitize-vr5400
3391 // start-sanitize-r5900
3393 // end-sanitize-r5900
3395 // start-sanitize-tx19
3397 // end-sanitize-tx19
3399 SyncOperation (STYPE);
3403 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3405 *mipsI,mipsII,mipsIII,mipsIV:
3407 // start-sanitize-vr4320
3409 // end-sanitize-vr4320
3410 // start-sanitize-vr5400
3412 // end-sanitize-vr5400
3413 // start-sanitize-r5900
3415 // end-sanitize-r5900
3417 // start-sanitize-tx19
3419 // end-sanitize-tx19
3421 SignalException(SystemCall, instruction_0);
3425 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3431 // start-sanitize-vr4320
3433 // end-sanitize-vr4320
3434 // start-sanitize-vr5400
3436 // end-sanitize-vr5400
3437 // start-sanitize-r5900
3439 // end-sanitize-r5900
3440 // start-sanitize-tx19
3442 // end-sanitize-tx19
3444 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3445 SignalException(Trap, instruction_0);
3449 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3450 "teqi r<RS>, <IMMEDIATE>"
3455 // start-sanitize-vr4320
3457 // end-sanitize-vr4320
3458 // start-sanitize-vr5400
3460 // end-sanitize-vr5400
3461 // start-sanitize-r5900
3463 // end-sanitize-r5900
3464 // start-sanitize-tx19
3466 // end-sanitize-tx19
3468 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3469 SignalException(Trap, instruction_0);
3473 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3479 // start-sanitize-vr4320
3481 // end-sanitize-vr4320
3482 // start-sanitize-vr5400
3484 // end-sanitize-vr5400
3485 // start-sanitize-r5900
3487 // end-sanitize-r5900
3488 // start-sanitize-tx19
3490 // end-sanitize-tx19
3492 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3493 SignalException(Trap, instruction_0);
3497 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3498 "tgei r<RS>, <IMMEDIATE>"
3503 // start-sanitize-vr4320
3505 // end-sanitize-vr4320
3506 // start-sanitize-vr5400
3508 // end-sanitize-vr5400
3509 // start-sanitize-r5900
3511 // end-sanitize-r5900
3512 // start-sanitize-tx19
3514 // end-sanitize-tx19
3516 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3517 SignalException(Trap, instruction_0);
3521 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3522 "tgeiu r<RS>, <IMMEDIATE>"
3527 // start-sanitize-vr4320
3529 // end-sanitize-vr4320
3530 // start-sanitize-vr5400
3532 // end-sanitize-vr5400
3533 // start-sanitize-r5900
3535 // end-sanitize-r5900
3536 // start-sanitize-tx19
3538 // end-sanitize-tx19
3540 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3541 SignalException(Trap, instruction_0);
3545 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3551 // start-sanitize-vr4320
3553 // end-sanitize-vr4320
3554 // start-sanitize-vr5400
3556 // end-sanitize-vr5400
3557 // start-sanitize-r5900
3559 // end-sanitize-r5900
3560 // start-sanitize-tx19
3562 // end-sanitize-tx19
3564 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3565 SignalException(Trap, instruction_0);
3569 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3575 // start-sanitize-vr4320
3577 // end-sanitize-vr4320
3578 // start-sanitize-vr5400
3580 // end-sanitize-vr5400
3581 // start-sanitize-r5900
3583 // end-sanitize-r5900
3584 // start-sanitize-tx19
3586 // end-sanitize-tx19
3588 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3589 SignalException(Trap, instruction_0);
3593 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3594 "tlti r<RS>, <IMMEDIATE>"
3599 // start-sanitize-vr4320
3601 // end-sanitize-vr4320
3602 // start-sanitize-vr5400
3604 // end-sanitize-vr5400
3605 // start-sanitize-r5900
3607 // end-sanitize-r5900
3608 // start-sanitize-tx19
3610 // end-sanitize-tx19
3612 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3613 SignalException(Trap, instruction_0);
3617 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3618 "tltiu r<RS>, <IMMEDIATE>"
3623 // start-sanitize-vr4320
3625 // end-sanitize-vr4320
3626 // start-sanitize-vr5400
3628 // end-sanitize-vr5400
3629 // start-sanitize-r5900
3631 // end-sanitize-r5900
3632 // start-sanitize-tx19
3634 // end-sanitize-tx19
3636 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3637 SignalException(Trap, instruction_0);
3641 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3647 // start-sanitize-vr4320
3649 // end-sanitize-vr4320
3650 // start-sanitize-vr5400
3652 // end-sanitize-vr5400
3653 // start-sanitize-r5900
3655 // end-sanitize-r5900
3656 // start-sanitize-tx19
3658 // end-sanitize-tx19
3660 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3661 SignalException(Trap, instruction_0);
3665 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3671 // start-sanitize-vr4320
3673 // end-sanitize-vr4320
3674 // start-sanitize-vr5400
3676 // end-sanitize-vr5400
3677 // start-sanitize-r5900
3679 // end-sanitize-r5900
3680 // start-sanitize-tx19
3682 // end-sanitize-tx19
3684 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3685 SignalException(Trap, instruction_0);
3689 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3690 "tne r<RS>, <IMMEDIATE>"
3695 // start-sanitize-vr4320
3697 // end-sanitize-vr4320
3698 // start-sanitize-vr5400
3700 // end-sanitize-vr5400
3701 // start-sanitize-r5900
3703 // end-sanitize-r5900
3704 // start-sanitize-tx19
3706 // end-sanitize-tx19
3708 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3709 SignalException(Trap, instruction_0);
3713 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3714 "xor r<RD>, r<RS>, r<RT>"
3715 *mipsI,mipsII,mipsIII,mipsIV:
3717 // start-sanitize-vr4320
3719 // end-sanitize-vr4320
3720 // start-sanitize-vr5400
3722 // end-sanitize-vr5400
3723 // start-sanitize-r5900
3725 // end-sanitize-r5900
3727 // start-sanitize-tx19
3729 // end-sanitize-tx19
3731 GPR[RD] = GPR[RS] ^ GPR[RT];
3735 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3736 "xori r<RT>, r<RS>, <IMMEDIATE>"
3737 *mipsI,mipsII,mipsIII,mipsIV:
3739 // start-sanitize-vr4320
3741 // end-sanitize-vr4320
3742 // start-sanitize-vr5400
3744 // end-sanitize-vr5400
3745 // start-sanitize-r5900
3747 // end-sanitize-r5900
3749 // start-sanitize-tx19
3751 // end-sanitize-tx19
3753 GPR[RT] = GPR[RS] ^ IMMEDIATE;
3758 // MIPS Architecture:
3760 // FPU Instruction Set (COP1 & COP1X)
3768 case fmt_single: return "s";
3769 case fmt_double: return "d";
3770 case fmt_word: return "w";
3771 case fmt_long: return "l";
3772 default: return "?";
3782 default: return "?";
3802 :%s::::COND:int cond
3806 case 00: return "f";
3807 case 01: return "un";
3808 case 02: return "eq";
3809 case 03: return "ueq";
3810 case 04: return "olt";
3811 case 05: return "ult";
3812 case 06: return "ole";
3813 case 07: return "ule";
3814 case 010: return "sf";
3815 case 011: return "ngle";
3816 case 012: return "seq";
3817 case 013: return "ngl";
3818 case 014: return "lt";
3819 case 015: return "nge";
3820 case 016: return "le";
3821 case 017: return "ngt";
3822 default: return "?";
3827 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3828 "abs.%s<FMT> f<FD>, f<FS>"
3829 *mipsI,mipsII,mipsIII,mipsIV:
3831 // start-sanitize-vr4320
3833 // end-sanitize-vr4320
3834 // start-sanitize-vr5400
3836 // end-sanitize-vr5400
3838 // start-sanitize-tx19
3840 // end-sanitize-tx19
3842 unsigned32 instruction = instruction_0;
3843 int destreg = ((instruction >> 6) & 0x0000001F);
3844 int fs = ((instruction >> 11) & 0x0000001F);
3845 int format = ((instruction >> 21) & 0x00000007);
3847 if ((format != fmt_single) && (format != fmt_double))
3848 SignalException(ReservedInstruction,instruction);
3850 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3856 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3857 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3858 *mipsI,mipsII,mipsIII,mipsIV:
3860 // start-sanitize-vr4320
3862 // end-sanitize-vr4320
3863 // start-sanitize-vr5400
3865 // end-sanitize-vr5400
3867 // start-sanitize-tx19
3869 // end-sanitize-tx19
3871 unsigned32 instruction = instruction_0;
3872 int destreg = ((instruction >> 6) & 0x0000001F);
3873 int fs = ((instruction >> 11) & 0x0000001F);
3874 int ft = ((instruction >> 16) & 0x0000001F);
3875 int format = ((instruction >> 21) & 0x00000007);
3877 if ((format != fmt_single) && (format != fmt_double))
3878 SignalException(ReservedInstruction, instruction);
3880 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3891 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3892 "bc1%s<TF>%s<ND> <OFFSET>"
3893 *mipsI,mipsII,mipsIII:
3894 // start-sanitize-r5900
3896 // end-sanitize-r5900
3898 TRACE_BRANCH_INPUT (PREVCOC1());
3899 if (PREVCOC1() == TF)
3901 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3902 TRACE_BRANCH_RESULT (dest);
3907 TRACE_BRANCH_RESULT (0);
3908 NULLIFY_NEXT_INSTRUCTION ();
3912 TRACE_BRANCH_RESULT (NIA);
3916 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3917 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3918 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3921 // start-sanitize-vr4320
3923 // end-sanitize-vr4320
3924 // start-sanitize-vr5400
3926 // end-sanitize-vr5400
3928 // start-sanitize-tx19
3930 // end-sanitize-tx19
3932 if (GETFCC(CC) == TF)
3934 DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3938 NULLIFY_NEXT_INSTRUCTION ();
3948 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3950 if ((fmt != fmt_single) && (fmt != fmt_double))
3951 SignalException (ReservedInstruction, insn);
3958 unsigned64 ofs = ValueFPR (fs, fmt);
3959 unsigned64 oft = ValueFPR (ft, fmt);
3960 if (NaN (ofs, fmt) || NaN (oft, fmt))
3962 if (FCSR & FP_ENABLE (IO))
3964 FCSR |= FP_CAUSE (IO);
3965 SignalExceptionFPE ();
3973 less = Less (ofs, oft, fmt);
3974 equal = Equal (ofs, oft, fmt);
3977 condition = (((cond & (1 << 2)) && less)
3978 || ((cond & (1 << 1)) && equal)
3979 || ((cond & (1 << 0)) && unordered));
3980 SETFCC (cc, condition);
3984 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3985 *mipsI,mipsII,mipsIII:
3986 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3988 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3991 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3992 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3993 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3996 // start-sanitize-vr4320
3998 // end-sanitize-vr4320
3999 // start-sanitize-vr5400
4001 // end-sanitize-vr5400
4003 // start-sanitize-tx19
4005 // end-sanitize-tx19
4007 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4011 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4012 "ceil.l.%s<FMT> f<FD>, f<FS>"
4016 // start-sanitize-vr4320
4018 // end-sanitize-vr4320
4019 // start-sanitize-vr5400
4021 // end-sanitize-vr5400
4022 // start-sanitize-r5900
4024 // end-sanitize-r5900
4026 // start-sanitize-tx19
4028 // end-sanitize-tx19
4030 unsigned32 instruction = instruction_0;
4031 int destreg = ((instruction >> 6) & 0x0000001F);
4032 int fs = ((instruction >> 11) & 0x0000001F);
4033 int format = ((instruction >> 21) & 0x00000007);
4035 if ((format != fmt_single) && (format != fmt_double))
4036 SignalException(ReservedInstruction,instruction);
4038 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4043 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4048 // start-sanitize-vr4320
4050 // end-sanitize-vr4320
4051 // start-sanitize-vr5400
4053 // end-sanitize-vr5400
4054 // start-sanitize-r5900
4056 // end-sanitize-r5900
4058 // start-sanitize-tx19
4060 // end-sanitize-tx19
4062 unsigned32 instruction = instruction_0;
4063 int destreg = ((instruction >> 6) & 0x0000001F);
4064 int fs = ((instruction >> 11) & 0x0000001F);
4065 int format = ((instruction >> 21) & 0x00000007);
4067 if ((format != fmt_single) && (format != fmt_double))
4068 SignalException(ReservedInstruction,instruction);
4070 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4077 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4078 "c%s<X>c1 r<RT>, f<FS>"
4086 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4088 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4090 PENDING_FILL(COCIDX,0); /* special case */
4093 { /* control from */
4095 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4097 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4101 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4102 "c%s<X>c1 r<RT>, f<FS>"
4105 // start-sanitize-vr4320
4107 // end-sanitize-vr4320
4108 // start-sanitize-vr5400
4110 // end-sanitize-vr5400
4111 // start-sanitize-r5900
4113 // end-sanitize-r5900
4115 // start-sanitize-tx19
4117 // end-sanitize-tx19
4122 TRACE_ALU_INPUT1 (GPR[RT]);
4125 FCR0 = VL4_8(GPR[RT]);
4126 TRACE_ALU_RESULT (FCR0);
4130 FCR31 = VL4_8(GPR[RT]);
4131 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4132 TRACE_ALU_RESULT (FCR31);
4136 TRACE_ALU_RESULT0 ();
4141 { /* control from */
4144 TRACE_ALU_INPUT1 (FCR0);
4145 GPR[RT] = SIGNEXTEND (FCR0, 32);
4149 TRACE_ALU_INPUT1 (FCR31);
4150 GPR[RT] = SIGNEXTEND (FCR31, 32);
4152 TRACE_ALU_RESULT (GPR[RT]);
4159 // FIXME: Does not correctly differentiate between mips*
4161 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4162 "cvt.d.%s<FMT> f<FD>, f<FS>"
4163 *mipsI,mipsII,mipsIII,mipsIV:
4165 // start-sanitize-vr4320
4167 // end-sanitize-vr4320
4168 // start-sanitize-vr5400
4170 // end-sanitize-vr5400
4172 // start-sanitize-tx19
4174 // end-sanitize-tx19
4176 unsigned32 instruction = instruction_0;
4177 int destreg = ((instruction >> 6) & 0x0000001F);
4178 int fs = ((instruction >> 11) & 0x0000001F);
4179 int format = ((instruction >> 21) & 0x00000007);
4181 if ((format == fmt_double) | 0)
4182 SignalException(ReservedInstruction,instruction);
4184 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4189 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4190 "cvt.l.%s<FMT> f<FD>, f<FS>"
4194 // start-sanitize-vr4320
4196 // end-sanitize-vr4320
4197 // start-sanitize-vr5400
4199 // end-sanitize-vr5400
4201 // start-sanitize-tx19
4203 // end-sanitize-tx19
4205 unsigned32 instruction = instruction_0;
4206 int destreg = ((instruction >> 6) & 0x0000001F);
4207 int fs = ((instruction >> 11) & 0x0000001F);
4208 int format = ((instruction >> 21) & 0x00000007);
4210 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4211 SignalException(ReservedInstruction,instruction);
4213 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4219 // FIXME: Does not correctly differentiate between mips*
4221 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4222 "cvt.s.%s<FMT> f<FD>, f<FS>"
4223 *mipsI,mipsII,mipsIII,mipsIV:
4225 // start-sanitize-vr4320
4227 // end-sanitize-vr4320
4228 // start-sanitize-vr5400
4230 // end-sanitize-vr5400
4232 // start-sanitize-tx19
4234 // end-sanitize-tx19
4236 unsigned32 instruction = instruction_0;
4237 int destreg = ((instruction >> 6) & 0x0000001F);
4238 int fs = ((instruction >> 11) & 0x0000001F);
4239 int format = ((instruction >> 21) & 0x00000007);
4241 if ((format == fmt_single) | 0)
4242 SignalException(ReservedInstruction,instruction);
4244 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4249 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4250 "cvt.w.%s<FMT> f<FD>, f<FS>"
4251 *mipsI,mipsII,mipsIII,mipsIV:
4253 // start-sanitize-vr4320
4255 // end-sanitize-vr4320
4256 // start-sanitize-vr5400
4258 // end-sanitize-vr5400
4260 // start-sanitize-tx19
4262 // end-sanitize-tx19
4264 unsigned32 instruction = instruction_0;
4265 int destreg = ((instruction >> 6) & 0x0000001F);
4266 int fs = ((instruction >> 11) & 0x0000001F);
4267 int format = ((instruction >> 21) & 0x00000007);
4269 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4270 SignalException(ReservedInstruction,instruction);
4272 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4277 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4278 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4279 *mipsI,mipsII,mipsIII,mipsIV:
4281 // start-sanitize-vr4320
4283 // end-sanitize-vr4320
4284 // start-sanitize-vr5400
4286 // end-sanitize-vr5400
4288 // start-sanitize-tx19
4290 // end-sanitize-tx19
4292 unsigned32 instruction = instruction_0;
4293 int destreg = ((instruction >> 6) & 0x0000001F);
4294 int fs = ((instruction >> 11) & 0x0000001F);
4295 int ft = ((instruction >> 16) & 0x0000001F);
4296 int format = ((instruction >> 21) & 0x00000007);
4298 if ((format != fmt_single) && (format != fmt_double))
4299 SignalException(ReservedInstruction,instruction);
4301 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4308 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4309 "dm%s<X>c1 r<RT>, f<FS>"
4314 if (SizeFGR() == 64)
4315 PENDING_FILL((FS + FGRIDX),GPR[RT]);
4316 else if ((FS & 0x1) == 0)
4318 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4319 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4324 if (SizeFGR() == 64)
4325 PENDING_FILL(RT,FGR[FS]);
4326 else if ((FS & 0x1) == 0)
4327 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4329 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4332 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4333 "dm%s<X>c1 r<RT>, f<FS>"
4336 // start-sanitize-vr4320
4338 // end-sanitize-vr4320
4339 // start-sanitize-vr5400
4341 // end-sanitize-vr5400
4342 // start-sanitize-r5900
4344 // end-sanitize-r5900
4346 // start-sanitize-tx19
4348 // end-sanitize-tx19
4352 if (SizeFGR() == 64)
4353 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4354 else if ((FS & 0x1) == 0)
4355 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4359 if (SizeFGR() == 64)
4361 else if ((FS & 0x1) == 0)
4362 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4364 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4369 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4370 "floor.l.%s<FMT> f<FD>, f<FS>"
4374 // start-sanitize-vr4320
4376 // end-sanitize-vr4320
4377 // start-sanitize-vr5400
4379 // end-sanitize-vr5400
4380 // start-sanitize-r5900
4382 // end-sanitize-r5900
4384 // start-sanitize-tx19
4386 // end-sanitize-tx19
4388 unsigned32 instruction = instruction_0;
4389 int destreg = ((instruction >> 6) & 0x0000001F);
4390 int fs = ((instruction >> 11) & 0x0000001F);
4391 int format = ((instruction >> 21) & 0x00000007);
4393 if ((format != fmt_single) && (format != fmt_double))
4394 SignalException(ReservedInstruction,instruction);
4396 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4401 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4402 "floor.w.%s<FMT> f<FD>, f<FS>"
4407 // start-sanitize-vr4320
4409 // end-sanitize-vr4320
4410 // start-sanitize-vr5400
4412 // end-sanitize-vr5400
4413 // start-sanitize-r5900
4415 // end-sanitize-r5900
4417 // start-sanitize-tx19
4419 // end-sanitize-tx19
4421 unsigned32 instruction = instruction_0;
4422 int destreg = ((instruction >> 6) & 0x0000001F);
4423 int fs = ((instruction >> 11) & 0x0000001F);
4424 int format = ((instruction >> 21) & 0x00000007);
4426 if ((format != fmt_single) && (format != fmt_double))
4427 SignalException(ReservedInstruction,instruction);
4429 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4434 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4435 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4440 // start-sanitize-vr4320
4442 // end-sanitize-vr4320
4443 // start-sanitize-vr5400
4445 // end-sanitize-vr5400
4447 // start-sanitize-tx19
4449 // end-sanitize-tx19
4451 address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
4454 if ((vaddr & 7) != 0)
4455 SignalExceptionAddressLoad();
4459 AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
4460 LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4461 COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
4466 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4467 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4470 // start-sanitize-vr4320
4472 // end-sanitize-vr4320
4473 // start-sanitize-vr5400
4475 // end-sanitize-vr5400
4477 unsigned32 instruction = instruction_0;
4478 int destreg = ((instruction >> 6) & 0x0000001F);
4479 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4480 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4482 address_word vaddr = ((unsigned64)op1 + op2);
4485 if ((vaddr & 7) != 0)
4486 SignalExceptionAddressLoad();
4489 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4491 unsigned64 memval = 0;
4492 unsigned64 memval1 = 0;
4493 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4494 COP_LD(1,destreg,memval);;
4502 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4503 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4504 *mipsI,mipsII,mipsIII,mipsIV:
4506 // start-sanitize-vr4320
4508 // end-sanitize-vr4320
4509 // start-sanitize-vr5400
4511 // end-sanitize-vr5400
4512 // start-sanitize-r5900
4514 // end-sanitize-r5900
4516 // start-sanitize-tx19
4518 // end-sanitize-tx19
4520 unsigned32 instruction = instruction_0;
4521 signed_word offset = EXTEND16 (OFFSET);
4522 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4523 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4525 address_word vaddr = ((uword64)op1 + offset);
4528 if ((vaddr & 3) != 0)
4529 SignalExceptionAddressLoad();
4532 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4535 uword64 memval1 = 0;
4537 unsigned int shift = 2;
4538 unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
4539 unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
4540 unsigned int byte UNUSED;
4541 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4542 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4543 byte = ((vaddr & mask) ^ (bigend << shift));
4544 COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4551 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4552 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4555 // start-sanitize-vr4320
4557 // end-sanitize-vr4320
4558 // start-sanitize-vr5400
4560 // end-sanitize-vr5400
4562 unsigned32 instruction = instruction_0;
4563 int destreg = ((instruction >> 6) & 0x0000001F);
4564 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4565 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4567 address_word vaddr = ((unsigned64)op1 + op2);
4570 if ((vaddr & 3) != 0)
4571 SignalExceptionAddressLoad();
4574 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4576 unsigned64 memval = 0;
4577 unsigned64 memval1 = 0;
4578 unsigned64 mask = 0x7;
4579 unsigned int shift = 2;
4580 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4581 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4583 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4584 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4585 byte = ((vaddr & mask) ^ (bigend << shift));
4586 COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4595 // FIXME: Not correct for mips*
4597 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4598 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4601 // start-sanitize-vr4320
4603 // end-sanitize-vr4320
4604 // start-sanitize-vr5400
4606 // end-sanitize-vr5400
4608 unsigned32 instruction = instruction_0;
4609 int destreg = ((instruction >> 6) & 0x0000001F);
4610 int fs = ((instruction >> 11) & 0x0000001F);
4611 int ft = ((instruction >> 16) & 0x0000001F);
4612 int fr = ((instruction >> 21) & 0x0000001F);
4614 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4619 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4620 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4623 // start-sanitize-vr4320
4625 // end-sanitize-vr4320
4626 // start-sanitize-vr5400
4628 // end-sanitize-vr5400
4630 unsigned32 instruction = instruction_0;
4631 int destreg = ((instruction >> 6) & 0x0000001F);
4632 int fs = ((instruction >> 11) & 0x0000001F);
4633 int ft = ((instruction >> 16) & 0x0000001F);
4634 int fr = ((instruction >> 21) & 0x0000001F);
4636 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4643 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4644 "m%s<X>c1 r<RT>, f<FS>"
4651 if (SizeFGR() == 64)
4652 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4654 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4657 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4659 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4660 "m%s<X>c1 r<RT>, f<FS>"
4663 // start-sanitize-vr4320
4665 // end-sanitize-vr4320
4666 // start-sanitize-vr5400
4668 // end-sanitize-vr5400
4670 // start-sanitize-tx19
4672 // end-sanitize-tx19
4676 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4678 GPR[RT] = SIGNEXTEND(FGR[FS],32);
4682 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4683 "mov.%s<FMT> f<FD>, f<FS>"
4684 *mipsI,mipsII,mipsIII,mipsIV:
4686 // start-sanitize-vr4320
4688 // end-sanitize-vr4320
4689 // start-sanitize-vr5400
4691 // end-sanitize-vr5400
4693 // start-sanitize-tx19
4695 // end-sanitize-tx19
4697 unsigned32 instruction = instruction_0;
4698 int destreg = ((instruction >> 6) & 0x0000001F);
4699 int fs = ((instruction >> 11) & 0x0000001F);
4700 int format = ((instruction >> 21) & 0x00000007);
4702 StoreFPR(destreg,format,ValueFPR(fs,format));
4708 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4709 "mov%s<TF> r<RD>, r<RS>, <CC>"
4712 // start-sanitize-vr4320
4714 // end-sanitize-vr4320
4715 // start-sanitize-vr5400
4717 // end-sanitize-vr5400
4718 // start-sanitize-r5900
4720 // end-sanitize-r5900
4722 if (GETFCC(CC) == TF)
4728 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4729 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4732 // start-sanitize-vr4320
4734 // end-sanitize-vr4320
4735 // start-sanitize-vr5400
4737 // end-sanitize-vr5400
4738 // start-sanitize-r5900
4740 // end-sanitize-r5900
4742 unsigned32 instruction = instruction_0;
4743 int format = ((instruction >> 21) & 0x00000007);
4745 if (GETFCC(CC) == TF)
4746 StoreFPR (FD, format, ValueFPR (FS, format));
4748 StoreFPR (FD, format, ValueFPR (FD, format));
4753 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4756 // start-sanitize-vr4320
4758 // end-sanitize-vr4320
4759 // start-sanitize-vr5400
4761 // end-sanitize-vr5400
4762 // start-sanitize-r5900
4764 // end-sanitize-r5900
4766 unsigned32 instruction = instruction_0;
4767 int destreg = ((instruction >> 6) & 0x0000001F);
4768 int fs = ((instruction >> 11) & 0x0000001F);
4769 int format = ((instruction >> 21) & 0x00000007);
4771 StoreFPR(destreg,format,ValueFPR(fs,format));
4779 // MOVT.fmt see MOVtf.fmt
4783 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4784 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4787 // start-sanitize-vr4320
4789 // end-sanitize-vr4320
4790 // start-sanitize-vr5400
4792 // end-sanitize-vr5400
4793 // start-sanitize-r5900
4795 // end-sanitize-r5900
4797 unsigned32 instruction = instruction_0;
4798 int destreg = ((instruction >> 6) & 0x0000001F);
4799 int fs = ((instruction >> 11) & 0x0000001F);
4800 int format = ((instruction >> 21) & 0x00000007);
4802 StoreFPR(destreg,format,ValueFPR(fs,format));
4808 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4809 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4812 // start-sanitize-vr4320
4814 // end-sanitize-vr4320
4815 // start-sanitize-vr5400
4817 // end-sanitize-vr5400
4818 // start-sanitize-r5900
4820 // end-sanitize-r5900
4822 unsigned32 instruction = instruction_0;
4823 int destreg = ((instruction >> 6) & 0x0000001F);
4824 int fs = ((instruction >> 11) & 0x0000001F);
4825 int ft = ((instruction >> 16) & 0x0000001F);
4826 int fr = ((instruction >> 21) & 0x0000001F);
4828 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4834 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4835 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4838 // start-sanitize-vr4320
4840 // end-sanitize-vr4320
4841 // start-sanitize-vr5400
4843 // end-sanitize-vr5400
4844 // start-sanitize-r5900
4846 // end-sanitize-r5900
4848 unsigned32 instruction = instruction_0;
4849 int destreg = ((instruction >> 6) & 0x0000001F);
4850 int fs = ((instruction >> 11) & 0x0000001F);
4851 int ft = ((instruction >> 16) & 0x0000001F);
4852 int fr = ((instruction >> 21) & 0x0000001F);
4854 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4862 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4863 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4864 *mipsI,mipsII,mipsIII,mipsIV:
4866 // start-sanitize-vr4320
4868 // end-sanitize-vr4320
4869 // start-sanitize-vr5400
4871 // end-sanitize-vr5400
4873 // start-sanitize-tx19
4875 // end-sanitize-tx19
4877 unsigned32 instruction = instruction_0;
4878 int destreg = ((instruction >> 6) & 0x0000001F);
4879 int fs = ((instruction >> 11) & 0x0000001F);
4880 int ft = ((instruction >> 16) & 0x0000001F);
4881 int format = ((instruction >> 21) & 0x00000007);
4883 if ((format != fmt_single) && (format != fmt_double))
4884 SignalException(ReservedInstruction,instruction);
4886 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4891 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4892 "neg.%s<FMT> f<FD>, f<FS>"
4893 *mipsI,mipsII,mipsIII,mipsIV:
4895 // start-sanitize-vr4320
4897 // end-sanitize-vr4320
4898 // start-sanitize-vr5400
4900 // end-sanitize-vr5400
4902 // start-sanitize-tx19
4904 // end-sanitize-tx19
4906 unsigned32 instruction = instruction_0;
4907 int destreg = ((instruction >> 6) & 0x0000001F);
4908 int fs = ((instruction >> 11) & 0x0000001F);
4909 int format = ((instruction >> 21) & 0x00000007);
4911 if ((format != fmt_single) && (format != fmt_double))
4912 SignalException(ReservedInstruction,instruction);
4914 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4920 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4921 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4924 // start-sanitize-vr4320
4926 // end-sanitize-vr4320
4927 // start-sanitize-vr5400
4929 // end-sanitize-vr5400
4931 unsigned32 instruction = instruction_0;
4932 int destreg = ((instruction >> 6) & 0x0000001F);
4933 int fs = ((instruction >> 11) & 0x0000001F);
4934 int ft = ((instruction >> 16) & 0x0000001F);
4935 int fr = ((instruction >> 21) & 0x0000001F);
4937 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4943 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4944 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4947 // start-sanitize-vr4320
4949 // end-sanitize-vr4320
4950 // start-sanitize-vr5400
4952 // end-sanitize-vr5400
4954 unsigned32 instruction = instruction_0;
4955 int destreg = ((instruction >> 6) & 0x0000001F);
4956 int fs = ((instruction >> 11) & 0x0000001F);
4957 int ft = ((instruction >> 16) & 0x0000001F);
4958 int fr = ((instruction >> 21) & 0x0000001F);
4960 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4966 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4967 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4970 // start-sanitize-vr4320
4972 // end-sanitize-vr4320
4973 // start-sanitize-vr5400
4975 // end-sanitize-vr5400
4977 unsigned32 instruction = instruction_0;
4978 int destreg = ((instruction >> 6) & 0x0000001F);
4979 int fs = ((instruction >> 11) & 0x0000001F);
4980 int ft = ((instruction >> 16) & 0x0000001F);
4981 int fr = ((instruction >> 21) & 0x0000001F);
4983 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4989 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4990 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4993 // start-sanitize-vr4320
4995 // end-sanitize-vr4320
4996 // start-sanitize-vr5400
4998 // end-sanitize-vr5400
5000 unsigned32 instruction = instruction_0;
5001 int destreg = ((instruction >> 6) & 0x0000001F);
5002 int fs = ((instruction >> 11) & 0x0000001F);
5003 int ft = ((instruction >> 16) & 0x0000001F);
5004 int fr = ((instruction >> 21) & 0x0000001F);
5006 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5011 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5012 "prefx <HINT>, r<INDEX>(r<BASE>)"
5015 // start-sanitize-vr4320
5017 // end-sanitize-vr4320
5018 // start-sanitize-vr5400
5020 // end-sanitize-vr5400
5022 unsigned32 instruction = instruction_0;
5023 int fs = ((instruction >> 11) & 0x0000001F);
5024 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5025 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5027 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5030 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5031 Prefetch(uncached,paddr,vaddr,isDATA,fs);
5035 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5037 "recip.%s<FMT> f<FD>, f<FS>"
5039 // start-sanitize-vr4320
5041 // end-sanitize-vr4320
5042 // start-sanitize-vr5400
5044 // end-sanitize-vr5400
5046 unsigned32 instruction = instruction_0;
5047 int destreg = ((instruction >> 6) & 0x0000001F);
5048 int fs = ((instruction >> 11) & 0x0000001F);
5049 int format = ((instruction >> 21) & 0x00000007);
5051 if ((format != fmt_single) && (format != fmt_double))
5052 SignalException(ReservedInstruction,instruction);
5054 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5059 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5060 "round.l.%s<FMT> f<FD>, f<FS>"
5064 // start-sanitize-vr4320
5066 // end-sanitize-vr4320
5067 // start-sanitize-vr5400
5069 // end-sanitize-vr5400
5070 // start-sanitize-r5900
5072 // end-sanitize-r5900
5074 // start-sanitize-tx19
5076 // end-sanitize-tx19
5078 unsigned32 instruction = instruction_0;
5079 int destreg = ((instruction >> 6) & 0x0000001F);
5080 int fs = ((instruction >> 11) & 0x0000001F);
5081 int format = ((instruction >> 21) & 0x00000007);
5083 if ((format != fmt_single) && (format != fmt_double))
5084 SignalException(ReservedInstruction,instruction);
5086 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5091 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5092 "round.w.%s<FMT> f<FD>, f<FS>"
5097 // start-sanitize-vr4320
5099 // end-sanitize-vr4320
5100 // start-sanitize-vr5400
5102 // end-sanitize-vr5400
5103 // start-sanitize-r5900
5105 // end-sanitize-r5900
5107 // start-sanitize-tx19
5109 // end-sanitize-tx19
5111 unsigned32 instruction = instruction_0;
5112 int destreg = ((instruction >> 6) & 0x0000001F);
5113 int fs = ((instruction >> 11) & 0x0000001F);
5114 int format = ((instruction >> 21) & 0x00000007);
5116 if ((format != fmt_single) && (format != fmt_double))
5117 SignalException(ReservedInstruction,instruction);
5119 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5124 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5126 "rsqrt.%s<FMT> f<FD>, f<FS>"
5128 // start-sanitize-vr4320
5130 // end-sanitize-vr4320
5131 // start-sanitize-vr5400
5133 // end-sanitize-vr5400
5135 unsigned32 instruction = instruction_0;
5136 int destreg = ((instruction >> 6) & 0x0000001F);
5137 int fs = ((instruction >> 11) & 0x0000001F);
5138 int format = ((instruction >> 21) & 0x00000007);
5140 if ((format != fmt_single) && (format != fmt_double))
5141 SignalException(ReservedInstruction,instruction);
5143 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5148 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5149 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5154 // start-sanitize-vr4320
5156 // end-sanitize-vr4320
5157 // start-sanitize-vr5400
5159 // end-sanitize-vr5400
5161 // start-sanitize-tx19
5163 // end-sanitize-tx19
5165 address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
5167 if ((vaddr & 7) != 0)
5168 SignalExceptionAddressStore();
5173 AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
5174 memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
5175 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
5180 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
5183 // start-sanitize-vr4320
5185 // end-sanitize-vr4320
5186 // start-sanitize-vr5400
5188 // end-sanitize-vr5400
5190 unsigned32 instruction = instruction_0;
5191 int fs = ((instruction >> 11) & 0x0000001F);
5192 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5193 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5195 address_word vaddr = ((unsigned64)op1 + op2);
5198 if ((vaddr & 7) != 0)
5199 SignalExceptionAddressStore();
5202 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5204 unsigned64 memval = 0;
5205 unsigned64 memval1 = 0;
5206 memval = (unsigned64)COP_SD(1,fs);
5208 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5216 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5217 "sqrt.%s<FMT> f<FD>, f<FS>"
5222 // start-sanitize-vr4320
5224 // end-sanitize-vr4320
5225 // start-sanitize-vr5400
5227 // end-sanitize-vr5400
5229 // start-sanitize-tx19
5231 // end-sanitize-tx19
5233 unsigned32 instruction = instruction_0;
5234 int destreg = ((instruction >> 6) & 0x0000001F);
5235 int fs = ((instruction >> 11) & 0x0000001F);
5236 int format = ((instruction >> 21) & 0x00000007);
5238 if ((format != fmt_single) && (format != fmt_double))
5239 SignalException(ReservedInstruction,instruction);
5241 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5246 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5247 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5248 *mipsI,mipsII,mipsIII,mipsIV:
5250 // start-sanitize-vr4320
5252 // end-sanitize-vr4320
5253 // start-sanitize-vr5400
5255 // end-sanitize-vr5400
5257 // start-sanitize-tx19
5259 // end-sanitize-tx19
5261 unsigned32 instruction = instruction_0;
5262 int destreg = ((instruction >> 6) & 0x0000001F);
5263 int fs = ((instruction >> 11) & 0x0000001F);
5264 int ft = ((instruction >> 16) & 0x0000001F);
5265 int format = ((instruction >> 21) & 0x00000007);
5267 if ((format != fmt_single) && (format != fmt_double))
5268 SignalException(ReservedInstruction,instruction);
5270 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5276 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5277 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5278 *mipsI,mipsII,mipsIII,mipsIV:
5280 // start-sanitize-vr4320
5282 // end-sanitize-vr4320
5283 // start-sanitize-vr5400
5285 // end-sanitize-vr5400
5286 // start-sanitize-r5900
5288 // end-sanitize-r5900
5290 // start-sanitize-tx19
5292 // end-sanitize-tx19
5294 unsigned32 instruction = instruction_0;
5295 signed_word offset = EXTEND16 (OFFSET);
5296 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5297 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5299 address_word vaddr = ((uword64)op1 + offset);
5302 if ((vaddr & 3) != 0)
5303 SignalExceptionAddressStore();
5306 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5309 uword64 memval1 = 0;
5312 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5313 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5314 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5316 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5324 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5325 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5328 // start-sanitize-vr4320
5330 // end-sanitize-vr4320
5331 // start-sanitize-vr5400
5333 // end-sanitize-vr5400
5335 unsigned32 instruction = instruction_0;
5336 int fs = ((instruction >> 11) & 0x0000001F);
5337 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5338 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5340 address_word vaddr = ((unsigned64)op1 + op2);
5343 if ((vaddr & 3) != 0)
5344 SignalExceptionAddressStore();
5347 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5349 unsigned64 memval = 0;
5350 unsigned64 memval1 = 0;
5351 unsigned64 mask = 0x7;
5353 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5354 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5355 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5357 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5365 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5366 "trunc.l.%s<FMT> f<FD>, f<FS>"
5370 // start-sanitize-vr4320
5372 // end-sanitize-vr4320
5373 // start-sanitize-vr5400
5375 // end-sanitize-vr5400
5376 // start-sanitize-r5900
5378 // end-sanitize-r5900
5380 // start-sanitize-tx19
5382 // end-sanitize-tx19
5384 unsigned32 instruction = instruction_0;
5385 int destreg = ((instruction >> 6) & 0x0000001F);
5386 int fs = ((instruction >> 11) & 0x0000001F);
5387 int format = ((instruction >> 21) & 0x00000007);
5389 if ((format != fmt_single) && (format != fmt_double))
5390 SignalException(ReservedInstruction,instruction);
5392 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5397 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5398 "trunc.w.%s<FMT> f<FD>, f<FS>"
5403 // start-sanitize-vr4320
5405 // end-sanitize-vr4320
5406 // start-sanitize-vr5400
5408 // end-sanitize-vr5400
5409 // start-sanitize-r5900
5411 // end-sanitize-r5900
5413 // start-sanitize-tx19
5415 // end-sanitize-tx19
5417 unsigned32 instruction = instruction_0;
5418 int destreg = ((instruction >> 6) & 0x0000001F);
5419 int fs = ((instruction >> 11) & 0x0000001F);
5420 int format = ((instruction >> 21) & 0x00000007);
5422 if ((format != fmt_single) && (format != fmt_double))
5423 SignalException(ReservedInstruction,instruction);
5425 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5431 // MIPS Architecture:
5433 // System Control Instruction Set (COP0)
5437 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5439 *mipsI,mipsII,mipsIII,mipsIV:
5441 // start-sanitize-vr4320
5443 // end-sanitize-vr4320
5444 // start-sanitize-vr5400
5446 // end-sanitize-vr5400
5447 // start-sanitize-r5900
5449 // end-sanitize-r5900
5452 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5454 *mipsI,mipsII,mipsIII,mipsIV:
5456 // start-sanitize-vr4320
5458 // end-sanitize-vr4320
5459 // start-sanitize-vr5400
5461 // end-sanitize-vr5400
5462 // start-sanitize-r5900
5464 // end-sanitize-r5900
5467 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5469 *mipsI,mipsII,mipsIII,mipsIV:
5470 // start-sanitize-r5900
5472 // end-sanitize-r5900
5476 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5478 *mipsI,mipsII,mipsIII,mipsIV:
5480 // start-sanitize-vr4320
5482 // end-sanitize-vr4320
5483 // start-sanitize-vr5400
5485 // end-sanitize-vr5400
5486 // start-sanitize-r5900
5488 // end-sanitize-r5900
5491 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5495 // start-sanitize-vr4320
5497 // end-sanitize-vr4320
5498 // start-sanitize-vr5400
5500 // end-sanitize-vr5400
5501 // start-sanitize-r5900
5503 // end-sanitize-r5900
5505 // start-sanitize-tx19
5507 // end-sanitize-tx19
5509 unsigned32 instruction = instruction_0;
5510 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5511 int hint = ((instruction >> 16) & 0x0000001F);
5512 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5514 address_word vaddr = (op1 + offset);
5517 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5518 CacheOp(hint,vaddr,paddr,instruction);
5523 010000,10000,000000000000000,111001:COP0:32::DI
5525 *mipsI,mipsII,mipsIII,mipsIV:
5527 // start-sanitize-vr4320
5529 // end-sanitize-vr4320
5530 // start-sanitize-vr5400
5532 // end-sanitize-vr5400
5533 // start-sanitize-r5900
5535 // end-sanitize-r5900
5538 010000,10000,000000000000000,111000:COP0:32::EI
5540 *mipsI,mipsII,mipsIII,mipsIV:
5542 // start-sanitize-vr4320
5544 // end-sanitize-vr4320
5545 // start-sanitize-vr5400
5547 // end-sanitize-vr5400
5548 // start-sanitize-r5900
5550 // end-sanitize-r5900
5553 010000,10000,000000000000000,011000:COP0:32::ERET
5558 // start-sanitize-vr4320
5560 // end-sanitize-vr4320
5561 // start-sanitize-vr5400
5563 // end-sanitize-vr5400
5564 // start-sanitize-r5900
5566 // end-sanitize-r5900
5569 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5570 "mfc0 r<RT>, r<RD> # <REGX>"
5571 *mipsI,mipsII,mipsIII,mipsIV:
5573 // start-sanitize-vr4320
5575 // end-sanitize-vr4320
5576 // start-sanitize-vr5400
5578 // end-sanitize-vr5400
5579 // start-sanitize-r5900
5581 // end-sanitize-r5900
5583 DecodeCoproc (instruction_0);
5586 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5587 "mtc0 r<RT>, r<RD> # <REGX>"
5588 *mipsI,mipsII,mipsIII,mipsIV:
5590 // start-sanitize-vr4320
5592 // end-sanitize-vr4320
5593 // start-sanitize-vr5400
5595 // end-sanitize-vr5400
5596 // start-sanitize-r5900
5598 // end-sanitize-r5900
5600 DecodeCoproc (instruction_0);
5604 010000,10000,000000000000000,001000:COP0:32::TLBP
5606 *mipsI,mipsII,mipsIII,mipsIV:
5608 // start-sanitize-vr4320
5610 // end-sanitize-vr4320
5611 // start-sanitize-vr5400
5613 // end-sanitize-vr5400
5614 // start-sanitize-r5900
5616 // end-sanitize-r5900
5619 010000,10000,000000000000000,000001:COP0:32::TLBR
5621 *mipsI,mipsII,mipsIII,mipsIV:
5623 // start-sanitize-vr4320
5625 // end-sanitize-vr4320
5626 // start-sanitize-vr5400
5628 // end-sanitize-vr5400
5629 // start-sanitize-r5900
5631 // end-sanitize-r5900
5634 010000,10000,000000000000000,000010:COP0:32::TLBWI
5636 *mipsI,mipsII,mipsIII,mipsIV:
5638 // start-sanitize-vr4320
5640 // end-sanitize-vr4320
5641 // start-sanitize-vr5400
5643 // end-sanitize-vr5400
5644 // start-sanitize-r5900
5646 // end-sanitize-r5900
5649 010000,10000,000000000000000,000110:COP0:32::TLBWR
5651 *mipsI,mipsII,mipsIII,mipsIV:
5653 // start-sanitize-vr4320
5655 // end-sanitize-vr4320
5656 // start-sanitize-vr5400
5658 // end-sanitize-vr5400
5659 // start-sanitize-r5900
5661 // end-sanitize-r5900
5664 :include:16::m16.igen
5665 // start-sanitize-vr4320
5666 :include::vr4320:vr4320.igen
5667 // end-sanitize-vr4320
5668 // start-sanitize-vr5400
5669 :include::vr5400:vr5400.igen
5670 :include:64,f::mdmx.igen
5671 // end-sanitize-vr5400
5672 // start-sanitize-r5900
5673 :include::r5900:r5900.igen
5674 // end-sanitize-r5900
5676 // start-sanitize-cygnus-never
5678 // // FIXME FIXME FIXME What is this instruction?
5679 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5684 // // start-sanitize-r5900
5686 // // end-sanitize-r5900
5688 // // start-sanitize-tx19
5690 // // end-sanitize-tx19
5692 // unsigned32 instruction = instruction_0;
5693 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5694 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5695 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5697 // if (CoProcPresent(3))
5698 // SignalException(CoProcessorUnusable);
5700 // SignalException(ReservedInstruction,instruction);
5704 // end-sanitize-cygnus-never
5705 // start-sanitize-cygnus-never
5707 // // FIXME FIXME FIXME What is this?
5708 // 11100,******,00001:RR:16::SDBBP
5711 // unsigned32 instruction = instruction_0;
5712 // if (have_extendval)
5713 // SignalException (ReservedInstruction, instruction);
5715 // SignalException(DebugBreakPoint,instruction);
5719 // end-sanitize-cygnus-never
5720 // start-sanitize-cygnus-never
5722 // // FIXME FIXME FIXME What is this?
5723 // 000000,********************,001110:SPECIAL:32::SDBBP
5726 // unsigned32 instruction = instruction_0;
5728 // SignalException(DebugBreakPoint,instruction);
5732 // end-sanitize-cygnus-never
5733 // start-sanitize-cygnus-never
5735 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5736 // // isn't yet reconized by this simulator.
5737 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5740 // unsigned32 instruction = instruction_0;
5741 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5742 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5744 // CHECKHILO("Multiply-Add");
5746 // unsigned64 temp = (op1 * op2);
5747 // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5748 // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5749 // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5754 // end-sanitize-cygnus-never
5755 // start-sanitize-cygnus-never
5757 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5758 // // isn't yet reconized by this simulator.
5759 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5762 // unsigned32 instruction = instruction_0;
5763 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5764 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5766 // CHECKHILO("Multiply-Add");
5768 // unsigned64 temp = (op1 * op2);
5774 // end-sanitize-cygnus-never