sim/mips/mips.igen

   1 //    <insn> ::=
   2 //        <insn-word> { "+" <insn-word> }
   3 //        ":" <format-name>
   4 //        ":" <filter-flags>
   5 //        ":" <options>
   6 //        ":" <name>
   7 //        <nl>
   8 //        { <insn-model> }
   9 //        { <insn-mnemonic> }
  10 //        <code-block>
  11 //
  12
  13
  14 // IGEN config - mips16
  15 :option:16:insn-bit-size:16
  16 :option:16:hi-bit-nr:15
  17 :option:16:insn-specifying-widths:true
  18 :option:16:gen-delayed-branch:false
  19
  20 // IGEN config - mips32/64..
  21 :option:32:insn-bit-size:32
  22 :option:32:hi-bit-nr:31
  23 :option:32:insn-specifying-widths:true
  24 :option:32:gen-delayed-branch:false
  25
  26
  27 // Generate separate simulators for each target
  28 // :option::multi-sim:true
  29
  30
  31 // Models known by this simulator
  32 :model::mipsI:mipsI:
  33 :model::mipsII:mipsII:
  34 :model::mipsIII:mipsIII:
  35 :model::mipsIV:mipsIV:
  36 :model::mips16:mips16:
  37 // start-sanitize-r5900
  38 :model::r5900:r5900:
  39 // end-sanitize-r5900
  40 :model::r3900:r3900:
  41 // start-sanitize-tx19
  42 :model::tx19:tx19:
  43 // end-sanitize-tx19
  44 // start-sanitize-vr5400
  45 :model::vr5400:vr5400:
  46 // end-sanitize-vr5400
  47
  48
  49
  50 // Pseudo instructions known by IGEN
  51 :internal:::illegal
  52 {
  53   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  54                   (unsigned long) CIA);
  55   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  56 }
  57
  58
  59
  60
  61 //
  62 // MIPS Architecture:
  63 //
  64 //        CPU Instruction Set (mipsI - mipsIV)
  65 //
  66
  67
  68 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
  69 "add r<RD>, r<RS>, r<RT>"
  70 *mipsI:
  71 *mipsII:
  72 *mipsIII:
  73 *mipsIV:
  74 // start-sanitize-vr5400
  75 *vr5400:
  76 // end-sanitize-vr5400
  77 // start-sanitize-r5900
  78 *r5900:
  79 // end-sanitize-r5900
  80 *r3900:
  81 // start-sanitize-tx19
  82 *tx19:
  83 // end-sanitize-tx19
  84 {
  85   ALU32_BEGIN (GPR[RS]);
  86   ALU32_ADD (GPR[RT]);
  87   ALU32_END (GPR[RD]);
  88 }
  89
  90
  91 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
  92 "addi r<RT>, r<RS>, IMMEDIATE"
  93 *mipsI:
  94 *mipsII:
  95 *mipsIII:
  96 *mipsIV:
  97 // start-sanitize-vr5400
  98 *vr5400:
  99 // end-sanitize-vr5400
 100 // start-sanitize-r5900
 101 *r5900:
 102 // end-sanitize-r5900
 103 *r3900:
 104 // start-sanitize-tx19
 105 *tx19:
 106 // end-sanitize-tx19
 107 {
 108   ALU32_BEGIN (GPR[RS]);
 109   ALU32_ADD (EXTEND16 (IMMEDIATE));
 110   ALU32_END (GPR[RT]);
 111 }
 112
 113
 114 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 115 "add r<RT>, r<RS>, IMMEDIATE"
 116 *mipsI:
 117 *mipsII:
 118 *mipsIII:
 119 *mipsIV:
 120 // start-sanitize-vr5400
 121 *vr5400:
 122 // end-sanitize-vr5400
 123 // start-sanitize-r5900
 124 *r5900:
 125 // end-sanitize-r5900
 126 *r3900:
 127 // start-sanitize-tx19
 128 *tx19:
 129 // end-sanitize-tx19
 130 {
 131   signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
 132   GPR[RT] = EXTEND32 (temp);
 133 }
 134
 135
 136 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 137 *mipsI:
 138 *mipsII:
 139 *mipsIII:
 140 *mipsIV:
 141 // start-sanitize-vr5400
 142 *vr5400:
 143 // end-sanitize-vr5400
 144 // start-sanitize-r5900
 145 *r5900:
 146 // end-sanitize-r5900
 147 *r3900:
 148 // start-sanitize-tx19
 149 *tx19:
 150 // end-sanitize-tx19
 151 {
 152   signed32 temp = GPR[RS] + GPR[RT];
 153   GPR[RD] = EXTEND32 (temp);
 154 }
 155
 156
 157 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 158 "and r<RD>, r<RS>, r<RT>"
 159 *mipsI:
 160 *mipsII:
 161 *mipsIII:
 162 *mipsIV:
 163 // start-sanitize-vr5400
 164 *vr5400:
 165 // end-sanitize-vr5400
 166 // start-sanitize-r5900
 167 *r5900:
 168 // end-sanitize-r5900
 169 *r3900:
 170 // start-sanitize-tx19
 171 *tx19:
 172 // end-sanitize-tx19
 173 {
 174   GPR[RD] = GPR[RS] & GPR[RT];
 175 }
 176
 177
 178 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 179 "and r<RT>, r<RS>, IMMEDIATE"
 180 *mipsI:
 181 *mipsII:
 182 *mipsIII:
 183 // start-sanitize-vr5400
 184 *vr5400:
 185 // end-sanitize-vr5400
 186 // start-sanitize-r5900
 187 *r5900:
 188 // end-sanitize-r5900
 189 *r3900:
 190 // start-sanitize-tx19
 191 *tx19:
 192 // end-sanitize-tx19
 193 {
 194   GPR[RT] = GPR[RS] & IMMEDIATE;
 195 }
 196
 197
 198 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 199 "beq r<RS>, r<RT>, OFFSET"
 200 *mipsI:
 201 *mipsII:
 202 *mipsIII:
 203 *mipsIV:
 204 // start-sanitize-vr5400
 205 *vr5400:
 206 // end-sanitize-vr5400
 207 // start-sanitize-r5900
 208 *r5900:
 209 // end-sanitize-r5900
 210 *r3900:
 211 // start-sanitize-tx19
 212 *tx19:
 213 // end-sanitize-tx19
 214 {
 215   address_word offset = EXTEND16 (OFFSET) << 2;
 216   if (GPR[RS] == GPR[RT])
 217     DELAY_SLOT (PC + offset);
 218 }
 219
 220
 221 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 222 "beql r<RS>, r<RT>, <OFFSET>"
 223 *mipsII:
 224 *mipsIII:
 225 *mipsIV:
 226 // start-sanitize-vr5400
 227 *vr5400:
 228 // end-sanitize-vr5400
 229 // start-sanitize-r5900
 230 *r5900:
 231 // end-sanitize-r5900
 232 *r3900:
 233 // start-sanitize-tx19
 234 *tx19:
 235 // end-sanitize-tx19
 236 {
 237   address_word offset = EXTEND16 (OFFSET) << 2;
 238   if (GPR[RS] == GPR[RT])
 239     DELAY_SLOT (PC + offset);
 240   else
 241     NULLIFY_NEXT_INSTRUCTION ();
 242 }
 243
 244
 245 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 246 "bgez r<RS>, <OFFSET>"
 247 *mipsI:
 248 *mipsII:
 249 *mipsIII:
 250 *mipsIV:
 251 // start-sanitize-vr5400
 252 *vr5400:
 253 // end-sanitize-vr5400
 254 // start-sanitize-r5900
 255 *r5900:
 256 // end-sanitize-r5900
 257 *r3900:
 258 // start-sanitize-tx19
 259 *tx19:
 260 // end-sanitize-tx19
 261 {
 262   address_word offset = EXTEND16 (OFFSET) << 2;
 263   if (GPR[RS] >= 0)
 264     DELAY_SLOT (PC + offset);
 265 }
 266
 267
 268 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 269 "bgezal r<RS>, <OFFSET>"
 270 *mipsI:
 271 *mipsII:
 272 *mipsIII:
 273 *mipsIV:
 274 // start-sanitize-vr5400
 275 *vr5400:
 276 // end-sanitize-vr5400
 277 // start-sanitize-r5900
 278 *r5900:
 279 // end-sanitize-r5900
 280 *r3900:
 281 // start-sanitize-tx19
 282 *tx19:
 283 // end-sanitize-tx19
 284 {
 285   address_word offset = EXTEND16 (OFFSET) << 2;
 286   RA = (CIA + 8);
 287   if (GPR[RS] >= 0)
 288     DELAY_SLOT (PC + offset);
 289 }
 290
 291
 292 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 293 "bgezall r<RS>, <OFFSET>"
 294 *mipsII:
 295 *mipsIII:
 296 *mipsIV:
 297 // start-sanitize-vr5400
 298 *vr5400:
 299 // end-sanitize-vr5400
 300 // start-sanitize-r5900
 301 *r5900:
 302 // end-sanitize-r5900
 303 *r3900:
 304 // start-sanitize-tx19
 305 *tx19:
 306 // end-sanitize-tx19
 307 {
 308   address_word offset = EXTEND16 (OFFSET) << 2;
 309   RA = (CIA + 8);
 310   /* NOTE: The branch occurs AFTER the next instruction has been
 311      executed */
 312   if (GPR[RS] >= 0)
 313     DELAY_SLOT (PC + offset);
 314   else
 315     NULLIFY_NEXT_INSTRUCTION ();
 316 }
 317
 318
 319 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 320 "bgezl r<RS>, <OFFSET>"
 321 *mipsII:
 322 *mipsIII:
 323 *mipsIV:
 324 // start-sanitize-vr5400
 325 *vr5400:
 326 // end-sanitize-vr5400
 327 // start-sanitize-r5900
 328 *r5900:
 329 // end-sanitize-r5900
 330 *r3900:
 331 // start-sanitize-tx19
 332 *tx19:
 333 // end-sanitize-tx19
 334 {
 335   address_word offset = EXTEND16 (OFFSET) << 2;
 336   if (GPR[RS] >= 0)
 337     DELAY_SLOT (PC + offset);
 338   else
 339     NULLIFY_NEXT_INSTRUCTION ();
 340 }
 341
 342
 343 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 344 "bgtz r<RS>, <OFFSET>"
 345 *mipsI:
 346 *mipsII:
 347 *mipsIII:
 348 *mipsIV:
 349 // start-sanitize-vr5400
 350 *vr5400:
 351 // end-sanitize-vr5400
 352 // start-sanitize-r5900
 353 *r5900:
 354 // end-sanitize-r5900
 355 *r3900:
 356 // start-sanitize-tx19
 357 *tx19:
 358 // end-sanitize-tx19
 359 {
 360   address_word offset = EXTEND16 (OFFSET) << 2;
 361   if (GPR[RS] > 0)
 362     DELAY_SLOT (PC + offset);
 363 }
 364
 365
 366 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 367 "bgtzl r<RS>, <OFFSET>"
 368 *mipsII:
 369 *mipsIII:
 370 *mipsIV:
 371 // start-sanitize-vr5400
 372 *vr5400:
 373 // end-sanitize-vr5400
 374 // start-sanitize-r5900
 375 *r5900:
 376 // end-sanitize-r5900
 377 *r3900:
 378 // start-sanitize-tx19
 379 *tx19:
 380 // end-sanitize-tx19
 381 {
 382   address_word offset = EXTEND16 (OFFSET) << 2;
 383   /* NOTE: The branch occurs AFTER the next instruction has been
 384      executed */
 385   if (GPR[RS] > 0)
 386     DELAY_SLOT (PC + offset);
 387   else
 388     NULLIFY_NEXT_INSTRUCTION ();
 389 }
 390
 391
 392 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 393 "blez r<RS>, <OFFSET>"
 394 *mipsI:
 395 *mipsII:
 396 *mipsIII:
 397 *mipsIV:
 398 // start-sanitize-vr5400
 399 *vr5400:
 400 // end-sanitize-vr5400
 401 // start-sanitize-r5900
 402 *r5900:
 403 // end-sanitize-r5900
 404 *r3900:
 405 // start-sanitize-tx19
 406 *tx19:
 407 // end-sanitize-tx19
 408 {
 409   address_word offset = EXTEND16 (OFFSET) << 2;
 410   /* NOTE: The branch occurs AFTER the next instruction has been
 411      executed */
 412   if (GPR[RS] <= 0)
 413     DELAY_SLOT (PC + offset);
 414 }
 415
 416
 417 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 418 "bgezl r<RS>, <OFFSET>"
 419 *mipsII:
 420 *mipsIII:
 421 *mipsIV:
 422 // start-sanitize-vr5400
 423 *vr5400:
 424 // end-sanitize-vr5400
 425 // start-sanitize-r5900
 426 *r5900:
 427 // end-sanitize-r5900
 428 *r3900:
 429 // start-sanitize-tx19
 430 *tx19:
 431 // end-sanitize-tx19
 432 {
 433   address_word offset = EXTEND16 (OFFSET) << 2;
 434   if (GPR[RS] <= 0)
 435     DELAY_SLOT (PC + offset);
 436   else
 437     NULLIFY_NEXT_INSTRUCTION ();
 438 }
 439
 440
 441 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 442 "bltz r<RS>, <OFFSET>"
 443 *mipsI:
 444 *mipsII:
 445 *mipsIII:
 446 *mipsIV:
 447 // start-sanitize-vr5400
 448 *vr5400:
 449 // end-sanitize-vr5400
 450 // start-sanitize-r5900
 451 *r5900:
 452 // end-sanitize-r5900
 453 *r3900:
 454 // start-sanitize-tx19
 455 *tx19:
 456 // end-sanitize-tx19
 457 {
 458   address_word offset = EXTEND16 (OFFSET) << 2;
 459   if (GPR[RS] < 0)
 460     DELAY_SLOT (PC + offset);
 461 }
 462
 463
 464 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 465 "bltzal r<RS>, <OFFSET>"
 466 *mipsI:
 467 *mipsII:
 468 *mipsIII:
 469 *mipsIV:
 470 // start-sanitize-vr5400
 471 *vr5400:
 472 // end-sanitize-vr5400
 473 // start-sanitize-r5900
 474 *r5900:
 475 // end-sanitize-r5900
 476 *r3900:
 477 // start-sanitize-tx19
 478 *tx19:
 479 // end-sanitize-tx19
 480 {
 481   address_word offset = EXTEND16 (OFFSET) << 2;
 482   RA = (CIA + 8);
 483   /* NOTE: The branch occurs AFTER the next instruction has been
 484      executed */
 485   if (GPR[RS] < 0)
 486     DELAY_SLOT (PC + offset);
 487 }
 488
 489
 490 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 491 "bltzall r<RS>, <OFFSET>"
 492 *mipsII:
 493 *mipsIII:
 494 *mipsIV:
 495 // start-sanitize-vr5400
 496 *vr5400:
 497 // end-sanitize-vr5400
 498 // start-sanitize-r5900
 499 *r5900:
 500 // end-sanitize-r5900
 501 *r3900:
 502 // start-sanitize-tx19
 503 *tx19:
 504 // end-sanitize-tx19
 505 {
 506   address_word offset = EXTEND16 (OFFSET) << 2;
 507   RA = (CIA + 8);
 508   if (GPR[RS] < 0)
 509     DELAY_SLOT (PC + offset);
 510   else
 511     NULLIFY_NEXT_INSTRUCTION ();
 512 }
 513
 514
 515 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 516 "bltzl r<RS>, <OFFSET>"
 517 *mipsII:
 518 *mipsIII:
 519 *mipsIV:
 520 // start-sanitize-vr5400
 521 *vr5400:
 522 // end-sanitize-vr5400
 523 // start-sanitize-r5900
 524 *r5900:
 525 // end-sanitize-r5900
 526 *r3900:
 527 // start-sanitize-tx19
 528 *tx19:
 529 // end-sanitize-tx19
 530 {
 531   address_word offset = EXTEND16 (OFFSET) << 2;
 532   /* NOTE: The branch occurs AFTER the next instruction has been
 533      executed */
 534   if (GPR[RS] < 0)
 535     DELAY_SLOT (PC + offset);
 536   else
 537     NULLIFY_NEXT_INSTRUCTION ();
 538 }
 539
 540
 541 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 542 "bne r<RS>, r<RT>, <OFFSET>"
 543 *mipsI:
 544 *mipsII:
 545 *mipsIII:
 546 *mipsIV:
 547 // start-sanitize-vr5400
 548 *vr5400:
 549 // end-sanitize-vr5400
 550 // start-sanitize-r5900
 551 *r5900:
 552 // end-sanitize-r5900
 553 *r3900:
 554 // start-sanitize-tx19
 555 *tx19:
 556 // end-sanitize-tx19
 557 {
 558   address_word offset = EXTEND16 (OFFSET) << 2;
 559   if (GPR[RS] != GPR[RT])
 560     DELAY_SLOT (PC + offset);
 561 }
 562
 563
 564 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 565 "bnel r<RS>, r<RT>, <OFFSET>"
 566 *mipsII:
 567 *mipsIII:
 568 *mipsIV:
 569 // start-sanitize-vr5400
 570 *vr5400:
 571 // end-sanitize-vr5400
 572 // start-sanitize-r5900
 573 *r5900:
 574 // end-sanitize-r5900
 575 *r3900:
 576 // start-sanitize-tx19
 577 *tx19:
 578 // end-sanitize-tx19
 579 {
 580   address_word offset = EXTEND16 (OFFSET) << 2;
 581   if (GPR[RS] != GPR[RT])
 582     DELAY_SLOT (PC + offset);
 583   else
 584     NULLIFY_NEXT_INSTRUCTION ();
 585 }
 586
 587
 588 000000,20.CODE,001101:SPECIAL:32::BREAK
 589 "break"
 590 *mipsI:
 591 *mipsII:
 592 *mipsIII:
 593 *mipsIV:
 594 // start-sanitize-vr5400
 595 *vr5400:
 596 // end-sanitize-vr5400
 597 // start-sanitize-r5900
 598 *r5900:
 599 // end-sanitize-r5900
 600 *r3900:
 601 // start-sanitize-tx19
 602 *tx19:
 603 // end-sanitize-tx19
 604 {
 605   SignalException(BreakPoint, instruction_0);
 606 }
 607
 608
 609 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 610 "cop<ZZ> <COP_FUN>"
 611 *mipsI:
 612 *mipsII:
 613 *mipsIII:
 614 *mipsIV:
 615 // start-sanitize-vr5400
 616 *vr5400:
 617 // end-sanitize-vr5400
 618 // start-sanitize-r5900
 619 *r5900:
 620 // end-sanitize-r5900
 621 *r3900:
 622 // start-sanitize-tx19
 623 *tx19:
 624 // end-sanitize-tx19
 625 {
 626   DecodeCoproc (instruction_0);
 627 }
 628
 629
 630 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 631 "dadd r<RD>, r<RS>, r<RT>"
 632 *mipsIII:
 633 *mipsIV:
 634 // start-sanitize-vr5400
 635 *vr5400:
 636 // end-sanitize-vr5400
 637 // start-sanitize-r5900
 638 *r5900:
 639 // end-sanitize-r5900
 640 *r3900:
 641 // start-sanitize-tx19
 642 *tx19:
 643 // end-sanitize-tx19
 644 {
 645   ALU64_BEGIN (GPR[RS]);
 646   ALU64_ADD (GPR[RT]);
 647   ALU64_END (GPR[RT]);
 648 }
 649
 650
 651 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 652 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 653 *mipsIII:
 654 *mipsIV:
 655 // start-sanitize-vr5400
 656 *vr5400:
 657 // end-sanitize-vr5400
 658 // start-sanitize-r5900
 659 *r5900:
 660 // end-sanitize-r5900
 661 *r3900:
 662 // start-sanitize-tx19
 663 *tx19:
 664 // end-sanitize-tx19
 665 {
 666   ALU64_BEGIN (GPR[RS]);
 667   ALU64_ADD (EXTEND16 (IMMEDIATE));
 668   ALU64_END (GPR[RT]);
 669 }
 670
 671
 672 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 673 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 674 *mipsIII:
 675 *mipsIV:
 676 // start-sanitize-vr5400
 677 *vr5400:
 678 // end-sanitize-vr5400
 679 // start-sanitize-r5900
 680 *r5900:
 681 // end-sanitize-r5900
 682 *r3900:
 683 // start-sanitize-tx19
 684 *tx19:
 685 // end-sanitize-tx19
 686 {
 687   GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
 688 }
 689
 690
 691 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 692 "daddu r<RD>, r<RS>, r<RT>"
 693 *mipsIII:
 694 *mipsIV:
 695 // start-sanitize-vr5400
 696 *vr5400:
 697 // end-sanitize-vr5400
 698 // start-sanitize-r5900
 699 *r5900:
 700 // end-sanitize-r5900
 701 *r3900:
 702 // start-sanitize-tx19
 703 *tx19:
 704 // end-sanitize-tx19
 705 {
 706   GPR[RD] = GPR[RS] + GPR[RT];
 707 }
 708
 709
 710 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 711 "ddiv r<RS>, r<RT>"
 712 *mipsIII:
 713 *mipsIV:
 714 // start-sanitize-vr5400
 715 *vr5400:
 716 // end-sanitize-vr5400
 717 // start-sanitize-r5900
 718 *r5900:
 719 // end-sanitize-r5900
 720 *r3900:
 721 // start-sanitize-tx19
 722 *tx19:
 723 // end-sanitize-tx19
 724 {
 725   CHECKHILO ("Division");
 726   {
 727     signed64 n = GPR[RS];
 728     signed64 d = GPR[RT];
 729     if (d == 0)
 730       {
 731         LO = SIGNED64 (0x8000000000000000);
 732         HI = 0;
 733       }
 734     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 735       {
 736         LO = SIGNED64 (0x8000000000000000);
 737         HI = 0;
 738       }
 739     else
 740       {
 741         LO = (n / d);
 742         HI = (n % d);
 743       }
 744   }
 745 }
 746
 747
 748
 749 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 750 "ddivu r<RS>, r<RT>"
 751 *mipsIII:
 752 *mipsIV:
 753 *r3900:
 754 // start-sanitize-vr5400
 755 *vr5400:
 756 // end-sanitize-vr5400
 757 // start-sanitize-tx19
 758 *tx19:
 759 // end-sanitize-tx19
 760 {
 761   CHECKHILO ("Division");
 762   {
 763     unsigned64 n = GPR[RS];
 764     unsigned64 d = GPR[RT];
 765     if (d == 0)
 766       {
 767         LO = SIGNED64 (0x8000000000000000);
 768         HI = 0;
 769       }
 770     else
 771       {
 772         LO = (n / d);
 773         HI = (n % d);
 774       }
 775   }
 776 }
 777
 778
 779 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 780 "div r<RS>, r<RT>"
 781 *mipsI:
 782 *mipsII:
 783 *mipsIII:
 784 *mipsIV:
 785 // start-sanitize-vr5400
 786 *vr5400:
 787 // end-sanitize-vr5400
 788 // start-sanitize-r5900
 789 *r5900:
 790 // end-sanitize-r5900
 791 *r3900:
 792 // start-sanitize-tx19
 793 *tx19:
 794 // end-sanitize-tx19
 795 {
 796   CHECKHILO("Division");
 797   {
 798     signed32 n = GPR[RS];
 799     signed32 d = GPR[RT];
 800     if (d == 0)
 801       {
 802         LO = EXTEND32 (0x80000000);
 803         HI = EXTEND32 (0);
 804       }
 805     else if (d == -1 && d == 0x80000000)
 806       {
 807         LO = EXTEND32 (0x80000000);
 808         HI = EXTEND32 (0);
 809       }
 810     else
 811       {
 812         LO = EXTEND32 (n / d);
 813         HI = EXTEND32 (n % d);
 814       }
 815   }
 816 }
 817
 818
 819 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 820 "divu r<RS>, r<RT>"
 821 *mipsI:
 822 *mipsII:
 823 *mipsIII:
 824 *mipsIV:
 825 // start-sanitize-vr5400
 826 *vr5400:
 827 // end-sanitize-vr5400
 828 // start-sanitize-r5900
 829 *r5900:
 830 // end-sanitize-r5900
 831 *r3900:
 832 // start-sanitize-tx19
 833 *tx19:
 834 // end-sanitize-tx19
 835 {
 836   CHECKHILO ("Division");
 837   {
 838     unsigned32 n = GPR[RS];
 839     unsigned32 d = GPR[RT];
 840     if (d == 0)
 841       {
 842         LO = EXTEND32 (0x80000000);
 843         HI = EXTEND32 (0);
 844       }
 845    else
 846      {
 847        LO = EXTEND32 (n / d);
 848        HI = EXTEND32 (n % d);
 849      }
 850   }
 851 }
 852
 853
 854 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 855 "dmult r<RS>, r<RT>"
 856 *mipsIII:
 857 *mipsIV:
 858 // start-sanitize-vr5400
 859 *vr5400:
 860 // end-sanitize-vr5400
 861 *r3900:
 862 // start-sanitize-tx19
 863 *tx19:
 864 // end-sanitize-tx19
 865 {
 866   CHECKHILO ("Multiplication");
 867   {
 868     signed64 op1 = GPR[RS];
 869     signed64 op2 = GPR[RT];
 870     unsigned64 lo;
 871     unsigned64 hi;
 872     unsigned64 m00;
 873     unsigned64 m01;
 874     unsigned64 m10;
 875     unsigned64 m11;
 876     unsigned64 mid;
 877     int sign = 0;
 878     /* make it unsigned */
 879     if (op1 < 0)
 880       {
 881         op1 = - op1;
 882         ++sign;
 883       }
 884     if (op2 < 0)
 885       {
 886         op2 = - op2;
 887         ++sign;
 888       }
 889     /* multuply out the 4 sub products */
 890     m00 = (VL4_8 (op1) * VL4_8 (op2));
 891     m10 = (VH4_8 (op1) * VL4_8 (op2));
 892     m01 = (VL4_8 (op1) * VH4_8 (op2));
 893     m11 = (VH4_8 (op1) * VH4_8 (op2));
 894     /* add the products */
 895     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 896     lo = U8_4 (mid, m00);
 897     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 898     /* save the result */
 899     if (sign & 1)
 900       {
 901         LO = -lo;
 902         if (lo == 0)
 903           HI = -hi;
 904         else
 905           HI = -hi - 1;
 906       }
 907     else
 908       {
 909         LO = lo;
 910         HI = hi;
 911       }
 912   }
 913 }
 914
 915
 916 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
 917 "dmultu r<RS>, r<RT>"
 918 *mipsIII:
 919 *mipsIV:
 920 // start-sanitize-vr5400
 921 *vr5400:
 922 // end-sanitize-vr5400
 923 *r3900:
 924 // start-sanitize-tx19
 925 *tx19:
 926 // end-sanitize-tx19
 927 {
 928   CHECKHILO ("Multiplication");
 929   {
 930     signed64 op1 = GPR[RS];
 931     signed64 op2 = GPR[RT];
 932     unsigned64 lo;
 933     unsigned64 hi;
 934     unsigned64 m00;
 935     unsigned64 m01;
 936     unsigned64 m10;
 937     unsigned64 m11;
 938     unsigned64 mid;
 939     /* multuply out the 4 sub products */
 940     m00 = (VL4_8 (op1) * VL4_8 (op2));
 941     m10 = (VH4_8 (op1) * VL4_8 (op2));
 942     m01 = (VL4_8 (op1) * VH4_8 (op2));
 943     m11 = (VH4_8 (op1) * VH4_8 (op2));
 944     /* add the products */
 945     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 946     lo = U8_4 (mid, m00);
 947     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 948     /* save the result */
 949     LO = lo;
 950     HI = hi;
 951   }
 952 }
 953
 954
 955 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
 956 "dsll r<RD>, r<RT>, <SA>"
 957 *mipsIII:
 958 *mipsIV:
 959 // start-sanitize-vr5400
 960 *vr5400:
 961 // end-sanitize-vr5400
 962 // start-sanitize-r5900
 963 *r5900:
 964 // end-sanitize-r5900
 965 *r3900:
 966 // start-sanitize-tx19
 967 *tx19:
 968 // end-sanitize-tx19
 969 {
 970   int s = SA;
 971   GPR[RD] = GPR[RT] << s;
 972 }
 973
 974
 975 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
 976 "dsll32 r<RD>, r<RT>, <SA>"
 977 *mipsIII:
 978 *mipsIV:
 979 // start-sanitize-vr5400
 980 *vr5400:
 981 // end-sanitize-vr5400
 982 // start-sanitize-r5900
 983 *r5900:
 984 // end-sanitize-r5900
 985 *r3900:
 986 // start-sanitize-tx19
 987 *tx19:
 988 // end-sanitize-tx19
 989 {
 990   int s = 32 + SA;
 991   GPR[RD] = GPR[RT] << s;
 992 }
 993
 994
 995 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
 996 "dsllv r<RD>, r<RT>, r<RS>"
 997 *mipsIII:
 998 *mipsIV:
 999 // start-sanitize-vr5400
1000 *vr5400:
1001 // end-sanitize-vr5400
1002 // start-sanitize-r5900
1003 *r5900:
1004 // end-sanitize-r5900
1005 *r3900:
1006 // start-sanitize-tx19
1007 *tx19:
1008 // end-sanitize-tx19
1009 {
1010   int s = MASKED64 (GPR[RS], 5, 0);
1011   GPR[RD] = GPR[RT] << s;
1012 }
1013
1014
1015 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1016 "dsra r<RD>, r<RT>, <SA>"
1017 *mipsIII:
1018 *mipsIV:
1019 // start-sanitize-vr5400
1020 *vr5400:
1021 // end-sanitize-vr5400
1022 // start-sanitize-r5900
1023 *r5900:
1024 // end-sanitize-r5900
1025 *r3900:
1026 // start-sanitize-tx19
1027 *tx19:
1028 // end-sanitize-tx19
1029 {
1030   int s = SA;
1031   GPR[RD] = ((signed64) GPR[RT]) >> s;
1032 }
1033
1034
1035 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1036 "dsra32 r<RT>, r<RD>, <SA>"
1037 *mipsIII:
1038 *mipsIV:
1039 // start-sanitize-vr5400
1040 *vr5400:
1041 // end-sanitize-vr5400
1042 // start-sanitize-r5900
1043 *r5900:
1044 // end-sanitize-r5900
1045 *r3900:
1046 // start-sanitize-tx19
1047 *tx19:
1048 // end-sanitize-tx19
1049 {
1050   int s = 32 + SA;
1051   GPR[RD] = ((signed64) GPR[RT]) >> s;
1052 }
1053
1054
1055 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1056 "dsra32 r<RT>, r<RD>, r<RS>"
1057 *mipsIII:
1058 *mipsIV:
1059 // start-sanitize-vr5400
1060 *vr5400:
1061 // end-sanitize-vr5400
1062 // start-sanitize-r5900
1063 *r5900:
1064 // end-sanitize-r5900
1065 *r3900:
1066 // start-sanitize-tx19
1067 *tx19:
1068 // end-sanitize-tx19
1069 {
1070   int s = MASKED64 (GPR[RS], 5, 0);
1071   GPR[RD] = ((signed64) GPR[RT]) >> s;
1072 }
1073
1074
1075 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1076 "dsrav r<RD>, r<RT>, <SA>"
1077 *mipsIII:
1078 *mipsIV:
1079 // start-sanitize-vr5400
1080 *vr5400:
1081 // end-sanitize-vr5400
1082 // start-sanitize-r5900
1083 *r5900:
1084 // end-sanitize-r5900
1085 *r3900:
1086 // start-sanitize-tx19
1087 *tx19:
1088 // end-sanitize-tx19
1089 {
1090   int s = SA;
1091   GPR[RD] = (unsigned64) GPR[RT] >> s;
1092 }
1093
1094
1095 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1096 "dsrl32 r<RD>, r<RT>, <SA>"
1097 *mipsIII:
1098 *mipsIV:
1099 // start-sanitize-vr5400
1100 *vr5400:
1101 // end-sanitize-vr5400
1102 // start-sanitize-r5900
1103 *r5900:
1104 // end-sanitize-r5900
1105 *r3900:
1106 // start-sanitize-tx19
1107 *tx19:
1108 // end-sanitize-tx19
1109 {
1110   int s = 32 + SA;
1111   GPR[RD] = (unsigned64) GPR[RT] >> s;
1112 }
1113
1114
1115 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1116 "dsrl32 r<RD>, r<RT>, r<RS>"
1117 *mipsIII:
1118 *mipsIV:
1119 // start-sanitize-vr5400
1120 *vr5400:
1121 // end-sanitize-vr5400
1122 // start-sanitize-r5900
1123 *r5900:
1124 // end-sanitize-r5900
1125 *r3900:
1126 // start-sanitize-tx19
1127 *tx19:
1128 // end-sanitize-tx19
1129 {
1130   int s = MASKED64 (GPR[RS], 5, 0);
1131   GPR[RD] = (unsigned64) GPR[RT] >> s;
1132 }
1133
1134
1135 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1136 "dsub r<RD>, r<RS>, r<RT>"
1137 *mipsIII:
1138 *mipsIV:
1139 // start-sanitize-vr5400
1140 *vr5400:
1141 // end-sanitize-vr5400
1142 // start-sanitize-r5900
1143 *r5900:
1144 // end-sanitize-r5900
1145 *r3900:
1146 // start-sanitize-tx19
1147 *tx19:
1148 // end-sanitize-tx19
1149 {
1150   ALU64_BEGIN (GPR[RS]);
1151   ALU64_SUB (GPR[RT]);
1152   ALU64_END (GPR[RD]);
1153 }
1154
1155
1156 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1157 "dsubu r<RD>, r<RS>, r<RT>"
1158 *mipsIII:
1159 *mipsIV:
1160 // start-sanitize-vr5400
1161 *vr5400:
1162 // end-sanitize-vr5400
1163 // start-sanitize-r5900
1164 *r5900:
1165 // end-sanitize-r5900
1166 *r3900:
1167 // start-sanitize-tx19
1168 *tx19:
1169 // end-sanitize-tx19
1170 {
1171   GPR[RD] = GPR[RS] - GPR[RT];
1172 }
1173
1174
1175 000010,26.INSTR_INDEX:NORMAL:32::J
1176 "j <INSTR_INDEX>"
1177 *mipsI:
1178 *mipsII:
1179 *mipsIII:
1180 *mipsIV:
1181 // start-sanitize-vr5400
1182 *vr5400:
1183 // end-sanitize-vr5400
1184 // start-sanitize-r5900
1185 *r5900:
1186 // end-sanitize-r5900
1187 *r3900:
1188 // start-sanitize-tx19
1189 *tx19:
1190 // end-sanitize-tx19
1191 {
1192   /* NOTE: The region used is that of the delay slot NIA and NOT the
1193      current instruction */
1194   address_word region = (NIA & MASK (63, 28));
1195   DELAY_SLOT (region | (INSTR_INDEX << 2));
1196 }
1197
1198
1199 000011,26.INSTR_INDEX:NORMAL:32::JAL
1200 "jal <INSTR_INDEX>"
1201 *mipsI:
1202 *mipsII:
1203 *mipsIII:
1204 *mipsIV:
1205 // start-sanitize-vr5400
1206 *vr5400:
1207 // end-sanitize-vr5400
1208 // start-sanitize-r5900
1209 *r5900:
1210 // end-sanitize-r5900
1211 *r3900:
1212 // start-sanitize-tx19
1213 *tx19:
1214 // end-sanitize-tx19
1215 {
1216   /* NOTE: The region used is that of the delay slot and NOT the
1217      current instruction */
1218   address_word region = (NIA & MASK (63, 28));
1219   GPR[31] = CIA + 8;
1220   DELAY_SLOT (region | (INSTR_INDEX << 2));
1221 }
1222
1223
1224 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1225 "jalr r<RS>":RD == 31
1226 "jalr r<RD>, r<RS>"
1227 *mipsI:
1228 *mipsII:
1229 *mipsIII:
1230 *mipsIV:
1231 // start-sanitize-vr5400
1232 *vr5400:
1233 // end-sanitize-vr5400
1234 // start-sanitize-r5900
1235 *r5900:
1236 // end-sanitize-r5900
1237 *r3900:
1238 // start-sanitize-tx19
1239 *tx19:
1240 // end-sanitize-tx19
1241 {
1242   address_word temp = GPR[RS];
1243   GPR[RD] = CIA + 8;
1244   DELAY_SLOT (temp);
1245 }
1246
1247
1248 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1249 "jr r<RS>"
1250 *mipsI:
1251 *mipsII:
1252 *mipsIII:
1253 *mipsIV:
1254 // start-sanitize-vr5400
1255 *vr5400:
1256 // end-sanitize-vr5400
1257 // start-sanitize-r5900
1258 *r5900:
1259 // end-sanitize-r5900
1260 *r3900:
1261 // start-sanitize-tx19
1262 *tx19:
1263 // end-sanitize-tx19
1264 {
1265   DELAY_SLOT (GPR[RS]);
1266 }
1267
1268
1269 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1270 "lb r<RT>, <OFFSET>(r<BASE>)"
1271 *mipsI:
1272 *mipsII:
1273 *mipsIII:
1274 *mipsIV:
1275 // start-sanitize-vr5400
1276 *vr5400:
1277 // end-sanitize-vr5400
1278 // start-sanitize-r5900
1279 *r5900:
1280 // end-sanitize-r5900
1281 *r3900:
1282 // start-sanitize-tx19
1283 *tx19:
1284 // end-sanitize-tx19
1285 {
1286   unsigned32 instruction = instruction_0;
1287   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1288   int destreg = ((instruction >> 16) & 0x0000001F);
1289   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1290   {
1291     address_word vaddr = ((uword64)op1 + offset);
1292     address_word paddr;
1293     int uncached;
1294     {
1295       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1296         {
1297           uword64 memval = 0;
1298           uword64 memval1 = 0;
1299           uword64 mask = 0x7;
1300           unsigned int shift = 0;
1301           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1302           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1303           unsigned int byte;
1304           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1305           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1306           byte = ((vaddr & mask) ^ (bigend << shift));
1307           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1308         }
1309     }
1310   }
1311 }
1312
1313
1314 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1315 "lbu r<RT>, <OFFSET>(r<BASE>)"
1316 *mipsI:
1317 *mipsII:
1318 *mipsIII:
1319 *mipsIV:
1320 // start-sanitize-vr5400
1321 *vr5400:
1322 // end-sanitize-vr5400
1323 // start-sanitize-r5900
1324 *r5900:
1325 // end-sanitize-r5900
1326 *r3900:
1327 // start-sanitize-tx19
1328 *tx19:
1329 // end-sanitize-tx19
1330 {
1331   unsigned32 instruction = instruction_0;
1332   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1333   int destreg = ((instruction >> 16) & 0x0000001F);
1334   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1335   {
1336     address_word vaddr = ((unsigned64)op1 + offset);
1337     address_word paddr;
1338     int uncached;
1339     {
1340       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1341         {
1342           unsigned64 memval = 0;
1343           unsigned64 memval1 = 0;
1344           unsigned64 mask = 0x7;
1345           unsigned int shift = 0;
1346           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1347           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1348           unsigned int byte;
1349           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1350           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1351           byte = ((vaddr & mask) ^ (bigend << shift));
1352           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1353         }
1354     }
1355   }
1356 }
1357
1358
1359 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1360 "ld r<RT>, <OFFSET>(r<BASE>)"
1361 *mipsIII:
1362 *mipsIV:
1363 // start-sanitize-vr5400
1364 *vr5400:
1365 // end-sanitize-vr5400
1366 // start-sanitize-r5900
1367 *r5900:
1368 // end-sanitize-r5900
1369 *r3900:
1370 // start-sanitize-tx19
1371 *tx19:
1372 // end-sanitize-tx19
1373 {
1374   unsigned32 instruction = instruction_0;
1375   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1376   int destreg = ((instruction >> 16) & 0x0000001F);
1377   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1378   {
1379     address_word vaddr = ((unsigned64)op1 + offset);
1380     address_word paddr;
1381     int uncached;
1382     if ((vaddr & 7) != 0)
1383       SignalExceptionAddressLoad();
1384     else
1385       {
1386         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1387           {
1388             unsigned64 memval = 0;
1389             unsigned64 memval1 = 0;
1390             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1391             GPR[destreg] = memval;
1392           }
1393       }
1394   }
1395 }
1396
1397
1398 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1399 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1400 *mipsII:
1401 *mipsIII:
1402 *mipsIV:
1403 // start-sanitize-vr5400
1404 *vr5400:
1405 // end-sanitize-vr5400
1406 // start-sanitize-r5900
1407 *r5900:
1408 // end-sanitize-r5900
1409 *r3900:
1410 // start-sanitize-tx19
1411 *tx19:
1412 // end-sanitize-tx19
1413 {
1414   unsigned32 instruction = instruction_0;
1415   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1416   int destreg = ((instruction >> 16) & 0x0000001F);
1417   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1418   {
1419     address_word vaddr = ((unsigned64)op1 + offset);
1420     address_word paddr;
1421     int uncached;
1422     if ((vaddr & 7) != 0)
1423       SignalExceptionAddressLoad();
1424     else
1425       {
1426         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1427           {
1428             unsigned64 memval = 0;
1429             unsigned64 memval1 = 0;
1430             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1431             COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1432           }
1433       }
1434   }
1435 }
1436
1437
1438 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1439 "ldl r<RT>, <OFFSET>(r<BASE>)"
1440 *mipsIII:
1441 *mipsIV:
1442 // start-sanitize-vr5400
1443 *vr5400:
1444 // end-sanitize-vr5400
1445 // start-sanitize-r5900
1446 *r5900:
1447 // end-sanitize-r5900
1448 *r3900:
1449 // start-sanitize-tx19
1450 *tx19:
1451 // end-sanitize-tx19
1452 {
1453   unsigned32 instruction = instruction_0;
1454   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1455   int destreg = ((instruction >> 16) & 0x0000001F);
1456   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1457   {
1458     address_word vaddr = ((unsigned64)op1 + offset);
1459     address_word paddr;
1460     int uncached;
1461     {
1462       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1463         {
1464           unsigned64 memval = 0;
1465           unsigned64 memval1 = 0;
1466           unsigned64 mask = 7;
1467           unsigned int reverse = (ReverseEndian ? mask : 0);
1468           unsigned int bigend = (BigEndianCPU ? mask : 0);
1469           int byte;
1470           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1471           byte = ((vaddr & mask) ^ bigend);
1472           if (!!ByteSwapMem)
1473             paddr &= ~mask;
1474           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1475           GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1476         }
1477     }
1478   }
1479 }
1480
1481
1482 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1483 "ldr r<RT>, <OFFSET>(r<BASE>)"
1484 *mipsIII:
1485 *mipsIV:
1486 // start-sanitize-vr5400
1487 *vr5400:
1488 // end-sanitize-vr5400
1489 // start-sanitize-r5900
1490 *r5900:
1491 // end-sanitize-r5900
1492 *r3900:
1493 // start-sanitize-tx19
1494 *tx19:
1495 // end-sanitize-tx19
1496 {
1497   unsigned32 instruction = instruction_0;
1498   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1499   int destreg = ((instruction >> 16) & 0x0000001F);
1500   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1501   {
1502     address_word vaddr = ((unsigned64)op1 + offset);
1503     address_word paddr;
1504     int uncached;
1505     {
1506       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1507         {
1508           unsigned64 memval = 0;
1509           unsigned64 memval1 = 0;
1510           unsigned64 mask = 7;
1511           unsigned int reverse = (ReverseEndian ? mask : 0);
1512           unsigned int bigend = (BigEndianCPU ? mask : 0);
1513           int byte;
1514           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1515           byte = ((vaddr & mask) ^ bigend);
1516           if (!ByteSwapMem)
1517             paddr &= ~mask;
1518           LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1519           {
1520             unsigned64 srcmask;
1521             if (byte == 0)
1522               srcmask = 0;
1523             else
1524               srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1525             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1526           }
1527         }
1528     }
1529   }
1530 }
1531
1532
1533 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1534 "lh r<RT>, <OFFSET>(r<BASE>)"
1535 *mipsI:
1536 *mipsII:
1537 *mipsIII:
1538 *mipsIV:
1539 // start-sanitize-vr5400
1540 *vr5400:
1541 // end-sanitize-vr5400
1542 // start-sanitize-r5900
1543 *r5900:
1544 // end-sanitize-r5900
1545 *r3900:
1546 // start-sanitize-tx19
1547 *tx19:
1548 // end-sanitize-tx19
1549 {
1550   unsigned32 instruction = instruction_0;
1551   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1552   int destreg = ((instruction >> 16) & 0x0000001F);
1553   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1554   {
1555     address_word vaddr = ((unsigned64)op1 + offset);
1556     address_word paddr;
1557     int uncached;
1558     if ((vaddr & 1) != 0)
1559       SignalExceptionAddressLoad();
1560     else
1561       {
1562         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1563           {
1564             unsigned64 memval = 0;
1565             unsigned64 memval1 = 0;
1566             unsigned64 mask = 0x7;
1567             unsigned int shift = 1;
1568             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1569             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1570             unsigned int byte;
1571             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1572             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1573             byte = ((vaddr & mask) ^ (bigend << shift));
1574             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1575           }
1576       }
1577   }
1578 }
1579
1580
1581 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1582 "lhu r<RT>, <OFFSET>(r<BASE>)"
1583 *mipsI:
1584 *mipsII:
1585 *mipsIII:
1586 *mipsIV:
1587 // start-sanitize-vr5400
1588 *vr5400:
1589 // end-sanitize-vr5400
1590 // start-sanitize-r5900
1591 *r5900:
1592 // end-sanitize-r5900
1593 *r3900:
1594 // start-sanitize-tx19
1595 *tx19:
1596 // end-sanitize-tx19
1597 {
1598   unsigned32 instruction = instruction_0;
1599   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1600   int destreg = ((instruction >> 16) & 0x0000001F);
1601   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1602   {
1603     address_word vaddr = ((unsigned64)op1 + offset);
1604     address_word paddr;
1605     int uncached;
1606     if ((vaddr & 1) != 0)
1607       SignalExceptionAddressLoad();
1608     else
1609       {
1610         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1611           {
1612             unsigned64 memval = 0;
1613             unsigned64 memval1 = 0;
1614             unsigned64 mask = 0x7;
1615             unsigned int shift = 1;
1616             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1617             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1618             unsigned int byte;
1619             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1620             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1621             byte = ((vaddr & mask) ^ (bigend << shift));
1622             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1623           }
1624       }
1625   }
1626 }
1627
1628
1629 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1630 "ll r<RT>, <OFFSET>(r<BASE>)"
1631 *mipsII:
1632 *mipsIII:
1633 *mipsIV:
1634 // start-sanitize-vr5400
1635 *vr5400:
1636 // end-sanitize-vr5400
1637 // start-sanitize-r5900
1638 *r5900:
1639 // end-sanitize-r5900
1640 *r3900:
1641 // start-sanitize-tx19
1642 *tx19:
1643 // end-sanitize-tx19
1644 {
1645   unsigned32 instruction = instruction_0;
1646   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1647   int destreg = ((instruction >> 16) & 0x0000001F);
1648   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1649   {
1650     address_word vaddr = ((unsigned64)op1 + offset);
1651     address_word paddr;
1652     int uncached;
1653     if ((vaddr & 3) != 0)
1654       SignalExceptionAddressLoad();
1655     else
1656       {
1657         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1658           {
1659             unsigned64 memval = 0;
1660             unsigned64 memval1 = 0;
1661             unsigned64 mask = 0x7;
1662             unsigned int shift = 2;
1663             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1664             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1665             unsigned int byte;
1666             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1667             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1668             byte = ((vaddr & mask) ^ (bigend << shift));
1669             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1670             LLBIT = 1;
1671           }
1672       }
1673   }
1674 }
1675
1676
1677 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1678 "lld r<RT>, <OFFSET>(r<BASE>)"
1679 *mipsIII:
1680 *mipsIV:
1681 // start-sanitize-vr5400
1682 *vr5400:
1683 // end-sanitize-vr5400
1684 // start-sanitize-r5900
1685 *r5900:
1686 // end-sanitize-r5900
1687 *r3900:
1688 // start-sanitize-tx19
1689 *tx19:
1690 // end-sanitize-tx19
1691 {
1692   unsigned32 instruction = instruction_0;
1693   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1694   int destreg = ((instruction >> 16) & 0x0000001F);
1695   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1696   {
1697     address_word vaddr = ((unsigned64)op1 + offset);
1698     address_word paddr;
1699     int uncached;
1700     if ((vaddr & 7) != 0)
1701       SignalExceptionAddressLoad();
1702     else
1703       {
1704         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1705           {
1706             unsigned64 memval = 0;
1707             unsigned64 memval1 = 0;
1708             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1709             GPR[destreg] = memval;
1710             LLBIT = 1;
1711           }
1712       }
1713   }
1714 }
1715
1716
1717 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1718 "lui r<RT>, <IMMEDIATE>"
1719 *mipsI:
1720 *mipsII:
1721 *mipsIII:
1722 *mipsIV:
1723 // start-sanitize-vr5400
1724 *vr5400:
1725 // end-sanitize-vr5400
1726 // start-sanitize-r5900
1727 *r5900:
1728 // end-sanitize-r5900
1729 *r3900:
1730 // start-sanitize-tx19
1731 *tx19:
1732 // end-sanitize-tx19
1733 {
1734   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1735 }
1736
1737
1738 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1739 "lw r<RT>, <OFFSET>(r<BASE>)"
1740 *mipsI:
1741 *mipsII:
1742 *mipsIII:
1743 *mipsIV:
1744 // start-sanitize-vr5400
1745 *vr5400:
1746 // end-sanitize-vr5400
1747 // start-sanitize-r5900
1748 *r5900:
1749 // end-sanitize-r5900
1750 *r3900:
1751 // start-sanitize-tx19
1752 *tx19:
1753 // end-sanitize-tx19
1754 {
1755   unsigned32 instruction = instruction_0;
1756   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1757   int destreg = ((instruction >> 16) & 0x0000001F);
1758   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1759   {
1760     address_word vaddr = ((unsigned64)op1 + offset);
1761     address_word paddr;
1762     int uncached;
1763     if ((vaddr & 3) != 0)
1764       SignalExceptionAddressLoad();
1765     else
1766       {
1767         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1768           {
1769             unsigned64 memval = 0;
1770             unsigned64 memval1 = 0;
1771             unsigned64 mask = 0x7;
1772             unsigned int shift = 2;
1773             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1774             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1775             unsigned int byte;
1776             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1777             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1778             byte = ((vaddr & mask) ^ (bigend << shift));
1779             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1780           }
1781       }
1782   }
1783 }
1784
1785
1786 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1787 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1788 *mipsI:
1789 *mipsII:
1790 *mipsIII:
1791 *mipsIV:
1792 // start-sanitize-vr5400
1793 *vr5400:
1794 // end-sanitize-vr5400
1795 // start-sanitize-r5900
1796 *r5900:
1797 // end-sanitize-r5900
1798 *r3900:
1799 // start-sanitize-tx19
1800 *tx19:
1801 // end-sanitize-tx19
1802 {
1803   unsigned32 instruction = instruction_0;
1804   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1805   int destreg = ((instruction >> 16) & 0x0000001F);
1806   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1807   {
1808     address_word vaddr = ((unsigned64)op1 + offset);
1809     address_word paddr;
1810     int uncached;
1811     if ((vaddr & 3) != 0)
1812       SignalExceptionAddressLoad();
1813     else
1814       {
1815         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1816           {
1817             unsigned64 memval = 0;
1818             unsigned64 memval1 = 0;
1819             unsigned64 mask = 0x7;
1820             unsigned int shift = 2;
1821             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1822             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1823             unsigned int byte;
1824             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1825             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1826             byte = ((vaddr & mask) ^ (bigend << shift));
1827             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
1828           }
1829       }
1830   }
1831 }
1832
1833
1834 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1835 "lwl r<RT>, <OFFSET>(r<BASE>)"
1836 *mipsI:
1837 *mipsII:
1838 *mipsIII:
1839 *mipsIV:
1840 // start-sanitize-vr5400
1841 *vr5400:
1842 // end-sanitize-vr5400
1843 // start-sanitize-r5900
1844 *r5900:
1845 // end-sanitize-r5900
1846 *r3900:
1847 // start-sanitize-tx19
1848 *tx19:
1849 // end-sanitize-tx19
1850 {
1851   unsigned32 instruction = instruction_0;
1852   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1853   int destreg = ((instruction >> 16) & 0x0000001F);
1854   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1855   {
1856     address_word vaddr = ((unsigned64)op1 + offset);
1857     address_word paddr;
1858     int uncached;
1859     {
1860       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1861         {
1862           unsigned64 memval = 0;
1863           unsigned64 memval1 = 0;
1864           unsigned64 mask = 3;
1865           unsigned int reverse = (ReverseEndian ? mask : 0);
1866           unsigned int bigend = (BigEndianCPU ? mask : 0);
1867           int byte;
1868           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1869           byte = ((vaddr & mask) ^ bigend);
1870           if (!!ByteSwapMem)
1871             paddr &= ~mask;
1872           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1873           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1874             memval >>= 32;
1875           }
1876           GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
1877           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1878         }
1879     }
1880   }
1881 }
1882
1883
1884 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1885 "lwr r<RT>, <OFFSET>(r<BASE>)"
1886 *mipsI:
1887 *mipsII:
1888 *mipsIII:
1889 *mipsIV:
1890 // start-sanitize-vr5400
1891 *vr5400:
1892 // end-sanitize-vr5400
1893 // start-sanitize-r5900
1894 *r5900:
1895 // end-sanitize-r5900
1896 *r3900:
1897 // start-sanitize-tx19
1898 *tx19:
1899 // end-sanitize-tx19
1900 {
1901   unsigned32 instruction = instruction_0;
1902   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1903   int destreg = ((instruction >> 16) & 0x0000001F);
1904   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1905   {
1906     address_word vaddr = ((unsigned64)op1 + offset);
1907     address_word paddr;
1908     int uncached;
1909     {
1910       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1911         {
1912           unsigned64 memval = 0;
1913           unsigned64 memval1 = 0;
1914           unsigned64 mask = 3;
1915           unsigned int reverse = (ReverseEndian ? mask : 0);
1916           unsigned int bigend = (BigEndianCPU ? mask : 0);
1917           int byte;
1918           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1919           byte = ((vaddr & mask) ^ bigend);
1920           if (!ByteSwapMem)
1921             paddr &= ~mask;
1922           LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
1923           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1924             memval >>= 32;
1925           }
1926           {
1927             unsigned64 srcmask;
1928             if (byte == 0)
1929               srcmask = 0;
1930             else
1931               srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
1932             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1933           }
1934           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1935         }
1936     }
1937   }
1938 }
1939
1940
1941 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1942 "lwu r<RT>, <OFFSET>(r<BASE>)"
1943 *mipsIII:
1944 *mipsIV:
1945 // start-sanitize-vr5400
1946 *vr5400:
1947 // end-sanitize-vr5400
1948 // start-sanitize-r5900
1949 *r5900:
1950 // end-sanitize-r5900
1951 *r3900:
1952 // start-sanitize-tx19
1953 *tx19:
1954 // end-sanitize-tx19
1955 {
1956   unsigned32 instruction = instruction_0;
1957   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1958   int destreg = ((instruction >> 16) & 0x0000001F);
1959   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1960   {
1961     address_word vaddr = ((unsigned64)op1 + offset);
1962     address_word paddr;
1963     int uncached;
1964     if ((vaddr & 3) != 0)
1965       SignalExceptionAddressLoad();
1966     else
1967       {
1968         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1969           {
1970             unsigned64 memval = 0;
1971             unsigned64 memval1 = 0;
1972             unsigned64 mask = 0x7;
1973             unsigned int shift = 2;
1974             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1975             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1976             unsigned int byte;
1977             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1978             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1979             byte = ((vaddr & mask) ^ (bigend << shift));
1980             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
1981           }
1982       }
1983   }
1984 }
1985
1986
1987 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1988 "mfhi r<RD>"
1989 *mipsI:
1990 *mipsII:
1991 *mipsIII:
1992 *mipsIV:
1993 // start-sanitize-vr5400
1994 *vr5400:
1995 // end-sanitize-vr5400
1996 // start-sanitize-r5900
1997 *r5900:
1998 // end-sanitize-r5900
1999 *r3900:
2000 // start-sanitize-tx19
2001 *tx19:
2002 // end-sanitize-tx19
2003 {
2004   GPR[RD] = HI;
2005   HIACCESS = 3;
2006 }
2007
2008
2009 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2010 "mflo r<RD>"
2011 *mipsI:
2012 *mipsII:
2013 *mipsIII:
2014 *mipsIV:
2015 // start-sanitize-vr5400
2016 *vr5400:
2017 // end-sanitize-vr5400
2018 // start-sanitize-r5900
2019 *r5900:
2020 // end-sanitize-r5900
2021 *r3900:
2022 // start-sanitize-tx19
2023 *tx19:
2024 // end-sanitize-tx19
2025 {
2026   GPR[RD] = LO;
2027   LOACCESS = 3; /* 3rd instruction will be safe */
2028 }
2029
2030
2031 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2032 "movn r<RD>, r<RS>, r<RT>"
2033 *mipsIV:
2034 // start-sanitize-vr5400
2035 *vr5400:
2036 // end-sanitize-vr5400
2037 // start-sanitize-r5900
2038 *r5900:
2039 // end-sanitize-r5900
2040 {
2041   if (GPR[RT] != 0)
2042     GPR[RD] = GPR[RS];
2043 }
2044
2045
2046 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2047 "movz r<RD>, r<RS>, r<RT>"
2048 *mipsIV:
2049 // start-sanitize-vr5400
2050 *vr5400:
2051 // end-sanitize-vr5400
2052 // start-sanitize-r5900
2053 *r5900:
2054 // end-sanitize-r5900
2055 {
2056   if (GPR[RT] == 0)
2057     GPR[RD] = GPR[RS];
2058 }
2059
2060
2061 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2062 "mthi r<RS>"
2063 *mipsI:
2064 *mipsII:
2065 *mipsIII:
2066 *mipsIV:
2067 // start-sanitize-vr5400
2068 *vr5400:
2069 // end-sanitize-vr5400
2070 // start-sanitize-r5900
2071 *r5900:
2072 // end-sanitize-r5900
2073 *r3900:
2074 // start-sanitize-tx19
2075 *tx19:
2076 // end-sanitize-tx19
2077 {
2078   if (HIACCESS != 0)
2079     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2080   HI = GPR[RS];
2081   HIACCESS = 3; /* 3rd instruction will be safe */
2082 }
2083
2084
2085 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2086 "mtlo r<RS>"
2087 *mipsI:
2088 *mipsII:
2089 *mipsIII:
2090 *mipsIV:
2091 // start-sanitize-vr5400
2092 *vr5400:
2093 // end-sanitize-vr5400
2094 // start-sanitize-r5900
2095 *r5900:
2096 // end-sanitize-r5900
2097 *r3900:
2098 // start-sanitize-tx19
2099 *tx19:
2100 // end-sanitize-tx19
2101 {
2102   if (LOACCESS != 0)
2103     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2104   LO = GPR[RS];
2105   LOACCESS = 3; /* 3rd instruction will be safe */
2106 }
2107
2108
2109 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2110 "mult r<RS>, r<RT>"
2111 *mipsI:
2112 *mipsII:
2113 *mipsIII:
2114 *mipsIV:
2115 // start-sanitize-vr5400
2116 *vr5400:
2117 // end-sanitize-vr5400
2118 // start-sanitize-r5900
2119 *r5900:
2120 // end-sanitize-r5900
2121 *r3900:
2122 // start-sanitize-tx19
2123 *tx19:
2124 // end-sanitize-tx19
2125 {
2126   signed64 prod;
2127   CHECKHILO ("Multiplication");
2128   prod = (((signed64)(signed32) GPR[RS])
2129           * ((signed64)(signed32) GPR[RT]));
2130   LO = EXTEND32 (VL4_8 (prod));
2131   HI = EXTEND32 (VH4_8 (prod));
2132 }
2133
2134
2135 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2136 "multu r<RS>, r<RT>"
2137 *mipsI:
2138 *mipsII:
2139 *mipsIII:
2140 *mipsIV:
2141 // start-sanitize-vr5400
2142 *vr5400:
2143 // end-sanitize-vr5400
2144 // start-sanitize-r5900
2145 *r5900:
2146 // end-sanitize-r5900
2147 *r3900:
2148 // start-sanitize-tx19
2149 *tx19:
2150 // end-sanitize-tx19
2151 {
2152   unsigned64 prod;
2153   CHECKHILO ("Multiplication");
2154   prod = (((unsigned64)(unsigned32) GPR[RS])
2155           * ((unsigned64)(unsigned32) GPR[RT]));
2156   LO = EXTEND32 (VL4_8 (prod));
2157   HI = EXTEND32 (VH4_8 (prod));
2158 }
2159
2160
2161 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2162 "nor r<RD>, r<RS>, r<RT>"
2163 *mipsI:
2164 *mipsII:
2165 *mipsIII:
2166 *mipsIV:
2167 // start-sanitize-vr5400
2168 *vr5400:
2169 // end-sanitize-vr5400
2170 // start-sanitize-r5900
2171 *r5900:
2172 // end-sanitize-r5900
2173 *r3900:
2174 // start-sanitize-tx19
2175 *tx19:
2176 // end-sanitize-tx19
2177 {
2178   GPR[RD] = ~ (GPR[RS] | GPR[RT]);
2179 }
2180
2181
2182 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2183 "or r<RD>, r<RS>, r<RT>"
2184 *mipsI:
2185 *mipsII:
2186 *mipsIII:
2187 *mipsIV:
2188 // start-sanitize-vr5400
2189 *vr5400:
2190 // end-sanitize-vr5400
2191 // start-sanitize-r5900
2192 *r5900:
2193 // end-sanitize-r5900
2194 *r3900:
2195 // start-sanitize-tx19
2196 *tx19:
2197 // end-sanitize-tx19
2198 {
2199   GPR[RD] = (GPR[RS] | GPR[RT]);
2200 }
2201
2202
2203 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2204 "ori r<RT>, r<RS>, <IMMEDIATE>"
2205 *mipsI:
2206 *mipsII:
2207 *mipsIII:
2208 *mipsIV:
2209 // start-sanitize-vr5400
2210 *vr5400:
2211 // end-sanitize-vr5400
2212 // start-sanitize-r5900
2213 *r5900:
2214 // end-sanitize-r5900
2215 *r3900:
2216 // start-sanitize-tx19
2217 *tx19:
2218 // end-sanitize-tx19
2219 {
2220   GPR[RT] = (GPR[RS] | IMMEDIATE);
2221 }
2222
2223
2224 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2225 *mipsIV:
2226 // start-sanitize-vr5400
2227 *vr5400:
2228 // end-sanitize-vr5400
2229 // start-sanitize-r5900
2230 *r5900:
2231 // end-sanitize-r5900
2232 {
2233   unsigned32 instruction = instruction_0;
2234   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2235   int hint = ((instruction >> 16) & 0x0000001F);
2236   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2237   {
2238     address_word vaddr = ((unsigned64)op1 + offset);
2239     address_word paddr;
2240     int uncached;
2241     {
2242       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2243         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2244     }
2245   }
2246 }
2247
2248 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2249 "sb r<RT>, <OFFSET>(r<BASE>)"
2250 *mipsI:
2251 *mipsII:
2252 *mipsIII:
2253 *mipsIV:
2254 // start-sanitize-vr5400
2255 *vr5400:
2256 // end-sanitize-vr5400
2257 // start-sanitize-r5900
2258 *r5900:
2259 // end-sanitize-r5900
2260 *r3900:
2261 // start-sanitize-tx19
2262 *tx19:
2263 // end-sanitize-tx19
2264 {
2265   unsigned32 instruction = instruction_0;
2266   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2267   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2268   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2269   {
2270     address_word vaddr = ((unsigned64)op1 + offset);
2271     address_word paddr;
2272     int uncached;
2273     {
2274       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2275         {
2276           unsigned64 memval = 0;
2277           unsigned64 memval1 = 0;
2278           unsigned64 mask = 0x7;
2279           unsigned int shift = 0;
2280           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2281           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2282           unsigned int byte;
2283           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2284           byte = ((vaddr & mask) ^ (bigend << shift));
2285           memval = ((unsigned64) op2 << (8 * byte));
2286           {
2287             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2288           }
2289         }
2290     }
2291   }
2292 }
2293
2294
2295 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2296 "sc r<RT>, <OFFSET>(r<BASE>)"
2297 *mipsII:
2298 *mipsIII:
2299 *mipsIV:
2300 // start-sanitize-vr5400
2301 *vr5400:
2302 // end-sanitize-vr5400
2303 // start-sanitize-r5900
2304 *r5900:
2305 // end-sanitize-r5900
2306 *r3900:
2307 // start-sanitize-tx19
2308 *tx19:
2309 // end-sanitize-tx19
2310 {
2311   unsigned32 instruction = instruction_0;
2312   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2313   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2314   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2315   {
2316     address_word vaddr = ((unsigned64)op1 + offset);
2317     address_word paddr;
2318     int uncached;
2319     if ((vaddr & 3) != 0)
2320       SignalExceptionAddressStore();
2321     else
2322       {
2323         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2324           {
2325             unsigned64 memval = 0;
2326             unsigned64 memval1 = 0;
2327             unsigned64 mask = 0x7;
2328             unsigned int byte;
2329             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2330             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2331             memval = ((unsigned64) op2 << (8 * byte));
2332             if (LLBIT)
2333               {
2334                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2335               }
2336             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2337           }
2338       }
2339   }
2340 }
2341
2342
2343 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2344 "scd r<RT>, <OFFSET>(r<BASE>)"
2345 *mipsIII:
2346 *mipsIV:
2347 // start-sanitize-vr5400
2348 *vr5400:
2349 // end-sanitize-vr5400
2350 // start-sanitize-r5900
2351 *r5900:
2352 // end-sanitize-r5900
2353 *r3900:
2354 // start-sanitize-tx19
2355 *tx19:
2356 // end-sanitize-tx19
2357 {
2358   unsigned32 instruction = instruction_0;
2359   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2360   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2361   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2362   {
2363     address_word vaddr = ((unsigned64)op1 + offset);
2364     address_word paddr;
2365     int uncached;
2366     if ((vaddr & 7) != 0)
2367       SignalExceptionAddressStore();
2368     else
2369       {
2370         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2371           {
2372             unsigned64 memval = 0;
2373             unsigned64 memval1 = 0;
2374             memval = op2;
2375             if (LLBIT)
2376               {
2377                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2378               }
2379             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2380           }
2381       }
2382   }
2383 }
2384
2385
2386 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2387 "sd r<RT>, <OFFSET>(r<BASE>)"
2388 *mipsIII:
2389 *mipsIV:
2390 // start-sanitize-vr5400
2391 *vr5400:
2392 // end-sanitize-vr5400
2393 // start-sanitize-r5900
2394 *r5900:
2395 // end-sanitize-r5900
2396 *r3900:
2397 // start-sanitize-tx19
2398 *tx19:
2399 // end-sanitize-tx19
2400 {
2401   unsigned32 instruction = instruction_0;
2402   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2403   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2404   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2405   {
2406     address_word vaddr = ((unsigned64)op1 + offset);
2407     address_word paddr;
2408     int uncached;
2409     if ((vaddr & 7) != 0)
2410       SignalExceptionAddressStore();
2411     else
2412       {
2413         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2414           {
2415             unsigned64 memval = 0;
2416             unsigned64 memval1 = 0;
2417             memval = op2;
2418             {
2419               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2420             }
2421           }
2422       }
2423   }
2424 }
2425
2426
2427 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2428 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2429 *mipsII:
2430 *mipsIII:
2431 *mipsIV:
2432 // start-sanitize-vr5400
2433 *vr5400:
2434 // end-sanitize-vr5400
2435 // start-sanitize-r5900
2436 *r5900:
2437 // end-sanitize-r5900
2438 *r3900:
2439 // start-sanitize-tx19
2440 *tx19:
2441 // end-sanitize-tx19
2442 {
2443   unsigned32 instruction = instruction_0;
2444   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2445   int destreg = ((instruction >> 16) & 0x0000001F);
2446   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2447   {
2448     address_word vaddr = ((unsigned64)op1 + offset);
2449     address_word paddr;
2450     int uncached;
2451     if ((vaddr & 7) != 0)
2452       SignalExceptionAddressStore();
2453     else
2454       {
2455         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2456           {
2457             unsigned64 memval = 0;
2458             unsigned64 memval1 = 0;
2459             memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2460             {
2461               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2462             }
2463           }
2464       }
2465   }
2466 }
2467
2468
2469 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2470 "sdl r<RT>, <OFFSET>(r<BASE>)"
2471 *mipsIII:
2472 *mipsIV:
2473 // start-sanitize-vr5400
2474 *vr5400:
2475 // end-sanitize-vr5400
2476 // start-sanitize-r5900
2477 *r5900:
2478 // end-sanitize-r5900
2479 *r3900:
2480 // start-sanitize-tx19
2481 *tx19:
2482 // end-sanitize-tx19
2483 {
2484   unsigned32 instruction = instruction_0;
2485   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2486   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2487   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2488   {
2489     address_word vaddr = ((unsigned64)op1 + offset);
2490     address_word paddr;
2491     int uncached;
2492     {
2493       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2494         {
2495           unsigned64 memval = 0;
2496           unsigned64 memval1 = 0;
2497           unsigned64 mask = 7;
2498           unsigned int reverse = (ReverseEndian ? mask : 0);
2499           unsigned int bigend = (BigEndianCPU ? mask : 0);
2500           int byte;
2501           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2502           byte = ((vaddr & mask) ^ bigend);
2503           if (!!ByteSwapMem)
2504             paddr &= ~mask;
2505           memval = (op2 >> (8 * (7 - byte)));
2506           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2507         }
2508     }
2509   }
2510 }
2511
2512
2513 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2514 "sdr r<RT>, <OFFSET>(r<BASE>)"
2515 *mipsIII:
2516 *mipsIV:
2517 // start-sanitize-vr5400
2518 *vr5400:
2519 // end-sanitize-vr5400
2520 // start-sanitize-r5900
2521 *r5900:
2522 // end-sanitize-r5900
2523 *r3900:
2524 // start-sanitize-tx19
2525 *tx19:
2526 // end-sanitize-tx19
2527 {
2528   unsigned32 instruction = instruction_0;
2529   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2530   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2531   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2532   {
2533     address_word vaddr = ((unsigned64)op1 + offset);
2534     address_word paddr;
2535     int uncached;
2536     {
2537       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2538         {
2539           unsigned64 memval = 0;
2540           unsigned64 memval1 = 0;
2541           unsigned64 mask = 7;
2542           unsigned int reverse = (ReverseEndian ? mask : 0);
2543           unsigned int bigend = (BigEndianCPU ? mask : 0);
2544           int byte;
2545           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2546           byte = ((vaddr & mask) ^ bigend);
2547           if (!ByteSwapMem)
2548             paddr &= ~mask;
2549           memval = ((unsigned64) op2 << (byte * 8));
2550           StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
2551         }
2552     }
2553   }
2554 }
2555
2556
2557 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2558 "sh r<RT>, <OFFSET>(r<BASE>)"
2559 *mipsI:
2560 *mipsII:
2561 *mipsIII:
2562 *mipsIV:
2563 // start-sanitize-vr5400
2564 *vr5400:
2565 // end-sanitize-vr5400
2566 // start-sanitize-r5900
2567 *r5900:
2568 // end-sanitize-r5900
2569 *r3900:
2570 // start-sanitize-tx19
2571 *tx19:
2572 // end-sanitize-tx19
2573 {
2574   unsigned32 instruction = instruction_0;
2575   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2576   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2577   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2578   {
2579     address_word vaddr = ((unsigned64)op1 + offset);
2580     address_word paddr;
2581     int uncached;
2582     if ((vaddr & 1) != 0)
2583       SignalExceptionAddressStore();
2584     else
2585       {
2586         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2587           {
2588             unsigned64 memval = 0;
2589             unsigned64 memval1 = 0;
2590             unsigned64 mask = 0x7;
2591             unsigned int shift = 1;
2592             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2593             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2594             unsigned int byte;
2595             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2596             byte = ((vaddr & mask) ^ (bigend << shift));
2597             memval = ((unsigned64) op2 << (8 * byte));
2598             {
2599               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2600             }
2601           }
2602       }
2603   }
2604 }
2605
2606
2607 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2608 "sll r<RD>, r<RT>, <SHIFT>"
2609 *mipsI:
2610 *mipsII:
2611 *mipsIII:
2612 *mipsIV:
2613 // start-sanitize-vr5400
2614 *vr5400:
2615 // end-sanitize-vr5400
2616 // start-sanitize-r5900
2617 *r5900:
2618 // end-sanitize-r5900
2619 *r3900:
2620 // start-sanitize-tx19
2621 *tx19:
2622 // end-sanitize-tx19
2623 {
2624   int s = SHIFT;
2625   unsigned32 temp = (GPR[RT] << s);
2626   GPR[RD] = EXTEND32 (temp);
2627 }
2628
2629
2630 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2631 "sllv r<RD>, r<RT>, r<RS>"
2632 *mipsI:
2633 *mipsII:
2634 *mipsIII:
2635 *mipsIV:
2636 // start-sanitize-vr5400
2637 *vr5400:
2638 // end-sanitize-vr5400
2639 // start-sanitize-r5900
2640 *r5900:
2641 // end-sanitize-r5900
2642 *r3900:
2643 // start-sanitize-tx19
2644 *tx19:
2645 // end-sanitize-tx19
2646 {
2647   int s = MASKED (GPR[RS], 4, 0);
2648   unsigned32 temp = (GPR[RT] << s);
2649   GPR[RD] = EXTEND32 (temp);
2650 }
2651
2652
2653 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2654 "slt r<RD>, r<RS>, r<RT>"
2655 *mipsI:
2656 *mipsII:
2657 *mipsIII:
2658 *mipsIV:
2659 // start-sanitize-vr5400
2660 *vr5400:
2661 // end-sanitize-vr5400
2662 // start-sanitize-r5900
2663 *r5900:
2664 // end-sanitize-r5900
2665 *r3900:
2666 // start-sanitize-tx19
2667 *tx19:
2668 // end-sanitize-tx19
2669 {
2670   GPR[RD] = (GPR[RS] < GPR[RT]);
2671 }
2672
2673
2674 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2675 "slti r<RT>, r<RS>, <IMMEDIATE>"
2676 *mipsI:
2677 *mipsII:
2678 *mipsIII:
2679 *mipsIV:
2680 // start-sanitize-vr5400
2681 *vr5400:
2682 // end-sanitize-vr5400
2683 // start-sanitize-r5900
2684 *r5900:
2685 // end-sanitize-r5900
2686 *r3900:
2687 // start-sanitize-tx19
2688 *tx19:
2689 // end-sanitize-tx19
2690 {
2691   GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE));
2692 }
2693
2694
2695 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2696 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2697 *mipsI:
2698 *mipsII:
2699 *mipsIII:
2700 *mipsIV:
2701 // start-sanitize-vr5400
2702 *vr5400:
2703 // end-sanitize-vr5400
2704 // start-sanitize-r5900
2705 *r5900:
2706 // end-sanitize-r5900
2707 *r3900:
2708 // start-sanitize-tx19
2709 *tx19:
2710 // end-sanitize-tx19
2711 {
2712   GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
2713 }
2714
2715 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2716 "sltu r<RD>, r<RS>, r<RT>"
2717 *mipsI:
2718 *mipsII:
2719 *mipsIII:
2720 *mipsIV:
2721 // start-sanitize-vr5400
2722 *vr5400:
2723 // end-sanitize-vr5400
2724 // start-sanitize-r5900
2725 *r5900:
2726 // end-sanitize-r5900
2727 *r3900:
2728 // start-sanitize-tx19
2729 *tx19:
2730 // end-sanitize-tx19
2731 {
2732   GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
2733 }
2734
2735
2736 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2737 "sra r<RD>, r<RT>, <SHIFT>"
2738 *mipsI:
2739 *mipsII:
2740 *mipsIII:
2741 *mipsIV:
2742 // start-sanitize-vr5400
2743 *vr5400:
2744 // end-sanitize-vr5400
2745 // start-sanitize-r5900
2746 *r5900:
2747 // end-sanitize-r5900
2748 *r3900:
2749 // start-sanitize-tx19
2750 *tx19:
2751 // end-sanitize-tx19
2752 {
2753   int s = SHIFT;
2754   signed32 temp = (signed32) GPR[RT] >> s;
2755   GPR[RD] = EXTEND32 (temp);
2756 }
2757
2758
2759 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2760 "srav r<RD>, r<RT>, r<RS>"
2761 *mipsI:
2762 *mipsII:
2763 *mipsIII:
2764 *mipsIV:
2765 // start-sanitize-vr5400
2766 *vr5400:
2767 // end-sanitize-vr5400
2768 // start-sanitize-r5900
2769 *r5900:
2770 // end-sanitize-r5900
2771 *r3900:
2772 // start-sanitize-tx19
2773 *tx19:
2774 // end-sanitize-tx19
2775 {
2776   int s = MASKED (GPR[RS], 4, 0);
2777   signed32 temp = (signed32) GPR[RT] >> s;
2778   GPR[RD] = EXTEND32 (temp);
2779 }
2780
2781
2782 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2783 "srl r<RD>, r<RT>, <SHIFT>"
2784 *mipsI:
2785 *mipsII:
2786 *mipsIII:
2787 *mipsIV:
2788 // start-sanitize-vr5400
2789 *vr5400:
2790 // end-sanitize-vr5400
2791 // start-sanitize-r5900
2792 *r5900:
2793 // end-sanitize-r5900
2794 *r3900:
2795 // start-sanitize-tx19
2796 *tx19:
2797 // end-sanitize-tx19
2798 {
2799   int s = SHIFT;
2800   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2801   GPR[RD] = EXTEND32 (temp);
2802 }
2803
2804
2805 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2806 "srlv r<RD>, r<RT>, r<RS>"
2807 *mipsI:
2808 *mipsII:
2809 *mipsIII:
2810 *mipsIV:
2811 // start-sanitize-vr5400
2812 *vr5400:
2813 // end-sanitize-vr5400
2814 // start-sanitize-r5900
2815 *r5900:
2816 // end-sanitize-r5900
2817 *r3900:
2818 // start-sanitize-tx19
2819 *tx19:
2820 // end-sanitize-tx19
2821 {
2822   int s = MASKED (GPR[RS], 4, 0);
2823   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2824   GPR[RD] = EXTEND32 (temp);
2825 }
2826
2827
2828 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2829 "sub r<RD>, r<RS>, r<RT>"
2830 *mipsI:
2831 *mipsII:
2832 *mipsIII:
2833 *mipsIV:
2834 // start-sanitize-vr5400
2835 *vr5400:
2836 // end-sanitize-vr5400
2837 // start-sanitize-r5900
2838 *r5900:
2839 // end-sanitize-r5900
2840 *r3900:
2841 // start-sanitize-tx19
2842 *tx19:
2843 // end-sanitize-tx19
2844 {
2845   ALU32_BEGIN (GPR[RS]);
2846   ALU32_SUB (GPR[RT]);
2847   ALU32_END (GPR[RD]);
2848 }
2849
2850
2851 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2852 "subu r<RD>, r<RS>, r<RT>"
2853 *mipsI:
2854 *mipsII:
2855 *mipsIII:
2856 *mipsIV:
2857 // start-sanitize-vr5400
2858 *vr5400:
2859 // end-sanitize-vr5400
2860 // start-sanitize-r5900
2861 *r5900:
2862 // end-sanitize-r5900
2863 *r3900:
2864 // start-sanitize-tx19
2865 *tx19:
2866 // end-sanitize-tx19
2867 {
2868   GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
2869 }
2870
2871
2872 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2873 "sw r<RT>, <OFFSET>(r<BASE>)"
2874 *mipsI:
2875 *mipsII:
2876 *mipsIII:
2877 *mipsIV:
2878 // start-sanitize-vr5400
2879 *vr5400:
2880 // end-sanitize-vr5400
2881 // start-sanitize-r5900
2882 *r5900:
2883 // end-sanitize-r5900
2884 *r3900:
2885 // start-sanitize-tx19
2886 *tx19:
2887 // end-sanitize-tx19
2888 {
2889   unsigned32 instruction = instruction_0;
2890   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2891   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2892   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2893   {
2894     address_word vaddr = ((unsigned64)op1 + offset);
2895     address_word paddr;
2896     int uncached;
2897     if ((vaddr & 3) != 0)
2898       SignalExceptionAddressStore();
2899     else
2900       {
2901         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2902           {
2903             unsigned64 memval = 0;
2904             unsigned64 memval1 = 0;
2905             unsigned64 mask = 0x7;
2906             unsigned int byte;
2907             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2908             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2909             memval = ((unsigned64) op2 << (8 * byte));
2910             {
2911               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2912             }
2913           }
2914       }
2915   }
2916 }
2917
2918
2919 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2920 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2921 *mipsI:
2922 *mipsII:
2923 *mipsIII:
2924 *mipsIV:
2925 // start-sanitize-vr5400
2926 *vr5400:
2927 // end-sanitize-vr5400
2928 // start-sanitize-r5900
2929 *r5900:
2930 // end-sanitize-r5900
2931 *r3900:
2932 // start-sanitize-tx19
2933 *tx19:
2934 // end-sanitize-tx19
2935 {
2936   unsigned32 instruction = instruction_0;
2937   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2938   int destreg = ((instruction >> 16) & 0x0000001F);
2939   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2940   {
2941     address_word vaddr = ((unsigned64)op1 + offset);
2942     address_word paddr;
2943     int uncached;
2944     if ((vaddr & 3) != 0)
2945       SignalExceptionAddressStore();
2946     else
2947       {
2948         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2949           {
2950             unsigned64 memval = 0;
2951             unsigned64 memval1 = 0;
2952             unsigned64 mask = 0x7;
2953             unsigned int byte;
2954             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2955             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2956             memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2957             {
2958               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2959             }
2960           }
2961       }
2962   }
2963 }
2964
2965
2966 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2967 "swl r<RT>, <OFFSET>(r<BASE>)"
2968 *mipsI:
2969 *mipsII:
2970 *mipsIII:
2971 *mipsIV:
2972 // start-sanitize-vr5400
2973 *vr5400:
2974 // end-sanitize-vr5400
2975 // start-sanitize-r5900
2976 *r5900:
2977 // end-sanitize-r5900
2978 *r3900:
2979 // start-sanitize-tx19
2980 *tx19:
2981 // end-sanitize-tx19
2982 {
2983   unsigned32 instruction = instruction_0;
2984   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2985   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2986   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2987   {
2988     address_word vaddr = ((unsigned64)op1 + offset);
2989     address_word paddr;
2990     int uncached;
2991     {
2992       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2993         {
2994           unsigned64 memval = 0;
2995           unsigned64 memval1 = 0;
2996           unsigned64 mask = 3;
2997           unsigned int reverse = (ReverseEndian ? mask : 0);
2998           unsigned int bigend = (BigEndianCPU ? mask : 0);
2999           int byte;
3000           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3001           byte = ((vaddr & mask) ^ bigend);
3002           if (!!ByteSwapMem)
3003             paddr &= ~mask;
3004           memval = (op2 >> (8 * (3 - byte)));
3005           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3006             memval <<= 32;
3007           }
3008           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
3009         }
3010     }
3011   }
3012 }
3013
3014
3015 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3016 "swr r<RT>, <OFFSET>(r<BASE>)"
3017 *mipsI:
3018 *mipsII:
3019 *mipsIII:
3020 *mipsIV:
3021 // start-sanitize-vr5400
3022 *vr5400:
3023 // end-sanitize-vr5400
3024 // start-sanitize-r5900
3025 *r5900:
3026 // end-sanitize-r5900
3027 *r3900:
3028 // start-sanitize-tx19
3029 *tx19:
3030 // end-sanitize-tx19
3031 {
3032   unsigned32 instruction = instruction_0;
3033   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3034   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3035   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3036   {
3037     address_word vaddr = ((unsigned64)op1 + offset);
3038     address_word paddr;
3039     int uncached;
3040     {
3041       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3042         {
3043           unsigned64 memval = 0;
3044           unsigned64 memval1 = 0;
3045           unsigned64 mask = 3;
3046           unsigned int reverse = (ReverseEndian ? mask : 0);
3047           unsigned int bigend = (BigEndianCPU ? mask : 0);
3048           int byte;
3049           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3050           byte = ((vaddr & mask) ^ bigend);
3051           if (!ByteSwapMem)
3052             paddr &= ~mask;
3053           memval = ((unsigned64) op2 << (byte * 8));
3054           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3055             memval <<= 32;
3056           }
3057           StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
3058         }
3059     }
3060   }
3061 }
3062
3063
3064 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3065 "sync":STYPE == 0
3066 "sync <STYPE>"
3067 *mipsII:
3068 *mipsIII:
3069 *mipsIV:
3070 // start-sanitize-vr5400
3071 *vr5400:
3072 // end-sanitize-vr5400
3073 // start-sanitize-r5900
3074 *r5900:
3075 // end-sanitize-r5900
3076 *r3900:
3077 // start-sanitize-tx19
3078 *tx19:
3079 // end-sanitize-tx19
3080 {
3081   SyncOperation (STYPE);
3082 }
3083
3084
3085 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3086 "syscall <CODE>"
3087 *mipsI:
3088 *mipsII:
3089 *mipsIII:
3090 *mipsIV:
3091 // start-sanitize-vr5400
3092 *vr5400:
3093 // end-sanitize-vr5400
3094 // start-sanitize-r5900
3095 *r5900:
3096 // end-sanitize-r5900
3097 *r3900:
3098 // start-sanitize-tx19
3099 *tx19:
3100 // end-sanitize-tx19
3101 {
3102   SignalException(SystemCall, instruction_0);
3103 }
3104
3105
3106 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3107 "teq r<RS>, r<RT>"
3108 *mipsII:
3109 *mipsIII:
3110 *mipsIV:
3111 // start-sanitize-vr5400
3112 *vr5400:
3113 // end-sanitize-vr5400
3114 // start-sanitize-r5900
3115 *r5900:
3116 // end-sanitize-r5900
3117 *r3900:
3118 // start-sanitize-tx19
3119 *tx19:
3120 // end-sanitize-tx19
3121 {
3122   if (GPR[RS] == GPR[RT])
3123     SignalException(Trap, instruction_0);
3124 }
3125
3126
3127 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3128 "teqi r<RS>, <IMMEDIATE>"
3129 *mipsII:
3130 *mipsIII:
3131 *mipsIV:
3132 // start-sanitize-vr5400
3133 *vr5400:
3134 // end-sanitize-vr5400
3135 // start-sanitize-r5900
3136 *r5900:
3137 // end-sanitize-r5900
3138 *r3900:
3139 // start-sanitize-tx19
3140 *tx19:
3141 // end-sanitize-tx19
3142 {
3143   if (GPR[RS] == EXTEND16 (IMMEDIATE))
3144     SignalException(Trap, instruction_0);
3145 }
3146
3147
3148 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3149 "tge r<RS>, r<RT>"
3150 *mipsII:
3151 *mipsIII:
3152 *mipsIV:
3153 // start-sanitize-vr5400
3154 *vr5400:
3155 // end-sanitize-vr5400
3156 // start-sanitize-r5900
3157 *r5900:
3158 // end-sanitize-r5900
3159 *r3900:
3160 // start-sanitize-tx19
3161 *tx19:
3162 // end-sanitize-tx19
3163 {
3164   if (GPR[RS] >= GPR[RT])
3165     SignalException(Trap, instruction_0);
3166 }
3167
3168
3169 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3170 "tgei r<RS>, <IMMEDIATE>"
3171 *mipsII:
3172 *mipsIII:
3173 *mipsIV:
3174 // start-sanitize-vr5400
3175 *vr5400:
3176 // end-sanitize-vr5400
3177 // start-sanitize-r5900
3178 *r5900:
3179 // end-sanitize-r5900
3180 *r3900:
3181 // start-sanitize-tx19
3182 *tx19:
3183 // end-sanitize-tx19
3184 {
3185   if (GPR[RS] >= EXTEND16 (IMMEDIATE))
3186     SignalException(Trap, instruction_0);
3187 }
3188
3189
3190 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3191 "tgeiu r<RS>, <IMMEDIATE>"
3192 *mipsII:
3193 *mipsIII:
3194 *mipsIV:
3195 // start-sanitize-vr5400
3196 *vr5400:
3197 // end-sanitize-vr5400
3198 // start-sanitize-r5900
3199 *r5900:
3200 // end-sanitize-r5900
3201 *r3900:
3202 // start-sanitize-tx19
3203 *tx19:
3204 // end-sanitize-tx19
3205 {
3206   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3207     SignalException(Trap, instruction_0);
3208 }
3209
3210
3211 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3212 "tgeu r<RS>, r<RT>"
3213 *mipsII:
3214 *mipsIII:
3215 *mipsIV:
3216 // start-sanitize-vr5400
3217 *vr5400:
3218 // end-sanitize-vr5400
3219 // start-sanitize-r5900
3220 *r5900:
3221 // end-sanitize-r5900
3222 *r3900:
3223 // start-sanitize-tx19
3224 *tx19:
3225 // end-sanitize-tx19
3226 {
3227   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3228     SignalException(Trap, instruction_0);
3229 }
3230
3231
3232 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3233 "tlt r<RS>, r<RT>"
3234 *mipsII:
3235 *mipsIII:
3236 *mipsIV:
3237 // start-sanitize-vr5400
3238 *vr5400:
3239 // end-sanitize-vr5400
3240 // start-sanitize-r5900
3241 *r5900:
3242 // end-sanitize-r5900
3243 *r3900:
3244 // start-sanitize-tx19
3245 *tx19:
3246 // end-sanitize-tx19
3247 {
3248   if (GPR[RS] < GPR[RT])
3249     SignalException(Trap, instruction_0);
3250 }
3251
3252
3253 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3254 "tlti r<RS>, <IMMEDIATE>"
3255 *mipsII:
3256 *mipsIII:
3257 *mipsIV:
3258 // start-sanitize-vr5400
3259 *vr5400:
3260 // end-sanitize-vr5400
3261 // start-sanitize-r5900
3262 *r5900:
3263 // end-sanitize-r5900
3264 *r3900:
3265 // start-sanitize-tx19
3266 *tx19:
3267 // end-sanitize-tx19
3268 {
3269   if (GPR[RS] < EXTEND16 (IMMEDIATE))
3270     SignalException(Trap, instruction_0);
3271 }
3272
3273
3274 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3275 "tltiu r<RS>, <IMMEDIATE>"
3276 *mipsII:
3277 *mipsIII:
3278 *mipsIV:
3279 // start-sanitize-vr5400
3280 *vr5400:
3281 // end-sanitize-vr5400
3282 // start-sanitize-r5900
3283 *r5900:
3284 // end-sanitize-r5900
3285 *r3900:
3286 // start-sanitize-tx19
3287 *tx19:
3288 // end-sanitize-tx19
3289 {
3290   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3291     SignalException(Trap, instruction_0);
3292 }
3293
3294
3295 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3296 "tltu r<RS>, r<RT>"
3297 *mipsII:
3298 *mipsIII:
3299 *mipsIV:
3300 // start-sanitize-vr5400
3301 *vr5400:
3302 // end-sanitize-vr5400
3303 // start-sanitize-r5900
3304 *r5900:
3305 // end-sanitize-r5900
3306 *r3900:
3307 // start-sanitize-tx19
3308 *tx19:
3309 // end-sanitize-tx19
3310 {
3311   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3312     SignalException(Trap, instruction_0);
3313 }
3314
3315
3316 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3317 "tne r<RS>, r<RT>"
3318 *mipsII:
3319 *mipsIII:
3320 *mipsIV:
3321 // start-sanitize-vr5400
3322 *vr5400:
3323 // end-sanitize-vr5400
3324 // start-sanitize-r5900
3325 *r5900:
3326 // end-sanitize-r5900
3327 *r3900:
3328 // start-sanitize-tx19
3329 *tx19:
3330 // end-sanitize-tx19
3331 {
3332   if (GPR[RS] != GPR[RT])
3333     SignalException(Trap, instruction_0);
3334 }
3335
3336
3337 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3338 "tne r<RS>, <IMMEDIATE>"
3339 *mipsII:
3340 *mipsIII:
3341 *mipsIV:
3342 // start-sanitize-vr5400
3343 *vr5400:
3344 // end-sanitize-vr5400
3345 // start-sanitize-r5900
3346 *r5900:
3347 // end-sanitize-r5900
3348 *r3900:
3349 // start-sanitize-tx19
3350 *tx19:
3351 // end-sanitize-tx19
3352 {
3353   if (GPR[RS] != EXTEND16 (IMMEDIATE))
3354     SignalException(Trap, instruction_0);
3355 }
3356
3357
3358 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3359 "xor r<RD>, r<RS>, r<RT>"
3360 *mipsI:
3361 *mipsII:
3362 *mipsIII:
3363 *mipsIV:
3364 // start-sanitize-vr5400
3365 *vr5400:
3366 // end-sanitize-vr5400
3367 // start-sanitize-r5900
3368 *r5900:
3369 // end-sanitize-r5900
3370 *r3900:
3371 // start-sanitize-tx19
3372 *tx19:
3373 // end-sanitize-tx19
3374 {
3375   GPR[RD] = GPR[RS] ^ GPR[RT];
3376 }
3377
3378
3379 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3380 "xori r<RT>, r<RS>, <IMMEDIATE>"
3381 *mipsI:
3382 *mipsII:
3383 *mipsIII:
3384 *mipsIV:
3385 // start-sanitize-vr5400
3386 *vr5400:
3387 // end-sanitize-vr5400
3388 // start-sanitize-r5900
3389 *r5900:
3390 // end-sanitize-r5900
3391 *r3900:
3392 // start-sanitize-tx19
3393 *tx19:
3394 // end-sanitize-tx19
3395 {
3396   GPR[RT] = GPR[RS] ^ IMMEDIATE;
3397 }
3398
3399 \f
3400 //
3401 // MIPS Architecture:
3402 //
3403 //        FPU Instruction Set (COP1 & COP1X)
3404 //
3405
3406
3407 :%s:::FMT:int fmt
3408 {
3409   switch (fmt)
3410     {
3411     case fmt_single: return "s";
3412     case fmt_double: return "d";
3413     case fmt_word: return "w";
3414     case fmt_long: return "l";
3415     default: return "?";
3416     }
3417 }
3418
3419 :%s:::TF:int tf
3420 {
3421   if (tf)
3422     return "t";
3423   else
3424     return "f";
3425 }
3426
3427 :%s:::ND:int nd
3428 {
3429   if (nd)
3430     return "l";
3431   else
3432     return "";
3433 }
3434
3435 :%s:::COND:int cond
3436 {
3437   switch (cond)
3438     {
3439     case 00: return "f";
3440     case 01: return "un";
3441     case 02: return "eq";
3442     case 03: return "ueq";
3443     case 04: return "olt";
3444     case 05: return "ult";
3445     case 06: return "ole";
3446     case 07: return "ule";
3447     case 010: return "sf";
3448     case 011: return "ngle";
3449     case 012: return "seq";
3450     case 013: return "ngl";
3451     case 014: return "lt";
3452     case 015: return "nge";
3453     case 016: return "le";
3454     case 017: return "ngt";
3455     default: return "?";
3456     }
3457 }
3458
3459
3460 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3461 "abs.%s<FMT> f<FD>, f<FS>"
3462 *mipsI:
3463 *mipsII:
3464 *mipsIII:
3465 *mipsIV:
3466 // start-sanitize-vr5400
3467 *vr5400:
3468 // end-sanitize-vr5400
3469 // start-sanitize-r5900
3470 *r5900:
3471 // end-sanitize-r5900
3472 *r3900:
3473 // start-sanitize-tx19
3474 *tx19:
3475 // end-sanitize-tx19
3476 {
3477   unsigned32 instruction = instruction_0;
3478   int destreg = ((instruction >> 6) & 0x0000001F);
3479   int fs = ((instruction >> 11) & 0x0000001F);
3480   int format = ((instruction >> 21) & 0x00000007);
3481   {
3482     if ((format != fmt_single) && (format != fmt_double))
3483       SignalException(ReservedInstruction,instruction);
3484     else
3485       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3486   }
3487 }
3488
3489
3490
3491
3492 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
3493 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3494 *mipsI:
3495 *mipsII:
3496 *mipsIII:
3497 *mipsIV:
3498 // start-sanitize-vr5400
3499 *vr5400:
3500 // end-sanitize-vr5400
3501 // start-sanitize-r5900
3502 *r5900:
3503 // end-sanitize-r5900
3504 *r3900:
3505 // start-sanitize-tx19
3506 *tx19:
3507 // end-sanitize-tx19
3508 {
3509   unsigned32 instruction = instruction_0;
3510   int destreg = ((instruction >> 6) & 0x0000001F);
3511   int fs = ((instruction >> 11) & 0x0000001F);
3512   int ft = ((instruction >> 16) & 0x0000001F);
3513   int format = ((instruction >> 21) & 0x00000007);
3514   {
3515     if ((format != fmt_single) && (format != fmt_double))
3516       SignalException(ReservedInstruction, instruction);
3517     else
3518       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3519   }
3520 }
3521
3522
3523 //
3524 // FIXME: This does not correctly resolve mipsI-mipsIV differences.
3525 //
3526 // BC1F
3527 // BC1FL
3528 // BC1T
3529 // BC1TL
3530 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3531 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3532 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3533 *mipsI:
3534 *mipsII:
3535 *mipsIII:
3536 *mipsIV:
3537 // start-sanitize-vr5400
3538 *vr5400:
3539 // end-sanitize-vr5400
3540 // start-sanitize-r5900
3541 *r5900:
3542 // end-sanitize-r5900
3543 *r3900:
3544 // start-sanitize-tx19
3545 *tx19:
3546 // end-sanitize-tx19
3547 {
3548   unsigned32 instruction = instruction_0;
3549   signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
3550   int boolean = ((instruction >> 16) & 0x00000001);
3551   int likely = ((instruction >> 17) & 0x00000001);
3552   int condition_code = ((instruction >> 18) & 0x00000007);
3553   {
3554     if (condition_code != 0)
3555       SignalException(ReservedInstruction,instruction);
3556     else {
3557       int condition = (PREVCOC1() == boolean);
3558       /* NOTE: The branch occurs AFTER the next instruction has been executed */
3559       if (condition) {
3560         DELAY_SLOT (PC + offset);
3561       }
3562       else if (likely) {
3563         NULLIFY_NEXT_INSTRUCTION ();
3564       }
3565     }
3566   }
3567 }
3568
3569
3570 //
3571 // FIXME: This does not correctly differentiate between mips*
3572 //
3573 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3574 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3575 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3576 *mipsI:
3577 *mipsII:
3578 *mipsIII:
3579 *mipsIV:
3580 // start-sanitize-vr5400
3581 *vr5400:
3582 // end-sanitize-vr5400
3583 // start-sanitize-r5900
3584 *r5900:
3585 // end-sanitize-r5900
3586 *r3900:
3587 // start-sanitize-tx19
3588 *tx19:
3589 // end-sanitize-tx19
3590 {
3591   unsigned32 instruction = instruction_0;
3592   int cmpflags = ((instruction >> 0) & 0x0000000F);
3593   int condition_code = ((instruction >> 8) & 0x00000007);
3594   int fs = ((instruction >> 11) & 0x0000001F);
3595   int ft = ((instruction >> 16) & 0x0000001F);
3596   int format = ((instruction >> 21) & 0x00000007);
3597   if (condition_code != 0)
3598     {
3599       SignalException(ReservedInstruction,instruction);
3600     }
3601   else
3602     {
3603       if ((format != fmt_single) && (format != fmt_double))
3604         SignalException(ReservedInstruction,instruction);
3605       else {
3606         if (condition_code != 0)
3607           SignalException(ReservedInstruction,instruction);
3608         else
3609           {
3610             int ignore = 0;
3611             int less = 0;
3612             int equal = 0;
3613             int unordered = 1;
3614             unsigned64 ofs = ValueFPR(fs,format);
3615             unsigned64 oft = ValueFPR(ft,format);
3616             if (NaN(ofs,format) || NaN(oft,format)) {
3617               if (FCSR & FP_ENABLE(IO)) {
3618                 FCSR |= FP_CAUSE(IO);
3619                 SignalExceptionFPE();
3620                 ignore = 1;
3621               }
3622             } else {
3623               less = Less(ofs,oft,format);
3624               equal = Equal(ofs,oft,format);
3625               unordered = 0;
3626             }
3627             if (!ignore) {
3628               int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
3629               SETFCC(condition_code,condition);
3630             }
3631           }
3632       }
3633     }
3634 }
3635
3636
3637 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3638 "ceil.l.%s<FMT> f<FD>, f<FS>"
3639 *mipsIII:
3640 *mipsIV:
3641 // start-sanitize-vr5400
3642 *vr5400:
3643 // end-sanitize-vr5400
3644 // start-sanitize-r5900
3645 *r5900:
3646 // end-sanitize-r5900
3647 *r3900:
3648 // start-sanitize-tx19
3649 *tx19:
3650 // end-sanitize-tx19
3651 {
3652   unsigned32 instruction = instruction_0;
3653   int destreg = ((instruction >> 6) & 0x0000001F);
3654   int fs = ((instruction >> 11) & 0x0000001F);
3655   int format = ((instruction >> 21) & 0x00000007);
3656   {
3657     if ((format != fmt_single) && (format != fmt_double))
3658       SignalException(ReservedInstruction,instruction);
3659     else
3660       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3661   }
3662 }
3663
3664
3665 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3666 *mipsII:
3667 *mipsIII:
3668 *mipsIV:
3669 // start-sanitize-vr5400
3670 *vr5400:
3671 // end-sanitize-vr5400
3672 // start-sanitize-r5900
3673 *r5900:
3674 // end-sanitize-r5900
3675 *r3900:
3676 // start-sanitize-tx19
3677 *tx19:
3678 // end-sanitize-tx19
3679 {
3680   unsigned32 instruction = instruction_0;
3681   int destreg = ((instruction >> 6) & 0x0000001F);
3682   int fs = ((instruction >> 11) & 0x0000001F);
3683   int format = ((instruction >> 21) & 0x00000007);
3684   {
3685   if ((format != fmt_single) && (format != fmt_double))
3686    SignalException(ReservedInstruction,instruction);
3687   else
3688    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3689   }
3690 }
3691
3692
3693 // CFC1
3694 // CTC1
3695 01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1
3696 *mipsI:
3697 *mipsII:
3698 *mipsIII:
3699 *mipsIV:
3700 // start-sanitize-vr5400
3701 *vr5400:
3702 // end-sanitize-vr5400
3703 // start-sanitize-r5900
3704 *r5900:
3705 // end-sanitize-r5900
3706 *r3900:
3707 // start-sanitize-tx19
3708 *tx19:
3709 // end-sanitize-tx19
3710 {
3711   unsigned32 instruction = instruction_0;
3712   int fs = ((instruction >> 11) & 0x0000001F);
3713   int ft = ((instruction >> 16) & 0x0000001F);
3714   int to = ((instruction >> 23) & 0x00000001);
3715   {
3716     if (to) {
3717       if (fs == 0) {
3718         PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft]));
3719       } else if (fs == 31) {
3720         PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft]));
3721       } /* else NOP */
3722       PENDING_FILL(COCIDX,0); /* special case */
3723     } else { /* control from */
3724       if (fs == 0) {
3725         PENDING_FILL(ft,SIGNEXTEND(FCR0,32));
3726       } else if (fs == 31) {
3727         PENDING_FILL(ft,SIGNEXTEND(FCR31,32));
3728       } /* else NOP */
3729     }
3730   }
3731 }
3732
3733
3734 //
3735 // FIXME: Does not correctly differentiate between mips*
3736 //
3737 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3738 "cvt.d.%s<FMT> f<FD>, f<FS>"
3739 *mipsI:
3740 *mipsII:
3741 *mipsIII:
3742 *mipsIV:
3743 // start-sanitize-vr5400
3744 *vr5400:
3745 // end-sanitize-vr5400
3746 // start-sanitize-r5900
3747 *r5900:
3748 // end-sanitize-r5900
3749 *r3900:
3750 // start-sanitize-tx19
3751 *tx19:
3752 // end-sanitize-tx19
3753 {
3754   unsigned32 instruction = instruction_0;
3755   int destreg = ((instruction >> 6) & 0x0000001F);
3756   int fs = ((instruction >> 11) & 0x0000001F);
3757   int format = ((instruction >> 21) & 0x00000007);
3758   {
3759     if ((format == fmt_double) | 0)
3760       SignalException(ReservedInstruction,instruction);
3761     else
3762       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3763   }
3764 }
3765
3766
3767 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3768 "cvt.l.%s<FMT> f<FD>, f<FS>"
3769 *mipsIII:
3770 *mipsIV:
3771 // start-sanitize-vr5400
3772 *vr5400:
3773 // end-sanitize-vr5400
3774 // start-sanitize-r5900
3775 *r5900:
3776 // end-sanitize-r5900
3777 *r3900:
3778 // start-sanitize-tx19
3779 *tx19:
3780 // end-sanitize-tx19
3781 {
3782   unsigned32 instruction = instruction_0;
3783   int destreg = ((instruction >> 6) & 0x0000001F);
3784   int fs = ((instruction >> 11) & 0x0000001F);
3785   int format = ((instruction >> 21) & 0x00000007);
3786   {
3787     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3788       SignalException(ReservedInstruction,instruction);
3789     else
3790       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3791   }
3792 }
3793
3794
3795 //
3796 // FIXME: Does not correctly differentiate between mips*
3797 //
3798 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3799 "cvt.s.%s<FMT> f<FD>, f<FS>"
3800 *mipsI:
3801 *mipsII:
3802 *mipsIII:
3803 *mipsIV:
3804 // start-sanitize-vr5400
3805 *vr5400:
3806 // end-sanitize-vr5400
3807 // start-sanitize-r5900
3808 *r5900:
3809 // end-sanitize-r5900
3810 *r3900:
3811 // start-sanitize-tx19
3812 *tx19:
3813 // end-sanitize-tx19
3814 {
3815   unsigned32 instruction = instruction_0;
3816   int destreg = ((instruction >> 6) & 0x0000001F);
3817   int fs = ((instruction >> 11) & 0x0000001F);
3818   int format = ((instruction >> 21) & 0x00000007);
3819   {
3820     if ((format == fmt_single) | 0)
3821       SignalException(ReservedInstruction,instruction);
3822     else
3823       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3824   }
3825 }
3826
3827
3828 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3829 "cvt.w.%s<FMT> f<FD>, f<FS>"
3830 *mipsI:
3831 *mipsII:
3832 *mipsIII:
3833 *mipsIV:
3834 // start-sanitize-vr5400
3835 *vr5400:
3836 // end-sanitize-vr5400
3837 // start-sanitize-r5900
3838 *r5900:
3839 // end-sanitize-r5900
3840 *r3900:
3841 // start-sanitize-tx19
3842 *tx19:
3843 // end-sanitize-tx19
3844 {
3845   unsigned32 instruction = instruction_0;
3846   int destreg = ((instruction >> 6) & 0x0000001F);
3847   int fs = ((instruction >> 11) & 0x0000001F);
3848   int format = ((instruction >> 21) & 0x00000007);
3849   {
3850     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3851       SignalException(ReservedInstruction,instruction);
3852     else
3853       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3854   }
3855 }
3856
3857
3858 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3859 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3860 *mipsI:
3861 *mipsII:
3862 *mipsIII:
3863 *mipsIV:
3864 // start-sanitize-vr5400
3865 *vr5400:
3866 // end-sanitize-vr5400
3867 // start-sanitize-r5900
3868 *r5900:
3869 // end-sanitize-r5900
3870 *r3900:
3871 // start-sanitize-tx19
3872 *tx19:
3873 // end-sanitize-tx19
3874 {
3875   unsigned32 instruction = instruction_0;
3876   int destreg = ((instruction >> 6) & 0x0000001F);
3877   int fs = ((instruction >> 11) & 0x0000001F);
3878   int ft = ((instruction >> 16) & 0x0000001F);
3879   int format = ((instruction >> 21) & 0x00000007);
3880   {
3881     if ((format != fmt_single) && (format != fmt_double))
3882       SignalException(ReservedInstruction,instruction);
3883     else
3884       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3885   }
3886 }
3887
3888
3889 // DMFC1
3890 // DMTC1
3891 01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1
3892 *mipsIII:
3893 *mipsIV:
3894 // start-sanitize-vr5400
3895 *vr5400:
3896 // end-sanitize-vr5400
3897 // start-sanitize-r5900
3898 *r5900:
3899 // end-sanitize-r5900
3900 *r3900:
3901 // start-sanitize-tx19
3902 *tx19:
3903 // end-sanitize-tx19
3904 {
3905   unsigned32 instruction = instruction_0;
3906   int fs = ((instruction >> 11) & 0x0000001F);
3907   int ft = ((instruction >> 16) & 0x0000001F);
3908   int to = ((instruction >> 23) & 0x00000001);
3909   {
3910     if (to) {
3911       if (SizeFGR() == 64) {
3912         PENDING_FILL((fs + FGRIDX),GPR[ft]);
3913       } else
3914         if ((fs & 0x1) == 0)
3915           {
3916             PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft]));
3917             PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft]));
3918           }
3919     } else {
3920       if (SizeFGR() == 64) {
3921         PENDING_FILL(ft,FGR[fs]);
3922       } else
3923         if ((fs & 0x1) == 0) {
3924           PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs]));
3925         } else {
3926           PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3927         }
3928     }
3929   }
3930 }
3931
3932
3933 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3934 "floor.l.%s<FMT> f<FD>, f<FS>"
3935 *mipsIII:
3936 *mipsIV:
3937 // start-sanitize-vr5400
3938 *vr5400:
3939 // end-sanitize-vr5400
3940 // start-sanitize-r5900
3941 *r5900:
3942 // end-sanitize-r5900
3943 *r3900:
3944 // start-sanitize-tx19
3945 *tx19:
3946 // end-sanitize-tx19
3947 {
3948   unsigned32 instruction = instruction_0;
3949   int destreg = ((instruction >> 6) & 0x0000001F);
3950   int fs = ((instruction >> 11) & 0x0000001F);
3951   int format = ((instruction >> 21) & 0x00000007);
3952   {
3953     if ((format != fmt_single) && (format != fmt_double))
3954       SignalException(ReservedInstruction,instruction);
3955     else
3956       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3957   }
3958 }
3959
3960
3961 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3962 "floor.w.%s<FMT> f<FD>, f<FS>"
3963 *mipsII:
3964 *mipsIII:
3965 *mipsIV:
3966 // start-sanitize-vr5400
3967 *vr5400:
3968 // end-sanitize-vr5400
3969 // start-sanitize-r5900
3970 *r5900:
3971 // end-sanitize-r5900
3972 *r3900:
3973 // start-sanitize-tx19
3974 *tx19:
3975 // end-sanitize-tx19
3976 {
3977   unsigned32 instruction = instruction_0;
3978   int destreg = ((instruction >> 6) & 0x0000001F);
3979   int fs = ((instruction >> 11) & 0x0000001F);
3980   int format = ((instruction >> 21) & 0x00000007);
3981   {
3982     if ((format != fmt_single) && (format != fmt_double))
3983       SignalException(ReservedInstruction,instruction);
3984     else
3985       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3986   }
3987 }
3988
3989
3990 // LDC1
3991 110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1
3992
3993
3994 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3995 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3996 *mipsIV:
3997 // start-sanitize-vr5400
3998 *vr5400:
3999 // end-sanitize-vr5400
4000 // start-sanitize-r5900
4001 *r5900:
4002 // end-sanitize-r5900
4003 {
4004   unsigned32 instruction = instruction_0;
4005   int destreg = ((instruction >> 6) & 0x0000001F);
4006   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4007   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4008   {
4009     address_word vaddr = ((unsigned64)op1 + op2);
4010     address_word paddr;
4011     int uncached;
4012     if ((vaddr & 7) != 0)
4013       SignalExceptionAddressLoad();
4014     else
4015       {
4016         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4017           {
4018             unsigned64 memval = 0;
4019             unsigned64 memval1 = 0;
4020             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4021             COP_LD(1,destreg,memval);;
4022           }
4023       }
4024   }
4025 }
4026
4027
4028 // LWC1
4029 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4030
4031
4032 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4033 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4034 *mipsIV:
4035 // start-sanitize-vr5400
4036 *vr5400:
4037 // end-sanitize-vr5400
4038 // start-sanitize-r5900
4039 *r5900:
4040 // end-sanitize-r5900
4041 {
4042   unsigned32 instruction = instruction_0;
4043   int destreg = ((instruction >> 6) & 0x0000001F);
4044   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4045   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4046   {
4047    address_word vaddr = ((unsigned64)op1 + op2);
4048    address_word paddr;
4049    int uncached;
4050    if ((vaddr & 3) != 0)
4051     SignalExceptionAddressLoad();
4052    else
4053    {
4054     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4055     {
4056      unsigned64 memval = 0;
4057      unsigned64 memval1 = 0;
4058      unsigned64 mask = 0x7;
4059      unsigned int shift = 2;
4060      unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4061      unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4062      unsigned int byte;
4063      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4064      LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4065      byte = ((vaddr & mask) ^ (bigend << shift));
4066      COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4067     }
4068    }
4069   }
4070 }
4071
4072
4073
4074 //
4075 // FIXME: Not correct for mips*
4076 //
4077 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
4078 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4079 *mipsIV:
4080 // start-sanitize-vr5400
4081 *vr5400:
4082 // end-sanitize-vr5400
4083 // start-sanitize-r5900
4084 *r5900:
4085 // end-sanitize-r5900
4086 {
4087   unsigned32 instruction = instruction_0;
4088   int destreg = ((instruction >> 6) & 0x0000001F);
4089   int fs = ((instruction >> 11) & 0x0000001F);
4090   int ft = ((instruction >> 16) & 0x0000001F);
4091   int fr = ((instruction >> 21) & 0x0000001F);
4092   {
4093     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4094   }
4095 }
4096
4097
4098 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
4099 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4100 *mipsIV:
4101 // start-sanitize-vr5400
4102 *vr5400:
4103 // end-sanitize-vr5400
4104 // start-sanitize-r5900
4105 *r5900:
4106 // end-sanitize-r5900
4107 {
4108   unsigned32 instruction = instruction_0;
4109   int destreg = ((instruction >> 6) & 0x0000001F);
4110   int fs = ((instruction >> 11) & 0x0000001F);
4111   int ft = ((instruction >> 16) & 0x0000001F);
4112   int fr = ((instruction >> 21) & 0x0000001F);
4113   {
4114     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4115   }
4116 }
4117
4118
4119 // MFC1
4120 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4121 "m<X>c1 r<RT>, f<FS>"
4122 *mipsI:
4123 *mipsII:
4124 *mipsIII:
4125 *mipsIV:
4126 // start-sanitize-vr5400
4127 *vr5400:
4128 // end-sanitize-vr5400
4129 // start-sanitize-r5900
4130 *r5900:
4131 // end-sanitize-r5900
4132 *r3900:
4133 // start-sanitize-tx19
4134 *tx19:
4135 // end-sanitize-tx19
4136 {
4137   unsigned32 instruction = instruction_0;
4138   int fs = ((instruction >> 11) & 0x0000001F);
4139   int ft = ((instruction >> 16) & 0x0000001F);
4140   int to = ((instruction >> 23) & 0x00000001);
4141   {
4142     if (to) {
4143       if (SizeFGR() == 64) {
4144         PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft])));
4145       } else {
4146         PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft]));
4147       }
4148     } else {
4149       PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32));
4150     }
4151   }
4152 }
4153
4154
4155 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4156 "mov.%s<FMT> f<FD>, f<FS>"
4157 *mipsI:
4158 *mipsII:
4159 *mipsIII:
4160 *mipsIV:
4161 // start-sanitize-vr5400
4162 *vr5400:
4163 // end-sanitize-vr5400
4164 // start-sanitize-r5900
4165 *r5900:
4166 // end-sanitize-r5900
4167 *r3900:
4168 // start-sanitize-tx19
4169 *tx19:
4170 // end-sanitize-tx19
4171 {
4172   unsigned32 instruction = instruction_0;
4173   int destreg = ((instruction >> 6) & 0x0000001F);
4174   int fs = ((instruction >> 11) & 0x0000001F);
4175   int format = ((instruction >> 21) & 0x00000007);
4176   {
4177     StoreFPR(destreg,format,ValueFPR(fs,format));
4178   }
4179 }
4180
4181
4182 // MOVF
4183 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4184 "mov%s<TF> r<RD>, r<RS>, <CC>"
4185 *mipsIV:
4186 // start-sanitize-vr5400
4187 *vr5400:
4188 // end-sanitize-vr5400
4189 // start-sanitize-r5900
4190 *r5900:
4191 // end-sanitize-r5900
4192 {
4193   if (GETFCC(CC) == TF)
4194     GPR[RD] = GPR[RS];
4195 }
4196
4197
4198 // MOVF.fmt
4199 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4200 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4201 *mipsIV:
4202 // start-sanitize-vr5400
4203 *vr5400:
4204 // end-sanitize-vr5400
4205 // start-sanitize-r5900
4206 *r5900:
4207 // end-sanitize-r5900
4208 {
4209   unsigned32 instruction = instruction_0;
4210   int format = ((instruction >> 21) & 0x00000007);
4211   {
4212    if (GETFCC(CC) == TF)
4213      StoreFPR (FD, format, ValueFPR (FS, format));
4214    else
4215      StoreFPR (FD, format, ValueFPR (FD, format));
4216   }
4217 }
4218
4219
4220 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4221 *mipsIV:
4222 // start-sanitize-vr5400
4223 *vr5400:
4224 // end-sanitize-vr5400
4225 // start-sanitize-r5900
4226 *r5900:
4227 // end-sanitize-r5900
4228 {
4229   unsigned32 instruction = instruction_0;
4230   int destreg = ((instruction >> 6) & 0x0000001F);
4231   int fs = ((instruction >> 11) & 0x0000001F);
4232   int format = ((instruction >> 21) & 0x00000007);
4233   {
4234     StoreFPR(destreg,format,ValueFPR(fs,format));
4235   }
4236 }
4237
4238
4239 // MOVT see MOVtf
4240
4241
4242 // MOVT.fmt see MOVtf.fmt
4243
4244
4245
4246 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4247 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4248 *mipsIV:
4249 // start-sanitize-vr5400
4250 *vr5400:
4251 // end-sanitize-vr5400
4252 // start-sanitize-r5900
4253 *r5900:
4254 // end-sanitize-r5900
4255 {
4256   unsigned32 instruction = instruction_0;
4257   int destreg = ((instruction >> 6) & 0x0000001F);
4258   int fs = ((instruction >> 11) & 0x0000001F);
4259   int format = ((instruction >> 21) & 0x00000007);
4260   {
4261    StoreFPR(destreg,format,ValueFPR(fs,format));
4262   }
4263 }
4264
4265
4266 // MSUB.fmt
4267 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4268 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4269 *mipsIV:
4270 // start-sanitize-vr5400
4271 *vr5400:
4272 // end-sanitize-vr5400
4273 // start-sanitize-r5900
4274 *r5900:
4275 // end-sanitize-r5900
4276 {
4277   unsigned32 instruction = instruction_0;
4278   int destreg = ((instruction >> 6) & 0x0000001F);
4279   int fs = ((instruction >> 11) & 0x0000001F);
4280   int ft = ((instruction >> 16) & 0x0000001F);
4281   int fr = ((instruction >> 21) & 0x0000001F);
4282   {
4283     StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4284   }
4285 }
4286
4287
4288 // MSUB.fmt
4289 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4290 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4291 *mipsIV:
4292 // start-sanitize-vr5400
4293 *vr5400:
4294 // end-sanitize-vr5400
4295 // start-sanitize-r5900
4296 *r5900:
4297 // end-sanitize-r5900
4298 {
4299   unsigned32 instruction = instruction_0;
4300   int destreg = ((instruction >> 6) & 0x0000001F);
4301   int fs = ((instruction >> 11) & 0x0000001F);
4302   int ft = ((instruction >> 16) & 0x0000001F);
4303   int fr = ((instruction >> 21) & 0x0000001F);
4304   {
4305    StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4306   }
4307 }
4308
4309
4310 // MTC1 see MxC1
4311
4312
4313 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4314 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4315 *mipsI:
4316 *mipsII:
4317 *mipsIII:
4318 *mipsIV:
4319 // start-sanitize-vr5400
4320 *vr5400:
4321 // end-sanitize-vr5400
4322 // start-sanitize-r5900
4323 *r5900:
4324 // end-sanitize-r5900
4325 *r3900:
4326 // start-sanitize-tx19
4327 *tx19:
4328 // end-sanitize-tx19
4329 {
4330   unsigned32 instruction = instruction_0;
4331   int destreg = ((instruction >> 6) & 0x0000001F);
4332   int fs = ((instruction >> 11) & 0x0000001F);
4333   int ft = ((instruction >> 16) & 0x0000001F);
4334   int format = ((instruction >> 21) & 0x00000007);
4335   {
4336     if ((format != fmt_single) && (format != fmt_double))
4337       SignalException(ReservedInstruction,instruction);
4338     else
4339       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4340   }
4341 }
4342
4343
4344 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4345 "neg.%s<FMT> f<FD>, f<FS>"
4346 *mipsI:
4347 *mipsII:
4348 *mipsIII:
4349 *mipsIV:
4350 // start-sanitize-vr5400
4351 *vr5400:
4352 // end-sanitize-vr5400
4353 // start-sanitize-r5900
4354 *r5900:
4355 // end-sanitize-r5900
4356 *r3900:
4357 // start-sanitize-tx19
4358 *tx19:
4359 // end-sanitize-tx19
4360 {
4361   unsigned32 instruction = instruction_0;
4362   int destreg = ((instruction >> 6) & 0x0000001F);
4363   int fs = ((instruction >> 11) & 0x0000001F);
4364   int format = ((instruction >> 21) & 0x00000007);
4365   {
4366     if ((format != fmt_single) && (format != fmt_double))
4367       SignalException(ReservedInstruction,instruction);
4368     else
4369       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4370   }
4371 }
4372
4373
4374 // NMADD.fmt
4375 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4376 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4377 *mipsIV:
4378 // start-sanitize-vr5400
4379 *vr5400:
4380 // end-sanitize-vr5400
4381 {
4382   unsigned32 instruction = instruction_0;
4383   int destreg = ((instruction >> 6) & 0x0000001F);
4384   int fs = ((instruction >> 11) & 0x0000001F);
4385   int ft = ((instruction >> 16) & 0x0000001F);
4386   int fr = ((instruction >> 21) & 0x0000001F);
4387   {
4388    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4389   }
4390 }
4391
4392
4393 // NMADD.fmt
4394 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4395 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4396 *mipsIV:
4397 // start-sanitize-vr5400
4398 *vr5400:
4399 // end-sanitize-vr5400
4400 {
4401   unsigned32 instruction = instruction_0;
4402   int destreg = ((instruction >> 6) & 0x0000001F);
4403   int fs = ((instruction >> 11) & 0x0000001F);
4404   int ft = ((instruction >> 16) & 0x0000001F);
4405   int fr = ((instruction >> 21) & 0x0000001F);
4406   {
4407    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4408   }
4409 }
4410
4411
4412 // NMSUB.fmt
4413 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4414 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4415 *mipsIV:
4416 // start-sanitize-vr5400
4417 *vr5400:
4418 // end-sanitize-vr5400
4419 {
4420   unsigned32 instruction = instruction_0;
4421   int destreg = ((instruction >> 6) & 0x0000001F);
4422   int fs = ((instruction >> 11) & 0x0000001F);
4423   int ft = ((instruction >> 16) & 0x0000001F);
4424   int fr = ((instruction >> 21) & 0x0000001F);
4425   {
4426    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4427   }
4428 }
4429
4430
4431 // NMSUB.fmt
4432 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4433 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4434 *mipsIV:
4435 // start-sanitize-vr5400
4436 *vr5400:
4437 // end-sanitize-vr5400
4438 {
4439   unsigned32 instruction = instruction_0;
4440   int destreg = ((instruction >> 6) & 0x0000001F);
4441   int fs = ((instruction >> 11) & 0x0000001F);
4442   int ft = ((instruction >> 16) & 0x0000001F);
4443   int fr = ((instruction >> 21) & 0x0000001F);
4444   {
4445     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4446   }
4447 }
4448
4449
4450 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4451 "prefx <HINT>, r<INDEX>(r<BASE>)"
4452 *mipsIV:
4453 // start-sanitize-vr5400
4454 *vr5400:
4455 // end-sanitize-vr5400
4456 {
4457   unsigned32 instruction = instruction_0;
4458   int fs = ((instruction >> 11) & 0x0000001F);
4459   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4460   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4461   {
4462     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4463     address_word paddr;
4464     int uncached;
4465     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4466       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4467   }
4468 }
4469
4470 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4471 *mipsIV:
4472 "recip.%s<FMT> f<FD>, f<FS>"
4473 // start-sanitize-vr5400
4474 *vr5400:
4475 // end-sanitize-vr5400
4476 {
4477   unsigned32 instruction = instruction_0;
4478   int destreg = ((instruction >> 6) & 0x0000001F);
4479   int fs = ((instruction >> 11) & 0x0000001F);
4480   int format = ((instruction >> 21) & 0x00000007);
4481   {
4482   if ((format != fmt_single) && (format != fmt_double))
4483    SignalException(ReservedInstruction,instruction);
4484   else
4485    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4486   }
4487 }
4488
4489
4490 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4491 "round.l.%s<FMT> f<FD>, f<FS>"
4492 *mipsIII:
4493 *mipsIV:
4494 // start-sanitize-vr5400
4495 *vr5400:
4496 // end-sanitize-vr5400
4497 // start-sanitize-r5900
4498 *r5900:
4499 // end-sanitize-r5900
4500 *r3900:
4501 // start-sanitize-tx19
4502 *tx19:
4503 // end-sanitize-tx19
4504 {
4505   unsigned32 instruction = instruction_0;
4506   int destreg = ((instruction >> 6) & 0x0000001F);
4507   int fs = ((instruction >> 11) & 0x0000001F);
4508   int format = ((instruction >> 21) & 0x00000007);
4509   {
4510     if ((format != fmt_single) && (format != fmt_double))
4511       SignalException(ReservedInstruction,instruction);
4512     else
4513       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4514   }
4515 }
4516
4517
4518 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4519 "round.w.%s<FMT> f<FD>, f<FS>"
4520 *mipsII:
4521 *mipsIII:
4522 *mipsIV:
4523 // start-sanitize-vr5400
4524 *vr5400:
4525 // end-sanitize-vr5400
4526 // start-sanitize-r5900
4527 *r5900:
4528 // end-sanitize-r5900
4529 *r3900:
4530 // start-sanitize-tx19
4531 *tx19:
4532 // end-sanitize-tx19
4533 {
4534   unsigned32 instruction = instruction_0;
4535   int destreg = ((instruction >> 6) & 0x0000001F);
4536   int fs = ((instruction >> 11) & 0x0000001F);
4537   int format = ((instruction >> 21) & 0x00000007);
4538   {
4539   if ((format != fmt_single) && (format != fmt_double))
4540    SignalException(ReservedInstruction,instruction);
4541   else
4542    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4543   }
4544 }
4545
4546
4547 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4548 *mipsIV:
4549 "rsqrt.%s<FMT> f<FD>, f<FS>"
4550 // start-sanitize-vr5400
4551 *vr5400:
4552 // end-sanitize-vr5400
4553 {
4554   unsigned32 instruction = instruction_0;
4555   int destreg = ((instruction >> 6) & 0x0000001F);
4556   int fs = ((instruction >> 11) & 0x0000001F);
4557   int format = ((instruction >> 21) & 0x00000007);
4558   {
4559   if ((format != fmt_single) && (format != fmt_double))
4560    SignalException(ReservedInstruction,instruction);
4561   else
4562    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4563   }
4564 }
4565
4566
4567 // SDC1
4568
4569
4570 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
4571 *mipsIV:
4572 // start-sanitize-vr5400
4573 *vr5400:
4574 // end-sanitize-vr5400
4575 // start-sanitize-r5900
4576 *r5900:
4577 // end-sanitize-r5900
4578 {
4579   unsigned32 instruction = instruction_0;
4580   int fs = ((instruction >> 11) & 0x0000001F);
4581   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4582   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4583   {
4584     address_word vaddr = ((unsigned64)op1 + op2);
4585     address_word paddr;
4586     int uncached;
4587     if ((vaddr & 7) != 0)
4588       SignalExceptionAddressStore();
4589     else
4590       {
4591         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4592           {
4593             unsigned64 memval = 0;
4594             unsigned64 memval1 = 0;
4595             memval = (unsigned64)COP_SD(1,fs);
4596             {
4597               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
4598             }
4599           }
4600       }
4601   }
4602 }
4603
4604
4605 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4606 "sqrt.%s<FMT> f<FD>, f<FS>"
4607 *mipsII:
4608 *mipsIII:
4609 *mipsIV:
4610 // start-sanitize-vr5400
4611 *vr5400:
4612 // end-sanitize-vr5400
4613 // start-sanitize-r5900
4614 *r5900:
4615 // end-sanitize-r5900
4616 *r3900:
4617 // start-sanitize-tx19
4618 *tx19:
4619 // end-sanitize-tx19
4620 {
4621   unsigned32 instruction = instruction_0;
4622   int destreg = ((instruction >> 6) & 0x0000001F);
4623   int fs = ((instruction >> 11) & 0x0000001F);
4624   int format = ((instruction >> 21) & 0x00000007);
4625   {
4626     if ((format != fmt_single) && (format != fmt_double))
4627       SignalException(ReservedInstruction,instruction);
4628     else
4629       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4630   }
4631 }
4632
4633
4634 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4635 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4636 *mipsI:
4637 *mipsII:
4638 *mipsIII:
4639 *mipsIV:
4640 // start-sanitize-vr5400
4641 *vr5400:
4642 // end-sanitize-vr5400
4643 // start-sanitize-r5900
4644 *r5900:
4645 // end-sanitize-r5900
4646 *r3900:
4647 // start-sanitize-tx19
4648 *tx19:
4649 // end-sanitize-tx19
4650 {
4651   unsigned32 instruction = instruction_0;
4652   int destreg = ((instruction >> 6) & 0x0000001F);
4653   int fs = ((instruction >> 11) & 0x0000001F);
4654   int ft = ((instruction >> 16) & 0x0000001F);
4655   int format = ((instruction >> 21) & 0x00000007);
4656   {
4657     if ((format != fmt_single) && (format != fmt_double))
4658       SignalException(ReservedInstruction,instruction);
4659     else
4660       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4661   }
4662 }
4663
4664
4665 // SWC1
4666
4667
4668 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4669 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4670 *mipsIV:
4671 // start-sanitize-vr5400
4672 *vr5400:
4673 // end-sanitize-vr5400
4674 // start-sanitize-r5900
4675 *r5900:
4676 // end-sanitize-r5900
4677 {
4678   unsigned32 instruction = instruction_0;
4679   int fs = ((instruction >> 11) & 0x0000001F);
4680   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4681   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4682   {
4683    address_word vaddr = ((unsigned64)op1 + op2);
4684    address_word paddr;
4685    int uncached;
4686    if ((vaddr & 3) != 0)
4687     SignalExceptionAddressStore();
4688    else
4689    {
4690     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4691     {
4692      unsigned64 memval = 0;
4693      unsigned64 memval1 = 0;
4694      unsigned64 mask = 0x7;
4695      unsigned int byte;
4696      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4697      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4698      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4699       {
4700        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4701       }
4702     }
4703    }
4704   }
4705 }
4706
4707
4708 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4709 "trunc.l.%s<FMT> f<FD>, f<FS>"
4710 *mipsIII:
4711 *mipsIV:
4712 // start-sanitize-vr5400
4713 *vr5400:
4714 // end-sanitize-vr5400
4715 // start-sanitize-r5900
4716 *r5900:
4717 // end-sanitize-r5900
4718 *r3900:
4719 // start-sanitize-tx19
4720 *tx19:
4721 // end-sanitize-tx19
4722 {
4723   unsigned32 instruction = instruction_0;
4724   int destreg = ((instruction >> 6) & 0x0000001F);
4725   int fs = ((instruction >> 11) & 0x0000001F);
4726   int format = ((instruction >> 21) & 0x00000007);
4727   {
4728   if ((format != fmt_single) && (format != fmt_double))
4729    SignalException(ReservedInstruction,instruction);
4730   else
4731    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4732   }
4733 }
4734
4735
4736 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4737 "trunc.w.%s<FMT> f<FD>, f<FS>"
4738 *mipsII:
4739 *mipsIII:
4740 *mipsIV:
4741 // start-sanitize-vr5400
4742 *vr5400:
4743 // end-sanitize-vr5400
4744 // start-sanitize-r5900
4745 *r5900:
4746 // end-sanitize-r5900
4747 *r3900:
4748 // start-sanitize-tx19
4749 *tx19:
4750 // end-sanitize-tx19
4751 {
4752   unsigned32 instruction = instruction_0;
4753   int destreg = ((instruction >> 6) & 0x0000001F);
4754   int fs = ((instruction >> 11) & 0x0000001F);
4755   int format = ((instruction >> 21) & 0x00000007);
4756   {
4757   if ((format != fmt_single) && (format != fmt_double))
4758    SignalException(ReservedInstruction,instruction);
4759   else
4760    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4761   }
4762 }
4763
4764 \f
4765 //
4766 // MIPS Architecture:
4767 //
4768 //        System Control Instruction Set (COP0)
4769 //
4770
4771
4772 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4773 "bc0f <OFFSET>"
4774 *mipsI:
4775 *mipsII:
4776 *mipsIII:
4777 *mipsIV:
4778 // start-sanitize-vr5400
4779 *vr5400:
4780 // end-sanitize-vr5400
4781 // start-sanitize-r5900
4782 *r5900:
4783 // end-sanitize-r5900
4784
4785
4786 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4787 "bc0fl <OFFSET>"
4788 *mipsI:
4789 *mipsII:
4790 *mipsIII:
4791 *mipsIV:
4792 // start-sanitize-vr5400
4793 *vr5400:
4794 // end-sanitize-vr5400
4795 // start-sanitize-r5900
4796 *r5900:
4797 // end-sanitize-r5900
4798
4799
4800 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4801 "bc0t <OFFSET>"
4802 *mipsI:
4803 *mipsII:
4804 *mipsIII:
4805 *mipsIV:
4806 // start-sanitize-r5900
4807 *r5900:
4808 // end-sanitize-r5900
4809
4810
4811
4812 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4813 "bc0tl <OFFSET>"
4814 *mipsI:
4815 *mipsII:
4816 *mipsIII:
4817 *mipsIV:
4818 // start-sanitize-vr5400
4819 *vr5400:
4820 // end-sanitize-vr5400
4821 // start-sanitize-r5900
4822 *r5900:
4823 // end-sanitize-r5900
4824
4825
4826 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4827 *mipsIII:
4828 *mipsIV:
4829 // start-sanitize-vr5400
4830 *vr5400:
4831 // end-sanitize-vr5400
4832 // start-sanitize-r5900
4833 *r5900:
4834 // end-sanitize-r5900
4835 *r3900:
4836 // start-sanitize-tx19
4837 *tx19:
4838 // end-sanitize-tx19
4839 {
4840   unsigned32 instruction = instruction_0;
4841   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
4842   int hint = ((instruction >> 16) & 0x0000001F);
4843   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4844   {
4845     address_word vaddr = (op1 + offset);
4846     address_word paddr;
4847     int uncached;
4848     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4849       CacheOp(hint,vaddr,paddr,instruction);
4850   }
4851 }
4852
4853
4854 010000,10000,000000000000000,111001:COP0:32::DI
4855 "di"
4856 *mipsI:
4857 *mipsII:
4858 *mipsIII:
4859 *mipsIV:
4860 // start-sanitize-vr5400
4861 *vr5400:
4862 // end-sanitize-vr5400
4863 // start-sanitize-r5900
4864 *r5900:
4865 // end-sanitize-r5900
4866
4867
4868 010000,10000,000000000000000,111000:COP0:32::EI
4869 "ei"
4870 *mipsI:
4871 *mipsII:
4872 *mipsIII:
4873 *mipsIV:
4874 // start-sanitize-vr5400
4875 *vr5400:
4876 // end-sanitize-vr5400
4877 // start-sanitize-r5900
4878 *r5900:
4879 // end-sanitize-r5900
4880
4881
4882 010000,10000,000000000000000,011000:COP0:32::ERET
4883 "eret"
4884 *mipsIII:
4885 *mipsIV:
4886 // start-sanitize-vr5400
4887 *vr5400:
4888 // end-sanitize-vr5400
4889 // start-sanitize-r5900
4890 *r5900:
4891 // end-sanitize-r5900
4892
4893
4894 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4895 "mfc0 r<RT>, r<RD> # <REGX>"
4896 *mipsI:
4897 *mipsII:
4898 *mipsIII:
4899 *mipsIV:
4900 // start-sanitize-vr5400
4901 *vr5400:
4902 // end-sanitize-vr5400
4903 // start-sanitize-r5900
4904 *r5900:
4905 // end-sanitize-r5900
4906
4907
4908 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4909 "mtc0 r<RT>, r<RD> # <REGX>"
4910 *mipsI:
4911 *mipsII:
4912 *mipsIII:
4913 *mipsIV:
4914 // start-sanitize-vr5400
4915 *vr5400:
4916 // end-sanitize-vr5400
4917 // start-sanitize-r5900
4918 *r5900:
4919 // end-sanitize-r5900
4920
4921
4922 010000,10000,000000000000000,001000:COP0:32::TLBP
4923 "tlbp"
4924 *mipsI:
4925 *mipsII:
4926 *mipsIII:
4927 *mipsIV:
4928 // start-sanitize-vr5400
4929 *vr5400:
4930 // end-sanitize-vr5400
4931 // start-sanitize-r5900
4932 *r5900:
4933 // end-sanitize-r5900
4934
4935
4936 010000,10000,000000000000000,000001:COP0:32::TLBR
4937 "tlbr"
4938 *mipsI:
4939 *mipsII:
4940 *mipsIII:
4941 *mipsIV:
4942 // start-sanitize-vr5400
4943 *vr5400:
4944 // end-sanitize-vr5400
4945 // start-sanitize-r5900
4946 *r5900:
4947 // end-sanitize-r5900
4948
4949
4950 010000,10000,000000000000000,000010:COP0:32::TLBWI
4951 "tlbwi"
4952 *mipsI:
4953 *mipsII:
4954 *mipsIII:
4955 *mipsIV:
4956 // start-sanitize-vr5400
4957 *vr5400:
4958 // end-sanitize-vr5400
4959 // start-sanitize-r5900
4960 *r5900:
4961 // end-sanitize-r5900
4962
4963
4964 010000,10000,000000000000000,000110:COP0:32::TLBWR
4965 "tlbwr"
4966 *mipsI:
4967 *mipsII:
4968 *mipsIII:
4969 *mipsIV:
4970 // start-sanitize-vr5400
4971 *vr5400:
4972 // end-sanitize-vr5400
4973 // start-sanitize-r5900
4974 *r5900:
4975 // end-sanitize-r5900
4976
4977 \f
4978 //
4979 // MIPS Architecture:
4980 //
4981 //        CPU Instruction Set (mips16)
4982 //
4983
4984 // The instructions in this section are ordered according
4985 // to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
4986
4987
4988 // FIXME: Instead of having the code for mips16 instructions here.
4989 // these instructions should instead call the corresponding 32bit
4990 // instruction (or a function implementing that instructions code).
4991
4992
4993 // Load and Store Instructions
4994
4995
4996 10000,xxx,ddd,55555:RRI:16::LB
4997 *mips16:
4998 {
4999   unsigned32 instruction = instruction_0;
5000   signed_word op1 = (instruction >> 8) & 0x7;
5001   int destreg = (instruction >> 5) & 0x7;
5002   int offset = (instruction >> 0) & 0x1f;
5003   if (op1 < 2)
5004     op1 += 16;
5005   op1 = GPR[op1];
5006   if (destreg < 2)
5007     destreg += 16;
5008   if (have_extendval)
5009     {
5010       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5011       if (offset >= 0x8000)
5012         offset -= 0x10000;
5013       have_extendval = 0;
5014     }
5015   else
5016     {
5017     }
5018   if (have_extendval)
5019     SignalException (ReservedInstruction, instruction);
5020   {
5021     address_word vaddr = ((unsigned64)op1 + offset);
5022     address_word paddr;
5023     int uncached;
5024     {
5025       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5026         {
5027           unsigned64 memval = 0;
5028           unsigned64 memval1 = 0;
5029           unsigned64 mask = 0x7;
5030           unsigned int shift = 0;
5031           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5032           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5033           unsigned int byte;
5034           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5035           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
5036           byte = ((vaddr & mask) ^ (bigend << shift));
5037           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
5038         }
5039     }
5040   }
5041 }
5042
5043
5044 10100,xxx,ddd,55555:RRI:16::LBU
5045 *mips16:
5046 {
5047   unsigned32 instruction = instruction_0;
5048   signed_word op1 = (instruction >> 8) & 0x7;
5049   int destreg = (instruction >> 5) & 0x7;
5050   int offset = (instruction >> 0) & 0x1f;
5051   if (op1 < 2)
5052     op1 += 16;
5053   op1 = GPR[op1];
5054   if (destreg < 2)
5055     destreg += 16;
5056   if (have_extendval)
5057     {
5058       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5059       if (offset >= 0x8000)
5060         offset -= 0x10000;
5061       have_extendval = 0;
5062     }
5063   else
5064     {
5065     }
5066   if (have_extendval)
5067     SignalException (ReservedInstruction, instruction);
5068   {
5069     address_word vaddr = ((unsigned64)op1 + offset);
5070     address_word paddr;
5071     int uncached;
5072     {
5073       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5074         {
5075           unsigned64 memval = 0;
5076           unsigned64 memval1 = 0;
5077           unsigned64 mask = 0x7;
5078           unsigned int shift = 0;
5079           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5080           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5081           unsigned int byte;
5082           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5083           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
5084           byte = ((vaddr & mask) ^ (bigend << shift));
5085           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
5086         }
5087     }
5088   }
5089 }
5090
5091
5092 10001,xxx,ddd,HHHHH:RRI:16::LH
5093 *mips16:
5094 {
5095   unsigned32 instruction = instruction_0;
5096   signed_word op1 = (instruction >> 8) & 0x7;
5097   int destreg = (instruction >> 5) & 0x7;
5098   int offset = (instruction >> 0) & 0x1f;
5099   if (op1 < 2)
5100     op1 += 16;
5101   op1 = GPR[op1];
5102   if (destreg < 2)
5103     destreg += 16;
5104   if (have_extendval)
5105     {
5106       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5107       if (offset >= 0x8000)
5108         offset -= 0x10000;
5109       have_extendval = 0;
5110     }
5111   else
5112     {
5113       offset <<= 1;
5114     }
5115   if (have_extendval)
5116     SignalException (ReservedInstruction, instruction);
5117   {
5118     address_word vaddr = ((unsigned64)op1 + offset);
5119     address_word paddr;
5120     int uncached;
5121     if ((vaddr & 1) != 0)
5122       SignalExceptionAddressLoad();
5123     else
5124       {
5125         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5126           {
5127             unsigned64 memval = 0;
5128             unsigned64 memval1 = 0;
5129             unsigned64 mask = 0x7;
5130             unsigned int shift = 1;
5131             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5132             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5133             unsigned int byte;
5134             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5135             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
5136             byte = ((vaddr & mask) ^ (bigend << shift));
5137             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
5138           }
5139       }
5140   }
5141 }
5142
5143
5144 10101,xxx,ddd,HHHHH:RRI:16::LHU
5145 *mips16:
5146 {
5147   unsigned32 instruction = instruction_0;
5148   signed_word op1 = (instruction >> 8) & 0x7;
5149   int destreg = (instruction >> 5) & 0x7;
5150   int offset = (instruction >> 0) & 0x1f;
5151   if (op1 < 2)
5152     op1 += 16;
5153   op1 = GPR[op1];
5154   if (destreg < 2)
5155     destreg += 16;
5156   if (have_extendval)
5157     {
5158       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5159       if (offset >= 0x8000)
5160         offset -= 0x10000;
5161       have_extendval = 0;
5162     }
5163   else
5164     {
5165       offset <<= 1;
5166     }
5167   if (have_extendval)
5168     SignalException (ReservedInstruction, instruction);
5169   {
5170     address_word vaddr = ((unsigned64)op1 + offset);
5171     address_word paddr;
5172     int uncached;
5173     if ((vaddr & 1) != 0)
5174       SignalExceptionAddressLoad();
5175     else
5176       {
5177         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5178           {
5179             unsigned64 memval = 0;
5180             unsigned64 memval1 = 0;
5181             unsigned64 mask = 0x7;
5182             unsigned int shift = 1;
5183             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5184             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5185             unsigned int byte;
5186             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5187             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
5188             byte = ((vaddr & mask) ^ (bigend << shift));
5189             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
5190           }
5191       }
5192   }
5193 }
5194
5195
5196 10011,xxx,ddd,WWWWW:RRI:16::LW
5197 *mips16:
5198 {
5199   unsigned32 instruction = instruction_0;
5200   signed_word op1 = (instruction >> 8) & 0x7;
5201   int destreg = (instruction >> 5) & 0x7;
5202   int offset = (instruction >> 0) & 0x1f;
5203   if (op1 < 2)
5204     op1 += 16;
5205   op1 = GPR[op1];
5206   if (destreg < 2)
5207     destreg += 16;
5208   if (have_extendval)
5209     {
5210       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5211       if (offset >= 0x8000)
5212         offset -= 0x10000;
5213       have_extendval = 0;
5214     }
5215   else
5216     {
5217       offset <<= 2;
5218     }
5219   if (have_extendval)
5220     SignalException (ReservedInstruction, instruction);
5221   {
5222     address_word vaddr = ((unsigned64)op1 + offset);
5223     address_word paddr;
5224     int uncached;
5225     if ((vaddr & 3) != 0)
5226       SignalExceptionAddressLoad();
5227     else
5228       {
5229         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5230           {
5231             unsigned64 memval = 0;
5232             unsigned64 memval1 = 0;
5233             unsigned64 mask = 0x7;
5234             unsigned int shift = 2;
5235             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5236             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5237             unsigned int byte;
5238             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5239             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
5240             byte = ((vaddr & mask) ^ (bigend << shift));
5241             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
5242           }
5243       }
5244   }
5245 }
5246
5247
5248 10110,ddd,VVVVVVVV,P:RI:16::LWPC
5249 *mips16:
5250 {
5251   unsigned32 instruction = instruction_0;
5252   int destreg = (instruction >> 8) & 0x7;
5253   int offset = (instruction >> 0) & 0xff;
5254   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
5255   if (destreg < 2)
5256     destreg += 16;
5257   if (have_extendval)
5258     {
5259       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5260       if (offset >= 0x8000)
5261         offset -= 0x10000;
5262       have_extendval = 0;
5263     }
5264   else
5265     {
5266       offset <<= 2;
5267     }
5268   if (have_extendval)
5269     SignalException (ReservedInstruction, instruction);
5270   {
5271     address_word vaddr = ((unsigned64)op1 + offset);
5272     address_word paddr;
5273     int uncached;
5274     if ((vaddr & 3) != 0)
5275       SignalExceptionAddressLoad();
5276     else
5277       {
5278         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5279           {
5280             unsigned64 memval = 0;
5281             unsigned64 memval1 = 0;
5282             unsigned64 mask = 0x7;
5283             unsigned int shift = 2;
5284             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5285             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5286             unsigned int byte;
5287             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5288             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
5289             byte = ((vaddr & mask) ^ (bigend << shift));
5290             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
5291           }
5292       }
5293   }
5294 }
5295
5296
5297 10010,ddd,VVVVVVVV,s:RI:16::LWSP
5298 *mips16:
5299 {
5300   unsigned32 instruction = instruction_0;
5301   int destreg = (instruction >> 8) & 0x7;
5302   int offset = (instruction >> 0) & 0xff;
5303   signed_word op1 = 29;
5304   if (destreg < 2)
5305     destreg += 16;
5306   if (have_extendval)
5307     {
5308       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5309       if (offset >= 0x8000)
5310         offset -= 0x10000;
5311       have_extendval = 0;
5312     }
5313   else
5314     {
5315       offset <<= 2;
5316     }
5317   op1 = GPR[op1];
5318   if (have_extendval)
5319     SignalException (ReservedInstruction, instruction);
5320   {
5321     address_word vaddr = ((unsigned64)op1 + offset);
5322     address_word paddr;
5323     int uncached;
5324     if ((vaddr & 3) != 0)
5325       SignalExceptionAddressLoad();
5326     else
5327       {
5328         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5329           {
5330             unsigned64 memval = 0;
5331             unsigned64 memval1 = 0;
5332             unsigned64 mask = 0x7;
5333             unsigned int shift = 2;
5334             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5335             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5336             unsigned int byte;
5337             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5338             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
5339             byte = ((vaddr & mask) ^ (bigend << shift));
5340             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
5341           }
5342       }
5343   }
5344 }
5345
5346
5347 10111,xxx,ddd,WWWWW:RRI:16::LWU
5348 *mips16:
5349 {
5350   unsigned32 instruction = instruction_0;
5351   signed_word op1 = (instruction >> 8) & 0x7;
5352   int destreg = (instruction >> 5) & 0x7;
5353   int offset = (instruction >> 0) & 0x1f;
5354   if (op1 < 2)
5355     op1 += 16;
5356   op1 = GPR[op1];
5357   if (destreg < 2)
5358     destreg += 16;
5359   if (have_extendval)
5360     {
5361       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5362       if (offset >= 0x8000)
5363         offset -= 0x10000;
5364       have_extendval = 0;
5365     }
5366   else
5367     {
5368       offset <<= 2;
5369     }
5370   if (have_extendval)
5371     SignalException (ReservedInstruction, instruction);
5372   {
5373     address_word vaddr = ((unsigned64)op1 + offset);
5374     address_word paddr;
5375     int uncached;
5376     if ((vaddr & 3) != 0)
5377       SignalExceptionAddressLoad();
5378     else
5379       {
5380         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5381           {
5382             unsigned64 memval = 0;
5383             unsigned64 memval1 = 0;
5384             unsigned64 mask = 0x7;
5385             unsigned int shift = 2;
5386             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5387             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5388             unsigned int byte;
5389             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5390             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
5391             byte = ((vaddr & mask) ^ (bigend << shift));
5392             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
5393           }
5394       }
5395   }
5396 }
5397
5398
5399 00111,xxx,ddd,DDDDD:RRI:16::LD
5400 *mips16:
5401 {
5402   unsigned32 instruction = instruction_0;
5403   signed_word op1 = (instruction >> 8) & 0x7;
5404   int destreg = (instruction >> 5) & 0x7;
5405   int offset = (instruction >> 0) & 0x1f;
5406   if (op1 < 2)
5407     op1 += 16;
5408   op1 = GPR[op1];
5409   if (destreg < 2)
5410     destreg += 16;
5411   if (have_extendval)
5412     {
5413       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5414       if (offset >= 0x8000)
5415         offset -= 0x10000;
5416       have_extendval = 0;
5417     }
5418   else
5419     {
5420       offset <<= 3;
5421     }
5422   if (have_extendval)
5423     SignalException (ReservedInstruction, instruction);
5424   {
5425     address_word vaddr = ((unsigned64)op1 + offset);
5426     address_word paddr;
5427     int uncached;
5428     if ((vaddr & 7) != 0)
5429       SignalExceptionAddressLoad();
5430     else
5431       {
5432         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5433           {
5434             unsigned64 memval = 0;
5435             unsigned64 memval1 = 0;
5436             unsigned64 mask = 0x7;
5437             unsigned int shift = 4;
5438             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5439             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5440             unsigned int byte;
5441             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
5442             GPR[destreg] = memval;
5443           }
5444       }
5445   }
5446 }
5447
5448
5449 11111100,ddd,5.RD,P:RI64:16::LDPC
5450 *mips16:
5451 {
5452   unsigned32 instruction = instruction_0;
5453   int destreg = (instruction >> 5) & 0x7;
5454   int offset = (instruction >> 0) & 0x1f;
5455   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x7;
5456   if (destreg < 2)
5457     destreg += 16;
5458   if (have_extendval)
5459     {
5460       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5461       if (offset >= 0x8000)
5462         offset -= 0x10000;
5463       have_extendval = 0;
5464     }
5465   else
5466     {
5467       offset <<= 3;
5468     }
5469   if (have_extendval)
5470     SignalException (ReservedInstruction, instruction);
5471   {
5472     address_word vaddr = ((unsigned64)op1 + offset);
5473     address_word paddr;
5474     int uncached;
5475     if ((vaddr & 7) != 0)
5476       SignalExceptionAddressLoad();
5477     else
5478       {
5479         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5480           {
5481             unsigned64 memval = 0;
5482             unsigned64 memval1 = 0;
5483             unsigned64 mask = 0x7;
5484             unsigned int shift = 4;
5485             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5486             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5487             unsigned int byte;
5488             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
5489             GPR[destreg] = memval;
5490           }
5491       }
5492   }
5493 }
5494
5495
5496 11111000,ddd,5.RD,s:RI64:16::LDSP
5497 *mips16:
5498 {
5499   unsigned32 instruction = instruction_0;
5500   int destreg = (instruction >> 5) & 0x7;
5501   int offset = (instruction >> 0) & 0x1f;
5502   signed_word op1 = 29;
5503   if (destreg < 2)
5504     destreg += 16;
5505   if (have_extendval)
5506     {
5507       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5508       if (offset >= 0x8000)
5509         offset -= 0x10000;
5510       have_extendval = 0;
5511     }
5512   else
5513     {
5514       offset <<= 3;
5515     }
5516   op1 = GPR[op1];
5517   if (have_extendval)
5518     SignalException (ReservedInstruction, instruction);
5519   {
5520     address_word vaddr = ((unsigned64)op1 + offset);
5521     address_word paddr;
5522     int uncached;
5523     if ((vaddr & 7) != 0)
5524       SignalExceptionAddressLoad();
5525     else
5526       {
5527         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5528           {
5529             unsigned64 memval = 0;
5530             unsigned64 memval1 = 0;
5531             unsigned64 mask = 0x7;
5532             unsigned int shift = 4;
5533             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5534             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5535             unsigned int byte;
5536             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
5537             GPR[destreg] = memval;
5538           }
5539       }
5540   }
5541 }
5542
5543
5544 11000,xxx,yyy,55555:RRI:16::SB
5545 *mips16:
5546 {
5547   unsigned32 instruction = instruction_0;
5548   signed_word op1 = (instruction >> 8) & 0x7;
5549   signed_word op2 = (instruction >> 5) & 0x7;
5550   int offset = (instruction >> 0) & 0x1f;
5551   if (op1 < 2)
5552     op1 += 16;
5553   op1 = GPR[op1];
5554   if (op2 < 2)
5555     op2 += 16;
5556   op2 = GPR[op2];
5557   if (have_extendval)
5558     {
5559       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5560       if (offset >= 0x8000)
5561         offset -= 0x10000;
5562       have_extendval = 0;
5563     }
5564   else
5565     {
5566     }
5567   if (have_extendval)
5568     SignalException (ReservedInstruction, instruction);
5569   {
5570     address_word vaddr = ((unsigned64)op1 + offset);
5571     address_word paddr;
5572     int uncached;
5573     {
5574       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5575         {
5576           unsigned64 memval = 0;
5577           unsigned64 memval1 = 0;
5578           unsigned64 mask = 0x7;
5579           unsigned int shift = 0;
5580           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5581           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5582           unsigned int byte;
5583           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5584           byte = ((vaddr & mask) ^ (bigend << shift));
5585           memval = ((unsigned64) op2 << (8 * byte));
5586           {
5587             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
5588           }
5589         }
5590     }
5591   }
5592 }
5593
5594
5595 11001,xxx,yyy,HHHHH:RRI:16::SH
5596 *mips16:
5597 {
5598   unsigned32 instruction = instruction_0;
5599   signed_word op1 = (instruction >> 8) & 0x7;
5600   signed_word op2 = (instruction >> 5) & 0x7;
5601   int offset = (instruction >> 0) & 0x1f;
5602   if (op1 < 2)
5603     op1 += 16;
5604   op1 = GPR[op1];
5605   if (op2 < 2)
5606     op2 += 16;
5607   op2 = GPR[op2];
5608   if (have_extendval)
5609     {
5610       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5611       if (offset >= 0x8000)
5612         offset -= 0x10000;
5613       have_extendval = 0;
5614     }
5615   else
5616     {
5617       offset <<= 1;
5618     }
5619   if (have_extendval)
5620     SignalException (ReservedInstruction, instruction);
5621   {
5622     address_word vaddr = ((unsigned64)op1 + offset);
5623     address_word paddr;
5624     int uncached;
5625     if ((vaddr & 1) != 0)
5626       SignalExceptionAddressStore();
5627     else
5628       {
5629         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5630           {
5631             unsigned64 memval = 0;
5632             unsigned64 memval1 = 0;
5633             unsigned64 mask = 0x7;
5634             unsigned int shift = 1;
5635             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
5636             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
5637             unsigned int byte;
5638             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
5639             byte = ((vaddr & mask) ^ (bigend << shift));
5640             memval = ((unsigned64) op2 << (8 * byte));
5641             {
5642               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
5643             }
5644           }
5645       }
5646   }
5647 }
5648
5649
5650 11011,xxx,yyy,WWWWW:RRI:16::SW
5651 *mips16:
5652 {
5653   unsigned32 instruction = instruction_0;
5654   signed_word op1 = (instruction >> 8) & 0x7;
5655   signed_word op2 = (instruction >> 5) & 0x7;
5656   int offset = (instruction >> 0) & 0x1f;
5657   if (op1 < 2)
5658     op1 += 16;
5659   op1 = GPR[op1];
5660   if (op2 < 2)
5661     op2 += 16;
5662   op2 = GPR[op2];
5663   if (have_extendval)
5664     {
5665       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5666       if (offset >= 0x8000)
5667         offset -= 0x10000;
5668       have_extendval = 0;
5669     }
5670   else
5671     {
5672       offset <<= 2;
5673     }
5674   if (have_extendval)
5675     SignalException (ReservedInstruction, instruction);
5676   {
5677     address_word vaddr = ((unsigned64)op1 + offset);
5678     address_word paddr;
5679     int uncached;
5680     if ((vaddr & 3) != 0)
5681       SignalExceptionAddressStore();
5682     else
5683       {
5684         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5685           {
5686             unsigned64 memval = 0;
5687             unsigned64 memval1 = 0;
5688             unsigned64 mask = 0x7;
5689             unsigned int byte;
5690             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5691             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5692             memval = ((unsigned64) op2 << (8 * byte));
5693             {
5694               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5695             }
5696           }
5697       }
5698   }
5699 }
5700
5701
5702 11010,yyy,VVVVVVVV,s:RI:16::SWSP
5703 *mips16:
5704 {
5705   unsigned32 instruction = instruction_0;
5706   signed_word op2 = (instruction >> 8) & 0x7;
5707   int offset = (instruction >> 0) & 0xff;
5708   signed_word op1 = 29;
5709   if (op2 < 2)
5710     op2 += 16;
5711   op2 = GPR[op2];
5712   if (have_extendval)
5713     {
5714       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5715       if (offset >= 0x8000)
5716         offset -= 0x10000;
5717       have_extendval = 0;
5718     }
5719   else
5720     {
5721       offset <<= 2;
5722     }
5723   op1 = GPR[op1];
5724   if (have_extendval)
5725     SignalException (ReservedInstruction, instruction);
5726   {
5727     address_word vaddr = ((unsigned64)op1 + offset);
5728     address_word paddr;
5729     int uncached;
5730     if ((vaddr & 3) != 0)
5731       SignalExceptionAddressStore();
5732     else
5733       {
5734         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5735           {
5736             unsigned64 memval = 0;
5737             unsigned64 memval1 = 0;
5738             unsigned64 mask = 0x7;
5739             unsigned int byte;
5740             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5741             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5742             memval = ((unsigned64) op2 << (8 * byte));
5743             {
5744               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5745             }
5746           }
5747       }
5748   }
5749 }
5750
5751
5752 01100010,VVVVVVVV,Q,s:I8:16::SWRASP
5753 *mips16:
5754 {
5755   unsigned32 instruction = instruction_0;
5756   int offset = (instruction >> 0) & 0xff;
5757   signed_word op2 = 31;
5758   signed_word op1 = 29;
5759   if (have_extendval)
5760     {
5761       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5762       if (offset >= 0x8000)
5763         offset -= 0x10000;
5764       have_extendval = 0;
5765     }
5766   else
5767     {
5768       offset <<= 2;
5769     }
5770   op2 = GPR[op2];
5771   op1 = GPR[op1];
5772   if (have_extendval)
5773     SignalException (ReservedInstruction, instruction);
5774   {
5775     address_word vaddr = ((unsigned64)op1 + offset);
5776     address_word paddr;
5777     int uncached;
5778     if ((vaddr & 3) != 0)
5779       SignalExceptionAddressStore();
5780     else
5781       {
5782         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5783           {
5784             unsigned64 memval = 0;
5785             unsigned64 memval1 = 0;
5786             unsigned64 mask = 0x7;
5787             unsigned int byte;
5788             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5789             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5790             memval = ((unsigned64) op2 << (8 * byte));
5791             {
5792               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5793             }
5794           }
5795       }
5796   }
5797 }
5798
5799
5800 01111,xxx,yyy,DDDDD:RRI:16::SD
5801 *mips16:
5802 {
5803   unsigned32 instruction = instruction_0;
5804   signed_word op1 = (instruction >> 8) & 0x7;
5805   signed_word op2 = (instruction >> 5) & 0x7;
5806   int offset = (instruction >> 0) & 0x1f;
5807   if (op1 < 2)
5808     op1 += 16;
5809   op1 = GPR[op1];
5810   if (op2 < 2)
5811     op2 += 16;
5812   op2 = GPR[op2];
5813   if (have_extendval)
5814     {
5815       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5816       if (offset >= 0x8000)
5817         offset -= 0x10000;
5818       have_extendval = 0;
5819     }
5820   else
5821     {
5822       offset <<= 3;
5823     }
5824   if (have_extendval)
5825     SignalException (ReservedInstruction, instruction);
5826   {
5827     address_word vaddr = ((unsigned64)op1 + offset);
5828     address_word paddr;
5829     int uncached;
5830     if ((vaddr & 7) != 0)
5831       SignalExceptionAddressStore();
5832     else
5833       {
5834         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5835           {
5836             unsigned64 memval = 0;
5837             unsigned64 memval1 = 0;
5838             memval = op2;
5839             {
5840               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5841             }
5842           }
5843       }
5844   }
5845 }
5846
5847
5848 11111001,yyy,5.RD,s:RI64:16::SDSP
5849 *mips16:
5850 {
5851   unsigned32 instruction = instruction_0;
5852   signed_word op2 = (instruction >> 5) & 0x7;
5853   int offset = (instruction >> 0) & 0x1f;
5854   signed_word op1 = 29;
5855   if (op2 < 2)
5856     op2 += 16;
5857   op2 = GPR[op2];
5858   if (have_extendval)
5859     {
5860       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5861       if (offset >= 0x8000)
5862         offset -= 0x10000;
5863       have_extendval = 0;
5864     }
5865   else
5866     {
5867       offset <<= 3;
5868     }
5869   op1 = GPR[op1];
5870   if (have_extendval)
5871     SignalException (ReservedInstruction, instruction);
5872   {
5873     address_word vaddr = ((unsigned64)op1 + offset);
5874     address_word paddr;
5875     int uncached;
5876     if ((vaddr & 7) != 0)
5877       SignalExceptionAddressStore();
5878     else
5879       {
5880         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5881           {
5882             unsigned64 memval = 0;
5883             unsigned64 memval1 = 0;
5884             memval = op2;
5885             {
5886               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5887             }
5888           }
5889       }
5890   }
5891 }
5892
5893
5894 11111010,CCCCCCCC,s,Q:I64:16::SDRASP
5895 *mips16:
5896 {
5897   unsigned32 instruction = instruction_0;
5898   int offset = (instruction >> 0) & 0xff;
5899   signed_word op1 = 29;
5900   signed_word op2 = 31;
5901   if (have_extendval)
5902     {
5903       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5904       if (offset >= 0x8000)
5905         offset -= 0x10000;
5906       have_extendval = 0;
5907     }
5908   else
5909     {
5910       offset <<= 3;
5911     }
5912   op1 = GPR[op1];
5913   op2 = GPR[op2];
5914   if (have_extendval)
5915     SignalException (ReservedInstruction, instruction);
5916   {
5917     address_word vaddr = ((unsigned64)op1 + offset);
5918     address_word paddr;
5919     int uncached;
5920     if ((vaddr & 7) != 0)
5921       SignalExceptionAddressStore();
5922     else
5923       {
5924         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5925           {
5926             unsigned64 memval = 0;
5927             unsigned64 memval1 = 0;
5928             memval = op2;
5929             {
5930               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5931             }
5932           }
5933       }
5934   }
5935 }
5936
5937
5938 // ALU Immediate Instructions
5939
5940
5941 01101,ddd,UUUUUUUU,Z:RI:16::LI
5942 *mips16:
5943 {
5944   unsigned32 instruction = instruction_0;
5945   int destreg = (instruction >> 8) & 0x7;
5946   int op2 = (instruction >> 0) & 0xff;
5947   signed_word op1 = 0;
5948   if (destreg < 2)
5949     destreg += 16;
5950   if (have_extendval)
5951     {
5952       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
5953       have_extendval = 0;
5954     }
5955   else
5956     {
5957     }
5958   if (have_extendval)
5959     SignalException (ReservedInstruction, instruction);
5960   {
5961     if (destreg != 0)
5962       GPR[destreg] = (op1 | op2);
5963   }
5964 }
5965
5966
5967 01000,xxx,ddd,04444:RRI_A:16::ADDIU
5968 *mips16:
5969 {
5970   unsigned32 instruction = instruction_0;
5971   signed_word op1 = (instruction >> 8) & 0x7;
5972   int destreg = (instruction >> 5) & 0x7;
5973   int op2 = (instruction >> 0) & 0xf;
5974   if (op1 < 2)
5975     op1 += 16;
5976   op1 = GPR[op1];
5977   if (destreg < 2)
5978     destreg += 16;
5979   if (have_extendval)
5980     {
5981       op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
5982       if (op2 >= 0x4000)
5983         op2 -= 0x8000;
5984       have_extendval = 0;
5985     }
5986   else
5987     {
5988       if (op2 >= 0x8)
5989         op2 -= 0x10;
5990     }
5991   if (have_extendval)
5992     SignalException (ReservedInstruction, instruction);
5993   {
5994     unsigned int temp = (unsigned int)(op1 + op2);
5995     signed int tempS = (signed int)temp;
5996     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
5997   }
5998 }
5999
6000
6001 01001,www,kkkkkkkk:RI:16::ADDIU8
6002 *mips16:
6003 {
6004   unsigned32 instruction = instruction_0;
6005   signed_word op1 = (instruction >> 8) & 0x7;
6006   int destreg;
6007   int op2 = (instruction >> 0) & 0xff;
6008   if (op1 < 2)
6009     op1 += 16;
6010   destreg = op1;
6011   op1 = GPR[op1];
6012   if (have_extendval)
6013     {
6014       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6015       if (op2 >= 0x8000)
6016         op2 -= 0x10000;
6017       have_extendval = 0;
6018     }
6019   else
6020     {
6021       if (op2 >= 0x80)
6022         op2 -= 0x100;
6023     }
6024   if (have_extendval)
6025     SignalException (ReservedInstruction, instruction);
6026   {
6027     unsigned int temp = (unsigned int)(op1 + op2);
6028     signed int tempS = (signed int)temp;
6029     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6030   }
6031 }
6032
6033
6034 01100011,KKKKKKKK,S:I8:16::ADJSP
6035 *mips16:
6036 {
6037   unsigned32 instruction = instruction_0;
6038   int op2 = (instruction >> 0) & 0xff;
6039   signed_word op1 = 29;
6040   int destreg;
6041   if (have_extendval)
6042     {
6043       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6044       if (op2 >= 0x8000)
6045         op2 -= 0x10000;
6046       have_extendval = 0;
6047     }
6048   else
6049     {
6050       if (op2 >= 0x80)
6051         op2 -= 0x100;
6052       op2 <<= 3;
6053     }
6054   destreg = op1;
6055   op1 = GPR[op1];
6056   if (have_extendval)
6057     SignalException (ReservedInstruction, instruction);
6058   {
6059     unsigned int temp = (unsigned int)(op1 + op2);
6060     signed int tempS = (signed int)temp;
6061     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6062   }
6063 }
6064
6065
6066 00001,ddd,AAAAAAAA,P:RI:16::ADDIUPC
6067 *mips16:
6068 {
6069   unsigned32 instruction = instruction_0;
6070   int destreg = (instruction >> 8) & 0x7;
6071   int op2 = (instruction >> 0) & 0xff;
6072   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
6073   if (destreg < 2)
6074     destreg += 16;
6075   if (have_extendval)
6076     {
6077       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6078       if (op2 >= 0x8000)
6079         op2 -= 0x10000;
6080       have_extendval = 0;
6081     }
6082   else
6083     {
6084       op2 <<= 2;
6085     }
6086   if (have_extendval)
6087     SignalException (ReservedInstruction, instruction);
6088   {
6089     unsigned int temp = (unsigned int)(op1 + op2);
6090     signed int tempS = (signed int)temp;
6091     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6092   }
6093 }
6094
6095
6096 00000,ddd,AAAAAAAA,s:RI:16::ADDIUSP
6097 *mips16:
6098 {
6099   unsigned32 instruction = instruction_0;
6100   int destreg = (instruction >> 8) & 0x7;
6101   int op2 = (instruction >> 0) & 0xff;
6102   signed_word op1 = 29;
6103   if (destreg < 2)
6104     destreg += 16;
6105   if (have_extendval)
6106     {
6107       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6108       if (op2 >= 0x8000)
6109         op2 -= 0x10000;
6110       have_extendval = 0;
6111     }
6112   else
6113     {
6114       op2 <<= 2;
6115     }
6116   op1 = GPR[op1];
6117   if (have_extendval)
6118     SignalException (ReservedInstruction, instruction);
6119   {
6120     unsigned int temp = (unsigned int)(op1 + op2);
6121     signed int tempS = (signed int)temp;
6122     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6123   }
6124 }
6125
6126
6127 01000,xxx,ddd,14444:RRI_A:16::DADDIU
6128 *mips16:
6129 {
6130   unsigned32 instruction = instruction_0;
6131   signed_word op1 = (instruction >> 8) & 0x7;
6132   int destreg = (instruction >> 5) & 0x7;
6133   int op2 = (instruction >> 0) & 0xf;
6134   if (op1 < 2)
6135     op1 += 16;
6136   op1 = GPR[op1];
6137   if (destreg < 2)
6138     destreg += 16;
6139   if (have_extendval)
6140     {
6141       op2 |= ((extendval & 0xf) << 11) | (extendval & 0x7f0);
6142       if (op2 >= 0x4000)
6143         op2 -= 0x8000;
6144       have_extendval = 0;
6145     }
6146   else
6147     {
6148       if (op2 >= 0x8)
6149         op2 -= 0x10;
6150     }
6151   if (have_extendval)
6152     SignalException (ReservedInstruction, instruction);
6153   {
6154     unsigned64 temp = (unsigned64)(op1 + op2);
6155     word64 tempS = (word64)temp;
6156     GPR[destreg] = (unsigned64)temp;
6157   }
6158 }
6159
6160
6161 11111101,www,jjjjj:RI64:16::DADDIU5
6162 *mips16:
6163 {
6164   unsigned32 instruction = instruction_0;
6165   signed_word op1 = (instruction >> 5) & 0x7;
6166   int destreg;
6167   int op2 = (instruction >> 0) & 0x1f;
6168   if (op1 < 2)
6169     op1 += 16;
6170   destreg = op1;
6171   op1 = GPR[op1];
6172   if (have_extendval)
6173     {
6174       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6175       if (op2 >= 0x8000)
6176         op2 -= 0x10000;
6177       have_extendval = 0;
6178     }
6179   else
6180     {
6181       if (op2 >= 0x10)
6182         op2 -= 0x20;
6183     }
6184   if (have_extendval)
6185     SignalException (ReservedInstruction, instruction);
6186   {
6187     unsigned64 temp = (unsigned64)(op1 + op2);
6188     word64 tempS = (word64)temp;
6189     GPR[destreg] = (unsigned64)temp;
6190   }
6191 }
6192
6193
6194 11111011,KKKKKKKK,S:I64:16::DADJSP
6195 *mips16:
6196 {
6197   unsigned32 instruction = instruction_0;
6198   int op2 = (instruction >> 0) & 0xff;
6199   signed_word op1 = 29;
6200   int destreg;
6201   if (have_extendval)
6202     {
6203       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6204       if (op2 >= 0x8000)
6205         op2 -= 0x10000;
6206       have_extendval = 0;
6207     }
6208   else
6209     {
6210       if (op2 >= 0x80)
6211         op2 -= 0x100;
6212       op2 <<= 3;
6213     }
6214   destreg = op1;
6215   op1 = GPR[op1];
6216   if (have_extendval)
6217     SignalException (ReservedInstruction, instruction);
6218   {
6219     unsigned64 temp = (unsigned64)(op1 + op2);
6220     word64 tempS = (word64)temp;
6221     GPR[destreg] = (unsigned64)temp;
6222   }
6223 }
6224
6225
6226 11111110,ddd,EEEEE,P:RI64:16::DADDIUPC
6227 *mips16:
6228 {
6229   unsigned32 instruction = instruction_0;
6230   int destreg = (instruction >> 5) & 0x7;
6231   int op2 = (instruction >> 0) & 0x1f;
6232   signed_word op1 = ((INDELAYSLOT () ? (INJALDELAYSLOT () ? IPC - 4 : IPC - 2) : (have_extendval ? IPC - 2 : IPC)) & ~ (unsigned64) 1) & ~ (unsigned64) 0x3;
6233   if (destreg < 2)
6234     destreg += 16;
6235   if (have_extendval)
6236     {
6237       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6238       if (op2 >= 0x8000)
6239         op2 -= 0x10000;
6240       have_extendval = 0;
6241     }
6242   else
6243     {
6244       op2 <<= 2;
6245     }
6246   if (have_extendval)
6247     SignalException (ReservedInstruction, instruction);
6248   {
6249     unsigned64 temp = (unsigned64)(op1 + op2);
6250     word64 tempS = (word64)temp;
6251     GPR[destreg] = (unsigned64)temp;
6252   }
6253 }
6254
6255
6256 11111111,ddd,EEEEE,s:RI64:16::DADDIUSP
6257 *mips16:
6258 {
6259   unsigned32 instruction = instruction_0;
6260   int destreg = (instruction >> 5) & 0x7;
6261   int op2 = (instruction >> 0) & 0x1f;
6262   signed_word op1 = 29;
6263   if (destreg < 2)
6264     destreg += 16;
6265   if (have_extendval)
6266     {
6267       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6268       if (op2 >= 0x8000)
6269         op2 -= 0x10000;
6270       have_extendval = 0;
6271     }
6272   else
6273     {
6274       op2 <<= 2;
6275     }
6276   op1 = GPR[op1];
6277   if (have_extendval)
6278     SignalException (ReservedInstruction, instruction);
6279   {
6280     unsigned64 temp = (unsigned64)(op1 + op2);
6281     word64 tempS = (word64)temp;
6282     GPR[destreg] = (unsigned64)temp;
6283   }
6284 }
6285
6286
6287 01010,xxx,88888888,T:RI:16::SLTI
6288 *mips16:
6289 {
6290   unsigned32 instruction = instruction_0;
6291   signed_word op1 = (instruction >> 8) & 0x7;
6292   int op2 = (instruction >> 0) & 0xff;
6293   int destreg = 24;
6294   if (op1 < 2)
6295     op1 += 16;
6296   op1 = GPR[op1];
6297   if (have_extendval)
6298     {
6299       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6300       if (op2 >= 0x8000)
6301         op2 -= 0x10000;
6302       have_extendval = 0;
6303     }
6304   else
6305     {
6306     }
6307   if (have_extendval)
6308     SignalException (ReservedInstruction, instruction);
6309   {
6310     if ((word64)op1 < (word64)op2)
6311       GPR[destreg] = 1;
6312     else
6313       GPR[destreg] = 0;
6314   }
6315 }
6316
6317
6318 01011,xxx,88888888,T:RI:16::SLTIU
6319 *mips16:
6320 {
6321   unsigned32 instruction = instruction_0;
6322   signed_word op1 = (instruction >> 8) & 0x7;
6323   int op2 = (instruction >> 0) & 0xff;
6324   int destreg = 24;
6325   if (op1 < 2)
6326     op1 += 16;
6327   op1 = GPR[op1];
6328   if (have_extendval)
6329     {
6330       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6331       if (op2 >= 0x8000)
6332         op2 -= 0x10000;
6333       have_extendval = 0;
6334     }
6335   else
6336     {
6337     }
6338   if (have_extendval)
6339     SignalException (ReservedInstruction, instruction);
6340   {
6341     if ((unsigned64)op1 < (unsigned64)op2)
6342       GPR[destreg] = 1;
6343     else
6344       GPR[destreg] = 0;
6345   }
6346 }
6347
6348
6349 11101,xxx,yyy,01010,T:RR:16::CMP
6350 *mips16:
6351 {
6352   unsigned32 instruction = instruction_0;
6353   signed_word op1 = (instruction >> 8) & 0x7;
6354   signed_word op2 = (instruction >> 5) & 0x7;
6355   int destreg = 24;
6356   if (op1 < 2)
6357     op1 += 16;
6358   op1 = GPR[op1];
6359   if (op2 < 2)
6360     op2 += 16;
6361   op2 = GPR[op2];
6362   if (have_extendval)
6363     SignalException (ReservedInstruction, instruction);
6364   {
6365     GPR[destreg] = (op1 ^ op2);
6366   }
6367 }
6368
6369
6370 01110,xxx,UUUUUUUU,T:RI:16::CMPI
6371 *mips16:
6372 {
6373   unsigned32 instruction = instruction_0;
6374   signed_word op1 = (instruction >> 8) & 0x7;
6375   int op2 = (instruction >> 0) & 0xff;
6376   int destreg = 24;
6377   if (op1 < 2)
6378     op1 += 16;
6379   op1 = GPR[op1];
6380   if (have_extendval)
6381     {
6382       op2 |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
6383       have_extendval = 0;
6384     }
6385   else
6386     {
6387     }
6388   if (have_extendval)
6389     SignalException (ReservedInstruction, instruction);
6390   {
6391     GPR[destreg] = (op1 ^ op2);
6392   }
6393 }
6394
6395
6396 // Two/Three Operand, Register-Type
6397
6398
6399 11100,xxx,yyy,ddd,01:RRR:16::ADDU
6400 *mips16:
6401 {
6402   unsigned32 instruction = instruction_0;
6403   signed_word op1 = (instruction >> 8) & 0x7;
6404   signed_word op2 = (instruction >> 5) & 0x7;
6405   int destreg = (instruction >> 2) & 0x7;
6406   if (op1 < 2)
6407     op1 += 16;
6408   op1 = GPR[op1];
6409   if (op2 < 2)
6410     op2 += 16;
6411   op2 = GPR[op2];
6412   if (destreg < 2)
6413     destreg += 16;
6414   if (have_extendval)
6415     SignalException (ReservedInstruction, instruction);
6416   {
6417     unsigned int temp = (unsigned int)(op1 + op2);
6418     signed int tempS = (signed int)temp;
6419     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6420   }
6421 }
6422
6423
6424 11100,xxx,yyy,ddd,11:RRR:16::SUBU
6425 *mips16:
6426 {
6427   unsigned32 instruction = instruction_0;
6428   signed_word op1 = (instruction >> 8) & 0x7;
6429   signed_word op2 = (instruction >> 5) & 0x7;
6430   int destreg = (instruction >> 2) & 0x7;
6431   if (op1 < 2)
6432     op1 += 16;
6433   op1 = GPR[op1];
6434   if (op2 < 2)
6435     op2 += 16;
6436   op2 = GPR[op2];
6437   if (destreg < 2)
6438     destreg += 16;
6439   if (have_extendval)
6440     SignalException (ReservedInstruction, instruction);
6441   {
6442     unsigned int temp = (unsigned int)(op1 - op2);
6443     signed int tempS = (signed int)temp;
6444     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6445   }
6446 }
6447
6448
6449 11100,xxx,yyy,ddd,00:RRR:16::DADDU
6450 *mips16:
6451 {
6452   unsigned32 instruction = instruction_0;
6453   signed_word op1 = (instruction >> 8) & 0x7;
6454   signed_word op2 = (instruction >> 5) & 0x7;
6455   int destreg = (instruction >> 2) & 0x7;
6456   if (op1 < 2)
6457     op1 += 16;
6458   op1 = GPR[op1];
6459   if (op2 < 2)
6460     op2 += 16;
6461   op2 = GPR[op2];
6462   if (destreg < 2)
6463     destreg += 16;
6464   if (have_extendval)
6465     SignalException (ReservedInstruction, instruction);
6466   {
6467     unsigned64 temp = (unsigned64)(op1 + op2);
6468     word64 tempS = (word64)temp;
6469     GPR[destreg] = (unsigned64)temp;
6470   }
6471 }
6472
6473
6474 11100,xxx,yyy,ddd,10:RRR:16::DSUBU
6475 *mips16:
6476 {
6477   unsigned32 instruction = instruction_0;
6478   signed_word op1 = (instruction >> 8) & 0x7;
6479   signed_word op2 = (instruction >> 5) & 0x7;
6480   int destreg = (instruction >> 2) & 0x7;
6481   if (op1 < 2)
6482     op1 += 16;
6483   op1 = GPR[op1];
6484   if (op2 < 2)
6485     op2 += 16;
6486   op2 = GPR[op2];
6487   if (destreg < 2)
6488     destreg += 16;
6489   if (have_extendval)
6490     SignalException (ReservedInstruction, instruction);
6491   {
6492     unsigned64 temp = (unsigned64)(op1 - op2);
6493     word64 tempS = (word64)temp;
6494     GPR[destreg] = (unsigned64)temp;
6495   }
6496 }
6497
6498
6499 11101,xxx,yyy,00010,T:RR:16::SLT
6500 *mips16:
6501 {
6502   unsigned32 instruction = instruction_0;
6503   signed_word op1 = (instruction >> 8) & 0x7;
6504   signed_word op2 = (instruction >> 5) & 0x7;
6505   int destreg = 24;
6506   if (op1 < 2)
6507     op1 += 16;
6508   op1 = GPR[op1];
6509   if (op2 < 2)
6510     op2 += 16;
6511   op2 = GPR[op2];
6512   if (have_extendval)
6513     SignalException (ReservedInstruction, instruction);
6514   {
6515     if ((word64)op1 < (word64)op2)
6516       GPR[destreg] = 1;
6517     else
6518       GPR[destreg] = 0;
6519   }
6520 }
6521
6522
6523 11101,xxx,yyy,00011,T:RR:16::SLTU
6524 *mips16:
6525 {
6526   unsigned32 instruction = instruction_0;
6527   signed_word op1 = (instruction >> 8) & 0x7;
6528   signed_word op2 = (instruction >> 5) & 0x7;
6529   int destreg = 24;
6530   if (op1 < 2)
6531     op1 += 16;
6532   op1 = GPR[op1];
6533   if (op2 < 2)
6534     op2 += 16;
6535   op2 = GPR[op2];
6536   if (have_extendval)
6537     SignalException (ReservedInstruction, instruction);
6538   {
6539     if ((unsigned64)op1 < (unsigned64)op2)
6540       GPR[destreg] = 1;
6541     else
6542       GPR[destreg] = 0;
6543   }
6544 }
6545
6546
6547 11101,ddd,yyy,01011,Z:RR:16::NEG
6548 *mips16:
6549 {
6550   unsigned32 instruction = instruction_0;
6551   int destreg = (instruction >> 8) & 0x7;
6552   signed_word op2 = (instruction >> 5) & 0x7;
6553   signed_word op1 = 0;
6554   if (destreg < 2)
6555     destreg += 16;
6556   if (op2 < 2)
6557     op2 += 16;
6558   op2 = GPR[op2];
6559   if (have_extendval)
6560     SignalException (ReservedInstruction, instruction);
6561   {
6562     unsigned int temp = (unsigned int)(op1 - op2);
6563     signed int tempS = (signed int)temp;
6564     GPR[destreg] = SIGNEXTEND(((unsigned64)temp),32);
6565   }
6566 }
6567
6568
6569 11101,www,yyy,01100:RR:16::AND
6570 *mips16:
6571 {
6572   unsigned32 instruction = instruction_0;
6573   signed_word op1 = (instruction >> 8) & 0x7;
6574   int destreg;
6575   signed_word op2 = (instruction >> 5) & 0x7;
6576   if (op1 < 2)
6577     op1 += 16;
6578   destreg = op1;
6579   op1 = GPR[op1];
6580   if (op2 < 2)
6581     op2 += 16;
6582   op2 = GPR[op2];
6583   if (have_extendval)
6584     SignalException (ReservedInstruction, instruction);
6585   {
6586     GPR[destreg] = (op1 & op2);
6587   }
6588 }
6589
6590
6591 11101,www,yyy,01101:RR:16::OR
6592 *mips16:
6593 {
6594   unsigned32 instruction = instruction_0;
6595   signed_word op1 = (instruction >> 8) & 0x7;
6596   int destreg;
6597   signed_word op2 = (instruction >> 5) & 0x7;
6598   if (op1 < 2)
6599     op1 += 16;
6600   destreg = op1;
6601   op1 = GPR[op1];
6602   if (op2 < 2)
6603     op2 += 16;
6604   op2 = GPR[op2];
6605   if (have_extendval)
6606     SignalException (ReservedInstruction, instruction);
6607   {
6608     if (destreg != 0)
6609       GPR[destreg] = (op1 | op2);
6610   }
6611 }
6612
6613
6614 11101,www,yyy,01110:RR:16::XOR
6615 *mips16:
6616 {
6617   unsigned32 instruction = instruction_0;
6618   signed_word op1 = (instruction >> 8) & 0x7;
6619   int destreg;
6620   signed_word op2 = (instruction >> 5) & 0x7;
6621   if (op1 < 2)
6622     op1 += 16;
6623   destreg = op1;
6624   op1 = GPR[op1];
6625   if (op2 < 2)
6626     op2 += 16;
6627   op2 = GPR[op2];
6628   if (have_extendval)
6629     SignalException (ReservedInstruction, instruction);
6630   {
6631     GPR[destreg] = (op1 ^ op2);
6632   }
6633 }
6634
6635
6636 11101,ddd,yyy,01111,Z:RR:16::NOT
6637 *mips16:
6638 {
6639   unsigned32 instruction = instruction_0;
6640   int destreg = (instruction >> 8) & 0x7;
6641   signed_word op2 = (instruction >> 5) & 0x7;
6642   signed_word op1 = 0;
6643   if (destreg < 2)
6644     destreg += 16;
6645   if (op2 < 2)
6646     op2 += 16;
6647   op2 = GPR[op2];
6648   if (have_extendval)
6649     SignalException (ReservedInstruction, instruction);
6650   {
6651     if (destreg != 0)
6652       GPR[destreg] = ~(op1 | op2);
6653   }
6654 }
6655
6656
6657 01100111,ddd,XXXXX,z:I8_MOVR32:16::MOVR32
6658 *mips16:
6659 {
6660   unsigned32 instruction = instruction_0;
6661   int destreg = (instruction >> 5) & 0x7;
6662   signed_word op1 = (instruction >> 0) & 0x1f;
6663   signed_word op2 = 0;
6664   if (destreg < 2)
6665     destreg += 16;
6666   op1 = GPR[op1];
6667   if (have_extendval)
6668     SignalException (ReservedInstruction, instruction);
6669   {
6670     if (destreg != 0)
6671       GPR[destreg] = (op1 | op2);
6672   }
6673 }
6674
6675
6676 01100101,YYYYY,xxx,z:I8_MOV32R:16::MOV32R
6677 *mips16:
6678 {
6679   unsigned32 instruction = instruction_0;
6680   int destreg = (instruction >> 3) & 0x1f;
6681   signed_word op1 = (instruction >> 0) & 0x7;
6682   signed_word op2 = 0;
6683   destreg = (destreg >> 2) | ((destreg & 3) << 3);
6684   if (op1 < 2)
6685     op1 += 16;
6686   op1 = GPR[op1];
6687   if (have_extendval)
6688     SignalException (ReservedInstruction, instruction);
6689   {
6690     if (destreg != 0)
6691       GPR[destreg] = (op1 | op2);
6692   }
6693 }
6694
6695
6696 00110,ddd,yyy,sss,00:ISHIFT:16::SLL
6697 *mips16:
6698 {
6699   unsigned32 instruction = instruction_0;
6700   int destreg = (instruction >> 8) & 0x7;
6701   signed_word op2 = (instruction >> 5) & 0x7;
6702   int op1 = (instruction >> 2) & 0x7;
6703   if (destreg < 2)
6704     destreg += 16;
6705   if (op2 < 2)
6706     op2 += 16;
6707   op2 = GPR[op2];
6708   if (have_extendval)
6709     {
6710       op1 = (extendval >> 6) & 0x1f;
6711       have_extendval = 0;
6712     }
6713   else
6714     {
6715       if (op1 == 0)
6716         op1 = 8;
6717     }
6718   if (have_extendval)
6719     SignalException (ReservedInstruction, instruction);
6720   {
6721     GPR[destreg] = ((unsigned64)op2 << op1);
6722     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6723   }
6724 }
6725
6726
6727 00110,ddd,yyy,sss,10:ISHIFT:16::SRL
6728 *mips16:
6729 {
6730   unsigned32 instruction = instruction_0;
6731   int destreg = (instruction >> 8) & 0x7;
6732   signed_word op2 = (instruction >> 5) & 0x7;
6733   int op1 = (instruction >> 2) & 0x7;
6734   if (destreg < 2)
6735     destreg += 16;
6736   if (op2 < 2)
6737     op2 += 16;
6738   op2 = GPR[op2];
6739   if (have_extendval)
6740     {
6741       op1 = (extendval >> 6) & 0x1f;
6742       have_extendval = 0;
6743     }
6744   else
6745     {
6746       if (op1 == 0)
6747         op1 = 8;
6748     }
6749   if (have_extendval)
6750     SignalException (ReservedInstruction, instruction);
6751   {
6752     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6753     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6754   }
6755 }
6756
6757
6758 00110,ddd,yyy,sss,11:ISHIFT:16::SRA
6759 *mips16:
6760 {
6761   unsigned32 instruction = instruction_0;
6762   int destreg = (instruction >> 8) & 0x7;
6763   signed_word op2 = (instruction >> 5) & 0x7;
6764   int op1 = (instruction >> 2) & 0x7;
6765   if (destreg < 2)
6766     destreg += 16;
6767   if (op2 < 2)
6768     op2 += 16;
6769   op2 = GPR[op2];
6770   if (have_extendval)
6771     {
6772       op1 = (extendval >> 6) & 0x1f;
6773       have_extendval = 0;
6774     }
6775   else
6776     {
6777       if (op1 == 0)
6778         op1 = 8;
6779     }
6780   if (have_extendval)
6781     SignalException (ReservedInstruction, instruction);
6782   {
6783     unsigned int highbit = (unsigned int)1 << 31;
6784     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6785     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
6786     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6787   }
6788 }
6789
6790
6791 11101,xxx,vvv,00100:RR:16::SLLV
6792 *mips16:
6793 {
6794   unsigned32 instruction = instruction_0;
6795   signed_word op1 = (instruction >> 8) & 0x7;
6796   signed_word op2 = (instruction >> 5) & 0x7;
6797   int destreg;
6798   if (op1 < 2)
6799     op1 += 16;
6800   op1 = GPR[op1];
6801   if (op2 < 2)
6802     op2 += 16;
6803   destreg = op2;
6804   op2 = GPR[op2];
6805   if (have_extendval)
6806     SignalException (ReservedInstruction, instruction);
6807   {
6808     op1 &= 0x1F;
6809     GPR[destreg] = ((unsigned64)op2 << op1);
6810     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6811   }
6812 }
6813
6814
6815 11101,xxx,vvv,00110:RR:16::SRLV
6816 *mips16:
6817 {
6818   unsigned32 instruction = instruction_0;
6819   signed_word op1 = (instruction >> 8) & 0x7;
6820   signed_word op2 = (instruction >> 5) & 0x7;
6821   int destreg;
6822   if (op1 < 2)
6823     op1 += 16;
6824   op1 = GPR[op1];
6825   if (op2 < 2)
6826     op2 += 16;
6827   destreg = op2;
6828   op2 = GPR[op2];
6829   if (have_extendval)
6830     SignalException (ReservedInstruction, instruction);
6831   {
6832     op1 &= 0x1F;
6833     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6834     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6835   }
6836 }
6837
6838
6839 11101,xxx,vvv,00111:RR:16::SRAV
6840 *mips16:
6841 {
6842   unsigned32 instruction = instruction_0;
6843   signed_word op1 = (instruction >> 8) & 0x7;
6844   signed_word op2 = (instruction >> 5) & 0x7;
6845   int destreg;
6846   if (op1 < 2)
6847     op1 += 16;
6848   op1 = GPR[op1];
6849   if (op2 < 2)
6850     op2 += 16;
6851   destreg = op2;
6852   op2 = GPR[op2];
6853   if (have_extendval)
6854     SignalException (ReservedInstruction, instruction);
6855   {
6856     unsigned int highbit = (unsigned int)1 << 31;
6857     op1 &= 0x1F;
6858     GPR[destreg] = ((unsigned64)(op2 & 0xFFFFFFFF) >> op1);
6859     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned int)1 << op1) - 1) << (32 - op1)) : 0);
6860     GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
6861   }
6862 }
6863
6864
6865 00110,ddd,yyy,[[[,01:ISHIFT:16::DSLL
6866 *mips16:
6867 {
6868   unsigned32 instruction = instruction_0;
6869   int destreg = (instruction >> 8) & 0x7;
6870   signed_word op2 = (instruction >> 5) & 0x7;
6871   int op1 = (instruction >> 2) & 0x7;
6872   if (destreg < 2)
6873     destreg += 16;
6874   if (op2 < 2)
6875     op2 += 16;
6876   op2 = GPR[op2];
6877   if (have_extendval)
6878     {
6879       op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6880       have_extendval = 0;
6881     }
6882   else
6883     {
6884       if (op1 == 0)
6885         op1 = 8;
6886     }
6887   if (have_extendval)
6888     SignalException (ReservedInstruction, instruction);
6889   {
6890     GPR[destreg] = ((unsigned64)op2 << op1);
6891   }
6892 }
6893
6894
6895 11101,XXX,vvv,01000:RR:16::DSRL
6896 *mips16:
6897 {
6898   unsigned32 instruction = instruction_0;
6899   int op1 = (instruction >> 8) & 0x7;
6900   signed_word op2 = (instruction >> 5) & 0x7;
6901   int destreg;
6902   if (have_extendval)
6903     {
6904       op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6905       have_extendval = 0;
6906     }
6907   else
6908     {
6909       if (op1 == 0)
6910         op1 = 8;
6911     }
6912   if (op2 < 2)
6913     op2 += 16;
6914   destreg = op2;
6915   op2 = GPR[op2];
6916   if (have_extendval)
6917     SignalException (ReservedInstruction, instruction);
6918   {
6919     GPR[destreg] = ((unsigned64)(op2) >> op1);
6920   }
6921 }
6922
6923
6924 11101,xxx,vvv,10011:RR:16::DSRA
6925 *mips16:
6926 {
6927   unsigned32 instruction = instruction_0;
6928   int op1 = (instruction >> 8) & 0x7;
6929   signed_word op2 = (instruction >> 5) & 0x7;
6930   int destreg;
6931   if (have_extendval)
6932     {
6933       op1 = ((extendval >> 6) & 0x1f) | (extendval & 0x20);
6934       have_extendval = 0;
6935     }
6936   else
6937     {
6938       if (op1 == 0)
6939         op1 = 8;
6940     }
6941   if (op2 < 2)
6942     op2 += 16;
6943   destreg = op2;
6944   op2 = GPR[op2];
6945   if (have_extendval)
6946     SignalException (ReservedInstruction, instruction);
6947   {
6948     unsigned64 highbit = (unsigned64)1 << 63;
6949     GPR[destreg] = ((unsigned64)(op2) >> op1);
6950     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
6951   }
6952 }
6953
6954
6955 11101,xxx,vvv,10100:RR:16::DSLLV
6956 *mips16:
6957 {
6958   unsigned32 instruction = instruction_0;
6959   signed_word op1 = (instruction >> 8) & 0x7;
6960   signed_word op2 = (instruction >> 5) & 0x7;
6961   int destreg;
6962   if (op1 < 2)
6963     op1 += 16;
6964   op1 = GPR[op1];
6965   if (op2 < 2)
6966     op2 += 16;
6967   destreg = op2;
6968   op2 = GPR[op2];
6969   if (have_extendval)
6970     SignalException (ReservedInstruction, instruction);
6971   {
6972     op1 &= 0x3F;
6973     GPR[destreg] = ((unsigned64)op2 << op1);
6974   }
6975 }
6976
6977
6978 11101,xxx,vvv,10110:RR:16::DSRLV
6979 *mips16:
6980 {
6981   unsigned32 instruction = instruction_0;
6982   signed_word op1 = (instruction >> 8) & 0x7;
6983   signed_word op2 = (instruction >> 5) & 0x7;
6984   int destreg;
6985   if (op1 < 2)
6986     op1 += 16;
6987   op1 = GPR[op1];
6988   if (op2 < 2)
6989     op2 += 16;
6990   destreg = op2;
6991   op2 = GPR[op2];
6992   if (have_extendval)
6993     SignalException (ReservedInstruction, instruction);
6994   {
6995     op1 &= 0x3F;
6996     GPR[destreg] = ((unsigned64)(op2) >> op1);
6997   }
6998 }
6999
7000
7001 11101,xxx,vvv,10111:RR:16::DSRAV
7002 *mips16:
7003 {
7004   unsigned32 instruction = instruction_0;
7005   signed_word op1 = (instruction >> 8) & 0x7;
7006   signed_word op2 = (instruction >> 5) & 0x7;
7007   int destreg;
7008   if (op1 < 2)
7009     op1 += 16;
7010   op1 = GPR[op1];
7011   if (op2 < 2)
7012     op2 += 16;
7013   destreg = op2;
7014   op2 = GPR[op2];
7015   if (have_extendval)
7016     SignalException (ReservedInstruction, instruction);
7017   {
7018     unsigned64 highbit = (unsigned64)1 << 63;
7019     op1 &= 0x3F;
7020     GPR[destreg] = ((unsigned64)(op2) >> op1);
7021     GPR[destreg] |= (op1 != 0 && (op2 & highbit) ? ((((unsigned64)1 << op1) - 1) << (64 - op1)) : 0);
7022   }
7023 }
7024
7025
7026 // Multiply /Divide Instructions
7027
7028
7029 11101,xxx,yyy,11000:RR:16::MULT
7030 *mips16:
7031 {
7032   unsigned32 instruction = instruction_0;
7033   signed_word op1 = (instruction >> 8) & 0x7;
7034   signed_word op2 = (instruction >> 5) & 0x7;
7035   if (op1 < 2)
7036     op1 += 16;
7037   op1 = GPR[op1];
7038   if (op2 < 2)
7039     op2 += 16;
7040   op2 = GPR[op2];
7041   if (have_extendval)
7042     SignalException (ReservedInstruction, instruction);
7043   {
7044     CHECKHILO("Multiplication");
7045     {
7046       unsigned64 temp = ((word64) op1 * (word64) op2);
7047       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7048       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7049     }
7050   }
7051 }
7052
7053
7054 11101,xxx,yyy,11001:RR:16::MULTU
7055 *mips16:
7056 {
7057   unsigned32 instruction = instruction_0;
7058   signed_word op1 = (instruction >> 8) & 0x7;
7059   signed_word op2 = (instruction >> 5) & 0x7;
7060   if (op1 < 2)
7061     op1 += 16;
7062   op1 = GPR[op1];
7063   if (op2 < 2)
7064     op2 += 16;
7065   op2 = GPR[op2];
7066   if (have_extendval)
7067     SignalException (ReservedInstruction, instruction);
7068   {
7069     CHECKHILO("Multiplication");
7070     {
7071       unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
7072       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7073       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7074     }
7075   }
7076 }
7077
7078
7079 11101,xxx,yyy,11010:RR:16::DIV
7080 *mips16:
7081 {
7082   unsigned32 instruction = instruction_0;
7083   signed_word op1 = (instruction >> 8) & 0x7;
7084   signed_word op2 = (instruction >> 5) & 0x7;
7085   if (op1 < 2)
7086     op1 += 16;
7087   op1 = GPR[op1];
7088   if (op2 < 2)
7089     op2 += 16;
7090   op2 = GPR[op2];
7091   if (have_extendval)
7092     SignalException (ReservedInstruction, instruction);
7093   {
7094     CHECKHILO("Division");
7095     {
7096       int d1 = op1;
7097       int d2 = op2;
7098       if (d2 == 0)
7099         {
7100           LO = SIGNEXTEND(0x80000000,32);
7101           HI = SIGNEXTEND(0,32);
7102         }
7103       else if (d2 == -1 && d1 == 0x80000000)
7104         {
7105           LO = SIGNEXTEND(0x80000000,32);
7106           HI = SIGNEXTEND(0,32);
7107         }
7108       else
7109         {
7110           LO = SIGNEXTEND((d1 / d2),32);
7111           HI = SIGNEXTEND((d1 % d2),32);
7112         }
7113     }
7114   }
7115 }
7116
7117
7118 11101,xxx,yyy,11011:RR:16::DIVU
7119 *mips16:
7120 {
7121   unsigned32 instruction = instruction_0;
7122   signed_word op1 = (instruction >> 8) & 0x7;
7123   signed_word op2 = (instruction >> 5) & 0x7;
7124   if (op1 < 2)
7125     op1 += 16;
7126   op1 = GPR[op1];
7127   if (op2 < 2)
7128     op2 += 16;
7129   op2 = GPR[op2];
7130   if (have_extendval)
7131     SignalException (ReservedInstruction, instruction);
7132   {
7133     CHECKHILO("Division");
7134     {
7135       unsigned int d1 = op1;
7136       unsigned int d2 = op2;
7137       if (d2 == 0)
7138         {
7139           LO = SIGNEXTEND(0x80000000,32);
7140           HI = SIGNEXTEND(0,32);
7141         }
7142       else if (d2 == -1 && d1 == 0x80000000)
7143         {
7144           LO = SIGNEXTEND(0x80000000,32);
7145           HI = SIGNEXTEND(0,32);
7146         }
7147       else
7148         {
7149           LO = SIGNEXTEND((d1 / d2),32);
7150           HI = SIGNEXTEND((d1 % d2),32);
7151         }
7152     }
7153   }
7154 }
7155
7156
7157 11101,ddd,00010000:RR:16::MFHI
7158 *mips16:
7159 {
7160   unsigned32 instruction = instruction_0;
7161   int destreg = (instruction >> 8) & 0x7;
7162   if (destreg < 2)
7163     destreg += 16;
7164   if (have_extendval)
7165     SignalException (ReservedInstruction, instruction);
7166   {
7167     GPR[destreg] = HI;
7168     HIACCESS = 3; /* 3rd instruction will be safe */
7169   }
7170 }
7171
7172
7173 11101,ddd,00010010:RR:16::MFLO
7174 *mips16:
7175 {
7176   unsigned32 instruction = instruction_0;
7177   int destreg = (instruction >> 8) & 0x7;
7178   if (destreg < 2)
7179     destreg += 16;
7180   if (have_extendval)
7181     SignalException (ReservedInstruction, instruction);
7182   {
7183     GPR[destreg] = LO;
7184     LOACCESS = 3; /* 3rd instruction will be safe */
7185   }
7186 }
7187
7188
7189 11101,xxx,yyy,11100:RR:16::DMULT
7190 *mips16:
7191 {
7192   unsigned32 instruction = instruction_0;
7193   signed_word op1 = (instruction >> 8) & 0x7;
7194   signed_word op2 = (instruction >> 5) & 0x7;
7195   if (op1 < 2)
7196     op1 += 16;
7197   op1 = GPR[op1];
7198   if (op2 < 2)
7199     op2 += 16;
7200   op2 = GPR[op2];
7201   if (have_extendval)
7202     SignalException (ReservedInstruction, instruction);
7203   {
7204     CHECKHILO("Multiplication");
7205     {
7206       unsigned64 mid;
7207       unsigned64 midhi;
7208       unsigned64 temp;
7209       int sign = 0;
7210       if (op1 < 0) { op1 = - op1; ++sign; }
7211       if (op2 < 0) { op2 = - op2; ++sign; }
7212       LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
7213       HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
7214       mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
7215       midhi = SET64HI(VL4_8(mid));
7216       temp = (LO + midhi);
7217       if ((temp == midhi) ? (LO != 0) : (temp < midhi))
7218         HI += 1;
7219       HI += VH4_8(mid);
7220       mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
7221       midhi = SET64HI(VL4_8(mid));
7222       LO = (temp + midhi);
7223       if ((LO == midhi) ? (temp != 0) : (LO < midhi))
7224         HI += 1;
7225       HI += VH4_8(mid);
7226       if (sign & 1) { LO = - LO; HI = (LO == 0 ? 0 : -1) - HI; }
7227     }
7228   }
7229 }
7230
7231
7232 11101,xxx,yyy,11101:RR:16::DMULTU
7233 *mips16:
7234 {
7235   unsigned32 instruction = instruction_0;
7236   signed_word op1 = (instruction >> 8) & 0x7;
7237   signed_word op2 = (instruction >> 5) & 0x7;
7238   if (op1 < 2)
7239     op1 += 16;
7240   op1 = GPR[op1];
7241   if (op2 < 2)
7242     op2 += 16;
7243   op2 = GPR[op2];
7244   if (have_extendval)
7245     SignalException (ReservedInstruction, instruction);
7246   {
7247     CHECKHILO("Multiplication");
7248     {
7249       unsigned64 mid;
7250       unsigned64 midhi;
7251       unsigned64 temp;
7252       LO = ((unsigned64)VL4_8(op1) * VL4_8(op2));
7253       HI = ((unsigned64)VH4_8(op1) * VH4_8(op2));
7254       mid = ((unsigned64)VH4_8(op1) * VL4_8(op2));
7255       midhi = SET64HI(VL4_8(mid));
7256       temp = (LO + midhi);
7257       if ((temp == midhi) ? (LO != 0) : (temp < midhi))
7258         HI += 1;
7259       HI += VH4_8(mid);
7260       mid = ((unsigned64)VL4_8(op1) * VH4_8(op2));
7261       midhi = SET64HI(VL4_8(mid));
7262       LO = (temp + midhi);
7263       if ((LO == midhi) ? (temp != 0) : (LO < midhi))
7264         HI += 1;
7265       HI += VH4_8(mid);
7266     }
7267   }
7268 }
7269
7270
7271 11101,xxx,yyy,11110:RR:16::DDIV
7272 *mips16:
7273 {
7274   unsigned32 instruction = instruction_0;
7275   signed_word op1 = (instruction >> 8) & 0x7;
7276   signed_word op2 = (instruction >> 5) & 0x7;
7277   if (op1 < 2)
7278     op1 += 16;
7279   op1 = GPR[op1];
7280   if (op2 < 2)
7281     op2 += 16;
7282   op2 = GPR[op2];
7283   if (have_extendval)
7284     SignalException (ReservedInstruction, instruction);
7285   {
7286     CHECKHILO("Division");
7287     {
7288       word64 d1 = op1;
7289       word64 d2 = op2;
7290       if (d2 == 0)
7291         {
7292           LO = SIGNED64 (0x8000000000000000);
7293           HI = 0;
7294         }
7295       else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
7296         {
7297           LO = SIGNED64 (0x8000000000000000);
7298           HI = 0;
7299         }
7300       else
7301         {
7302           LO = (d1 / d2);
7303           HI = (d1 % d2);
7304         }
7305     }
7306   }
7307 }
7308
7309
7310 11101,xxx,yyy,11111:RR:16::DDIVU
7311 *mips16:
7312 {
7313   unsigned32 instruction = instruction_0;
7314   signed_word op1 = (instruction >> 8) & 0x7;
7315   signed_word op2 = (instruction >> 5) & 0x7;
7316   if (op1 < 2)
7317     op1 += 16;
7318   op1 = GPR[op1];
7319   if (op2 < 2)
7320     op2 += 16;
7321   op2 = GPR[op2];
7322   if (have_extendval)
7323     SignalException (ReservedInstruction, instruction);
7324   {
7325     CHECKHILO("Division");
7326     {
7327       unsigned64 d1 = op1;
7328       unsigned64 d2 = op2;
7329       if (d2 == 0)
7330         {
7331           LO = SIGNED64 (0x8000000000000000);
7332           HI = 0;
7333         }
7334       else if (d2 == -1 && d1 == SIGNED64 (0x8000000000000000))
7335         {
7336           LO = SIGNED64 (0x8000000000000000);
7337           HI = 0;
7338         }
7339       else
7340         {
7341           LO = (d1 / d2);
7342           HI = (d1 % d2);
7343         }
7344     }
7345   }
7346 }
7347
7348
7349 // Jump and Branch Instructions
7350
7351
7352 // JALX
7353 // JAL
7354 00011,aaaaaaaaaaa:I:16::JAL
7355 *mips16:
7356 {
7357   unsigned32 instruction = instruction_0;
7358   unsigned_word op1 = (instruction >> 0) & 0x7ff;
7359   {
7360     address_word paddr;
7361     int uncached;
7362     if (AddressTranslation (PC &~ (unsigned64) 1, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL))
7363       {
7364         unsigned64 memval;
7365         unsigned int reverse = (ReverseEndian ? 3 : 0);
7366         unsigned int bigend = (BigEndianCPU ? 3 : 0);
7367         unsigned int byte;
7368         paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 1)));
7369         LoadMemory (&memval,0,uncached, AccessLength_HALFWORD, paddr, PC, isINSTRUCTION, isREAL);
7370         byte = (((PC &~ (unsigned64) 1) & 0x7) ^ (bigend << 1));
7371         memval = (memval >> (8 * byte)) & 0xffff;
7372         op1 = (((op1 & 0x1f) << 23)
7373                | ((op1 & 0x3e0) << 13)
7374                | (memval << 2));
7375         if ((instruction & 0x400) == 0)
7376           op1 |= 1;
7377         PC += 2;
7378       }
7379   }
7380   op1 |= PC & ~ (unsigned64) 0x0fffffff;
7381   if (have_extendval)
7382     SignalException (ReservedInstruction, instruction);
7383   {
7384     int destreg = 31;
7385     GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
7386     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
7387        so we just truncate it to 32 bits here.  */
7388     op1 = VL4_8(op1);
7389     /* NOTE: The jump occurs AFTER the next instruction has been executed */
7390     DELAY_SLOT op1;
7391     JALDELAYSLOT();
7392   }
7393 }
7394
7395
7396 11101,xxx,00000000:RR:16::JR
7397 *mips16:
7398 {
7399   unsigned32 instruction = instruction_0;
7400   signed_word op1 = (instruction >> 8) & 0x7;
7401   if (op1 < 2)
7402     op1 += 16;
7403   op1 = GPR[op1];
7404   if (have_extendval)
7405     SignalException (ReservedInstruction, instruction);
7406   {
7407     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
7408        so we just truncate it to 32 bits here.  */
7409     op1 = VL4_8(op1);
7410     /* NOTE: The jump occurs AFTER the next instruction has been executed */
7411     DELAY_SLOT op1;
7412     DELAYSLOT();
7413   }
7414 }
7415
7416
7417 1110100000100000,r:RR:16::JRRA
7418 *mips16:
7419 {
7420   unsigned32 instruction = instruction_0;
7421   signed_word op1 = 31;
7422   op1 = GPR[op1];
7423   if (have_extendval)
7424     SignalException (ReservedInstruction, instruction);
7425   {
7426     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
7427        so we just truncate it to 32 bits here.  */
7428     op1 = VL4_8(op1);
7429     /* NOTE: The jump occurs AFTER the next instruction has been executed */
7430     DELAY_SLOT op1;
7431     DELAYSLOT();
7432   }
7433 }
7434
7435
7436 11101,xxx,01000000,R:RR:16::JALR
7437 *mips16:
7438 {
7439   unsigned32 instruction = instruction_0;
7440   signed_word op1 = (instruction >> 8) & 0x7;
7441   int destreg = 31;
7442   if (op1 < 2)
7443     op1 += 16;
7444   op1 = GPR[op1];
7445   if (have_extendval)
7446     SignalException (ReservedInstruction, instruction);
7447   {
7448     GPR[destreg] = (PC + 2); /* NOTE: The PC is already 2 ahead within the simulator */
7449     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
7450        so we just truncate it to 32 bits here.  */
7451     op1 = VL4_8(op1);
7452     /* NOTE: The jump occurs AFTER the next instruction has been executed */
7453     DELAY_SLOT op1;
7454     DELAYSLOT();
7455   }
7456 }
7457
7458
7459 00100,xxx,pppppppp,z:RI:16::BEQZ
7460 *mips16:
7461 {
7462   unsigned32 instruction = instruction_0;
7463   signed_word op1 = (instruction >> 8) & 0x7;
7464   int offset = (instruction >> 0) & 0xff;
7465   signed_word op2 = 0;
7466   if (op1 < 2)
7467     op1 += 16;
7468   op1 = GPR[op1];
7469   if (have_extendval)
7470     {
7471       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7472       if (offset >= 0x8000)
7473         offset -= 0x10000;
7474       have_extendval = 0;
7475     }
7476   else
7477     {
7478       if (offset >= 0x80)
7479         offset -= 0x100;
7480     }
7481   offset *= 2;
7482   if (have_extendval)
7483     SignalException (ReservedInstruction, instruction);
7484   {
7485     int condition = (op1 == op2);
7486     if (condition)
7487       PC = PC + offset;
7488   }
7489 }
7490
7491
7492 00101,xxx,pppppppp,z:RI:16::BNEZ
7493 *mips16:
7494 {
7495   unsigned32 instruction = instruction_0;
7496   signed_word op1 = (instruction >> 8) & 0x7;
7497   int offset = (instruction >> 0) & 0xff;
7498   signed_word op2 = 0;
7499   if (op1 < 2)
7500     op1 += 16;
7501   op1 = GPR[op1];
7502   if (have_extendval)
7503     {
7504       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7505       if (offset >= 0x8000)
7506         offset -= 0x10000;
7507       have_extendval = 0;
7508     }
7509   else
7510     {
7511       if (offset >= 0x80)
7512         offset -= 0x100;
7513     }
7514   offset *= 2;
7515   if (have_extendval)
7516     SignalException (ReservedInstruction, instruction);
7517   {
7518     int condition = (op1 != op2);
7519     if (condition)
7520       PC = PC + offset;
7521   }
7522 }
7523
7524
7525 01100000,pppppppp,t,z:I8:16::BTEQZ
7526 *mips16:
7527 {
7528   unsigned32 instruction = instruction_0;
7529   int offset = (instruction >> 0) & 0xff;
7530   signed_word op1 = 24;
7531   signed_word op2 = 0;
7532   if (have_extendval)
7533     {
7534       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7535       if (offset >= 0x8000)
7536         offset -= 0x10000;
7537       have_extendval = 0;
7538     }
7539   else
7540     {
7541       if (offset >= 0x80)
7542         offset -= 0x100;
7543     }
7544   offset *= 2;
7545   op1 = GPR[op1];
7546   if (have_extendval)
7547     SignalException (ReservedInstruction, instruction);
7548   {
7549     int condition = (op1 == op2);
7550     if (condition)
7551       PC = PC + offset;
7552   }
7553 }
7554
7555
7556 01100001,pppppppp,t,z:I8:16::BTNEZ
7557 *mips16:
7558 {
7559   unsigned32 instruction = instruction_0;
7560   int offset = (instruction >> 0) & 0xff;
7561   signed_word op1 = 24;
7562   signed_word op2 = 0;
7563   if (have_extendval)
7564     {
7565       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7566       if (offset >= 0x8000)
7567         offset -= 0x10000;
7568       have_extendval = 0;
7569     }
7570   else
7571     {
7572       if (offset >= 0x80)
7573         offset -= 0x100;
7574     }
7575   offset *= 2;
7576   op1 = GPR[op1];
7577   if (have_extendval)
7578     SignalException (ReservedInstruction, instruction);
7579   {
7580     int condition = (op1 != op2);
7581     if (condition)
7582       PC = PC + offset;
7583   }
7584 }
7585
7586
7587 00010,qqqqqqqqqqq,z,Z:I:16::B
7588 *mips16:
7589 {
7590   unsigned32 instruction = instruction_0;
7591   int offset = (instruction >> 0) & 0x7ff;
7592   signed_word op2 = 0;
7593   signed_word op1 = 0;
7594   if (have_extendval)
7595     {
7596       offset |= ((extendval & 0x1f) << 11) | (extendval & 0x7e0);
7597       if (offset >= 0x8000)
7598         offset -= 0x10000;
7599       have_extendval = 0;
7600     }
7601   else
7602     {
7603       if (offset >= 0x400)
7604         offset -= 0x800;
7605     }
7606   offset *= 2;
7607   if (have_extendval)
7608     SignalException (ReservedInstruction, instruction);
7609   {
7610     int condition = (op1 == op2);
7611     if (condition)
7612       PC = PC + offset;
7613   }
7614 }
7615
7616
7617 // Special Instructions
7618
7619
7620 // See the front of the mips16 doc
7621 11110,eeeeeeeeeee:I:16::EXTEND
7622 *mips16:
7623 {
7624   unsigned32 instruction = instruction_0;
7625   int ext = (instruction >> 0) & 0x7ff;
7626   if (have_extendval)
7627     SignalException (ReservedInstruction, instruction);
7628   {
7629     extendval = ext;
7630     have_extendval = 1;
7631   }
7632 }
7633
7634
7635 01100,******,00101:RR:16::BREAK
7636 *mips16:
7637 {
7638   unsigned32 instruction = instruction_0;
7639   if (have_extendval)
7640     SignalException (ReservedInstruction, instruction);
7641   {
7642     SignalException(BreakPoint,instruction);
7643   }
7644 }
7645
7646 \f
7647 // start-sanitize-r5900
7648
7649 // FIXME: The instructions below which are typically r5900 specific
7650 //        need to be merged back into the above.
7651
7652 // end-sanitize-r5900
7653 // start-sanitize-r5900
7654
7655 011100,5.RS,5.RT,0000000000011010:MMINORM:32::DIV1
7656 *r5900:
7657 {
7658   unsigned32 instruction = instruction_0;
7659   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7660   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7661   {
7662     CHECKHILO("Division");
7663     {
7664       int d1 = op1;
7665       int d2 = op2;
7666       if (d2 == 0)
7667         {
7668           LO1 = SIGNEXTEND(0x80000000,32);
7669           HI1 = SIGNEXTEND(0,32);
7670         }
7671       else if (d2 == -1 && d1 == 0x80000000)
7672         {
7673           LO1 = SIGNEXTEND(0x80000000,32);
7674           HI1 = SIGNEXTEND(0,32);
7675         }
7676       else
7677         {
7678           LO1 = SIGNEXTEND((d1 / d2),32);
7679           HI1 = SIGNEXTEND((d1 % d2),32);
7680         }
7681     }
7682   }
7683 }
7684
7685 // end-sanitize-r5900
7686 // start-sanitize-r5900
7687
7688 011100,5.RS,5.RT,0000000000011011:MMINORM:32::DIVU1
7689 *r5900:
7690 {
7691   unsigned32 instruction = instruction_0;
7692   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7693   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7694   {
7695     CHECKHILO("Division");
7696     {
7697       unsigned int d1 = op1;
7698       unsigned int d2 = op2;
7699       if (d2 == 0)
7700         {
7701           LO1 = SIGNEXTEND(0x80000000,32);
7702           HI1 = SIGNEXTEND(0,32);
7703         }
7704       else if (d2 == -1 && d1 == 0x80000000)
7705         {
7706           LO1 = SIGNEXTEND(0x80000000,32);
7707           HI1 = SIGNEXTEND(0,32);
7708         }
7709       else
7710         {
7711           LO1 = SIGNEXTEND((d1 / d2),32);
7712           HI1 = SIGNEXTEND((d1 % d2),32);
7713         }
7714     }
7715   }
7716 }
7717
7718 // end-sanitize-r5900
7719
7720 011101,26.INSTR_INDEX:NORMAL:32::JALX
7721 // start-sanitize-r5900
7722 *r5900:
7723 // end-sanitize-r5900
7724 *r3900:
7725 // start-sanitize-tx19
7726 *tx19:
7727 // end-sanitize-tx19
7728 {
7729   unsigned32 instruction = instruction_0;
7730   unsigned_word op1 = (((instruction >> 0) & 0x03FFFFFF) << 2);
7731   op1 |= (PC & ~0x0FFFFFFF); /* address of instruction in delay slot for the jump */
7732   {
7733     int destreg = 31;
7734     GPR[destreg] = (PC + 4); /* NOTE: The PC is already 4 ahead within the simulator */
7735     op1 ^= 1;
7736     /* NOTE: ??? Gdb gets confused if the PC is sign-extended,
7737        so we just truncate it to 32 bits here.  */
7738     op1 = VL4_8(op1);
7739     /* NOTE: The jump occurs AFTER the next instruction has been executed */
7740     DELAY_SLOT op1;
7741     /* JALDELAYSLOT(); FIXME */
7742   }
7743 }
7744
7745 // start-sanitize-r5900
7746
7747 011110,5.RS,5.RT,16.OFFSET:NORMAL:128::LQ
7748 *r5900:
7749 {
7750   unsigned32 instruction = instruction_0;
7751   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
7752   int destreg = ((instruction >> 16) & 0x0000001F);
7753   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7754   {
7755     address_word vaddr = ((unsigned64)op1 + offset);
7756     address_word paddr;
7757     int uncached;
7758     if ((vaddr & 15) != 0)
7759       SignalExceptionAddressLoad();
7760     else
7761       {
7762         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
7763           {
7764             unsigned64 memval = 0;
7765             unsigned64 memval1 = 0;
7766             unsigned64 mask = 0x7;
7767             unsigned int shift = 8;
7768             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
7769             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
7770             unsigned int byte;
7771             LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
7772             GPR[destreg] = memval;
7773             GPR1[destreg] = memval1;
7774           }
7775       }
7776   }
7777 }
7778
7779 // end-sanitize-r5900
7780 // start-sanitize-r5900
7781
7782 011100,5.RS,5.RT,5.RD,00000000000:MMINORM:32::MADD
7783 *r5900:
7784 *r3900:
7785 {
7786   unsigned32 instruction = instruction_0;
7787   int destreg = ((instruction >> 11) & 0x0000001F);
7788   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7789   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7790   {
7791     word64 prod = (word64)WORD64(VL4_8(HI),VL4_8(LO)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32));
7792     LO = SIGNEXTEND(prod,32);
7793     HI = SIGNEXTEND( VH4_8(prod), 32);
7794     if( destreg != 0 ) GPR[destreg] = LO;
7795   }
7796 }
7797
7798 // end-sanitize-r5900
7799 // start-sanitize-r5900
7800
7801 011100,5.RS,5.RT,5.RD,00000000001:MMINORM:32::MADDU
7802 *r5900:
7803 *r3900:
7804 {
7805   unsigned32 instruction = instruction_0;
7806   int destreg = ((instruction >> 11) & 0x0000001F);
7807   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7808   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7809   {
7810     unsigned64 prod = (unsigned64)WORD64(VL4_8(HI),VL4_8(LO)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2));
7811     LO = SIGNEXTEND(prod,32);
7812     HI = SIGNEXTEND( VH4_8(prod), 32);
7813     if( destreg != 0 ) GPR[destreg] = LO;
7814   }
7815 }
7816
7817 // end-sanitize-r5900
7818 // start-sanitize-r5900
7819
7820 011100,5.RS,5.RT,5.RD,00000100000:MMINORM:32::MADD1
7821 *r5900:
7822 {
7823   unsigned32 instruction = instruction_0;
7824   int destreg = ((instruction >> 11) & 0x0000001F);
7825   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7826   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7827   {
7828     word64 prod = (word64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((word64)SIGNEXTEND(op1,32) * (word64)SIGNEXTEND(op2,32));
7829     LO1 = SIGNEXTEND(prod,32);
7830     HI1 = SIGNEXTEND( VH4_8(prod), 32);
7831     if( destreg != 0 ) GPR[destreg] = LO1;
7832   }
7833 }
7834
7835 // end-sanitize-r5900
7836 // start-sanitize-r5900
7837
7838 011100,5.RS,5.RT,5.RD,00000100001:MMINORM:32::MADDU1
7839 *r5900:
7840 {
7841   unsigned32 instruction = instruction_0;
7842   int destreg = ((instruction >> 11) & 0x0000001F);
7843   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7844   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7845   {
7846     unsigned64 prod = (unsigned64)WORD64(VL4_8(HI1),VL4_8(LO1)) + ((unsigned64)VL4_8(op1) * (unsigned64)VL4_8(op2));
7847     LO1 = SIGNEXTEND(prod,32);
7848     HI1 = SIGNEXTEND( VH4_8(prod), 32);
7849     if( destreg != 0 ) GPR[destreg] = LO1;
7850   }
7851 }
7852
7853 // end-sanitize-r5900
7854 // start-sanitize-r5900
7855
7856 0111000000000000,5.RD,00000010000:MMINORM:32::MFHI1
7857 *r5900:
7858 {
7859   unsigned32 instruction = instruction_0;
7860   int destreg = ((instruction >> 11) & 0x0000001F);
7861   {
7862     GPR[destreg] = HI1;
7863     HI1ACCESS = 3; /* 3rd instruction will be safe */
7864   }
7865 }
7866
7867 // end-sanitize-r5900
7868 // start-sanitize-r5900
7869
7870 0111000000000000,5.RD,00000010010:MMINORM:32::MFLO1
7871 *r5900:
7872 {
7873   unsigned32 instruction = instruction_0;
7874   int destreg = ((instruction >> 11) & 0x0000001F);
7875   {
7876     GPR[destreg] = LO1;
7877     LO1ACCESS = 3; /* 3rd instruction will be safe */
7878   }
7879 }
7880
7881 // end-sanitize-r5900
7882 // start-sanitize-r5900
7883
7884 0000000000000000,5.RD,00000101000:SPECIAL:32::MFSA
7885 *r5900:
7886 {
7887   unsigned32 instruction = instruction_0;
7888   int destreg = ((instruction >> 11) & 0x0000001F);
7889   {
7890     GPR[destreg] = SA;
7891   }
7892 }
7893
7894 // end-sanitize-r5900
7895 // start-sanitize-r5900
7896
7897 011100,5.RS,000000000000000010001:MMINORM:32::MTHI1
7898 *r5900:
7899 {
7900   unsigned32 instruction = instruction_0;
7901   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7902   {
7903     if (HI1ACCESS != 0)
7904       sim_io_error(sd,"MT (move-to) over-writing HI register value\n");
7905     HI1 = op1;
7906     HI1ACCESS = 3; /* 3rd instruction will be safe */
7907   }
7908 }
7909
7910 // end-sanitize-r5900
7911 // start-sanitize-r5900
7912
7913 011100,5.RS,000000000000000010011:MMINORM:32::MTLO1
7914 *r5900:
7915 {
7916   unsigned32 instruction = instruction_0;
7917   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7918   {
7919     if (LO1ACCESS != 0)
7920       sim_io_error(sd,"MT (move-to) over-writing LO register value");
7921     LO1 = op1;
7922     LO1ACCESS = 3; /* 3rd instruction will be safe */
7923   }
7924 }
7925
7926 // end-sanitize-r5900
7927 // start-sanitize-r5900
7928
7929 000000,5.RS,000000000000000101001:SPECIAL:32::MTSA
7930 *r5900:
7931 {
7932   unsigned32 instruction = instruction_0;
7933   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7934   {
7935     SA = op1;
7936   }
7937 }
7938
7939 // end-sanitize-r5900
7940 // start-sanitize-r5900
7941
7942 000001,5.RS,11000,16.IMMEDIATE:REGIMM:32::MTSAB
7943 *r5900:
7944 {
7945   SA = ((GPR[RA] & 0xF) ^ (IMMEDIATE & 0xF)) * 8;
7946 }
7947
7948 // end-sanitize-r5900
7949 // start-sanitize-r5900
7950
7951 000001,5.RS,11001,16.IMMEDIATE:REGIMM:32::MTSAH
7952 *r5900:
7953 {
7954   SA = ((GPR[RS] & 0x7) ^ (IMMEDIATE & 0x7)) * 16;
7955 }
7956
7957 // end-sanitize-r5900
7958 // start-sanitize-r5900
7959
7960 011100,5.RS,5.RT,5.RD,00000011000:MMINORM:32::MULT1
7961 *r5900:
7962 {
7963   unsigned32 instruction = instruction_0;
7964   int destreg = ((instruction >> 11) & 0x0000001F);
7965   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7966   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7967   {
7968     CHECKHILO("Multiplication");
7969     {
7970       unsigned64 temp = ((word64) op1 * (word64) op2);
7971       LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7972       HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7973       if ( destreg != 0 )
7974         GPR[destreg] = LO1;
7975     }
7976   }
7977 }
7978
7979 // end-sanitize-r5900
7980 // start-sanitize-r5900
7981
7982 011100,5.RS,5.RT,5.RD,00000011001:MMINORM:32::MULTU1
7983 *r5900:
7984 {
7985   unsigned32 instruction = instruction_0;
7986   int destreg = ((instruction >> 11) & 0x0000001F);
7987   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
7988   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
7989   {
7990     CHECKHILO("Multiplication");
7991     {
7992       unsigned64 temp = ((unsigned64)(op1 & 0xffffffff) * (unsigned64)(op2 & 0xffffffff));
7993       LO1 = SIGNEXTEND((unsigned64)VL4_8(temp),32);
7994       HI1 = SIGNEXTEND((unsigned64)VH4_8(temp),32);
7995       if ( destreg != 0 )
7996         GPR[destreg] = LO1;
7997     }
7998   }
7999 }
8000
8001 // end-sanitize-r5900
8002 // start-sanitize-r5900
8003
8004 01110000000,5.RT,5.RD,00101101000:MMI1:32::PABSH
8005 *r5900:
8006 {
8007   unsigned32 instruction = instruction_0;
8008   int destreg = ((instruction >> 11) & 0x0000001F);
8009   signed_word rt_reg = GPR[RT];
8010   signed_word rt_reg1 = GPR1[RT];
8011   {
8012     int i;
8013     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
8014       {
8015         if (RT_SH(i) >= 0)
8016           GPR_SH(destreg,i) =  RT_SH(i);
8017         else if (RT_SH(i) == -32768)
8018           GPR_SH(destreg,i) = 32767;
8019         else
8020           GPR_SH(destreg,i) = -RT_SH(i);
8021       }
8022   }
8023 }
8024
8025 // end-sanitize-r5900
8026 // start-sanitize-r5900
8027
8028 01110000000,5.RT,5.RD,00001101000:MMI1:32::PABSW
8029 *r5900:
8030 {
8031   unsigned32 instruction = instruction_0;
8032   int destreg = ((instruction >> 11) & 0x0000001F);
8033   signed_word rt_reg = GPR[RT];
8034   signed_word rt_reg1 = GPR1[RT];
8035   {
8036     int i;
8037     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8038       {
8039         if (RT_SW(i) >= 0)
8040           GPR_SW(destreg,i) =  RT_SW(i);
8041         else if (RT_SW(i) == (int)0x80000000)
8042           GPR_SW(destreg,i) = (int)0x7FFFFFFF;
8043         else
8044           GPR_SW(destreg,i) = -RT_SW(i);
8045       }
8046   }
8047 }
8048
8049 // end-sanitize-r5900
8050 // start-sanitize-r5900
8051
8052 011100,5.RS,5.RT,5.RD,01000001000:MMI0:32::PADDB
8053 *r5900:
8054 {
8055   unsigned32 instruction = instruction_0;
8056   int destreg = ((instruction >> 11) & 0x0000001F);
8057   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8058   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8059   signed_word rt_reg = GPR[RT];
8060   signed_word rt_reg1 = GPR1[RT];
8061   {
8062     int i;
8063     for (i=0; i < BYTES_IN_MMI_REGS; i++)
8064       {
8065         int s = RS_SB(i);
8066         int t = RT_SB(i);
8067         int r = s + t;
8068         GPR_SB(destreg,i) = r;
8069       }
8070   }
8071 }
8072
8073 // end-sanitize-r5900
8074 // start-sanitize-r5900
8075
8076 011100,5.RS,5.RT,5.RD,00100001000:MMI0:32::PADDH
8077 *r5900:
8078 {
8079   unsigned32 instruction = instruction_0;
8080   int destreg = ((instruction >> 11) & 0x0000001F);
8081   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8082   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8083   signed_word rt_reg = GPR[RT];
8084   signed_word rt_reg1 = GPR1[RT];
8085   {
8086     int i;
8087     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
8088       {
8089         int s = RS_SH(i);
8090         int t = RT_SH(i);
8091         int r = s + t;
8092         GPR_SH(destreg,i) = r;
8093       }
8094   }
8095 }
8096
8097 // end-sanitize-r5900
8098 // start-sanitize-r5900
8099
8100 011100,5.RS,5.RT,5.RD,00000001000:MMI0:32::PADDW
8101 *r5900:
8102 {
8103   unsigned32 instruction = instruction_0;
8104   int destreg = ((instruction >> 11) & 0x0000001F);
8105   signed_word rs_reg = GPR[RS];
8106   signed_word rs_reg1 = GPR1[RS];
8107   signed_word rt_reg = GPR[RT];
8108   signed_word rt_reg1 = GPR1[RT];
8109   {
8110     int i;
8111     for (i=0; i < WORDS_IN_MMI_REGS; i++)
8112       {
8113         signed64 s = RS_SW(i);
8114         signed64 t = RT_SW(i);
8115         signed64 r = s + t;
8116         GPR_SW(destreg,i) = r;
8117       }
8118   }
8119 }
8120
8121 // end-sanitize-r5900
8122 // start-sanitize-r5900
8123
8124 011100,5.RS,5.RT,5.RD,11000001000:MMI0:32::PADDSB
8125 *r5900:
8126 {
8127   unsigned32 instruction = instruction_0;
8128   int destreg = ((instruction >> 11) & 0x0000001F);
8129   signed_word rs_reg = GPR[RS];
8130   signed_word rs_reg1 = GPR1[RS];
8131   signed_word rt_reg = GPR[RT];
8132   signed_word rt_reg1 = GPR1[RT];
8133   {
8134     int i;
8135     for (i=0; i < BYTES_IN_MMI_REGS; i++)
8136       {
8137         int s = RS_SB(i);
8138         int t = RT_SB(i);
8139         int r = s + t;
8140         if (r > 127)
8141           GPR_SB(destreg,i) = 127;
8142         else if (r < -128)
8143           GPR_SB(destreg,i) = -128;
8144         else
8145           GPR_SB(destreg,i) = r;
8146       }
8147   }
8148 }
8149
8150 // end-sanitize-r5900
8151 // start-sanitize-r5900
8152
8153 011100,5.RS,5.RT,5.RD,10100001000:MMI0:32::PADDSH
8154 *r5900:
8155 {
8156   unsigned32 instruction = instruction_0;
8157   int destreg = ((instruction >> 11) & 0x0000001F);
8158   signed_word rs_reg = GPR[RS];
8159   signed_word rs_reg1 = GPR1[RS];
8160   signed_word rt_reg = GPR[RT];
8161   signed_word rt_reg1 = GPR1[RT];
8162   {
8163     int i;
8164     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
8165       {
8166         int s = RS_SH(i);
8167         int t = RT_SH(i);
8168         int r = s + t;
8169         if (r > 32767)
8170           GPR_SH(destreg,i) = 32767;
8171         else if (r < -32768)
8172           GPR_SH(destreg,i) = -32768;
8173         else
8174           GPR_SH(destreg,i) = r;
8175       }
8176   }
8177 }
8178
8179 // end-sanitize-r5900
8180 // start-sanitize-r5900
8181
8182 011100,5.RS,5.RT,5.RD,10000001000:MMI0:32::PADDSW
8183 *r5900:
8184 {
8185   unsigned32 instruction = instruction_0;
8186   int destreg = ((instruction >> 11) & 0x0000001F);
8187   signed_word rs_reg = GPR[RS];
8188   signed_word rs_reg1 = GPR1[RS];
8189   signed_word rt_reg = GPR[RT];
8190   signed_word rt_reg1 = GPR1[RT];
8191   {
8192     int i;
8193     for (i=0; i < WORDS_IN_MMI_REGS; i++)
8194       {
8195         signed64 s = RS_SW(i);
8196         signed64 t = RT_SW(i);
8197         signed64 r = s + t;
8198         if (r > (int)0x7FFFFFFF)
8199           GPR_SW(destreg,i) = (int)0x7FFFFFFF;
8200         else if (r < (int)0x80000000)
8201           GPR_SW(destreg,i) = (int)0x80000000;
8202         else
8203           GPR_SW(destreg,i) = r;
8204       }
8205   }
8206 }
8207
8208 // end-sanitize-r5900
8209 // start-sanitize-r5900
8210
8211 011100,5.RS,5.RT,5.RD,11000101000:MMI1:32::PADDUB
8212 *r5900:
8213 {
8214   unsigned32 instruction = instruction_0;
8215   int destreg = ((instruction >> 11) & 0x0000001F);
8216   signed_word rs_reg = GPR[RS];
8217   signed_word rs_reg1 = GPR1[RS];
8218   signed_word rt_reg = GPR[RT];
8219   signed_word rt_reg1 = GPR1[RT];
8220   {
8221     int i;
8222     for (i=0; i < BYTES_IN_MMI_REGS; i++)
8223       {
8224         unsigned int s = RS_UB(i);
8225         unsigned int t = RT_UB(i);
8226         unsigned int r = s + t;
8227         if (r > 0xFF)
8228           GPR_UB(destreg,i) = 0xFF;
8229         else
8230           GPR_UB(destreg,i) = r;
8231       }
8232   }
8233 }
8234
8235 // end-sanitize-r5900
8236 // start-sanitize-r5900
8237
8238 011100,5.RS,5.RT,5.RD,10100101000:MMI1:32::PADDUH
8239 *r5900:
8240 {
8241   unsigned32 instruction = instruction_0;
8242   int destreg = ((instruction >> 11) & 0x0000001F);
8243   signed_word rs_reg = GPR[RS];
8244   signed_word rs_reg1 = GPR1[RS];
8245   signed_word rt_reg = GPR[RT];
8246   signed_word rt_reg1 = GPR1[RT];
8247   {
8248     int i;
8249     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
8250       {
8251         unsigned int s = RS_UH(i);
8252         unsigned int t = RT_UH(i);
8253         unsigned int r = s + t;
8254         if (r > 0xFFFF)
8255           GPR_UH(destreg,i) = 0xFFFF;
8256         else
8257           GPR_UH(destreg,i) = r;
8258       }
8259   }
8260 }
8261
8262 // end-sanitize-r5900
8263 // start-sanitize-r5900
8264
8265 011100,5.RS,5.RT,5.RD,10000101000:MMI1:32::PADDUW
8266 *r5900:
8267 {
8268   unsigned32 instruction = instruction_0;
8269   int destreg = ((instruction >> 11) & 0x0000001F);
8270   signed_word rs_reg = GPR[RS];
8271   signed_word rs_reg1 = GPR1[RS];
8272   signed_word rt_reg = GPR[RT];
8273   signed_word rt_reg1 = GPR1[RT];
8274   {
8275     int i;
8276     for (i=0; i < WORDS_IN_MMI_REGS; i++)
8277       {
8278         unsigned64 s = RS_UW(i);
8279         unsigned64 t = RT_UW(i);
8280         unsigned64 r = s + t;
8281         if (r > 0xFFFFFFFF)
8282           GPR_UW(destreg,i) = 0xFFFFFFFF;
8283         else
8284           GPR_UW(destreg,i) = r;
8285       }
8286   }
8287 }
8288
8289 // end-sanitize-r5900
8290 // start-sanitize-r5900
8291
8292 011100,5.RS,5.RT,5.RD,00100101000:MMI1:32::PADSBH
8293 *r5900:
8294 {
8295   unsigned32 instruction = instruction_0;
8296   int destreg = ((instruction >> 11) & 0x0000001F);
8297   signed_word rs_reg = GPR[RS];
8298   signed_word rs_reg1 = GPR1[RS];
8299   signed_word rt_reg = GPR[RT];
8300   signed_word rt_reg1 = GPR1[RT];
8301   {
8302     int i;
8303     for(i=0;i<HALFWORDS_IN_MMI_REGS/2;i++)
8304       GPR_SH(destreg,i) = RS_SH(i) - RT_SH(i);
8305     for(;i<HALFWORDS_IN_MMI_REGS;i++)
8306       GPR_SH(destreg,i) = RS_SH(i) + RT_SH(i);
8307   }
8308 }
8309
8310 // end-sanitize-r5900
8311 // start-sanitize-r5900
8312
8313 011100,5.RS,5.RT,5.RD,10010001001:MMI2:32::PAND
8314 *r5900:
8315 {
8316   unsigned32 instruction = instruction_0;
8317   int destreg = ((instruction >> 11) & 0x0000001F);
8318   signed_word rs_reg = GPR[RS];
8319   signed_word rs_reg1 = GPR1[RS];
8320   signed_word rt_reg = GPR[RT];
8321   signed_word rt_reg1 = GPR1[RT];
8322   {
8323     int i;
8324     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8325       GPR_UW(destreg,i) = (RS_UW(i) & RT_UW(i));
8326   }
8327 }
8328
8329 // end-sanitize-r5900
8330 // start-sanitize-r5900
8331
8332 011100,5.RS,5.RT,5.RD,01010101000:MMI1:32::PCEQB
8333 *r5900:
8334 {
8335   unsigned32 instruction = instruction_0;
8336   int destreg = ((instruction >> 11) & 0x0000001F);
8337   signed_word rs_reg = GPR[RS];
8338   signed_word rs_reg1 = GPR1[RS];
8339   signed_word rt_reg = GPR[RT];
8340   signed_word rt_reg1 = GPR1[RT];
8341   {
8342     int i;
8343     for(i=0;i<BYTES_IN_MMI_REGS;i++)
8344       {
8345         if (RS_SB(i) == RT_SB(i)) GPR_SB(destreg,i) = 0xFF;
8346         else                        GPR_SB(destreg,i) = 0;
8347       }
8348   }
8349 }
8350
8351 // end-sanitize-r5900
8352 // start-sanitize-r5900
8353
8354 011100,5.RS,5.RT,5.RD,00110101000:MMI1:32::PCEQH
8355 *r5900:
8356 {
8357   unsigned32 instruction = instruction_0;
8358   int destreg = ((instruction >> 11) & 0x0000001F);
8359   signed_word rs_reg = GPR[RS];
8360   signed_word rs_reg1 = GPR1[RS];
8361   signed_word rt_reg = GPR[RT];
8362   signed_word rt_reg1 = GPR1[RT];
8363   {
8364     int i;
8365     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
8366       {
8367         if (RS_SH(i) == RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF;
8368         else                        GPR_SH(destreg,i) = 0;
8369       }
8370   }
8371 }
8372
8373 // end-sanitize-r5900
8374 // start-sanitize-r5900
8375
8376 011100,5.RS,5.RT,5.RD,00010101000:MMI1:32::PCEQW
8377 *r5900:
8378 {
8379   unsigned32 instruction = instruction_0;
8380   int destreg = ((instruction >> 11) & 0x0000001F);
8381   signed_word rs_reg = GPR[RS];
8382   signed_word rs_reg1 = GPR1[RS];
8383   signed_word rt_reg = GPR[RT];
8384   signed_word rt_reg1 = GPR1[RT];
8385   {
8386     int i;
8387     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8388       {
8389         if (RS_SW(i) == RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF;
8390         else                        GPR_SW(destreg,i) = 0;
8391       }
8392   }
8393 }
8394
8395 // end-sanitize-r5900
8396 // start-sanitize-r5900
8397
8398 011100,5.RS,5.RT,5.RD,01010001000:MMI0:32::PCGTB
8399 *r5900:
8400 {
8401   unsigned32 instruction = instruction_0;
8402   int destreg = ((instruction >> 11) & 0x0000001F);
8403   signed_word rs_reg = GPR[RS];
8404   signed_word rs_reg1 = GPR1[RS];
8405   signed_word rt_reg = GPR[RT];
8406   signed_word rt_reg1 = GPR1[RT];
8407   {
8408     int i;
8409     for(i=0;i<BYTES_IN_MMI_REGS;i++)
8410       {
8411         if (RS_SB(i) > RT_SB(i)) GPR_SB(destreg,i) = 0xFF;
8412         else                        GPR_SB(destreg,i) = 0;
8413       }
8414   }
8415 }
8416
8417 // end-sanitize-r5900
8418 // start-sanitize-r5900
8419
8420 011100,5.RS,5.RT,5.RD,00110001000:MMI0:32::PCGTH
8421 *r5900:
8422 {
8423   unsigned32 instruction = instruction_0;
8424   int destreg = ((instruction >> 11) & 0x0000001F);
8425   signed_word rs_reg = GPR[RS];
8426   signed_word rs_reg1 = GPR1[RS];
8427   signed_word rt_reg = GPR[RT];
8428   signed_word rt_reg1 = GPR1[RT];
8429   {
8430     int i;
8431     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
8432       {
8433         if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = 0xFFFF;
8434         else                        GPR_SH(destreg,i) = 0;
8435       }
8436   }
8437 }
8438
8439 // end-sanitize-r5900
8440 // start-sanitize-r5900
8441
8442 011100,5.RS,5.RT,5.RD,00010001000:MMI0:32::PCGTW
8443 *r5900:
8444 {
8445   unsigned32 instruction = instruction_0;
8446   int destreg = ((instruction >> 11) & 0x0000001F);
8447   signed_word rs_reg = GPR[RS];
8448   signed_word rs_reg1 = GPR1[RS];
8449   signed_word rt_reg = GPR[RT];
8450   signed_word rt_reg1 = GPR1[RT];
8451   {
8452     int i;
8453     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8454       {
8455         if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = 0xFFFFFFFF;
8456         else                        GPR_SW(destreg,i) = 0;
8457       }
8458   }
8459 }
8460
8461 // end-sanitize-r5900
8462 // start-sanitize-r5900
8463
8464 01110000000,5.RT,5.RD,11011101001:MMI3:32::PCPYH
8465 *r5900:
8466 {
8467   unsigned32 instruction = instruction_0;
8468   int destreg = ((instruction >> 11) & 0x0000001F);
8469   signed_word rt_reg = GPR[RT];
8470   signed_word rt_reg1 = GPR1[RT];
8471   {
8472     GPR_UH(destreg,7) = GPR_UH(destreg,6) = GPR_UH(destreg,5) = GPR_UH(destreg,4) = RT_UH(4);
8473     GPR_UH(destreg,3) = GPR_UH(destreg,2) = GPR_UH(destreg,1) = GPR_UH(destreg,0) = RT_UH(0);
8474   }
8475 }
8476
8477 // end-sanitize-r5900
8478 // start-sanitize-r5900
8479
8480 011100,5.RS,5.RT,5.RD,01110001001:MMI2:32::PCPYLD
8481 *r5900:
8482 {
8483   unsigned32 instruction = instruction_0;
8484   int destreg = ((instruction >> 11) & 0x0000001F);
8485   signed_word rs_reg = GPR[RS];
8486   signed_word rs_reg1 = GPR1[RS];
8487   signed_word rt_reg = GPR[RT];
8488   signed_word rt_reg1 = GPR1[RT];
8489   {
8490     GPR_UD(destreg,0) = RT_UD(0);
8491     GPR_UD(destreg,1) = RS_UD(0);
8492   }
8493 }
8494
8495 // end-sanitize-r5900
8496 // start-sanitize-r5900
8497
8498 011100,5.RS,5.RT,5.RD,01110101001:MMI3:32::PCPYUD
8499 *r5900:
8500 {
8501   unsigned32 instruction = instruction_0;
8502   int destreg = ((instruction >> 11) & 0x0000001F);
8503   signed_word rs_reg = GPR[RS];
8504   signed_word rs_reg1 = GPR1[RS];
8505   signed_word rt_reg = GPR[RT];
8506   signed_word rt_reg1 = GPR1[RT];
8507   {
8508     GPR_UD(destreg,0) = RS_UD(1);
8509     GPR_UD(destreg,1) = RT_UD(1);
8510   }
8511 }
8512
8513 // end-sanitize-r5900
8514 // start-sanitize-r5900
8515
8516 011100,5.RS,5.RT,0000011101001001:MMI2:32::PDIVBW
8517 *r5900:
8518 {
8519   signed_word rs_reg = GPR[RS];
8520   signed_word rs_reg1 = GPR1[RS];
8521   signed_word rt_reg = GPR[RT];
8522   signed_word rt_reg1 = GPR1[RT];
8523   {
8524     signed32 devisor = RT_SH(0);
8525     if (devisor == -1)
8526       {
8527         LO_SW(0) = -RS_SW(0);
8528         HI_SW(0) = 0;
8529         LO_SW(1) = -RS_SW(1);
8530         HI_SW(1) = 0;
8531         LO_SW(2) = -RS_SW(2);
8532         HI_SW(2) = 0;
8533         LO_SW(3) = -RS_SW(3);
8534         HI_SW(3) = 0;
8535       }
8536     else if (devisor != 0)
8537       {
8538         LO_SW(0) = RS_SW(0) / devisor;
8539         HI_SW(0) = SIGNEXTEND( (RS_SW(0) % devisor), 16 );
8540         LO_SW(1) = RS_SW(1) / devisor;
8541         HI_SW(1) = SIGNEXTEND( (RS_SW(1) % devisor), 16 );
8542         LO_SW(2) = RS_SW(2) / devisor;
8543         HI_SW(2) = SIGNEXTEND( (RS_SW(2) % devisor), 16 );
8544         LO_SW(3) = RS_SW(3) / devisor;
8545         HI_SW(3) = SIGNEXTEND( (RS_SW(3) % devisor), 16 );
8546       }
8547   }
8548 }
8549
8550 // end-sanitize-r5900
8551 // start-sanitize-r5900
8552
8553 011100,5.RS,5.RT,0000001101101001:MMI3:32::PDIVUW
8554 *r5900:
8555 {
8556   signed_word rs_reg = GPR[RS];
8557   signed_word rs_reg1 = GPR1[RS];
8558   signed_word rt_reg = GPR[RT];
8559   signed_word rt_reg1 = GPR1[RT];
8560   {
8561     if (RT_UW(0) != 0)
8562       {
8563         LO  = (signed32)(RS_UW(0) / RT_UW(0));
8564         HI  = (signed32)(RS_UW(0) % RT_UW(0));
8565       }
8566     if (RT_UW(2) != 0)
8567       {
8568         LO1 = (signed32)(RS_UW(2) / RT_UW(2));
8569         HI1 = (signed32)(RS_UW(2) % RT_UW(2));
8570       }
8571   }
8572 }
8573
8574 // end-sanitize-r5900
8575 // start-sanitize-r5900
8576
8577 011100,5.RS,5.RT,0000001101001001:MMI2:32::PDIVW
8578 *r5900:
8579 {
8580   signed_word rs_reg = GPR[RS];
8581   signed_word rs_reg1 = GPR1[RS];
8582   signed_word rt_reg = GPR[RT];
8583   signed_word rt_reg1 = GPR1[RT];
8584   {
8585     if (RT_SW(0) == -1)
8586       {
8587         LO  = -RS_SW(0);
8588         HI  = 0;
8589       }
8590     else if (RT_UW(0) != 0)
8591       {
8592         LO  = (signed32)(RS_SW(0) / RT_SW(0));
8593         HI  = (signed32)(RS_SW(0) % RT_SW(0));
8594       }
8595     if (RT_SW(2) == -1)
8596       {
8597         LO1 = -RS_SW(2);
8598         HI1 = 0;
8599       }
8600     else if (RT_UW(2) != 0)
8601       {
8602         LO1 = (signed32)(RS_SW(2) / RT_SW(2));
8603         HI1 = (signed32)(RS_SW(2) % RT_SW(2));
8604       }
8605   }
8606 }
8607
8608 // end-sanitize-r5900
8609 // start-sanitize-r5900
8610
8611 01110000000,5.RT,5.RD,11010101001:MMI3:32::PEXCH
8612 *r5900:
8613 {
8614   unsigned32 instruction = instruction_0;
8615   int destreg = ((instruction >> 11) & 0x0000001F);
8616   signed_word rt_reg = GPR[RT];
8617   signed_word rt_reg1 = GPR1[RT];
8618   {
8619     GPR_UH(destreg,0) = RT_UH(0);
8620     GPR_UH(destreg,1) = RT_UH(2);
8621     GPR_UH(destreg,2) = RT_UH(1);
8622     GPR_UH(destreg,3) = RT_UH(3);
8623     GPR_UH(destreg,4) = RT_UH(4);
8624     GPR_UH(destreg,5) = RT_UH(6);
8625     GPR_UH(destreg,6) = RT_UH(5);
8626     GPR_UH(destreg,7) = RT_UH(7);
8627   }
8628 }
8629
8630 // end-sanitize-r5900
8631 // start-sanitize-r5900
8632
8633 01110000000,5.RT,5.RD,11110101001:MMI3:32::PEXCW
8634 *r5900:
8635 {
8636   unsigned32 instruction = instruction_0;
8637   int destreg = ((instruction >> 11) & 0x0000001F);
8638   signed_word rt_reg = GPR[RT];
8639   signed_word rt_reg1 = GPR1[RT];
8640   {
8641     GPR_UW(destreg,0) = RT_UW(0);
8642     GPR_UW(destreg,1) = RT_UW(2);
8643     GPR_UW(destreg,2) = RT_UW(1);
8644     GPR_UW(destreg,3) = RT_UW(3);
8645   }
8646 }
8647
8648 // end-sanitize-r5900
8649 // start-sanitize-r5900
8650
8651 01110000000,5.RT,5.RD,11010001001:MMI2:32::PEXOH
8652 *r5900:
8653 {
8654   unsigned32 instruction = instruction_0;
8655   int destreg = ((instruction >> 11) & 0x0000001F);
8656   signed_word rt_reg = GPR[RT];
8657   signed_word rt_reg1 = GPR1[RT];
8658   {
8659     GPR_UH(destreg,0) = RT_UH(2);
8660     GPR_UH(destreg,1) = RT_UH(1);
8661     GPR_UH(destreg,2) = RT_UH(0);
8662     GPR_UH(destreg,3) = RT_UH(3);
8663     GPR_UH(destreg,4) = RT_UH(6);
8664     GPR_UH(destreg,5) = RT_UH(5);
8665     GPR_UH(destreg,6) = RT_UH(4);
8666     GPR_UH(destreg,7) = RT_UH(7);
8667   }
8668 }
8669
8670 // end-sanitize-r5900
8671 // start-sanitize-r5900
8672
8673 01110000000,5.RT,5.RD,11110001001:MMI2:32::PEXOW
8674 *r5900:
8675 {
8676   unsigned32 instruction = instruction_0;
8677   int destreg = ((instruction >> 11) & 0x0000001F);
8678   signed_word rt_reg = GPR[RT];
8679   signed_word rt_reg1 = GPR1[RT];
8680   {
8681     GPR_UW(destreg,0) = RT_UW(2);
8682     GPR_UW(destreg,1) = RT_UW(1);
8683     GPR_UW(destreg,2) = RT_UW(0);
8684     GPR_UW(destreg,3) = RT_UW(3);
8685   }
8686 }
8687
8688 // end-sanitize-r5900
8689 // start-sanitize-r5900
8690
8691 01110000000,5.RT,5.RD,11110001000:MMI0:32::PEXT5
8692 *r5900:
8693 {
8694   unsigned32 instruction = instruction_0;
8695   int destreg = ((instruction >> 11) & 0x0000001F);
8696   signed_word rt_reg = GPR[RT];
8697   signed_word rt_reg1 = GPR1[RT];
8698   {
8699     int i;
8700     for(i=0;i<WORDS_IN_MMI_REGS;i++)
8701       {
8702         unsigned32 x = RT_UW(i);
8703         GPR_UW(destreg,i) = ((x & (1  << 15)) << (31 - 15))
8704           | ((x & (31 << 10)) << (19 - 10))
8705           | ((x & (31 << 5))  << (11 - 5))
8706           | ((x & (31 << 0))  << (3  - 0));
8707       }
8708   }
8709 }
8710
8711 // end-sanitize-r5900
8712 // start-sanitize-r5900
8713
8714 011100,5.RS,5.RT,5.RD,11010001000:MMI0:32::PEXTLB
8715 *r5900:
8716 {
8717   unsigned32 instruction = instruction_0;
8718   int destreg = ((instruction >> 11) & 0x0000001F);
8719   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8720   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8721   signed_word rt_reg = GPR[RT];
8722   signed_word rt_reg1 = GPR1[RT];
8723   {
8724     GPR_UB(destreg,0)  = RT_UB(0);
8725     GPR_UB(destreg,1)  = RS_UB(0);
8726     GPR_UB(destreg,2)  = RT_UB(1);
8727     GPR_UB(destreg,3)  = RS_UB(1);
8728     GPR_UB(destreg,4)  = RT_UB(2);
8729     GPR_UB(destreg,5)  = RS_UB(2);
8730     GPR_UB(destreg,6)  = RT_UB(3);
8731     GPR_UB(destreg,7)  = RS_UB(3);
8732     GPR_UB(destreg,8)  = RT_UB(4);
8733     GPR_UB(destreg,9)  = RS_UB(4);
8734     GPR_UB(destreg,10) = RT_UB(5);
8735     GPR_UB(destreg,11) = RS_UB(5);
8736     GPR_UB(destreg,12) = RT_UB(6);
8737     GPR_UB(destreg,13) = RS_UB(6);
8738     GPR_UB(destreg,14) = RT_UB(7);
8739     GPR_UB(destreg,15) = RS_UB(7);
8740   }
8741 }
8742
8743 // end-sanitize-r5900
8744 // start-sanitize-r5900
8745
8746 011100,5.RS,5.RT,5.RD,10110001000:MMI0:32::PEXTLH
8747 *r5900:
8748 {
8749   unsigned32 instruction = instruction_0;
8750   int destreg = ((instruction >> 11) & 0x0000001F);
8751   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8752   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8753   signed_word rt_reg = GPR[RT];
8754   signed_word rt_reg1 = GPR1[RT];
8755   {
8756     GPR_UH(destreg,0)  = RT_UH(0);
8757     GPR_UH(destreg,1)  = RS_UH(0);
8758     GPR_UH(destreg,2)  = RT_UH(1);
8759     GPR_UH(destreg,3)  = RS_UH(1);
8760     GPR_UH(destreg,4)  = RT_UH(2);
8761     GPR_UH(destreg,5)  = RS_UH(2);
8762     GPR_UH(destreg,6)  = RT_UH(3);
8763     GPR_UH(destreg,7)  = RS_UH(3);
8764   }
8765 }
8766
8767 // end-sanitize-r5900
8768 // start-sanitize-r5900
8769
8770 011100,5.RS,5.RT,5.RD,10010001000:MMI0:32::PEXTLW
8771 *r5900:
8772 {
8773   unsigned32 instruction = instruction_0;
8774   int destreg = ((instruction >> 11) & 0x0000001F);
8775   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8776   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8777   signed_word rt_reg = GPR[RT];
8778   signed_word rt_reg1 = GPR1[RT];
8779   {
8780     GPR_UW(destreg,0)  = RT_UW(0);
8781     GPR_UW(destreg,1)  = RS_UW(0);
8782     GPR_UW(destreg,2)  = RT_UW(1);
8783     GPR_UW(destreg,3)  = RS_UW(1);
8784   }
8785 }
8786
8787 // end-sanitize-r5900
8788 // start-sanitize-r5900
8789
8790 011100,5.RS,5.RT,5.RD,11010101000:MMI1:32::PEXTUB
8791 *r5900:
8792 {
8793   unsigned32 instruction = instruction_0;
8794   int destreg = ((instruction >> 11) & 0x0000001F);
8795   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8796   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8797   signed_word rt_reg = GPR[RT];
8798   signed_word rt_reg1 = GPR1[RT];
8799   {
8800     GPR_UB(destreg,0)  = RT_UB(8);
8801     GPR_UB(destreg,1)  = RS_UB(8);
8802     GPR_UB(destreg,2)  = RT_UB(9);
8803     GPR_UB(destreg,3)  = RS_UB(9);
8804     GPR_UB(destreg,4)  = RT_UB(10);
8805     GPR_UB(destreg,5)  = RS_UB(10);
8806     GPR_UB(destreg,6)  = RT_UB(11);
8807     GPR_UB(destreg,7)  = RS_UB(11);
8808     GPR_UB(destreg,8)  = RT_UB(12);
8809     GPR_UB(destreg,9)  = RS_UB(12);
8810     GPR_UB(destreg,10) = RT_UB(13);
8811     GPR_UB(destreg,11) = RS_UB(13);
8812     GPR_UB(destreg,12) = RT_UB(14);
8813     GPR_UB(destreg,13) = RS_UB(14);
8814     GPR_UB(destreg,14) = RT_UB(15);
8815     GPR_UB(destreg,15) = RS_UB(15);
8816   }
8817 }
8818
8819 // end-sanitize-r5900
8820 // start-sanitize-r5900
8821
8822 011100,5.RS,5.RT,5.RD,10110101000:MMI1:32::PEXTUH
8823 *r5900:
8824 {
8825   unsigned32 instruction = instruction_0;
8826   int destreg = ((instruction >> 11) & 0x0000001F);
8827   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8828   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8829   signed_word rt_reg = GPR[RT];
8830   signed_word rt_reg1 = GPR1[RT];
8831   {
8832     GPR_UH(destreg,0)  = RT_UH(4);
8833     GPR_UH(destreg,1)  = RS_UH(4);
8834     GPR_UH(destreg,2)  = RT_UH(5);
8835     GPR_UH(destreg,3)  = RS_UH(5);
8836     GPR_UH(destreg,4)  = RT_UH(6);
8837     GPR_UH(destreg,5)  = RS_UH(6);
8838     GPR_UH(destreg,6)  = RT_UH(7);
8839     GPR_UH(destreg,7)  = RS_UH(7);
8840   }
8841 }
8842
8843 // end-sanitize-r5900
8844 // start-sanitize-r5900
8845
8846 011100,5.RS,5.RT,5.RD,10010101000:MMI1:32::PEXTUW
8847 *r5900:
8848 {
8849   unsigned32 instruction = instruction_0;
8850   int destreg = ((instruction >> 11) & 0x0000001F);
8851   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8852   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8853   signed_word rt_reg = GPR[RT];
8854   signed_word rt_reg1 = GPR1[RT];
8855   {
8856     GPR_UW(destreg,0)  = RT_UW(2);
8857     GPR_UW(destreg,1)  = RS_UW(2);
8858     GPR_UW(destreg,2)  = RT_UW(3);
8859     GPR_UW(destreg,3)  = RS_UW(3);
8860   }
8861 }
8862
8863 // end-sanitize-r5900
8864 // start-sanitize-r5900
8865
8866 011100,5.RS,5.RT,5.RD,10001001001:MMI2:32::PHMADDH
8867 *r5900:
8868 {
8869   unsigned32 instruction = instruction_0;
8870   int destreg = ((instruction >> 11) & 0x0000001F);
8871   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8872   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8873   signed_word rt_reg = GPR[RT];
8874   signed_word rt_reg1 = GPR1[RT];
8875   {
8876     GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) + (RS_SH(0) * RT_SH(0));
8877     GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) + (RS_SH(2) * RT_SH(2));
8878     GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) + (RS_SH(4) * RT_SH(4));
8879     GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) + (RS_SH(6) * RT_SH(6));
8880   }
8881 }
8882
8883 // end-sanitize-r5900
8884 // start-sanitize-r5900
8885
8886 011100,5.RS,5.RT,5.RD,10101001001:MMI2:32::PHMSUBH
8887 *r5900:
8888 {
8889   unsigned32 instruction = instruction_0;
8890   int destreg = ((instruction >> 11) & 0x0000001F);
8891   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8892   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8893   signed_word rt_reg = GPR[RT];
8894   signed_word rt_reg1 = GPR1[RT];
8895   {
8896     GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(1) * RT_SH(1)) - (RS_SH(0) * RT_SH(0));
8897     GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(3) * RT_SH(3)) - (RS_SH(2) * RT_SH(2));
8898     GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(5) * RT_SH(5)) - (RS_SH(4) * RT_SH(4));
8899     GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(7) * RT_SH(7)) - (RS_SH(6) * RT_SH(6));
8900   }
8901 }
8902
8903 // end-sanitize-r5900
8904 // start-sanitize-r5900
8905
8906 011100,5.RS,5.RT,5.RD,01010001001:MMI2:32::PINTH
8907 *r5900:
8908 {
8909   unsigned32 instruction = instruction_0;
8910   int destreg = ((instruction >> 11) & 0x0000001F);
8911   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8912   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8913   signed_word rt_reg = GPR[RT];
8914   signed_word rt_reg1 = GPR1[RT];
8915   {
8916     GPR_UH(destreg,0)  = RT_UH(0);
8917     GPR_UH(destreg,1)  = RS_UH(4);
8918     GPR_UH(destreg,2)  = RT_UH(1);
8919     GPR_UH(destreg,3)  = RS_UH(5);
8920     GPR_UH(destreg,4)  = RT_UH(2);
8921     GPR_UH(destreg,5)  = RS_UH(6);
8922     GPR_UH(destreg,6)  = RT_UH(3);
8923     GPR_UH(destreg,7)  = RS_UH(7);
8924   }
8925 }
8926
8927 // end-sanitize-r5900
8928 // start-sanitize-r5900
8929
8930 011100,5.RS,5.RT,5.RD,01010101001:MMI3:32::PINTOH
8931 *r5900:
8932 {
8933   unsigned32 instruction = instruction_0;
8934   int destreg = ((instruction >> 11) & 0x0000001F);
8935   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8936   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8937   signed_word rt_reg = GPR[RT];
8938   signed_word rt_reg1 = GPR1[RT];
8939   {
8940     GPR_UH(destreg,0) = RT_UH(0);
8941     GPR_UH(destreg,1) = RS_UH(0);
8942     GPR_UH(destreg,2) = RT_UH(2);
8943     GPR_UH(destreg,3) = RS_UH(2);
8944     GPR_UH(destreg,4) = RT_UH(4);
8945     GPR_UH(destreg,5) = RS_UH(4);
8946     GPR_UH(destreg,6) = RT_UH(6);
8947     GPR_UH(destreg,7) = RS_UH(6);
8948   }
8949 }
8950
8951 // end-sanitize-r5900
8952 // start-sanitize-r5900
8953
8954 011100,5.RS,00000,5.RD,00000000100:MMINORM:32::PLZCW
8955 *r5900:
8956 {
8957   unsigned32 instruction = instruction_0;
8958   int destreg = ((instruction >> 11) & 0x0000001F);
8959   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8960   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8961   {
8962     unsigned long value;
8963     int test;
8964     int count;
8965     int i;
8966     value = RS_UW(0);
8967     count = 0;
8968     test = !!(value & (1 << 31));
8969     for(i=30; i>=0 && (test == !!(value & (1 << i))); i--)
8970       count++;
8971     GPR_UW(destreg,0) = count;
8972     value = RS_UW(1);
8973     count = 0;
8974     test = !!(value & (1 << 31));
8975     for(i=30; i>=0 && (test == !!(value & (1 << i))); i--)
8976       count++;
8977     GPR_UW(destreg,1) = count;
8978   }
8979 }
8980
8981 // end-sanitize-r5900
8982 // start-sanitize-r5900
8983
8984 011100,5.RS,5.RT,5.RD,10000001001:MMI2:32::PMADDH
8985 *r5900:
8986 {
8987   unsigned32 instruction = instruction_0;
8988   int destreg = ((instruction >> 11) & 0x0000001F);
8989   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
8990   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
8991   signed_word rt_reg = GPR[RT];
8992   signed_word rt_reg1 = GPR1[RT];
8993   {
8994     GPR_SW(destreg,0) = LO_SW(0) += (RS_SH(0) * RT_SH(0));
8995     LO_SW(1) += (RS_SH(1) * RT_SH(1));
8996     GPR_SW(destreg,1) = HI_SW(0) += (RS_SH(2) * RT_SH(2));
8997     HI_SW(1) += (RS_SH(3) * RT_SH(3));
8998     GPR_SW(destreg,2) = LO_SW(2) += (RS_SH(4) * RT_SH(4));
8999     LO_SW(3) += (RS_SH(5) * RT_SH(5));
9000     GPR_SW(destreg,3) = HI_SW(2) += (RS_SH(6) * RT_SH(6));
9001     HI_SW(3) += (RS_SH(7) * RT_SH(7));
9002   }
9003 }
9004
9005 // end-sanitize-r5900
9006 // start-sanitize-r5900
9007
9008 011100,5.RS,5.RT,5.RD,00000101001:MMI3:32::PMADDUW
9009 *r5900:
9010 {
9011   unsigned32 instruction = instruction_0;
9012   int destreg = ((instruction >> 11) & 0x0000001F);
9013   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9014   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9015   signed_word rt_reg = GPR[RT];
9016   signed_word rt_reg1 = GPR1[RT];
9017   {
9018     unsigned64 sum0 = U8_4 (HI_SW(0), LO_SW(0));
9019     unsigned64 sum1 = U8_4 (HI_SW(2), LO_SW(2));
9020     unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0);
9021     unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2);
9022     sum0 += prod0;
9023     sum1 += prod1;
9024     GPR_UD(destreg,0) = sum0;
9025     GPR_UD(destreg,1) = sum1;
9026     LO  = SIGNEXTEND( sum0, 32 );
9027     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
9028     LO1 = SIGNEXTEND( sum1, 32 );
9029     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
9030   }
9031 }
9032
9033 // end-sanitize-r5900
9034 // start-sanitize-r5900
9035
9036 011100,5.RS,5.RT,5.RD,00000001001:MMI2:32::PMADDW
9037 *r5900:
9038 {
9039   unsigned32 instruction = instruction_0;
9040   int destreg = ((instruction >> 11) & 0x0000001F);
9041   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9042   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9043   signed_word rt_reg = GPR[RT];
9044   signed_word rt_reg1 = GPR1[RT];
9045   {
9046     signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) );
9047     signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) );
9048     signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
9049     signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
9050     sum0 += prod0;
9051     sum1 += prod1;
9052     GPR_SD(destreg,0) = sum0;
9053     GPR_SD(destreg,1) = sum1;
9054     LO  = SIGNEXTEND( sum0, 32 );
9055     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
9056     LO1 = SIGNEXTEND( sum1, 32 );
9057     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
9058   }
9059 }
9060
9061 // end-sanitize-r5900
9062 // start-sanitize-r5900
9063
9064 011100,5.RS,5.RT,5.RD,00111001000:MMI0:32::PMAXH
9065 *r5900:
9066 {
9067   unsigned32 instruction = instruction_0;
9068   int destreg = ((instruction >> 11) & 0x0000001F);
9069   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9070   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9071   signed_word rt_reg = GPR[RT];
9072   signed_word rt_reg1 = GPR1[RT];
9073   {
9074     int i;
9075     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9076       {
9077         if (RS_SH(i) > RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i);
9078         else                        GPR_SH(destreg,i) = RT_SH(i);
9079       }
9080   }
9081 }
9082
9083 // end-sanitize-r5900
9084 // start-sanitize-r5900
9085
9086 011100,5.RS,5.RT,5.RD,00011001000:MMI0:32::PMAXW
9087 *r5900:
9088 {
9089   unsigned32 instruction = instruction_0;
9090   int destreg = ((instruction >> 11) & 0x0000001F);
9091   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9092   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9093   signed_word rt_reg = GPR[RT];
9094   signed_word rt_reg1 = GPR1[RT];
9095   {
9096     int i;
9097     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9098       {
9099         if (RS_SW(i) > RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i);
9100         else                        GPR_SW(destreg,i) = RT_SW(i);
9101       }
9102   }
9103 }
9104
9105 // end-sanitize-r5900
9106 // start-sanitize-r5900
9107
9108 0111000000000000,5.RD,01000001001:MMI2:32::PMFHI
9109 *r5900:
9110 {
9111   unsigned32 instruction = instruction_0;
9112   int destreg = ((instruction >> 11) & 0x0000001F);
9113   {
9114     GPR_SD(destreg,0) = HI;
9115     GPR_SD(destreg,1) = HI1;
9116   }
9117 }
9118
9119 // end-sanitize-r5900
9120 // start-sanitize-r5900
9121
9122 0111000000000000,5.RD,01001001001:MMI2:32::PMFLO
9123 *r5900:
9124 {
9125   unsigned32 instruction = instruction_0;
9126   int destreg = ((instruction >> 11) & 0x0000001F);
9127   {
9128     GPR_SD(destreg,0) = LO;
9129     GPR_SD(destreg,1) = LO1;
9130   }
9131 }
9132
9133 // end-sanitize-r5900
9134 // start-sanitize-r5900
9135
9136 0111000000000000,5.RD,5.SHIFT,110000:MMINORM:32::PMFHL
9137 *r5900:
9138 {
9139   unsigned32 instruction = instruction_0;
9140   int op1 = ((instruction >> 6) & 0x0000001F);
9141   int destreg = ((instruction >> 11) & 0x0000001F);
9142   {
9143     if (op1 == 0)
9144       {
9145         GPR_UW(destreg,0) = LO_UW(0);
9146         GPR_UW(destreg,1) = HI_UW(0);
9147         GPR_UW(destreg,2) = LO_UW(2);
9148         GPR_UW(destreg,3) = HI_UW(2);
9149       }
9150     else if (op1 == 1)
9151       {
9152         GPR_UW(destreg,0) = LO_UW(1);
9153         GPR_UW(destreg,1) = HI_UW(1);
9154         GPR_UW(destreg,2) = LO_UW(3);
9155         GPR_UW(destreg,3) = HI_UW(3);
9156       }
9157     else if (op1 == 2)
9158       {
9159         /* NOTE: This code implements a saturate according to the
9160            figure on page B-115 and not according to the
9161            definition on page B-113 */
9162         signed64 t = ((unsigned64)HI_UW(0) << 32) | (unsigned64)LO_UW(0);
9163         signed64 u = ((unsigned64)HI_UW(2) << 32) | (unsigned64)LO_UW(2);
9164         if ( t > SIGNED64 (0x000000007FFFFFFF) )
9165           GPR_SD(destreg,0) = SIGNED64 (0x000000007FFFFFFF);
9166         else if ( t < - SIGNED64 (0x0000000080000000) )
9167           GPR_SD(destreg,0) = - SIGNED64 (0x0000000080000000);
9168         else
9169           GPR_SD(destreg,0) = t;
9170         if ( u > SIGNED64 (0x000000007FFFFFFF) )
9171           GPR_SD(destreg,1) = SIGNED64 (0x000000007FFFFFFF);
9172         else if ( u < - SIGNED64 (0x0000000080000000) )
9173           GPR_SD(destreg,1) = - SIGNED64 (0x0000000080000000);
9174         else
9175           GPR_SD(destreg,1) = u;
9176       }
9177     else if (op1 == 3)
9178       {
9179         GPR_UH(destreg,0) = LO_UH(0);
9180         GPR_UH(destreg,1) = LO_UH(2);
9181         GPR_UH(destreg,2) = HI_UH(0);
9182         GPR_UH(destreg,3) = HI_UH(2);
9183         GPR_UH(destreg,4) = LO_UH(4);
9184         GPR_UH(destreg,5) = LO_UH(6);
9185         GPR_UH(destreg,6) = HI_UH(4);
9186         GPR_UH(destreg,7) = HI_UH(6);
9187       }
9188     else if (op1 == 4)
9189       {
9190         if (LO_SW(0) > 0x7FFF)
9191           GPR_UH(destreg,0) = 0x7FFF;
9192         else if (LO_SW(0) < -0x8000)
9193           GPR_UH(destreg,0) = 0x8000;
9194         else
9195           GPR_UH(destreg,0) = LO_UH(0);
9196         if (LO_SW(1) > 0x7FFF)
9197           GPR_UH(destreg,1) = 0x7FFF;
9198         else if (LO_SW(1) < -0x8000)
9199           GPR_UH(destreg,1) = 0x8000;
9200         else
9201           GPR_UH(destreg,1) = LO_UH(2);
9202         if (HI_SW(0) > 0x7FFF)
9203           GPR_UH(destreg,2) = 0x7FFF;
9204         else if (HI_SW(0) < -0x8000)
9205           GPR_UH(destreg,2) = 0x8000;
9206         else
9207           GPR_UH(destreg,2) = HI_UH(0);
9208         if (HI_SW(1) > 0x7FFF)
9209           GPR_UH(destreg,3) = 0x7FFF;
9210         else if (HI_SW(1) < -0x8000)
9211           GPR_UH(destreg,3) = 0x8000;
9212         else
9213           GPR_UH(destreg,3) = HI_UH(2);
9214         if (LO_SW(2) > 0x7FFF)
9215           GPR_UH(destreg,4) = 0x7FFF;
9216         else if (LO_SW(2) < -0x8000)
9217           GPR_UH(destreg,4) = 0x8000;
9218         else
9219           GPR_UH(destreg,4) = LO_UH(4);
9220         if (LO_SW(3) > 0x7FFF)
9221           GPR_UH(destreg,5) = 0x7FFF;
9222         else if (LO_SW(3) < -0x8000)
9223           GPR_UH(destreg,5) = 0x8000;
9224         else
9225           GPR_UH(destreg,5) = LO_UH(6);
9226         if (HI_SW(2) > 0x7FFF)
9227           GPR_UH(destreg,6) = 0x7FFF;
9228         else if (HI_SW(2) < -0x8000)
9229           GPR_UH(destreg,6) = 0x8000;
9230         else
9231           GPR_UH(destreg,6) = HI_UH(4);
9232         if (HI_SW(3) > 0x7FFF)
9233           GPR_UH(destreg,7) = 0x7FFF;
9234         else if (HI_SW(3) < -0x8000)
9235           GPR_UH(destreg,7) = 0x8000;
9236         else
9237           GPR_UH(destreg,7) = HI_UH(6);
9238       }
9239   }
9240 }
9241
9242 // end-sanitize-r5900
9243 // start-sanitize-r5900
9244
9245 011100,5.RS,5.RT,5.RD,00111101000:MMI1:32::PMINH
9246 *r5900:
9247 {
9248   unsigned32 instruction = instruction_0;
9249   int destreg = ((instruction >> 11) & 0x0000001F);
9250   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9251   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9252   signed_word rt_reg = GPR[RT];
9253   signed_word rt_reg1 = GPR1[RT];
9254   {
9255     int i;
9256     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9257       {
9258         if (RS_SH(i) < RT_SH(i)) GPR_SH(destreg,i) = RS_SH(i);
9259         else                        GPR_SH(destreg,i) = RT_SH(i);
9260       }
9261   }
9262 }
9263
9264 // end-sanitize-r5900
9265 // start-sanitize-r5900
9266
9267 011100,5.RS,5.RT,5.RD,00011101000:MMI1:32::PMINW
9268 *r5900:
9269 {
9270   unsigned32 instruction = instruction_0;
9271   int destreg = ((instruction >> 11) & 0x0000001F);
9272   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9273   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9274   signed_word rt_reg = GPR[RT];
9275   signed_word rt_reg1 = GPR1[RT];
9276   {
9277     int i;
9278     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9279       {
9280         if (RS_SW(i) < RT_SW(i)) GPR_SW(destreg,i) = RS_SW(i);
9281         else                        GPR_SW(destreg,i) = RT_SW(i);
9282       }
9283   }
9284 }
9285
9286 // end-sanitize-r5900
9287 // start-sanitize-r5900
9288
9289 011100,5.RS,5.RT,5.RD,10100001001:MMI2:32::PMSUBH
9290 *r5900:
9291 {
9292   unsigned32 instruction = instruction_0;
9293   int destreg = ((instruction >> 11) & 0x0000001F);
9294   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9295   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9296   signed_word rt_reg = GPR[RT];
9297   signed_word rt_reg1 = GPR1[RT];
9298   {
9299     GPR_SW(destreg,0) = LO_SW(0) -= (RS_SH(0) * RT_SH(0));
9300     LO_SW(1) -= (RS_SH(1) * RT_SH(1));
9301     GPR_SW(destreg,1) = HI_SW(0) -= (RS_SH(2) * RT_SH(2));
9302     HI_SW(1) -= (RS_SH(3) * RT_SH(3));
9303     GPR_SW(destreg,2) = LO_SW(2) -= (RS_SH(4) * RT_SH(4));
9304     LO_SW(3) -= (RS_SH(5) * RT_SH(5));
9305     GPR_SW(destreg,3) = HI_SW(2) -= (RS_SH(6) * RT_SH(6));
9306     HI_SW(3) -= (RS_SH(7) * RT_SH(7));
9307   }
9308 }
9309
9310 // end-sanitize-r5900
9311 // start-sanitize-r5900
9312
9313 011100,5.RS,5.RT,5.RD,00100001001:MMI2:32::PMSUBW
9314 *r5900:
9315 {
9316   unsigned32 instruction = instruction_0;
9317   int destreg = ((instruction >> 11) & 0x0000001F);
9318   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9319   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9320   signed_word rt_reg = GPR[RT];
9321   signed_word rt_reg1 = GPR1[RT];
9322   {
9323     signed64 sum0 = WORD64( HI_SW(0), LO_SW(0) );
9324     signed64 sum1 = WORD64( HI_SW(2), LO_SW(2) );
9325     signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
9326     signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
9327     sum0 -= prod0;
9328     sum1 -= prod1;
9329     GPR_SD(destreg,0) = sum0;
9330     GPR_SD(destreg,1) = sum1;
9331     LO  = SIGNEXTEND( sum0, 32 );
9332     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
9333     LO1 = SIGNEXTEND( sum1, 32 );
9334     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
9335   }
9336 }
9337
9338 // end-sanitize-r5900
9339 // start-sanitize-r5900
9340
9341 011100,5.RS,000000000001000101001:MMI3:32::PMTHI
9342 *r5900:
9343 {
9344   unsigned32 instruction = instruction_0;
9345   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9346   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9347   {
9348     HI  = RS_SD(0);
9349     HI1 = RS_SD(1);
9350   }
9351 }
9352
9353 // end-sanitize-r5900
9354 // start-sanitize-r5900
9355
9356 011100,5.RS,000000000001001101001:MMI3:32::PMTLO
9357 *r5900:
9358 {
9359   unsigned32 instruction = instruction_0;
9360   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9361   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9362   {
9363     LO  = RS_SD(0);
9364     LO1 = RS_SD(1);
9365   }
9366 }
9367
9368 // end-sanitize-r5900
9369 // start-sanitize-r5900
9370
9371 011100,5.RS,000000000000000110001:MMINORM:32::PMTHL.LW
9372 *r5900:
9373 {
9374   unsigned32 instruction = instruction_0;
9375   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9376   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9377   {
9378     LO_UW(0) = RS_UW(0);
9379     HI_UW(0) = RS_UW(1);
9380     LO_UW(2) = RS_UW(2);
9381     HI_UW(2) = RS_UW(3);
9382   }
9383 }
9384
9385 // end-sanitize-r5900
9386 // start-sanitize-r5900
9387
9388 011100,5.RS,5.RT,5.RD,11100001001:MMI2:32::PMULTH
9389 *r5900:
9390 {
9391   unsigned32 instruction = instruction_0;
9392   int destreg = ((instruction >> 11) & 0x0000001F);
9393   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9394   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9395   signed_word rt_reg = GPR[RT];
9396   signed_word rt_reg1 = GPR1[RT];
9397   {
9398     GPR_SW(destreg,0) = LO_SW(0) = (RS_SH(0) * RT_SH(0));
9399     LO_SW(1) = (RS_SH(1) * RT_SH(1));
9400     GPR_SW(destreg,1) = HI_SW(0) = (RS_SH(2) * RT_SH(2));
9401     HI_SW(1) = (RS_SH(3) * RT_SH(3));
9402     GPR_SW(destreg,2) = LO_SW(2) = (RS_SH(4) * RT_SH(4));
9403     LO_SW(3) = (RS_SH(5) * RT_SH(5));
9404     GPR_SW(destreg,3) = HI_SW(2) = (RS_SH(6) * RT_SH(6));
9405     HI_SW(3) = (RS_SH(7) * RT_SH(7));
9406   }
9407 }
9408
9409 // end-sanitize-r5900
9410 // start-sanitize-r5900
9411
9412 011100,5.RS,5.RT,5.RD,01100101001:MMI3:32::PMULTUW
9413 *r5900:
9414 {
9415   unsigned32 instruction = instruction_0;
9416   int destreg = ((instruction >> 11) & 0x0000001F);
9417   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9418   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9419   signed_word rt_reg = GPR[RT];
9420   signed_word rt_reg1 = GPR1[RT];
9421   {
9422     unsigned64 sum0 = 0;
9423     unsigned64 sum1 = 0;
9424     unsigned64 prod0 = (unsigned64)RS_UW(0) * (unsigned64)RT_UW(0);
9425     unsigned64 prod1 = (unsigned64)RS_UW(2) * (unsigned64)RT_UW(2);
9426     sum0 = prod0;
9427     sum1 = prod1;
9428     GPR_UD(destreg,0) = sum0;
9429     GPR_UD(destreg,1) = sum1;
9430     LO  = SIGNEXTEND( sum0, 32 );
9431     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
9432     LO1 = SIGNEXTEND( sum1, 32 );
9433     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
9434   }
9435 }
9436
9437 // end-sanitize-r5900
9438 // start-sanitize-r5900
9439
9440 011100,5.RS,5.RT,5.RD,01100001001:MMI2:32::PMULTW
9441 *r5900:
9442 {
9443   unsigned32 instruction = instruction_0;
9444   int destreg = ((instruction >> 11) & 0x0000001F);
9445   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9446   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9447   signed_word rt_reg = GPR[RT];
9448   signed_word rt_reg1 = GPR1[RT];
9449   {
9450     signed64 sum0 = 0;
9451     signed64 sum1 = 0;
9452     signed64 prod0 = (signed64)RS_SW(0) * (signed64)RT_SW(0);
9453     signed64 prod1 = (signed64)RS_SW(2) * (signed64)RT_SW(2);
9454     sum0 = prod0;
9455     sum1 = prod1;
9456     GPR_SD(destreg,0) = sum0;
9457     GPR_SD(destreg,1) = sum1;
9458     LO  = SIGNEXTEND( sum0, 32 );
9459     HI  = SIGNEXTEND( VH4_8(sum0), 32 );
9460     LO1 = SIGNEXTEND( sum1, 32 );
9461     HI1 = SIGNEXTEND( VH4_8(sum1), 32 );
9462   }
9463 }
9464
9465 // end-sanitize-r5900
9466 // start-sanitize-r5900
9467
9468 011100,5.RS,5.RT,5.RD,10011101001:MMI3:32::PNOR
9469 *r5900:
9470 {
9471   unsigned32 instruction = instruction_0;
9472   int destreg = ((instruction >> 11) & 0x0000001F);
9473   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9474   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9475   signed_word rt_reg = GPR[RT];
9476   signed_word rt_reg1 = GPR1[RT];
9477   {
9478     int i;
9479     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9480       GPR_UW(destreg,i) = ~(RS_UW(i) | RT_UW(i));
9481   }
9482 }
9483
9484 // end-sanitize-r5900
9485 // start-sanitize-r5900
9486
9487 011100,5.RS,5.RT,5.RD,10010101001:MMI3:32::POR
9488 *r5900:
9489 {
9490   unsigned32 instruction = instruction_0;
9491   int destreg = ((instruction >> 11) & 0x0000001F);
9492   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9493   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9494   signed_word rt_reg = GPR[RT];
9495   signed_word rt_reg1 = GPR1[RT];
9496   {
9497     int i;
9498     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9499       GPR_UW(destreg,i) = (RS_UW(i) | RT_UW(i));
9500   }
9501 }
9502
9503 // end-sanitize-r5900
9504 // start-sanitize-r5900
9505
9506 01110000000,5.RT,5.RD,11111001000:MMI0:32::PPAC5
9507 *r5900:
9508 {
9509   unsigned32 instruction = instruction_0;
9510   int destreg = ((instruction >> 11) & 0x0000001F);
9511   signed_word rt_reg = GPR[RT];
9512   signed_word rt_reg1 = GPR1[RT];
9513   {
9514     int i;
9515     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9516       {
9517         unsigned32 x = RT_UW(i);
9518         GPR_UW(destreg,i) = ((x & (1  << 31)) >> (31 - 15))
9519           | ((x & (31 << 19)) >> (19 - 10))
9520           | ((x & (31 << 11)) >> (11 - 5))
9521           | ((x & (31 <<  3)) >> (3  - 0));
9522       }
9523   }
9524 }
9525
9526 // end-sanitize-r5900
9527 // start-sanitize-r5900
9528
9529 011100,5.RS,5.RT,5.RD,11011001000:MMI0:32::PPACB
9530 *r5900:
9531 {
9532   unsigned32 instruction = instruction_0;
9533   int destreg = ((instruction >> 11) & 0x0000001F);
9534   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9535   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9536   signed_word rt_reg = GPR[RT];
9537   signed_word rt_reg1 = GPR1[RT];
9538   {
9539     GPR_UB(destreg,0)  = RT_UB(0);
9540     GPR_UB(destreg,1)  = RT_UB(2);
9541     GPR_UB(destreg,2)  = RT_UB(4);
9542     GPR_UB(destreg,3)  = RT_UB(6);
9543     GPR_UB(destreg,4)  = RT_UB(8);
9544     GPR_UB(destreg,5)  = RT_UB(10);
9545     GPR_UB(destreg,6)  = RT_UB(12);
9546     GPR_UB(destreg,7)  = RT_UB(14);
9547     GPR_UB(destreg,8)  = RS_UB(0);
9548     GPR_UB(destreg,9)  = RS_UB(2);
9549     GPR_UB(destreg,10) = RS_UB(4);
9550     GPR_UB(destreg,11) = RS_UB(6);
9551     GPR_UB(destreg,12) = RS_UB(8);
9552     GPR_UB(destreg,13) = RS_UB(10);
9553     GPR_UB(destreg,14) = RS_UB(12);
9554     GPR_UB(destreg,15) = RS_UB(14);
9555   }
9556 }
9557
9558 // end-sanitize-r5900
9559 // start-sanitize-r5900
9560
9561 011100,5.RS,5.RT,5.RD,10111001000:MMI0:32::PPACH
9562 *r5900:
9563 {
9564   unsigned32 instruction = instruction_0;
9565   int destreg = ((instruction >> 11) & 0x0000001F);
9566   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9567   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9568   signed_word rt_reg = GPR[RT];
9569   signed_word rt_reg1 = GPR1[RT];
9570   {
9571     GPR_UH(destreg,0)  = RT_UH(0);
9572     GPR_UH(destreg,1)  = RT_UH(2);
9573     GPR_UH(destreg,2)  = RT_UH(4);
9574     GPR_UH(destreg,3)  = RT_UH(6);
9575     GPR_UH(destreg,4)  = RS_UH(0);
9576     GPR_UH(destreg,5)  = RS_UH(2);
9577     GPR_UH(destreg,6)  = RS_UH(4);
9578     GPR_UH(destreg,7)  = RS_UH(6);
9579   }
9580 }
9581
9582 // end-sanitize-r5900
9583 // start-sanitize-r5900
9584
9585 011100,5.RS,5.RT,5.RD,10011001000:MMI0:32::PPACW
9586 *r5900:
9587 {
9588   unsigned32 instruction = instruction_0;
9589   int destreg = ((instruction >> 11) & 0x0000001F);
9590   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9591   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9592   signed_word rt_reg = GPR[RT];
9593   signed_word rt_reg1 = GPR1[RT];
9594   {
9595     GPR_UW(destreg,0)  = RT_UW(0);
9596     GPR_UW(destreg,1)  = RT_UW(2);
9597     GPR_UW(destreg,2)  = RS_UW(0);
9598     GPR_UW(destreg,3)  = RS_UW(2);
9599   }
9600 }
9601
9602 // end-sanitize-r5900
9603 // start-sanitize-r5900
9604
9605 01110000000,5.RT,5.RD,11011001001:MMI2:32::PREVH
9606 *r5900:
9607 {
9608   unsigned32 instruction = instruction_0;
9609   int destreg = ((instruction >> 11) & 0x0000001F);
9610   signed_word rt_reg = GPR[RT];
9611   signed_word rt_reg1 = GPR1[RT];
9612   {
9613     GPR_UH(destreg,0)  = RT_UH(3);
9614     GPR_UH(destreg,1)  = RT_UH(2);
9615     GPR_UH(destreg,2)  = RT_UH(1);
9616     GPR_UH(destreg,3)  = RT_UH(0);
9617     GPR_UH(destreg,4)  = RT_UH(7);
9618     GPR_UH(destreg,5)  = RT_UH(6);
9619     GPR_UH(destreg,6)  = RT_UH(5);
9620     GPR_UH(destreg,7)  = RT_UH(4);
9621   }
9622 }
9623
9624 // end-sanitize-r5900
9625 // start-sanitize-r5900
9626
9627 01110000000,5.RT,5.RD,11111001001:MMI2:32::PROT3W
9628 *r5900:
9629 {
9630   unsigned32 instruction = instruction_0;
9631   int destreg = ((instruction >> 11) & 0x0000001F);
9632   signed_word rt_reg = GPR[RT];
9633   signed_word rt_reg1 = GPR1[RT];
9634   {
9635     GPR_UW(destreg,0)  = RT_UW(0);
9636     GPR_UW(destreg,1)  = RT_UW(3);
9637     GPR_UW(destreg,2)  = RT_UW(1);
9638     GPR_UW(destreg,3)  = RT_UW(2);
9639   }
9640 }
9641
9642 // end-sanitize-r5900
9643 // start-sanitize-r5900
9644
9645 01110000000,5.RT,5.RD,5.SHIFT,110100:MMINORM:32::PSLLH
9646 *r5900:
9647 {
9648   unsigned32 instruction = instruction_0;
9649   int op1 = ((instruction >> 6) & 0x0000001F);
9650   int destreg = ((instruction >> 11) & 0x0000001F);
9651   signed_word rt_reg = GPR[RT];
9652   signed_word rt_reg1 = GPR1[RT];
9653   {
9654     int shift_by = op1 & (16-1);
9655     int i;
9656     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9657       GPR_UH(destreg,i) = (RT_UH(i) << shift_by);
9658   }
9659 }
9660
9661 // end-sanitize-r5900
9662 // start-sanitize-r5900
9663
9664 011100,5.RS,5.RT,5.RD,00010001001:MMI2:32::PSLLVW
9665 *r5900:
9666 {
9667   unsigned32 instruction = instruction_0;
9668   int destreg = ((instruction >> 11) & 0x0000001F);
9669   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9670   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9671   signed_word rt_reg = GPR[RT];
9672   signed_word rt_reg1 = GPR1[RT];
9673   {
9674     int s0 = (RS_UB(0) & 0x1F);
9675     int s1 = (RS_UB(8) & 0x1F);
9676     signed32 temp0 = RT_UW(0) << s0;
9677     signed32 temp1 = RT_UW(2) << s1;
9678     GPR_SD(destreg,0) = (signed64)temp0;
9679     GPR_SD(destreg,1) = (signed64)temp1;
9680   }
9681 }
9682
9683 // end-sanitize-r5900
9684 // start-sanitize-r5900
9685
9686 01110000000,5.RT,5.RD,5.SHIFT,111100:MMINORM:32::PSLLW
9687 *r5900:
9688 {
9689   unsigned32 instruction = instruction_0;
9690   int op1 = ((instruction >> 6) & 0x0000001F);
9691   int destreg = ((instruction >> 11) & 0x0000001F);
9692   signed_word rt_reg = GPR[RT];
9693   signed_word rt_reg1 = GPR1[RT];
9694   {
9695     int shift_by = op1 & (32-1);
9696     int i;
9697     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9698       GPR_UW(destreg,i) = (RT_UW(i) << shift_by);
9699   }
9700 }
9701
9702 // end-sanitize-r5900
9703 // start-sanitize-r5900
9704
9705 01110000000,5.RT,5.RD,5.SHIFT,110111:MMINORM:32::PSRAH
9706 *r5900:
9707 {
9708   unsigned32 instruction = instruction_0;
9709   int op1 = ((instruction >> 6) & 0x0000001F);
9710   int destreg = ((instruction >> 11) & 0x0000001F);
9711   signed_word rt_reg = GPR[RT];
9712   signed_word rt_reg1 = GPR1[RT];
9713   {
9714     int shift_by = op1 & (16-1);
9715     int i;
9716     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9717       GPR_SH(destreg,i) = SIGNEXTEND( (RT_SH(i) >> shift_by), (16-shift_by) );
9718   }
9719 }
9720
9721 // end-sanitize-r5900
9722 // start-sanitize-r5900
9723
9724 011100,5.RS,5.RT,5.RD,00011101001:MMI3:32::PSRAVW
9725 *r5900:
9726 {
9727   unsigned32 instruction = instruction_0;
9728   int destreg = ((instruction >> 11) & 0x0000001F);
9729   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9730   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9731   signed_word rt_reg = GPR[RT];
9732   signed_word rt_reg1 = GPR1[RT];
9733   {
9734     GPR_SD(destreg,0) = SIGNEXTEND( (RT_SW (0) >> (RS_UB(0) & 0x1F)), 32-(RS_UB(0) & 0x1F) );
9735     GPR_SD(destreg,1) = SIGNEXTEND( (RT_SW (2) >> (RS_UB(8) & 0x1F)), 32-(RS_UB(8) & 0x1F) );
9736   }
9737 }
9738
9739 // end-sanitize-r5900
9740 // start-sanitize-r5900
9741
9742 01110000000,5.RT,5.RD,5.SHIFT,111111:MMINORM:32::PSRAW
9743 *r5900:
9744 {
9745   unsigned32 instruction = instruction_0;
9746   int op1 = ((instruction >> 6) & 0x0000001F);
9747   int destreg = ((instruction >> 11) & 0x0000001F);
9748   signed_word rt_reg = GPR[RT];
9749   signed_word rt_reg1 = GPR1[RT];
9750   {
9751     int shift_by = op1 & (32-1);
9752     int i;
9753     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9754       GPR_SW(destreg,i) = SIGNEXTEND( (RT_SW(i) >> shift_by), (32-shift_by) );
9755   }
9756 }
9757
9758 // end-sanitize-r5900
9759 // start-sanitize-r5900
9760
9761 01110000000,5.RT,5.RD,5.SHIFT,110110:MMINORM:32::PSRLH
9762 *r5900:
9763 {
9764   unsigned32 instruction = instruction_0;
9765   int op1 = ((instruction >> 6) & 0x0000001F);
9766   int destreg = ((instruction >> 11) & 0x0000001F);
9767   signed_word rt_reg = GPR[RT];
9768   signed_word rt_reg1 = GPR1[RT];
9769   {
9770     int shift_by = op1 & (16-1);
9771     int i;
9772     for(i=0;i<HALFWORDS_IN_MMI_REGS;i++)
9773       GPR_UH(destreg,i) = (RT_UH(i) >> shift_by);
9774   }
9775 }
9776
9777 // end-sanitize-r5900
9778 // start-sanitize-r5900
9779
9780 011100,5.RS,5.RT,5.RD,00011001001:MMI2:32::PSRLVW
9781 *r5900:
9782 {
9783   unsigned32 instruction = instruction_0;
9784   int destreg = ((instruction >> 11) & 0x0000001F);
9785   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9786   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9787   signed_word rt_reg = GPR[RT];
9788   signed_word rt_reg1 = GPR1[RT];
9789   {
9790     GPR_UD(destreg,0) = SIGNEXTEND ( RT_UW(0) >> (RS_UB(0) & 0x1F), 31);
9791     GPR_UD(destreg,1) = SIGNEXTEND ( RT_UW(2) >> (RS_UB(8) & 0x1F), 31);
9792   }
9793 }
9794
9795 // end-sanitize-r5900
9796 // start-sanitize-r5900
9797
9798 01110000000,5.RT,5.RD,5.SHIFT,111110:MMINORM:32::PSRLW
9799 *r5900:
9800 {
9801   unsigned32 instruction = instruction_0;
9802   int op1 = ((instruction >> 6) & 0x0000001F);
9803   int destreg = ((instruction >> 11) & 0x0000001F);
9804   signed_word rt_reg = GPR[RT];
9805   signed_word rt_reg1 = GPR1[RT];
9806   {
9807     int shift_by = op1 & (32-1);
9808     int i;
9809     for(i=0;i<WORDS_IN_MMI_REGS;i++)
9810       GPR_UW(destreg,i) = (RT_UW(i) >> shift_by);
9811   }
9812 }
9813
9814 // end-sanitize-r5900
9815 // start-sanitize-r5900
9816
9817 011100,5.RS,5.RT,5.RD,01001001000:MMI0:32::PSUBB
9818 *r5900:
9819 {
9820   unsigned32 instruction = instruction_0;
9821   int destreg = ((instruction >> 11) & 0x0000001F);
9822   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9823   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9824   signed_word rt_reg = GPR[RT];
9825   signed_word rt_reg1 = GPR1[RT];
9826   {
9827     int i;
9828     for (i=0; i < BYTES_IN_MMI_REGS; i++)
9829       {
9830         int s = RS_SB(i);
9831         int t = RT_SB(i);
9832         int r = s - t;
9833         GPR_SB(destreg,i) = r;
9834       }
9835   }
9836 }
9837
9838 // end-sanitize-r5900
9839 // start-sanitize-r5900
9840
9841 011100,5.RS,5.RT,5.RD,00101001000:MMI0:32::PSUBH
9842 *r5900:
9843 {
9844   unsigned32 instruction = instruction_0;
9845   int destreg = ((instruction >> 11) & 0x0000001F);
9846   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9847   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9848   signed_word rt_reg = GPR[RT];
9849   signed_word rt_reg1 = GPR1[RT];
9850   {
9851     int i;
9852     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9853       {
9854         int s = RS_SH(i);
9855         int t = RT_SH(i);
9856         int r = s - t;
9857         GPR_SH(destreg,i) = r;
9858       }
9859   }
9860 }
9861
9862 // end-sanitize-r5900
9863 // start-sanitize-r5900
9864
9865 011100,5.RS,5.RT,5.RD,11001001000:MMI0:32::PSUBSB
9866 *r5900:
9867 {
9868   unsigned32 instruction = instruction_0;
9869   int destreg = ((instruction >> 11) & 0x0000001F);
9870   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9871   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9872   signed_word rt_reg = GPR[RT];
9873   signed_word rt_reg1 = GPR1[RT];
9874   {
9875     int i;
9876     for (i=0; i < BYTES_IN_MMI_REGS; i++)
9877       {
9878         int s = RS_SB(i);
9879         int t = RT_SB(i);
9880         int r = s - t;
9881         if (r > 127)
9882           GPR_SB(destreg,i) = 127;
9883         else if (r < -128)
9884           GPR_SB(destreg,i) = -128;
9885         else
9886           GPR_SB(destreg,i) = r;
9887       }
9888   }
9889 }
9890
9891 // end-sanitize-r5900
9892 // start-sanitize-r5900
9893
9894 011100,5.RS,5.RT,5.RD,10101001000:MMI0:32::PSUBSH
9895 *r5900:
9896 {
9897   unsigned32 instruction = instruction_0;
9898   int destreg = ((instruction >> 11) & 0x0000001F);
9899   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9900   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9901   signed_word rt_reg = GPR[RT];
9902   signed_word rt_reg1 = GPR1[RT];
9903   {
9904     int i;
9905     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9906       {
9907         int s = RS_SH(i);
9908         int t = RT_SH(i);
9909         int r = s - t;
9910         if (r > 32767)
9911           GPR_SH(destreg,i) = 32767;
9912         else if (r < -32768)
9913           GPR_SH(destreg,i) = -32768;
9914         else
9915           GPR_SH(destreg,i) = r;
9916       }
9917   }
9918 }
9919
9920 // end-sanitize-r5900
9921 // start-sanitize-r5900
9922
9923 011100,5.RS,5.RT,5.RD,10001001000:MMI0:32::PSUBSW
9924 *r5900:
9925 {
9926   unsigned32 instruction = instruction_0;
9927   int destreg = ((instruction >> 11) & 0x0000001F);
9928   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9929   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9930   signed_word rt_reg = GPR[RT];
9931   signed_word rt_reg1 = GPR1[RT];
9932   {
9933     int i;
9934     for (i=0; i < WORDS_IN_MMI_REGS; i++)
9935       {
9936         signed64 s = RS_SW(i);
9937         signed64 t = RT_SW(i);
9938         signed64 r = s - t;
9939         if (r > (int)0x7FFFFFFF)
9940           GPR_SW(destreg,i) = (int)0x7FFFFFFF;
9941         else if (r < (int)0x80000000)
9942           GPR_SW(destreg,i) = (int)0x80000000;
9943         else
9944           GPR_SW(destreg,i) = r;
9945       }
9946   }
9947 }
9948
9949 // end-sanitize-r5900
9950 // start-sanitize-r5900
9951
9952 011100,5.RS,5.RT,5.RD,11001101000:MMI1:32::PSUBUB
9953 *r5900:
9954 {
9955   unsigned32 instruction = instruction_0;
9956   int destreg = ((instruction >> 11) & 0x0000001F);
9957   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9958   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9959   signed_word rt_reg = GPR[RT];
9960   signed_word rt_reg1 = GPR1[RT];
9961   {
9962     int i;
9963     for (i=0; i < BYTES_IN_MMI_REGS; i++)
9964       {
9965         unsigned int s = RS_UB(i);
9966         unsigned int t = RT_UB(i);
9967         unsigned int r = s - t;
9968         if (r > 0xFF)
9969           GPR_UB(destreg,i) = 0;
9970         else
9971           GPR_UB(destreg,i) = r;
9972       }
9973   }
9974 }
9975
9976 // end-sanitize-r5900
9977 // start-sanitize-r5900
9978
9979 011100,5.RS,5.RT,5.RD,10101101000:MMI1:32::PSUBUH
9980 *r5900:
9981 {
9982   unsigned32 instruction = instruction_0;
9983   int destreg = ((instruction >> 11) & 0x0000001F);
9984   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
9985   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
9986   signed_word rt_reg = GPR[RT];
9987   signed_word rt_reg1 = GPR1[RT];
9988   {
9989     int i;
9990     for (i=0; i < HALFWORDS_IN_MMI_REGS; i++)
9991       {
9992         unsigned int s = RS_UH(i);
9993         unsigned int t = RT_UH(i);
9994         unsigned int r = s - t;
9995         if (r > 0xFFFF)
9996           GPR_UH(destreg,i) = 0;
9997         else
9998           GPR_UH(destreg,i) = r;
9999       }
10000   }
10001 }
10002
10003 // end-sanitize-r5900
10004 // start-sanitize-r5900
10005
10006 011100,5.RS,5.RT,5.RD,10001101000:MMI1:32::PSUBUW
10007 *r5900:
10008 {
10009   unsigned32 instruction = instruction_0;
10010   int destreg = ((instruction >> 11) & 0x0000001F);
10011   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
10012   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
10013   signed_word rt_reg = GPR[RT];
10014   signed_word rt_reg1 = GPR1[RT];
10015   {
10016     int i;
10017     for (i=0; i < WORDS_IN_MMI_REGS; i++)
10018       {
10019         unsigned64 s = RS_UW(i);
10020         unsigned64 t = RT_UW(i);
10021         unsigned64 r = s - t;
10022         if (r > 0xFFFFFFFF)
10023           GPR_UW(destreg,i) = 0;
10024         else
10025           GPR_UW(destreg,i) = r;
10026       }
10027   }
10028 }
10029
10030 // end-sanitize-r5900
10031 // start-sanitize-r5900
10032
10033 011100,5.RS,5.RT,5.RD,00001001000:MMI0:32::PSUBW
10034 *r5900:
10035 {
10036   unsigned32 instruction = instruction_0;
10037   int destreg = ((instruction >> 11) & 0x0000001F);
10038   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
10039   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
10040   signed_word rt_reg = GPR[RT];
10041   signed_word rt_reg1 = GPR1[RT];
10042   {
10043     int i;
10044     for (i=0; i < WORDS_IN_MMI_REGS; i++)
10045       {
10046         signed64 s = RS_SW(i);
10047         signed64 t = RT_SW(i);
10048         signed64 r = s - t;
10049         GPR_SW(destreg,i) = r;
10050       }
10051   }
10052 }
10053
10054 // end-sanitize-r5900
10055 // start-sanitize-r5900
10056
10057 011100,5.RS,5.RT,5.RD,10011001001:MMI2:32::PXOR
10058 *r5900:
10059 {
10060   unsigned32 instruction = instruction_0;
10061   int destreg = ((instruction >> 11) & 0x0000001F);
10062   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
10063   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
10064   signed_word rt_reg = GPR[RT];
10065   signed_word rt_reg1 = GPR1[RT];
10066   {
10067     int i;
10068     for(i=0;i<WORDS_IN_MMI_REGS;i++)
10069       GPR_UW(destreg,i) = (RS_UW(i) ^ RT_UW(i));
10070   }
10071 }
10072
10073 // end-sanitize-r5900
10074 // start-sanitize-r5900
10075
10076 011100,5.RS,5.RT,5.RD,11011101000:MMI1:32::QFSRV
10077 *r5900:
10078 {
10079   unsigned32 instruction = instruction_0;
10080   int destreg = ((instruction >> 11) & 0x0000001F);
10081   signed_word rs_reg = GPR[((instruction >> 21) & 0x0000001F)];
10082   signed_word rs_reg1 = GPR1[((instruction >> 21) & 0x0000001F)];
10083   signed_word rt_reg = GPR[RT];
10084   signed_word rt_reg1 = GPR1[RT];
10085   {
10086     int bytes = (SA / 8) % 16;
10087     if (SA % 8)
10088       SignalException(ReservedInstruction,instruction);
10089     else
10090       {
10091         int i;
10092         for(i=0;i<(16-bytes);i++)
10093           GPR_SB(destreg,i) = RT_SB(bytes+i);
10094         for(;i<16;i++)
10095           GPR_SB(destreg,i) = RS_SB(i-(16-bytes));
10096       }
10097   }
10098 }
10099
10100 // end-sanitize-r5900
10101 // start-sanitize-r5900
10102
10103 011111,5.RS,5.RT,16.OFFSET:NORMAL:128::SQ
10104 *r5900:
10105 {
10106   unsigned32 instruction = instruction_0;
10107   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
10108   signed_word rsigned_word = GPR[((instruction >> 16) & 0x0000001F)];
10109   signed_word rsigned_word1 = GPR1[((instruction >> 16) & 0x0000001F)];
10110   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
10111   signed_word rt_reg = GPR[RT];
10112   signed_word rt_reg1 = GPR1[RT];
10113   {
10114     address_word vaddr = ((unsigned64)op1 + offset);
10115     address_word paddr;
10116     int uncached;
10117     if ((vaddr & 15) != 0)
10118       SignalExceptionAddressStore();
10119     else
10120       {
10121         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
10122           {
10123             unsigned64 memval = 0;
10124             unsigned64 memval1 = 0;
10125             memval  = rsigned_word;
10126             memval1 = rsigned_word1;
10127             {
10128               StoreMemory(uncached,AccessLength_QUADWORD,memval,memval1,paddr,vaddr,isREAL);
10129             }
10130           }
10131       }
10132   }
10133 }
10134
10135 // end-sanitize-r5900
10136 \f
10137 // start-sanitize-cygnus-never
10138
10139 // // FIXME FIXME FIXME What is this instruction?
10140 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
10141 // *mipsI:
10142 // *mipsII:
10143 // *mipsIII:
10144 // *mipsIV:
10145 // // start-sanitize-r5900
10146 // *r5900:
10147 // // end-sanitize-r5900
10148 // *r3900:
10149 // // start-sanitize-tx19
10150 // *tx19:
10151 // // end-sanitize-tx19
10152 // {
10153 //   unsigned32 instruction = instruction_0;
10154 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
10155 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
10156 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
10157 //   {
10158 //     if (CoProcPresent(3))
10159 //       SignalException(CoProcessorUnusable);
10160 //     else
10161 //       SignalException(ReservedInstruction,instruction);
10162 //   }
10163 // }
10164
10165 // end-sanitize-cygnus-never
10166 // start-sanitize-cygnus-never
10167
10168 // // FIXME FIXME FIXME What is this?
10169 // 11100,******,00001:RR:16::SDBBP
10170 // *mips16:
10171 // {
10172 //   unsigned32 instruction = instruction_0;
10173 //   if (have_extendval)
10174 //     SignalException (ReservedInstruction, instruction);
10175 //   {
10176 //     SignalException(DebugBreakPoint,instruction);
10177 //   }
10178 // }
10179
10180 // end-sanitize-cygnus-never
10181 // start-sanitize-cygnus-never
10182
10183 // // FIXME FIXME FIXME What is this?
10184 // 000000,********************,001110:SPECIAL:32::SDBBP
10185 // *r3900:
10186 // {
10187 //   unsigned32 instruction = instruction_0;
10188 //   {
10189 //     SignalException(DebugBreakPoint,instruction);
10190 //   }
10191 // }
10192
10193 // end-sanitize-cygnus-never
10194 // start-sanitize-cygnus-never
10195
10196 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
10197 // // isn't yet reconized by this simulator.
10198 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
10199 // *vr4100:
10200 // {
10201 //   unsigned32 instruction = instruction_0;
10202 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
10203 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
10204 //   {
10205 //     CHECKHILO("Multiply-Add");
10206 //     {
10207 //       unsigned64 temp = (op1 * op2);
10208 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
10209 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
10210 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
10211 //     }
10212 //   }
10213 // }
10214
10215 // end-sanitize-cygnus-never
10216 // start-sanitize-cygnus-never
10217
10218 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
10219 // // isn't yet reconized by this simulator.
10220 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
10221 // *vr4100:
10222 // {
10223 //   unsigned32 instruction = instruction_0;
10224 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
10225 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
10226 //   {
10227 //     CHECKHILO("Multiply-Add");
10228 //     {
10229 //       unsigned64 temp = (op1 * op2);
10230 //       LO = LO + temp;
10231 //     }
10232 //   }
10233 // }
10234
10235 // start-sanitize-cygnus-never