sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 // start-sanitize-vr4320
  47 :model:::vr4320:mips4320:
  48 // end-sanitize-vr4320
  49 // start-sanitize-vr5400
  50 :model:::vr5400:mips5400:
  51 :model:::mdmx:mdmx:
  52 // end-sanitize-vr5400
  53 :model:::vr5000:mips5000:
  54
  55
  56
  57 // Pseudo instructions known by IGEN
  58 :internal::::illegal:
  59 {
  60   SignalException (ReservedInstruction, 0);
  61 }
  62
  63
  64 // Pseudo instructions known by interp.c
  65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  67 "rsvd <OP>"
  68 {
  69   SignalException (ReservedInstruction, instruction_0);
  70 }
  71
  72
  73
  74 // Helper:
  75 //
  76 // Simulate a 32 bit delayslot instruction
  77 //
  78
  79 :function:::address_word:delayslot32:address_word target
  80 {
  81   instruction_word delay_insn;
  82   sim_events_slip (SD, 1);
  83   DSPC = CIA;
  84   CIA = CIA + 4; /* NOTE not mips16 */
  85   STATE |= simDELAYSLOT;
  86   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  87   idecode_issue (CPU_, delay_insn, (CIA));
  88   STATE &= ~simDELAYSLOT;
  89   return target;
  90 }
  91
  92 :function:::address_word:nullify_next_insn32:
  93 {
  94   sim_events_slip (SD, 1);
  95   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  96   return CIA + 8;
  97 }
  98
  99
 100
 101 //
 102 // Mips Architecture:
 103 //
 104 //        CPU Instruction Set (mipsI - mipsIV)
 105 //
 106
 107
 108
 109 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 110 "add r<RD>, r<RS>, r<RT>"
 111 *mipsI,mipsII,mipsIII,mipsIV:
 112 *vr5000:
 113 // start-sanitize-vr4320
 114 *vr4320:
 115 // end-sanitize-vr4320
 116 // start-sanitize-vr5400
 117 *vr5400:
 118 // end-sanitize-vr5400
 119 // start-sanitize-r5900
 120 *r5900:
 121 // end-sanitize-r5900
 122 *r3900:
 123 // start-sanitize-tx19
 124 *tx19:
 125 // end-sanitize-tx19
 126 {
 127   ALU32_BEGIN (GPR[RS]);
 128   ALU32_ADD (GPR[RT]);
 129   ALU32_END (GPR[RD]);
 130 }
 131
 132
 133
 134 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 135 "addi r<RT>, r<RS>, IMMEDIATE"
 136 *mipsI,mipsII,mipsIII,mipsIV:
 137 *vr5000:
 138 // start-sanitize-vr4320
 139 *vr4320:
 140 // end-sanitize-vr4320
 141 // start-sanitize-vr5400
 142 *vr5400:
 143 // end-sanitize-vr5400
 144 // start-sanitize-r5900
 145 *r5900:
 146 // end-sanitize-r5900
 147 *r3900:
 148 // start-sanitize-tx19
 149 *tx19:
 150 // end-sanitize-tx19
 151 {
 152   ALU32_BEGIN (GPR[RS]);
 153   ALU32_ADD (EXTEND16 (IMMEDIATE));
 154   ALU32_END (GPR[RT]);
 155 }
 156
 157
 158
 159 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 160 {
 161   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 162   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 163   TRACE_ALU_RESULT (GPR[rt]);
 164 }
 165
 166 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 167 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 168 *mipsI,mipsII,mipsIII,mipsIV:
 169 *vr5000:
 170 // start-sanitize-vr4320
 171 *vr4320:
 172 // end-sanitize-vr4320
 173 // start-sanitize-vr5400
 174 *vr5400:
 175 // end-sanitize-vr5400
 176 // start-sanitize-r5900
 177 *r5900:
 178 // end-sanitize-r5900
 179 *r3900:
 180 // start-sanitize-tx19
 181 *tx19:
 182 // end-sanitize-tx19
 183 {
 184   do_addiu (SD_, RS, RT, IMMEDIATE);
 185 }
 186
 187
 188
 189 :function:::void:do_addu:int rs, int rt, int rd
 190 {
 191   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 192   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 193   TRACE_ALU_RESULT (GPR[rd]);
 194 }
 195
 196 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 197 "addu r<RD>, r<RS>, r<RT>"
 198 *mipsI,mipsII,mipsIII,mipsIV:
 199 *vr5000:
 200 // start-sanitize-vr4320
 201 *vr4320:
 202 // end-sanitize-vr4320
 203 // start-sanitize-vr5400
 204 *vr5400:
 205 // end-sanitize-vr5400
 206 // start-sanitize-r5900
 207 *r5900:
 208 // end-sanitize-r5900
 209 *r3900:
 210 // start-sanitize-tx19
 211 *tx19:
 212 // end-sanitize-tx19
 213 {
 214   do_addu (SD_, RS, RT, RD);
 215 }
 216
 217
 218
 219 :function:::void:do_and:int rs, int rt, int rd
 220 {
 221   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 222   GPR[rd] = GPR[rs] & GPR[rt];
 223   TRACE_ALU_RESULT (GPR[rd]);
 224 }
 225
 226 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 227 "and r<RD>, r<RS>, r<RT>"
 228 *mipsI,mipsII,mipsIII,mipsIV:
 229 *vr5000:
 230 // start-sanitize-vr4320
 231 *vr4320:
 232 // end-sanitize-vr4320
 233 // start-sanitize-vr5400
 234 *vr5400:
 235 // end-sanitize-vr5400
 236 // start-sanitize-r5900
 237 *r5900:
 238 // end-sanitize-r5900
 239 *r3900:
 240 // start-sanitize-tx19
 241 *tx19:
 242 // end-sanitize-tx19
 243 {
 244   do_and (SD_, RS, RT, RD);
 245 }
 246
 247
 248
 249 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 250 "and r<RT>, r<RS>, <IMMEDIATE>"
 251 *mipsI,mipsII,mipsIII,mipsIV:
 252 *vr5000:
 253 // start-sanitize-vr4320
 254 *vr4320:
 255 // end-sanitize-vr4320
 256 // start-sanitize-vr5400
 257 *vr5400:
 258 // end-sanitize-vr5400
 259 // start-sanitize-r5900
 260 *r5900:
 261 // end-sanitize-r5900
 262 *r3900:
 263 // start-sanitize-tx19
 264 *tx19:
 265 // end-sanitize-tx19
 266 {
 267   GPR[RT] = GPR[RS] & IMMEDIATE;
 268 }
 269
 270
 271
 272 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 273 "beq r<RS>, r<RT>, <OFFSET>"
 274 *mipsI,mipsII,mipsIII,mipsIV:
 275 *vr5000:
 276 // start-sanitize-vr4320
 277 *vr4320:
 278 // end-sanitize-vr4320
 279 // start-sanitize-vr5400
 280 *vr5400:
 281 // end-sanitize-vr5400
 282 // start-sanitize-r5900
 283 *r5900:
 284 // end-sanitize-r5900
 285 *r3900:
 286 // start-sanitize-tx19
 287 *tx19:
 288 // end-sanitize-tx19
 289 {
 290   address_word offset = EXTEND16 (OFFSET) << 2;
 291   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 292     DELAY_SLOT (NIA + offset);
 293 }
 294
 295
 296
 297 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 298 "beql r<RS>, r<RT>, <OFFSET>"
 299 *mipsII:
 300 *mipsIII:
 301 *mipsIV:
 302 *vr5000:
 303 // start-sanitize-vr4320
 304 *vr4320:
 305 // end-sanitize-vr4320
 306 // start-sanitize-vr5400
 307 *vr5400:
 308 // end-sanitize-vr5400
 309 // start-sanitize-r5900
 310 *r5900:
 311 // end-sanitize-r5900
 312 *r3900:
 313 // start-sanitize-tx19
 314 *tx19:
 315 // end-sanitize-tx19
 316 {
 317   address_word offset = EXTEND16 (OFFSET) << 2;
 318   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 319     DELAY_SLOT (NIA + offset);
 320   else
 321     NULLIFY_NEXT_INSTRUCTION ();
 322 }
 323
 324
 325
 326 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 327 "bgez r<RS>, <OFFSET>"
 328 *mipsI,mipsII,mipsIII,mipsIV:
 329 *vr5000:
 330 // start-sanitize-vr4320
 331 *vr4320:
 332 // end-sanitize-vr4320
 333 // start-sanitize-vr5400
 334 *vr5400:
 335 // end-sanitize-vr5400
 336 // start-sanitize-r5900
 337 *r5900:
 338 // end-sanitize-r5900
 339 *r3900:
 340 // start-sanitize-tx19
 341 *tx19:
 342 // end-sanitize-tx19
 343 {
 344   address_word offset = EXTEND16 (OFFSET) << 2;
 345   if ((signed_word) GPR[RS] >= 0)
 346     DELAY_SLOT (NIA + offset);
 347 }
 348
 349
 350
 351 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 352 "bgezal r<RS>, <OFFSET>"
 353 *mipsI,mipsII,mipsIII,mipsIV:
 354 *vr5000:
 355 // start-sanitize-vr4320
 356 *vr4320:
 357 // end-sanitize-vr4320
 358 // start-sanitize-vr5400
 359 *vr5400:
 360 // end-sanitize-vr5400
 361 // start-sanitize-r5900
 362 *r5900:
 363 // end-sanitize-r5900
 364 *r3900:
 365 // start-sanitize-tx19
 366 *tx19:
 367 // end-sanitize-tx19
 368 {
 369   address_word offset = EXTEND16 (OFFSET) << 2;
 370   RA = (CIA + 8);
 371   if ((signed_word) GPR[RS] >= 0)
 372     DELAY_SLOT (NIA + offset);
 373 }
 374
 375
 376
 377 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 378 "bgezall r<RS>, <OFFSET>"
 379 *mipsII:
 380 *mipsIII:
 381 *mipsIV:
 382 *vr5000:
 383 // start-sanitize-vr4320
 384 *vr4320:
 385 // end-sanitize-vr4320
 386 // start-sanitize-vr5400
 387 *vr5400:
 388 // end-sanitize-vr5400
 389 // start-sanitize-r5900
 390 *r5900:
 391 // end-sanitize-r5900
 392 *r3900:
 393 // start-sanitize-tx19
 394 *tx19:
 395 // end-sanitize-tx19
 396 {
 397   address_word offset = EXTEND16 (OFFSET) << 2;
 398   RA = (CIA + 8);
 399   /* NOTE: The branch occurs AFTER the next instruction has been
 400      executed */
 401   if ((signed_word) GPR[RS] >= 0)
 402     DELAY_SLOT (NIA + offset);
 403   else
 404     NULLIFY_NEXT_INSTRUCTION ();
 405 }
 406
 407
 408
 409 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 410 "bgezl r<RS>, <OFFSET>"
 411 *mipsII:
 412 *mipsIII:
 413 *mipsIV:
 414 *vr5000:
 415 // start-sanitize-vr4320
 416 *vr4320:
 417 // end-sanitize-vr4320
 418 // start-sanitize-vr5400
 419 *vr5400:
 420 // end-sanitize-vr5400
 421 // start-sanitize-r5900
 422 *r5900:
 423 // end-sanitize-r5900
 424 *r3900:
 425 // start-sanitize-tx19
 426 *tx19:
 427 // end-sanitize-tx19
 428 {
 429   address_word offset = EXTEND16 (OFFSET) << 2;
 430   if ((signed_word) GPR[RS] >= 0)
 431     DELAY_SLOT (NIA + offset);
 432   else
 433     NULLIFY_NEXT_INSTRUCTION ();
 434 }
 435
 436
 437
 438 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 439 "bgtz r<RS>, <OFFSET>"
 440 *mipsI,mipsII,mipsIII,mipsIV:
 441 *vr5000:
 442 // start-sanitize-vr4320
 443 *vr4320:
 444 // end-sanitize-vr4320
 445 // start-sanitize-vr5400
 446 *vr5400:
 447 // end-sanitize-vr5400
 448 // start-sanitize-r5900
 449 *r5900:
 450 // end-sanitize-r5900
 451 *r3900:
 452 // start-sanitize-tx19
 453 *tx19:
 454 // end-sanitize-tx19
 455 {
 456   address_word offset = EXTEND16 (OFFSET) << 2;
 457   if ((signed_word) GPR[RS] > 0)
 458     DELAY_SLOT (NIA + offset);
 459 }
 460
 461
 462
 463 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 464 "bgtzl r<RS>, <OFFSET>"
 465 *mipsII:
 466 *mipsIII:
 467 *mipsIV:
 468 *vr5000:
 469 // start-sanitize-vr4320
 470 *vr4320:
 471 // end-sanitize-vr4320
 472 // start-sanitize-vr5400
 473 *vr5400:
 474 // end-sanitize-vr5400
 475 // start-sanitize-r5900
 476 *r5900:
 477 // end-sanitize-r5900
 478 *r3900:
 479 // start-sanitize-tx19
 480 *tx19:
 481 // end-sanitize-tx19
 482 {
 483   address_word offset = EXTEND16 (OFFSET) << 2;
 484   /* NOTE: The branch occurs AFTER the next instruction has been
 485      executed */
 486   if ((signed_word) GPR[RS] > 0)
 487     DELAY_SLOT (NIA + offset);
 488   else
 489     NULLIFY_NEXT_INSTRUCTION ();
 490 }
 491
 492
 493
 494 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 495 "blez r<RS>, <OFFSET>"
 496 *mipsI,mipsII,mipsIII,mipsIV:
 497 *vr5000:
 498 // start-sanitize-vr4320
 499 *vr4320:
 500 // end-sanitize-vr4320
 501 // start-sanitize-vr5400
 502 *vr5400:
 503 // end-sanitize-vr5400
 504 // start-sanitize-r5900
 505 *r5900:
 506 // end-sanitize-r5900
 507 *r3900:
 508 // start-sanitize-tx19
 509 *tx19:
 510 // end-sanitize-tx19
 511 {
 512   address_word offset = EXTEND16 (OFFSET) << 2;
 513   /* NOTE: The branch occurs AFTER the next instruction has been
 514      executed */
 515   if ((signed_word) GPR[RS] <= 0)
 516     DELAY_SLOT (NIA + offset);
 517 }
 518
 519
 520
 521 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 522 "bgezl r<RS>, <OFFSET>"
 523 *mipsII:
 524 *mipsIII:
 525 *mipsIV:
 526 *vr5000:
 527 // start-sanitize-vr4320
 528 *vr4320:
 529 // end-sanitize-vr4320
 530 // start-sanitize-vr5400
 531 *vr5400:
 532 // end-sanitize-vr5400
 533 // start-sanitize-r5900
 534 *r5900:
 535 // end-sanitize-r5900
 536 *r3900:
 537 // start-sanitize-tx19
 538 *tx19:
 539 // end-sanitize-tx19
 540 {
 541   address_word offset = EXTEND16 (OFFSET) << 2;
 542   if ((signed_word) GPR[RS] <= 0)
 543     DELAY_SLOT (NIA + offset);
 544   else
 545     NULLIFY_NEXT_INSTRUCTION ();
 546 }
 547
 548
 549
 550 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 551 "bltz r<RS>, <OFFSET>"
 552 *mipsI,mipsII,mipsIII,mipsIV:
 553 *vr5000:
 554 // start-sanitize-vr4320
 555 *vr4320:
 556 // end-sanitize-vr4320
 557 // start-sanitize-vr5400
 558 *vr5400:
 559 // end-sanitize-vr5400
 560 // start-sanitize-r5900
 561 *r5900:
 562 // end-sanitize-r5900
 563 *r3900:
 564 // start-sanitize-tx19
 565 *tx19:
 566 // end-sanitize-tx19
 567 {
 568   address_word offset = EXTEND16 (OFFSET) << 2;
 569   if ((signed_word) GPR[RS] < 0)
 570     DELAY_SLOT (NIA + offset);
 571 }
 572
 573
 574
 575 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 576 "bltzal r<RS>, <OFFSET>"
 577 *mipsI,mipsII,mipsIII,mipsIV:
 578 *vr5000:
 579 // start-sanitize-vr4320
 580 *vr4320:
 581 // end-sanitize-vr4320
 582 // start-sanitize-vr5400
 583 *vr5400:
 584 // end-sanitize-vr5400
 585 // start-sanitize-r5900
 586 *r5900:
 587 // end-sanitize-r5900
 588 *r3900:
 589 // start-sanitize-tx19
 590 *tx19:
 591 // end-sanitize-tx19
 592 {
 593   address_word offset = EXTEND16 (OFFSET) << 2;
 594   RA = (CIA + 8);
 595   /* NOTE: The branch occurs AFTER the next instruction has been
 596      executed */
 597   if ((signed_word) GPR[RS] < 0)
 598     DELAY_SLOT (NIA + offset);
 599 }
 600
 601
 602
 603 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 604 "bltzall r<RS>, <OFFSET>"
 605 *mipsII:
 606 *mipsIII:
 607 *mipsIV:
 608 *vr5000:
 609 // start-sanitize-vr4320
 610 *vr4320:
 611 // end-sanitize-vr4320
 612 // start-sanitize-vr5400
 613 *vr5400:
 614 // end-sanitize-vr5400
 615 // start-sanitize-r5900
 616 *r5900:
 617 // end-sanitize-r5900
 618 *r3900:
 619 // start-sanitize-tx19
 620 *tx19:
 621 // end-sanitize-tx19
 622 {
 623   address_word offset = EXTEND16 (OFFSET) << 2;
 624   RA = (CIA + 8);
 625   if ((signed_word) GPR[RS] < 0)
 626     DELAY_SLOT (NIA + offset);
 627   else
 628     NULLIFY_NEXT_INSTRUCTION ();
 629 }
 630
 631
 632
 633 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 634 "bltzl r<RS>, <OFFSET>"
 635 *mipsII:
 636 *mipsIII:
 637 *mipsIV:
 638 *vr5000:
 639 // start-sanitize-vr4320
 640 *vr4320:
 641 // end-sanitize-vr4320
 642 // start-sanitize-vr5400
 643 *vr5400:
 644 // end-sanitize-vr5400
 645 // start-sanitize-r5900
 646 *r5900:
 647 // end-sanitize-r5900
 648 *r3900:
 649 // start-sanitize-tx19
 650 *tx19:
 651 // end-sanitize-tx19
 652 {
 653   address_word offset = EXTEND16 (OFFSET) << 2;
 654   /* NOTE: The branch occurs AFTER the next instruction has been
 655      executed */
 656   if ((signed_word) GPR[RS] < 0)
 657     DELAY_SLOT (NIA + offset);
 658   else
 659     NULLIFY_NEXT_INSTRUCTION ();
 660 }
 661
 662
 663
 664 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 665 "bne r<RS>, r<RT>, <OFFSET>"
 666 *mipsI,mipsII,mipsIII,mipsIV:
 667 *vr5000:
 668 // start-sanitize-vr4320
 669 *vr4320:
 670 // end-sanitize-vr4320
 671 // start-sanitize-vr5400
 672 *vr5400:
 673 // end-sanitize-vr5400
 674 // start-sanitize-r5900
 675 *r5900:
 676 // end-sanitize-r5900
 677 *r3900:
 678 // start-sanitize-tx19
 679 *tx19:
 680 // end-sanitize-tx19
 681 {
 682   address_word offset = EXTEND16 (OFFSET) << 2;
 683   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 684     DELAY_SLOT (NIA + offset);
 685 }
 686
 687
 688
 689 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 690 "bnel r<RS>, r<RT>, <OFFSET>"
 691 *mipsII:
 692 *mipsIII:
 693 *mipsIV:
 694 *vr5000:
 695 // start-sanitize-vr4320
 696 *vr4320:
 697 // end-sanitize-vr4320
 698 // start-sanitize-vr5400
 699 *vr5400:
 700 // end-sanitize-vr5400
 701 // start-sanitize-r5900
 702 *r5900:
 703 // end-sanitize-r5900
 704 *r3900:
 705 // start-sanitize-tx19
 706 *tx19:
 707 // end-sanitize-tx19
 708 {
 709   address_word offset = EXTEND16 (OFFSET) << 2;
 710   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 711     DELAY_SLOT (NIA + offset);
 712   else
 713     NULLIFY_NEXT_INSTRUCTION ();
 714 }
 715
 716
 717
 718 000000,20.CODE,001101:SPECIAL:32::BREAK
 719 "break"
 720 *mipsI,mipsII,mipsIII,mipsIV:
 721 *vr5000:
 722 // start-sanitize-vr4320
 723 *vr4320:
 724 // end-sanitize-vr4320
 725 // start-sanitize-vr5400
 726 *vr5400:
 727 // end-sanitize-vr5400
 728 // start-sanitize-r5900
 729 *r5900:
 730 // end-sanitize-r5900
 731 *r3900:
 732 // start-sanitize-tx19
 733 *tx19:
 734 // end-sanitize-tx19
 735 {
 736   SignalException(BreakPoint, instruction_0);
 737 }
 738
 739
 740
 741 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 742 "cop<ZZ> <COP_FUN>"
 743 *mipsI,mipsII,mipsIII,mipsIV:
 744 // start-sanitize-r5900
 745 *r5900:
 746 // end-sanitize-r5900
 747 *r3900:
 748 // start-sanitize-tx19
 749 *tx19:
 750 // end-sanitize-tx19
 751 {
 752   DecodeCoproc (instruction_0);
 753 }
 754
 755
 756
 757 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 758 "dadd r<RD>, r<RS>, r<RT>"
 759 *mipsIII:
 760 *mipsIV:
 761 *vr5000:
 762 // start-sanitize-vr4320
 763 *vr4320:
 764 // end-sanitize-vr4320
 765 // start-sanitize-vr5400
 766 *vr5400:
 767 // end-sanitize-vr5400
 768 // start-sanitize-r5900
 769 *r5900:
 770 // end-sanitize-r5900
 771 // start-sanitize-tx19
 772 *tx19:
 773 // end-sanitize-tx19
 774 {
 775   /* this check's for overflow */
 776   ALU64_BEGIN (GPR[RS]);
 777   ALU64_ADD (GPR[RT]);
 778   ALU64_END (GPR[RD]);
 779 }
 780
 781
 782
 783 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 784 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 785 *mipsIII:
 786 *mipsIV:
 787 *vr5000:
 788 // start-sanitize-vr4320
 789 *vr4320:
 790 // end-sanitize-vr4320
 791 // start-sanitize-vr5400
 792 *vr5400:
 793 // end-sanitize-vr5400
 794 // start-sanitize-r5900
 795 *r5900:
 796 // end-sanitize-r5900
 797 // start-sanitize-tx19
 798 *tx19:
 799 // end-sanitize-tx19
 800 {
 801   ALU64_BEGIN (GPR[RS]);
 802   ALU64_ADD (EXTEND16 (IMMEDIATE));
 803   ALU64_END (GPR[RT]);
 804 }
 805
 806
 807
 808 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
 809 {
 810   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 811   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
 812   TRACE_ALU_RESULT (GPR[rt]);
 813 }
 814
 815 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 816 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 817 *mipsIII:
 818 *mipsIV:
 819 *vr5000:
 820 // start-sanitize-vr4320
 821 *vr4320:
 822 // end-sanitize-vr4320
 823 // start-sanitize-vr5400
 824 *vr5400:
 825 // end-sanitize-vr5400
 826 // start-sanitize-r5900
 827 *r5900:
 828 // end-sanitize-r5900
 829 // start-sanitize-tx19
 830 *tx19:
 831 // end-sanitize-tx19
 832 {
 833   do_daddiu (SD_, RS, RT, IMMEDIATE);
 834 }
 835
 836
 837
 838 :function:::void:do_daddu:int rs, int rt, int rd
 839 {
 840   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 841   GPR[rd] = GPR[rs] + GPR[rt];
 842   TRACE_ALU_RESULT (GPR[rd]);
 843 }
 844
 845 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 846 "daddu r<RD>, r<RS>, r<RT>"
 847 *mipsIII:
 848 *mipsIV:
 849 *vr5000:
 850 // start-sanitize-vr4320
 851 *vr4320:
 852 // end-sanitize-vr4320
 853 // start-sanitize-vr5400
 854 *vr5400:
 855 // end-sanitize-vr5400
 856 // start-sanitize-r5900
 857 *r5900:
 858 // end-sanitize-r5900
 859 // start-sanitize-tx19
 860 *tx19:
 861 // end-sanitize-tx19
 862 {
 863   do_daddu (SD_, RS, RT, RD);
 864 }
 865
 866
 867
 868 :function:64::void:do_ddiv:int rs, int rt
 869 {
 870   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 871   CHECKHILO ("Division");
 872   {
 873     signed64 n = GPR[rs];
 874     signed64 d = GPR[rt];
 875     if (d == 0)
 876       {
 877         LO = SIGNED64 (0x8000000000000000);
 878         HI = 0;
 879       }
 880     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 881       {
 882         LO = SIGNED64 (0x8000000000000000);
 883         HI = 0;
 884       }
 885     else
 886       {
 887         LO = (n / d);
 888         HI = (n % d);
 889       }
 890   }
 891   TRACE_ALU_RESULT2 (HI, LO);
 892 }
 893
 894 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 895 "ddiv r<RS>, r<RT>"
 896 *mipsIII:
 897 *mipsIV:
 898 *vr5000:
 899 // start-sanitize-vr4320
 900 *vr4320:
 901 // end-sanitize-vr4320
 902 // start-sanitize-vr5400
 903 *vr5400:
 904 // end-sanitize-vr5400
 905 // start-sanitize-r5900
 906 *r5900:
 907 // end-sanitize-r5900
 908 // start-sanitize-tx19
 909 *tx19:
 910 // end-sanitize-tx19
 911 {
 912   do_ddiv (SD_, RS, RT);
 913 }
 914
 915
 916
 917 :function:64::void:do_ddivu:int rs, int rt
 918 {
 919   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 920   CHECKHILO ("Division");
 921   {
 922     unsigned64 n = GPR[rs];
 923     unsigned64 d = GPR[rt];
 924     if (d == 0)
 925       {
 926         LO = SIGNED64 (0x8000000000000000);
 927         HI = 0;
 928       }
 929     else
 930       {
 931         LO = (n / d);
 932         HI = (n % d);
 933       }
 934   }
 935   TRACE_ALU_RESULT2 (HI, LO);
 936 }
 937
 938 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 939 "ddivu r<RS>, r<RT>"
 940 *mipsIII:
 941 *mipsIV:
 942 *vr5000:
 943 // start-sanitize-vr4320
 944 *vr4320:
 945 // end-sanitize-vr4320
 946 // start-sanitize-vr5400
 947 *vr5400:
 948 // end-sanitize-vr5400
 949 // start-sanitize-tx19
 950 *tx19:
 951 // end-sanitize-tx19
 952 {
 953   do_ddivu (SD_, RS, RT);
 954 }
 955
 956
 957
 958 :function:::void:do_div:int rs, int rt
 959 {
 960   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 961   CHECKHILO("Division");
 962   {
 963     signed32 n = GPR[rs];
 964     signed32 d = GPR[rt];
 965     if (d == 0)
 966       {
 967         LO = EXTEND32 (0x80000000);
 968         HI = EXTEND32 (0);
 969       }
 970     else if (n == SIGNED32 (0x80000000) && d == -1)
 971       {
 972         LO = EXTEND32 (0x80000000);
 973         HI = EXTEND32 (0);
 974       }
 975     else
 976       {
 977         LO = EXTEND32 (n / d);
 978         HI = EXTEND32 (n % d);
 979       }
 980   }
 981   TRACE_ALU_RESULT2 (HI, LO);
 982 }
 983
 984 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 985 "div r<RS>, r<RT>"
 986 *mipsI,mipsII,mipsIII,mipsIV:
 987 *vr5000:
 988 // start-sanitize-vr4320
 989 *vr4320:
 990 // end-sanitize-vr4320
 991 // start-sanitize-vr5400
 992 *vr5400:
 993 // end-sanitize-vr5400
 994 // start-sanitize-r5900
 995 *r5900:
 996 // end-sanitize-r5900
 997 *r3900:
 998 // start-sanitize-tx19
 999 *tx19:
1000 // end-sanitize-tx19
1001 {
1002   do_div (SD_, RS, RT);
1003 }
1004
1005
1006
1007 :function:::void:do_divu:int rs, int rt
1008 {
1009   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1010   CHECKHILO ("Division");
1011   {
1012     unsigned32 n = GPR[rs];
1013     unsigned32 d = GPR[rt];
1014     if (d == 0)
1015       {
1016         LO = EXTEND32 (0x80000000);
1017         HI = EXTEND32 (0);
1018       }
1019    else
1020      {
1021        LO = EXTEND32 (n / d);
1022        HI = EXTEND32 (n % d);
1023      }
1024   }
1025   TRACE_ALU_RESULT2 (HI, LO);
1026 }
1027
1028 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1029 "divu r<RS>, r<RT>"
1030 *mipsI,mipsII,mipsIII,mipsIV:
1031 *vr5000:
1032 // start-sanitize-vr4320
1033 *vr4320:
1034 // end-sanitize-vr4320
1035 // start-sanitize-vr5400
1036 *vr5400:
1037 // end-sanitize-vr5400
1038 // start-sanitize-r5900
1039 *r5900:
1040 // end-sanitize-r5900
1041 *r3900:
1042 // start-sanitize-tx19
1043 *tx19:
1044 // end-sanitize-tx19
1045 {
1046   do_divu (SD_, RS, RT);
1047 }
1048
1049
1050
1051 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1052 {
1053   unsigned64 lo;
1054   unsigned64 hi;
1055   unsigned64 m00;
1056   unsigned64 m01;
1057   unsigned64 m10;
1058   unsigned64 m11;
1059   unsigned64 mid;
1060   int sign;
1061   unsigned64 op1 = GPR[rs];
1062   unsigned64 op2 = GPR[rt];
1063   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1064   CHECKHILO ("Multiplication");
1065   /* make signed multiply unsigned */
1066   sign = 0;
1067   if (signed_p)
1068     {
1069       if (op1 < 0)
1070         {
1071           op1 = - op1;
1072           ++sign;
1073         }
1074       if (op2 < 0)
1075         {
1076           op2 = - op2;
1077           ++sign;
1078         }
1079     }
1080   /* multuply out the 4 sub products */
1081   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1082   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1083   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1084   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1085   /* add the products */
1086   mid = ((unsigned64) VH4_8 (m00)
1087          + (unsigned64) VL4_8 (m10)
1088          + (unsigned64) VL4_8 (m01));
1089   lo = U8_4 (mid, m00);
1090   hi = (m11
1091         + (unsigned64) VH4_8 (mid)
1092         + (unsigned64) VH4_8 (m01)
1093         + (unsigned64) VH4_8 (m10));
1094   /* fix the sign */
1095   if (sign & 1)
1096     {
1097       lo = -lo;
1098       if (lo == 0)
1099         hi = -hi;
1100       else
1101         hi = -hi - 1;
1102     }
1103   /* save the result HI/LO (and a gpr) */
1104   LO = lo;
1105   HI = hi;
1106   if (rd != 0)
1107     GPR[rd] = lo;
1108   TRACE_ALU_RESULT2 (HI, LO);
1109 }
1110
1111 :function:::void:do_dmult:int rs, int rt, int rd
1112 {
1113   do_dmultx (SD_, rs, rt, rd, 1);
1114 }
1115
1116 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1117 "dmult r<RS>, r<RT>"
1118 *mipsIII,mipsIV:
1119 // start-sanitize-tx19
1120 *tx19:
1121 // end-sanitize-tx19
1122 // start-sanitize-vr4320
1123 *vr4320:
1124 // end-sanitize-vr4320
1125 {
1126   do_dmult (SD_, RS, RT, 0);
1127 }
1128
1129 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1130 "dmult r<RS>, r<RT>":RD == 0
1131 "dmult r<RD>, r<RS>, r<RT>"
1132 *vr5000:
1133 // start-sanitize-vr5400
1134 *vr5400:
1135 // end-sanitize-vr5400
1136 {
1137   do_dmult (SD_, RS, RT, RD);
1138 }
1139
1140
1141
1142 :function:::void:do_dmultu:int rs, int rt, int rd
1143 {
1144   do_dmultx (SD_, rs, rt, rd, 0);
1145 }
1146
1147 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1148 "dmultu r<RS>, r<RT>"
1149 *mipsIII,mipsIV:
1150 // start-sanitize-tx19
1151 *tx19:
1152 // end-sanitize-tx19
1153 // start-sanitize-vr4320
1154 *vr4320:
1155 // end-sanitize-vr4320
1156 {
1157   do_dmultu (SD_, RS, RT, 0);
1158 }
1159
1160 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1161 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1162 "dmultu r<RS>, r<RT>"
1163 *vr5000:
1164 // start-sanitize-vr5400
1165 *vr5400:
1166 // end-sanitize-vr5400
1167 {
1168   do_dmultu (SD_, RS, RT, RD);
1169 }
1170
1171
1172
1173 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1174 "dsll r<RD>, r<RT>, <SHIFT>"
1175 *mipsIII:
1176 *mipsIV:
1177 *vr5000:
1178 // start-sanitize-vr4320
1179 *vr4320:
1180 // end-sanitize-vr4320
1181 // start-sanitize-vr5400
1182 *vr5400:
1183 // end-sanitize-vr5400
1184 // start-sanitize-r5900
1185 *r5900:
1186 // end-sanitize-r5900
1187 // start-sanitize-tx19
1188 *tx19:
1189 // end-sanitize-tx19
1190 {
1191   int s = SHIFT;
1192   GPR[RD] = GPR[RT] << s;
1193 }
1194
1195
1196 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1197 "dsll32 r<RD>, r<RT>, <SHIFT>"
1198 *mipsIII:
1199 *mipsIV:
1200 *vr5000:
1201 // start-sanitize-vr4320
1202 *vr4320:
1203 // end-sanitize-vr4320
1204 // start-sanitize-vr5400
1205 *vr5400:
1206 // end-sanitize-vr5400
1207 // start-sanitize-r5900
1208 *r5900:
1209 // end-sanitize-r5900
1210 // start-sanitize-tx19
1211 *tx19:
1212 // end-sanitize-tx19
1213 {
1214   int s = 32 + SHIFT;
1215   GPR[RD] = GPR[RT] << s;
1216 }
1217
1218
1219
1220 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1221 "dsllv r<RD>, r<RT>, r<RS>"
1222 *mipsIII:
1223 *mipsIV:
1224 *vr5000:
1225 // start-sanitize-vr4320
1226 *vr4320:
1227 // end-sanitize-vr4320
1228 // start-sanitize-vr5400
1229 *vr5400:
1230 // end-sanitize-vr5400
1231 // start-sanitize-r5900
1232 *r5900:
1233 // end-sanitize-r5900
1234 // start-sanitize-tx19
1235 *tx19:
1236 // end-sanitize-tx19
1237 {
1238   int s = MASKED64 (GPR[RS], 5, 0);
1239   GPR[RD] = GPR[RT] << s;
1240 }
1241
1242
1243
1244 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1245 "dsra r<RD>, r<RT>, <SHIFT>"
1246 *mipsIII:
1247 *mipsIV:
1248 *vr5000:
1249 // start-sanitize-vr4320
1250 *vr4320:
1251 // end-sanitize-vr4320
1252 // start-sanitize-vr5400
1253 *vr5400:
1254 // end-sanitize-vr5400
1255 // start-sanitize-r5900
1256 *r5900:
1257 // end-sanitize-r5900
1258 // start-sanitize-tx19
1259 *tx19:
1260 // end-sanitize-tx19
1261 {
1262   int s = SHIFT;
1263   GPR[RD] = ((signed64) GPR[RT]) >> s;
1264 }
1265
1266
1267 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1268 "dsra32 r<RT>, r<RD>, <SHIFT>"
1269 *mipsIII:
1270 *mipsIV:
1271 *vr5000:
1272 // start-sanitize-vr4320
1273 *vr4320:
1274 // end-sanitize-vr4320
1275 // start-sanitize-vr5400
1276 *vr5400:
1277 // end-sanitize-vr5400
1278 // start-sanitize-r5900
1279 *r5900:
1280 // end-sanitize-r5900
1281 // start-sanitize-tx19
1282 *tx19:
1283 // end-sanitize-tx19
1284 {
1285   int s = 32 + SHIFT;
1286   GPR[RD] = ((signed64) GPR[RT]) >> s;
1287 }
1288
1289
1290 :function:::void:do_dsrav:int rs, int rt, int rd
1291 {
1292   int s = MASKED64 (GPR[rs], 5, 0);
1293   TRACE_ALU_INPUT2 (GPR[rt], s);
1294   GPR[rd] = ((signed64) GPR[rt]) >> s;
1295   TRACE_ALU_RESULT (GPR[rd]);
1296 }
1297
1298 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1299 "dsra32 r<RT>, r<RD>, r<RS>"
1300 *mipsIII:
1301 *mipsIV:
1302 *vr5000:
1303 // start-sanitize-vr4320
1304 *vr4320:
1305 // end-sanitize-vr4320
1306 // start-sanitize-vr5400
1307 *vr5400:
1308 // end-sanitize-vr5400
1309 // start-sanitize-r5900
1310 *r5900:
1311 // end-sanitize-r5900
1312 // start-sanitize-tx19
1313 *tx19:
1314 // end-sanitize-tx19
1315 {
1316   do_dsrav (SD_, RS, RT, RD);
1317 }
1318
1319
1320 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1321 "dsrl r<RD>, r<RT>, <SHIFT>"
1322 *mipsIII:
1323 *mipsIV:
1324 *vr5000:
1325 // start-sanitize-vr4320
1326 *vr4320:
1327 // end-sanitize-vr4320
1328 // start-sanitize-vr5400
1329 *vr5400:
1330 // end-sanitize-vr5400
1331 // start-sanitize-r5900
1332 *r5900:
1333 // end-sanitize-r5900
1334 // start-sanitize-tx19
1335 *tx19:
1336 // end-sanitize-tx19
1337 {
1338   int s = SHIFT;
1339   GPR[RD] = (unsigned64) GPR[RT] >> s;
1340 }
1341
1342
1343 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1344 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1345 *mipsIII:
1346 *mipsIV:
1347 *vr5000:
1348 // start-sanitize-vr4320
1349 *vr4320:
1350 // end-sanitize-vr4320
1351 // start-sanitize-vr5400
1352 *vr5400:
1353 // end-sanitize-vr5400
1354 // start-sanitize-r5900
1355 *r5900:
1356 // end-sanitize-r5900
1357 // start-sanitize-tx19
1358 *tx19:
1359 // end-sanitize-tx19
1360 {
1361   int s = 32 + SHIFT;
1362   GPR[RD] = (unsigned64) GPR[RT] >> s;
1363 }
1364
1365
1366 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1367 "dsrl32 r<RD>, r<RT>, r<RS>"
1368 *mipsIII:
1369 *mipsIV:
1370 *vr5000:
1371 // start-sanitize-vr4320
1372 *vr4320:
1373 // end-sanitize-vr4320
1374 // start-sanitize-vr5400
1375 *vr5400:
1376 // end-sanitize-vr5400
1377 // start-sanitize-r5900
1378 *r5900:
1379 // end-sanitize-r5900
1380 // start-sanitize-tx19
1381 *tx19:
1382 // end-sanitize-tx19
1383 {
1384   int s = MASKED64 (GPR[RS], 5, 0);
1385   GPR[RD] = (unsigned64) GPR[RT] >> s;
1386 }
1387
1388
1389 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1390 "dsub r<RD>, r<RS>, r<RT>"
1391 *mipsIII:
1392 *mipsIV:
1393 *vr5000:
1394 // start-sanitize-vr4320
1395 *vr4320:
1396 // end-sanitize-vr4320
1397 // start-sanitize-vr5400
1398 *vr5400:
1399 // end-sanitize-vr5400
1400 // start-sanitize-r5900
1401 *r5900:
1402 // end-sanitize-r5900
1403 // start-sanitize-tx19
1404 *tx19:
1405 // end-sanitize-tx19
1406 {
1407   ALU64_BEGIN (GPR[RS]);
1408   ALU64_SUB (GPR[RT]);
1409   ALU64_END (GPR[RD]);
1410 }
1411
1412
1413 :function:::void:do_dsubu:int rs, int rt, int rd
1414 {
1415   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1416   GPR[rd] = GPR[rs] - GPR[rt];
1417   TRACE_ALU_RESULT (GPR[rd]);
1418 }
1419
1420 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1421 "dsubu r<RD>, r<RS>, r<RT>"
1422 *mipsIII:
1423 *mipsIV:
1424 *vr5000:
1425 // start-sanitize-vr4320
1426 *vr4320:
1427 // end-sanitize-vr4320
1428 // start-sanitize-vr5400
1429 *vr5400:
1430 // end-sanitize-vr5400
1431 // start-sanitize-r5900
1432 *r5900:
1433 // end-sanitize-r5900
1434 // start-sanitize-tx19
1435 *tx19:
1436 // end-sanitize-tx19
1437 {
1438   do_dsubu (SD_, RS, RT, RD);
1439 }
1440
1441
1442 000010,26.INSTR_INDEX:NORMAL:32::J
1443 "j <INSTR_INDEX>"
1444 *mipsI,mipsII,mipsIII,mipsIV:
1445 *vr5000:
1446 // start-sanitize-vr4320
1447 *vr4320:
1448 // end-sanitize-vr4320
1449 // start-sanitize-vr5400
1450 *vr5400:
1451 // end-sanitize-vr5400
1452 // start-sanitize-r5900
1453 *r5900:
1454 // end-sanitize-r5900
1455 *r3900:
1456 // start-sanitize-tx19
1457 *tx19:
1458 // end-sanitize-tx19
1459 {
1460   /* NOTE: The region used is that of the delay slot NIA and NOT the
1461      current instruction */
1462   address_word region = (NIA & MASK (63, 28));
1463   DELAY_SLOT (region | (INSTR_INDEX << 2));
1464 }
1465
1466
1467 000011,26.INSTR_INDEX:NORMAL:32::JAL
1468 "jal <INSTR_INDEX>"
1469 *mipsI,mipsII,mipsIII,mipsIV:
1470 *vr5000:
1471 // start-sanitize-vr4320
1472 *vr4320:
1473 // end-sanitize-vr4320
1474 // start-sanitize-vr5400
1475 *vr5400:
1476 // end-sanitize-vr5400
1477 // start-sanitize-r5900
1478 *r5900:
1479 // end-sanitize-r5900
1480 *r3900:
1481 // start-sanitize-tx19
1482 *tx19:
1483 // end-sanitize-tx19
1484 {
1485   /* NOTE: The region used is that of the delay slot and NOT the
1486      current instruction */
1487   address_word region = (NIA & MASK (63, 28));
1488   GPR[31] = CIA + 8;
1489   DELAY_SLOT (region | (INSTR_INDEX << 2));
1490 }
1491
1492
1493 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1494 "jalr r<RS>":RD == 31
1495 "jalr r<RD>, r<RS>"
1496 *mipsI,mipsII,mipsIII,mipsIV:
1497 *vr5000:
1498 // start-sanitize-vr4320
1499 *vr4320:
1500 // end-sanitize-vr4320
1501 // start-sanitize-vr5400
1502 *vr5400:
1503 // end-sanitize-vr5400
1504 // start-sanitize-r5900
1505 *r5900:
1506 // end-sanitize-r5900
1507 *r3900:
1508 // start-sanitize-tx19
1509 *tx19:
1510 // end-sanitize-tx19
1511 {
1512   address_word temp = GPR[RS];
1513   GPR[RD] = CIA + 8;
1514   DELAY_SLOT (temp);
1515 }
1516
1517
1518 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1519 "jr r<RS>"
1520 *mipsI,mipsII,mipsIII,mipsIV:
1521 *vr5000:
1522 // start-sanitize-vr4320
1523 *vr4320:
1524 // end-sanitize-vr4320
1525 // start-sanitize-vr5400
1526 *vr5400:
1527 // end-sanitize-vr5400
1528 // start-sanitize-r5900
1529 *r5900:
1530 // end-sanitize-r5900
1531 *r3900:
1532 // start-sanitize-tx19
1533 *tx19:
1534 // end-sanitize-tx19
1535 {
1536   DELAY_SLOT (GPR[RS]);
1537 }
1538
1539
1540 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1541 {
1542   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1543   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1544   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1545   unsigned int byte;
1546   address_word paddr;
1547   int uncached;
1548   unsigned64 memval;
1549   address_word vaddr;
1550
1551   vaddr = base + offset;
1552   if ((vaddr & access) != 0)
1553     SignalExceptionAddressLoad ();
1554   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1555   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1556   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1557   byte = ((vaddr & mask) ^ bigendiancpu);
1558   return (memval >> (8 * byte));
1559 }
1560
1561
1562 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1563 "lb r<RT>, <OFFSET>(r<BASE>)"
1564 *mipsI,mipsII,mipsIII,mipsIV:
1565 *vr5000:
1566 // start-sanitize-vr4320
1567 *vr4320:
1568 // end-sanitize-vr4320
1569 // start-sanitize-vr5400
1570 *vr5400:
1571 // end-sanitize-vr5400
1572 // start-sanitize-r5900
1573 *r5900:
1574 // end-sanitize-r5900
1575 *r3900:
1576 // start-sanitize-tx19
1577 *tx19:
1578 // end-sanitize-tx19
1579 {
1580   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1581 }
1582
1583
1584 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1585 "lbu r<RT>, <OFFSET>(r<BASE>)"
1586 *mipsI,mipsII,mipsIII,mipsIV:
1587 *vr5000:
1588 // start-sanitize-vr4320
1589 *vr4320:
1590 // end-sanitize-vr4320
1591 // start-sanitize-vr5400
1592 *vr5400:
1593 // end-sanitize-vr5400
1594 // start-sanitize-r5900
1595 *r5900:
1596 // end-sanitize-r5900
1597 *r3900:
1598 // start-sanitize-tx19
1599 *tx19:
1600 // end-sanitize-tx19
1601 {
1602   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1603 }
1604
1605
1606 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1607 "ld r<RT>, <OFFSET>(r<BASE>)"
1608 *mipsIII:
1609 *mipsIV:
1610 *vr5000:
1611 // start-sanitize-vr4320
1612 *vr4320:
1613 // end-sanitize-vr4320
1614 // start-sanitize-vr5400
1615 *vr5400:
1616 // end-sanitize-vr5400
1617 // start-sanitize-r5900
1618 *r5900:
1619 // end-sanitize-r5900
1620 // start-sanitize-tx19
1621 *tx19:
1622 // end-sanitize-tx19
1623 {
1624   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1625 }
1626
1627
1628 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1629 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1630 *mipsII:
1631 *mipsIII:
1632 *mipsIV:
1633 *vr5000:
1634 // start-sanitize-vr4320
1635 *vr4320:
1636 // end-sanitize-vr4320
1637 // start-sanitize-vr5400
1638 *vr5400:
1639 // end-sanitize-vr5400
1640 *r3900:
1641 // start-sanitize-tx19
1642 *tx19:
1643 // end-sanitize-tx19
1644 {
1645   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1646 }
1647
1648
1649
1650
1651 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1652 "ldl r<RT>, <OFFSET>(r<BASE>)"
1653 *mipsIII:
1654 *mipsIV:
1655 *vr5000:
1656 // start-sanitize-vr4320
1657 *vr4320:
1658 // end-sanitize-vr4320
1659 // start-sanitize-vr5400
1660 *vr5400:
1661 // end-sanitize-vr5400
1662 // start-sanitize-r5900
1663 *r5900:
1664 // end-sanitize-r5900
1665 // start-sanitize-tx19
1666 *tx19:
1667 // end-sanitize-tx19
1668 {
1669   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1670 }
1671
1672
1673 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1674 "ldr r<RT>, <OFFSET>(r<BASE>)"
1675 *mipsIII:
1676 *mipsIV:
1677 *vr5000:
1678 // start-sanitize-vr4320
1679 *vr4320:
1680 // end-sanitize-vr4320
1681 // start-sanitize-vr5400
1682 *vr5400:
1683 // end-sanitize-vr5400
1684 // start-sanitize-r5900
1685 *r5900:
1686 // end-sanitize-r5900
1687 // start-sanitize-tx19
1688 *tx19:
1689 // end-sanitize-tx19
1690 {
1691   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1692 }
1693
1694
1695 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1696 "lh r<RT>, <OFFSET>(r<BASE>)"
1697 *mipsI,mipsII,mipsIII,mipsIV:
1698 *vr5000:
1699 // start-sanitize-vr4320
1700 *vr4320:
1701 // end-sanitize-vr4320
1702 // start-sanitize-vr5400
1703 *vr5400:
1704 // end-sanitize-vr5400
1705 // start-sanitize-r5900
1706 *r5900:
1707 // end-sanitize-r5900
1708 *r3900:
1709 // start-sanitize-tx19
1710 *tx19:
1711 // end-sanitize-tx19
1712 {
1713   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1714 }
1715
1716
1717 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1718 "lhu r<RT>, <OFFSET>(r<BASE>)"
1719 *mipsI,mipsII,mipsIII,mipsIV:
1720 *vr5000:
1721 // start-sanitize-vr4320
1722 *vr4320:
1723 // end-sanitize-vr4320
1724 // start-sanitize-vr5400
1725 *vr5400:
1726 // end-sanitize-vr5400
1727 // start-sanitize-r5900
1728 *r5900:
1729 // end-sanitize-r5900
1730 *r3900:
1731 // start-sanitize-tx19
1732 *tx19:
1733 // end-sanitize-tx19
1734 {
1735   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1736 }
1737
1738
1739 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1740 "ll r<RT>, <OFFSET>(r<BASE>)"
1741 *mipsII:
1742 *mipsIII:
1743 *mipsIV:
1744 *vr5000:
1745 // start-sanitize-vr4320
1746 *vr4320:
1747 // end-sanitize-vr4320
1748 // start-sanitize-vr5400
1749 *vr5400:
1750 // end-sanitize-vr5400
1751 // start-sanitize-r5900
1752 *r5900:
1753 // end-sanitize-r5900
1754 // start-sanitize-tx19
1755 *tx19:
1756 // end-sanitize-tx19
1757 {
1758   unsigned32 instruction = instruction_0;
1759   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1760   int destreg = ((instruction >> 16) & 0x0000001F);
1761   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1762   {
1763     address_word vaddr = ((unsigned64)op1 + offset);
1764     address_word paddr;
1765     int uncached;
1766     if ((vaddr & 3) != 0)
1767       SignalExceptionAddressLoad();
1768     else
1769       {
1770         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1771           {
1772             unsigned64 memval = 0;
1773             unsigned64 memval1 = 0;
1774             unsigned64 mask = 0x7;
1775             unsigned int shift = 2;
1776             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1777             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1778             unsigned int byte;
1779             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1780             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1781             byte = ((vaddr & mask) ^ (bigend << shift));
1782             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1783             LLBIT = 1;
1784           }
1785       }
1786   }
1787 }
1788
1789
1790 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1791 "lld r<RT>, <OFFSET>(r<BASE>)"
1792 *mipsIII:
1793 *mipsIV:
1794 *vr5000:
1795 // start-sanitize-vr4320
1796 *vr4320:
1797 // end-sanitize-vr4320
1798 // start-sanitize-vr5400
1799 *vr5400:
1800 // end-sanitize-vr5400
1801 // start-sanitize-r5900
1802 *r5900:
1803 // end-sanitize-r5900
1804 // start-sanitize-tx19
1805 *tx19:
1806 // end-sanitize-tx19
1807 {
1808   unsigned32 instruction = instruction_0;
1809   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1810   int destreg = ((instruction >> 16) & 0x0000001F);
1811   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1812   {
1813     address_word vaddr = ((unsigned64)op1 + offset);
1814     address_word paddr;
1815     int uncached;
1816     if ((vaddr & 7) != 0)
1817       SignalExceptionAddressLoad();
1818     else
1819       {
1820         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1821           {
1822             unsigned64 memval = 0;
1823             unsigned64 memval1 = 0;
1824             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1825             GPR[destreg] = memval;
1826             LLBIT = 1;
1827           }
1828       }
1829   }
1830 }
1831
1832
1833 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1834 "lui r<RT>, <IMMEDIATE>"
1835 *mipsI,mipsII,mipsIII,mipsIV:
1836 *vr5000:
1837 // start-sanitize-vr4320
1838 *vr4320:
1839 // end-sanitize-vr4320
1840 // start-sanitize-vr5400
1841 *vr5400:
1842 // end-sanitize-vr5400
1843 // start-sanitize-r5900
1844 *r5900:
1845 // end-sanitize-r5900
1846 *r3900:
1847 // start-sanitize-tx19
1848 *tx19:
1849 // end-sanitize-tx19
1850 {
1851   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1852 }
1853
1854
1855 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1856 "lw r<RT>, <OFFSET>(r<BASE>)"
1857 *mipsI,mipsII,mipsIII,mipsIV:
1858 *vr5000:
1859 // start-sanitize-vr4320
1860 *vr4320:
1861 // end-sanitize-vr4320
1862 // start-sanitize-vr5400
1863 *vr5400:
1864 // end-sanitize-vr5400
1865 // start-sanitize-r5900
1866 *r5900:
1867 // end-sanitize-r5900
1868 *r3900:
1869 // start-sanitize-tx19
1870 *tx19:
1871 // end-sanitize-tx19
1872 {
1873   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1874 }
1875
1876
1877 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1878 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1879 *mipsI,mipsII,mipsIII,mipsIV:
1880 *vr5000:
1881 // start-sanitize-vr4320
1882 *vr4320:
1883 // end-sanitize-vr4320
1884 // start-sanitize-vr5400
1885 *vr5400:
1886 // end-sanitize-vr5400
1887 // start-sanitize-r5900
1888 *r5900:
1889 // end-sanitize-r5900
1890 *r3900:
1891 // start-sanitize-tx19
1892 *tx19:
1893 // end-sanitize-tx19
1894 {
1895   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1896 }
1897
1898
1899 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1900 {
1901   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1902   address_word reverseendian = (ReverseEndian ? -1 : 0);
1903   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1904   unsigned int byte;
1905   address_word paddr;
1906   int uncached;
1907   unsigned64 memval;
1908   address_word vaddr;
1909
1910   vaddr = base + offset;
1911   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1912   paddr = (paddr ^ (reverseendian & mask));
1913   if (BigEndianMem == 0)
1914     paddr = paddr & ~access;
1915   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1916   LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
1917   /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
1918      (long) vaddr, byte, (long) paddr, (long) memval); */
1919   if ((byte & ~access) == 0)
1920     {
1921       int bits = 8 * (access - byte);
1922       unsigned_word screen = LSMASK (bits - 1, 0);
1923       rt &= screen;
1924       rt |= ((memval << bits) & ~screen);
1925     }
1926   else
1927     {
1928       unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
1929       rt &= screen;
1930       rt |= ((memval >> (8 * (mask - byte))) & ~screen);
1931     }
1932   return rt;
1933 }
1934
1935
1936 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1937 "lwl r<RT>, <OFFSET>(r<BASE>)"
1938 *mipsI,mipsII,mipsIII,mipsIV:
1939 *vr5000:
1940 // start-sanitize-vr4320
1941 *vr4320:
1942 // end-sanitize-vr4320
1943 // start-sanitize-vr5400
1944 *vr5400:
1945 // end-sanitize-vr5400
1946 // start-sanitize-r5900
1947 *r5900:
1948 // end-sanitize-r5900
1949 *r3900:
1950 // start-sanitize-tx19
1951 *tx19:
1952 // end-sanitize-tx19
1953 {
1954   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
1955 }
1956
1957
1958 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1959 {
1960   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1961   address_word reverseendian = (ReverseEndian ? -1 : 0);
1962   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1963   unsigned int byte;
1964   address_word paddr;
1965   int uncached;
1966   unsigned64 memval;
1967   address_word vaddr;
1968
1969   vaddr = base + offset;
1970   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1971   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1972   paddr = (paddr ^ (reverseendian & mask));
1973   if (BigEndianMem != 0)
1974     paddr = paddr & ~access;
1975   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1976   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1977   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1978   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1979      (long) paddr, byte, (long) paddr, (long) memval); */
1980   {
1981     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1982     rt &= ~screen;
1983     rt |= (memval >> (8 * byte)) & screen;
1984   }
1985   return rt;
1986 }
1987
1988
1989 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1990 "lwr r<RT>, <OFFSET>(r<BASE>)"
1991 *mipsI,mipsII,mipsIII,mipsIV:
1992 *vr5000:
1993 // start-sanitize-vr4320
1994 *vr4320:
1995 // end-sanitize-vr4320
1996 // start-sanitize-vr5400
1997 *vr5400:
1998 // end-sanitize-vr5400
1999 // start-sanitize-r5900
2000 *r5900:
2001 // end-sanitize-r5900
2002 *r3900:
2003 // start-sanitize-tx19
2004 *tx19:
2005 // end-sanitize-tx19
2006 {
2007   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2008 }
2009
2010
2011 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2012 "lwu r<RT>, <OFFSET>(r<BASE>)"
2013 *mipsIII:
2014 *mipsIV:
2015 *vr5000:
2016 // start-sanitize-vr4320
2017 *vr4320:
2018 // end-sanitize-vr4320
2019 // start-sanitize-vr5400
2020 *vr5400:
2021 // end-sanitize-vr5400
2022 // start-sanitize-r5900
2023 *r5900:
2024 // end-sanitize-r5900
2025 // start-sanitize-tx19
2026 *tx19:
2027 // end-sanitize-tx19
2028 {
2029   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2030 }
2031
2032
2033 :function:::void:do_mfhi:int rd
2034 {
2035   TRACE_ALU_INPUT1 (HI);
2036   GPR[rd] = HI;
2037   TRACE_ALU_RESULT (GPR[rd]);
2038 #if 0
2039   HIACCESS = 3;
2040 #endif
2041 }
2042
2043 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2044 "mfhi r<RD>"
2045 *mipsI,mipsII,mipsIII,mipsIV:
2046 *vr5000:
2047 // start-sanitize-vr4320
2048 *vr4320:
2049 // end-sanitize-vr4320
2050 // start-sanitize-vr5400
2051 *vr5400:
2052 // end-sanitize-vr5400
2053 // start-sanitize-r5900
2054 *r5900:
2055 // end-sanitize-r5900
2056 *r3900:
2057 // start-sanitize-tx19
2058 *tx19:
2059 // end-sanitize-tx19
2060 {
2061   do_mfhi (SD_, RD);
2062 }
2063
2064
2065
2066 :function:::void:do_mflo:int rd
2067 {
2068   TRACE_ALU_INPUT1 (LO);
2069   GPR[rd] = LO;
2070   TRACE_ALU_RESULT (GPR[rd]);
2071 #if 0
2072   LOACCESS = 3; /* 3rd instruction will be safe */
2073 #endif
2074 }
2075
2076 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2077 "mflo r<RD>"
2078 *mipsI,mipsII,mipsIII,mipsIV:
2079 *vr5000:
2080 // start-sanitize-vr4320
2081 *vr4320:
2082 // end-sanitize-vr4320
2083 // start-sanitize-vr5400
2084 *vr5400:
2085 // end-sanitize-vr5400
2086 // start-sanitize-r5900
2087 *r5900:
2088 // end-sanitize-r5900
2089 *r3900:
2090 // start-sanitize-tx19
2091 *tx19:
2092 // end-sanitize-tx19
2093 {
2094   do_mflo (SD_, RD);
2095 }
2096
2097
2098
2099 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2100 "movn r<RD>, r<RS>, r<RT>"
2101 *mipsIV:
2102 *vr5000:
2103 // start-sanitize-vr4320
2104 *vr4320:
2105 // end-sanitize-vr4320
2106 // start-sanitize-vr5400
2107 *vr5400:
2108 // end-sanitize-vr5400
2109 // start-sanitize-r5900
2110 *r5900:
2111 // end-sanitize-r5900
2112 {
2113   if (GPR[RT] != 0)
2114     GPR[RD] = GPR[RS];
2115 }
2116
2117
2118
2119 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2120 "movz r<RD>, r<RS>, r<RT>"
2121 *mipsIV:
2122 *vr5000:
2123 // start-sanitize-vr4320
2124 *vr4320:
2125 // end-sanitize-vr4320
2126 // start-sanitize-vr5400
2127 *vr5400:
2128 // end-sanitize-vr5400
2129 // start-sanitize-r5900
2130 *r5900:
2131 // end-sanitize-r5900
2132 {
2133   if (GPR[RT] == 0)
2134     GPR[RD] = GPR[RS];
2135 }
2136
2137
2138
2139 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2140 "mthi r<RS>"
2141 *mipsI,mipsII,mipsIII,mipsIV:
2142 *vr5000:
2143 // start-sanitize-vr4320
2144 *vr4320:
2145 // end-sanitize-vr4320
2146 // start-sanitize-vr5400
2147 *vr5400:
2148 // end-sanitize-vr5400
2149 // start-sanitize-r5900
2150 *r5900:
2151 // end-sanitize-r5900
2152 *r3900:
2153 // start-sanitize-tx19
2154 *tx19:
2155 // end-sanitize-tx19
2156 {
2157 #if 0
2158   if (HIACCESS != 0)
2159     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2160 #endif
2161   HI = GPR[RS];
2162 #if 0
2163   HIACCESS = 3; /* 3rd instruction will be safe */
2164 #endif
2165 }
2166
2167
2168
2169 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2170 "mtlo r<RS>"
2171 *mipsI,mipsII,mipsIII,mipsIV:
2172 *vr5000:
2173 // start-sanitize-vr4320
2174 *vr4320:
2175 // end-sanitize-vr4320
2176 // start-sanitize-vr5400
2177 *vr5400:
2178 // end-sanitize-vr5400
2179 // start-sanitize-r5900
2180 *r5900:
2181 // end-sanitize-r5900
2182 *r3900:
2183 // start-sanitize-tx19
2184 *tx19:
2185 // end-sanitize-tx19
2186 {
2187 #if 0
2188   if (LOACCESS != 0)
2189     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2190 #endif
2191   LO = GPR[RS];
2192 #if 0
2193   LOACCESS = 3; /* 3rd instruction will be safe */
2194 #endif
2195 }
2196
2197
2198
2199 :function:::void:do_mult:int rs, int rt, int rd
2200 {
2201   signed64 prod;
2202   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2203   CHECKHILO ("Multiplication");
2204   prod = (((signed64)(signed32) GPR[rs])
2205           * ((signed64)(signed32) GPR[rt]));
2206   LO = EXTEND32 (VL4_8 (prod));
2207   HI = EXTEND32 (VH4_8 (prod));
2208   if (rd != 0)
2209     GPR[rd] = LO;
2210   TRACE_ALU_RESULT2 (HI, LO);
2211 }
2212
2213 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2214 "mult r<RS>, r<RT>"
2215 *mipsI,mipsII,mipsIII,mipsIV:
2216 // start-sanitize-vr4320
2217 *vr4320:
2218 // end-sanitize-vr4320
2219 {
2220   do_mult (SD_, RS, RT, 0);
2221 }
2222
2223
2224 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2225 "mult r<RD>, r<RS>, r<RT>"
2226 *vr5000:
2227 // start-sanitize-vr5400
2228 *vr5400:
2229 // end-sanitize-vr5400
2230 // start-sanitize-r5900
2231 *r5900:
2232 // end-sanitize-r5900
2233 *r3900:
2234 // start-sanitize-tx19
2235 *tx19:
2236 // end-sanitize-tx19
2237 {
2238   do_mult (SD_, RS, RT, RD);
2239 }
2240
2241
2242 :function:::void:do_multu:int rs, int rt, int rd
2243 {
2244   unsigned64 prod;
2245   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2246   CHECKHILO ("Multiplication");
2247   prod = (((unsigned64)(unsigned32) GPR[rs])
2248           * ((unsigned64)(unsigned32) GPR[rt]));
2249   LO = EXTEND32 (VL4_8 (prod));
2250   HI = EXTEND32 (VH4_8 (prod));
2251   if (rd != 0)
2252     GPR[rd] = LO;
2253   TRACE_ALU_RESULT2 (HI, LO);
2254 }
2255
2256 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2257 "multu r<RS>, r<RT>"
2258 *mipsI,mipsII,mipsIII,mipsIV:
2259 // start-sanitize-vr4320
2260 *vr4320:
2261 // end-sanitize-vr4320
2262 {
2263   do_multu (SD_, RS, RT, 0);
2264 }
2265
2266 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2267 "multu r<RD>, r<RS>, r<RT>"
2268 *vr5000:
2269 // start-sanitize-vr5400
2270 *vr5400:
2271 // end-sanitize-vr5400
2272 // start-sanitize-r5900
2273 *r5900:
2274 // end-sanitize-r5900
2275 *r3900:
2276 // start-sanitize-tx19
2277 *tx19:
2278 // end-sanitize-tx19
2279 {
2280   do_multu (SD_, RS, RT, 0);
2281 }
2282
2283
2284 :function:::void:do_nor:int rs, int rt, int rd
2285 {
2286   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2287   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2288   TRACE_ALU_RESULT (GPR[rd]);
2289 }
2290
2291 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2292 "nor r<RD>, r<RS>, r<RT>"
2293 *mipsI,mipsII,mipsIII,mipsIV:
2294 *vr5000:
2295 // start-sanitize-vr4320
2296 *vr4320:
2297 // end-sanitize-vr4320
2298 // start-sanitize-vr5400
2299 *vr5400:
2300 // end-sanitize-vr5400
2301 // start-sanitize-r5900
2302 *r5900:
2303 // end-sanitize-r5900
2304 *r3900:
2305 // start-sanitize-tx19
2306 *tx19:
2307 // end-sanitize-tx19
2308 {
2309   do_nor (SD_, RS, RT, RD);
2310 }
2311
2312
2313 :function:::void:do_or:int rs, int rt, int rd
2314 {
2315   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2316   GPR[rd] = (GPR[rs] | GPR[rt]);
2317   TRACE_ALU_RESULT (GPR[rd]);
2318 }
2319
2320 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2321 "or r<RD>, r<RS>, r<RT>"
2322 *mipsI,mipsII,mipsIII,mipsIV:
2323 *vr5000:
2324 // start-sanitize-vr4320
2325 *vr4320:
2326 // end-sanitize-vr4320
2327 // start-sanitize-vr5400
2328 *vr5400:
2329 // end-sanitize-vr5400
2330 // start-sanitize-r5900
2331 *r5900:
2332 // end-sanitize-r5900
2333 *r3900:
2334 // start-sanitize-tx19
2335 *tx19:
2336 // end-sanitize-tx19
2337 {
2338   do_or (SD_, RS, RT, RD);
2339 }
2340
2341
2342
2343 :function:::void:do_ori:int rs, int rt, unsigned immediate
2344 {
2345   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2346   GPR[rt] = (GPR[rs] | immediate);
2347   TRACE_ALU_RESULT (GPR[rt]);
2348 }
2349
2350 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2351 "ori r<RT>, r<RS>, <IMMEDIATE>"
2352 *mipsI,mipsII,mipsIII,mipsIV:
2353 *vr5000:
2354 // start-sanitize-vr4320
2355 *vr4320:
2356 // end-sanitize-vr4320
2357 // start-sanitize-vr5400
2358 *vr5400:
2359 // end-sanitize-vr5400
2360 // start-sanitize-r5900
2361 *r5900:
2362 // end-sanitize-r5900
2363 *r3900:
2364 // start-sanitize-tx19
2365 *tx19:
2366 // end-sanitize-tx19
2367 {
2368   do_ori (SD_, RS, RT, IMMEDIATE);
2369 }
2370
2371
2372 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2373 *mipsIV:
2374 *vr5000:
2375 // start-sanitize-vr4320
2376 *vr4320:
2377 // end-sanitize-vr4320
2378 // start-sanitize-vr5400
2379 *vr5400:
2380 // end-sanitize-vr5400
2381 // start-sanitize-r5900
2382 *r5900:
2383 // end-sanitize-r5900
2384 {
2385   unsigned32 instruction = instruction_0;
2386   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2387   int hint = ((instruction >> 16) & 0x0000001F);
2388   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2389   {
2390     address_word vaddr = ((unsigned64)op1 + offset);
2391     address_word paddr;
2392     int uncached;
2393     {
2394       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2395         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2396     }
2397   }
2398 }
2399
2400 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2401 {
2402   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2403   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2404   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2405   unsigned int byte;
2406   address_word paddr;
2407   int uncached;
2408   unsigned64 memval;
2409   address_word vaddr;
2410
2411   vaddr = base + offset;
2412   if ((vaddr & access) != 0)
2413     SignalExceptionAddressStore ();
2414   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2415   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2416   byte = ((vaddr & mask) ^ bigendiancpu);
2417   memval = (word << (8 * byte));
2418   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2419 }
2420
2421
2422 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2423 "sb r<RT>, <OFFSET>(r<BASE>)"
2424 *mipsI,mipsII,mipsIII,mipsIV:
2425 *vr5000:
2426 // start-sanitize-vr4320
2427 *vr4320:
2428 // end-sanitize-vr4320
2429 // start-sanitize-vr5400
2430 *vr5400:
2431 // end-sanitize-vr5400
2432 // start-sanitize-r5900
2433 *r5900:
2434 // end-sanitize-r5900
2435 *r3900:
2436 // start-sanitize-tx19
2437 *tx19:
2438 // end-sanitize-tx19
2439 {
2440   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2441 }
2442
2443
2444 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2445 "sc r<RT>, <OFFSET>(r<BASE>)"
2446 *mipsII:
2447 *mipsIII:
2448 *mipsIV:
2449 *vr5000:
2450 // start-sanitize-vr4320
2451 *vr4320:
2452 // end-sanitize-vr4320
2453 // start-sanitize-vr5400
2454 *vr5400:
2455 // end-sanitize-vr5400
2456 // start-sanitize-r5900
2457 *r5900:
2458 // end-sanitize-r5900
2459 // start-sanitize-tx19
2460 *tx19:
2461 // end-sanitize-tx19
2462 {
2463   unsigned32 instruction = instruction_0;
2464   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2465   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2466   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2467   {
2468     address_word vaddr = ((unsigned64)op1 + offset);
2469     address_word paddr;
2470     int uncached;
2471     if ((vaddr & 3) != 0)
2472       SignalExceptionAddressStore();
2473     else
2474       {
2475         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2476           {
2477             unsigned64 memval = 0;
2478             unsigned64 memval1 = 0;
2479             unsigned64 mask = 0x7;
2480             unsigned int byte;
2481             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2482             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2483             memval = ((unsigned64) op2 << (8 * byte));
2484             if (LLBIT)
2485               {
2486                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2487               }
2488             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2489           }
2490       }
2491   }
2492 }
2493
2494
2495 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2496 "scd r<RT>, <OFFSET>(r<BASE>)"
2497 *mipsIII:
2498 *mipsIV:
2499 *vr5000:
2500 // start-sanitize-vr4320
2501 *vr4320:
2502 // end-sanitize-vr4320
2503 // start-sanitize-vr5400
2504 *vr5400:
2505 // end-sanitize-vr5400
2506 // start-sanitize-r5900
2507 *r5900:
2508 // end-sanitize-r5900
2509 // start-sanitize-tx19
2510 *tx19:
2511 // end-sanitize-tx19
2512 {
2513   unsigned32 instruction = instruction_0;
2514   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2515   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2516   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2517   {
2518     address_word vaddr = ((unsigned64)op1 + offset);
2519     address_word paddr;
2520     int uncached;
2521     if ((vaddr & 7) != 0)
2522       SignalExceptionAddressStore();
2523     else
2524       {
2525         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2526           {
2527             unsigned64 memval = 0;
2528             unsigned64 memval1 = 0;
2529             memval = op2;
2530             if (LLBIT)
2531               {
2532                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2533               }
2534             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2535           }
2536       }
2537   }
2538 }
2539
2540
2541 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2542 "sd r<RT>, <OFFSET>(r<BASE>)"
2543 *mipsIII:
2544 *mipsIV:
2545 *vr5000:
2546 // start-sanitize-vr4320
2547 *vr4320:
2548 // end-sanitize-vr4320
2549 // start-sanitize-vr5400
2550 *vr5400:
2551 // end-sanitize-vr5400
2552 // start-sanitize-r5900
2553 *r5900:
2554 // end-sanitize-r5900
2555 // start-sanitize-tx19
2556 *tx19:
2557 // end-sanitize-tx19
2558 {
2559   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2560 }
2561
2562
2563 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2564 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2565 *mipsII:
2566 *mipsIII:
2567 *mipsIV:
2568 *vr5000:
2569 // start-sanitize-vr4320
2570 *vr4320:
2571 // end-sanitize-vr4320
2572 // start-sanitize-vr5400
2573 *vr5400:
2574 // end-sanitize-vr5400
2575 // start-sanitize-r5900
2576 *r5900:
2577 // end-sanitize-r5900
2578 // start-sanitize-tx19
2579 *tx19:
2580 // end-sanitize-tx19
2581 {
2582   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2583 }
2584
2585
2586 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2587 "sdl r<RT>, <OFFSET>(r<BASE>)"
2588 *mipsIII:
2589 *mipsIV:
2590 *vr5000:
2591 // start-sanitize-vr4320
2592 *vr4320:
2593 // end-sanitize-vr4320
2594 // start-sanitize-vr5400
2595 *vr5400:
2596 // end-sanitize-vr5400
2597 // start-sanitize-r5900
2598 *r5900:
2599 // end-sanitize-r5900
2600 // start-sanitize-tx19
2601 *tx19:
2602 // end-sanitize-tx19
2603 {
2604   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2605 }
2606
2607
2608 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2609 "sdr r<RT>, <OFFSET>(r<BASE>)"
2610 *mipsIII:
2611 *mipsIV:
2612 *vr5000:
2613 // start-sanitize-vr4320
2614 *vr4320:
2615 // end-sanitize-vr4320
2616 // start-sanitize-vr5400
2617 *vr5400:
2618 // end-sanitize-vr5400
2619 // start-sanitize-r5900
2620 *r5900:
2621 // end-sanitize-r5900
2622 // start-sanitize-tx19
2623 *tx19:
2624 // end-sanitize-tx19
2625 {
2626   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2627 }
2628
2629
2630 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2631 "sh r<RT>, <OFFSET>(r<BASE>)"
2632 *mipsI,mipsII,mipsIII,mipsIV:
2633 *vr5000:
2634 // start-sanitize-vr4320
2635 *vr4320:
2636 // end-sanitize-vr4320
2637 // start-sanitize-vr5400
2638 *vr5400:
2639 // end-sanitize-vr5400
2640 // start-sanitize-r5900
2641 *r5900:
2642 // end-sanitize-r5900
2643 *r3900:
2644 // start-sanitize-tx19
2645 *tx19:
2646 // end-sanitize-tx19
2647 {
2648   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2649 }
2650
2651
2652 :function:::void:do_sll:int rt, int rd, int shift
2653 {
2654   unsigned32 temp = (GPR[rt] << shift);
2655   TRACE_ALU_INPUT2 (GPR[rt], shift);
2656   GPR[rd] = EXTEND32 (temp);
2657   TRACE_ALU_RESULT (GPR[rd]);
2658 }
2659
2660 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2661 "sll r<RD>, r<RT>, <SHIFT>"
2662 *mipsI,mipsII,mipsIII,mipsIV:
2663 *vr5000:
2664 // start-sanitize-vr4320
2665 *vr4320:
2666 // end-sanitize-vr4320
2667 // start-sanitize-vr5400
2668 *vr5400:
2669 // end-sanitize-vr5400
2670 // start-sanitize-r5900
2671 *r5900:
2672 // end-sanitize-r5900
2673 *r3900:
2674 // start-sanitize-tx19
2675 *tx19:
2676 // end-sanitize-tx19
2677 {
2678   do_sll (SD_, RT, RD, SHIFT);
2679 }
2680
2681
2682 :function:::void:do_sllv:int rs, int rt, int rd
2683 {
2684   int s = MASKED (GPR[rs], 4, 0);
2685   unsigned32 temp = (GPR[rt] << s);
2686   TRACE_ALU_INPUT2 (GPR[rt], s);
2687   GPR[rd] = EXTEND32 (temp);
2688   TRACE_ALU_RESULT (GPR[rd]);
2689 }
2690
2691 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2692 "sllv r<RD>, r<RT>, r<RS>"
2693 *mipsI,mipsII,mipsIII,mipsIV:
2694 *vr5000:
2695 // start-sanitize-vr4320
2696 *vr4320:
2697 // end-sanitize-vr4320
2698 // start-sanitize-vr5400
2699 *vr5400:
2700 // end-sanitize-vr5400
2701 // start-sanitize-r5900
2702 *r5900:
2703 // end-sanitize-r5900
2704 *r3900:
2705 // start-sanitize-tx19
2706 *tx19:
2707 // end-sanitize-tx19
2708 {
2709   do_sllv (SD_, RS, RT, RD);
2710 }
2711
2712
2713 :function:::void:do_slt:int rs, int rt, int rd
2714 {
2715   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2716   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2717   TRACE_ALU_RESULT (GPR[rd]);
2718 }
2719
2720 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2721 "slt r<RD>, r<RS>, r<RT>"
2722 *mipsI,mipsII,mipsIII,mipsIV:
2723 *vr5000:
2724 // start-sanitize-vr4320
2725 *vr4320:
2726 // end-sanitize-vr4320
2727 // start-sanitize-vr5400
2728 *vr5400:
2729 // end-sanitize-vr5400
2730 // start-sanitize-r5900
2731 *r5900:
2732 // end-sanitize-r5900
2733 *r3900:
2734 // start-sanitize-tx19
2735 *tx19:
2736 // end-sanitize-tx19
2737 {
2738   do_slt (SD_, RS, RT, RD);
2739 }
2740
2741
2742 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2743 {
2744   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2745   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2746   TRACE_ALU_RESULT (GPR[rt]);
2747 }
2748
2749 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2750 "slti r<RT>, r<RS>, <IMMEDIATE>"
2751 *mipsI,mipsII,mipsIII,mipsIV:
2752 *vr5000:
2753 // start-sanitize-vr4320
2754 *vr4320:
2755 // end-sanitize-vr4320
2756 // start-sanitize-vr5400
2757 *vr5400:
2758 // end-sanitize-vr5400
2759 // start-sanitize-r5900
2760 *r5900:
2761 // end-sanitize-r5900
2762 *r3900:
2763 // start-sanitize-tx19
2764 *tx19:
2765 // end-sanitize-tx19
2766 {
2767   do_slti (SD_, RS, RT, IMMEDIATE);
2768 }
2769
2770
2771 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2772 {
2773   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2774   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2775   TRACE_ALU_RESULT (GPR[rt]);
2776 }
2777
2778 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2779 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2780 *mipsI,mipsII,mipsIII,mipsIV:
2781 *vr5000:
2782 // start-sanitize-vr4320
2783 *vr4320:
2784 // end-sanitize-vr4320
2785 // start-sanitize-vr5400
2786 *vr5400:
2787 // end-sanitize-vr5400
2788 // start-sanitize-r5900
2789 *r5900:
2790 // end-sanitize-r5900
2791 *r3900:
2792 // start-sanitize-tx19
2793 *tx19:
2794 // end-sanitize-tx19
2795 {
2796   do_sltiu (SD_, RS, RT, IMMEDIATE);
2797 }
2798
2799
2800
2801 :function:::void:do_sltu:int rs, int rt, int rd
2802 {
2803   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2804   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2805   TRACE_ALU_RESULT (GPR[rd]);
2806 }
2807
2808 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2809 "sltu r<RD>, r<RS>, r<RT>"
2810 *mipsI,mipsII,mipsIII,mipsIV:
2811 *vr5000:
2812 // start-sanitize-vr4320
2813 *vr4320:
2814 // end-sanitize-vr4320
2815 // start-sanitize-vr5400
2816 *vr5400:
2817 // end-sanitize-vr5400
2818 // start-sanitize-r5900
2819 *r5900:
2820 // end-sanitize-r5900
2821 *r3900:
2822 // start-sanitize-tx19
2823 *tx19:
2824 // end-sanitize-tx19
2825 {
2826   do_sltu (SD_, RS, RT, RD);
2827 }
2828
2829
2830 :function:::void:do_sra:int rt, int rd, int shift
2831 {
2832   signed32 temp = (signed32) GPR[rt] >> shift;
2833   TRACE_ALU_INPUT2 (GPR[rt], shift);
2834   GPR[rd] = EXTEND32 (temp);
2835   TRACE_ALU_RESULT (GPR[rd]);
2836 }
2837
2838 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2839 "sra r<RD>, r<RT>, <SHIFT>"
2840 *mipsI,mipsII,mipsIII,mipsIV:
2841 *vr5000:
2842 // start-sanitize-vr4320
2843 *vr4320:
2844 // end-sanitize-vr4320
2845 // start-sanitize-vr5400
2846 *vr5400:
2847 // end-sanitize-vr5400
2848 // start-sanitize-r5900
2849 *r5900:
2850 // end-sanitize-r5900
2851 *r3900:
2852 // start-sanitize-tx19
2853 *tx19:
2854 // end-sanitize-tx19
2855 {
2856   do_sra (SD_, RT, RD, SHIFT);
2857 }
2858
2859
2860
2861 :function:::void:do_srav:int rs, int rt, int rd
2862 {
2863   int s = MASKED (GPR[rs], 4, 0);
2864   signed32 temp = (signed32) GPR[rt] >> s;
2865   TRACE_ALU_INPUT2 (GPR[rt], s);
2866   GPR[rd] = EXTEND32 (temp);
2867   TRACE_ALU_RESULT (GPR[rd]);
2868 }
2869
2870 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2871 "srav r<RD>, r<RT>, r<RS>"
2872 *mipsI,mipsII,mipsIII,mipsIV:
2873 *vr5000:
2874 // start-sanitize-vr4320
2875 *vr4320:
2876 // end-sanitize-vr4320
2877 // start-sanitize-vr5400
2878 *vr5400:
2879 // end-sanitize-vr5400
2880 // start-sanitize-r5900
2881 *r5900:
2882 // end-sanitize-r5900
2883 *r3900:
2884 // start-sanitize-tx19
2885 *tx19:
2886 // end-sanitize-tx19
2887 {
2888   do_srav (SD_, RS, RT, RD);
2889 }
2890
2891
2892
2893 :function:::void:do_srl:int rt, int rd, int shift
2894 {
2895   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2896   TRACE_ALU_INPUT2 (GPR[rt], shift);
2897   GPR[rd] = EXTEND32 (temp);
2898   TRACE_ALU_RESULT (GPR[rd]);
2899 }
2900
2901 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2902 "srl r<RD>, r<RT>, <SHIFT>"
2903 *mipsI,mipsII,mipsIII,mipsIV:
2904 *vr5000:
2905 // start-sanitize-vr4320
2906 *vr4320:
2907 // end-sanitize-vr4320
2908 // start-sanitize-vr5400
2909 *vr5400:
2910 // end-sanitize-vr5400
2911 // start-sanitize-r5900
2912 *r5900:
2913 // end-sanitize-r5900
2914 *r3900:
2915 // start-sanitize-tx19
2916 *tx19:
2917 // end-sanitize-tx19
2918 {
2919   do_srl (SD_, RT, RD, SHIFT);
2920 }
2921
2922
2923 :function:::void:do_srlv:int rs, int rt, int rd
2924 {
2925   int s = MASKED (GPR[rs], 4, 0);
2926   unsigned32 temp = (unsigned32) GPR[rt] >> s;
2927   TRACE_ALU_INPUT2 (GPR[rt], s);
2928   GPR[rd] = EXTEND32 (temp);
2929   TRACE_ALU_RESULT (GPR[rd]);
2930 }
2931
2932 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2933 "srlv r<RD>, r<RT>, r<RS>"
2934 *mipsI,mipsII,mipsIII,mipsIV:
2935 *vr5000:
2936 // start-sanitize-vr4320
2937 *vr4320:
2938 // end-sanitize-vr4320
2939 // start-sanitize-vr5400
2940 *vr5400:
2941 // end-sanitize-vr5400
2942 // start-sanitize-r5900
2943 *r5900:
2944 // end-sanitize-r5900
2945 *r3900:
2946 // start-sanitize-tx19
2947 *tx19:
2948 // end-sanitize-tx19
2949 {
2950   do_srlv (SD_, RS, RT, RD);
2951 }
2952
2953
2954 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2955 "sub r<RD>, r<RS>, r<RT>"
2956 *mipsI,mipsII,mipsIII,mipsIV:
2957 *vr5000:
2958 // start-sanitize-vr4320
2959 *vr4320:
2960 // end-sanitize-vr4320
2961 // start-sanitize-vr5400
2962 *vr5400:
2963 // end-sanitize-vr5400
2964 // start-sanitize-r5900
2965 *r5900:
2966 // end-sanitize-r5900
2967 *r3900:
2968 // start-sanitize-tx19
2969 *tx19:
2970 // end-sanitize-tx19
2971 {
2972   ALU32_BEGIN (GPR[RS]);
2973   ALU32_SUB (GPR[RT]);
2974   ALU32_END (GPR[RD]);
2975 }
2976
2977
2978 :function:::void:do_subu:int rs, int rt, int rd
2979 {
2980   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2981   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2982   TRACE_ALU_RESULT (GPR[rd]);
2983 }
2984
2985 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2986 "subu r<RD>, r<RS>, r<RT>"
2987 *mipsI,mipsII,mipsIII,mipsIV:
2988 *vr5000:
2989 // start-sanitize-vr4320
2990 *vr4320:
2991 // end-sanitize-vr4320
2992 // start-sanitize-vr5400
2993 *vr5400:
2994 // end-sanitize-vr5400
2995 // start-sanitize-r5900
2996 *r5900:
2997 // end-sanitize-r5900
2998 *r3900:
2999 // start-sanitize-tx19
3000 *tx19:
3001 // end-sanitize-tx19
3002 {
3003   do_subu (SD_, RS, RT, RD);
3004 }
3005
3006
3007 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3008 "sw r<RT>, <OFFSET>(r<BASE>)"
3009 *mipsI,mipsII,mipsIII,mipsIV:
3010 // start-sanitize-tx19
3011 *tx19:
3012 // end-sanitize-tx19
3013 *r3900:
3014 // start-sanitize-vr4320
3015 *vr4320:
3016 // end-sanitize-vr4320
3017 *vr5000:
3018 // start-sanitize-vr5400
3019 *vr5400:
3020 // end-sanitize-vr5400
3021 // start-sanitize-r5900
3022 *r5900:
3023 // end-sanitize-r5900
3024 {
3025   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3026 }
3027
3028
3029 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3030 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3031 *mipsI,mipsII,mipsIII,mipsIV:
3032 *vr5000:
3033 // start-sanitize-vr4320
3034 *vr4320:
3035 // end-sanitize-vr4320
3036 // start-sanitize-vr5400
3037 *vr5400:
3038 // end-sanitize-vr5400
3039 *r3900:
3040 // start-sanitize-tx19
3041 *tx19:
3042 // end-sanitize-tx19
3043 {
3044   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3045 }
3046
3047
3048
3049 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3050 {
3051   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3052   address_word reverseendian = (ReverseEndian ? -1 : 0);
3053   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3054   unsigned int byte;
3055   address_word paddr;
3056   int uncached;
3057   unsigned64 memval;
3058   address_word vaddr;
3059
3060   vaddr = base + offset;
3061   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3062   paddr = (paddr ^ (reverseendian & mask));
3063   if (BigEndianMem == 0)
3064     paddr = paddr & ~access;
3065   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3066   if ((byte & ~access) == 0)
3067     memval = (rt >> (8 * (access - byte)));
3068   else
3069     memval = (rt << (8 * (mask - byte)));
3070   StoreMemory (uncached, byte & access, memval, NULL, paddr, vaddr, isREAL);
3071 }
3072
3073
3074 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3075 "swl r<RT>, <OFFSET>(r<BASE>)"
3076 *mipsI,mipsII,mipsIII,mipsIV:
3077 *vr5000:
3078 // start-sanitize-vr4320
3079 *vr4320:
3080 // end-sanitize-vr4320
3081 // start-sanitize-vr5400
3082 *vr5400:
3083 // end-sanitize-vr5400
3084 // start-sanitize-r5900
3085 *r5900:
3086 // end-sanitize-r5900
3087 *r3900:
3088 // start-sanitize-tx19
3089 *tx19:
3090 // end-sanitize-tx19
3091 {
3092   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3093 }
3094
3095
3096 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3097 {
3098   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3099   address_word reverseendian = (ReverseEndian ? -1 : 0);
3100   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3101   unsigned int byte;
3102   address_word paddr;
3103   int uncached;
3104   unsigned64 memval;
3105   address_word vaddr;
3106
3107   vaddr = base + offset;
3108   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3109   paddr = (paddr ^ (reverseendian & mask));
3110   if (BigEndianMem != 0)
3111     paddr &= ~access;
3112   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3113   memval = (rt << (byte * 8));
3114   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3115 }
3116
3117 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3118 "swr r<RT>, <OFFSET>(r<BASE>)"
3119 *mipsI,mipsII,mipsIII,mipsIV:
3120 *vr5000:
3121 // start-sanitize-vr4320
3122 *vr4320:
3123 // end-sanitize-vr4320
3124 // start-sanitize-vr5400
3125 *vr5400:
3126 // end-sanitize-vr5400
3127 // start-sanitize-r5900
3128 *r5900:
3129 // end-sanitize-r5900
3130 *r3900:
3131 // start-sanitize-tx19
3132 *tx19:
3133 // end-sanitize-tx19
3134 {
3135   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3136 }
3137
3138
3139 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3140 "sync":STYPE == 0
3141 "sync <STYPE>"
3142 *mipsII:
3143 *mipsIII:
3144 *mipsIV:
3145 *vr5000:
3146 // start-sanitize-vr4320
3147 *vr4320:
3148 // end-sanitize-vr4320
3149 // start-sanitize-vr5400
3150 *vr5400:
3151 // end-sanitize-vr5400
3152 // start-sanitize-r5900
3153 *r5900:
3154 // end-sanitize-r5900
3155 *r3900:
3156 // start-sanitize-tx19
3157 *tx19:
3158 // end-sanitize-tx19
3159 {
3160   SyncOperation (STYPE);
3161 }
3162
3163
3164 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3165 "syscall <CODE>"
3166 *mipsI,mipsII,mipsIII,mipsIV:
3167 *vr5000:
3168 // start-sanitize-vr4320
3169 *vr4320:
3170 // end-sanitize-vr4320
3171 // start-sanitize-vr5400
3172 *vr5400:
3173 // end-sanitize-vr5400
3174 // start-sanitize-r5900
3175 *r5900:
3176 // end-sanitize-r5900
3177 *r3900:
3178 // start-sanitize-tx19
3179 *tx19:
3180 // end-sanitize-tx19
3181 {
3182   SignalException(SystemCall, instruction_0);
3183 }
3184
3185
3186 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3187 "teq r<RS>, r<RT>"
3188 *mipsII:
3189 *mipsIII:
3190 *mipsIV:
3191 *vr5000:
3192 // start-sanitize-vr4320
3193 *vr4320:
3194 // end-sanitize-vr4320
3195 // start-sanitize-vr5400
3196 *vr5400:
3197 // end-sanitize-vr5400
3198 // start-sanitize-r5900
3199 *r5900:
3200 // end-sanitize-r5900
3201 // start-sanitize-tx19
3202 *tx19:
3203 // end-sanitize-tx19
3204 {
3205   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3206     SignalException(Trap, instruction_0);
3207 }
3208
3209
3210 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3211 "teqi r<RS>, <IMMEDIATE>"
3212 *mipsII:
3213 *mipsIII:
3214 *mipsIV:
3215 *vr5000:
3216 // start-sanitize-vr4320
3217 *vr4320:
3218 // end-sanitize-vr4320
3219 // start-sanitize-vr5400
3220 *vr5400:
3221 // end-sanitize-vr5400
3222 // start-sanitize-r5900
3223 *r5900:
3224 // end-sanitize-r5900
3225 // start-sanitize-tx19
3226 *tx19:
3227 // end-sanitize-tx19
3228 {
3229   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3230     SignalException(Trap, instruction_0);
3231 }
3232
3233
3234 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3235 "tge r<RS>, r<RT>"
3236 *mipsII:
3237 *mipsIII:
3238 *mipsIV:
3239 *vr5000:
3240 // start-sanitize-vr4320
3241 *vr4320:
3242 // end-sanitize-vr4320
3243 // start-sanitize-vr5400
3244 *vr5400:
3245 // end-sanitize-vr5400
3246 // start-sanitize-r5900
3247 *r5900:
3248 // end-sanitize-r5900
3249 // start-sanitize-tx19
3250 *tx19:
3251 // end-sanitize-tx19
3252 {
3253   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3254     SignalException(Trap, instruction_0);
3255 }
3256
3257
3258 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3259 "tgei r<RS>, <IMMEDIATE>"
3260 *mipsII:
3261 *mipsIII:
3262 *mipsIV:
3263 *vr5000:
3264 // start-sanitize-vr4320
3265 *vr4320:
3266 // end-sanitize-vr4320
3267 // start-sanitize-vr5400
3268 *vr5400:
3269 // end-sanitize-vr5400
3270 // start-sanitize-r5900
3271 *r5900:
3272 // end-sanitize-r5900
3273 // start-sanitize-tx19
3274 *tx19:
3275 // end-sanitize-tx19
3276 {
3277   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3278     SignalException(Trap, instruction_0);
3279 }
3280
3281
3282 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3283 "tgeiu r<RS>, <IMMEDIATE>"
3284 *mipsII:
3285 *mipsIII:
3286 *mipsIV:
3287 *vr5000:
3288 // start-sanitize-vr4320
3289 *vr4320:
3290 // end-sanitize-vr4320
3291 // start-sanitize-vr5400
3292 *vr5400:
3293 // end-sanitize-vr5400
3294 // start-sanitize-r5900
3295 *r5900:
3296 // end-sanitize-r5900
3297 // start-sanitize-tx19
3298 *tx19:
3299 // end-sanitize-tx19
3300 {
3301   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3302     SignalException(Trap, instruction_0);
3303 }
3304
3305
3306 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3307 "tgeu r<RS>, r<RT>"
3308 *mipsII:
3309 *mipsIII:
3310 *mipsIV:
3311 *vr5000:
3312 // start-sanitize-vr4320
3313 *vr4320:
3314 // end-sanitize-vr4320
3315 // start-sanitize-vr5400
3316 *vr5400:
3317 // end-sanitize-vr5400
3318 // start-sanitize-r5900
3319 *r5900:
3320 // end-sanitize-r5900
3321 // start-sanitize-tx19
3322 *tx19:
3323 // end-sanitize-tx19
3324 {
3325   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3326     SignalException(Trap, instruction_0);
3327 }
3328
3329
3330 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3331 "tlt r<RS>, r<RT>"
3332 *mipsII:
3333 *mipsIII:
3334 *mipsIV:
3335 *vr5000:
3336 // start-sanitize-vr4320
3337 *vr4320:
3338 // end-sanitize-vr4320
3339 // start-sanitize-vr5400
3340 *vr5400:
3341 // end-sanitize-vr5400
3342 // start-sanitize-r5900
3343 *r5900:
3344 // end-sanitize-r5900
3345 // start-sanitize-tx19
3346 *tx19:
3347 // end-sanitize-tx19
3348 {
3349   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3350     SignalException(Trap, instruction_0);
3351 }
3352
3353
3354 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3355 "tlti r<RS>, <IMMEDIATE>"
3356 *mipsII:
3357 *mipsIII:
3358 *mipsIV:
3359 *vr5000:
3360 // start-sanitize-vr4320
3361 *vr4320:
3362 // end-sanitize-vr4320
3363 // start-sanitize-vr5400
3364 *vr5400:
3365 // end-sanitize-vr5400
3366 // start-sanitize-r5900
3367 *r5900:
3368 // end-sanitize-r5900
3369 // start-sanitize-tx19
3370 *tx19:
3371 // end-sanitize-tx19
3372 {
3373   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3374     SignalException(Trap, instruction_0);
3375 }
3376
3377
3378 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3379 "tltiu r<RS>, <IMMEDIATE>"
3380 *mipsII:
3381 *mipsIII:
3382 *mipsIV:
3383 *vr5000:
3384 // start-sanitize-vr4320
3385 *vr4320:
3386 // end-sanitize-vr4320
3387 // start-sanitize-vr5400
3388 *vr5400:
3389 // end-sanitize-vr5400
3390 // start-sanitize-r5900
3391 *r5900:
3392 // end-sanitize-r5900
3393 // start-sanitize-tx19
3394 *tx19:
3395 // end-sanitize-tx19
3396 {
3397   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3398     SignalException(Trap, instruction_0);
3399 }
3400
3401
3402 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3403 "tltu r<RS>, r<RT>"
3404 *mipsII:
3405 *mipsIII:
3406 *mipsIV:
3407 *vr5000:
3408 // start-sanitize-vr4320
3409 *vr4320:
3410 // end-sanitize-vr4320
3411 // start-sanitize-vr5400
3412 *vr5400:
3413 // end-sanitize-vr5400
3414 // start-sanitize-r5900
3415 *r5900:
3416 // end-sanitize-r5900
3417 // start-sanitize-tx19
3418 *tx19:
3419 // end-sanitize-tx19
3420 {
3421   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3422     SignalException(Trap, instruction_0);
3423 }
3424
3425
3426 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3427 "tne r<RS>, r<RT>"
3428 *mipsII:
3429 *mipsIII:
3430 *mipsIV:
3431 *vr5000:
3432 // start-sanitize-vr4320
3433 *vr4320:
3434 // end-sanitize-vr4320
3435 // start-sanitize-vr5400
3436 *vr5400:
3437 // end-sanitize-vr5400
3438 // start-sanitize-r5900
3439 *r5900:
3440 // end-sanitize-r5900
3441 // start-sanitize-tx19
3442 *tx19:
3443 // end-sanitize-tx19
3444 {
3445   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3446     SignalException(Trap, instruction_0);
3447 }
3448
3449
3450 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3451 "tne r<RS>, <IMMEDIATE>"
3452 *mipsII:
3453 *mipsIII:
3454 *mipsIV:
3455 *vr5000:
3456 // start-sanitize-vr4320
3457 *vr4320:
3458 // end-sanitize-vr4320
3459 // start-sanitize-vr5400
3460 *vr5400:
3461 // end-sanitize-vr5400
3462 // start-sanitize-r5900
3463 *r5900:
3464 // end-sanitize-r5900
3465 // start-sanitize-tx19
3466 *tx19:
3467 // end-sanitize-tx19
3468 {
3469   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3470     SignalException(Trap, instruction_0);
3471 }
3472
3473
3474 :function:::void:do_xor:int rs, int rt, int rd
3475 {
3476   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3477   GPR[rd] = GPR[rs] ^ GPR[rt];
3478   TRACE_ALU_RESULT (GPR[rd]);
3479 }
3480
3481 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3482 "xor r<RD>, r<RS>, r<RT>"
3483 *mipsI,mipsII,mipsIII,mipsIV:
3484 *vr5000:
3485 // start-sanitize-vr4320
3486 *vr4320:
3487 // end-sanitize-vr4320
3488 // start-sanitize-vr5400
3489 *vr5400:
3490 // end-sanitize-vr5400
3491 // start-sanitize-r5900
3492 *r5900:
3493 // end-sanitize-r5900
3494 *r3900:
3495 // start-sanitize-tx19
3496 *tx19:
3497 // end-sanitize-tx19
3498 {
3499   do_xor (SD_, RS, RT, RD);
3500 }
3501
3502
3503 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3504 {
3505   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3506   GPR[rt] = GPR[rs] ^ immediate;
3507   TRACE_ALU_RESULT (GPR[rt]);
3508 }
3509
3510 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3511 "xori r<RT>, r<RS>, <IMMEDIATE>"
3512 *mipsI,mipsII,mipsIII,mipsIV:
3513 *vr5000:
3514 // start-sanitize-vr4320
3515 *vr4320:
3516 // end-sanitize-vr4320
3517 // start-sanitize-vr5400
3518 *vr5400:
3519 // end-sanitize-vr5400
3520 // start-sanitize-r5900
3521 *r5900:
3522 // end-sanitize-r5900
3523 *r3900:
3524 // start-sanitize-tx19
3525 *tx19:
3526 // end-sanitize-tx19
3527 {
3528   do_xori (SD_, RS, RT, IMMEDIATE);
3529 }
3530
3531 \f
3532 //
3533 // MIPS Architecture:
3534 //
3535 //        FPU Instruction Set (COP1 & COP1X)
3536 //
3537
3538
3539 :%s::::FMT:int fmt
3540 {
3541   switch (fmt)
3542     {
3543     case fmt_single: return "s";
3544     case fmt_double: return "d";
3545     case fmt_word: return "w";
3546     case fmt_long: return "l";
3547     default: return "?";
3548     }
3549 }
3550
3551 :%s::::X:int x
3552 {
3553   switch (x)
3554     {
3555     case 0: return "f";
3556     case 1: return "t";
3557     default: return "?";
3558     }
3559 }
3560
3561 :%s::::TF:int tf
3562 {
3563   if (tf)
3564     return "t";
3565   else
3566     return "f";
3567 }
3568
3569 :%s::::ND:int nd
3570 {
3571   if (nd)
3572     return "l";
3573   else
3574     return "";
3575 }
3576
3577 :%s::::COND:int cond
3578 {
3579   switch (cond)
3580     {
3581     case 00: return "f";
3582     case 01: return "un";
3583     case 02: return "eq";
3584     case 03: return "ueq";
3585     case 04: return "olt";
3586     case 05: return "ult";
3587     case 06: return "ole";
3588     case 07: return "ule";
3589     case 010: return "sf";
3590     case 011: return "ngle";
3591     case 012: return "seq";
3592     case 013: return "ngl";
3593     case 014: return "lt";
3594     case 015: return "nge";
3595     case 016: return "le";
3596     case 017: return "ngt";
3597     default: return "?";
3598     }
3599 }
3600
3601
3602 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3603 "abs.%s<FMT> f<FD>, f<FS>"
3604 *mipsI,mipsII,mipsIII,mipsIV:
3605 *vr5000:
3606 // start-sanitize-vr4320
3607 *vr4320:
3608 // end-sanitize-vr4320
3609 // start-sanitize-vr5400
3610 *vr5400:
3611 // end-sanitize-vr5400
3612 *r3900:
3613 // start-sanitize-tx19
3614 *tx19:
3615 // end-sanitize-tx19
3616 {
3617   unsigned32 instruction = instruction_0;
3618   int destreg = ((instruction >> 6) & 0x0000001F);
3619   int fs = ((instruction >> 11) & 0x0000001F);
3620   int format = ((instruction >> 21) & 0x00000007);
3621   {
3622     if ((format != fmt_single) && (format != fmt_double))
3623       SignalException(ReservedInstruction,instruction);
3624     else
3625       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3626   }
3627 }
3628
3629
3630
3631 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3632 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3633 *mipsI,mipsII,mipsIII,mipsIV:
3634 *vr5000:
3635 // start-sanitize-vr4320
3636 *vr4320:
3637 // end-sanitize-vr4320
3638 // start-sanitize-vr5400
3639 *vr5400:
3640 // end-sanitize-vr5400
3641 *r3900:
3642 // start-sanitize-tx19
3643 *tx19:
3644 // end-sanitize-tx19
3645 {
3646   unsigned32 instruction = instruction_0;
3647   int destreg = ((instruction >> 6) & 0x0000001F);
3648   int fs = ((instruction >> 11) & 0x0000001F);
3649   int ft = ((instruction >> 16) & 0x0000001F);
3650   int format = ((instruction >> 21) & 0x00000007);
3651   {
3652     if ((format != fmt_single) && (format != fmt_double))
3653       SignalException(ReservedInstruction, instruction);
3654     else
3655       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3656   }
3657 }
3658
3659
3660
3661 // BC1F
3662 // BC1FL
3663 // BC1T
3664 // BC1TL
3665
3666 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3667 "bc1%s<TF>%s<ND> <OFFSET>"
3668 *mipsI,mipsII,mipsIII:
3669 // start-sanitize-r5900
3670 *r5900:
3671 // end-sanitize-r5900
3672 {
3673   TRACE_BRANCH_INPUT (PREVCOC1());
3674   if (PREVCOC1() == TF)
3675     {
3676       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3677       TRACE_BRANCH_RESULT (dest);
3678       DELAY_SLOT (dest);
3679     }
3680   else if (ND)
3681     {
3682       TRACE_BRANCH_RESULT (0);
3683       NULLIFY_NEXT_INSTRUCTION ();
3684     }
3685   else
3686     {
3687       TRACE_BRANCH_RESULT (NIA);
3688     }
3689 }
3690
3691 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3692 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3693 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3694 *mipsIV:
3695 *vr5000:
3696 // start-sanitize-vr4320
3697 *vr4320:
3698 // end-sanitize-vr4320
3699 // start-sanitize-vr5400
3700 *vr5400:
3701 // end-sanitize-vr5400
3702 *r3900:
3703 // start-sanitize-tx19
3704 *tx19:
3705 // end-sanitize-tx19
3706 {
3707   if (GETFCC(CC) == TF)
3708     {
3709       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3710     }
3711   else if (ND)
3712     {
3713       NULLIFY_NEXT_INSTRUCTION ();
3714     }
3715 }
3716
3717
3718
3719 // C.EQ.S
3720 // C.EQ.D
3721 // ...
3722
3723 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3724 {
3725   if ((fmt != fmt_single) && (fmt != fmt_double))
3726     SignalException (ReservedInstruction, insn);
3727   else
3728     {
3729       int less;
3730       int equal;
3731       int unordered;
3732       int condition;
3733       unsigned64 ofs = ValueFPR (fs, fmt);
3734       unsigned64 oft = ValueFPR (ft, fmt);
3735       if (NaN (ofs, fmt) || NaN (oft, fmt))
3736         {
3737           if (FCSR & FP_ENABLE (IO))
3738             {
3739               FCSR |= FP_CAUSE (IO);
3740               SignalExceptionFPE ();
3741             }
3742           less = 0;
3743           equal = 0;
3744           unordered = 1;
3745         }
3746       else
3747         {
3748           less = Less (ofs, oft, fmt);
3749           equal = Equal (ofs, oft, fmt);
3750           unordered = 0;
3751         }
3752       condition = (((cond & (1 << 2)) && less)
3753                    || ((cond & (1 << 1)) && equal)
3754                    || ((cond & (1 << 0)) && unordered));
3755       SETFCC (cc, condition);
3756     }
3757 }
3758
3759 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3760 *mipsI,mipsII,mipsIII:
3761 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3762 {
3763   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3764 }
3765
3766 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3767 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3768 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3769 *mipsIV:
3770 *vr5000:
3771 // start-sanitize-vr4320
3772 *vr4320:
3773 // end-sanitize-vr4320
3774 // start-sanitize-vr5400
3775 *vr5400:
3776 // end-sanitize-vr5400
3777 *r3900:
3778 // start-sanitize-tx19
3779 *tx19:
3780 // end-sanitize-tx19
3781 {
3782   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3783 }
3784
3785
3786 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3787 "ceil.l.%s<FMT> f<FD>, f<FS>"
3788 *mipsIII:
3789 *mipsIV:
3790 *vr5000:
3791 // start-sanitize-vr4320
3792 *vr4320:
3793 // end-sanitize-vr4320
3794 // start-sanitize-vr5400
3795 *vr5400:
3796 // end-sanitize-vr5400
3797 // start-sanitize-r5900
3798 *r5900:
3799 // end-sanitize-r5900
3800 *r3900:
3801 // start-sanitize-tx19
3802 *tx19:
3803 // end-sanitize-tx19
3804 {
3805   unsigned32 instruction = instruction_0;
3806   int destreg = ((instruction >> 6) & 0x0000001F);
3807   int fs = ((instruction >> 11) & 0x0000001F);
3808   int format = ((instruction >> 21) & 0x00000007);
3809   {
3810     if ((format != fmt_single) && (format != fmt_double))
3811       SignalException(ReservedInstruction,instruction);
3812     else
3813       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3814   }
3815 }
3816
3817
3818 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3819 *mipsII:
3820 *mipsIII:
3821 *mipsIV:
3822 *vr5000:
3823 // start-sanitize-vr4320
3824 *vr4320:
3825 // end-sanitize-vr4320
3826 // start-sanitize-vr5400
3827 *vr5400:
3828 // end-sanitize-vr5400
3829 // start-sanitize-r5900
3830 *r5900:
3831 // end-sanitize-r5900
3832 *r3900:
3833 // start-sanitize-tx19
3834 *tx19:
3835 // end-sanitize-tx19
3836 {
3837   unsigned32 instruction = instruction_0;
3838   int destreg = ((instruction >> 6) & 0x0000001F);
3839   int fs = ((instruction >> 11) & 0x0000001F);
3840   int format = ((instruction >> 21) & 0x00000007);
3841   {
3842   if ((format != fmt_single) && (format != fmt_double))
3843    SignalException(ReservedInstruction,instruction);
3844   else
3845    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3846   }
3847 }
3848
3849
3850 // CFC1
3851 // CTC1
3852 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3853 "c%s<X>c1 r<RT>, f<FS>"
3854 *mipsI:
3855 *mipsII:
3856 *mipsIII:
3857 {
3858   if (X)
3859     {
3860       if (FS == 0)
3861         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3862       else if (FS == 31)
3863         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
3864       /* else NOP */
3865       PENDING_FILL(COCIDX,0); /* special case */
3866     }
3867   else
3868     { /* control from */
3869       if (FS == 0)
3870         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3871       else if (FS == 31)
3872         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3873       /* else NOP */
3874     }
3875 }
3876 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3877 "c%s<X>c1 r<RT>, f<FS>"
3878 *mipsIV:
3879 *vr5000:
3880 // start-sanitize-vr4320
3881 *vr4320:
3882 // end-sanitize-vr4320
3883 // start-sanitize-vr5400
3884 *vr5400:
3885 // end-sanitize-vr5400
3886 // start-sanitize-r5900
3887 *r5900:
3888 // end-sanitize-r5900
3889 *r3900:
3890 // start-sanitize-tx19
3891 *tx19:
3892 // end-sanitize-tx19
3893 {
3894   if (X)
3895     {
3896       /* control to */
3897       TRACE_ALU_INPUT1 (GPR[RT]);
3898       if (FS == 0)
3899         {
3900           FCR0 = VL4_8(GPR[RT]);
3901           TRACE_ALU_RESULT (FCR0);
3902         }
3903       else if (FS == 31)
3904         {
3905           FCR31 = VL4_8(GPR[RT]);
3906           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3907           TRACE_ALU_RESULT (FCR31);
3908         }
3909       else
3910         {
3911           TRACE_ALU_RESULT0 ();
3912         }
3913       /* else NOP */
3914     }
3915   else
3916     { /* control from */
3917       if (FS == 0)
3918         {
3919           TRACE_ALU_INPUT1 (FCR0);
3920           GPR[RT] = SIGNEXTEND (FCR0, 32);
3921         }
3922       else if (FS == 31)
3923         {
3924           TRACE_ALU_INPUT1 (FCR31);
3925           GPR[RT] = SIGNEXTEND (FCR31, 32);
3926         }
3927       TRACE_ALU_RESULT (GPR[RT]);
3928       /* else NOP */
3929     }
3930 }
3931
3932
3933 //
3934 // FIXME: Does not correctly differentiate between mips*
3935 //
3936 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3937 "cvt.d.%s<FMT> f<FD>, f<FS>"
3938 *mipsI,mipsII,mipsIII,mipsIV:
3939 *vr5000:
3940 // start-sanitize-vr4320
3941 *vr4320:
3942 // end-sanitize-vr4320
3943 // start-sanitize-vr5400
3944 *vr5400:
3945 // end-sanitize-vr5400
3946 *r3900:
3947 // start-sanitize-tx19
3948 *tx19:
3949 // end-sanitize-tx19
3950 {
3951   unsigned32 instruction = instruction_0;
3952   int destreg = ((instruction >> 6) & 0x0000001F);
3953   int fs = ((instruction >> 11) & 0x0000001F);
3954   int format = ((instruction >> 21) & 0x00000007);
3955   {
3956     if ((format == fmt_double) | 0)
3957       SignalException(ReservedInstruction,instruction);
3958     else
3959       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3960   }
3961 }
3962
3963
3964 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3965 "cvt.l.%s<FMT> f<FD>, f<FS>"
3966 *mipsIII:
3967 *mipsIV:
3968 *vr5000:
3969 // start-sanitize-vr4320
3970 *vr4320:
3971 // end-sanitize-vr4320
3972 // start-sanitize-vr5400
3973 *vr5400:
3974 // end-sanitize-vr5400
3975 *r3900:
3976 // start-sanitize-tx19
3977 *tx19:
3978 // end-sanitize-tx19
3979 {
3980   unsigned32 instruction = instruction_0;
3981   int destreg = ((instruction >> 6) & 0x0000001F);
3982   int fs = ((instruction >> 11) & 0x0000001F);
3983   int format = ((instruction >> 21) & 0x00000007);
3984   {
3985     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3986       SignalException(ReservedInstruction,instruction);
3987     else
3988       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3989   }
3990 }
3991
3992
3993 //
3994 // FIXME: Does not correctly differentiate between mips*
3995 //
3996 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3997 "cvt.s.%s<FMT> f<FD>, f<FS>"
3998 *mipsI,mipsII,mipsIII,mipsIV:
3999 *vr5000:
4000 // start-sanitize-vr4320
4001 *vr4320:
4002 // end-sanitize-vr4320
4003 // start-sanitize-vr5400
4004 *vr5400:
4005 // end-sanitize-vr5400
4006 *r3900:
4007 // start-sanitize-tx19
4008 *tx19:
4009 // end-sanitize-tx19
4010 {
4011   unsigned32 instruction = instruction_0;
4012   int destreg = ((instruction >> 6) & 0x0000001F);
4013   int fs = ((instruction >> 11) & 0x0000001F);
4014   int format = ((instruction >> 21) & 0x00000007);
4015   {
4016     if ((format == fmt_single) | 0)
4017       SignalException(ReservedInstruction,instruction);
4018     else
4019       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4020   }
4021 }
4022
4023
4024 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4025 "cvt.w.%s<FMT> f<FD>, f<FS>"
4026 *mipsI,mipsII,mipsIII,mipsIV:
4027 *vr5000:
4028 // start-sanitize-vr4320
4029 *vr4320:
4030 // end-sanitize-vr4320
4031 // start-sanitize-vr5400
4032 *vr5400:
4033 // end-sanitize-vr5400
4034 *r3900:
4035 // start-sanitize-tx19
4036 *tx19:
4037 // end-sanitize-tx19
4038 {
4039   unsigned32 instruction = instruction_0;
4040   int destreg = ((instruction >> 6) & 0x0000001F);
4041   int fs = ((instruction >> 11) & 0x0000001F);
4042   int format = ((instruction >> 21) & 0x00000007);
4043   {
4044     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4045       SignalException(ReservedInstruction,instruction);
4046     else
4047       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4048   }
4049 }
4050
4051
4052 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4053 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4054 *mipsI,mipsII,mipsIII,mipsIV:
4055 *vr5000:
4056 // start-sanitize-vr4320
4057 *vr4320:
4058 // end-sanitize-vr4320
4059 // start-sanitize-vr5400
4060 *vr5400:
4061 // end-sanitize-vr5400
4062 *r3900:
4063 // start-sanitize-tx19
4064 *tx19:
4065 // end-sanitize-tx19
4066 {
4067   unsigned32 instruction = instruction_0;
4068   int destreg = ((instruction >> 6) & 0x0000001F);
4069   int fs = ((instruction >> 11) & 0x0000001F);
4070   int ft = ((instruction >> 16) & 0x0000001F);
4071   int format = ((instruction >> 21) & 0x00000007);
4072   {
4073     if ((format != fmt_single) && (format != fmt_double))
4074       SignalException(ReservedInstruction,instruction);
4075     else
4076       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4077   }
4078 }
4079
4080
4081 // DMFC1
4082 // DMTC1
4083 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4084 "dm%s<X>c1 r<RT>, f<FS>"
4085 *mipsIII:
4086 {
4087   if (X)
4088     {
4089       if (SizeFGR() == 64)
4090         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4091       else if ((FS & 0x1) == 0)
4092         {
4093           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4094           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4095         }
4096     }
4097   else
4098     {
4099       if (SizeFGR() == 64)
4100         PENDING_FILL(RT,FGR[FS]);
4101       else if ((FS & 0x1) == 0)
4102         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4103       else
4104         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4105     }
4106 }
4107 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4108 "dm%s<X>c1 r<RT>, f<FS>"
4109 *mipsIV:
4110 *vr5000:
4111 // start-sanitize-vr4320
4112 *vr4320:
4113 // end-sanitize-vr4320
4114 // start-sanitize-vr5400
4115 *vr5400:
4116 // end-sanitize-vr5400
4117 // start-sanitize-r5900
4118 *r5900:
4119 // end-sanitize-r5900
4120 *r3900:
4121 // start-sanitize-tx19
4122 *tx19:
4123 // end-sanitize-tx19
4124 {
4125   if (X)
4126     {
4127       if (SizeFGR() == 64)
4128         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4129       else if ((FS & 0x1) == 0)
4130         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4131     }
4132   else
4133     {
4134       if (SizeFGR() == 64)
4135         GPR[RT] = FGR[FS];
4136       else if ((FS & 0x1) == 0)
4137         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4138       else
4139         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4140     }
4141 }
4142
4143
4144 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4145 "floor.l.%s<FMT> f<FD>, f<FS>"
4146 *mipsIII:
4147 *mipsIV:
4148 *vr5000:
4149 // start-sanitize-vr4320
4150 *vr4320:
4151 // end-sanitize-vr4320
4152 // start-sanitize-vr5400
4153 *vr5400:
4154 // end-sanitize-vr5400
4155 // start-sanitize-r5900
4156 *r5900:
4157 // end-sanitize-r5900
4158 *r3900:
4159 // start-sanitize-tx19
4160 *tx19:
4161 // end-sanitize-tx19
4162 {
4163   unsigned32 instruction = instruction_0;
4164   int destreg = ((instruction >> 6) & 0x0000001F);
4165   int fs = ((instruction >> 11) & 0x0000001F);
4166   int format = ((instruction >> 21) & 0x00000007);
4167   {
4168     if ((format != fmt_single) && (format != fmt_double))
4169       SignalException(ReservedInstruction,instruction);
4170     else
4171       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4172   }
4173 }
4174
4175
4176 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4177 "floor.w.%s<FMT> f<FD>, f<FS>"
4178 *mipsII:
4179 *mipsIII:
4180 *mipsIV:
4181 *vr5000:
4182 // start-sanitize-vr4320
4183 *vr4320:
4184 // end-sanitize-vr4320
4185 // start-sanitize-vr5400
4186 *vr5400:
4187 // end-sanitize-vr5400
4188 // start-sanitize-r5900
4189 *r5900:
4190 // end-sanitize-r5900
4191 *r3900:
4192 // start-sanitize-tx19
4193 *tx19:
4194 // end-sanitize-tx19
4195 {
4196   unsigned32 instruction = instruction_0;
4197   int destreg = ((instruction >> 6) & 0x0000001F);
4198   int fs = ((instruction >> 11) & 0x0000001F);
4199   int format = ((instruction >> 21) & 0x00000007);
4200   {
4201     if ((format != fmt_single) && (format != fmt_double))
4202       SignalException(ReservedInstruction,instruction);
4203     else
4204       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4205   }
4206 }
4207
4208
4209 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4210 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4211 *mipsII:
4212 *mipsIII:
4213 *mipsIV:
4214 *vr5000:
4215 // start-sanitize-vr4320
4216 *vr4320:
4217 // end-sanitize-vr4320
4218 // start-sanitize-vr5400
4219 *vr5400:
4220 // end-sanitize-vr5400
4221 *r3900:
4222 // start-sanitize-tx19
4223 *tx19:
4224 // end-sanitize-tx19
4225 {
4226   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4227 }
4228
4229
4230 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4231 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4232 *mipsIV:
4233 *vr5000:
4234 // start-sanitize-vr4320
4235 *vr4320:
4236 // end-sanitize-vr4320
4237 // start-sanitize-vr5400
4238 *vr5400:
4239 // end-sanitize-vr5400
4240 {
4241   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4242 }
4243
4244
4245
4246 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4247 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4248 *mipsI,mipsII,mipsIII,mipsIV:
4249 *vr5000:
4250 // start-sanitize-vr4320
4251 *vr4320:
4252 // end-sanitize-vr4320
4253 // start-sanitize-vr5400
4254 *vr5400:
4255 // end-sanitize-vr5400
4256 // start-sanitize-r5900
4257 *r5900:
4258 // end-sanitize-r5900
4259 *r3900:
4260 // start-sanitize-tx19
4261 *tx19:
4262 // end-sanitize-tx19
4263 {
4264   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4265 }
4266
4267
4268 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4269 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4270 *mipsIV:
4271 *vr5000:
4272 // start-sanitize-vr4320
4273 *vr4320:
4274 // end-sanitize-vr4320
4275 // start-sanitize-vr5400
4276 *vr5400:
4277 // end-sanitize-vr5400
4278 {
4279   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4280 }
4281
4282
4283
4284 //
4285 // FIXME: Not correct for mips*
4286 //
4287 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4288 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4289 *mipsIV:
4290 *vr5000:
4291 // start-sanitize-vr4320
4292 *vr4320:
4293 // end-sanitize-vr4320
4294 // start-sanitize-vr5400
4295 *vr5400:
4296 // end-sanitize-vr5400
4297 {
4298   unsigned32 instruction = instruction_0;
4299   int destreg = ((instruction >> 6) & 0x0000001F);
4300   int fs = ((instruction >> 11) & 0x0000001F);
4301   int ft = ((instruction >> 16) & 0x0000001F);
4302   int fr = ((instruction >> 21) & 0x0000001F);
4303   {
4304     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4305   }
4306 }
4307
4308
4309 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4310 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4311 *mipsIV:
4312 *vr5000:
4313 // start-sanitize-vr4320
4314 *vr4320:
4315 // end-sanitize-vr4320
4316 // start-sanitize-vr5400
4317 *vr5400:
4318 // end-sanitize-vr5400
4319 {
4320   unsigned32 instruction = instruction_0;
4321   int destreg = ((instruction >> 6) & 0x0000001F);
4322   int fs = ((instruction >> 11) & 0x0000001F);
4323   int ft = ((instruction >> 16) & 0x0000001F);
4324   int fr = ((instruction >> 21) & 0x0000001F);
4325   {
4326     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4327   }
4328 }
4329
4330
4331 // MFC1
4332 // MTC1
4333 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4334 "m%s<X>c1 r<RT>, f<FS>"
4335 *mipsI:
4336 *mipsII:
4337 *mipsIII:
4338 {
4339   if (X)
4340     { /*MTC1*/
4341       if (SizeFGR() == 64)
4342         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4343       else
4344         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4345     }
4346   else /*MFC1*/
4347     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4348 }
4349 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4350 "m%s<X>c1 r<RT>, f<FS>"
4351 *mipsIV:
4352 *vr5000:
4353 // start-sanitize-vr4320
4354 *vr4320:
4355 // end-sanitize-vr4320
4356 // start-sanitize-vr5400
4357 *vr5400:
4358 // end-sanitize-vr5400
4359 *r3900:
4360 // start-sanitize-tx19
4361 *tx19:
4362 // end-sanitize-tx19
4363 {
4364   if (X)
4365     /*MTC1*/
4366     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4367   else /*MFC1*/
4368     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4369 }
4370
4371
4372 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4373 "mov.%s<FMT> f<FD>, f<FS>"
4374 *mipsI,mipsII,mipsIII,mipsIV:
4375 *vr5000:
4376 // start-sanitize-vr4320
4377 *vr4320:
4378 // end-sanitize-vr4320
4379 // start-sanitize-vr5400
4380 *vr5400:
4381 // end-sanitize-vr5400
4382 *r3900:
4383 // start-sanitize-tx19
4384 *tx19:
4385 // end-sanitize-tx19
4386 {
4387   unsigned32 instruction = instruction_0;
4388   int destreg = ((instruction >> 6) & 0x0000001F);
4389   int fs = ((instruction >> 11) & 0x0000001F);
4390   int format = ((instruction >> 21) & 0x00000007);
4391   {
4392     StoreFPR(destreg,format,ValueFPR(fs,format));
4393   }
4394 }
4395
4396
4397 // MOVF
4398 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4399 "mov%s<TF> r<RD>, r<RS>, <CC>"
4400 *mipsIV:
4401 *vr5000:
4402 // start-sanitize-vr4320
4403 *vr4320:
4404 // end-sanitize-vr4320
4405 // start-sanitize-vr5400
4406 *vr5400:
4407 // end-sanitize-vr5400
4408 // start-sanitize-r5900
4409 *r5900:
4410 // end-sanitize-r5900
4411 {
4412   if (GETFCC(CC) == TF)
4413     GPR[RD] = GPR[RS];
4414 }
4415
4416
4417 // MOVF.fmt
4418 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4419 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4420 *mipsIV:
4421 *vr5000:
4422 // start-sanitize-vr4320
4423 *vr4320:
4424 // end-sanitize-vr4320
4425 // start-sanitize-vr5400
4426 *vr5400:
4427 // end-sanitize-vr5400
4428 // start-sanitize-r5900
4429 *r5900:
4430 // end-sanitize-r5900
4431 {
4432   unsigned32 instruction = instruction_0;
4433   int format = ((instruction >> 21) & 0x00000007);
4434   {
4435    if (GETFCC(CC) == TF)
4436      StoreFPR (FD, format, ValueFPR (FS, format));
4437    else
4438      StoreFPR (FD, format, ValueFPR (FD, format));
4439   }
4440 }
4441
4442
4443 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4444 *mipsIV:
4445 *vr5000:
4446 // start-sanitize-vr4320
4447 *vr4320:
4448 // end-sanitize-vr4320
4449 // start-sanitize-vr5400
4450 *vr5400:
4451 // end-sanitize-vr5400
4452 // start-sanitize-r5900
4453 *r5900:
4454 // end-sanitize-r5900
4455 {
4456   unsigned32 instruction = instruction_0;
4457   int destreg = ((instruction >> 6) & 0x0000001F);
4458   int fs = ((instruction >> 11) & 0x0000001F);
4459   int format = ((instruction >> 21) & 0x00000007);
4460   {
4461     StoreFPR(destreg,format,ValueFPR(fs,format));
4462   }
4463 }
4464
4465
4466 // MOVT see MOVtf
4467
4468
4469 // MOVT.fmt see MOVtf.fmt
4470
4471
4472
4473 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4474 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4475 *mipsIV:
4476 *vr5000:
4477 // start-sanitize-vr4320
4478 *vr4320:
4479 // end-sanitize-vr4320
4480 // start-sanitize-vr5400
4481 *vr5400:
4482 // end-sanitize-vr5400
4483 // start-sanitize-r5900
4484 *r5900:
4485 // end-sanitize-r5900
4486 {
4487   unsigned32 instruction = instruction_0;
4488   int destreg = ((instruction >> 6) & 0x0000001F);
4489   int fs = ((instruction >> 11) & 0x0000001F);
4490   int format = ((instruction >> 21) & 0x00000007);
4491   {
4492    StoreFPR(destreg,format,ValueFPR(fs,format));
4493   }
4494 }
4495
4496
4497 // MSUB.fmt
4498 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4499 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4500 *mipsIV:
4501 *vr5000:
4502 // start-sanitize-vr4320
4503 *vr4320:
4504 // end-sanitize-vr4320
4505 // start-sanitize-vr5400
4506 *vr5400:
4507 // end-sanitize-vr5400
4508 // start-sanitize-r5900
4509 *r5900:
4510 // end-sanitize-r5900
4511 {
4512   unsigned32 instruction = instruction_0;
4513   int destreg = ((instruction >> 6) & 0x0000001F);
4514   int fs = ((instruction >> 11) & 0x0000001F);
4515   int ft = ((instruction >> 16) & 0x0000001F);
4516   int fr = ((instruction >> 21) & 0x0000001F);
4517   {
4518     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4519   }
4520 }
4521
4522
4523 // MSUB.fmt
4524 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4525 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4526 *mipsIV:
4527 *vr5000:
4528 // start-sanitize-vr4320
4529 *vr4320:
4530 // end-sanitize-vr4320
4531 // start-sanitize-vr5400
4532 *vr5400:
4533 // end-sanitize-vr5400
4534 // start-sanitize-r5900
4535 *r5900:
4536 // end-sanitize-r5900
4537 {
4538   unsigned32 instruction = instruction_0;
4539   int destreg = ((instruction >> 6) & 0x0000001F);
4540   int fs = ((instruction >> 11) & 0x0000001F);
4541   int ft = ((instruction >> 16) & 0x0000001F);
4542   int fr = ((instruction >> 21) & 0x0000001F);
4543   {
4544    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4545   }
4546 }
4547
4548
4549 // MTC1 see MxC1
4550
4551
4552 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4553 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4554 *mipsI,mipsII,mipsIII,mipsIV:
4555 *vr5000:
4556 // start-sanitize-vr4320
4557 *vr4320:
4558 // end-sanitize-vr4320
4559 // start-sanitize-vr5400
4560 *vr5400:
4561 // end-sanitize-vr5400
4562 *r3900:
4563 // start-sanitize-tx19
4564 *tx19:
4565 // end-sanitize-tx19
4566 {
4567   unsigned32 instruction = instruction_0;
4568   int destreg = ((instruction >> 6) & 0x0000001F);
4569   int fs = ((instruction >> 11) & 0x0000001F);
4570   int ft = ((instruction >> 16) & 0x0000001F);
4571   int format = ((instruction >> 21) & 0x00000007);
4572   {
4573     if ((format != fmt_single) && (format != fmt_double))
4574       SignalException(ReservedInstruction,instruction);
4575     else
4576       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4577   }
4578 }
4579
4580
4581 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4582 "neg.%s<FMT> f<FD>, f<FS>"
4583 *mipsI,mipsII,mipsIII,mipsIV:
4584 *vr5000:
4585 // start-sanitize-vr4320
4586 *vr4320:
4587 // end-sanitize-vr4320
4588 // start-sanitize-vr5400
4589 *vr5400:
4590 // end-sanitize-vr5400
4591 *r3900:
4592 // start-sanitize-tx19
4593 *tx19:
4594 // end-sanitize-tx19
4595 {
4596   unsigned32 instruction = instruction_0;
4597   int destreg = ((instruction >> 6) & 0x0000001F);
4598   int fs = ((instruction >> 11) & 0x0000001F);
4599   int format = ((instruction >> 21) & 0x00000007);
4600   {
4601     if ((format != fmt_single) && (format != fmt_double))
4602       SignalException(ReservedInstruction,instruction);
4603     else
4604       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4605   }
4606 }
4607
4608
4609 // NMADD.fmt
4610 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4611 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4612 *mipsIV:
4613 *vr5000:
4614 // start-sanitize-vr4320
4615 *vr4320:
4616 // end-sanitize-vr4320
4617 // start-sanitize-vr5400
4618 *vr5400:
4619 // end-sanitize-vr5400
4620 {
4621   unsigned32 instruction = instruction_0;
4622   int destreg = ((instruction >> 6) & 0x0000001F);
4623   int fs = ((instruction >> 11) & 0x0000001F);
4624   int ft = ((instruction >> 16) & 0x0000001F);
4625   int fr = ((instruction >> 21) & 0x0000001F);
4626   {
4627    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4628   }
4629 }
4630
4631
4632 // NMADD.fmt
4633 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4634 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4635 *mipsIV:
4636 *vr5000:
4637 // start-sanitize-vr4320
4638 *vr4320:
4639 // end-sanitize-vr4320
4640 // start-sanitize-vr5400
4641 *vr5400:
4642 // end-sanitize-vr5400
4643 {
4644   unsigned32 instruction = instruction_0;
4645   int destreg = ((instruction >> 6) & 0x0000001F);
4646   int fs = ((instruction >> 11) & 0x0000001F);
4647   int ft = ((instruction >> 16) & 0x0000001F);
4648   int fr = ((instruction >> 21) & 0x0000001F);
4649   {
4650    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4651   }
4652 }
4653
4654
4655 // NMSUB.fmt
4656 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4657 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4658 *mipsIV:
4659 *vr5000:
4660 // start-sanitize-vr4320
4661 *vr4320:
4662 // end-sanitize-vr4320
4663 // start-sanitize-vr5400
4664 *vr5400:
4665 // end-sanitize-vr5400
4666 {
4667   unsigned32 instruction = instruction_0;
4668   int destreg = ((instruction >> 6) & 0x0000001F);
4669   int fs = ((instruction >> 11) & 0x0000001F);
4670   int ft = ((instruction >> 16) & 0x0000001F);
4671   int fr = ((instruction >> 21) & 0x0000001F);
4672   {
4673    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4674   }
4675 }
4676
4677
4678 // NMSUB.fmt
4679 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4680 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4681 *mipsIV:
4682 *vr5000:
4683 // start-sanitize-vr4320
4684 *vr4320:
4685 // end-sanitize-vr4320
4686 // start-sanitize-vr5400
4687 *vr5400:
4688 // end-sanitize-vr5400
4689 {
4690   unsigned32 instruction = instruction_0;
4691   int destreg = ((instruction >> 6) & 0x0000001F);
4692   int fs = ((instruction >> 11) & 0x0000001F);
4693   int ft = ((instruction >> 16) & 0x0000001F);
4694   int fr = ((instruction >> 21) & 0x0000001F);
4695   {
4696     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4697   }
4698 }
4699
4700
4701 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4702 "prefx <HINT>, r<INDEX>(r<BASE>)"
4703 *mipsIV:
4704 *vr5000:
4705 // start-sanitize-vr4320
4706 *vr4320:
4707 // end-sanitize-vr4320
4708 // start-sanitize-vr5400
4709 *vr5400:
4710 // end-sanitize-vr5400
4711 {
4712   unsigned32 instruction = instruction_0;
4713   int fs = ((instruction >> 11) & 0x0000001F);
4714   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4715   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4716   {
4717     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4718     address_word paddr;
4719     int uncached;
4720     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4721       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4722   }
4723 }
4724
4725 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4726 *mipsIV:
4727 "recip.%s<FMT> f<FD>, f<FS>"
4728 *vr5000:
4729 // start-sanitize-vr4320
4730 *vr4320:
4731 // end-sanitize-vr4320
4732 // start-sanitize-vr5400
4733 *vr5400:
4734 // end-sanitize-vr5400
4735 {
4736   unsigned32 instruction = instruction_0;
4737   int destreg = ((instruction >> 6) & 0x0000001F);
4738   int fs = ((instruction >> 11) & 0x0000001F);
4739   int format = ((instruction >> 21) & 0x00000007);
4740   {
4741   if ((format != fmt_single) && (format != fmt_double))
4742    SignalException(ReservedInstruction,instruction);
4743   else
4744    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4745   }
4746 }
4747
4748
4749 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4750 "round.l.%s<FMT> f<FD>, f<FS>"
4751 *mipsIII:
4752 *mipsIV:
4753 *vr5000:
4754 // start-sanitize-vr4320
4755 *vr4320:
4756 // end-sanitize-vr4320
4757 // start-sanitize-vr5400
4758 *vr5400:
4759 // end-sanitize-vr5400
4760 // start-sanitize-r5900
4761 *r5900:
4762 // end-sanitize-r5900
4763 *r3900:
4764 // start-sanitize-tx19
4765 *tx19:
4766 // end-sanitize-tx19
4767 {
4768   unsigned32 instruction = instruction_0;
4769   int destreg = ((instruction >> 6) & 0x0000001F);
4770   int fs = ((instruction >> 11) & 0x0000001F);
4771   int format = ((instruction >> 21) & 0x00000007);
4772   {
4773     if ((format != fmt_single) && (format != fmt_double))
4774       SignalException(ReservedInstruction,instruction);
4775     else
4776       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4777   }
4778 }
4779
4780
4781 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4782 "round.w.%s<FMT> f<FD>, f<FS>"
4783 *mipsII:
4784 *mipsIII:
4785 *mipsIV:
4786 *vr5000:
4787 // start-sanitize-vr4320
4788 *vr4320:
4789 // end-sanitize-vr4320
4790 // start-sanitize-vr5400
4791 *vr5400:
4792 // end-sanitize-vr5400
4793 // start-sanitize-r5900
4794 *r5900:
4795 // end-sanitize-r5900
4796 *r3900:
4797 // start-sanitize-tx19
4798 *tx19:
4799 // end-sanitize-tx19
4800 {
4801   unsigned32 instruction = instruction_0;
4802   int destreg = ((instruction >> 6) & 0x0000001F);
4803   int fs = ((instruction >> 11) & 0x0000001F);
4804   int format = ((instruction >> 21) & 0x00000007);
4805   {
4806   if ((format != fmt_single) && (format != fmt_double))
4807    SignalException(ReservedInstruction,instruction);
4808   else
4809    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4810   }
4811 }
4812
4813
4814 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4815 *mipsIV:
4816 "rsqrt.%s<FMT> f<FD>, f<FS>"
4817 *vr5000:
4818 // start-sanitize-vr4320
4819 *vr4320:
4820 // end-sanitize-vr4320
4821 // start-sanitize-vr5400
4822 *vr5400:
4823 // end-sanitize-vr5400
4824 {
4825   unsigned32 instruction = instruction_0;
4826   int destreg = ((instruction >> 6) & 0x0000001F);
4827   int fs = ((instruction >> 11) & 0x0000001F);
4828   int format = ((instruction >> 21) & 0x00000007);
4829   {
4830   if ((format != fmt_single) && (format != fmt_double))
4831    SignalException(ReservedInstruction,instruction);
4832   else
4833    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4834   }
4835 }
4836
4837
4838 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4839 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4840 *mipsII:
4841 *mipsIII:
4842 *mipsIV:
4843 *vr5000:
4844 // start-sanitize-vr4320
4845 *vr4320:
4846 // end-sanitize-vr4320
4847 // start-sanitize-vr5400
4848 *vr5400:
4849 // end-sanitize-vr5400
4850 *r3900:
4851 // start-sanitize-tx19
4852 *tx19:
4853 // end-sanitize-tx19
4854 {
4855   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4856 }
4857
4858
4859 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
4860 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
4861 *mipsIV:
4862 *vr5000:
4863 // start-sanitize-vr4320
4864 *vr4320:
4865 // end-sanitize-vr4320
4866 // start-sanitize-vr5400
4867 *vr5400:
4868 // end-sanitize-vr5400
4869 {
4870   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4871 }
4872
4873
4874 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4875 "sqrt.%s<FMT> f<FD>, f<FS>"
4876 *mipsII:
4877 *mipsIII:
4878 *mipsIV:
4879 *vr5000:
4880 // start-sanitize-vr4320
4881 *vr4320:
4882 // end-sanitize-vr4320
4883 // start-sanitize-vr5400
4884 *vr5400:
4885 // end-sanitize-vr5400
4886 *r3900:
4887 // start-sanitize-tx19
4888 *tx19:
4889 // end-sanitize-tx19
4890 {
4891   unsigned32 instruction = instruction_0;
4892   int destreg = ((instruction >> 6) & 0x0000001F);
4893   int fs = ((instruction >> 11) & 0x0000001F);
4894   int format = ((instruction >> 21) & 0x00000007);
4895   {
4896     if ((format != fmt_single) && (format != fmt_double))
4897       SignalException(ReservedInstruction,instruction);
4898     else
4899       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4900   }
4901 }
4902
4903
4904 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4905 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4906 *mipsI,mipsII,mipsIII,mipsIV:
4907 *vr5000:
4908 // start-sanitize-vr4320
4909 *vr4320:
4910 // end-sanitize-vr4320
4911 // start-sanitize-vr5400
4912 *vr5400:
4913 // end-sanitize-vr5400
4914 *r3900:
4915 // start-sanitize-tx19
4916 *tx19:
4917 // end-sanitize-tx19
4918 {
4919   unsigned32 instruction = instruction_0;
4920   int destreg = ((instruction >> 6) & 0x0000001F);
4921   int fs = ((instruction >> 11) & 0x0000001F);
4922   int ft = ((instruction >> 16) & 0x0000001F);
4923   int format = ((instruction >> 21) & 0x00000007);
4924   {
4925     if ((format != fmt_single) && (format != fmt_double))
4926       SignalException(ReservedInstruction,instruction);
4927     else
4928       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4929   }
4930 }
4931
4932
4933
4934 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
4935 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4936 *mipsI,mipsII,mipsIII,mipsIV:
4937 *vr5000:
4938 // start-sanitize-vr4320
4939 *vr4320:
4940 // end-sanitize-vr4320
4941 // start-sanitize-vr5400
4942 *vr5400:
4943 // end-sanitize-vr5400
4944 // start-sanitize-r5900
4945 *r5900:
4946 // end-sanitize-r5900
4947 *r3900:
4948 // start-sanitize-tx19
4949 *tx19:
4950 // end-sanitize-tx19
4951 {
4952   unsigned32 instruction = instruction_0;
4953   signed_word offset = EXTEND16 (OFFSET);
4954   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4955   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4956   {
4957     address_word vaddr = ((uword64)op1 + offset);
4958     address_word paddr;
4959     int uncached;
4960     if ((vaddr & 3) != 0)
4961       SignalExceptionAddressStore();
4962     else
4963       {
4964         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4965           {
4966             uword64 memval = 0;
4967             uword64 memval1 = 0;
4968             uword64 mask = 0x7;
4969             unsigned int byte;
4970             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4971             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4972             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
4973             {
4974               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4975             }
4976           }
4977       }
4978   }
4979 }
4980
4981
4982 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4983 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4984 *mipsIV:
4985 *vr5000:
4986 // start-sanitize-vr4320
4987 *vr4320:
4988 // end-sanitize-vr4320
4989 // start-sanitize-vr5400
4990 *vr5400:
4991 // end-sanitize-vr5400
4992 {
4993   unsigned32 instruction = instruction_0;
4994   int fs = ((instruction >> 11) & 0x0000001F);
4995   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4996   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4997   {
4998    address_word vaddr = ((unsigned64)op1 + op2);
4999    address_word paddr;
5000    int uncached;
5001    if ((vaddr & 3) != 0)
5002     SignalExceptionAddressStore();
5003    else
5004    {
5005     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5006     {
5007      unsigned64 memval = 0;
5008      unsigned64 memval1 = 0;
5009      unsigned64 mask = 0x7;
5010      unsigned int byte;
5011      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5012      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5013      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5014       {
5015        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5016       }
5017     }
5018    }
5019   }
5020 }
5021
5022
5023 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5024 "trunc.l.%s<FMT> f<FD>, f<FS>"
5025 *mipsIII:
5026 *mipsIV:
5027 *vr5000:
5028 // start-sanitize-vr4320
5029 *vr4320:
5030 // end-sanitize-vr4320
5031 // start-sanitize-vr5400
5032 *vr5400:
5033 // end-sanitize-vr5400
5034 // start-sanitize-r5900
5035 *r5900:
5036 // end-sanitize-r5900
5037 *r3900:
5038 // start-sanitize-tx19
5039 *tx19:
5040 // end-sanitize-tx19
5041 {
5042   unsigned32 instruction = instruction_0;
5043   int destreg = ((instruction >> 6) & 0x0000001F);
5044   int fs = ((instruction >> 11) & 0x0000001F);
5045   int format = ((instruction >> 21) & 0x00000007);
5046   {
5047   if ((format != fmt_single) && (format != fmt_double))
5048    SignalException(ReservedInstruction,instruction);
5049   else
5050    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5051   }
5052 }
5053
5054
5055 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5056 "trunc.w.%s<FMT> f<FD>, f<FS>"
5057 *mipsII:
5058 *mipsIII:
5059 *mipsIV:
5060 *vr5000:
5061 // start-sanitize-vr4320
5062 *vr4320:
5063 // end-sanitize-vr4320
5064 // start-sanitize-vr5400
5065 *vr5400:
5066 // end-sanitize-vr5400
5067 // start-sanitize-r5900
5068 *r5900:
5069 // end-sanitize-r5900
5070 *r3900:
5071 // start-sanitize-tx19
5072 *tx19:
5073 // end-sanitize-tx19
5074 {
5075   unsigned32 instruction = instruction_0;
5076   int destreg = ((instruction >> 6) & 0x0000001F);
5077   int fs = ((instruction >> 11) & 0x0000001F);
5078   int format = ((instruction >> 21) & 0x00000007);
5079   {
5080   if ((format != fmt_single) && (format != fmt_double))
5081    SignalException(ReservedInstruction,instruction);
5082   else
5083    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5084   }
5085 }
5086
5087 \f
5088 //
5089 // MIPS Architecture:
5090 //
5091 //        System Control Instruction Set (COP0)
5092 //
5093
5094
5095 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5096 "bc0f <OFFSET>"
5097 *mipsI,mipsII,mipsIII,mipsIV:
5098 *vr5000:
5099 // start-sanitize-vr4320
5100 *vr4320:
5101 // end-sanitize-vr4320
5102 // start-sanitize-vr5400
5103 *vr5400:
5104 // end-sanitize-vr5400
5105 // start-sanitize-r5900
5106 *r5900:
5107 // end-sanitize-r5900
5108
5109
5110 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5111 "bc0fl <OFFSET>"
5112 *mipsI,mipsII,mipsIII,mipsIV:
5113 *vr5000:
5114 // start-sanitize-vr4320
5115 *vr4320:
5116 // end-sanitize-vr4320
5117 // start-sanitize-vr5400
5118 *vr5400:
5119 // end-sanitize-vr5400
5120 // start-sanitize-r5900
5121 *r5900:
5122 // end-sanitize-r5900
5123
5124
5125 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5126 "bc0t <OFFSET>"
5127 *mipsI,mipsII,mipsIII,mipsIV:
5128 // start-sanitize-r5900
5129 *r5900:
5130 // end-sanitize-r5900
5131
5132
5133
5134 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5135 "bc0tl <OFFSET>"
5136 *mipsI,mipsII,mipsIII,mipsIV:
5137 *vr5000:
5138 // start-sanitize-vr4320
5139 *vr4320:
5140 // end-sanitize-vr4320
5141 // start-sanitize-vr5400
5142 *vr5400:
5143 // end-sanitize-vr5400
5144 // start-sanitize-r5900
5145 *r5900:
5146 // end-sanitize-r5900
5147
5148
5149 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5150 *mipsIII:
5151 *mipsIV:
5152 *vr5000:
5153 // start-sanitize-vr4320
5154 *vr4320:
5155 // end-sanitize-vr4320
5156 // start-sanitize-vr5400
5157 *vr5400:
5158 // end-sanitize-vr5400
5159 // start-sanitize-r5900
5160 *r5900:
5161 // end-sanitize-r5900
5162 *r3900:
5163 // start-sanitize-tx19
5164 *tx19:
5165 // end-sanitize-tx19
5166 {
5167   unsigned32 instruction = instruction_0;
5168   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5169   int hint = ((instruction >> 16) & 0x0000001F);
5170   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5171   {
5172     address_word vaddr = (op1 + offset);
5173     address_word paddr;
5174     int uncached;
5175     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5176       CacheOp(hint,vaddr,paddr,instruction);
5177   }
5178 }
5179
5180
5181 010000,10000,000000000000000,111001:COP0:32::DI
5182 "di"
5183 *mipsI,mipsII,mipsIII,mipsIV:
5184 *vr5000:
5185 // start-sanitize-vr4320
5186 *vr4320:
5187 // end-sanitize-vr4320
5188 // start-sanitize-vr5400
5189 *vr5400:
5190 // end-sanitize-vr5400
5191 // start-sanitize-r5900
5192 *r5900:
5193 // end-sanitize-r5900
5194
5195
5196 010000,10000,000000000000000,111000:COP0:32::EI
5197 "ei"
5198 *mipsI,mipsII,mipsIII,mipsIV:
5199 *vr5000:
5200 // start-sanitize-vr4320
5201 *vr4320:
5202 // end-sanitize-vr4320
5203 // start-sanitize-vr5400
5204 *vr5400:
5205 // end-sanitize-vr5400
5206 // start-sanitize-r5900
5207 *r5900:
5208 // end-sanitize-r5900
5209
5210
5211 010000,10000,000000000000000,011000:COP0:32::ERET
5212 "eret"
5213 *mipsIII:
5214 *mipsIV:
5215 *vr5000:
5216 // start-sanitize-vr4320
5217 *vr4320:
5218 // end-sanitize-vr4320
5219 // start-sanitize-vr5400
5220 *vr5400:
5221 // end-sanitize-vr5400
5222 // start-sanitize-r5900
5223 *r5900:
5224 // end-sanitize-r5900
5225
5226
5227 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5228 "mfc0 r<RT>, r<RD> # <REGX>"
5229 *mipsI,mipsII,mipsIII,mipsIV:
5230 *vr5000:
5231 // start-sanitize-vr4320
5232 *vr4320:
5233 // end-sanitize-vr4320
5234 // start-sanitize-vr5400
5235 *vr5400:
5236 // end-sanitize-vr5400
5237 // start-sanitize-r5900
5238 *r5900:
5239 // end-sanitize-r5900
5240 {
5241   DecodeCoproc (instruction_0);
5242 }
5243
5244 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5245 "mtc0 r<RT>, r<RD> # <REGX>"
5246 *mipsI,mipsII,mipsIII,mipsIV:
5247 // start-sanitize-tx19
5248 *tx19:
5249 // end-sanitize-tx19
5250 *r3900:
5251 // start-sanitize-vr4320
5252 *vr4320:
5253 // end-sanitize-vr4320
5254 *vr5000:
5255 // start-sanitize-vr5400
5256 *vr5400:
5257 // end-sanitize-vr5400
5258 // start-sanitize-r5900
5259 *r5900:
5260 // end-sanitize-r5900
5261 {
5262   DecodeCoproc (instruction_0);
5263 }
5264
5265
5266 010000,10000,000000000000000,001000:COP0:32::TLBP
5267 "tlbp"
5268 *mipsI,mipsII,mipsIII,mipsIV:
5269 *vr5000:
5270 // start-sanitize-vr4320
5271 *vr4320:
5272 // end-sanitize-vr4320
5273 // start-sanitize-vr5400
5274 *vr5400:
5275 // end-sanitize-vr5400
5276 // start-sanitize-r5900
5277 *r5900:
5278 // end-sanitize-r5900
5279
5280
5281 010000,10000,000000000000000,000001:COP0:32::TLBR
5282 "tlbr"
5283 *mipsI,mipsII,mipsIII,mipsIV:
5284 *vr5000:
5285 // start-sanitize-vr4320
5286 *vr4320:
5287 // end-sanitize-vr4320
5288 // start-sanitize-vr5400
5289 *vr5400:
5290 // end-sanitize-vr5400
5291 // start-sanitize-r5900
5292 *r5900:
5293 // end-sanitize-r5900
5294
5295
5296 010000,10000,000000000000000,000010:COP0:32::TLBWI
5297 "tlbwi"
5298 *mipsI,mipsII,mipsIII,mipsIV:
5299 *vr5000:
5300 // start-sanitize-vr4320
5301 *vr4320:
5302 // end-sanitize-vr4320
5303 // start-sanitize-vr5400
5304 *vr5400:
5305 // end-sanitize-vr5400
5306 // start-sanitize-r5900
5307 *r5900:
5308 // end-sanitize-r5900
5309
5310
5311 010000,10000,000000000000000,000110:COP0:32::TLBWR
5312 "tlbwr"
5313 *mipsI,mipsII,mipsIII,mipsIV:
5314 *vr5000:
5315 // start-sanitize-vr4320
5316 *vr4320:
5317 // end-sanitize-vr4320
5318 // start-sanitize-vr5400
5319 *vr5400:
5320 // end-sanitize-vr5400
5321 // start-sanitize-r5900
5322 *r5900:
5323 // end-sanitize-r5900
5324
5325 \f
5326 :include:::m16.igen
5327 // start-sanitize-vr4320
5328 :include::vr4320:vr4320.igen
5329 // end-sanitize-vr4320
5330 // start-sanitize-vr5400
5331 :include::vr5400:vr5400.igen
5332 :include:64,f::mdmx.igen
5333 // end-sanitize-vr5400
5334 // start-sanitize-r5900
5335 :include::r5900:r5900.igen
5336 // end-sanitize-r5900
5337 :include:::tx.igen
5338 \f
5339 // start-sanitize-cygnus-never
5340
5341 // // FIXME FIXME FIXME What is this instruction?
5342 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5343 // *mipsI:
5344 // *mipsII:
5345 // *mipsIII:
5346 // *mipsIV:
5347 // // start-sanitize-r5900
5348 // *r5900:
5349 // // end-sanitize-r5900
5350 // *r3900:
5351 // // start-sanitize-tx19
5352 // *tx19:
5353 // // end-sanitize-tx19
5354 // {
5355 //   unsigned32 instruction = instruction_0;
5356 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5357 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5358 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5359 //   {
5360 //     if (CoProcPresent(3))
5361 //       SignalException(CoProcessorUnusable);
5362 //     else
5363 //       SignalException(ReservedInstruction,instruction);
5364 //   }
5365 // }
5366
5367 // end-sanitize-cygnus-never
5368 // start-sanitize-cygnus-never
5369
5370 // // FIXME FIXME FIXME What is this?
5371 // 11100,******,00001:RR:16::SDBBP
5372 // *mips16:
5373 // {
5374 //   unsigned32 instruction = instruction_0;
5375 //   if (have_extendval)
5376 //     SignalException (ReservedInstruction, instruction);
5377 //   {
5378 //     SignalException(DebugBreakPoint,instruction);
5379 //   }
5380 // }
5381
5382 // end-sanitize-cygnus-never
5383 // start-sanitize-cygnus-never
5384
5385 // // FIXME FIXME FIXME What is this?
5386 // 000000,********************,001110:SPECIAL:32::SDBBP
5387 // *r3900:
5388 // {
5389 //   unsigned32 instruction = instruction_0;
5390 //   {
5391 //     SignalException(DebugBreakPoint,instruction);
5392 //   }
5393 // }
5394
5395 // end-sanitize-cygnus-never
5396 // start-sanitize-cygnus-never
5397
5398 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5399 // // isn't yet reconized by this simulator.
5400 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5401 // *vr4100:
5402 // {
5403 //   unsigned32 instruction = instruction_0;
5404 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5405 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5406 //   {
5407 //     CHECKHILO("Multiply-Add");
5408 //     {
5409 //       unsigned64 temp = (op1 * op2);
5410 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5411 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5412 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5413 //     }
5414 //   }
5415 // }
5416
5417 // end-sanitize-cygnus-never
5418 // start-sanitize-cygnus-never
5419
5420 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5421 // // isn't yet reconized by this simulator.
5422 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5423 // *vr4100:
5424 // {
5425 //   unsigned32 instruction = instruction_0;
5426 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5427 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5428 //   {
5429 //     CHECKHILO("Multiply-Add");
5430 //     {
5431 //       unsigned64 temp = (op1 * op2);
5432 //       LO = LO + temp;
5433 //     }
5434 //   }
5435 // }
5436
5437 // end-sanitize-cygnus-never