4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator are defined below.
35 // When placing models in the instruction descriptions, please place
36 // them one per line, in the order given here.
40 // Instructions and related functions for these models are included in
42 :model:::mipsI:mips3000:
43 :model:::mipsII:mips6000:
44 :model:::mipsIII:mips4000:
45 :model:::mipsIV:mips8000:
46 :model:::mipsV:mipsisaV:
47 :model:::mips32:mipsisa32:
48 :model:::mips32r2:mipsisa32r2:
49 :model:::mips64:mipsisa64:
50 :model:::mips64r2:mipsisa64r2:
54 // Standard MIPS ISA instructions used for these models are listed here,
55 // as are functions needed by those standard instructions. Instructions
56 // which are model-dependent and which are not in the standard MIPS ISAs
57 // (or which pre-date or use different encodings than the standard
58 // instructions) are (for the most part) in separate .igen files.
59 :model:::vr4100:mips4100: // vr.igen
60 :model:::vr4120:mips4120:
61 :model:::vr5000:mips5000:
62 :model:::vr5400:mips5400:
63 :model:::vr5500:mips5500:
64 :model:::r3900:mips3900: // tx.igen
66 // MIPS Application Specific Extensions (ASEs)
68 // Instructions for the ASEs are in separate .igen files.
69 // ASEs add instructions on to a base ISA.
70 :model:::mips16:mips16: // m16.igen (and m16.dc)
71 :model:::mips16e:mips16e: // m16e.igen
72 :model:::mips3d:mips3d: // mips3d.igen
73 :model:::mdmx:mdmx: // mdmx.igen
74 :model:::dsp:dsp: // dsp.igen
75 :model:::smartmips:smartmips: // smartmips.igen
79 // Instructions specific to these extensions are in separate .igen files.
80 // Extensions add instructions on to a base ISA.
81 :model:::sb1:sb1: // sb1.igen
84 // Pseudo instructions known by IGEN
87 SignalException (ReservedInstruction, 0);
91 // Pseudo instructions known by interp.c
92 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
93 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
96 SignalException (ReservedInstruction, instruction_0);
103 // Simulate a 32 bit delayslot instruction
106 :function:::address_word:delayslot32:address_word target
108 instruction_word delay_insn;
109 sim_events_slip (SD, 1);
111 CIA = CIA + 4; /* NOTE not mips16 */
112 STATE |= simDELAYSLOT;
113 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
114 ENGINE_ISSUE_PREFIX_HOOK();
115 idecode_issue (CPU_, delay_insn, (CIA));
116 STATE &= ~simDELAYSLOT;
120 :function:::address_word:nullify_next_insn32:
122 sim_events_slip (SD, 1);
123 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
130 // Calculate an effective address given a base and an offset.
133 :function:::address_word:loadstore_ea:address_word base, address_word offset
145 return base + offset;
148 :function:::address_word:loadstore_ea:address_word base, address_word offset
152 #if 0 /* XXX FIXME: enable this only after some additional testing. */
153 /* If in user mode and UX is not set, use 32-bit compatibility effective
154 address computations as defined in the MIPS64 Architecture for
155 Programmers Volume III, Revision 0.95, section 4.9. */
156 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
157 == (ksu_user << status_KSU_shift))
158 return (address_word)((signed32)base + (signed32)offset);
160 return base + offset;
166 // Check that a 32-bit register value is properly sign-extended.
167 // (See NotWordValue in ISA spec.)
170 :function:::int:not_word_value:unsigned_word value
180 /* For historical simulator compatibility (until documentation is
181 found that makes these operations unpredictable on some of these
182 architectures), this check never returns true. */
186 :function:::int:not_word_value:unsigned_word value
190 /* On MIPS32, since registers are 32-bits, there's no check to be done. */
194 :function:::int:not_word_value:unsigned_word value
198 return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
204 // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
205 // theoretically portable code which invokes non-portable behaviour from
206 // running with no indication of the portability issue.
207 // (See definition of UNPREDICTABLE in ISA spec.)
210 :function:::void:unpredictable:
222 :function:::void:unpredictable:
228 unpredictable_action (CPU, CIA);
234 // Check that an access to a HI/LO register meets timing requirements
238 // OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
239 // makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
241 // The following restrictions exist for MIPS I - MIPS III:
243 // MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
244 // in between makes MF UNPREDICTABLE. (2)
246 // MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
247 // in between makes MF UNPREDICTABLE. (3)
249 // On the r3900, restriction (2) is not present, and restriction (3) is not
250 // present for multiplication.
252 // Unfortunately, there seems to be some confusion about whether the last
253 // two restrictions should apply to "MIPS IV" as well. One edition of
254 // the MIPS IV ISA says they do, but references in later ISA documents
255 // suggest they don't.
257 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
258 // these restrictions, while others, like the VR5500, don't. To accomodate
259 // such differences, the MIPS IV and MIPS V version of these helper functions
260 // use auxillary routines to determine whether the restriction applies.
264 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
265 // to check for restrictions (2) and (3) above.
267 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
269 if (history->mf.timestamp + 3 > time)
271 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
272 itable[MY_INDEX].name,
274 (long) history->mf.cia);
283 // Check for restriction (2) above (for ISAs/processors that have it),
284 // and record timestamps for restriction (1) above.
286 :function:::int:check_mt_hilo:hilo_history *history
293 signed64 time = sim_events_time (SD);
294 int ok = check_mf_cycles (SD_, history, time, "MT");
295 history->mt.timestamp = time;
296 history->mt.cia = CIA;
300 :function:::int:check_mt_hilo:hilo_history *history
304 signed64 time = sim_events_time (SD);
305 int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
306 || check_mf_cycles (SD_, history, time, "MT"));
307 history->mt.timestamp = time;
308 history->mt.cia = CIA;
312 :function:::int:check_mt_hilo:hilo_history *history
319 signed64 time = sim_events_time (SD);
320 history->mt.timestamp = time;
321 history->mt.cia = CIA;
328 // Check for restriction (1) above, and record timestamps for
329 // restriction (2) and (3) above.
331 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
345 signed64 time = sim_events_time (SD);
348 && peer->mt.timestamp > history->op.timestamp
349 && history->mt.timestamp < history->op.timestamp
350 && ! (history->mf.timestamp > history->op.timestamp
351 && history->mf.timestamp < peer->mt.timestamp)
352 && ! (peer->mf.timestamp > history->op.timestamp
353 && peer->mf.timestamp < peer->mt.timestamp))
355 /* The peer has been written to since the last OP yet we have
357 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
358 itable[MY_INDEX].name,
360 (long) history->op.cia,
361 (long) peer->mt.cia);
364 history->mf.timestamp = time;
365 history->mf.cia = CIA;
373 // Check for restriction (3) above (for ISAs/processors that have it)
374 // for MULT ops, and record timestamps for restriction (1) above.
376 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
383 signed64 time = sim_events_time (SD);
384 int ok = (check_mf_cycles (SD_, hi, time, "OP")
385 && check_mf_cycles (SD_, lo, time, "OP"));
386 hi->op.timestamp = time;
387 lo->op.timestamp = time;
393 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
397 signed64 time = sim_events_time (SD);
398 int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
399 || (check_mf_cycles (SD_, hi, time, "OP")
400 && check_mf_cycles (SD_, lo, time, "OP")));
401 hi->op.timestamp = time;
402 lo->op.timestamp = time;
408 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
415 /* FIXME: could record the fact that a stall occured if we want */
416 signed64 time = sim_events_time (SD);
417 hi->op.timestamp = time;
418 lo->op.timestamp = time;
427 // Check for restriction (3) above (for ISAs/processors that have it)
428 // for DIV ops, and record timestamps for restriction (1) above.
430 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
438 signed64 time = sim_events_time (SD);
439 int ok = (check_mf_cycles (SD_, hi, time, "OP")
440 && check_mf_cycles (SD_, lo, time, "OP"));
441 hi->op.timestamp = time;
442 lo->op.timestamp = time;
448 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
452 signed64 time = sim_events_time (SD);
453 int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
454 || (check_mf_cycles (SD_, hi, time, "OP")
455 && check_mf_cycles (SD_, lo, time, "OP")));
456 hi->op.timestamp = time;
457 lo->op.timestamp = time;
463 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
469 signed64 time = sim_events_time (SD);
470 hi->op.timestamp = time;
471 lo->op.timestamp = time;
480 // Check that the 64-bit instruction can currently be used, and signal
481 // a ReservedInstruction exception if not.
484 :function:::void:check_u64:instruction_word insn
493 // The check should be similar to mips64 for any with PX/UX bit equivalents.
496 :function:::void:check_u64:instruction_word insn
501 #if 0 /* XXX FIXME: enable this only after some additional testing. */
502 if (UserMode && (SR & (status_UX|status_PX)) == 0)
503 SignalException (ReservedInstruction, insn);
510 // MIPS Architecture:
512 // CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
517 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
518 "add r<RD>, r<RS>, r<RT>"
532 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
534 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
536 ALU32_BEGIN (GPR[RS]);
538 ALU32_END (GPR[RD]); /* This checks for overflow. */
540 TRACE_ALU_RESULT (GPR[RD]);
545 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
546 "addi r<RT>, r<RS>, <IMMEDIATE>"
560 if (NotWordValue (GPR[RS]))
562 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
564 ALU32_BEGIN (GPR[RS]);
565 ALU32_ADD (EXTEND16 (IMMEDIATE));
566 ALU32_END (GPR[RT]); /* This checks for overflow. */
568 TRACE_ALU_RESULT (GPR[RT]);
573 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
575 if (NotWordValue (GPR[rs]))
577 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
578 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
579 TRACE_ALU_RESULT (GPR[rt]);
582 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
583 "addiu r<RT>, r<RS>, <IMMEDIATE>"
597 do_addiu (SD_, RS, RT, IMMEDIATE);
602 :function:::void:do_addu:int rs, int rt, int rd
604 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
606 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
607 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
608 TRACE_ALU_RESULT (GPR[rd]);
611 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
612 "addu r<RD>, r<RS>, r<RT>"
626 do_addu (SD_, RS, RT, RD);
631 :function:::void:do_and:int rs, int rt, int rd
633 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
634 GPR[rd] = GPR[rs] & GPR[rt];
635 TRACE_ALU_RESULT (GPR[rd]);
638 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
639 "and r<RD>, r<RS>, r<RT>"
653 do_and (SD_, RS, RT, RD);
658 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
659 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
673 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
674 GPR[RT] = GPR[RS] & IMMEDIATE;
675 TRACE_ALU_RESULT (GPR[RT]);
680 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
681 "beq r<RS>, r<RT>, <OFFSET>"
695 address_word offset = EXTEND16 (OFFSET) << 2;
696 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
698 DELAY_SLOT (NIA + offset);
704 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
705 "beql r<RS>, r<RT>, <OFFSET>"
718 address_word offset = EXTEND16 (OFFSET) << 2;
719 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
721 DELAY_SLOT (NIA + offset);
724 NULLIFY_NEXT_INSTRUCTION ();
729 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
730 "bgez r<RS>, <OFFSET>"
744 address_word offset = EXTEND16 (OFFSET) << 2;
745 if ((signed_word) GPR[RS] >= 0)
747 DELAY_SLOT (NIA + offset);
753 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
754 "bgezal r<RS>, <OFFSET>"
768 address_word offset = EXTEND16 (OFFSET) << 2;
772 if ((signed_word) GPR[RS] >= 0)
774 DELAY_SLOT (NIA + offset);
780 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
781 "bgezall r<RS>, <OFFSET>"
794 address_word offset = EXTEND16 (OFFSET) << 2;
798 /* NOTE: The branch occurs AFTER the next instruction has been
800 if ((signed_word) GPR[RS] >= 0)
802 DELAY_SLOT (NIA + offset);
805 NULLIFY_NEXT_INSTRUCTION ();
810 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
811 "bgezl r<RS>, <OFFSET>"
824 address_word offset = EXTEND16 (OFFSET) << 2;
825 if ((signed_word) GPR[RS] >= 0)
827 DELAY_SLOT (NIA + offset);
830 NULLIFY_NEXT_INSTRUCTION ();
835 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
836 "bgtz r<RS>, <OFFSET>"
850 address_word offset = EXTEND16 (OFFSET) << 2;
851 if ((signed_word) GPR[RS] > 0)
853 DELAY_SLOT (NIA + offset);
859 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
860 "bgtzl r<RS>, <OFFSET>"
873 address_word offset = EXTEND16 (OFFSET) << 2;
874 /* NOTE: The branch occurs AFTER the next instruction has been
876 if ((signed_word) GPR[RS] > 0)
878 DELAY_SLOT (NIA + offset);
881 NULLIFY_NEXT_INSTRUCTION ();
886 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
887 "blez r<RS>, <OFFSET>"
901 address_word offset = EXTEND16 (OFFSET) << 2;
902 /* NOTE: The branch occurs AFTER the next instruction has been
904 if ((signed_word) GPR[RS] <= 0)
906 DELAY_SLOT (NIA + offset);
912 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
913 "bgezl r<RS>, <OFFSET>"
926 address_word offset = EXTEND16 (OFFSET) << 2;
927 if ((signed_word) GPR[RS] <= 0)
929 DELAY_SLOT (NIA + offset);
932 NULLIFY_NEXT_INSTRUCTION ();
937 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
938 "bltz r<RS>, <OFFSET>"
952 address_word offset = EXTEND16 (OFFSET) << 2;
953 if ((signed_word) GPR[RS] < 0)
955 DELAY_SLOT (NIA + offset);
961 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
962 "bltzal r<RS>, <OFFSET>"
976 address_word offset = EXTEND16 (OFFSET) << 2;
980 /* NOTE: The branch occurs AFTER the next instruction has been
982 if ((signed_word) GPR[RS] < 0)
984 DELAY_SLOT (NIA + offset);
990 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
991 "bltzall r<RS>, <OFFSET>"
1004 address_word offset = EXTEND16 (OFFSET) << 2;
1008 if ((signed_word) GPR[RS] < 0)
1010 DELAY_SLOT (NIA + offset);
1013 NULLIFY_NEXT_INSTRUCTION ();
1018 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1019 "bltzl r<RS>, <OFFSET>"
1032 address_word offset = EXTEND16 (OFFSET) << 2;
1033 /* NOTE: The branch occurs AFTER the next instruction has been
1035 if ((signed_word) GPR[RS] < 0)
1037 DELAY_SLOT (NIA + offset);
1040 NULLIFY_NEXT_INSTRUCTION ();
1045 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1046 "bne r<RS>, r<RT>, <OFFSET>"
1060 address_word offset = EXTEND16 (OFFSET) << 2;
1061 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1063 DELAY_SLOT (NIA + offset);
1069 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1070 "bnel r<RS>, r<RT>, <OFFSET>"
1083 address_word offset = EXTEND16 (OFFSET) << 2;
1084 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1086 DELAY_SLOT (NIA + offset);
1089 NULLIFY_NEXT_INSTRUCTION ();
1094 000000,20.CODE,001101:SPECIAL:32::BREAK
1109 /* Check for some break instruction which are reserved for use by the simulator. */
1110 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1111 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1112 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1114 sim_engine_halt (SD, CPU, NULL, cia,
1115 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1117 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1118 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1120 if (STATE & simDELAYSLOT)
1121 PC = cia - 4; /* reference the branch instruction */
1124 SignalException (BreakPoint, instruction_0);
1129 /* If we get this far, we're not an instruction reserved by the sim. Raise
1131 SignalException (BreakPoint, instruction_0);
1137 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1145 unsigned32 temp = GPR[RS];
1149 if (NotWordValue (GPR[RS]))
1151 TRACE_ALU_INPUT1 (GPR[RS]);
1152 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1154 if ((temp & mask) == 0)
1158 GPR[RD] = EXTEND32 (i);
1159 TRACE_ALU_RESULT (GPR[RD]);
1164 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1172 unsigned32 temp = GPR[RS];
1176 if (NotWordValue (GPR[RS]))
1178 TRACE_ALU_INPUT1 (GPR[RS]);
1179 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1181 if ((temp & mask) != 0)
1185 GPR[RD] = EXTEND32 (i);
1186 TRACE_ALU_RESULT (GPR[RD]);
1191 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1192 "dadd r<RD>, r<RS>, r<RT>"
1201 check_u64 (SD_, instruction_0);
1202 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1204 ALU64_BEGIN (GPR[RS]);
1205 ALU64_ADD (GPR[RT]);
1206 ALU64_END (GPR[RD]); /* This checks for overflow. */
1208 TRACE_ALU_RESULT (GPR[RD]);
1213 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1214 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1223 check_u64 (SD_, instruction_0);
1224 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1226 ALU64_BEGIN (GPR[RS]);
1227 ALU64_ADD (EXTEND16 (IMMEDIATE));
1228 ALU64_END (GPR[RT]); /* This checks for overflow. */
1230 TRACE_ALU_RESULT (GPR[RT]);
1235 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1237 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1238 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1239 TRACE_ALU_RESULT (GPR[rt]);
1242 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1243 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1252 check_u64 (SD_, instruction_0);
1253 do_daddiu (SD_, RS, RT, IMMEDIATE);
1258 :function:::void:do_daddu:int rs, int rt, int rd
1260 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1261 GPR[rd] = GPR[rs] + GPR[rt];
1262 TRACE_ALU_RESULT (GPR[rd]);
1265 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1266 "daddu r<RD>, r<RS>, r<RT>"
1275 check_u64 (SD_, instruction_0);
1276 do_daddu (SD_, RS, RT, RD);
1281 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1287 unsigned64 temp = GPR[RS];
1290 check_u64 (SD_, instruction_0);
1293 TRACE_ALU_INPUT1 (GPR[RS]);
1294 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1296 if ((temp & mask) == 0)
1300 GPR[RD] = EXTEND32 (i);
1301 TRACE_ALU_RESULT (GPR[RD]);
1306 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1312 unsigned64 temp = GPR[RS];
1315 check_u64 (SD_, instruction_0);
1318 TRACE_ALU_INPUT1 (GPR[RS]);
1319 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1321 if ((temp & mask) != 0)
1325 GPR[RD] = EXTEND32 (i);
1326 TRACE_ALU_RESULT (GPR[RD]);
1331 :function:::void:do_ddiv:int rs, int rt
1333 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1334 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1336 signed64 n = GPR[rs];
1337 signed64 d = GPR[rt];
1342 lo = SIGNED64 (0x8000000000000000);
1345 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1347 lo = SIGNED64 (0x8000000000000000);
1358 TRACE_ALU_RESULT2 (HI, LO);
1361 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1371 check_u64 (SD_, instruction_0);
1372 do_ddiv (SD_, RS, RT);
1377 :function:::void:do_ddivu:int rs, int rt
1379 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1380 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1382 unsigned64 n = GPR[rs];
1383 unsigned64 d = GPR[rt];
1388 lo = SIGNED64 (0x8000000000000000);
1399 TRACE_ALU_RESULT2 (HI, LO);
1402 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1403 "ddivu r<RS>, r<RT>"
1412 check_u64 (SD_, instruction_0);
1413 do_ddivu (SD_, RS, RT);
1416 :function:::void:do_div:int rs, int rt
1418 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1419 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1421 signed32 n = GPR[rs];
1422 signed32 d = GPR[rt];
1425 LO = EXTEND32 (0x80000000);
1428 else if (n == SIGNED32 (0x80000000) && d == -1)
1430 LO = EXTEND32 (0x80000000);
1435 LO = EXTEND32 (n / d);
1436 HI = EXTEND32 (n % d);
1439 TRACE_ALU_RESULT2 (HI, LO);
1442 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1457 do_div (SD_, RS, RT);
1462 :function:::void:do_divu:int rs, int rt
1464 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1465 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1467 unsigned32 n = GPR[rs];
1468 unsigned32 d = GPR[rt];
1471 LO = EXTEND32 (0x80000000);
1476 LO = EXTEND32 (n / d);
1477 HI = EXTEND32 (n % d);
1480 TRACE_ALU_RESULT2 (HI, LO);
1483 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1498 do_divu (SD_, RS, RT);
1502 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1512 unsigned64 op1 = GPR[rs];
1513 unsigned64 op2 = GPR[rt];
1514 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1515 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1516 /* make signed multiply unsigned */
1520 if ((signed64) op1 < 0)
1525 if ((signed64) op2 < 0)
1531 /* multiply out the 4 sub products */
1532 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1533 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1534 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1535 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1536 /* add the products */
1537 mid = ((unsigned64) VH4_8 (m00)
1538 + (unsigned64) VL4_8 (m10)
1539 + (unsigned64) VL4_8 (m01));
1540 lo = U8_4 (mid, m00);
1542 + (unsigned64) VH4_8 (mid)
1543 + (unsigned64) VH4_8 (m01)
1544 + (unsigned64) VH4_8 (m10));
1554 /* save the result HI/LO (and a gpr) */
1559 TRACE_ALU_RESULT2 (HI, LO);
1562 :function:::void:do_dmult:int rs, int rt, int rd
1564 do_dmultx (SD_, rs, rt, rd, 1);
1567 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1568 "dmult r<RS>, r<RT>"
1576 check_u64 (SD_, instruction_0);
1577 do_dmult (SD_, RS, RT, 0);
1580 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1581 "dmult r<RS>, r<RT>":RD == 0
1582 "dmult r<RD>, r<RS>, r<RT>"
1585 check_u64 (SD_, instruction_0);
1586 do_dmult (SD_, RS, RT, RD);
1591 :function:::void:do_dmultu:int rs, int rt, int rd
1593 do_dmultx (SD_, rs, rt, rd, 0);
1596 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1597 "dmultu r<RS>, r<RT>"
1605 check_u64 (SD_, instruction_0);
1606 do_dmultu (SD_, RS, RT, 0);
1609 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1610 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1611 "dmultu r<RS>, r<RT>"
1614 check_u64 (SD_, instruction_0);
1615 do_dmultu (SD_, RS, RT, RD);
1619 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1624 TRACE_ALU_INPUT2 (x, y);
1625 result = ROTR64 (x, y);
1626 TRACE_ALU_RESULT (result);
1630 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1631 "dror r<RD>, r<RT>, <SHIFT>"
1636 check_u64 (SD_, instruction_0);
1637 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1640 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1641 "dror32 r<RD>, r<RT>, <SHIFT>"
1646 check_u64 (SD_, instruction_0);
1647 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1650 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1651 "drorv r<RD>, r<RT>, r<RS>"
1656 check_u64 (SD_, instruction_0);
1657 GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1661 :function:::void:do_dsll:int rt, int rd, int shift
1663 TRACE_ALU_INPUT2 (GPR[rt], shift);
1664 GPR[rd] = GPR[rt] << shift;
1665 TRACE_ALU_RESULT (GPR[rd]);
1668 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1669 "dsll r<RD>, r<RT>, <SHIFT>"
1678 check_u64 (SD_, instruction_0);
1679 do_dsll (SD_, RT, RD, SHIFT);
1683 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1684 "dsll32 r<RD>, r<RT>, <SHIFT>"
1694 check_u64 (SD_, instruction_0);
1695 TRACE_ALU_INPUT2 (GPR[RT], s);
1696 GPR[RD] = GPR[RT] << s;
1697 TRACE_ALU_RESULT (GPR[RD]);
1700 :function:::void:do_dsllv:int rs, int rt, int rd
1702 int s = MASKED64 (GPR[rs], 5, 0);
1703 TRACE_ALU_INPUT2 (GPR[rt], s);
1704 GPR[rd] = GPR[rt] << s;
1705 TRACE_ALU_RESULT (GPR[rd]);
1708 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1709 "dsllv r<RD>, r<RT>, r<RS>"
1718 check_u64 (SD_, instruction_0);
1719 do_dsllv (SD_, RS, RT, RD);
1722 :function:::void:do_dsra:int rt, int rd, int shift
1724 TRACE_ALU_INPUT2 (GPR[rt], shift);
1725 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1726 TRACE_ALU_RESULT (GPR[rd]);
1730 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1731 "dsra r<RD>, r<RT>, <SHIFT>"
1740 check_u64 (SD_, instruction_0);
1741 do_dsra (SD_, RT, RD, SHIFT);
1745 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1746 "dsra32 r<RD>, r<RT>, <SHIFT>"
1756 check_u64 (SD_, instruction_0);
1757 TRACE_ALU_INPUT2 (GPR[RT], s);
1758 GPR[RD] = ((signed64) GPR[RT]) >> s;
1759 TRACE_ALU_RESULT (GPR[RD]);
1763 :function:::void:do_dsrav:int rs, int rt, int rd
1765 int s = MASKED64 (GPR[rs], 5, 0);
1766 TRACE_ALU_INPUT2 (GPR[rt], s);
1767 GPR[rd] = ((signed64) GPR[rt]) >> s;
1768 TRACE_ALU_RESULT (GPR[rd]);
1771 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1772 "dsrav r<RD>, r<RT>, r<RS>"
1781 check_u64 (SD_, instruction_0);
1782 do_dsrav (SD_, RS, RT, RD);
1785 :function:::void:do_dsrl:int rt, int rd, int shift
1787 TRACE_ALU_INPUT2 (GPR[rt], shift);
1788 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1789 TRACE_ALU_RESULT (GPR[rd]);
1793 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1794 "dsrl r<RD>, r<RT>, <SHIFT>"
1803 check_u64 (SD_, instruction_0);
1804 do_dsrl (SD_, RT, RD, SHIFT);
1808 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1809 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1819 check_u64 (SD_, instruction_0);
1820 TRACE_ALU_INPUT2 (GPR[RT], s);
1821 GPR[RD] = (unsigned64) GPR[RT] >> s;
1822 TRACE_ALU_RESULT (GPR[RD]);
1826 :function:::void:do_dsrlv:int rs, int rt, int rd
1828 int s = MASKED64 (GPR[rs], 5, 0);
1829 TRACE_ALU_INPUT2 (GPR[rt], s);
1830 GPR[rd] = (unsigned64) GPR[rt] >> s;
1831 TRACE_ALU_RESULT (GPR[rd]);
1836 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1837 "dsrlv r<RD>, r<RT>, r<RS>"
1846 check_u64 (SD_, instruction_0);
1847 do_dsrlv (SD_, RS, RT, RD);
1851 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1852 "dsub r<RD>, r<RS>, r<RT>"
1861 check_u64 (SD_, instruction_0);
1862 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1864 ALU64_BEGIN (GPR[RS]);
1865 ALU64_SUB (GPR[RT]);
1866 ALU64_END (GPR[RD]); /* This checks for overflow. */
1868 TRACE_ALU_RESULT (GPR[RD]);
1872 :function:::void:do_dsubu:int rs, int rt, int rd
1874 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1875 GPR[rd] = GPR[rs] - GPR[rt];
1876 TRACE_ALU_RESULT (GPR[rd]);
1879 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1880 "dsubu r<RD>, r<RS>, r<RT>"
1889 check_u64 (SD_, instruction_0);
1890 do_dsubu (SD_, RS, RT, RD);
1894 000010,26.INSTR_INDEX:NORMAL:32::J
1909 /* NOTE: The region used is that of the delay slot NIA and NOT the
1910 current instruction */
1911 address_word region = (NIA & MASK (63, 28));
1912 DELAY_SLOT (region | (INSTR_INDEX << 2));
1916 000011,26.INSTR_INDEX:NORMAL:32::JAL
1931 /* NOTE: The region used is that of the delay slot and NOT the
1932 current instruction */
1933 address_word region = (NIA & MASK (63, 28));
1935 DELAY_SLOT (region | (INSTR_INDEX << 2));
1938 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1939 "jalr r<RS>":RD == 31
1954 address_word temp = GPR[RS];
1960 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1975 DELAY_SLOT (GPR[RS]);
1979 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1981 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1982 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1983 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1990 vaddr = loadstore_ea (SD_, base, offset);
1991 if ((vaddr & access) != 0)
1993 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1995 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1996 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1997 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1998 byte = ((vaddr & mask) ^ bigendiancpu);
1999 return (memval >> (8 * byte));
2002 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2004 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2005 address_word reverseendian = (ReverseEndian ? -1 : 0);
2006 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2015 unsigned_word lhs_mask;
2018 vaddr = loadstore_ea (SD_, base, offset);
2019 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2020 paddr = (paddr ^ (reverseendian & mask));
2021 if (BigEndianMem == 0)
2022 paddr = paddr & ~access;
2024 /* compute where within the word/mem we are */
2025 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2026 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2027 nr_lhs_bits = 8 * byte + 8;
2028 nr_rhs_bits = 8 * access - 8 * byte;
2029 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2031 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2032 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2033 (long) ((unsigned64) paddr >> 32), (long) paddr,
2034 word, byte, nr_lhs_bits, nr_rhs_bits); */
2036 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2039 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2040 temp = (memval << nr_rhs_bits);
2044 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2045 temp = (memval >> nr_lhs_bits);
2047 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2048 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2050 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2051 (long) ((unsigned64) memval >> 32), (long) memval,
2052 (long) ((unsigned64) temp >> 32), (long) temp,
2053 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2054 (long) (rt >> 32), (long) rt); */
2058 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2060 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2061 address_word reverseendian = (ReverseEndian ? -1 : 0);
2062 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2069 vaddr = loadstore_ea (SD_, base, offset);
2070 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2071 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2072 paddr = (paddr ^ (reverseendian & mask));
2073 if (BigEndianMem != 0)
2074 paddr = paddr & ~access;
2075 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2076 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2077 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2078 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2079 (long) paddr, byte, (long) paddr, (long) memval); */
2081 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2083 rt |= (memval >> (8 * byte)) & screen;
2089 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2090 "lb r<RT>, <OFFSET>(r<BASE>)"
2104 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2108 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2109 "lbu r<RT>, <OFFSET>(r<BASE>)"
2123 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2127 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2128 "ld r<RT>, <OFFSET>(r<BASE>)"
2137 check_u64 (SD_, instruction_0);
2138 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2142 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2143 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2156 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2162 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2163 "ldl r<RT>, <OFFSET>(r<BASE>)"
2172 check_u64 (SD_, instruction_0);
2173 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2177 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2178 "ldr r<RT>, <OFFSET>(r<BASE>)"
2187 check_u64 (SD_, instruction_0);
2188 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2192 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2193 "lh r<RT>, <OFFSET>(r<BASE>)"
2207 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2211 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2212 "lhu r<RT>, <OFFSET>(r<BASE>)"
2226 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2230 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2231 "ll r<RT>, <OFFSET>(r<BASE>)"
2243 address_word base = GPR[BASE];
2244 address_word offset = EXTEND16 (OFFSET);
2246 address_word vaddr = loadstore_ea (SD_, base, offset);
2249 if ((vaddr & 3) != 0)
2251 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2255 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2257 unsigned64 memval = 0;
2258 unsigned64 memval1 = 0;
2259 unsigned64 mask = 0x7;
2260 unsigned int shift = 2;
2261 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2262 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2264 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2265 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2266 byte = ((vaddr & mask) ^ (bigend << shift));
2267 GPR[RT] = EXTEND32 (memval >> (8 * byte));
2275 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2276 "lld r<RT>, <OFFSET>(r<BASE>)"
2285 address_word base = GPR[BASE];
2286 address_word offset = EXTEND16 (OFFSET);
2287 check_u64 (SD_, instruction_0);
2289 address_word vaddr = loadstore_ea (SD_, base, offset);
2292 if ((vaddr & 7) != 0)
2294 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2298 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2300 unsigned64 memval = 0;
2301 unsigned64 memval1 = 0;
2302 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2311 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2312 "lui r<RT>, %#lx<IMMEDIATE>"
2326 TRACE_ALU_INPUT1 (IMMEDIATE);
2327 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2328 TRACE_ALU_RESULT (GPR[RT]);
2332 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2333 "lw r<RT>, <OFFSET>(r<BASE>)"
2347 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2351 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2352 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2366 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2370 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2371 "lwl r<RT>, <OFFSET>(r<BASE>)"
2385 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2389 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2390 "lwr r<RT>, <OFFSET>(r<BASE>)"
2404 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2408 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2409 "lwu r<RT>, <OFFSET>(r<BASE>)"
2418 check_u64 (SD_, instruction_0);
2419 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2424 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2433 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2434 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2436 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2437 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2438 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2439 LO = EXTEND32 (temp);
2440 HI = EXTEND32 (VH4_8 (temp));
2441 TRACE_ALU_RESULT2 (HI, LO);
2446 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2447 "maddu r<RS>, r<RT>"
2455 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2456 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2458 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2459 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2460 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2461 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
2462 LO = EXTEND32 (temp);
2463 HI = EXTEND32 (VH4_8 (temp));
2464 TRACE_ALU_RESULT2 (HI, LO);
2468 :function:::void:do_mfhi:int rd
2470 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2471 TRACE_ALU_INPUT1 (HI);
2473 TRACE_ALU_RESULT (GPR[rd]);
2476 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2492 :function:::void:do_mflo:int rd
2494 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2495 TRACE_ALU_INPUT1 (LO);
2497 TRACE_ALU_RESULT (GPR[rd]);
2500 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2516 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2517 "movn r<RD>, r<RS>, r<RT>"
2529 TRACE_ALU_RESULT (GPR[RD]);
2535 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2536 "movz r<RD>, r<RS>, r<RT>"
2548 TRACE_ALU_RESULT (GPR[RD]);
2554 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2563 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2564 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2566 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2567 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2568 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2569 LO = EXTEND32 (temp);
2570 HI = EXTEND32 (VH4_8 (temp));
2571 TRACE_ALU_RESULT2 (HI, LO);
2576 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2577 "msubu r<RS>, r<RT>"
2585 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2586 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2588 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2589 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2590 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2591 LO = EXTEND32 (temp);
2592 HI = EXTEND32 (VH4_8 (temp));
2593 TRACE_ALU_RESULT2 (HI, LO);
2598 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2609 check_mt_hilo (SD_, HIHISTORY);
2615 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2626 check_mt_hilo (SD_, LOHISTORY);
2632 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2633 "mul r<RD>, r<RS>, r<RT>"
2641 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2643 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2644 prod = (((signed64)(signed32) GPR[RS])
2645 * ((signed64)(signed32) GPR[RT]));
2646 GPR[RD] = EXTEND32 (VL4_8 (prod));
2647 TRACE_ALU_RESULT (GPR[RD]);
2652 :function:::void:do_mult:int rs, int rt, int rd
2655 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2656 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2658 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2659 prod = (((signed64)(signed32) GPR[rs])
2660 * ((signed64)(signed32) GPR[rt]));
2661 LO = EXTEND32 (VL4_8 (prod));
2662 HI = EXTEND32 (VH4_8 (prod));
2663 ACX = 0; /* SmartMIPS */
2666 TRACE_ALU_RESULT2 (HI, LO);
2669 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2682 do_mult (SD_, RS, RT, 0);
2686 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2687 "mult r<RS>, r<RT>":RD == 0
2688 "mult r<RD>, r<RS>, r<RT>"
2692 do_mult (SD_, RS, RT, RD);
2696 :function:::void:do_multu:int rs, int rt, int rd
2699 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2700 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2702 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2703 prod = (((unsigned64)(unsigned32) GPR[rs])
2704 * ((unsigned64)(unsigned32) GPR[rt]));
2705 LO = EXTEND32 (VL4_8 (prod));
2706 HI = EXTEND32 (VH4_8 (prod));
2709 TRACE_ALU_RESULT2 (HI, LO);
2712 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2713 "multu r<RS>, r<RT>"
2725 do_multu (SD_, RS, RT, 0);
2728 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2729 "multu r<RS>, r<RT>":RD == 0
2730 "multu r<RD>, r<RS>, r<RT>"
2734 do_multu (SD_, RS, RT, RD);
2738 :function:::void:do_nor:int rs, int rt, int rd
2740 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2741 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2742 TRACE_ALU_RESULT (GPR[rd]);
2745 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2746 "nor r<RD>, r<RS>, r<RT>"
2760 do_nor (SD_, RS, RT, RD);
2764 :function:::void:do_or:int rs, int rt, int rd
2766 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2767 GPR[rd] = (GPR[rs] | GPR[rt]);
2768 TRACE_ALU_RESULT (GPR[rd]);
2771 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2772 "or r<RD>, r<RS>, r<RT>"
2786 do_or (SD_, RS, RT, RD);
2791 :function:::void:do_ori:int rs, int rt, unsigned immediate
2793 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2794 GPR[rt] = (GPR[rs] | immediate);
2795 TRACE_ALU_RESULT (GPR[rt]);
2798 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2799 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2813 do_ori (SD_, RS, RT, IMMEDIATE);
2817 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2818 "pref <HINT>, <OFFSET>(r<BASE>)"
2827 address_word base = GPR[BASE];
2828 address_word offset = EXTEND16 (OFFSET);
2830 address_word vaddr = loadstore_ea (SD_, base, offset);
2834 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2835 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2841 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
2846 TRACE_ALU_INPUT2 (x, y);
2847 result = EXTEND32 (ROTR32 (x, y));
2848 TRACE_ALU_RESULT (result);
2852 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
2853 "ror r<RD>, r<RT>, <SHIFT>"
2860 GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
2863 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
2864 "rorv r<RD>, r<RT>, r<RS>"
2871 GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
2875 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2877 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2878 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2879 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2886 vaddr = loadstore_ea (SD_, base, offset);
2887 if ((vaddr & access) != 0)
2889 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2891 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2892 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2893 byte = ((vaddr & mask) ^ bigendiancpu);
2894 memval = (word << (8 * byte));
2895 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2898 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2900 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2901 address_word reverseendian = (ReverseEndian ? -1 : 0);
2902 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2912 vaddr = loadstore_ea (SD_, base, offset);
2913 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2914 paddr = (paddr ^ (reverseendian & mask));
2915 if (BigEndianMem == 0)
2916 paddr = paddr & ~access;
2918 /* compute where within the word/mem we are */
2919 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2920 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2921 nr_lhs_bits = 8 * byte + 8;
2922 nr_rhs_bits = 8 * access - 8 * byte;
2923 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2924 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2925 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2926 (long) ((unsigned64) paddr >> 32), (long) paddr,
2927 word, byte, nr_lhs_bits, nr_rhs_bits); */
2931 memval = (rt >> nr_rhs_bits);
2935 memval = (rt << nr_lhs_bits);
2937 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2938 (long) ((unsigned64) rt >> 32), (long) rt,
2939 (long) ((unsigned64) memval >> 32), (long) memval); */
2940 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2943 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2945 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2946 address_word reverseendian = (ReverseEndian ? -1 : 0);
2947 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2954 vaddr = loadstore_ea (SD_, base, offset);
2955 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2956 paddr = (paddr ^ (reverseendian & mask));
2957 if (BigEndianMem != 0)
2959 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2960 memval = (rt << (byte * 8));
2961 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2965 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2966 "sb r<RT>, <OFFSET>(r<BASE>)"
2980 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2984 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2985 "sc r<RT>, <OFFSET>(r<BASE>)"
2997 unsigned32 instruction = instruction_0;
2998 address_word base = GPR[BASE];
2999 address_word offset = EXTEND16 (OFFSET);
3001 address_word vaddr = loadstore_ea (SD_, base, offset);
3004 if ((vaddr & 3) != 0)
3006 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3010 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3012 unsigned64 memval = 0;
3013 unsigned64 memval1 = 0;
3014 unsigned64 mask = 0x7;
3016 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3017 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3018 memval = ((unsigned64) GPR[RT] << (8 * byte));
3021 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3030 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3031 "scd r<RT>, <OFFSET>(r<BASE>)"
3040 address_word base = GPR[BASE];
3041 address_word offset = EXTEND16 (OFFSET);
3042 check_u64 (SD_, instruction_0);
3044 address_word vaddr = loadstore_ea (SD_, base, offset);
3047 if ((vaddr & 7) != 0)
3049 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3053 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3055 unsigned64 memval = 0;
3056 unsigned64 memval1 = 0;
3060 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3069 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3070 "sd r<RT>, <OFFSET>(r<BASE>)"
3079 check_u64 (SD_, instruction_0);
3080 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3084 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3085 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3097 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3101 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3102 "sdl r<RT>, <OFFSET>(r<BASE>)"
3111 check_u64 (SD_, instruction_0);
3112 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3116 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3117 "sdr r<RT>, <OFFSET>(r<BASE>)"
3126 check_u64 (SD_, instruction_0);
3127 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3132 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3133 "sh r<RT>, <OFFSET>(r<BASE>)"
3147 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3151 :function:::void:do_sll:int rt, int rd, int shift
3153 unsigned32 temp = (GPR[rt] << shift);
3154 TRACE_ALU_INPUT2 (GPR[rt], shift);
3155 GPR[rd] = EXTEND32 (temp);
3156 TRACE_ALU_RESULT (GPR[rd]);
3159 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
3160 "nop":RD == 0 && RT == 0 && SHIFT == 0
3161 "sll r<RD>, r<RT>, <SHIFT>"
3171 /* Skip shift for NOP, so that there won't be lots of extraneous
3173 if (RD != 0 || RT != 0 || SHIFT != 0)
3174 do_sll (SD_, RT, RD, SHIFT);
3177 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3178 "nop":RD == 0 && RT == 0 && SHIFT == 0
3179 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
3180 "sll r<RD>, r<RT>, <SHIFT>"
3186 /* Skip shift for NOP and SSNOP, so that there won't be lots of
3187 extraneous trace output. */
3188 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3189 do_sll (SD_, RT, RD, SHIFT);
3193 :function:::void:do_sllv:int rs, int rt, int rd
3195 int s = MASKED (GPR[rs], 4, 0);
3196 unsigned32 temp = (GPR[rt] << s);
3197 TRACE_ALU_INPUT2 (GPR[rt], s);
3198 GPR[rd] = EXTEND32 (temp);
3199 TRACE_ALU_RESULT (GPR[rd]);
3202 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
3203 "sllv r<RD>, r<RT>, r<RS>"
3217 do_sllv (SD_, RS, RT, RD);
3221 :function:::void:do_slt:int rs, int rt, int rd
3223 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3224 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3225 TRACE_ALU_RESULT (GPR[rd]);
3228 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
3229 "slt r<RD>, r<RS>, r<RT>"
3243 do_slt (SD_, RS, RT, RD);
3247 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3249 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3250 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3251 TRACE_ALU_RESULT (GPR[rt]);
3254 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3255 "slti r<RT>, r<RS>, <IMMEDIATE>"
3269 do_slti (SD_, RS, RT, IMMEDIATE);
3273 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3275 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3276 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3277 TRACE_ALU_RESULT (GPR[rt]);
3280 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3281 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3295 do_sltiu (SD_, RS, RT, IMMEDIATE);
3300 :function:::void:do_sltu:int rs, int rt, int rd
3302 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3303 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3304 TRACE_ALU_RESULT (GPR[rd]);
3307 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3308 "sltu r<RD>, r<RS>, r<RT>"
3322 do_sltu (SD_, RS, RT, RD);
3326 :function:::void:do_sra:int rt, int rd, int shift
3328 signed32 temp = (signed32) GPR[rt] >> shift;
3329 if (NotWordValue (GPR[rt]))
3331 TRACE_ALU_INPUT2 (GPR[rt], shift);
3332 GPR[rd] = EXTEND32 (temp);
3333 TRACE_ALU_RESULT (GPR[rd]);
3336 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3337 "sra r<RD>, r<RT>, <SHIFT>"
3351 do_sra (SD_, RT, RD, SHIFT);
3356 :function:::void:do_srav:int rs, int rt, int rd
3358 int s = MASKED (GPR[rs], 4, 0);
3359 signed32 temp = (signed32) GPR[rt] >> s;
3360 if (NotWordValue (GPR[rt]))
3362 TRACE_ALU_INPUT2 (GPR[rt], s);
3363 GPR[rd] = EXTEND32 (temp);
3364 TRACE_ALU_RESULT (GPR[rd]);
3367 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3368 "srav r<RD>, r<RT>, r<RS>"
3382 do_srav (SD_, RS, RT, RD);
3387 :function:::void:do_srl:int rt, int rd, int shift
3389 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3390 if (NotWordValue (GPR[rt]))
3392 TRACE_ALU_INPUT2 (GPR[rt], shift);
3393 GPR[rd] = EXTEND32 (temp);
3394 TRACE_ALU_RESULT (GPR[rd]);
3397 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3398 "srl r<RD>, r<RT>, <SHIFT>"
3412 do_srl (SD_, RT, RD, SHIFT);
3416 :function:::void:do_srlv:int rs, int rt, int rd
3418 int s = MASKED (GPR[rs], 4, 0);
3419 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3420 if (NotWordValue (GPR[rt]))
3422 TRACE_ALU_INPUT2 (GPR[rt], s);
3423 GPR[rd] = EXTEND32 (temp);
3424 TRACE_ALU_RESULT (GPR[rd]);
3427 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3428 "srlv r<RD>, r<RT>, r<RS>"
3442 do_srlv (SD_, RS, RT, RD);
3446 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3447 "sub r<RD>, r<RS>, r<RT>"
3461 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3463 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3465 ALU32_BEGIN (GPR[RS]);
3466 ALU32_SUB (GPR[RT]);
3467 ALU32_END (GPR[RD]); /* This checks for overflow. */
3469 TRACE_ALU_RESULT (GPR[RD]);
3473 :function:::void:do_subu:int rs, int rt, int rd
3475 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3477 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3478 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3479 TRACE_ALU_RESULT (GPR[rd]);
3482 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3483 "subu r<RD>, r<RS>, r<RT>"
3497 do_subu (SD_, RS, RT, RD);
3501 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3502 "sw r<RT>, <OFFSET>(r<BASE>)"
3516 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3520 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3521 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3535 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3539 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3540 "swl r<RT>, <OFFSET>(r<BASE>)"
3554 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3558 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3559 "swr r<RT>, <OFFSET>(r<BASE>)"
3573 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3577 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3592 SyncOperation (STYPE);
3596 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3597 "syscall %#lx<CODE>"
3611 SignalException (SystemCall, instruction_0);
3615 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3628 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3629 SignalException (Trap, instruction_0);
3633 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3634 "teqi r<RS>, <IMMEDIATE>"
3646 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3647 SignalException (Trap, instruction_0);
3651 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3664 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3665 SignalException (Trap, instruction_0);
3669 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3670 "tgei r<RS>, <IMMEDIATE>"
3682 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3683 SignalException (Trap, instruction_0);
3687 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3688 "tgeiu r<RS>, <IMMEDIATE>"
3700 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3701 SignalException (Trap, instruction_0);
3705 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3718 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3719 SignalException (Trap, instruction_0);
3723 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3736 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3737 SignalException (Trap, instruction_0);
3741 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3742 "tlti r<RS>, <IMMEDIATE>"
3754 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3755 SignalException (Trap, instruction_0);
3759 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3760 "tltiu r<RS>, <IMMEDIATE>"
3772 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3773 SignalException (Trap, instruction_0);
3777 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3790 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3791 SignalException (Trap, instruction_0);
3795 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3808 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3809 SignalException (Trap, instruction_0);
3813 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3814 "tnei r<RS>, <IMMEDIATE>"
3826 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3827 SignalException (Trap, instruction_0);
3831 :function:::void:do_xor:int rs, int rt, int rd
3833 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3834 GPR[rd] = GPR[rs] ^ GPR[rt];
3835 TRACE_ALU_RESULT (GPR[rd]);
3838 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3839 "xor r<RD>, r<RS>, r<RT>"
3853 do_xor (SD_, RS, RT, RD);
3857 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3859 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3860 GPR[rt] = GPR[rs] ^ immediate;
3861 TRACE_ALU_RESULT (GPR[rt]);
3864 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3865 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3879 do_xori (SD_, RS, RT, IMMEDIATE);
3884 // MIPS Architecture:
3886 // FPU Instruction Set (COP1 & COP1X)
3894 case fmt_single: return "s";
3895 case fmt_double: return "d";
3896 case fmt_word: return "w";
3897 case fmt_long: return "l";
3898 case fmt_ps: return "ps";
3899 default: return "?";
3919 :%s::::COND:int cond
3923 case 00: return "f";
3924 case 01: return "un";
3925 case 02: return "eq";
3926 case 03: return "ueq";
3927 case 04: return "olt";
3928 case 05: return "ult";
3929 case 06: return "ole";
3930 case 07: return "ule";
3931 case 010: return "sf";
3932 case 011: return "ngle";
3933 case 012: return "seq";
3934 case 013: return "ngl";
3935 case 014: return "lt";
3936 case 015: return "nge";
3937 case 016: return "le";
3938 case 017: return "ngt";
3939 default: return "?";
3946 // Check that the given FPU format is usable, and signal a
3947 // ReservedInstruction exception if not.
3950 // check_fmt_p checks that the format is single, double, or paired single.
3951 :function:::void:check_fmt_p:int fmt, instruction_word insn
3962 /* None of these ISAs support Paired Single, so just fall back to
3963 the single/double check. */
3964 if ((fmt != fmt_single) && (fmt != fmt_double))
3965 SignalException (ReservedInstruction, insn);
3968 :function:::void:check_fmt_p:int fmt, instruction_word insn
3973 if ((fmt != fmt_single) && (fmt != fmt_double)
3974 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3975 SignalException (ReservedInstruction, insn);
3981 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3982 // exception if not.
3985 :function:::void:check_fpu:
3999 if (! COP_Usable (1))
4000 SignalExceptionCoProcessorUnusable (1);
4006 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
4007 // or MIPS32. do_load cannot be used instead because it returns an
4008 // unsigned_word, which is limited to the size of the machine's registers.
4011 :function:::unsigned64:do_load_double:address_word base, address_word offset
4016 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4023 vaddr = loadstore_ea (SD_, base, offset);
4024 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4026 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4027 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4028 sim_core_unaligned_signal);
4030 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4032 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4034 v = (unsigned64)memval;
4035 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4037 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4043 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4044 // or MIPS32. do_load cannot be used instead because it returns an
4045 // unsigned_word, which is limited to the size of the machine's registers.
4048 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4053 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4059 vaddr = loadstore_ea (SD_, base, offset);
4060 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4062 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4063 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4064 sim_core_unaligned_signal);
4066 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4068 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4069 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4071 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4072 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4077 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4078 "abs.%s<FMT> f<FD>, f<FS>"
4094 check_fmt_p (SD_, fmt, instruction_0);
4095 StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
4100 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4101 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4117 check_fmt_p (SD_, fmt, instruction_0);
4118 StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4122 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
4123 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4132 check_u64 (SD_, instruction_0);
4133 fs = ValueFPR (FS, fmt_ps);
4134 if ((GPR[RS] & 0x3) != 0)
4136 if ((GPR[RS] & 0x4) == 0)
4140 ft = ValueFPR (FT, fmt_ps);
4142 fd = PackPS (PSLower (fs), PSUpper (ft));
4144 fd = PackPS (PSLower (ft), PSUpper (fs));
4146 StoreFPR (FD, fmt_ps, fd);
4155 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4156 "bc1%s<TF>%s<ND> <OFFSET>"
4162 TRACE_BRANCH_INPUT (PREVCOC1());
4163 if (PREVCOC1() == TF)
4165 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4166 TRACE_BRANCH_RESULT (dest);
4171 TRACE_BRANCH_RESULT (0);
4172 NULLIFY_NEXT_INSTRUCTION ();
4176 TRACE_BRANCH_RESULT (NIA);
4180 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4181 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4182 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4194 if (GETFCC(CC) == TF)
4196 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4201 NULLIFY_NEXT_INSTRUCTION ();
4206 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
4207 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4214 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4215 TRACE_ALU_RESULT (ValueFCR (31));
4218 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
4219 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4220 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4233 check_fmt_p (SD_, fmt, instruction_0);
4234 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4235 TRACE_ALU_RESULT (ValueFCR (31));
4239 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
4240 "ceil.l.%s<FMT> f<FD>, f<FS>"
4252 StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4257 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
4258 "ceil.w.%s<FMT> f<FD>, f<FS>"
4273 StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4278 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4286 PENDING_FILL (RT, EXTEND32 (FCR0));
4288 PENDING_FILL (RT, EXTEND32 (FCR31));
4292 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4300 if (FS == 0 || FS == 31)
4302 unsigned_word fcr = ValueFCR (FS);
4303 TRACE_ALU_INPUT1 (fcr);
4307 TRACE_ALU_RESULT (GPR[RT]);
4310 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4319 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4321 unsigned_word fcr = ValueFCR (FS);
4322 TRACE_ALU_INPUT1 (fcr);
4326 TRACE_ALU_RESULT (GPR[RT]);
4329 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4337 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4341 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4349 TRACE_ALU_INPUT1 (GPR[RT]);
4351 StoreFCR (FS, GPR[RT]);
4355 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4364 TRACE_ALU_INPUT1 (GPR[RT]);
4365 if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4366 StoreFCR (FS, GPR[RT]);
4372 // FIXME: Does not correctly differentiate between mips*
4374 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4375 "cvt.d.%s<FMT> f<FD>, f<FS>"
4391 if ((fmt == fmt_double) | 0)
4392 SignalException (ReservedInstruction, instruction_0);
4393 StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4398 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4399 "cvt.l.%s<FMT> f<FD>, f<FS>"
4411 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4412 SignalException (ReservedInstruction, instruction_0);
4413 StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4418 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4419 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4425 check_u64 (SD_, instruction_0);
4426 StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4427 ValueFPR (FT, fmt_single)));
4432 // FIXME: Does not correctly differentiate between mips*
4434 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4435 "cvt.s.%s<FMT> f<FD>, f<FS>"
4451 if ((fmt == fmt_single) | 0)
4452 SignalException (ReservedInstruction, instruction_0);
4453 StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4458 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4459 "cvt.s.pl f<FD>, f<FS>"
4465 check_u64 (SD_, instruction_0);
4466 StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4470 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4471 "cvt.s.pu f<FD>, f<FS>"
4477 check_u64 (SD_, instruction_0);
4478 StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4482 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4483 "cvt.w.%s<FMT> f<FD>, f<FS>"
4499 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4500 SignalException (ReservedInstruction, instruction_0);
4501 StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4506 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4507 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4523 StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4527 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4528 "dmfc1 r<RT>, f<FS>"
4533 check_u64 (SD_, instruction_0);
4534 if (SizeFGR () == 64)
4536 else if ((FS & 0x1) == 0)
4537 v = SET64HI (FGR[FS+1]) | FGR[FS];
4539 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4540 PENDING_FILL (RT, v);
4541 TRACE_ALU_RESULT (v);
4544 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4545 "dmfc1 r<RT>, f<FS>"
4555 check_u64 (SD_, instruction_0);
4556 if (SizeFGR () == 64)
4558 else if ((FS & 0x1) == 0)
4559 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4561 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4562 TRACE_ALU_RESULT (GPR[RT]);
4566 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4567 "dmtc1 r<RT>, f<FS>"
4572 check_u64 (SD_, instruction_0);
4573 if (SizeFGR () == 64)
4574 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4575 else if ((FS & 0x1) == 0)
4577 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4578 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4582 TRACE_FP_RESULT (GPR[RT]);
4585 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4586 "dmtc1 r<RT>, f<FS>"
4596 check_u64 (SD_, instruction_0);
4597 if (SizeFGR () == 64)
4598 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4599 else if ((FS & 0x1) == 0)
4600 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4606 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4607 "floor.l.%s<FMT> f<FD>, f<FS>"
4619 StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4624 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4625 "floor.w.%s<FMT> f<FD>, f<FS>"
4640 StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4645 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4646 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4652 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4656 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4657 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4668 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4672 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4673 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4681 check_u64 (SD_, instruction_0);
4682 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4686 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4687 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4692 address_word base = GPR[BASE];
4693 address_word index = GPR[INDEX];
4694 address_word vaddr = base + index;
4696 check_u64 (SD_, instruction_0);
4697 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
4698 if ((vaddr & 0x7) != 0)
4699 index -= (vaddr & 0x7);
4700 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4704 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4705 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4720 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4724 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4725 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4733 check_u64 (SD_, instruction_0);
4734 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4739 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
4740 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4749 check_u64 (SD_, instruction_0);
4750 check_fmt_p (SD_, fmt, instruction_0);
4751 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4752 ValueFPR (FR, fmt), fmt));
4756 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4764 v = EXTEND32 (FGR[FS]);
4765 PENDING_FILL (RT, v);
4766 TRACE_ALU_RESULT (v);
4769 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4782 GPR[RT] = EXTEND32 (FGR[FS]);
4783 TRACE_ALU_RESULT (GPR[RT]);
4787 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4788 "mov.%s<FMT> f<FD>, f<FS>"
4804 check_fmt_p (SD_, fmt, instruction_0);
4805 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4811 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4812 "mov%s<TF> r<RD>, r<RS>, <CC>"
4822 if (GETFCC(CC) == TF)
4829 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4830 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4843 if (GETFCC(CC) == TF)
4844 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4846 StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
4851 fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4853 PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4855 StoreFPR (FD, fmt_ps, fd);
4860 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4861 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4872 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4874 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4881 // MOVT.fmt see MOVtf.fmt
4885 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4886 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4897 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4899 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4903 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
4904 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4913 check_u64 (SD_, instruction_0);
4914 check_fmt_p (SD_, fmt, instruction_0);
4915 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4916 ValueFPR (FR, fmt), fmt));
4920 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4927 if (SizeFGR () == 64)
4928 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4930 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4931 TRACE_FP_RESULT (GPR[RT]);
4934 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4947 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4951 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4952 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4968 check_fmt_p (SD_, fmt, instruction_0);
4969 StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4973 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4974 "neg.%s<FMT> f<FD>, f<FS>"
4990 check_fmt_p (SD_, fmt, instruction_0);
4991 StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4995 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
4996 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5005 check_u64 (SD_, instruction_0);
5006 check_fmt_p (SD_, fmt, instruction_0);
5007 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5008 ValueFPR (FR, fmt), fmt));
5012 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
5013 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5022 check_u64 (SD_, instruction_0);
5023 check_fmt_p (SD_, fmt, instruction_0);
5024 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5025 ValueFPR (FR, fmt), fmt));
5029 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
5030 "pll.ps f<FD>, f<FS>, f<FT>"
5036 check_u64 (SD_, instruction_0);
5037 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5038 PSLower (ValueFPR (FT, fmt_ps))));
5042 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
5043 "plu.ps f<FD>, f<FS>, f<FT>"
5049 check_u64 (SD_, instruction_0);
5050 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5051 PSUpper (ValueFPR (FT, fmt_ps))));
5055 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
5056 "prefx <HINT>, r<INDEX>(r<BASE>)"
5063 address_word base = GPR[BASE];
5064 address_word index = GPR[INDEX];
5066 address_word vaddr = loadstore_ea (SD_, base, index);
5069 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5070 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
5075 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
5076 "pul.ps f<FD>, f<FS>, f<FT>"
5082 check_u64 (SD_, instruction_0);
5083 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5084 PSLower (ValueFPR (FT, fmt_ps))));
5088 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
5089 "puu.ps f<FD>, f<FS>, f<FT>"
5095 check_u64 (SD_, instruction_0);
5096 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5097 PSUpper (ValueFPR (FT, fmt_ps))));
5101 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
5102 "recip.%s<FMT> f<FD>, f<FS>"
5111 StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
5115 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
5116 "round.l.%s<FMT> f<FD>, f<FS>"
5128 StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5133 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
5134 "round.w.%s<FMT> f<FD>, f<FS>"
5149 StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5154 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
5155 "rsqrt.%s<FMT> f<FD>, f<FS>"
5164 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
5168 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
5169 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5175 do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5179 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5180 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5191 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5195 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
5196 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5204 check_u64 (SD_, instruction_0);
5205 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5209 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5210 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5216 address_word base = GPR[BASE];
5217 address_word index = GPR[INDEX];
5218 address_word vaddr = base + index;
5220 check_u64 (SD_, instruction_0);
5221 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
5222 if ((vaddr & 0x7) != 0)
5223 index -= (vaddr & 0x7);
5224 do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5228 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
5229 "sqrt.%s<FMT> f<FD>, f<FS>"
5244 StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
5248 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
5249 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5265 check_fmt_p (SD_, fmt, instruction_0);
5266 StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5271 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
5272 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5286 address_word base = GPR[BASE];
5287 address_word offset = EXTEND16 (OFFSET);
5290 address_word vaddr = loadstore_ea (SD_, base, offset);
5293 if ((vaddr & 3) != 0)
5295 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5299 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5302 uword64 memval1 = 0;
5303 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5304 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5305 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5307 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5308 byte = ((vaddr & mask) ^ bigendiancpu);
5309 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
5310 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5317 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
5318 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5326 address_word base = GPR[BASE];
5327 address_word index = GPR[INDEX];
5329 check_u64 (SD_, instruction_0);
5331 address_word vaddr = loadstore_ea (SD_, base, index);
5334 if ((vaddr & 3) != 0)
5336 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5340 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5342 unsigned64 memval = 0;
5343 unsigned64 memval1 = 0;
5344 unsigned64 mask = 0x7;
5346 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5347 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5348 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
5350 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5358 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
5359 "trunc.l.%s<FMT> f<FD>, f<FS>"
5371 StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5376 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
5377 "trunc.w.%s<FMT> f<FD>, f<FS>"
5392 StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5398 // MIPS Architecture:
5400 // System Control Instruction Set (COP0)
5404 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5418 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5420 // stub needed for eCos as tx39 hardware bug workaround
5427 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5442 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5456 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5471 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5472 "cache <OP>, <OFFSET>(r<BASE>)"
5484 address_word base = GPR[BASE];
5485 address_word offset = EXTEND16 (OFFSET);
5487 address_word vaddr = loadstore_ea (SD_, base, offset);
5490 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5491 CacheOp(OP,vaddr,paddr,instruction_0);
5496 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5497 "dmfc0 r<RT>, r<RD>"
5504 check_u64 (SD_, instruction_0);
5505 DecodeCoproc (instruction_0);
5509 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5510 "dmtc0 r<RT>, r<RD>"
5517 check_u64 (SD_, instruction_0);
5518 DecodeCoproc (instruction_0);
5522 010000,1,0000000000000000000,011000:COP0:32::ERET
5534 if (SR & status_ERL)
5536 /* Oops, not yet available */
5537 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5549 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5550 "mfc0 r<RT>, r<RD> # <REGX>"
5564 TRACE_ALU_INPUT0 ();
5565 DecodeCoproc (instruction_0);
5566 TRACE_ALU_RESULT (GPR[RT]);
5569 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5570 "mtc0 r<RT>, r<RD> # <REGX>"
5584 DecodeCoproc (instruction_0);
5588 010000,1,0000000000000000000,010000:COP0:32::RFE
5599 DecodeCoproc (instruction_0);
5603 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5604 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5617 DecodeCoproc (instruction_0);
5622 010000,1,0000000000000000000,001000:COP0:32::TLBP
5637 010000,1,0000000000000000000,000001:COP0:32::TLBR
5652 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5667 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5682 :include:::mips3264r2.igen
5684 :include:::m16e.igen
5685 :include:::mdmx.igen
5686 :include:::mips3d.igen
5691 :include:::smartmips.igen