2 // <insn-word> { "+" <insn-word> }
14 // IGEN config - mips16
15 :option:16::insn-bit-size:16
16 :option:16::hi-bit-nr:15
17 :option:16::insn-specifying-widths:true
18 :option:16::gen-delayed-branch:false
20 // IGEN config - mips32/64..
21 :option:32::insn-bit-size:32
22 :option:32::hi-bit-nr:31
23 :option:32::insn-specifying-widths:true
24 :option:32::gen-delayed-branch:false
27 // Generate separate simulators for each target
28 // :option:::multi-sim:true
31 // Models known by this simulator
33 :model:::mipsII:mipsII:
34 :model:::mipsIII:mipsIII:
35 :model:::mipsIV:mipsIV:
36 :model:::mips16:mips16:
37 // start-sanitize-r5900
41 // start-sanitize-tx19
44 // start-sanitize-vr5400
45 :model:::vr5400:vr5400:
46 // end-sanitize-vr5400
50 // Pseudo instructions known by IGEN
53 SignalException (ReservedInstruction, 0);
57 // Pseudo instructions known by interp.c
58 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
59 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
62 SignalException (ReservedInstruction, instruction_0);
70 // CPU Instruction Set (mipsI - mipsIV)
74 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
75 "add r<RD>, r<RS>, r<RT>"
80 // start-sanitize-vr5400
82 // end-sanitize-vr5400
83 // start-sanitize-r5900
87 // start-sanitize-tx19
91 ALU32_BEGIN (GPR[RS]);
97 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
98 "addi r<RT>, r<RS>, IMMEDIATE"
103 // start-sanitize-vr5400
105 // end-sanitize-vr5400
106 // start-sanitize-r5900
108 // end-sanitize-r5900
110 // start-sanitize-tx19
114 ALU32_BEGIN (GPR[RS]);
115 ALU32_ADD (EXTEND16 (IMMEDIATE));
120 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
121 "add r<RT>, r<RS>, <IMMEDIATE>"
126 // start-sanitize-vr5400
128 // end-sanitize-vr5400
129 // start-sanitize-r5900
131 // end-sanitize-r5900
133 // start-sanitize-tx19
137 signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
138 GPR[RT] = EXTEND32 (temp);
142 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
147 // start-sanitize-vr5400
149 // end-sanitize-vr5400
150 // start-sanitize-r5900
152 // end-sanitize-r5900
154 // start-sanitize-tx19
158 signed32 temp = GPR[RS] + GPR[RT];
159 GPR[RD] = EXTEND32 (temp);
163 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
164 "and r<RD>, r<RS>, r<RT>"
169 // start-sanitize-vr5400
171 // end-sanitize-vr5400
172 // start-sanitize-r5900
174 // end-sanitize-r5900
176 // start-sanitize-tx19
180 GPR[RD] = GPR[RS] & GPR[RT];
184 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
185 "and r<RT>, r<RS>, IMMEDIATE"
189 // start-sanitize-vr5400
191 // end-sanitize-vr5400
192 // start-sanitize-r5900
194 // end-sanitize-r5900
196 // start-sanitize-tx19
200 GPR[RT] = GPR[RS] & IMMEDIATE;
204 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
205 "beq r<RS>, r<RT>, <OFFSET>"
210 // start-sanitize-vr5400
212 // end-sanitize-vr5400
213 // start-sanitize-r5900
215 // end-sanitize-r5900
217 // start-sanitize-tx19
221 address_word offset = EXTEND16 (OFFSET) << 2;
222 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
223 DELAY_SLOT (NIA + offset);
227 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
228 "beql r<RS>, r<RT>, <OFFSET>"
232 // start-sanitize-vr5400
234 // end-sanitize-vr5400
235 // start-sanitize-r5900
237 // end-sanitize-r5900
239 // start-sanitize-tx19
243 address_word offset = EXTEND16 (OFFSET) << 2;
244 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
245 DELAY_SLOT (NIA + offset);
247 NULLIFY_NEXT_INSTRUCTION ();
251 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
252 "bgez r<RS>, <OFFSET>"
257 // start-sanitize-vr5400
259 // end-sanitize-vr5400
260 // start-sanitize-r5900
262 // end-sanitize-r5900
264 // start-sanitize-tx19
268 address_word offset = EXTEND16 (OFFSET) << 2;
269 if ((signed_word) GPR[RS] >= 0)
270 DELAY_SLOT (NIA + offset);
274 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
275 "bgezal r<RS>, <OFFSET>"
280 // start-sanitize-vr5400
282 // end-sanitize-vr5400
283 // start-sanitize-r5900
285 // end-sanitize-r5900
287 // start-sanitize-tx19
291 address_word offset = EXTEND16 (OFFSET) << 2;
293 if ((signed_word) GPR[RS] >= 0)
294 DELAY_SLOT (NIA + offset);
298 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
299 "bgezall r<RS>, <OFFSET>"
303 // start-sanitize-vr5400
305 // end-sanitize-vr5400
306 // start-sanitize-r5900
308 // end-sanitize-r5900
310 // start-sanitize-tx19
314 address_word offset = EXTEND16 (OFFSET) << 2;
316 /* NOTE: The branch occurs AFTER the next instruction has been
318 if ((signed_word) GPR[RS] >= 0)
319 DELAY_SLOT (NIA + offset);
321 NULLIFY_NEXT_INSTRUCTION ();
325 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
326 "bgezl r<RS>, <OFFSET>"
330 // start-sanitize-vr5400
332 // end-sanitize-vr5400
333 // start-sanitize-r5900
335 // end-sanitize-r5900
337 // start-sanitize-tx19
341 address_word offset = EXTEND16 (OFFSET) << 2;
342 if ((signed_word) GPR[RS] >= 0)
343 DELAY_SLOT (NIA + offset);
345 NULLIFY_NEXT_INSTRUCTION ();
349 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
350 "bgtz r<RS>, <OFFSET>"
355 // start-sanitize-vr5400
357 // end-sanitize-vr5400
358 // start-sanitize-r5900
360 // end-sanitize-r5900
362 // start-sanitize-tx19
366 address_word offset = EXTEND16 (OFFSET) << 2;
367 if ((signed_word) GPR[RS] > 0)
368 DELAY_SLOT (NIA + offset);
372 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
373 "bgtzl r<RS>, <OFFSET>"
377 // start-sanitize-vr5400
379 // end-sanitize-vr5400
380 // start-sanitize-r5900
382 // end-sanitize-r5900
384 // start-sanitize-tx19
388 address_word offset = EXTEND16 (OFFSET) << 2;
389 /* NOTE: The branch occurs AFTER the next instruction has been
391 if ((signed_word) GPR[RS] > 0)
392 DELAY_SLOT (NIA + offset);
394 NULLIFY_NEXT_INSTRUCTION ();
398 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
399 "blez r<RS>, <OFFSET>"
404 // start-sanitize-vr5400
406 // end-sanitize-vr5400
407 // start-sanitize-r5900
409 // end-sanitize-r5900
411 // start-sanitize-tx19
415 address_word offset = EXTEND16 (OFFSET) << 2;
416 /* NOTE: The branch occurs AFTER the next instruction has been
418 if ((signed_word) GPR[RS] <= 0)
419 DELAY_SLOT (NIA + offset);
423 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
424 "bgezl r<RS>, <OFFSET>"
428 // start-sanitize-vr5400
430 // end-sanitize-vr5400
431 // start-sanitize-r5900
433 // end-sanitize-r5900
435 // start-sanitize-tx19
439 address_word offset = EXTEND16 (OFFSET) << 2;
440 if ((signed_word) GPR[RS] <= 0)
441 DELAY_SLOT (NIA + offset);
443 NULLIFY_NEXT_INSTRUCTION ();
447 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
448 "bltz r<RS>, <OFFSET>"
453 // start-sanitize-vr5400
455 // end-sanitize-vr5400
456 // start-sanitize-r5900
458 // end-sanitize-r5900
460 // start-sanitize-tx19
464 address_word offset = EXTEND16 (OFFSET) << 2;
465 if ((signed_word) GPR[RS] < 0)
466 DELAY_SLOT (NIA + offset);
470 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
471 "bltzal r<RS>, <OFFSET>"
476 // start-sanitize-vr5400
478 // end-sanitize-vr5400
479 // start-sanitize-r5900
481 // end-sanitize-r5900
483 // start-sanitize-tx19
487 address_word offset = EXTEND16 (OFFSET) << 2;
489 /* NOTE: The branch occurs AFTER the next instruction has been
491 if ((signed_word) GPR[RS] < 0)
492 DELAY_SLOT (NIA + offset);
496 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
497 "bltzall r<RS>, <OFFSET>"
501 // start-sanitize-vr5400
503 // end-sanitize-vr5400
504 // start-sanitize-r5900
506 // end-sanitize-r5900
508 // start-sanitize-tx19
512 address_word offset = EXTEND16 (OFFSET) << 2;
514 if ((signed_word) GPR[RS] < 0)
515 DELAY_SLOT (NIA + offset);
517 NULLIFY_NEXT_INSTRUCTION ();
521 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
522 "bltzl r<RS>, <OFFSET>"
526 // start-sanitize-vr5400
528 // end-sanitize-vr5400
529 // start-sanitize-r5900
531 // end-sanitize-r5900
533 // start-sanitize-tx19
537 address_word offset = EXTEND16 (OFFSET) << 2;
538 /* NOTE: The branch occurs AFTER the next instruction has been
540 if ((signed_word) GPR[RS] < 0)
541 DELAY_SLOT (NIA + offset);
543 NULLIFY_NEXT_INSTRUCTION ();
547 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
548 "bne r<RS>, r<RT>, <OFFSET>"
553 // start-sanitize-vr5400
555 // end-sanitize-vr5400
556 // start-sanitize-r5900
558 // end-sanitize-r5900
560 // start-sanitize-tx19
564 address_word offset = EXTEND16 (OFFSET) << 2;
565 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
566 DELAY_SLOT (NIA + offset);
570 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
571 "bnel r<RS>, r<RT>, <OFFSET>"
575 // start-sanitize-vr5400
577 // end-sanitize-vr5400
578 // start-sanitize-r5900
580 // end-sanitize-r5900
582 // start-sanitize-tx19
586 address_word offset = EXTEND16 (OFFSET) << 2;
587 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
588 DELAY_SLOT (NIA + offset);
590 NULLIFY_NEXT_INSTRUCTION ();
594 000000,20.CODE,001101:SPECIAL:32::BREAK
600 // start-sanitize-vr5400
602 // end-sanitize-vr5400
603 // start-sanitize-r5900
605 // end-sanitize-r5900
607 // start-sanitize-tx19
611 SignalException(BreakPoint, instruction_0);
615 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
621 // start-sanitize-r5900
623 // end-sanitize-r5900
625 // start-sanitize-tx19
629 DecodeCoproc (instruction_0);
633 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
634 "dadd r<RD>, r<RS>, r<RT>"
637 // start-sanitize-vr5400
639 // end-sanitize-vr5400
640 // start-sanitize-r5900
642 // end-sanitize-r5900
644 // start-sanitize-tx19
648 ALU64_BEGIN (GPR[RS]);
654 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
655 "daddi r<RT>, r<RS>, <IMMEDIATE>"
658 // start-sanitize-vr5400
660 // end-sanitize-vr5400
661 // start-sanitize-r5900
663 // end-sanitize-r5900
665 // start-sanitize-tx19
669 ALU64_BEGIN (GPR[RS]);
670 ALU64_ADD (EXTEND16 (IMMEDIATE));
675 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
676 "daddu r<RT>, r<RS>, <IMMEDIATE>"
679 // start-sanitize-vr5400
681 // end-sanitize-vr5400
682 // start-sanitize-r5900
684 // end-sanitize-r5900
686 // start-sanitize-tx19
690 GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
694 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
695 "daddu r<RD>, r<RS>, r<RT>"
698 // start-sanitize-vr5400
700 // end-sanitize-vr5400
701 // start-sanitize-r5900
703 // end-sanitize-r5900
705 // start-sanitize-tx19
709 GPR[RD] = GPR[RS] + GPR[RT];
713 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
717 // start-sanitize-vr5400
719 // end-sanitize-vr5400
720 // start-sanitize-r5900
722 // end-sanitize-r5900
724 // start-sanitize-tx19
728 CHECKHILO ("Division");
730 signed64 n = GPR[RS];
731 signed64 d = GPR[RT];
734 LO = SIGNED64 (0x8000000000000000);
737 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
739 LO = SIGNED64 (0x8000000000000000);
752 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
757 // start-sanitize-vr5400
759 // end-sanitize-vr5400
760 // start-sanitize-tx19
764 CHECKHILO ("Division");
766 unsigned64 n = GPR[RS];
767 unsigned64 d = GPR[RT];
770 LO = SIGNED64 (0x8000000000000000);
782 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
788 // start-sanitize-vr5400
790 // end-sanitize-vr5400
791 // start-sanitize-r5900
793 // end-sanitize-r5900
795 // start-sanitize-tx19
799 CHECKHILO("Division");
801 signed32 n = GPR[RS];
802 signed32 d = GPR[RT];
805 LO = EXTEND32 (0x80000000);
808 else if (d == -1 && d == 0x80000000)
810 LO = EXTEND32 (0x80000000);
815 LO = EXTEND32 (n / d);
816 HI = EXTEND32 (n % d);
822 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
828 // start-sanitize-vr5400
830 // end-sanitize-vr5400
831 // start-sanitize-r5900
833 // end-sanitize-r5900
835 // start-sanitize-tx19
839 CHECKHILO ("Division");
841 unsigned32 n = GPR[RS];
842 unsigned32 d = GPR[RT];
845 LO = EXTEND32 (0x80000000);
850 LO = EXTEND32 (n / d);
851 HI = EXTEND32 (n % d);
857 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
861 // start-sanitize-vr5400
863 // end-sanitize-vr5400
865 // start-sanitize-tx19
869 CHECKHILO ("Multiplication");
871 signed64 op1 = GPR[RS];
872 signed64 op2 = GPR[RT];
881 /* make it unsigned */
892 /* multuply out the 4 sub products */
893 m00 = (VL4_8 (op1) * VL4_8 (op2));
894 m10 = (VH4_8 (op1) * VL4_8 (op2));
895 m01 = (VL4_8 (op1) * VH4_8 (op2));
896 m11 = (VH4_8 (op1) * VH4_8 (op2));
897 /* add the products */
898 mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
899 lo = U8_4 (mid, m00);
900 hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
901 /* save the result */
919 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
920 "dmultu r<RS>, r<RT>"
923 // start-sanitize-vr5400
925 // end-sanitize-vr5400
927 // start-sanitize-tx19
931 CHECKHILO ("Multiplication");
933 signed64 op1 = GPR[RS];
934 signed64 op2 = GPR[RT];
942 /* multuply out the 4 sub products */
943 m00 = (VL4_8 (op1) * VL4_8 (op2));
944 m10 = (VH4_8 (op1) * VL4_8 (op2));
945 m01 = (VL4_8 (op1) * VH4_8 (op2));
946 m11 = (VH4_8 (op1) * VH4_8 (op2));
947 /* add the products */
948 mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
949 lo = U8_4 (mid, m00);
950 hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
951 /* save the result */
958 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
959 "dsll r<RD>, r<RT>, <SHIFT>"
962 // start-sanitize-vr5400
964 // end-sanitize-vr5400
965 // start-sanitize-r5900
967 // end-sanitize-r5900
969 // start-sanitize-tx19
974 GPR[RD] = GPR[RT] << s;
978 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
979 "dsll32 r<RD>, r<RT>, <SHIFT>"
982 // start-sanitize-vr5400
984 // end-sanitize-vr5400
985 // start-sanitize-r5900
987 // end-sanitize-r5900
989 // start-sanitize-tx19
994 GPR[RD] = GPR[RT] << s;
998 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
999 "dsllv r<RD>, r<RT>, r<RS>"
1002 // start-sanitize-vr5400
1004 // end-sanitize-vr5400
1005 // start-sanitize-r5900
1007 // end-sanitize-r5900
1009 // start-sanitize-tx19
1011 // end-sanitize-tx19
1013 int s = MASKED64 (GPR[RS], 5, 0);
1014 GPR[RD] = GPR[RT] << s;
1018 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1019 "dsra r<RD>, r<RT>, <SHIFT>"
1022 // start-sanitize-vr5400
1024 // end-sanitize-vr5400
1025 // start-sanitize-r5900
1027 // end-sanitize-r5900
1029 // start-sanitize-tx19
1031 // end-sanitize-tx19
1034 GPR[RD] = ((signed64) GPR[RT]) >> s;
1038 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1039 "dsra32 r<RT>, r<RD>, <SHIFT>"
1042 // start-sanitize-vr5400
1044 // end-sanitize-vr5400
1045 // start-sanitize-r5900
1047 // end-sanitize-r5900
1049 // start-sanitize-tx19
1051 // end-sanitize-tx19
1054 GPR[RD] = ((signed64) GPR[RT]) >> s;
1058 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1059 "dsra32 r<RT>, r<RD>, r<RS>"
1062 // start-sanitize-vr5400
1064 // end-sanitize-vr5400
1065 // start-sanitize-r5900
1067 // end-sanitize-r5900
1069 // start-sanitize-tx19
1071 // end-sanitize-tx19
1073 int s = MASKED64 (GPR[RS], 5, 0);
1074 GPR[RD] = ((signed64) GPR[RT]) >> s;
1078 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1079 "dsrav r<RD>, r<RT>, <SHIFT>"
1082 // start-sanitize-vr5400
1084 // end-sanitize-vr5400
1085 // start-sanitize-r5900
1087 // end-sanitize-r5900
1089 // start-sanitize-tx19
1091 // end-sanitize-tx19
1094 GPR[RD] = (unsigned64) GPR[RT] >> s;
1098 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1099 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1102 // start-sanitize-vr5400
1104 // end-sanitize-vr5400
1105 // start-sanitize-r5900
1107 // end-sanitize-r5900
1109 // start-sanitize-tx19
1111 // end-sanitize-tx19
1114 GPR[RD] = (unsigned64) GPR[RT] >> s;
1118 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1119 "dsrl32 r<RD>, r<RT>, r<RS>"
1122 // start-sanitize-vr5400
1124 // end-sanitize-vr5400
1125 // start-sanitize-r5900
1127 // end-sanitize-r5900
1129 // start-sanitize-tx19
1131 // end-sanitize-tx19
1133 int s = MASKED64 (GPR[RS], 5, 0);
1134 GPR[RD] = (unsigned64) GPR[RT] >> s;
1138 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1139 "dsub r<RD>, r<RS>, r<RT>"
1142 // start-sanitize-vr5400
1144 // end-sanitize-vr5400
1145 // start-sanitize-r5900
1147 // end-sanitize-r5900
1149 // start-sanitize-tx19
1151 // end-sanitize-tx19
1153 ALU64_BEGIN (GPR[RS]);
1154 ALU64_SUB (GPR[RT]);
1155 ALU64_END (GPR[RD]);
1159 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1160 "dsubu r<RD>, r<RS>, r<RT>"
1163 // start-sanitize-vr5400
1165 // end-sanitize-vr5400
1166 // start-sanitize-r5900
1168 // end-sanitize-r5900
1170 // start-sanitize-tx19
1172 // end-sanitize-tx19
1174 GPR[RD] = GPR[RS] - GPR[RT];
1178 000010,26.INSTR_INDEX:NORMAL:32::J
1184 // start-sanitize-vr5400
1186 // end-sanitize-vr5400
1187 // start-sanitize-r5900
1189 // end-sanitize-r5900
1191 // start-sanitize-tx19
1193 // end-sanitize-tx19
1195 /* NOTE: The region used is that of the delay slot NIA and NOT the
1196 current instruction */
1197 address_word region = (NIA & MASK (63, 28));
1198 DELAY_SLOT (region | (INSTR_INDEX << 2));
1202 000011,26.INSTR_INDEX:NORMAL:32::JAL
1208 // start-sanitize-vr5400
1210 // end-sanitize-vr5400
1211 // start-sanitize-r5900
1213 // end-sanitize-r5900
1215 // start-sanitize-tx19
1217 // end-sanitize-tx19
1219 /* NOTE: The region used is that of the delay slot and NOT the
1220 current instruction */
1221 address_word region = (NIA & MASK (63, 28));
1223 DELAY_SLOT (region | (INSTR_INDEX << 2));
1227 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1228 "jalr r<RS>":RD == 31
1234 // start-sanitize-vr5400
1236 // end-sanitize-vr5400
1237 // start-sanitize-r5900
1239 // end-sanitize-r5900
1241 // start-sanitize-tx19
1243 // end-sanitize-tx19
1245 address_word temp = GPR[RS];
1251 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1257 // start-sanitize-vr5400
1259 // end-sanitize-vr5400
1260 // start-sanitize-r5900
1262 // end-sanitize-r5900
1264 // start-sanitize-tx19
1266 // end-sanitize-tx19
1268 DELAY_SLOT (GPR[RS]);
1272 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1273 "lb r<RT>, <OFFSET>(r<BASE>)"
1278 // start-sanitize-vr5400
1280 // end-sanitize-vr5400
1281 // start-sanitize-r5900
1283 // end-sanitize-r5900
1285 // start-sanitize-tx19
1287 // end-sanitize-tx19
1289 unsigned32 instruction = instruction_0;
1290 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1291 int destreg = ((instruction >> 16) & 0x0000001F);
1292 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1294 address_word vaddr = ((uword64)op1 + offset);
1298 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1301 uword64 memval1 = 0;
1303 unsigned int shift = 0;
1304 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1305 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1307 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1308 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1309 byte = ((vaddr & mask) ^ (bigend << shift));
1310 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1317 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1318 "lbu r<RT>, <OFFSET>(r<BASE>)"
1323 // start-sanitize-vr5400
1325 // end-sanitize-vr5400
1326 // start-sanitize-r5900
1328 // end-sanitize-r5900
1330 // start-sanitize-tx19
1332 // end-sanitize-tx19
1334 unsigned32 instruction = instruction_0;
1335 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1336 int destreg = ((instruction >> 16) & 0x0000001F);
1337 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1339 address_word vaddr = ((unsigned64)op1 + offset);
1343 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1345 unsigned64 memval = 0;
1346 unsigned64 memval1 = 0;
1347 unsigned64 mask = 0x7;
1348 unsigned int shift = 0;
1349 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1350 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1352 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1353 LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1354 byte = ((vaddr & mask) ^ (bigend << shift));
1355 GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1362 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1363 "ld r<RT>, <OFFSET>(r<BASE>)"
1366 // start-sanitize-vr5400
1368 // end-sanitize-vr5400
1369 // start-sanitize-r5900
1371 // end-sanitize-r5900
1373 // start-sanitize-tx19
1375 // end-sanitize-tx19
1377 unsigned32 instruction = instruction_0;
1378 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1379 int destreg = ((instruction >> 16) & 0x0000001F);
1380 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1382 address_word vaddr = ((unsigned64)op1 + offset);
1385 if ((vaddr & 7) != 0)
1386 SignalExceptionAddressLoad();
1389 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1391 unsigned64 memval = 0;
1392 unsigned64 memval1 = 0;
1393 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1394 GPR[destreg] = memval;
1401 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1402 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1406 // start-sanitize-vr5400
1408 // end-sanitize-vr5400
1409 // start-sanitize-r5900
1411 // end-sanitize-r5900
1413 // start-sanitize-tx19
1415 // end-sanitize-tx19
1417 unsigned32 instruction = instruction_0;
1418 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1419 int destreg = ((instruction >> 16) & 0x0000001F);
1420 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1422 address_word vaddr = ((unsigned64)op1 + offset);
1425 if ((vaddr & 7) != 0)
1426 SignalExceptionAddressLoad();
1429 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1431 unsigned64 memval = 0;
1432 unsigned64 memval1 = 0;
1433 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1434 COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1441 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1442 "ldl r<RT>, <OFFSET>(r<BASE>)"
1445 // start-sanitize-vr5400
1447 // end-sanitize-vr5400
1448 // start-sanitize-r5900
1450 // end-sanitize-r5900
1452 // start-sanitize-tx19
1454 // end-sanitize-tx19
1456 unsigned32 instruction = instruction_0;
1457 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1458 int destreg = ((instruction >> 16) & 0x0000001F);
1459 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1461 address_word vaddr = ((unsigned64)op1 + offset);
1465 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1467 unsigned64 memval = 0;
1468 unsigned64 memval1 = 0;
1469 unsigned64 mask = 7;
1470 unsigned int reverse = (ReverseEndian ? mask : 0);
1471 unsigned int bigend = (BigEndianCPU ? mask : 0);
1473 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1474 byte = ((vaddr & mask) ^ bigend);
1477 LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1478 GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1485 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1486 "ldr r<RT>, <OFFSET>(r<BASE>)"
1489 // start-sanitize-vr5400
1491 // end-sanitize-vr5400
1492 // start-sanitize-r5900
1494 // end-sanitize-r5900
1496 // start-sanitize-tx19
1498 // end-sanitize-tx19
1500 unsigned32 instruction = instruction_0;
1501 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1502 int destreg = ((instruction >> 16) & 0x0000001F);
1503 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1505 address_word vaddr = ((unsigned64)op1 + offset);
1509 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1511 unsigned64 memval = 0;
1512 unsigned64 memval1 = 0;
1513 unsigned64 mask = 7;
1514 unsigned int reverse = (ReverseEndian ? mask : 0);
1515 unsigned int bigend = (BigEndianCPU ? mask : 0);
1517 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1518 byte = ((vaddr & mask) ^ bigend);
1521 LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1527 srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1528 GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1536 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1537 "lh r<RT>, <OFFSET>(r<BASE>)"
1542 // start-sanitize-vr5400
1544 // end-sanitize-vr5400
1545 // start-sanitize-r5900
1547 // end-sanitize-r5900
1549 // start-sanitize-tx19
1551 // end-sanitize-tx19
1553 unsigned32 instruction = instruction_0;
1554 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1555 int destreg = ((instruction >> 16) & 0x0000001F);
1556 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1558 address_word vaddr = ((unsigned64)op1 + offset);
1561 if ((vaddr & 1) != 0)
1562 SignalExceptionAddressLoad();
1565 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1567 unsigned64 memval = 0;
1568 unsigned64 memval1 = 0;
1569 unsigned64 mask = 0x7;
1570 unsigned int shift = 1;
1571 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1572 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1574 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1575 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1576 byte = ((vaddr & mask) ^ (bigend << shift));
1577 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1584 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1585 "lhu r<RT>, <OFFSET>(r<BASE>)"
1590 // start-sanitize-vr5400
1592 // end-sanitize-vr5400
1593 // start-sanitize-r5900
1595 // end-sanitize-r5900
1597 // start-sanitize-tx19
1599 // end-sanitize-tx19
1601 unsigned32 instruction = instruction_0;
1602 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1603 int destreg = ((instruction >> 16) & 0x0000001F);
1604 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1606 address_word vaddr = ((unsigned64)op1 + offset);
1609 if ((vaddr & 1) != 0)
1610 SignalExceptionAddressLoad();
1613 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1615 unsigned64 memval = 0;
1616 unsigned64 memval1 = 0;
1617 unsigned64 mask = 0x7;
1618 unsigned int shift = 1;
1619 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1620 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1622 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1623 LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1624 byte = ((vaddr & mask) ^ (bigend << shift));
1625 GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1632 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1633 "ll r<RT>, <OFFSET>(r<BASE>)"
1637 // start-sanitize-vr5400
1639 // end-sanitize-vr5400
1640 // start-sanitize-r5900
1642 // end-sanitize-r5900
1644 // start-sanitize-tx19
1646 // end-sanitize-tx19
1648 unsigned32 instruction = instruction_0;
1649 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1650 int destreg = ((instruction >> 16) & 0x0000001F);
1651 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1653 address_word vaddr = ((unsigned64)op1 + offset);
1656 if ((vaddr & 3) != 0)
1657 SignalExceptionAddressLoad();
1660 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1662 unsigned64 memval = 0;
1663 unsigned64 memval1 = 0;
1664 unsigned64 mask = 0x7;
1665 unsigned int shift = 2;
1666 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1667 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1669 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1670 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1671 byte = ((vaddr & mask) ^ (bigend << shift));
1672 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1680 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1681 "lld r<RT>, <OFFSET>(r<BASE>)"
1684 // start-sanitize-vr5400
1686 // end-sanitize-vr5400
1687 // start-sanitize-r5900
1689 // end-sanitize-r5900
1691 // start-sanitize-tx19
1693 // end-sanitize-tx19
1695 unsigned32 instruction = instruction_0;
1696 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1697 int destreg = ((instruction >> 16) & 0x0000001F);
1698 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1700 address_word vaddr = ((unsigned64)op1 + offset);
1703 if ((vaddr & 7) != 0)
1704 SignalExceptionAddressLoad();
1707 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1709 unsigned64 memval = 0;
1710 unsigned64 memval1 = 0;
1711 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1712 GPR[destreg] = memval;
1720 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1721 "lui r<RT>, <IMMEDIATE>"
1726 // start-sanitize-vr5400
1728 // end-sanitize-vr5400
1729 // start-sanitize-r5900
1731 // end-sanitize-r5900
1733 // start-sanitize-tx19
1735 // end-sanitize-tx19
1737 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1741 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1742 "lw r<RT>, <OFFSET>(r<BASE>)"
1747 // start-sanitize-vr5400
1749 // end-sanitize-vr5400
1750 // start-sanitize-r5900
1752 // end-sanitize-r5900
1754 // start-sanitize-tx19
1756 // end-sanitize-tx19
1758 unsigned32 instruction = instruction_0;
1759 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1760 int destreg = ((instruction >> 16) & 0x0000001F);
1761 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1763 address_word vaddr = ((unsigned64)op1 + offset);
1766 if ((vaddr & 3) != 0)
1767 SignalExceptionAddressLoad();
1770 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1772 unsigned64 memval = 0;
1773 unsigned64 memval1 = 0;
1774 unsigned64 mask = 0x7;
1775 unsigned int shift = 2;
1776 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1777 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1779 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1780 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1781 byte = ((vaddr & mask) ^ (bigend << shift));
1782 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1789 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1790 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1795 // start-sanitize-vr5400
1797 // end-sanitize-vr5400
1798 // start-sanitize-r5900
1800 // end-sanitize-r5900
1802 // start-sanitize-tx19
1804 // end-sanitize-tx19
1806 unsigned32 instruction = instruction_0;
1807 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1808 int destreg = ((instruction >> 16) & 0x0000001F);
1809 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1811 address_word vaddr = ((unsigned64)op1 + offset);
1814 if ((vaddr & 3) != 0)
1815 SignalExceptionAddressLoad();
1818 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1820 unsigned64 memval = 0;
1821 unsigned64 memval1 = 0;
1822 unsigned64 mask = 0x7;
1823 unsigned int shift = 2;
1824 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1825 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1827 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1828 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1829 byte = ((vaddr & mask) ^ (bigend << shift));
1830 COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
1837 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1838 "lwl r<RT>, <OFFSET>(r<BASE>)"
1843 // start-sanitize-vr5400
1845 // end-sanitize-vr5400
1846 // start-sanitize-r5900
1848 // end-sanitize-r5900
1850 // start-sanitize-tx19
1852 // end-sanitize-tx19
1854 unsigned32 instruction = instruction_0;
1855 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1856 int destreg = ((instruction >> 16) & 0x0000001F);
1857 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1859 address_word vaddr = ((unsigned64)op1 + offset);
1863 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1865 unsigned64 memval = 0;
1866 unsigned64 memval1 = 0;
1867 unsigned64 mask = 3;
1868 unsigned int reverse = (ReverseEndian ? mask : 0);
1869 unsigned int bigend = (BigEndianCPU ? mask : 0);
1871 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1872 byte = ((vaddr & mask) ^ bigend);
1875 LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1876 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1879 GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
1880 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1887 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1888 "lwr r<RT>, <OFFSET>(r<BASE>)"
1893 // start-sanitize-vr5400
1895 // end-sanitize-vr5400
1896 // start-sanitize-r5900
1898 // end-sanitize-r5900
1900 // start-sanitize-tx19
1902 // end-sanitize-tx19
1904 unsigned32 instruction = instruction_0;
1905 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1906 int destreg = ((instruction >> 16) & 0x0000001F);
1907 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1909 address_word vaddr = ((unsigned64)op1 + offset);
1913 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1915 unsigned64 memval = 0;
1916 unsigned64 memval1 = 0;
1917 unsigned64 mask = 3;
1918 unsigned int reverse = (ReverseEndian ? mask : 0);
1919 unsigned int bigend = (BigEndianCPU ? mask : 0);
1921 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1922 byte = ((vaddr & mask) ^ bigend);
1925 LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
1926 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1934 srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
1935 GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1937 GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1944 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1945 "lwu r<RT>, <OFFSET>(r<BASE>)"
1948 // start-sanitize-vr5400
1950 // end-sanitize-vr5400
1951 // start-sanitize-r5900
1953 // end-sanitize-r5900
1955 // start-sanitize-tx19
1957 // end-sanitize-tx19
1959 unsigned32 instruction = instruction_0;
1960 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1961 int destreg = ((instruction >> 16) & 0x0000001F);
1962 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1964 address_word vaddr = ((unsigned64)op1 + offset);
1967 if ((vaddr & 3) != 0)
1968 SignalExceptionAddressLoad();
1971 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1973 unsigned64 memval = 0;
1974 unsigned64 memval1 = 0;
1975 unsigned64 mask = 0x7;
1976 unsigned int shift = 2;
1977 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1978 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1980 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1981 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1982 byte = ((vaddr & mask) ^ (bigend << shift));
1983 GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
1990 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1996 // start-sanitize-vr5400
1998 // end-sanitize-vr5400
1999 // start-sanitize-r5900
2001 // end-sanitize-r5900
2003 // start-sanitize-tx19
2005 // end-sanitize-tx19
2014 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2020 // start-sanitize-vr5400
2022 // end-sanitize-vr5400
2023 // start-sanitize-r5900
2025 // end-sanitize-r5900
2027 // start-sanitize-tx19
2029 // end-sanitize-tx19
2033 LOACCESS = 3; /* 3rd instruction will be safe */
2038 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2039 "movn r<RD>, r<RS>, r<RT>"
2041 // start-sanitize-vr5400
2043 // end-sanitize-vr5400
2044 // start-sanitize-r5900
2046 // end-sanitize-r5900
2053 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2054 "movz r<RD>, r<RS>, r<RT>"
2056 // start-sanitize-vr5400
2058 // end-sanitize-vr5400
2059 // start-sanitize-r5900
2061 // end-sanitize-r5900
2068 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2074 // start-sanitize-vr5400
2076 // end-sanitize-vr5400
2077 // start-sanitize-r5900
2079 // end-sanitize-r5900
2081 // start-sanitize-tx19
2083 // end-sanitize-tx19
2087 sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2091 HIACCESS = 3; /* 3rd instruction will be safe */
2096 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2102 // start-sanitize-vr5400
2104 // end-sanitize-vr5400
2105 // start-sanitize-r5900
2107 // end-sanitize-r5900
2109 // start-sanitize-tx19
2111 // end-sanitize-tx19
2115 sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2119 LOACCESS = 3; /* 3rd instruction will be safe */
2124 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2132 CHECKHILO ("Multiplication");
2133 prod = (((signed64)(signed32) GPR[RS])
2134 * ((signed64)(signed32) GPR[RT]));
2135 LO = EXTEND32 (VL4_8 (prod));
2136 HI = EXTEND32 (VH4_8 (prod));
2138 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2139 "mult r<RD>, r<RS>, r<RT>"
2140 // start-sanitize-vr5400
2142 // end-sanitize-vr5400
2143 // start-sanitize-r5900
2145 // end-sanitize-r5900
2147 // start-sanitize-tx19
2149 // end-sanitize-tx19
2152 CHECKHILO ("Multiplication");
2153 prod = (((signed64)(signed32) GPR[RS])
2154 * ((signed64)(signed32) GPR[RT]));
2155 LO = EXTEND32 (VL4_8 (prod));
2156 HI = EXTEND32 (VH4_8 (prod));
2162 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2163 "multu r<RS>, r<RT>"
2170 CHECKHILO ("Multiplication");
2171 prod = (((unsigned64)(unsigned32) GPR[RS])
2172 * ((unsigned64)(unsigned32) GPR[RT]));
2173 LO = EXTEND32 (VL4_8 (prod));
2174 HI = EXTEND32 (VH4_8 (prod));
2176 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2177 "multu r<RD>, r<RS>, r<RT>"
2178 // start-sanitize-vr5400
2180 // end-sanitize-vr5400
2181 // start-sanitize-r5900
2183 // end-sanitize-r5900
2185 // start-sanitize-tx19
2187 // end-sanitize-tx19
2190 CHECKHILO ("Multiplication");
2191 prod = (((unsigned64)(unsigned32) GPR[RS])
2192 * ((unsigned64)(unsigned32) GPR[RT]));
2193 LO = EXTEND32 (VL4_8 (prod));
2194 HI = EXTEND32 (VH4_8 (prod));
2200 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2201 "nor r<RD>, r<RS>, r<RT>"
2206 // start-sanitize-vr5400
2208 // end-sanitize-vr5400
2209 // start-sanitize-r5900
2211 // end-sanitize-r5900
2213 // start-sanitize-tx19
2215 // end-sanitize-tx19
2217 GPR[RD] = ~ (GPR[RS] | GPR[RT]);
2221 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2222 "or r<RD>, r<RS>, r<RT>"
2227 // start-sanitize-vr5400
2229 // end-sanitize-vr5400
2230 // start-sanitize-r5900
2232 // end-sanitize-r5900
2234 // start-sanitize-tx19
2236 // end-sanitize-tx19
2238 GPR[RD] = (GPR[RS] | GPR[RT]);
2242 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2243 "ori r<RT>, r<RS>, <IMMEDIATE>"
2248 // start-sanitize-vr5400
2250 // end-sanitize-vr5400
2251 // start-sanitize-r5900
2253 // end-sanitize-r5900
2255 // start-sanitize-tx19
2257 // end-sanitize-tx19
2259 GPR[RT] = (GPR[RS] | IMMEDIATE);
2263 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2265 // start-sanitize-vr5400
2267 // end-sanitize-vr5400
2268 // start-sanitize-r5900
2270 // end-sanitize-r5900
2272 unsigned32 instruction = instruction_0;
2273 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2274 int hint = ((instruction >> 16) & 0x0000001F);
2275 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2277 address_word vaddr = ((unsigned64)op1 + offset);
2281 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2282 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2287 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2288 "sb r<RT>, <OFFSET>(r<BASE>)"
2293 // start-sanitize-vr5400
2295 // end-sanitize-vr5400
2296 // start-sanitize-r5900
2298 // end-sanitize-r5900
2300 // start-sanitize-tx19
2302 // end-sanitize-tx19
2304 unsigned32 instruction = instruction_0;
2305 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2306 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2307 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2309 address_word vaddr = ((unsigned64)op1 + offset);
2313 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2315 unsigned64 memval = 0;
2316 unsigned64 memval1 = 0;
2317 unsigned64 mask = 0x7;
2318 unsigned int shift = 0;
2319 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2320 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2322 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2323 byte = ((vaddr & mask) ^ (bigend << shift));
2324 memval = ((unsigned64) op2 << (8 * byte));
2326 StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2334 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2335 "sc r<RT>, <OFFSET>(r<BASE>)"
2339 // start-sanitize-vr5400
2341 // end-sanitize-vr5400
2342 // start-sanitize-r5900
2344 // end-sanitize-r5900
2346 // start-sanitize-tx19
2348 // end-sanitize-tx19
2350 unsigned32 instruction = instruction_0;
2351 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2352 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2353 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2355 address_word vaddr = ((unsigned64)op1 + offset);
2358 if ((vaddr & 3) != 0)
2359 SignalExceptionAddressStore();
2362 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2364 unsigned64 memval = 0;
2365 unsigned64 memval1 = 0;
2366 unsigned64 mask = 0x7;
2368 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2369 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2370 memval = ((unsigned64) op2 << (8 * byte));
2373 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2375 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2382 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2383 "scd r<RT>, <OFFSET>(r<BASE>)"
2386 // start-sanitize-vr5400
2388 // end-sanitize-vr5400
2389 // start-sanitize-r5900
2391 // end-sanitize-r5900
2393 // start-sanitize-tx19
2395 // end-sanitize-tx19
2397 unsigned32 instruction = instruction_0;
2398 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2399 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2400 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2402 address_word vaddr = ((unsigned64)op1 + offset);
2405 if ((vaddr & 7) != 0)
2406 SignalExceptionAddressStore();
2409 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2411 unsigned64 memval = 0;
2412 unsigned64 memval1 = 0;
2416 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2418 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2425 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2426 "sd r<RT>, <OFFSET>(r<BASE>)"
2429 // start-sanitize-vr5400
2431 // end-sanitize-vr5400
2432 // start-sanitize-r5900
2434 // end-sanitize-r5900
2436 // start-sanitize-tx19
2438 // end-sanitize-tx19
2440 unsigned32 instruction = instruction_0;
2441 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2442 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2443 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2445 address_word vaddr = ((unsigned64)op1 + offset);
2448 if ((vaddr & 7) != 0)
2449 SignalExceptionAddressStore();
2452 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2454 unsigned64 memval = 0;
2455 unsigned64 memval1 = 0;
2458 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2466 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2467 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2471 // start-sanitize-vr5400
2473 // end-sanitize-vr5400
2474 // start-sanitize-r5900
2476 // end-sanitize-r5900
2478 // start-sanitize-tx19
2480 // end-sanitize-tx19
2482 unsigned32 instruction = instruction_0;
2483 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2484 int destreg = ((instruction >> 16) & 0x0000001F);
2485 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2487 address_word vaddr = ((unsigned64)op1 + offset);
2490 if ((vaddr & 7) != 0)
2491 SignalExceptionAddressStore();
2494 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2496 unsigned64 memval = 0;
2497 unsigned64 memval1 = 0;
2498 memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2500 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2508 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2509 "sdl r<RT>, <OFFSET>(r<BASE>)"
2512 // start-sanitize-vr5400
2514 // end-sanitize-vr5400
2515 // start-sanitize-r5900
2517 // end-sanitize-r5900
2519 // start-sanitize-tx19
2521 // end-sanitize-tx19
2523 unsigned32 instruction = instruction_0;
2524 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2525 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2526 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2528 address_word vaddr = ((unsigned64)op1 + offset);
2532 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2534 unsigned64 memval = 0;
2535 unsigned64 memval1 = 0;
2536 unsigned64 mask = 7;
2537 unsigned int reverse = (ReverseEndian ? mask : 0);
2538 unsigned int bigend = (BigEndianCPU ? mask : 0);
2540 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2541 byte = ((vaddr & mask) ^ bigend);
2544 memval = (op2 >> (8 * (7 - byte)));
2545 StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2552 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2553 "sdr r<RT>, <OFFSET>(r<BASE>)"
2556 // start-sanitize-vr5400
2558 // end-sanitize-vr5400
2559 // start-sanitize-r5900
2561 // end-sanitize-r5900
2563 // start-sanitize-tx19
2565 // end-sanitize-tx19
2567 unsigned32 instruction = instruction_0;
2568 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2569 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2570 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2572 address_word vaddr = ((unsigned64)op1 + offset);
2576 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2578 unsigned64 memval = 0;
2579 unsigned64 memval1 = 0;
2580 unsigned64 mask = 7;
2581 unsigned int reverse = (ReverseEndian ? mask : 0);
2582 unsigned int bigend = (BigEndianCPU ? mask : 0);
2584 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2585 byte = ((vaddr & mask) ^ bigend);
2588 memval = ((unsigned64) op2 << (byte * 8));
2589 StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
2596 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2597 "sh r<RT>, <OFFSET>(r<BASE>)"
2602 // start-sanitize-vr5400
2604 // end-sanitize-vr5400
2605 // start-sanitize-r5900
2607 // end-sanitize-r5900
2609 // start-sanitize-tx19
2611 // end-sanitize-tx19
2613 unsigned32 instruction = instruction_0;
2614 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2615 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2616 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2618 address_word vaddr = ((unsigned64)op1 + offset);
2621 if ((vaddr & 1) != 0)
2622 SignalExceptionAddressStore();
2625 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2627 unsigned64 memval = 0;
2628 unsigned64 memval1 = 0;
2629 unsigned64 mask = 0x7;
2630 unsigned int shift = 1;
2631 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2632 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2634 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2635 byte = ((vaddr & mask) ^ (bigend << shift));
2636 memval = ((unsigned64) op2 << (8 * byte));
2638 StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2646 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2647 "sll r<RD>, r<RT>, <SHIFT>"
2652 // start-sanitize-vr5400
2654 // end-sanitize-vr5400
2655 // start-sanitize-r5900
2657 // end-sanitize-r5900
2659 // start-sanitize-tx19
2661 // end-sanitize-tx19
2664 unsigned32 temp = (GPR[RT] << s);
2665 GPR[RD] = EXTEND32 (temp);
2669 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2670 "sllv r<RD>, r<RT>, r<RS>"
2675 // start-sanitize-vr5400
2677 // end-sanitize-vr5400
2678 // start-sanitize-r5900
2680 // end-sanitize-r5900
2682 // start-sanitize-tx19
2684 // end-sanitize-tx19
2686 int s = MASKED (GPR[RS], 4, 0);
2687 unsigned32 temp = (GPR[RT] << s);
2688 GPR[RD] = EXTEND32 (temp);
2692 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2693 "slt r<RD>, r<RS>, r<RT>"
2698 // start-sanitize-vr5400
2700 // end-sanitize-vr5400
2701 // start-sanitize-r5900
2703 // end-sanitize-r5900
2705 // start-sanitize-tx19
2707 // end-sanitize-tx19
2709 GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
2713 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2714 "slti r<RT>, r<RS>, <IMMEDIATE>"
2719 // start-sanitize-vr5400
2721 // end-sanitize-vr5400
2722 // start-sanitize-r5900
2724 // end-sanitize-r5900
2726 // start-sanitize-tx19
2728 // end-sanitize-tx19
2730 GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
2734 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2735 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2740 // start-sanitize-vr5400
2742 // end-sanitize-vr5400
2743 // start-sanitize-r5900
2745 // end-sanitize-r5900
2747 // start-sanitize-tx19
2749 // end-sanitize-tx19
2751 GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
2754 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2755 "sltu r<RD>, r<RS>, r<RT>"
2760 // start-sanitize-vr5400
2762 // end-sanitize-vr5400
2763 // start-sanitize-r5900
2765 // end-sanitize-r5900
2767 // start-sanitize-tx19
2769 // end-sanitize-tx19
2771 GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
2775 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2776 "sra r<RD>, r<RT>, <SHIFT>"
2781 // start-sanitize-vr5400
2783 // end-sanitize-vr5400
2784 // start-sanitize-r5900
2786 // end-sanitize-r5900
2788 // start-sanitize-tx19
2790 // end-sanitize-tx19
2793 signed32 temp = (signed32) GPR[RT] >> s;
2794 GPR[RD] = EXTEND32 (temp);
2798 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2799 "srav r<RD>, r<RT>, r<RS>"
2804 // start-sanitize-vr5400
2806 // end-sanitize-vr5400
2807 // start-sanitize-r5900
2809 // end-sanitize-r5900
2811 // start-sanitize-tx19
2813 // end-sanitize-tx19
2815 int s = MASKED (GPR[RS], 4, 0);
2816 signed32 temp = (signed32) GPR[RT] >> s;
2817 GPR[RD] = EXTEND32 (temp);
2821 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2822 "srl r<RD>, r<RT>, <SHIFT>"
2827 // start-sanitize-vr5400
2829 // end-sanitize-vr5400
2830 // start-sanitize-r5900
2832 // end-sanitize-r5900
2834 // start-sanitize-tx19
2836 // end-sanitize-tx19
2839 unsigned32 temp = (unsigned32) GPR[RT] >> s;
2840 GPR[RD] = EXTEND32 (temp);
2844 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2845 "srlv r<RD>, r<RT>, r<RS>"
2850 // start-sanitize-vr5400
2852 // end-sanitize-vr5400
2853 // start-sanitize-r5900
2855 // end-sanitize-r5900
2857 // start-sanitize-tx19
2859 // end-sanitize-tx19
2861 int s = MASKED (GPR[RS], 4, 0);
2862 unsigned32 temp = (unsigned32) GPR[RT] >> s;
2863 GPR[RD] = EXTEND32 (temp);
2867 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2868 "sub r<RD>, r<RS>, r<RT>"
2873 // start-sanitize-vr5400
2875 // end-sanitize-vr5400
2876 // start-sanitize-r5900
2878 // end-sanitize-r5900
2880 // start-sanitize-tx19
2882 // end-sanitize-tx19
2884 ALU32_BEGIN (GPR[RS]);
2885 ALU32_SUB (GPR[RT]);
2886 ALU32_END (GPR[RD]);
2890 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2891 "subu r<RD>, r<RS>, r<RT>"
2896 // start-sanitize-vr5400
2898 // end-sanitize-vr5400
2899 // start-sanitize-r5900
2901 // end-sanitize-r5900
2903 // start-sanitize-tx19
2905 // end-sanitize-tx19
2907 GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
2911 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2912 "sw r<RT>, <OFFSET>(r<BASE>)"
2917 // start-sanitize-vr5400
2919 // end-sanitize-vr5400
2920 // start-sanitize-r5900
2922 // end-sanitize-r5900
2924 // start-sanitize-tx19
2926 // end-sanitize-tx19
2928 unsigned32 instruction = instruction_0;
2929 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2930 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2931 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2933 address_word vaddr = ((unsigned64)op1 + offset);
2936 if ((vaddr & 3) != 0)
2937 SignalExceptionAddressStore();
2940 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2942 unsigned64 memval = 0;
2943 unsigned64 memval1 = 0;
2944 unsigned64 mask = 0x7;
2946 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2947 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2948 memval = ((unsigned64) op2 << (8 * byte));
2950 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2958 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2959 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2964 // start-sanitize-vr5400
2966 // end-sanitize-vr5400
2967 // start-sanitize-r5900
2969 // end-sanitize-r5900
2971 // start-sanitize-tx19
2973 // end-sanitize-tx19
2975 unsigned32 instruction = instruction_0;
2976 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2977 int destreg = ((instruction >> 16) & 0x0000001F);
2978 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2980 address_word vaddr = ((unsigned64)op1 + offset);
2983 if ((vaddr & 3) != 0)
2984 SignalExceptionAddressStore();
2987 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2989 unsigned64 memval = 0;
2990 unsigned64 memval1 = 0;
2991 unsigned64 mask = 0x7;
2993 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2994 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2995 memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2997 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3005 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3006 "swl r<RT>, <OFFSET>(r<BASE>)"
3011 // start-sanitize-vr5400
3013 // end-sanitize-vr5400
3014 // start-sanitize-r5900
3016 // end-sanitize-r5900
3018 // start-sanitize-tx19
3020 // end-sanitize-tx19
3022 unsigned32 instruction = instruction_0;
3023 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3024 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3025 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3027 address_word vaddr = ((unsigned64)op1 + offset);
3031 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3033 unsigned64 memval = 0;
3034 unsigned64 memval1 = 0;
3035 unsigned64 mask = 3;
3036 unsigned int reverse = (ReverseEndian ? mask : 0);
3037 unsigned int bigend = (BigEndianCPU ? mask : 0);
3039 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3040 byte = ((vaddr & mask) ^ bigend);
3043 memval = (op2 >> (8 * (3 - byte)));
3044 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3047 StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
3054 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3055 "swr r<RT>, <OFFSET>(r<BASE>)"
3060 // start-sanitize-vr5400
3062 // end-sanitize-vr5400
3063 // start-sanitize-r5900
3065 // end-sanitize-r5900
3067 // start-sanitize-tx19
3069 // end-sanitize-tx19
3071 unsigned32 instruction = instruction_0;
3072 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3073 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3074 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3076 address_word vaddr = ((unsigned64)op1 + offset);
3080 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3082 unsigned64 memval = 0;
3083 unsigned64 memval1 = 0;
3084 unsigned64 mask = 3;
3085 unsigned int reverse = (ReverseEndian ? mask : 0);
3086 unsigned int bigend = (BigEndianCPU ? mask : 0);
3088 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3089 byte = ((vaddr & mask) ^ bigend);
3092 memval = ((unsigned64) op2 << (byte * 8));
3093 if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3096 StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
3103 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3109 // start-sanitize-vr5400
3111 // end-sanitize-vr5400
3112 // start-sanitize-r5900
3114 // end-sanitize-r5900
3116 // start-sanitize-tx19
3118 // end-sanitize-tx19
3120 SyncOperation (STYPE);
3124 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3130 // start-sanitize-vr5400
3132 // end-sanitize-vr5400
3133 // start-sanitize-r5900
3135 // end-sanitize-r5900
3137 // start-sanitize-tx19
3139 // end-sanitize-tx19
3141 SignalException(SystemCall, instruction_0);
3145 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3150 // start-sanitize-vr5400
3152 // end-sanitize-vr5400
3153 // start-sanitize-r5900
3155 // end-sanitize-r5900
3157 // start-sanitize-tx19
3159 // end-sanitize-tx19
3161 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3162 SignalException(Trap, instruction_0);
3166 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3167 "teqi r<RS>, <IMMEDIATE>"
3171 // start-sanitize-vr5400
3173 // end-sanitize-vr5400
3174 // start-sanitize-r5900
3176 // end-sanitize-r5900
3178 // start-sanitize-tx19
3180 // end-sanitize-tx19
3182 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3183 SignalException(Trap, instruction_0);
3187 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3192 // start-sanitize-vr5400
3194 // end-sanitize-vr5400
3195 // start-sanitize-r5900
3197 // end-sanitize-r5900
3199 // start-sanitize-tx19
3201 // end-sanitize-tx19
3203 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3204 SignalException(Trap, instruction_0);
3208 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3209 "tgei r<RS>, <IMMEDIATE>"
3213 // start-sanitize-vr5400
3215 // end-sanitize-vr5400
3216 // start-sanitize-r5900
3218 // end-sanitize-r5900
3220 // start-sanitize-tx19
3222 // end-sanitize-tx19
3224 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3225 SignalException(Trap, instruction_0);
3229 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3230 "tgeiu r<RS>, <IMMEDIATE>"
3234 // start-sanitize-vr5400
3236 // end-sanitize-vr5400
3237 // start-sanitize-r5900
3239 // end-sanitize-r5900
3241 // start-sanitize-tx19
3243 // end-sanitize-tx19
3245 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3246 SignalException(Trap, instruction_0);
3250 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3255 // start-sanitize-vr5400
3257 // end-sanitize-vr5400
3258 // start-sanitize-r5900
3260 // end-sanitize-r5900
3262 // start-sanitize-tx19
3264 // end-sanitize-tx19
3266 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3267 SignalException(Trap, instruction_0);
3271 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3276 // start-sanitize-vr5400
3278 // end-sanitize-vr5400
3279 // start-sanitize-r5900
3281 // end-sanitize-r5900
3283 // start-sanitize-tx19
3285 // end-sanitize-tx19
3287 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3288 SignalException(Trap, instruction_0);
3292 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3293 "tlti r<RS>, <IMMEDIATE>"
3297 // start-sanitize-vr5400
3299 // end-sanitize-vr5400
3300 // start-sanitize-r5900
3302 // end-sanitize-r5900
3304 // start-sanitize-tx19
3306 // end-sanitize-tx19
3308 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3309 SignalException(Trap, instruction_0);
3313 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3314 "tltiu r<RS>, <IMMEDIATE>"
3318 // start-sanitize-vr5400
3320 // end-sanitize-vr5400
3321 // start-sanitize-r5900
3323 // end-sanitize-r5900
3325 // start-sanitize-tx19
3327 // end-sanitize-tx19
3329 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3330 SignalException(Trap, instruction_0);
3334 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3339 // start-sanitize-vr5400
3341 // end-sanitize-vr5400
3342 // start-sanitize-r5900
3344 // end-sanitize-r5900
3346 // start-sanitize-tx19
3348 // end-sanitize-tx19
3350 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3351 SignalException(Trap, instruction_0);
3355 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3360 // start-sanitize-vr5400
3362 // end-sanitize-vr5400
3363 // start-sanitize-r5900
3365 // end-sanitize-r5900
3367 // start-sanitize-tx19
3369 // end-sanitize-tx19
3371 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3372 SignalException(Trap, instruction_0);
3376 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3377 "tne r<RS>, <IMMEDIATE>"
3381 // start-sanitize-vr5400
3383 // end-sanitize-vr5400
3384 // start-sanitize-r5900
3386 // end-sanitize-r5900
3388 // start-sanitize-tx19
3390 // end-sanitize-tx19
3392 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3393 SignalException(Trap, instruction_0);
3397 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3398 "xor r<RD>, r<RS>, r<RT>"
3403 // start-sanitize-vr5400
3405 // end-sanitize-vr5400
3406 // start-sanitize-r5900
3408 // end-sanitize-r5900
3410 // start-sanitize-tx19
3412 // end-sanitize-tx19
3414 GPR[RD] = GPR[RS] ^ GPR[RT];
3418 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3419 "xori r<RT>, r<RS>, <IMMEDIATE>"
3424 // start-sanitize-vr5400
3426 // end-sanitize-vr5400
3427 // start-sanitize-r5900
3429 // end-sanitize-r5900
3431 // start-sanitize-tx19
3433 // end-sanitize-tx19
3435 GPR[RT] = GPR[RS] ^ IMMEDIATE;
3440 // MIPS Architecture:
3442 // FPU Instruction Set (COP1 & COP1X)
3450 case fmt_single: return "s";
3451 case fmt_double: return "d";
3452 case fmt_word: return "w";
3453 case fmt_long: return "l";
3454 default: return "?";
3464 default: return "?";
3484 :%s::::COND:int cond
3488 case 00: return "f";
3489 case 01: return "un";
3490 case 02: return "eq";
3491 case 03: return "ueq";
3492 case 04: return "olt";
3493 case 05: return "ult";
3494 case 06: return "ole";
3495 case 07: return "ule";
3496 case 010: return "sf";
3497 case 011: return "ngle";
3498 case 012: return "seq";
3499 case 013: return "ngl";
3500 case 014: return "lt";
3501 case 015: return "nge";
3502 case 016: return "le";
3503 case 017: return "ngt";
3504 default: return "?";
3509 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3510 "abs.%s<FMT> f<FD>, f<FS>"
3515 // start-sanitize-vr5400
3517 // end-sanitize-vr5400
3518 // start-sanitize-r5900
3520 // end-sanitize-r5900
3522 // start-sanitize-tx19
3524 // end-sanitize-tx19
3526 unsigned32 instruction = instruction_0;
3527 int destreg = ((instruction >> 6) & 0x0000001F);
3528 int fs = ((instruction >> 11) & 0x0000001F);
3529 int format = ((instruction >> 21) & 0x00000007);
3531 if ((format != fmt_single) && (format != fmt_double))
3532 SignalException(ReservedInstruction,instruction);
3534 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3541 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
3542 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3547 // start-sanitize-vr5400
3549 // end-sanitize-vr5400
3550 // start-sanitize-r5900
3552 // end-sanitize-r5900
3554 // start-sanitize-tx19
3556 // end-sanitize-tx19
3558 unsigned32 instruction = instruction_0;
3559 int destreg = ((instruction >> 6) & 0x0000001F);
3560 int fs = ((instruction >> 11) & 0x0000001F);
3561 int ft = ((instruction >> 16) & 0x0000001F);
3562 int format = ((instruction >> 21) & 0x00000007);
3564 if ((format != fmt_single) && (format != fmt_double))
3565 SignalException(ReservedInstruction, instruction);
3567 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3573 // FIXME: This does not correctly resolve mipsI-mipsIV differences.
3579 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3580 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3581 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3586 // start-sanitize-vr5400
3588 // end-sanitize-vr5400
3589 // start-sanitize-r5900
3591 // end-sanitize-r5900
3593 // start-sanitize-tx19
3595 // end-sanitize-tx19
3597 unsigned32 instruction = instruction_0;
3598 signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
3599 int boolean = ((instruction >> 16) & 0x00000001);
3600 int likely = ((instruction >> 17) & 0x00000001);
3601 int condition_code = ((instruction >> 18) & 0x00000007);
3603 if (condition_code != 0)
3604 SignalException(ReservedInstruction,instruction);
3606 int condition = (PREVCOC1() == boolean);
3607 /* NOTE: The branch occurs AFTER the next instruction has been executed */
3609 DELAY_SLOT (NIA + offset);
3612 NULLIFY_NEXT_INSTRUCTION ();
3620 // FIXME: This does not correctly differentiate between mips*
3622 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3623 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3624 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3629 // start-sanitize-vr5400
3631 // end-sanitize-vr5400
3632 // start-sanitize-r5900
3634 // end-sanitize-r5900
3636 // start-sanitize-tx19
3638 // end-sanitize-tx19
3640 unsigned32 instruction = instruction_0;
3641 int cmpflags = ((instruction >> 0) & 0x0000000F);
3642 int condition_code = ((instruction >> 8) & 0x00000007);
3643 int fs = ((instruction >> 11) & 0x0000001F);
3644 int ft = ((instruction >> 16) & 0x0000001F);
3645 int format = ((instruction >> 21) & 0x00000007);
3646 if (condition_code != 0)
3648 SignalException(ReservedInstruction,instruction);
3652 if ((format != fmt_single) && (format != fmt_double))
3653 SignalException(ReservedInstruction,instruction);
3655 if (condition_code != 0)
3656 SignalException(ReservedInstruction,instruction);
3663 unsigned64 ofs = ValueFPR(fs,format);
3664 unsigned64 oft = ValueFPR(ft,format);
3665 if (NaN(ofs,format) || NaN(oft,format)) {
3666 if (FCSR & FP_ENABLE(IO)) {
3667 FCSR |= FP_CAUSE(IO);
3668 SignalExceptionFPE();
3672 less = Less(ofs,oft,format);
3673 equal = Equal(ofs,oft,format);
3677 int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
3678 SETFCC(condition_code,condition);
3686 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3687 "ceil.l.%s<FMT> f<FD>, f<FS>"
3690 // start-sanitize-vr5400
3692 // end-sanitize-vr5400
3693 // start-sanitize-r5900
3695 // end-sanitize-r5900
3697 // start-sanitize-tx19
3699 // end-sanitize-tx19
3701 unsigned32 instruction = instruction_0;
3702 int destreg = ((instruction >> 6) & 0x0000001F);
3703 int fs = ((instruction >> 11) & 0x0000001F);
3704 int format = ((instruction >> 21) & 0x00000007);
3706 if ((format != fmt_single) && (format != fmt_double))
3707 SignalException(ReservedInstruction,instruction);
3709 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3714 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3718 // start-sanitize-vr5400
3720 // end-sanitize-vr5400
3721 // start-sanitize-r5900
3723 // end-sanitize-r5900
3725 // start-sanitize-tx19
3727 // end-sanitize-tx19
3729 unsigned32 instruction = instruction_0;
3730 int destreg = ((instruction >> 6) & 0x0000001F);
3731 int fs = ((instruction >> 11) & 0x0000001F);
3732 int format = ((instruction >> 21) & 0x00000007);
3734 if ((format != fmt_single) && (format != fmt_double))
3735 SignalException(ReservedInstruction,instruction);
3737 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3744 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3745 "c%s<X>c1 r<RT>, f<FS>"
3753 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3755 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
3757 PENDING_FILL(COCIDX,0); /* special case */
3760 { /* control from */
3762 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3764 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3768 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3769 "c%s<X>c1 r<RT>, f<FS>"
3771 // start-sanitize-vr5400
3773 // end-sanitize-vr5400
3774 // start-sanitize-r5900
3776 // end-sanitize-r5900
3778 // start-sanitize-tx19
3780 // end-sanitize-tx19
3785 FCR0 = VL4_8(GPR[RT]);
3787 FCR31 = VL4_8(GPR[RT]);
3789 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3792 { /* control from */
3794 GPR[RT] = SIGNEXTEND (FCR0, 32);
3796 GPR[RT] = SIGNEXTEND (FCR31, 32);
3803 // FIXME: Does not correctly differentiate between mips*
3805 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3806 "cvt.d.%s<FMT> f<FD>, f<FS>"
3811 // start-sanitize-vr5400
3813 // end-sanitize-vr5400
3814 // start-sanitize-r5900
3816 // end-sanitize-r5900
3818 // start-sanitize-tx19
3820 // end-sanitize-tx19
3822 unsigned32 instruction = instruction_0;
3823 int destreg = ((instruction >> 6) & 0x0000001F);
3824 int fs = ((instruction >> 11) & 0x0000001F);
3825 int format = ((instruction >> 21) & 0x00000007);
3827 if ((format == fmt_double) | 0)
3828 SignalException(ReservedInstruction,instruction);
3830 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3835 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3836 "cvt.l.%s<FMT> f<FD>, f<FS>"
3839 // start-sanitize-vr5400
3841 // end-sanitize-vr5400
3842 // start-sanitize-r5900
3844 // end-sanitize-r5900
3846 // start-sanitize-tx19
3848 // end-sanitize-tx19
3850 unsigned32 instruction = instruction_0;
3851 int destreg = ((instruction >> 6) & 0x0000001F);
3852 int fs = ((instruction >> 11) & 0x0000001F);
3853 int format = ((instruction >> 21) & 0x00000007);
3855 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3856 SignalException(ReservedInstruction,instruction);
3858 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3864 // FIXME: Does not correctly differentiate between mips*
3866 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3867 "cvt.s.%s<FMT> f<FD>, f<FS>"
3872 // start-sanitize-vr5400
3874 // end-sanitize-vr5400
3875 // start-sanitize-r5900
3877 // end-sanitize-r5900
3879 // start-sanitize-tx19
3881 // end-sanitize-tx19
3883 unsigned32 instruction = instruction_0;
3884 int destreg = ((instruction >> 6) & 0x0000001F);
3885 int fs = ((instruction >> 11) & 0x0000001F);
3886 int format = ((instruction >> 21) & 0x00000007);
3888 if ((format == fmt_single) | 0)
3889 SignalException(ReservedInstruction,instruction);
3891 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3896 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3897 "cvt.w.%s<FMT> f<FD>, f<FS>"
3902 // start-sanitize-vr5400
3904 // end-sanitize-vr5400
3905 // start-sanitize-r5900
3907 // end-sanitize-r5900
3909 // start-sanitize-tx19
3911 // end-sanitize-tx19
3913 unsigned32 instruction = instruction_0;
3914 int destreg = ((instruction >> 6) & 0x0000001F);
3915 int fs = ((instruction >> 11) & 0x0000001F);
3916 int format = ((instruction >> 21) & 0x00000007);
3918 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3919 SignalException(ReservedInstruction,instruction);
3921 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3926 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3927 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3932 // start-sanitize-vr5400
3934 // end-sanitize-vr5400
3935 // start-sanitize-r5900
3937 // end-sanitize-r5900
3939 // start-sanitize-tx19
3941 // end-sanitize-tx19
3943 unsigned32 instruction = instruction_0;
3944 int destreg = ((instruction >> 6) & 0x0000001F);
3945 int fs = ((instruction >> 11) & 0x0000001F);
3946 int ft = ((instruction >> 16) & 0x0000001F);
3947 int format = ((instruction >> 21) & 0x00000007);
3949 if ((format != fmt_single) && (format != fmt_double))
3950 SignalException(ReservedInstruction,instruction);
3952 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3959 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
3960 "dm%s<X>c1 r<RT>, f<FS>"
3965 if (SizeFGR() == 64)
3966 PENDING_FILL((FS + FGRIDX),GPR[RT]);
3967 else if ((FS & 0x1) == 0)
3969 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3970 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3975 if (SizeFGR() == 64)
3976 PENDING_FILL(RT,FGR[FS]);
3977 else if ((FS & 0x1) == 0)
3978 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3980 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3983 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
3984 "dm%s<X>c1 r<RT>, f<FS>"
3986 // start-sanitize-vr5400
3988 // end-sanitize-vr5400
3989 // start-sanitize-r5900
3991 // end-sanitize-r5900
3993 // start-sanitize-tx19
3995 // end-sanitize-tx19
3999 if (SizeFGR() == 64)
4001 else if ((FS & 0x1) == 0)
4003 FGR[FS + 1] = VH4_8 (GPR[RT]);
4004 FGR[FS] = VL4_8 (GPR[RT]);
4009 if (SizeFGR() == 64)
4011 else if ((FS & 0x1) == 0)
4012 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4014 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4019 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4020 "floor.l.%s<FMT> f<FD>, f<FS>"
4023 // start-sanitize-vr5400
4025 // end-sanitize-vr5400
4026 // start-sanitize-r5900
4028 // end-sanitize-r5900
4030 // start-sanitize-tx19
4032 // end-sanitize-tx19
4034 unsigned32 instruction = instruction_0;
4035 int destreg = ((instruction >> 6) & 0x0000001F);
4036 int fs = ((instruction >> 11) & 0x0000001F);
4037 int format = ((instruction >> 21) & 0x00000007);
4039 if ((format != fmt_single) && (format != fmt_double))
4040 SignalException(ReservedInstruction,instruction);
4042 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4047 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4048 "floor.w.%s<FMT> f<FD>, f<FS>"
4052 // start-sanitize-vr5400
4054 // end-sanitize-vr5400
4055 // start-sanitize-r5900
4057 // end-sanitize-r5900
4059 // start-sanitize-tx19
4061 // end-sanitize-tx19
4063 unsigned32 instruction = instruction_0;
4064 int destreg = ((instruction >> 6) & 0x0000001F);
4065 int fs = ((instruction >> 11) & 0x0000001F);
4066 int format = ((instruction >> 21) & 0x00000007);
4068 if ((format != fmt_single) && (format != fmt_double))
4069 SignalException(ReservedInstruction,instruction);
4071 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4076 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4077 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4081 // start-sanitize-vr5400
4083 // end-sanitize-vr5400
4085 // start-sanitize-tx19
4087 // end-sanitize-tx19
4089 address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
4092 if ((vaddr & 7) != 0)
4093 SignalExceptionAddressLoad();
4097 AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
4098 LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4099 COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
4104 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4105 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4107 // start-sanitize-vr5400
4109 // end-sanitize-vr5400
4111 unsigned32 instruction = instruction_0;
4112 int destreg = ((instruction >> 6) & 0x0000001F);
4113 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4114 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4116 address_word vaddr = ((unsigned64)op1 + op2);
4119 if ((vaddr & 7) != 0)
4120 SignalExceptionAddressLoad();
4123 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4125 unsigned64 memval = 0;
4126 unsigned64 memval1 = 0;
4127 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4128 COP_LD(1,destreg,memval);;
4136 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4137 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4142 // start-sanitize-vr5400
4144 // end-sanitize-vr5400
4145 // start-sanitize-r5900
4147 // end-sanitize-r5900
4149 // start-sanitize-tx19
4151 // end-sanitize-tx19
4153 unsigned32 instruction = instruction_0;
4154 signed_word offset = EXTEND16 (OFFSET);
4155 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4156 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4158 address_word vaddr = ((uword64)op1 + offset);
4161 if ((vaddr & 3) != 0)
4162 SignalExceptionAddressLoad();
4165 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4168 uword64 memval1 = 0;
4170 unsigned int shift = 2;
4171 unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
4172 unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
4173 unsigned int byte UNUSED;
4174 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4175 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4176 byte = ((vaddr & mask) ^ (bigend << shift));
4177 COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4184 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4185 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4187 // start-sanitize-vr5400
4189 // end-sanitize-vr5400
4191 unsigned32 instruction = instruction_0;
4192 int destreg = ((instruction >> 6) & 0x0000001F);
4193 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4194 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4196 address_word vaddr = ((unsigned64)op1 + op2);
4199 if ((vaddr & 3) != 0)
4200 SignalExceptionAddressLoad();
4203 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4205 unsigned64 memval = 0;
4206 unsigned64 memval1 = 0;
4207 unsigned64 mask = 0x7;
4208 unsigned int shift = 2;
4209 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4210 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4212 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4213 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4214 byte = ((vaddr & mask) ^ (bigend << shift));
4215 COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4224 // FIXME: Not correct for mips*
4226 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
4227 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4229 // start-sanitize-vr5400
4231 // end-sanitize-vr5400
4232 // start-sanitize-r5900
4234 // end-sanitize-r5900
4236 unsigned32 instruction = instruction_0;
4237 int destreg = ((instruction >> 6) & 0x0000001F);
4238 int fs = ((instruction >> 11) & 0x0000001F);
4239 int ft = ((instruction >> 16) & 0x0000001F);
4240 int fr = ((instruction >> 21) & 0x0000001F);
4242 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4247 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
4248 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4250 // start-sanitize-vr5400
4252 // end-sanitize-vr5400
4253 // start-sanitize-r5900
4255 // end-sanitize-r5900
4257 unsigned32 instruction = instruction_0;
4258 int destreg = ((instruction >> 6) & 0x0000001F);
4259 int fs = ((instruction >> 11) & 0x0000001F);
4260 int ft = ((instruction >> 16) & 0x0000001F);
4261 int fr = ((instruction >> 21) & 0x0000001F);
4263 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4270 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4271 "m%s<X>c1 r<RT>, f<FS>"
4278 if (SizeFGR() == 64)
4279 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4281 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4284 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4286 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4287 "m%s<X>c1 r<RT>, f<FS>"
4289 // start-sanitize-vr5400
4291 // end-sanitize-vr5400
4292 // start-sanitize-r5900
4294 // end-sanitize-r5900
4296 // start-sanitize-tx19
4298 // end-sanitize-tx19
4302 if (SizeFGR() == 64)
4303 FGR[FS] = (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT]));
4305 FGR[FS] = VL4_8 (GPR[RT]);
4308 GPR[RT] = SIGNEXTEND(FGR[FS],32);
4312 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4313 "mov.%s<FMT> f<FD>, f<FS>"
4318 // start-sanitize-vr5400
4320 // end-sanitize-vr5400
4321 // start-sanitize-r5900
4323 // end-sanitize-r5900
4325 // start-sanitize-tx19
4327 // end-sanitize-tx19
4329 unsigned32 instruction = instruction_0;
4330 int destreg = ((instruction >> 6) & 0x0000001F);
4331 int fs = ((instruction >> 11) & 0x0000001F);
4332 int format = ((instruction >> 21) & 0x00000007);
4334 StoreFPR(destreg,format,ValueFPR(fs,format));
4340 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4341 "mov%s<TF> r<RD>, r<RS>, <CC>"
4343 // start-sanitize-vr5400
4345 // end-sanitize-vr5400
4346 // start-sanitize-r5900
4348 // end-sanitize-r5900
4350 if (GETFCC(CC) == TF)
4356 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4357 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4359 // start-sanitize-vr5400
4361 // end-sanitize-vr5400
4362 // start-sanitize-r5900
4364 // end-sanitize-r5900
4366 unsigned32 instruction = instruction_0;
4367 int format = ((instruction >> 21) & 0x00000007);
4369 if (GETFCC(CC) == TF)
4370 StoreFPR (FD, format, ValueFPR (FS, format));
4372 StoreFPR (FD, format, ValueFPR (FD, format));
4377 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4379 // start-sanitize-vr5400
4381 // end-sanitize-vr5400
4382 // start-sanitize-r5900
4384 // end-sanitize-r5900
4386 unsigned32 instruction = instruction_0;
4387 int destreg = ((instruction >> 6) & 0x0000001F);
4388 int fs = ((instruction >> 11) & 0x0000001F);
4389 int format = ((instruction >> 21) & 0x00000007);
4391 StoreFPR(destreg,format,ValueFPR(fs,format));
4399 // MOVT.fmt see MOVtf.fmt
4403 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4404 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4406 // start-sanitize-vr5400
4408 // end-sanitize-vr5400
4409 // start-sanitize-r5900
4411 // end-sanitize-r5900
4413 unsigned32 instruction = instruction_0;
4414 int destreg = ((instruction >> 6) & 0x0000001F);
4415 int fs = ((instruction >> 11) & 0x0000001F);
4416 int format = ((instruction >> 21) & 0x00000007);
4418 StoreFPR(destreg,format,ValueFPR(fs,format));
4424 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4425 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4427 // start-sanitize-vr5400
4429 // end-sanitize-vr5400
4430 // start-sanitize-r5900
4432 // end-sanitize-r5900
4434 unsigned32 instruction = instruction_0;
4435 int destreg = ((instruction >> 6) & 0x0000001F);
4436 int fs = ((instruction >> 11) & 0x0000001F);
4437 int ft = ((instruction >> 16) & 0x0000001F);
4438 int fr = ((instruction >> 21) & 0x0000001F);
4440 StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4446 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4447 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4449 // start-sanitize-vr5400
4451 // end-sanitize-vr5400
4452 // start-sanitize-r5900
4454 // end-sanitize-r5900
4456 unsigned32 instruction = instruction_0;
4457 int destreg = ((instruction >> 6) & 0x0000001F);
4458 int fs = ((instruction >> 11) & 0x0000001F);
4459 int ft = ((instruction >> 16) & 0x0000001F);
4460 int fr = ((instruction >> 21) & 0x0000001F);
4462 StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4470 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4471 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4476 // start-sanitize-vr5400
4478 // end-sanitize-vr5400
4479 // start-sanitize-r5900
4481 // end-sanitize-r5900
4483 // start-sanitize-tx19
4485 // end-sanitize-tx19
4487 unsigned32 instruction = instruction_0;
4488 int destreg = ((instruction >> 6) & 0x0000001F);
4489 int fs = ((instruction >> 11) & 0x0000001F);
4490 int ft = ((instruction >> 16) & 0x0000001F);
4491 int format = ((instruction >> 21) & 0x00000007);
4493 if ((format != fmt_single) && (format != fmt_double))
4494 SignalException(ReservedInstruction,instruction);
4496 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4501 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4502 "neg.%s<FMT> f<FD>, f<FS>"
4507 // start-sanitize-vr5400
4509 // end-sanitize-vr5400
4510 // start-sanitize-r5900
4512 // end-sanitize-r5900
4514 // start-sanitize-tx19
4516 // end-sanitize-tx19
4518 unsigned32 instruction = instruction_0;
4519 int destreg = ((instruction >> 6) & 0x0000001F);
4520 int fs = ((instruction >> 11) & 0x0000001F);
4521 int format = ((instruction >> 21) & 0x00000007);
4523 if ((format != fmt_single) && (format != fmt_double))
4524 SignalException(ReservedInstruction,instruction);
4526 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4532 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4533 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4535 // start-sanitize-vr5400
4537 // end-sanitize-vr5400
4539 unsigned32 instruction = instruction_0;
4540 int destreg = ((instruction >> 6) & 0x0000001F);
4541 int fs = ((instruction >> 11) & 0x0000001F);
4542 int ft = ((instruction >> 16) & 0x0000001F);
4543 int fr = ((instruction >> 21) & 0x0000001F);
4545 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4551 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4552 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4554 // start-sanitize-vr5400
4556 // end-sanitize-vr5400
4558 unsigned32 instruction = instruction_0;
4559 int destreg = ((instruction >> 6) & 0x0000001F);
4560 int fs = ((instruction >> 11) & 0x0000001F);
4561 int ft = ((instruction >> 16) & 0x0000001F);
4562 int fr = ((instruction >> 21) & 0x0000001F);
4564 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4570 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4571 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4573 // start-sanitize-vr5400
4575 // end-sanitize-vr5400
4577 unsigned32 instruction = instruction_0;
4578 int destreg = ((instruction >> 6) & 0x0000001F);
4579 int fs = ((instruction >> 11) & 0x0000001F);
4580 int ft = ((instruction >> 16) & 0x0000001F);
4581 int fr = ((instruction >> 21) & 0x0000001F);
4583 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4589 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4590 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4592 // start-sanitize-vr5400
4594 // end-sanitize-vr5400
4596 unsigned32 instruction = instruction_0;
4597 int destreg = ((instruction >> 6) & 0x0000001F);
4598 int fs = ((instruction >> 11) & 0x0000001F);
4599 int ft = ((instruction >> 16) & 0x0000001F);
4600 int fr = ((instruction >> 21) & 0x0000001F);
4602 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4607 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4608 "prefx <HINT>, r<INDEX>(r<BASE>)"
4610 // start-sanitize-vr5400
4612 // end-sanitize-vr5400
4614 unsigned32 instruction = instruction_0;
4615 int fs = ((instruction >> 11) & 0x0000001F);
4616 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4617 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4619 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4622 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4623 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4627 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4629 "recip.%s<FMT> f<FD>, f<FS>"
4630 // start-sanitize-vr5400
4632 // end-sanitize-vr5400
4634 unsigned32 instruction = instruction_0;
4635 int destreg = ((instruction >> 6) & 0x0000001F);
4636 int fs = ((instruction >> 11) & 0x0000001F);
4637 int format = ((instruction >> 21) & 0x00000007);
4639 if ((format != fmt_single) && (format != fmt_double))
4640 SignalException(ReservedInstruction,instruction);
4642 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4647 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4648 "round.l.%s<FMT> f<FD>, f<FS>"
4651 // start-sanitize-vr5400
4653 // end-sanitize-vr5400
4654 // start-sanitize-r5900
4656 // end-sanitize-r5900
4658 // start-sanitize-tx19
4660 // end-sanitize-tx19
4662 unsigned32 instruction = instruction_0;
4663 int destreg = ((instruction >> 6) & 0x0000001F);
4664 int fs = ((instruction >> 11) & 0x0000001F);
4665 int format = ((instruction >> 21) & 0x00000007);
4667 if ((format != fmt_single) && (format != fmt_double))
4668 SignalException(ReservedInstruction,instruction);
4670 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4675 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4676 "round.w.%s<FMT> f<FD>, f<FS>"
4680 // start-sanitize-vr5400
4682 // end-sanitize-vr5400
4683 // start-sanitize-r5900
4685 // end-sanitize-r5900
4687 // start-sanitize-tx19
4689 // end-sanitize-tx19
4691 unsigned32 instruction = instruction_0;
4692 int destreg = ((instruction >> 6) & 0x0000001F);
4693 int fs = ((instruction >> 11) & 0x0000001F);
4694 int format = ((instruction >> 21) & 0x00000007);
4696 if ((format != fmt_single) && (format != fmt_double))
4697 SignalException(ReservedInstruction,instruction);
4699 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4704 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4706 "rsqrt.%s<FMT> f<FD>, f<FS>"
4707 // start-sanitize-vr5400
4709 // end-sanitize-vr5400
4711 unsigned32 instruction = instruction_0;
4712 int destreg = ((instruction >> 6) & 0x0000001F);
4713 int fs = ((instruction >> 11) & 0x0000001F);
4714 int format = ((instruction >> 21) & 0x00000007);
4716 if ((format != fmt_single) && (format != fmt_double))
4717 SignalException(ReservedInstruction,instruction);
4719 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4724 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4725 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4729 // start-sanitize-vr5400
4731 // end-sanitize-vr5400
4733 // start-sanitize-tx19
4735 // end-sanitize-tx19
4737 address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
4739 if ((vaddr & 7) != 0)
4740 SignalExceptionAddressStore();
4745 AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
4746 memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
4747 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
4753 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
4755 // start-sanitize-vr5400
4757 // end-sanitize-vr5400
4759 unsigned32 instruction = instruction_0;
4760 int fs = ((instruction >> 11) & 0x0000001F);
4761 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4762 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4764 address_word vaddr = ((unsigned64)op1 + op2);
4767 if ((vaddr & 7) != 0)
4768 SignalExceptionAddressStore();
4771 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4773 unsigned64 memval = 0;
4774 unsigned64 memval1 = 0;
4775 memval = (unsigned64)COP_SD(1,fs);
4777 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
4785 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4786 "sqrt.%s<FMT> f<FD>, f<FS>"
4790 // start-sanitize-vr5400
4792 // end-sanitize-vr5400
4793 // start-sanitize-r5900
4795 // end-sanitize-r5900
4797 // start-sanitize-tx19
4799 // end-sanitize-tx19
4801 unsigned32 instruction = instruction_0;
4802 int destreg = ((instruction >> 6) & 0x0000001F);
4803 int fs = ((instruction >> 11) & 0x0000001F);
4804 int format = ((instruction >> 21) & 0x00000007);
4806 if ((format != fmt_single) && (format != fmt_double))
4807 SignalException(ReservedInstruction,instruction);
4809 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4814 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4815 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4820 // start-sanitize-vr5400
4822 // end-sanitize-vr5400
4823 // start-sanitize-r5900
4825 // end-sanitize-r5900
4827 // start-sanitize-tx19
4829 // end-sanitize-tx19
4831 unsigned32 instruction = instruction_0;
4832 int destreg = ((instruction >> 6) & 0x0000001F);
4833 int fs = ((instruction >> 11) & 0x0000001F);
4834 int ft = ((instruction >> 16) & 0x0000001F);
4835 int format = ((instruction >> 21) & 0x00000007);
4837 if ((format != fmt_single) && (format != fmt_double))
4838 SignalException(ReservedInstruction,instruction);
4840 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4846 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
4847 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4852 // start-sanitize-vr5400
4854 // end-sanitize-vr5400
4855 // start-sanitize-r5900
4857 // end-sanitize-r5900
4859 // start-sanitize-tx19
4861 // end-sanitize-tx19
4863 unsigned32 instruction = instruction_0;
4864 signed_word offset = EXTEND16 (OFFSET);
4865 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4866 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4868 address_word vaddr = ((uword64)op1 + offset);
4871 if ((vaddr & 3) != 0)
4872 SignalExceptionAddressStore();
4875 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4878 uword64 memval1 = 0;
4881 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4882 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4883 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
4885 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4893 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4894 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4896 // start-sanitize-vr5400
4898 // end-sanitize-vr5400
4900 unsigned32 instruction = instruction_0;
4901 int fs = ((instruction >> 11) & 0x0000001F);
4902 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4903 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4905 address_word vaddr = ((unsigned64)op1 + op2);
4908 if ((vaddr & 3) != 0)
4909 SignalExceptionAddressStore();
4912 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4914 unsigned64 memval = 0;
4915 unsigned64 memval1 = 0;
4916 unsigned64 mask = 0x7;
4918 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4919 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4920 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4922 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4930 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4931 "trunc.l.%s<FMT> f<FD>, f<FS>"
4934 // start-sanitize-vr5400
4936 // end-sanitize-vr5400
4937 // start-sanitize-r5900
4939 // end-sanitize-r5900
4941 // start-sanitize-tx19
4943 // end-sanitize-tx19
4945 unsigned32 instruction = instruction_0;
4946 int destreg = ((instruction >> 6) & 0x0000001F);
4947 int fs = ((instruction >> 11) & 0x0000001F);
4948 int format = ((instruction >> 21) & 0x00000007);
4950 if ((format != fmt_single) && (format != fmt_double))
4951 SignalException(ReservedInstruction,instruction);
4953 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4958 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4959 "trunc.w.%s<FMT> f<FD>, f<FS>"
4963 // start-sanitize-vr5400
4965 // end-sanitize-vr5400
4966 // start-sanitize-r5900
4968 // end-sanitize-r5900
4970 // start-sanitize-tx19
4972 // end-sanitize-tx19
4974 unsigned32 instruction = instruction_0;
4975 int destreg = ((instruction >> 6) & 0x0000001F);
4976 int fs = ((instruction >> 11) & 0x0000001F);
4977 int format = ((instruction >> 21) & 0x00000007);
4979 if ((format != fmt_single) && (format != fmt_double))
4980 SignalException(ReservedInstruction,instruction);
4982 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4988 // MIPS Architecture:
4990 // System Control Instruction Set (COP0)
4994 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5000 // start-sanitize-vr5400
5002 // end-sanitize-vr5400
5003 // start-sanitize-r5900
5005 // end-sanitize-r5900
5008 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5014 // start-sanitize-vr5400
5016 // end-sanitize-vr5400
5017 // start-sanitize-r5900
5019 // end-sanitize-r5900
5022 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5028 // start-sanitize-r5900
5030 // end-sanitize-r5900
5034 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5040 // start-sanitize-vr5400
5042 // end-sanitize-vr5400
5043 // start-sanitize-r5900
5045 // end-sanitize-r5900
5048 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5051 // start-sanitize-vr5400
5053 // end-sanitize-vr5400
5054 // start-sanitize-r5900
5056 // end-sanitize-r5900
5058 // start-sanitize-tx19
5060 // end-sanitize-tx19
5062 unsigned32 instruction = instruction_0;
5063 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5064 int hint = ((instruction >> 16) & 0x0000001F);
5065 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5067 address_word vaddr = (op1 + offset);
5070 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5071 CacheOp(hint,vaddr,paddr,instruction);
5076 010000,10000,000000000000000,111001:COP0:32::DI
5082 // start-sanitize-vr5400
5084 // end-sanitize-vr5400
5085 // start-sanitize-r5900
5087 // end-sanitize-r5900
5090 010000,10000,000000000000000,111000:COP0:32::EI
5096 // start-sanitize-vr5400
5098 // end-sanitize-vr5400
5099 // start-sanitize-r5900
5101 // end-sanitize-r5900
5104 010000,10000,000000000000000,011000:COP0:32::ERET
5108 // start-sanitize-vr5400
5110 // end-sanitize-vr5400
5111 // start-sanitize-r5900
5113 // end-sanitize-r5900
5116 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5117 "mfc0 r<RT>, r<RD> # <REGX>"
5122 // start-sanitize-vr5400
5124 // end-sanitize-vr5400
5125 // start-sanitize-r5900
5127 // end-sanitize-r5900
5129 DecodeCoproc (instruction_0);
5132 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5133 "mtc0 r<RT>, r<RD> # <REGX>"
5138 // start-sanitize-vr5400
5140 // end-sanitize-vr5400
5141 // start-sanitize-r5900
5143 // end-sanitize-r5900
5145 DecodeCoproc (instruction_0);
5149 010000,10000,000000000000000,001000:COP0:32::TLBP
5155 // start-sanitize-vr5400
5157 // end-sanitize-vr5400
5158 // start-sanitize-r5900
5160 // end-sanitize-r5900
5163 010000,10000,000000000000000,000001:COP0:32::TLBR
5169 // start-sanitize-vr5400
5171 // end-sanitize-vr5400
5172 // start-sanitize-r5900
5174 // end-sanitize-r5900
5177 010000,10000,000000000000000,000010:COP0:32::TLBWI
5183 // start-sanitize-vr5400
5185 // end-sanitize-vr5400
5186 // start-sanitize-r5900
5188 // end-sanitize-r5900
5191 010000,10000,000000000000000,000110:COP0:32::TLBWR
5197 // start-sanitize-vr5400
5199 // end-sanitize-vr5400
5200 // start-sanitize-r5900
5202 // end-sanitize-r5900
5206 // start-sanitize-vr5400
5207 :include::vr5400:vr5400.igen
5208 // end-sanitize-vr5400
5209 // start-sanitize-r5900
5210 :include::r5900:r5900.igen
5211 // end-sanitize-r5900
5213 // start-sanitize-cygnus-never
5215 // // FIXME FIXME FIXME What is this instruction?
5216 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5221 // // start-sanitize-r5900
5223 // // end-sanitize-r5900
5225 // // start-sanitize-tx19
5227 // // end-sanitize-tx19
5229 // unsigned32 instruction = instruction_0;
5230 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5231 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5232 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5234 // if (CoProcPresent(3))
5235 // SignalException(CoProcessorUnusable);
5237 // SignalException(ReservedInstruction,instruction);
5241 // end-sanitize-cygnus-never
5242 // start-sanitize-cygnus-never
5244 // // FIXME FIXME FIXME What is this?
5245 // 11100,******,00001:RR:16::SDBBP
5248 // unsigned32 instruction = instruction_0;
5249 // if (have_extendval)
5250 // SignalException (ReservedInstruction, instruction);
5252 // SignalException(DebugBreakPoint,instruction);
5256 // end-sanitize-cygnus-never
5257 // start-sanitize-cygnus-never
5259 // // FIXME FIXME FIXME What is this?
5260 // 000000,********************,001110:SPECIAL:32::SDBBP
5263 // unsigned32 instruction = instruction_0;
5265 // SignalException(DebugBreakPoint,instruction);
5269 // end-sanitize-cygnus-never
5270 // start-sanitize-cygnus-never
5272 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5273 // // isn't yet reconized by this simulator.
5274 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5277 // unsigned32 instruction = instruction_0;
5278 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5279 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5281 // CHECKHILO("Multiply-Add");
5283 // unsigned64 temp = (op1 * op2);
5284 // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5285 // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5286 // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5291 // end-sanitize-cygnus-never
5292 // start-sanitize-cygnus-never
5294 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5295 // // isn't yet reconized by this simulator.
5296 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5299 // unsigned32 instruction = instruction_0;
5300 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5301 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5303 // CHECKHILO("Multiply-Add");
5305 // unsigned64 temp = (op1 * op2);
5311 // start-sanitize-cygnus-never