sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 // start-sanitize-vr4320
  47 :model:::vr4320:mips4320:
  48 // end-sanitize-vr4320
  49 // start-sanitize-vr5400
  50 :model:::vr5400:mips5400:
  51 :model:::mdmx:mdmx:
  52 // end-sanitize-vr5400
  53 :model:::vr5000:mips5000:
  54
  55
  56
  57 // Pseudo instructions known by IGEN
  58 :internal::::illegal:
  59 {
  60   SignalException (ReservedInstruction, 0);
  61 }
  62
  63
  64 // Pseudo instructions known by interp.c
  65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  67 "rsvd <OP>"
  68 {
  69   SignalException (ReservedInstruction, instruction_0);
  70 }
  71
  72
  73
  74 // Helper:
  75 //
  76 // Simulate a 32 bit delayslot instruction
  77 //
  78
  79 :function:::address_word:delayslot32:address_word target
  80 {
  81   instruction_word delay_insn;
  82   sim_events_slip (SD, 1);
  83   DSPC = CIA;
  84   CIA = CIA + 4; /* NOTE not mips16 */
  85   STATE |= simDELAYSLOT;
  86   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  87   idecode_issue (CPU_, delay_insn, (CIA));
  88   STATE &= ~simDELAYSLOT;
  89   return target;
  90 }
  91
  92 :function:::address_word:nullify_next_insn32:
  93 {
  94   sim_events_slip (SD, 1);
  95   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  96   return CIA + 8;
  97 }
  98
  99
 100
 101 // Helper:
 102 //
 103 // Check that an access to a HI/LO register meets timing requirements
 104 //
 105 // The following requirements exist:
 106 //
 107 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 108 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 109 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 110 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 111 //
 112
 113 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 114 {
 115   if (history->mf.timestamp + 3 > time)
 116     {
 117       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 118                         itable[MY_INDEX].name,
 119                         new, (long) CIA,
 120                         (long) history->mf.cia);
 121       return 0;
 122     }
 123   return 1;
 124 }
 125
 126 :function:::int:check_mt_hilo:hilo_history *history
 127 *mipsI,mipsII,mipsIII,mipsIV:
 128 *vr5000:
 129 // start-sanitize-vr4320
 130 *vr4320:
 131 // end-sanitize-vr4320
 132 // start-sanitize-vr5400
 133 *vr5400:
 134 // end-sanitize-vr5400
 135 // start-sanitize-r5900
 136 *r5900:
 137 // end-sanitize-r5900
 138 {
 139   signed64 time = sim_events_time (SD);
 140   int ok = check_mf_cycles (SD_, history, time, "MT");
 141   history->mt.timestamp = time;
 142   history->mt.cia = CIA;
 143   return ok;
 144 }
 145
 146 :function:::int:check_mt_hilo:hilo_history *history
 147 *r3900:
 148 // start-sanitize-tx19
 149 *tx19:
 150 // end-sanitize-tx19
 151 {
 152   signed64 time = sim_events_time (SD);
 153   history->mt.timestamp = time;
 154   history->mt.cia = CIA;
 155   return 1;
 156 }
 157
 158 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 159 {
 160   signed64 time = sim_events_time (SD);
 161   int ok = 1;
 162   if (peer != NULL
 163       && peer->mt.timestamp > history->op.timestamp
 164       && history->mf.timestamp < history->op.timestamp)
 165     {
 166       /* The peer has been written to since the last OP yet we have
 167          not */
 168       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 169                         itable[MY_INDEX].name,
 170                         (long) CIA,
 171                         (long) history->op.cia,
 172                         (long) peer->mt.cia);
 173       ok = 0;
 174     }
 175   history->mf.timestamp = time;
 176   history->mf.cia = CIA;
 177   return ok;
 178 }
 179
 180 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 181 *mipsI,mipsII,mipsIII,mipsIV:
 182 *vr5000:
 183 // start-sanitize-vr4320
 184 *vr4320:
 185 // end-sanitize-vr4320
 186 // start-sanitize-vr5400
 187 *vr5400:
 188 // end-sanitize-vr5400
 189 // start-sanitize-r5900
 190 *r5900:
 191 // end-sanitize-r5900
 192 {
 193   signed64 time = sim_events_time (SD);
 194   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 195             && check_mf_cycles (SD_, lo, time, "OP"));
 196   hi->op.timestamp = time;
 197   lo->op.timestamp = time;
 198   hi->op.cia = CIA;
 199   lo->op.cia = CIA;
 200   return ok;
 201 }
 202
 203
 204 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 205 // a mf{hi,lo}
 206 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 207 *r3900:
 208 // start-sanitize-tx19
 209 *tx19:
 210 // end-sanitize-tx19
 211 {
 212   signed64 time = sim_events_time (SD);
 213   hi->op.timestamp = time;
 214   lo->op.timestamp = time;
 215   hi->op.cia = CIA;
 216   lo->op.cia = CIA;
 217   return 1;
 218 }
 219
 220 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 221 *mipsI,mipsII,mipsIII,mipsIV:
 222 *vr5000:
 223 // start-sanitize-vr4320
 224 *vr4320:
 225 // end-sanitize-vr4320
 226 // start-sanitize-vr5400
 227 *vr5400:
 228 // end-sanitize-vr5400
 229 *r3900:
 230 // start-sanitize-tx19
 231 *tx19:
 232 // end-sanitize-tx19
 233 // start-sanitize-r5900
 234 *r5900:
 235 // end-sanitize-r5900
 236 {
 237   signed64 time = sim_events_time (SD);
 238   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 239             && check_mf_cycles (SD_, lo, time, "OP"));
 240   hi->op.timestamp = time;
 241   lo->op.timestamp = time;
 242   hi->op.cia = CIA;
 243   lo->op.cia = CIA;
 244   return ok;
 245 }
 246
 247
 248
 249 //
 250 // Mips Architecture:
 251 //
 252 //        CPU Instruction Set (mipsI - mipsIV)
 253 //
 254
 255
 256
 257 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 258 "add r<RD>, r<RS>, r<RT>"
 259 *mipsI,mipsII,mipsIII,mipsIV:
 260 *vr5000:
 261 // start-sanitize-vr4320
 262 *vr4320:
 263 // end-sanitize-vr4320
 264 // start-sanitize-vr5400
 265 *vr5400:
 266 // end-sanitize-vr5400
 267 // start-sanitize-r5900
 268 *r5900:
 269 // end-sanitize-r5900
 270 *r3900:
 271 // start-sanitize-tx19
 272 *tx19:
 273 // end-sanitize-tx19
 274 {
 275   ALU32_BEGIN (GPR[RS]);
 276   ALU32_ADD (GPR[RT]);
 277   ALU32_END (GPR[RD]);
 278 }
 279
 280
 281
 282 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 283 "addi r<RT>, r<RS>, IMMEDIATE"
 284 *mipsI,mipsII,mipsIII,mipsIV:
 285 *vr5000:
 286 // start-sanitize-vr4320
 287 *vr4320:
 288 // end-sanitize-vr4320
 289 // start-sanitize-vr5400
 290 *vr5400:
 291 // end-sanitize-vr5400
 292 // start-sanitize-r5900
 293 *r5900:
 294 // end-sanitize-r5900
 295 *r3900:
 296 // start-sanitize-tx19
 297 *tx19:
 298 // end-sanitize-tx19
 299 {
 300   ALU32_BEGIN (GPR[RS]);
 301   ALU32_ADD (EXTEND16 (IMMEDIATE));
 302   ALU32_END (GPR[RT]);
 303 }
 304
 305
 306
 307 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 308 {
 309   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 310   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 311   TRACE_ALU_RESULT (GPR[rt]);
 312 }
 313
 314 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 315 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 316 *mipsI,mipsII,mipsIII,mipsIV:
 317 *vr5000:
 318 // start-sanitize-vr4320
 319 *vr4320:
 320 // end-sanitize-vr4320
 321 // start-sanitize-vr5400
 322 *vr5400:
 323 // end-sanitize-vr5400
 324 // start-sanitize-r5900
 325 *r5900:
 326 // end-sanitize-r5900
 327 *r3900:
 328 // start-sanitize-tx19
 329 *tx19:
 330 // end-sanitize-tx19
 331 {
 332   do_addiu (SD_, RS, RT, IMMEDIATE);
 333 }
 334
 335
 336
 337 :function:::void:do_addu:int rs, int rt, int rd
 338 {
 339   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 340   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 341   TRACE_ALU_RESULT (GPR[rd]);
 342 }
 343
 344 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 345 "addu r<RD>, r<RS>, r<RT>"
 346 *mipsI,mipsII,mipsIII,mipsIV:
 347 *vr5000:
 348 // start-sanitize-vr4320
 349 *vr4320:
 350 // end-sanitize-vr4320
 351 // start-sanitize-vr5400
 352 *vr5400:
 353 // end-sanitize-vr5400
 354 // start-sanitize-r5900
 355 *r5900:
 356 // end-sanitize-r5900
 357 *r3900:
 358 // start-sanitize-tx19
 359 *tx19:
 360 // end-sanitize-tx19
 361 {
 362   do_addu (SD_, RS, RT, RD);
 363 }
 364
 365
 366
 367 :function:::void:do_and:int rs, int rt, int rd
 368 {
 369   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 370   GPR[rd] = GPR[rs] & GPR[rt];
 371   TRACE_ALU_RESULT (GPR[rd]);
 372 }
 373
 374 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 375 "and r<RD>, r<RS>, r<RT>"
 376 *mipsI,mipsII,mipsIII,mipsIV:
 377 *vr5000:
 378 // start-sanitize-vr4320
 379 *vr4320:
 380 // end-sanitize-vr4320
 381 // start-sanitize-vr5400
 382 *vr5400:
 383 // end-sanitize-vr5400
 384 // start-sanitize-r5900
 385 *r5900:
 386 // end-sanitize-r5900
 387 *r3900:
 388 // start-sanitize-tx19
 389 *tx19:
 390 // end-sanitize-tx19
 391 {
 392   do_and (SD_, RS, RT, RD);
 393 }
 394
 395
 396
 397 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 398 "and r<RT>, r<RS>, <IMMEDIATE>"
 399 *mipsI,mipsII,mipsIII,mipsIV:
 400 *vr5000:
 401 // start-sanitize-vr4320
 402 *vr4320:
 403 // end-sanitize-vr4320
 404 // start-sanitize-vr5400
 405 *vr5400:
 406 // end-sanitize-vr5400
 407 // start-sanitize-r5900
 408 *r5900:
 409 // end-sanitize-r5900
 410 *r3900:
 411 // start-sanitize-tx19
 412 *tx19:
 413 // end-sanitize-tx19
 414 {
 415   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 416   GPR[RT] = GPR[RS] & IMMEDIATE;
 417   TRACE_ALU_RESULT (GPR[RT]);
 418 }
 419
 420
 421
 422 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 423 "beq r<RS>, r<RT>, <OFFSET>"
 424 *mipsI,mipsII,mipsIII,mipsIV:
 425 *vr5000:
 426 // start-sanitize-vr4320
 427 *vr4320:
 428 // end-sanitize-vr4320
 429 // start-sanitize-vr5400
 430 *vr5400:
 431 // end-sanitize-vr5400
 432 // start-sanitize-r5900
 433 *r5900:
 434 // end-sanitize-r5900
 435 *r3900:
 436 // start-sanitize-tx19
 437 *tx19:
 438 // end-sanitize-tx19
 439 {
 440   address_word offset = EXTEND16 (OFFSET) << 2;
 441   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 442     DELAY_SLOT (NIA + offset);
 443 }
 444
 445
 446
 447 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 448 "beql r<RS>, r<RT>, <OFFSET>"
 449 *mipsII:
 450 *mipsIII:
 451 *mipsIV:
 452 *vr5000:
 453 // start-sanitize-vr4320
 454 *vr4320:
 455 // end-sanitize-vr4320
 456 // start-sanitize-vr5400
 457 *vr5400:
 458 // end-sanitize-vr5400
 459 // start-sanitize-r5900
 460 *r5900:
 461 // end-sanitize-r5900
 462 *r3900:
 463 // start-sanitize-tx19
 464 *tx19:
 465 // end-sanitize-tx19
 466 {
 467   address_word offset = EXTEND16 (OFFSET) << 2;
 468   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 469     DELAY_SLOT (NIA + offset);
 470   else
 471     NULLIFY_NEXT_INSTRUCTION ();
 472 }
 473
 474
 475
 476 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 477 "bgez r<RS>, <OFFSET>"
 478 *mipsI,mipsII,mipsIII,mipsIV:
 479 *vr5000:
 480 // start-sanitize-vr4320
 481 *vr4320:
 482 // end-sanitize-vr4320
 483 // start-sanitize-vr5400
 484 *vr5400:
 485 // end-sanitize-vr5400
 486 // start-sanitize-r5900
 487 *r5900:
 488 // end-sanitize-r5900
 489 *r3900:
 490 // start-sanitize-tx19
 491 *tx19:
 492 // end-sanitize-tx19
 493 {
 494   address_word offset = EXTEND16 (OFFSET) << 2;
 495   if ((signed_word) GPR[RS] >= 0)
 496     DELAY_SLOT (NIA + offset);
 497 }
 498
 499
 500
 501 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 502 "bgezal r<RS>, <OFFSET>"
 503 *mipsI,mipsII,mipsIII,mipsIV:
 504 *vr5000:
 505 // start-sanitize-vr4320
 506 *vr4320:
 507 // end-sanitize-vr4320
 508 // start-sanitize-vr5400
 509 *vr5400:
 510 // end-sanitize-vr5400
 511 // start-sanitize-r5900
 512 *r5900:
 513 // end-sanitize-r5900
 514 *r3900:
 515 // start-sanitize-tx19
 516 *tx19:
 517 // end-sanitize-tx19
 518 {
 519   address_word offset = EXTEND16 (OFFSET) << 2;
 520   RA = (CIA + 8);
 521   if ((signed_word) GPR[RS] >= 0)
 522     DELAY_SLOT (NIA + offset);
 523 }
 524
 525
 526
 527 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 528 "bgezall r<RS>, <OFFSET>"
 529 *mipsII:
 530 *mipsIII:
 531 *mipsIV:
 532 *vr5000:
 533 // start-sanitize-vr4320
 534 *vr4320:
 535 // end-sanitize-vr4320
 536 // start-sanitize-vr5400
 537 *vr5400:
 538 // end-sanitize-vr5400
 539 // start-sanitize-r5900
 540 *r5900:
 541 // end-sanitize-r5900
 542 *r3900:
 543 // start-sanitize-tx19
 544 *tx19:
 545 // end-sanitize-tx19
 546 {
 547   address_word offset = EXTEND16 (OFFSET) << 2;
 548   RA = (CIA + 8);
 549   /* NOTE: The branch occurs AFTER the next instruction has been
 550      executed */
 551   if ((signed_word) GPR[RS] >= 0)
 552     DELAY_SLOT (NIA + offset);
 553   else
 554     NULLIFY_NEXT_INSTRUCTION ();
 555 }
 556
 557
 558
 559 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 560 "bgezl r<RS>, <OFFSET>"
 561 *mipsII:
 562 *mipsIII:
 563 *mipsIV:
 564 *vr5000:
 565 // start-sanitize-vr4320
 566 *vr4320:
 567 // end-sanitize-vr4320
 568 // start-sanitize-vr5400
 569 *vr5400:
 570 // end-sanitize-vr5400
 571 // start-sanitize-r5900
 572 *r5900:
 573 // end-sanitize-r5900
 574 *r3900:
 575 // start-sanitize-tx19
 576 *tx19:
 577 // end-sanitize-tx19
 578 {
 579   address_word offset = EXTEND16 (OFFSET) << 2;
 580   if ((signed_word) GPR[RS] >= 0)
 581     DELAY_SLOT (NIA + offset);
 582   else
 583     NULLIFY_NEXT_INSTRUCTION ();
 584 }
 585
 586
 587
 588 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 589 "bgtz r<RS>, <OFFSET>"
 590 *mipsI,mipsII,mipsIII,mipsIV:
 591 *vr5000:
 592 // start-sanitize-vr4320
 593 *vr4320:
 594 // end-sanitize-vr4320
 595 // start-sanitize-vr5400
 596 *vr5400:
 597 // end-sanitize-vr5400
 598 // start-sanitize-r5900
 599 *r5900:
 600 // end-sanitize-r5900
 601 *r3900:
 602 // start-sanitize-tx19
 603 *tx19:
 604 // end-sanitize-tx19
 605 {
 606   address_word offset = EXTEND16 (OFFSET) << 2;
 607   if ((signed_word) GPR[RS] > 0)
 608     DELAY_SLOT (NIA + offset);
 609 }
 610
 611
 612
 613 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 614 "bgtzl r<RS>, <OFFSET>"
 615 *mipsII:
 616 *mipsIII:
 617 *mipsIV:
 618 *vr5000:
 619 // start-sanitize-vr4320
 620 *vr4320:
 621 // end-sanitize-vr4320
 622 // start-sanitize-vr5400
 623 *vr5400:
 624 // end-sanitize-vr5400
 625 // start-sanitize-r5900
 626 *r5900:
 627 // end-sanitize-r5900
 628 *r3900:
 629 // start-sanitize-tx19
 630 *tx19:
 631 // end-sanitize-tx19
 632 {
 633   address_word offset = EXTEND16 (OFFSET) << 2;
 634   /* NOTE: The branch occurs AFTER the next instruction has been
 635      executed */
 636   if ((signed_word) GPR[RS] > 0)
 637     DELAY_SLOT (NIA + offset);
 638   else
 639     NULLIFY_NEXT_INSTRUCTION ();
 640 }
 641
 642
 643
 644 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 645 "blez r<RS>, <OFFSET>"
 646 *mipsI,mipsII,mipsIII,mipsIV:
 647 *vr5000:
 648 // start-sanitize-vr4320
 649 *vr4320:
 650 // end-sanitize-vr4320
 651 // start-sanitize-vr5400
 652 *vr5400:
 653 // end-sanitize-vr5400
 654 // start-sanitize-r5900
 655 *r5900:
 656 // end-sanitize-r5900
 657 *r3900:
 658 // start-sanitize-tx19
 659 *tx19:
 660 // end-sanitize-tx19
 661 {
 662   address_word offset = EXTEND16 (OFFSET) << 2;
 663   /* NOTE: The branch occurs AFTER the next instruction has been
 664      executed */
 665   if ((signed_word) GPR[RS] <= 0)
 666     DELAY_SLOT (NIA + offset);
 667 }
 668
 669
 670
 671 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 672 "bgezl r<RS>, <OFFSET>"
 673 *mipsII:
 674 *mipsIII:
 675 *mipsIV:
 676 *vr5000:
 677 // start-sanitize-vr4320
 678 *vr4320:
 679 // end-sanitize-vr4320
 680 // start-sanitize-vr5400
 681 *vr5400:
 682 // end-sanitize-vr5400
 683 // start-sanitize-r5900
 684 *r5900:
 685 // end-sanitize-r5900
 686 *r3900:
 687 // start-sanitize-tx19
 688 *tx19:
 689 // end-sanitize-tx19
 690 {
 691   address_word offset = EXTEND16 (OFFSET) << 2;
 692   if ((signed_word) GPR[RS] <= 0)
 693     DELAY_SLOT (NIA + offset);
 694   else
 695     NULLIFY_NEXT_INSTRUCTION ();
 696 }
 697
 698
 699
 700 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 701 "bltz r<RS>, <OFFSET>"
 702 *mipsI,mipsII,mipsIII,mipsIV:
 703 *vr5000:
 704 // start-sanitize-vr4320
 705 *vr4320:
 706 // end-sanitize-vr4320
 707 // start-sanitize-vr5400
 708 *vr5400:
 709 // end-sanitize-vr5400
 710 // start-sanitize-r5900
 711 *r5900:
 712 // end-sanitize-r5900
 713 *r3900:
 714 // start-sanitize-tx19
 715 *tx19:
 716 // end-sanitize-tx19
 717 {
 718   address_word offset = EXTEND16 (OFFSET) << 2;
 719   if ((signed_word) GPR[RS] < 0)
 720     DELAY_SLOT (NIA + offset);
 721 }
 722
 723
 724
 725 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 726 "bltzal r<RS>, <OFFSET>"
 727 *mipsI,mipsII,mipsIII,mipsIV:
 728 *vr5000:
 729 // start-sanitize-vr4320
 730 *vr4320:
 731 // end-sanitize-vr4320
 732 // start-sanitize-vr5400
 733 *vr5400:
 734 // end-sanitize-vr5400
 735 // start-sanitize-r5900
 736 *r5900:
 737 // end-sanitize-r5900
 738 *r3900:
 739 // start-sanitize-tx19
 740 *tx19:
 741 // end-sanitize-tx19
 742 {
 743   address_word offset = EXTEND16 (OFFSET) << 2;
 744   RA = (CIA + 8);
 745   /* NOTE: The branch occurs AFTER the next instruction has been
 746      executed */
 747   if ((signed_word) GPR[RS] < 0)
 748     DELAY_SLOT (NIA + offset);
 749 }
 750
 751
 752
 753 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 754 "bltzall r<RS>, <OFFSET>"
 755 *mipsII:
 756 *mipsIII:
 757 *mipsIV:
 758 *vr5000:
 759 // start-sanitize-vr4320
 760 *vr4320:
 761 // end-sanitize-vr4320
 762 // start-sanitize-vr5400
 763 *vr5400:
 764 // end-sanitize-vr5400
 765 // start-sanitize-r5900
 766 *r5900:
 767 // end-sanitize-r5900
 768 *r3900:
 769 // start-sanitize-tx19
 770 *tx19:
 771 // end-sanitize-tx19
 772 {
 773   address_word offset = EXTEND16 (OFFSET) << 2;
 774   RA = (CIA + 8);
 775   if ((signed_word) GPR[RS] < 0)
 776     DELAY_SLOT (NIA + offset);
 777   else
 778     NULLIFY_NEXT_INSTRUCTION ();
 779 }
 780
 781
 782
 783 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 784 "bltzl r<RS>, <OFFSET>"
 785 *mipsII:
 786 *mipsIII:
 787 *mipsIV:
 788 *vr5000:
 789 // start-sanitize-vr4320
 790 *vr4320:
 791 // end-sanitize-vr4320
 792 // start-sanitize-vr5400
 793 *vr5400:
 794 // end-sanitize-vr5400
 795 // start-sanitize-r5900
 796 *r5900:
 797 // end-sanitize-r5900
 798 *r3900:
 799 // start-sanitize-tx19
 800 *tx19:
 801 // end-sanitize-tx19
 802 {
 803   address_word offset = EXTEND16 (OFFSET) << 2;
 804   /* NOTE: The branch occurs AFTER the next instruction has been
 805      executed */
 806   if ((signed_word) GPR[RS] < 0)
 807     DELAY_SLOT (NIA + offset);
 808   else
 809     NULLIFY_NEXT_INSTRUCTION ();
 810 }
 811
 812
 813
 814 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 815 "bne r<RS>, r<RT>, <OFFSET>"
 816 *mipsI,mipsII,mipsIII,mipsIV:
 817 *vr5000:
 818 // start-sanitize-vr4320
 819 *vr4320:
 820 // end-sanitize-vr4320
 821 // start-sanitize-vr5400
 822 *vr5400:
 823 // end-sanitize-vr5400
 824 // start-sanitize-r5900
 825 *r5900:
 826 // end-sanitize-r5900
 827 *r3900:
 828 // start-sanitize-tx19
 829 *tx19:
 830 // end-sanitize-tx19
 831 {
 832   address_word offset = EXTEND16 (OFFSET) << 2;
 833   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 834     DELAY_SLOT (NIA + offset);
 835 }
 836
 837
 838
 839 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 840 "bnel r<RS>, r<RT>, <OFFSET>"
 841 *mipsII:
 842 *mipsIII:
 843 *mipsIV:
 844 *vr5000:
 845 // start-sanitize-vr4320
 846 *vr4320:
 847 // end-sanitize-vr4320
 848 // start-sanitize-vr5400
 849 *vr5400:
 850 // end-sanitize-vr5400
 851 // start-sanitize-r5900
 852 *r5900:
 853 // end-sanitize-r5900
 854 *r3900:
 855 // start-sanitize-tx19
 856 *tx19:
 857 // end-sanitize-tx19
 858 {
 859   address_word offset = EXTEND16 (OFFSET) << 2;
 860   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 861     DELAY_SLOT (NIA + offset);
 862   else
 863     NULLIFY_NEXT_INSTRUCTION ();
 864 }
 865
 866
 867
 868 000000,20.CODE,001101:SPECIAL:32::BREAK
 869 "break"
 870 *mipsI,mipsII,mipsIII,mipsIV:
 871 *vr5000:
 872 // start-sanitize-vr4320
 873 *vr4320:
 874 // end-sanitize-vr4320
 875 // start-sanitize-vr5400
 876 *vr5400:
 877 // end-sanitize-vr5400
 878 // start-sanitize-r5900
 879 *r5900:
 880 // end-sanitize-r5900
 881 *r3900:
 882 // start-sanitize-tx19
 883 *tx19:
 884 // end-sanitize-tx19
 885 {
 886   SignalException(BreakPoint, instruction_0);
 887 }
 888
 889
 890
 891 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 892 "cop<ZZ> <COP_FUN>"
 893 *mipsI,mipsII,mipsIII,mipsIV:
 894 // start-sanitize-r5900
 895 *r5900:
 896 // end-sanitize-r5900
 897 *r3900:
 898 // start-sanitize-tx19
 899 *tx19:
 900 // end-sanitize-tx19
 901 {
 902   DecodeCoproc (instruction_0);
 903 }
 904
 905
 906
 907 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 908 "dadd r<RD>, r<RS>, r<RT>"
 909 *mipsIII:
 910 *mipsIV:
 911 *vr5000:
 912 // start-sanitize-vr4320
 913 *vr4320:
 914 // end-sanitize-vr4320
 915 // start-sanitize-vr5400
 916 *vr5400:
 917 // end-sanitize-vr5400
 918 // start-sanitize-r5900
 919 *r5900:
 920 // end-sanitize-r5900
 921 // start-sanitize-tx19
 922 *tx19:
 923 // end-sanitize-tx19
 924 {
 925   /* this check's for overflow */
 926   ALU64_BEGIN (GPR[RS]);
 927   ALU64_ADD (GPR[RT]);
 928   ALU64_END (GPR[RD]);
 929 }
 930
 931
 932
 933 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 934 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 935 *mipsIII:
 936 *mipsIV:
 937 *vr5000:
 938 // start-sanitize-vr4320
 939 *vr4320:
 940 // end-sanitize-vr4320
 941 // start-sanitize-vr5400
 942 *vr5400:
 943 // end-sanitize-vr5400
 944 // start-sanitize-r5900
 945 *r5900:
 946 // end-sanitize-r5900
 947 // start-sanitize-tx19
 948 *tx19:
 949 // end-sanitize-tx19
 950 {
 951   ALU64_BEGIN (GPR[RS]);
 952   ALU64_ADD (EXTEND16 (IMMEDIATE));
 953   ALU64_END (GPR[RT]);
 954 }
 955
 956
 957
 958 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
 959 {
 960   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 961   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
 962   TRACE_ALU_RESULT (GPR[rt]);
 963 }
 964
 965 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 966 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 967 *mipsIII:
 968 *mipsIV:
 969 *vr5000:
 970 // start-sanitize-vr4320
 971 *vr4320:
 972 // end-sanitize-vr4320
 973 // start-sanitize-vr5400
 974 *vr5400:
 975 // end-sanitize-vr5400
 976 // start-sanitize-r5900
 977 *r5900:
 978 // end-sanitize-r5900
 979 // start-sanitize-tx19
 980 *tx19:
 981 // end-sanitize-tx19
 982 {
 983   do_daddiu (SD_, RS, RT, IMMEDIATE);
 984 }
 985
 986
 987
 988 :function:::void:do_daddu:int rs, int rt, int rd
 989 {
 990   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 991   GPR[rd] = GPR[rs] + GPR[rt];
 992   TRACE_ALU_RESULT (GPR[rd]);
 993 }
 994
 995 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 996 "daddu r<RD>, r<RS>, r<RT>"
 997 *mipsIII:
 998 *mipsIV:
 999 *vr5000:
1000 // start-sanitize-vr4320
1001 *vr4320:
1002 // end-sanitize-vr4320
1003 // start-sanitize-vr5400
1004 *vr5400:
1005 // end-sanitize-vr5400
1006 // start-sanitize-r5900
1007 *r5900:
1008 // end-sanitize-r5900
1009 // start-sanitize-tx19
1010 *tx19:
1011 // end-sanitize-tx19
1012 {
1013   do_daddu (SD_, RS, RT, RD);
1014 }
1015
1016
1017
1018 :function:64::void:do_ddiv:int rs, int rt
1019 {
1020   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1021   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1022   {
1023     signed64 n = GPR[rs];
1024     signed64 d = GPR[rt];
1025     if (d == 0)
1026       {
1027         LO = SIGNED64 (0x8000000000000000);
1028         HI = 0;
1029       }
1030     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1031       {
1032         LO = SIGNED64 (0x8000000000000000);
1033         HI = 0;
1034       }
1035     else
1036       {
1037         LO = (n / d);
1038         HI = (n % d);
1039       }
1040   }
1041   TRACE_ALU_RESULT2 (HI, LO);
1042 }
1043
1044 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1045 "ddiv r<RS>, r<RT>"
1046 *mipsIII:
1047 *mipsIV:
1048 *vr5000:
1049 // start-sanitize-vr4320
1050 *vr4320:
1051 // end-sanitize-vr4320
1052 // start-sanitize-vr5400
1053 *vr5400:
1054 // end-sanitize-vr5400
1055 // start-sanitize-r5900
1056 *r5900:
1057 // end-sanitize-r5900
1058 // start-sanitize-tx19
1059 *tx19:
1060 // end-sanitize-tx19
1061 {
1062   do_ddiv (SD_, RS, RT);
1063 }
1064
1065
1066
1067 :function:64::void:do_ddivu:int rs, int rt
1068 {
1069   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1070   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1071   {
1072     unsigned64 n = GPR[rs];
1073     unsigned64 d = GPR[rt];
1074     if (d == 0)
1075       {
1076         LO = SIGNED64 (0x8000000000000000);
1077         HI = 0;
1078       }
1079     else
1080       {
1081         LO = (n / d);
1082         HI = (n % d);
1083       }
1084   }
1085   TRACE_ALU_RESULT2 (HI, LO);
1086 }
1087
1088 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1089 "ddivu r<RS>, r<RT>"
1090 *mipsIII:
1091 *mipsIV:
1092 *vr5000:
1093 // start-sanitize-vr4320
1094 *vr4320:
1095 // end-sanitize-vr4320
1096 // start-sanitize-vr5400
1097 *vr5400:
1098 // end-sanitize-vr5400
1099 // start-sanitize-tx19
1100 *tx19:
1101 // end-sanitize-tx19
1102 {
1103   do_ddivu (SD_, RS, RT);
1104 }
1105
1106
1107
1108 :function:::void:do_div:int rs, int rt
1109 {
1110   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1111   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1112   {
1113     signed32 n = GPR[rs];
1114     signed32 d = GPR[rt];
1115     if (d == 0)
1116       {
1117         LO = EXTEND32 (0x80000000);
1118         HI = EXTEND32 (0);
1119       }
1120     else if (n == SIGNED32 (0x80000000) && d == -1)
1121       {
1122         LO = EXTEND32 (0x80000000);
1123         HI = EXTEND32 (0);
1124       }
1125     else
1126       {
1127         LO = EXTEND32 (n / d);
1128         HI = EXTEND32 (n % d);
1129       }
1130   }
1131   TRACE_ALU_RESULT2 (HI, LO);
1132 }
1133
1134 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1135 "div r<RS>, r<RT>"
1136 *mipsI,mipsII,mipsIII,mipsIV:
1137 *vr5000:
1138 // start-sanitize-vr4320
1139 *vr4320:
1140 // end-sanitize-vr4320
1141 // start-sanitize-vr5400
1142 *vr5400:
1143 // end-sanitize-vr5400
1144 // start-sanitize-r5900
1145 *r5900:
1146 // end-sanitize-r5900
1147 *r3900:
1148 // start-sanitize-tx19
1149 *tx19:
1150 // end-sanitize-tx19
1151 {
1152   do_div (SD_, RS, RT);
1153 }
1154
1155
1156
1157 :function:::void:do_divu:int rs, int rt
1158 {
1159   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1160   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1161   {
1162     unsigned32 n = GPR[rs];
1163     unsigned32 d = GPR[rt];
1164     if (d == 0)
1165       {
1166         LO = EXTEND32 (0x80000000);
1167         HI = EXTEND32 (0);
1168       }
1169    else
1170      {
1171        LO = EXTEND32 (n / d);
1172        HI = EXTEND32 (n % d);
1173      }
1174   }
1175   TRACE_ALU_RESULT2 (HI, LO);
1176 }
1177
1178 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1179 "divu r<RS>, r<RT>"
1180 *mipsI,mipsII,mipsIII,mipsIV:
1181 *vr5000:
1182 // start-sanitize-vr4320
1183 *vr4320:
1184 // end-sanitize-vr4320
1185 // start-sanitize-vr5400
1186 *vr5400:
1187 // end-sanitize-vr5400
1188 // start-sanitize-r5900
1189 *r5900:
1190 // end-sanitize-r5900
1191 *r3900:
1192 // start-sanitize-tx19
1193 *tx19:
1194 // end-sanitize-tx19
1195 {
1196   do_divu (SD_, RS, RT);
1197 }
1198
1199
1200
1201 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1202 {
1203   unsigned64 lo;
1204   unsigned64 hi;
1205   unsigned64 m00;
1206   unsigned64 m01;
1207   unsigned64 m10;
1208   unsigned64 m11;
1209   unsigned64 mid;
1210   int sign;
1211   unsigned64 op1 = GPR[rs];
1212   unsigned64 op2 = GPR[rt];
1213   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1214   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1215   /* make signed multiply unsigned */
1216   sign = 0;
1217   if (signed_p)
1218     {
1219       if (op1 < 0)
1220         {
1221           op1 = - op1;
1222           ++sign;
1223         }
1224       if (op2 < 0)
1225         {
1226           op2 = - op2;
1227           ++sign;
1228         }
1229     }
1230   /* multuply out the 4 sub products */
1231   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1232   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1233   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1234   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1235   /* add the products */
1236   mid = ((unsigned64) VH4_8 (m00)
1237          + (unsigned64) VL4_8 (m10)
1238          + (unsigned64) VL4_8 (m01));
1239   lo = U8_4 (mid, m00);
1240   hi = (m11
1241         + (unsigned64) VH4_8 (mid)
1242         + (unsigned64) VH4_8 (m01)
1243         + (unsigned64) VH4_8 (m10));
1244   /* fix the sign */
1245   if (sign & 1)
1246     {
1247       lo = -lo;
1248       if (lo == 0)
1249         hi = -hi;
1250       else
1251         hi = -hi - 1;
1252     }
1253   /* save the result HI/LO (and a gpr) */
1254   LO = lo;
1255   HI = hi;
1256   if (rd != 0)
1257     GPR[rd] = lo;
1258   TRACE_ALU_RESULT2 (HI, LO);
1259 }
1260
1261 :function:::void:do_dmult:int rs, int rt, int rd
1262 {
1263   do_dmultx (SD_, rs, rt, rd, 1);
1264 }
1265
1266 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1267 "dmult r<RS>, r<RT>"
1268 *mipsIII,mipsIV:
1269 // start-sanitize-tx19
1270 *tx19:
1271 // end-sanitize-tx19
1272 // start-sanitize-vr4320
1273 *vr4320:
1274 // end-sanitize-vr4320
1275 {
1276   do_dmult (SD_, RS, RT, 0);
1277 }
1278
1279 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1280 "dmult r<RS>, r<RT>":RD == 0
1281 "dmult r<RD>, r<RS>, r<RT>"
1282 *vr5000:
1283 // start-sanitize-vr5400
1284 *vr5400:
1285 // end-sanitize-vr5400
1286 {
1287   do_dmult (SD_, RS, RT, RD);
1288 }
1289
1290
1291
1292 :function:::void:do_dmultu:int rs, int rt, int rd
1293 {
1294   do_dmultx (SD_, rs, rt, rd, 0);
1295 }
1296
1297 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1298 "dmultu r<RS>, r<RT>"
1299 *mipsIII,mipsIV:
1300 // start-sanitize-tx19
1301 *tx19:
1302 // end-sanitize-tx19
1303 // start-sanitize-vr4320
1304 *vr4320:
1305 // end-sanitize-vr4320
1306 {
1307   do_dmultu (SD_, RS, RT, 0);
1308 }
1309
1310 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1311 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1312 "dmultu r<RS>, r<RT>"
1313 *vr5000:
1314 // start-sanitize-vr5400
1315 *vr5400:
1316 // end-sanitize-vr5400
1317 {
1318   do_dmultu (SD_, RS, RT, RD);
1319 }
1320
1321
1322
1323 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1324 "dsll r<RD>, r<RT>, <SHIFT>"
1325 *mipsIII:
1326 *mipsIV:
1327 *vr5000:
1328 // start-sanitize-vr4320
1329 *vr4320:
1330 // end-sanitize-vr4320
1331 // start-sanitize-vr5400
1332 *vr5400:
1333 // end-sanitize-vr5400
1334 // start-sanitize-r5900
1335 *r5900:
1336 // end-sanitize-r5900
1337 // start-sanitize-tx19
1338 *tx19:
1339 // end-sanitize-tx19
1340 {
1341   int s = SHIFT;
1342   GPR[RD] = GPR[RT] << s;
1343 }
1344
1345
1346 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1347 "dsll32 r<RD>, r<RT>, <SHIFT>"
1348 *mipsIII:
1349 *mipsIV:
1350 *vr5000:
1351 // start-sanitize-vr4320
1352 *vr4320:
1353 // end-sanitize-vr4320
1354 // start-sanitize-vr5400
1355 *vr5400:
1356 // end-sanitize-vr5400
1357 // start-sanitize-r5900
1358 *r5900:
1359 // end-sanitize-r5900
1360 // start-sanitize-tx19
1361 *tx19:
1362 // end-sanitize-tx19
1363 {
1364   int s = 32 + SHIFT;
1365   GPR[RD] = GPR[RT] << s;
1366 }
1367
1368
1369
1370 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1371 "dsllv r<RD>, r<RT>, r<RS>"
1372 *mipsIII:
1373 *mipsIV:
1374 *vr5000:
1375 // start-sanitize-vr4320
1376 *vr4320:
1377 // end-sanitize-vr4320
1378 // start-sanitize-vr5400
1379 *vr5400:
1380 // end-sanitize-vr5400
1381 // start-sanitize-r5900
1382 *r5900:
1383 // end-sanitize-r5900
1384 // start-sanitize-tx19
1385 *tx19:
1386 // end-sanitize-tx19
1387 {
1388   int s = MASKED64 (GPR[RS], 5, 0);
1389   GPR[RD] = GPR[RT] << s;
1390 }
1391
1392
1393
1394 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1395 "dsra r<RD>, r<RT>, <SHIFT>"
1396 *mipsIII:
1397 *mipsIV:
1398 *vr5000:
1399 // start-sanitize-vr4320
1400 *vr4320:
1401 // end-sanitize-vr4320
1402 // start-sanitize-vr5400
1403 *vr5400:
1404 // end-sanitize-vr5400
1405 // start-sanitize-r5900
1406 *r5900:
1407 // end-sanitize-r5900
1408 // start-sanitize-tx19
1409 *tx19:
1410 // end-sanitize-tx19
1411 {
1412   int s = SHIFT;
1413   GPR[RD] = ((signed64) GPR[RT]) >> s;
1414 }
1415
1416
1417 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1418 "dsra32 r<RT>, r<RD>, <SHIFT>"
1419 *mipsIII:
1420 *mipsIV:
1421 *vr5000:
1422 // start-sanitize-vr4320
1423 *vr4320:
1424 // end-sanitize-vr4320
1425 // start-sanitize-vr5400
1426 *vr5400:
1427 // end-sanitize-vr5400
1428 // start-sanitize-r5900
1429 *r5900:
1430 // end-sanitize-r5900
1431 // start-sanitize-tx19
1432 *tx19:
1433 // end-sanitize-tx19
1434 {
1435   int s = 32 + SHIFT;
1436   GPR[RD] = ((signed64) GPR[RT]) >> s;
1437 }
1438
1439
1440 :function:::void:do_dsrav:int rs, int rt, int rd
1441 {
1442   int s = MASKED64 (GPR[rs], 5, 0);
1443   TRACE_ALU_INPUT2 (GPR[rt], s);
1444   GPR[rd] = ((signed64) GPR[rt]) >> s;
1445   TRACE_ALU_RESULT (GPR[rd]);
1446 }
1447
1448 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1449 "dsra32 r<RT>, r<RD>, r<RS>"
1450 *mipsIII:
1451 *mipsIV:
1452 *vr5000:
1453 // start-sanitize-vr4320
1454 *vr4320:
1455 // end-sanitize-vr4320
1456 // start-sanitize-vr5400
1457 *vr5400:
1458 // end-sanitize-vr5400
1459 // start-sanitize-r5900
1460 *r5900:
1461 // end-sanitize-r5900
1462 // start-sanitize-tx19
1463 *tx19:
1464 // end-sanitize-tx19
1465 {
1466   do_dsrav (SD_, RS, RT, RD);
1467 }
1468
1469
1470 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1471 "dsrl r<RD>, r<RT>, <SHIFT>"
1472 *mipsIII:
1473 *mipsIV:
1474 *vr5000:
1475 // start-sanitize-vr4320
1476 *vr4320:
1477 // end-sanitize-vr4320
1478 // start-sanitize-vr5400
1479 *vr5400:
1480 // end-sanitize-vr5400
1481 // start-sanitize-r5900
1482 *r5900:
1483 // end-sanitize-r5900
1484 // start-sanitize-tx19
1485 *tx19:
1486 // end-sanitize-tx19
1487 {
1488   int s = SHIFT;
1489   GPR[RD] = (unsigned64) GPR[RT] >> s;
1490 }
1491
1492
1493 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1494 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1495 *mipsIII:
1496 *mipsIV:
1497 *vr5000:
1498 // start-sanitize-vr4320
1499 *vr4320:
1500 // end-sanitize-vr4320
1501 // start-sanitize-vr5400
1502 *vr5400:
1503 // end-sanitize-vr5400
1504 // start-sanitize-r5900
1505 *r5900:
1506 // end-sanitize-r5900
1507 // start-sanitize-tx19
1508 *tx19:
1509 // end-sanitize-tx19
1510 {
1511   int s = 32 + SHIFT;
1512   GPR[RD] = (unsigned64) GPR[RT] >> s;
1513 }
1514
1515
1516 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1517 "dsrl32 r<RD>, r<RT>, r<RS>"
1518 *mipsIII:
1519 *mipsIV:
1520 *vr5000:
1521 // start-sanitize-vr4320
1522 *vr4320:
1523 // end-sanitize-vr4320
1524 // start-sanitize-vr5400
1525 *vr5400:
1526 // end-sanitize-vr5400
1527 // start-sanitize-r5900
1528 *r5900:
1529 // end-sanitize-r5900
1530 // start-sanitize-tx19
1531 *tx19:
1532 // end-sanitize-tx19
1533 {
1534   int s = MASKED64 (GPR[RS], 5, 0);
1535   GPR[RD] = (unsigned64) GPR[RT] >> s;
1536 }
1537
1538
1539 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1540 "dsub r<RD>, r<RS>, r<RT>"
1541 *mipsIII:
1542 *mipsIV:
1543 *vr5000:
1544 // start-sanitize-vr4320
1545 *vr4320:
1546 // end-sanitize-vr4320
1547 // start-sanitize-vr5400
1548 *vr5400:
1549 // end-sanitize-vr5400
1550 // start-sanitize-r5900
1551 *r5900:
1552 // end-sanitize-r5900
1553 // start-sanitize-tx19
1554 *tx19:
1555 // end-sanitize-tx19
1556 {
1557   ALU64_BEGIN (GPR[RS]);
1558   ALU64_SUB (GPR[RT]);
1559   ALU64_END (GPR[RD]);
1560 }
1561
1562
1563 :function:::void:do_dsubu:int rs, int rt, int rd
1564 {
1565   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1566   GPR[rd] = GPR[rs] - GPR[rt];
1567   TRACE_ALU_RESULT (GPR[rd]);
1568 }
1569
1570 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1571 "dsubu r<RD>, r<RS>, r<RT>"
1572 *mipsIII:
1573 *mipsIV:
1574 *vr5000:
1575 // start-sanitize-vr4320
1576 *vr4320:
1577 // end-sanitize-vr4320
1578 // start-sanitize-vr5400
1579 *vr5400:
1580 // end-sanitize-vr5400
1581 // start-sanitize-r5900
1582 *r5900:
1583 // end-sanitize-r5900
1584 // start-sanitize-tx19
1585 *tx19:
1586 // end-sanitize-tx19
1587 {
1588   do_dsubu (SD_, RS, RT, RD);
1589 }
1590
1591
1592 000010,26.INSTR_INDEX:NORMAL:32::J
1593 "j <INSTR_INDEX>"
1594 *mipsI,mipsII,mipsIII,mipsIV:
1595 *vr5000:
1596 // start-sanitize-vr4320
1597 *vr4320:
1598 // end-sanitize-vr4320
1599 // start-sanitize-vr5400
1600 *vr5400:
1601 // end-sanitize-vr5400
1602 // start-sanitize-r5900
1603 *r5900:
1604 // end-sanitize-r5900
1605 *r3900:
1606 // start-sanitize-tx19
1607 *tx19:
1608 // end-sanitize-tx19
1609 {
1610   /* NOTE: The region used is that of the delay slot NIA and NOT the
1611      current instruction */
1612   address_word region = (NIA & MASK (63, 28));
1613   DELAY_SLOT (region | (INSTR_INDEX << 2));
1614 }
1615
1616
1617 000011,26.INSTR_INDEX:NORMAL:32::JAL
1618 "jal <INSTR_INDEX>"
1619 *mipsI,mipsII,mipsIII,mipsIV:
1620 *vr5000:
1621 // start-sanitize-vr4320
1622 *vr4320:
1623 // end-sanitize-vr4320
1624 // start-sanitize-vr5400
1625 *vr5400:
1626 // end-sanitize-vr5400
1627 // start-sanitize-r5900
1628 *r5900:
1629 // end-sanitize-r5900
1630 *r3900:
1631 // start-sanitize-tx19
1632 *tx19:
1633 // end-sanitize-tx19
1634 {
1635   /* NOTE: The region used is that of the delay slot and NOT the
1636      current instruction */
1637   address_word region = (NIA & MASK (63, 28));
1638   GPR[31] = CIA + 8;
1639   DELAY_SLOT (region | (INSTR_INDEX << 2));
1640 }
1641
1642
1643 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1644 "jalr r<RS>":RD == 31
1645 "jalr r<RD>, r<RS>"
1646 *mipsI,mipsII,mipsIII,mipsIV:
1647 *vr5000:
1648 // start-sanitize-vr4320
1649 *vr4320:
1650 // end-sanitize-vr4320
1651 // start-sanitize-vr5400
1652 *vr5400:
1653 // end-sanitize-vr5400
1654 // start-sanitize-r5900
1655 *r5900:
1656 // end-sanitize-r5900
1657 *r3900:
1658 // start-sanitize-tx19
1659 *tx19:
1660 // end-sanitize-tx19
1661 {
1662   address_word temp = GPR[RS];
1663   GPR[RD] = CIA + 8;
1664   DELAY_SLOT (temp);
1665 }
1666
1667
1668 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1669 "jr r<RS>"
1670 *mipsI,mipsII,mipsIII,mipsIV:
1671 *vr5000:
1672 // start-sanitize-vr4320
1673 *vr4320:
1674 // end-sanitize-vr4320
1675 // start-sanitize-vr5400
1676 *vr5400:
1677 // end-sanitize-vr5400
1678 // start-sanitize-r5900
1679 *r5900:
1680 // end-sanitize-r5900
1681 *r3900:
1682 // start-sanitize-tx19
1683 *tx19:
1684 // end-sanitize-tx19
1685 {
1686   DELAY_SLOT (GPR[RS]);
1687 }
1688
1689
1690 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1691 {
1692   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1693   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1694   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1695   unsigned int byte;
1696   address_word paddr;
1697   int uncached;
1698   unsigned64 memval;
1699   address_word vaddr;
1700
1701   vaddr = base + offset;
1702   if ((vaddr & access) != 0)
1703     SignalExceptionAddressLoad ();
1704   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1705   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1706   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1707   byte = ((vaddr & mask) ^ bigendiancpu);
1708   return (memval >> (8 * byte));
1709 }
1710
1711
1712 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1713 "lb r<RT>, <OFFSET>(r<BASE>)"
1714 *mipsI,mipsII,mipsIII,mipsIV:
1715 *vr5000:
1716 // start-sanitize-vr4320
1717 *vr4320:
1718 // end-sanitize-vr4320
1719 // start-sanitize-vr5400
1720 *vr5400:
1721 // end-sanitize-vr5400
1722 // start-sanitize-r5900
1723 *r5900:
1724 // end-sanitize-r5900
1725 *r3900:
1726 // start-sanitize-tx19
1727 *tx19:
1728 // end-sanitize-tx19
1729 {
1730   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1731 }
1732
1733
1734 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1735 "lbu r<RT>, <OFFSET>(r<BASE>)"
1736 *mipsI,mipsII,mipsIII,mipsIV:
1737 *vr5000:
1738 // start-sanitize-vr4320
1739 *vr4320:
1740 // end-sanitize-vr4320
1741 // start-sanitize-vr5400
1742 *vr5400:
1743 // end-sanitize-vr5400
1744 // start-sanitize-r5900
1745 *r5900:
1746 // end-sanitize-r5900
1747 *r3900:
1748 // start-sanitize-tx19
1749 *tx19:
1750 // end-sanitize-tx19
1751 {
1752   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1753 }
1754
1755
1756 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1757 "ld r<RT>, <OFFSET>(r<BASE>)"
1758 *mipsIII:
1759 *mipsIV:
1760 *vr5000:
1761 // start-sanitize-vr4320
1762 *vr4320:
1763 // end-sanitize-vr4320
1764 // start-sanitize-vr5400
1765 *vr5400:
1766 // end-sanitize-vr5400
1767 // start-sanitize-r5900
1768 *r5900:
1769 // end-sanitize-r5900
1770 // start-sanitize-tx19
1771 *tx19:
1772 // end-sanitize-tx19
1773 {
1774   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1775 }
1776
1777
1778 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1779 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1780 *mipsII:
1781 *mipsIII:
1782 *mipsIV:
1783 *vr5000:
1784 // start-sanitize-vr4320
1785 *vr4320:
1786 // end-sanitize-vr4320
1787 // start-sanitize-vr5400
1788 *vr5400:
1789 // end-sanitize-vr5400
1790 *r3900:
1791 // start-sanitize-tx19
1792 *tx19:
1793 // end-sanitize-tx19
1794 {
1795   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1796 }
1797
1798
1799
1800
1801 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1802 "ldl r<RT>, <OFFSET>(r<BASE>)"
1803 *mipsIII:
1804 *mipsIV:
1805 *vr5000:
1806 // start-sanitize-vr4320
1807 *vr4320:
1808 // end-sanitize-vr4320
1809 // start-sanitize-vr5400
1810 *vr5400:
1811 // end-sanitize-vr5400
1812 // start-sanitize-r5900
1813 *r5900:
1814 // end-sanitize-r5900
1815 // start-sanitize-tx19
1816 *tx19:
1817 // end-sanitize-tx19
1818 {
1819   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1820 }
1821
1822
1823 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1824 "ldr r<RT>, <OFFSET>(r<BASE>)"
1825 *mipsIII:
1826 *mipsIV:
1827 *vr5000:
1828 // start-sanitize-vr4320
1829 *vr4320:
1830 // end-sanitize-vr4320
1831 // start-sanitize-vr5400
1832 *vr5400:
1833 // end-sanitize-vr5400
1834 // start-sanitize-r5900
1835 *r5900:
1836 // end-sanitize-r5900
1837 // start-sanitize-tx19
1838 *tx19:
1839 // end-sanitize-tx19
1840 {
1841   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1842 }
1843
1844
1845 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1846 "lh r<RT>, <OFFSET>(r<BASE>)"
1847 *mipsI,mipsII,mipsIII,mipsIV:
1848 *vr5000:
1849 // start-sanitize-vr4320
1850 *vr4320:
1851 // end-sanitize-vr4320
1852 // start-sanitize-vr5400
1853 *vr5400:
1854 // end-sanitize-vr5400
1855 // start-sanitize-r5900
1856 *r5900:
1857 // end-sanitize-r5900
1858 *r3900:
1859 // start-sanitize-tx19
1860 *tx19:
1861 // end-sanitize-tx19
1862 {
1863   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1864 }
1865
1866
1867 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1868 "lhu r<RT>, <OFFSET>(r<BASE>)"
1869 *mipsI,mipsII,mipsIII,mipsIV:
1870 *vr5000:
1871 // start-sanitize-vr4320
1872 *vr4320:
1873 // end-sanitize-vr4320
1874 // start-sanitize-vr5400
1875 *vr5400:
1876 // end-sanitize-vr5400
1877 // start-sanitize-r5900
1878 *r5900:
1879 // end-sanitize-r5900
1880 *r3900:
1881 // start-sanitize-tx19
1882 *tx19:
1883 // end-sanitize-tx19
1884 {
1885   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1886 }
1887
1888
1889 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1890 "ll r<RT>, <OFFSET>(r<BASE>)"
1891 *mipsII:
1892 *mipsIII:
1893 *mipsIV:
1894 *vr5000:
1895 // start-sanitize-vr4320
1896 *vr4320:
1897 // end-sanitize-vr4320
1898 // start-sanitize-vr5400
1899 *vr5400:
1900 // end-sanitize-vr5400
1901 // start-sanitize-r5900
1902 *r5900:
1903 // end-sanitize-r5900
1904 // start-sanitize-tx19
1905 *tx19:
1906 // end-sanitize-tx19
1907 {
1908   unsigned32 instruction = instruction_0;
1909   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1910   int destreg = ((instruction >> 16) & 0x0000001F);
1911   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1912   {
1913     address_word vaddr = ((unsigned64)op1 + offset);
1914     address_word paddr;
1915     int uncached;
1916     if ((vaddr & 3) != 0)
1917       SignalExceptionAddressLoad();
1918     else
1919       {
1920         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1921           {
1922             unsigned64 memval = 0;
1923             unsigned64 memval1 = 0;
1924             unsigned64 mask = 0x7;
1925             unsigned int shift = 2;
1926             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1927             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1928             unsigned int byte;
1929             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1930             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1931             byte = ((vaddr & mask) ^ (bigend << shift));
1932             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1933             LLBIT = 1;
1934           }
1935       }
1936   }
1937 }
1938
1939
1940 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1941 "lld r<RT>, <OFFSET>(r<BASE>)"
1942 *mipsIII:
1943 *mipsIV:
1944 *vr5000:
1945 // start-sanitize-vr4320
1946 *vr4320:
1947 // end-sanitize-vr4320
1948 // start-sanitize-vr5400
1949 *vr5400:
1950 // end-sanitize-vr5400
1951 // start-sanitize-r5900
1952 *r5900:
1953 // end-sanitize-r5900
1954 // start-sanitize-tx19
1955 *tx19:
1956 // end-sanitize-tx19
1957 {
1958   unsigned32 instruction = instruction_0;
1959   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1960   int destreg = ((instruction >> 16) & 0x0000001F);
1961   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1962   {
1963     address_word vaddr = ((unsigned64)op1 + offset);
1964     address_word paddr;
1965     int uncached;
1966     if ((vaddr & 7) != 0)
1967       SignalExceptionAddressLoad();
1968     else
1969       {
1970         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1971           {
1972             unsigned64 memval = 0;
1973             unsigned64 memval1 = 0;
1974             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1975             GPR[destreg] = memval;
1976             LLBIT = 1;
1977           }
1978       }
1979   }
1980 }
1981
1982
1983 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1984 "lui r<RT>, <IMMEDIATE>"
1985 *mipsI,mipsII,mipsIII,mipsIV:
1986 *vr5000:
1987 // start-sanitize-vr4320
1988 *vr4320:
1989 // end-sanitize-vr4320
1990 // start-sanitize-vr5400
1991 *vr5400:
1992 // end-sanitize-vr5400
1993 // start-sanitize-r5900
1994 *r5900:
1995 // end-sanitize-r5900
1996 *r3900:
1997 // start-sanitize-tx19
1998 *tx19:
1999 // end-sanitize-tx19
2000 {
2001   TRACE_ALU_INPUT1 (IMMEDIATE);
2002   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2003   TRACE_ALU_RESULT (GPR[RT]);
2004 }
2005
2006
2007 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2008 "lw r<RT>, <OFFSET>(r<BASE>)"
2009 *mipsI,mipsII,mipsIII,mipsIV:
2010 *vr5000:
2011 // start-sanitize-vr4320
2012 *vr4320:
2013 // end-sanitize-vr4320
2014 // start-sanitize-vr5400
2015 *vr5400:
2016 // end-sanitize-vr5400
2017 // start-sanitize-r5900
2018 *r5900:
2019 // end-sanitize-r5900
2020 *r3900:
2021 // start-sanitize-tx19
2022 *tx19:
2023 // end-sanitize-tx19
2024 {
2025   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2026 }
2027
2028
2029 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2030 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2031 *mipsI,mipsII,mipsIII,mipsIV:
2032 *vr5000:
2033 // start-sanitize-vr4320
2034 *vr4320:
2035 // end-sanitize-vr4320
2036 // start-sanitize-vr5400
2037 *vr5400:
2038 // end-sanitize-vr5400
2039 // start-sanitize-r5900
2040 *r5900:
2041 // end-sanitize-r5900
2042 *r3900:
2043 // start-sanitize-tx19
2044 *tx19:
2045 // end-sanitize-tx19
2046 {
2047   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2048 }
2049
2050
2051 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2052 {
2053   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2054   address_word reverseendian = (ReverseEndian ? -1 : 0);
2055   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2056   unsigned int byte;
2057   address_word paddr;
2058   int uncached;
2059   unsigned64 memval;
2060   address_word vaddr;
2061
2062   vaddr = base + offset;
2063   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2064   paddr = (paddr ^ (reverseendian & mask));
2065   if (BigEndianMem == 0)
2066     paddr = paddr & ~access;
2067   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2068   LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
2069   /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
2070      (long) vaddr, byte, (long) paddr, (long) memval); */
2071   if ((byte & ~access) == 0)
2072     {
2073       int bits = 8 * (access - byte);
2074       unsigned_word screen = LSMASK (bits - 1, 0);
2075       rt &= screen;
2076       rt |= ((memval << bits) & ~screen);
2077     }
2078   else
2079     {
2080       unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
2081       rt &= screen;
2082       rt |= ((memval >> (8 * (mask - byte))) & ~screen);
2083     }
2084   return rt;
2085 }
2086
2087
2088 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2089 "lwl r<RT>, <OFFSET>(r<BASE>)"
2090 *mipsI,mipsII,mipsIII,mipsIV:
2091 *vr5000:
2092 // start-sanitize-vr4320
2093 *vr4320:
2094 // end-sanitize-vr4320
2095 // start-sanitize-vr5400
2096 *vr5400:
2097 // end-sanitize-vr5400
2098 // start-sanitize-r5900
2099 *r5900:
2100 // end-sanitize-r5900
2101 *r3900:
2102 // start-sanitize-tx19
2103 *tx19:
2104 // end-sanitize-tx19
2105 {
2106   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2107 }
2108
2109
2110 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2111 {
2112   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2113   address_word reverseendian = (ReverseEndian ? -1 : 0);
2114   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2115   unsigned int byte;
2116   address_word paddr;
2117   int uncached;
2118   unsigned64 memval;
2119   address_word vaddr;
2120
2121   vaddr = base + offset;
2122   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2123   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2124   paddr = (paddr ^ (reverseendian & mask));
2125   if (BigEndianMem != 0)
2126     paddr = paddr & ~access;
2127   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2128   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2129   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2130   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2131      (long) paddr, byte, (long) paddr, (long) memval); */
2132   {
2133     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2134     rt &= ~screen;
2135     rt |= (memval >> (8 * byte)) & screen;
2136   }
2137   return rt;
2138 }
2139
2140
2141 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2142 "lwr r<RT>, <OFFSET>(r<BASE>)"
2143 *mipsI,mipsII,mipsIII,mipsIV:
2144 *vr5000:
2145 // start-sanitize-vr4320
2146 *vr4320:
2147 // end-sanitize-vr4320
2148 // start-sanitize-vr5400
2149 *vr5400:
2150 // end-sanitize-vr5400
2151 // start-sanitize-r5900
2152 *r5900:
2153 // end-sanitize-r5900
2154 *r3900:
2155 // start-sanitize-tx19
2156 *tx19:
2157 // end-sanitize-tx19
2158 {
2159   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2160 }
2161
2162
2163 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2164 "lwu r<RT>, <OFFSET>(r<BASE>)"
2165 *mipsIII:
2166 *mipsIV:
2167 *vr5000:
2168 // start-sanitize-vr4320
2169 *vr4320:
2170 // end-sanitize-vr4320
2171 // start-sanitize-vr5400
2172 *vr5400:
2173 // end-sanitize-vr5400
2174 // start-sanitize-r5900
2175 *r5900:
2176 // end-sanitize-r5900
2177 // start-sanitize-tx19
2178 *tx19:
2179 // end-sanitize-tx19
2180 {
2181   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2182 }
2183
2184
2185 :function:::void:do_mfhi:int rd
2186 {
2187   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2188   TRACE_ALU_INPUT1 (HI);
2189   GPR[rd] = HI;
2190   TRACE_ALU_RESULT (GPR[rd]);
2191 }
2192
2193 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2194 "mfhi r<RD>"
2195 *mipsI,mipsII,mipsIII,mipsIV:
2196 *vr5000:
2197 // start-sanitize-vr4320
2198 *vr4320:
2199 // end-sanitize-vr4320
2200 // start-sanitize-vr5400
2201 *vr5400:
2202 // end-sanitize-vr5400
2203 // start-sanitize-r5900
2204 *r5900:
2205 // end-sanitize-r5900
2206 *r3900:
2207 // start-sanitize-tx19
2208 *tx19:
2209 // end-sanitize-tx19
2210 {
2211   do_mfhi (SD_, RD);
2212 }
2213
2214
2215
2216 :function:::void:do_mflo:int rd
2217 {
2218   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2219   TRACE_ALU_INPUT1 (LO);
2220   GPR[rd] = LO;
2221   TRACE_ALU_RESULT (GPR[rd]);
2222 }
2223
2224 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2225 "mflo r<RD>"
2226 *mipsI,mipsII,mipsIII,mipsIV:
2227 *vr5000:
2228 // start-sanitize-vr4320
2229 *vr4320:
2230 // end-sanitize-vr4320
2231 // start-sanitize-vr5400
2232 *vr5400:
2233 // end-sanitize-vr5400
2234 // start-sanitize-r5900
2235 *r5900:
2236 // end-sanitize-r5900
2237 *r3900:
2238 // start-sanitize-tx19
2239 *tx19:
2240 // end-sanitize-tx19
2241 {
2242   do_mflo (SD_, RD);
2243 }
2244
2245
2246
2247 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2248 "movn r<RD>, r<RS>, r<RT>"
2249 *mipsIV:
2250 *vr5000:
2251 // start-sanitize-vr4320
2252 *vr4320:
2253 // end-sanitize-vr4320
2254 // start-sanitize-vr5400
2255 *vr5400:
2256 // end-sanitize-vr5400
2257 // start-sanitize-r5900
2258 *r5900:
2259 // end-sanitize-r5900
2260 {
2261   if (GPR[RT] != 0)
2262     GPR[RD] = GPR[RS];
2263 }
2264
2265
2266
2267 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2268 "movz r<RD>, r<RS>, r<RT>"
2269 *mipsIV:
2270 *vr5000:
2271 // start-sanitize-vr4320
2272 *vr4320:
2273 // end-sanitize-vr4320
2274 // start-sanitize-vr5400
2275 *vr5400:
2276 // end-sanitize-vr5400
2277 // start-sanitize-r5900
2278 *r5900:
2279 // end-sanitize-r5900
2280 {
2281   if (GPR[RT] == 0)
2282     GPR[RD] = GPR[RS];
2283 }
2284
2285
2286
2287 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2288 "mthi r<RS>"
2289 *mipsI,mipsII,mipsIII,mipsIV:
2290 *vr5000:
2291 // start-sanitize-vr4320
2292 *vr4320:
2293 // end-sanitize-vr4320
2294 // start-sanitize-vr5400
2295 *vr5400:
2296 // end-sanitize-vr5400
2297 // start-sanitize-r5900
2298 *r5900:
2299 // end-sanitize-r5900
2300 *r3900:
2301 // start-sanitize-tx19
2302 *tx19:
2303 // end-sanitize-tx19
2304 {
2305   check_mt_hilo (SD_, HIHISTORY);
2306   HI = GPR[RS];
2307 }
2308
2309
2310
2311 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2312 "mtlo r<RS>"
2313 *mipsI,mipsII,mipsIII,mipsIV:
2314 *vr5000:
2315 // start-sanitize-vr4320
2316 *vr4320:
2317 // end-sanitize-vr4320
2318 // start-sanitize-vr5400
2319 *vr5400:
2320 // end-sanitize-vr5400
2321 // start-sanitize-r5900
2322 *r5900:
2323 // end-sanitize-r5900
2324 *r3900:
2325 // start-sanitize-tx19
2326 *tx19:
2327 // end-sanitize-tx19
2328 {
2329   check_mt_hilo (SD_, LOHISTORY);
2330   LO = GPR[RS];
2331 }
2332
2333
2334
2335 :function:::void:do_mult:int rs, int rt, int rd
2336 {
2337   signed64 prod;
2338   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2339   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2340   prod = (((signed64)(signed32) GPR[rs])
2341           * ((signed64)(signed32) GPR[rt]));
2342   LO = EXTEND32 (VL4_8 (prod));
2343   HI = EXTEND32 (VH4_8 (prod));
2344   if (rd != 0)
2345     GPR[rd] = LO;
2346   TRACE_ALU_RESULT2 (HI, LO);
2347 }
2348
2349 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2350 "mult r<RS>, r<RT>"
2351 *mipsI,mipsII,mipsIII,mipsIV:
2352 // start-sanitize-vr4320
2353 *vr4320:
2354 // end-sanitize-vr4320
2355 {
2356   do_mult (SD_, RS, RT, 0);
2357 }
2358
2359
2360 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2361 "mult r<RD>, r<RS>, r<RT>"
2362 *vr5000:
2363 // start-sanitize-vr5400
2364 *vr5400:
2365 // end-sanitize-vr5400
2366 // start-sanitize-r5900
2367 *r5900:
2368 // end-sanitize-r5900
2369 *r3900:
2370 // start-sanitize-tx19
2371 *tx19:
2372 // end-sanitize-tx19
2373 {
2374   do_mult (SD_, RS, RT, RD);
2375 }
2376
2377
2378 :function:::void:do_multu:int rs, int rt, int rd
2379 {
2380   unsigned64 prod;
2381   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2382   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2383   prod = (((unsigned64)(unsigned32) GPR[rs])
2384           * ((unsigned64)(unsigned32) GPR[rt]));
2385   LO = EXTEND32 (VL4_8 (prod));
2386   HI = EXTEND32 (VH4_8 (prod));
2387   if (rd != 0)
2388     GPR[rd] = LO;
2389   TRACE_ALU_RESULT2 (HI, LO);
2390 }
2391
2392 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2393 "multu r<RS>, r<RT>"
2394 *mipsI,mipsII,mipsIII,mipsIV:
2395 // start-sanitize-vr4320
2396 *vr4320:
2397 // end-sanitize-vr4320
2398 {
2399   do_multu (SD_, RS, RT, 0);
2400 }
2401
2402 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2403 "multu r<RD>, r<RS>, r<RT>"
2404 *vr5000:
2405 // start-sanitize-vr5400
2406 *vr5400:
2407 // end-sanitize-vr5400
2408 // start-sanitize-r5900
2409 *r5900:
2410 // end-sanitize-r5900
2411 *r3900:
2412 // start-sanitize-tx19
2413 *tx19:
2414 // end-sanitize-tx19
2415 {
2416   do_multu (SD_, RS, RT, 0);
2417 }
2418
2419
2420 :function:::void:do_nor:int rs, int rt, int rd
2421 {
2422   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2423   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2424   TRACE_ALU_RESULT (GPR[rd]);
2425 }
2426
2427 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2428 "nor r<RD>, r<RS>, r<RT>"
2429 *mipsI,mipsII,mipsIII,mipsIV:
2430 *vr5000:
2431 // start-sanitize-vr4320
2432 *vr4320:
2433 // end-sanitize-vr4320
2434 // start-sanitize-vr5400
2435 *vr5400:
2436 // end-sanitize-vr5400
2437 // start-sanitize-r5900
2438 *r5900:
2439 // end-sanitize-r5900
2440 *r3900:
2441 // start-sanitize-tx19
2442 *tx19:
2443 // end-sanitize-tx19
2444 {
2445   do_nor (SD_, RS, RT, RD);
2446 }
2447
2448
2449 :function:::void:do_or:int rs, int rt, int rd
2450 {
2451   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2452   GPR[rd] = (GPR[rs] | GPR[rt]);
2453   TRACE_ALU_RESULT (GPR[rd]);
2454 }
2455
2456 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2457 "or r<RD>, r<RS>, r<RT>"
2458 *mipsI,mipsII,mipsIII,mipsIV:
2459 *vr5000:
2460 // start-sanitize-vr4320
2461 *vr4320:
2462 // end-sanitize-vr4320
2463 // start-sanitize-vr5400
2464 *vr5400:
2465 // end-sanitize-vr5400
2466 // start-sanitize-r5900
2467 *r5900:
2468 // end-sanitize-r5900
2469 *r3900:
2470 // start-sanitize-tx19
2471 *tx19:
2472 // end-sanitize-tx19
2473 {
2474   do_or (SD_, RS, RT, RD);
2475 }
2476
2477
2478
2479 :function:::void:do_ori:int rs, int rt, unsigned immediate
2480 {
2481   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2482   GPR[rt] = (GPR[rs] | immediate);
2483   TRACE_ALU_RESULT (GPR[rt]);
2484 }
2485
2486 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2487 "ori r<RT>, r<RS>, <IMMEDIATE>"
2488 *mipsI,mipsII,mipsIII,mipsIV:
2489 *vr5000:
2490 // start-sanitize-vr4320
2491 *vr4320:
2492 // end-sanitize-vr4320
2493 // start-sanitize-vr5400
2494 *vr5400:
2495 // end-sanitize-vr5400
2496 // start-sanitize-r5900
2497 *r5900:
2498 // end-sanitize-r5900
2499 *r3900:
2500 // start-sanitize-tx19
2501 *tx19:
2502 // end-sanitize-tx19
2503 {
2504   do_ori (SD_, RS, RT, IMMEDIATE);
2505 }
2506
2507
2508 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2509 *mipsIV:
2510 *vr5000:
2511 // start-sanitize-vr4320
2512 *vr4320:
2513 // end-sanitize-vr4320
2514 // start-sanitize-vr5400
2515 *vr5400:
2516 // end-sanitize-vr5400
2517 // start-sanitize-r5900
2518 *r5900:
2519 // end-sanitize-r5900
2520 {
2521   unsigned32 instruction = instruction_0;
2522   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2523   int hint = ((instruction >> 16) & 0x0000001F);
2524   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2525   {
2526     address_word vaddr = ((unsigned64)op1 + offset);
2527     address_word paddr;
2528     int uncached;
2529     {
2530       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2531         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2532     }
2533   }
2534 }
2535
2536 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2537 {
2538   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2539   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2540   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2541   unsigned int byte;
2542   address_word paddr;
2543   int uncached;
2544   unsigned64 memval;
2545   address_word vaddr;
2546
2547   vaddr = base + offset;
2548   if ((vaddr & access) != 0)
2549     SignalExceptionAddressStore ();
2550   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2551   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2552   byte = ((vaddr & mask) ^ bigendiancpu);
2553   memval = (word << (8 * byte));
2554   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2555 }
2556
2557
2558 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2559 "sb r<RT>, <OFFSET>(r<BASE>)"
2560 *mipsI,mipsII,mipsIII,mipsIV:
2561 *vr5000:
2562 // start-sanitize-vr4320
2563 *vr4320:
2564 // end-sanitize-vr4320
2565 // start-sanitize-vr5400
2566 *vr5400:
2567 // end-sanitize-vr5400
2568 // start-sanitize-r5900
2569 *r5900:
2570 // end-sanitize-r5900
2571 *r3900:
2572 // start-sanitize-tx19
2573 *tx19:
2574 // end-sanitize-tx19
2575 {
2576   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2577 }
2578
2579
2580 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2581 "sc r<RT>, <OFFSET>(r<BASE>)"
2582 *mipsII:
2583 *mipsIII:
2584 *mipsIV:
2585 *vr5000:
2586 // start-sanitize-vr4320
2587 *vr4320:
2588 // end-sanitize-vr4320
2589 // start-sanitize-vr5400
2590 *vr5400:
2591 // end-sanitize-vr5400
2592 // start-sanitize-r5900
2593 *r5900:
2594 // end-sanitize-r5900
2595 // start-sanitize-tx19
2596 *tx19:
2597 // end-sanitize-tx19
2598 {
2599   unsigned32 instruction = instruction_0;
2600   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2601   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2602   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2603   {
2604     address_word vaddr = ((unsigned64)op1 + offset);
2605     address_word paddr;
2606     int uncached;
2607     if ((vaddr & 3) != 0)
2608       SignalExceptionAddressStore();
2609     else
2610       {
2611         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2612           {
2613             unsigned64 memval = 0;
2614             unsigned64 memval1 = 0;
2615             unsigned64 mask = 0x7;
2616             unsigned int byte;
2617             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2618             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2619             memval = ((unsigned64) op2 << (8 * byte));
2620             if (LLBIT)
2621               {
2622                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2623               }
2624             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2625           }
2626       }
2627   }
2628 }
2629
2630
2631 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2632 "scd r<RT>, <OFFSET>(r<BASE>)"
2633 *mipsIII:
2634 *mipsIV:
2635 *vr5000:
2636 // start-sanitize-vr4320
2637 *vr4320:
2638 // end-sanitize-vr4320
2639 // start-sanitize-vr5400
2640 *vr5400:
2641 // end-sanitize-vr5400
2642 // start-sanitize-r5900
2643 *r5900:
2644 // end-sanitize-r5900
2645 // start-sanitize-tx19
2646 *tx19:
2647 // end-sanitize-tx19
2648 {
2649   unsigned32 instruction = instruction_0;
2650   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2651   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2652   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2653   {
2654     address_word vaddr = ((unsigned64)op1 + offset);
2655     address_word paddr;
2656     int uncached;
2657     if ((vaddr & 7) != 0)
2658       SignalExceptionAddressStore();
2659     else
2660       {
2661         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2662           {
2663             unsigned64 memval = 0;
2664             unsigned64 memval1 = 0;
2665             memval = op2;
2666             if (LLBIT)
2667               {
2668                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2669               }
2670             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2671           }
2672       }
2673   }
2674 }
2675
2676
2677 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2678 "sd r<RT>, <OFFSET>(r<BASE>)"
2679 *mipsIII:
2680 *mipsIV:
2681 *vr5000:
2682 // start-sanitize-vr4320
2683 *vr4320:
2684 // end-sanitize-vr4320
2685 // start-sanitize-vr5400
2686 *vr5400:
2687 // end-sanitize-vr5400
2688 // start-sanitize-r5900
2689 *r5900:
2690 // end-sanitize-r5900
2691 // start-sanitize-tx19
2692 *tx19:
2693 // end-sanitize-tx19
2694 {
2695   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2696 }
2697
2698
2699 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2700 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2701 *mipsII:
2702 *mipsIII:
2703 *mipsIV:
2704 *vr5000:
2705 // start-sanitize-vr4320
2706 *vr4320:
2707 // end-sanitize-vr4320
2708 // start-sanitize-vr5400
2709 *vr5400:
2710 // end-sanitize-vr5400
2711 // start-sanitize-r5900
2712 *r5900:
2713 // end-sanitize-r5900
2714 // start-sanitize-tx19
2715 *tx19:
2716 // end-sanitize-tx19
2717 {
2718   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2719 }
2720
2721
2722 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2723 "sdl r<RT>, <OFFSET>(r<BASE>)"
2724 *mipsIII:
2725 *mipsIV:
2726 *vr5000:
2727 // start-sanitize-vr4320
2728 *vr4320:
2729 // end-sanitize-vr4320
2730 // start-sanitize-vr5400
2731 *vr5400:
2732 // end-sanitize-vr5400
2733 // start-sanitize-r5900
2734 *r5900:
2735 // end-sanitize-r5900
2736 // start-sanitize-tx19
2737 *tx19:
2738 // end-sanitize-tx19
2739 {
2740   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2741 }
2742
2743
2744 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2745 "sdr r<RT>, <OFFSET>(r<BASE>)"
2746 *mipsIII:
2747 *mipsIV:
2748 *vr5000:
2749 // start-sanitize-vr4320
2750 *vr4320:
2751 // end-sanitize-vr4320
2752 // start-sanitize-vr5400
2753 *vr5400:
2754 // end-sanitize-vr5400
2755 // start-sanitize-r5900
2756 *r5900:
2757 // end-sanitize-r5900
2758 // start-sanitize-tx19
2759 *tx19:
2760 // end-sanitize-tx19
2761 {
2762   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2763 }
2764
2765
2766 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2767 "sh r<RT>, <OFFSET>(r<BASE>)"
2768 *mipsI,mipsII,mipsIII,mipsIV:
2769 *vr5000:
2770 // start-sanitize-vr4320
2771 *vr4320:
2772 // end-sanitize-vr4320
2773 // start-sanitize-vr5400
2774 *vr5400:
2775 // end-sanitize-vr5400
2776 // start-sanitize-r5900
2777 *r5900:
2778 // end-sanitize-r5900
2779 *r3900:
2780 // start-sanitize-tx19
2781 *tx19:
2782 // end-sanitize-tx19
2783 {
2784   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2785 }
2786
2787
2788 :function:::void:do_sll:int rt, int rd, int shift
2789 {
2790   unsigned32 temp = (GPR[rt] << shift);
2791   TRACE_ALU_INPUT2 (GPR[rt], shift);
2792   GPR[rd] = EXTEND32 (temp);
2793   TRACE_ALU_RESULT (GPR[rd]);
2794 }
2795
2796 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2797 "sll r<RD>, r<RT>, <SHIFT>"
2798 *mipsI,mipsII,mipsIII,mipsIV:
2799 *vr5000:
2800 // start-sanitize-vr4320
2801 *vr4320:
2802 // end-sanitize-vr4320
2803 // start-sanitize-vr5400
2804 *vr5400:
2805 // end-sanitize-vr5400
2806 // start-sanitize-r5900
2807 *r5900:
2808 // end-sanitize-r5900
2809 *r3900:
2810 // start-sanitize-tx19
2811 *tx19:
2812 // end-sanitize-tx19
2813 {
2814   do_sll (SD_, RT, RD, SHIFT);
2815 }
2816
2817
2818 :function:::void:do_sllv:int rs, int rt, int rd
2819 {
2820   int s = MASKED (GPR[rs], 4, 0);
2821   unsigned32 temp = (GPR[rt] << s);
2822   TRACE_ALU_INPUT2 (GPR[rt], s);
2823   GPR[rd] = EXTEND32 (temp);
2824   TRACE_ALU_RESULT (GPR[rd]);
2825 }
2826
2827 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2828 "sllv r<RD>, r<RT>, r<RS>"
2829 *mipsI,mipsII,mipsIII,mipsIV:
2830 *vr5000:
2831 // start-sanitize-vr4320
2832 *vr4320:
2833 // end-sanitize-vr4320
2834 // start-sanitize-vr5400
2835 *vr5400:
2836 // end-sanitize-vr5400
2837 // start-sanitize-r5900
2838 *r5900:
2839 // end-sanitize-r5900
2840 *r3900:
2841 // start-sanitize-tx19
2842 *tx19:
2843 // end-sanitize-tx19
2844 {
2845   do_sllv (SD_, RS, RT, RD);
2846 }
2847
2848
2849 :function:::void:do_slt:int rs, int rt, int rd
2850 {
2851   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2852   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2853   TRACE_ALU_RESULT (GPR[rd]);
2854 }
2855
2856 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2857 "slt r<RD>, r<RS>, r<RT>"
2858 *mipsI,mipsII,mipsIII,mipsIV:
2859 *vr5000:
2860 // start-sanitize-vr4320
2861 *vr4320:
2862 // end-sanitize-vr4320
2863 // start-sanitize-vr5400
2864 *vr5400:
2865 // end-sanitize-vr5400
2866 // start-sanitize-r5900
2867 *r5900:
2868 // end-sanitize-r5900
2869 *r3900:
2870 // start-sanitize-tx19
2871 *tx19:
2872 // end-sanitize-tx19
2873 {
2874   do_slt (SD_, RS, RT, RD);
2875 }
2876
2877
2878 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2879 {
2880   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2881   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2882   TRACE_ALU_RESULT (GPR[rt]);
2883 }
2884
2885 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2886 "slti r<RT>, r<RS>, <IMMEDIATE>"
2887 *mipsI,mipsII,mipsIII,mipsIV:
2888 *vr5000:
2889 // start-sanitize-vr4320
2890 *vr4320:
2891 // end-sanitize-vr4320
2892 // start-sanitize-vr5400
2893 *vr5400:
2894 // end-sanitize-vr5400
2895 // start-sanitize-r5900
2896 *r5900:
2897 // end-sanitize-r5900
2898 *r3900:
2899 // start-sanitize-tx19
2900 *tx19:
2901 // end-sanitize-tx19
2902 {
2903   do_slti (SD_, RS, RT, IMMEDIATE);
2904 }
2905
2906
2907 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2908 {
2909   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2910   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2911   TRACE_ALU_RESULT (GPR[rt]);
2912 }
2913
2914 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2915 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2916 *mipsI,mipsII,mipsIII,mipsIV:
2917 *vr5000:
2918 // start-sanitize-vr4320
2919 *vr4320:
2920 // end-sanitize-vr4320
2921 // start-sanitize-vr5400
2922 *vr5400:
2923 // end-sanitize-vr5400
2924 // start-sanitize-r5900
2925 *r5900:
2926 // end-sanitize-r5900
2927 *r3900:
2928 // start-sanitize-tx19
2929 *tx19:
2930 // end-sanitize-tx19
2931 {
2932   do_sltiu (SD_, RS, RT, IMMEDIATE);
2933 }
2934
2935
2936
2937 :function:::void:do_sltu:int rs, int rt, int rd
2938 {
2939   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2940   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2941   TRACE_ALU_RESULT (GPR[rd]);
2942 }
2943
2944 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2945 "sltu r<RD>, r<RS>, r<RT>"
2946 *mipsI,mipsII,mipsIII,mipsIV:
2947 *vr5000:
2948 // start-sanitize-vr4320
2949 *vr4320:
2950 // end-sanitize-vr4320
2951 // start-sanitize-vr5400
2952 *vr5400:
2953 // end-sanitize-vr5400
2954 // start-sanitize-r5900
2955 *r5900:
2956 // end-sanitize-r5900
2957 *r3900:
2958 // start-sanitize-tx19
2959 *tx19:
2960 // end-sanitize-tx19
2961 {
2962   do_sltu (SD_, RS, RT, RD);
2963 }
2964
2965
2966 :function:::void:do_sra:int rt, int rd, int shift
2967 {
2968   signed32 temp = (signed32) GPR[rt] >> shift;
2969   TRACE_ALU_INPUT2 (GPR[rt], shift);
2970   GPR[rd] = EXTEND32 (temp);
2971   TRACE_ALU_RESULT (GPR[rd]);
2972 }
2973
2974 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2975 "sra r<RD>, r<RT>, <SHIFT>"
2976 *mipsI,mipsII,mipsIII,mipsIV:
2977 *vr5000:
2978 // start-sanitize-vr4320
2979 *vr4320:
2980 // end-sanitize-vr4320
2981 // start-sanitize-vr5400
2982 *vr5400:
2983 // end-sanitize-vr5400
2984 // start-sanitize-r5900
2985 *r5900:
2986 // end-sanitize-r5900
2987 *r3900:
2988 // start-sanitize-tx19
2989 *tx19:
2990 // end-sanitize-tx19
2991 {
2992   do_sra (SD_, RT, RD, SHIFT);
2993 }
2994
2995
2996
2997 :function:::void:do_srav:int rs, int rt, int rd
2998 {
2999   int s = MASKED (GPR[rs], 4, 0);
3000   signed32 temp = (signed32) GPR[rt] >> s;
3001   TRACE_ALU_INPUT2 (GPR[rt], s);
3002   GPR[rd] = EXTEND32 (temp);
3003   TRACE_ALU_RESULT (GPR[rd]);
3004 }
3005
3006 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3007 "srav r<RD>, r<RT>, r<RS>"
3008 *mipsI,mipsII,mipsIII,mipsIV:
3009 *vr5000:
3010 // start-sanitize-vr4320
3011 *vr4320:
3012 // end-sanitize-vr4320
3013 // start-sanitize-vr5400
3014 *vr5400:
3015 // end-sanitize-vr5400
3016 // start-sanitize-r5900
3017 *r5900:
3018 // end-sanitize-r5900
3019 *r3900:
3020 // start-sanitize-tx19
3021 *tx19:
3022 // end-sanitize-tx19
3023 {
3024   do_srav (SD_, RS, RT, RD);
3025 }
3026
3027
3028
3029 :function:::void:do_srl:int rt, int rd, int shift
3030 {
3031   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3032   TRACE_ALU_INPUT2 (GPR[rt], shift);
3033   GPR[rd] = EXTEND32 (temp);
3034   TRACE_ALU_RESULT (GPR[rd]);
3035 }
3036
3037 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3038 "srl r<RD>, r<RT>, <SHIFT>"
3039 *mipsI,mipsII,mipsIII,mipsIV:
3040 *vr5000:
3041 // start-sanitize-vr4320
3042 *vr4320:
3043 // end-sanitize-vr4320
3044 // start-sanitize-vr5400
3045 *vr5400:
3046 // end-sanitize-vr5400
3047 // start-sanitize-r5900
3048 *r5900:
3049 // end-sanitize-r5900
3050 *r3900:
3051 // start-sanitize-tx19
3052 *tx19:
3053 // end-sanitize-tx19
3054 {
3055   do_srl (SD_, RT, RD, SHIFT);
3056 }
3057
3058
3059 :function:::void:do_srlv:int rs, int rt, int rd
3060 {
3061   int s = MASKED (GPR[rs], 4, 0);
3062   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3063   TRACE_ALU_INPUT2 (GPR[rt], s);
3064   GPR[rd] = EXTEND32 (temp);
3065   TRACE_ALU_RESULT (GPR[rd]);
3066 }
3067
3068 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3069 "srlv r<RD>, r<RT>, r<RS>"
3070 *mipsI,mipsII,mipsIII,mipsIV:
3071 *vr5000:
3072 // start-sanitize-vr4320
3073 *vr4320:
3074 // end-sanitize-vr4320
3075 // start-sanitize-vr5400
3076 *vr5400:
3077 // end-sanitize-vr5400
3078 // start-sanitize-r5900
3079 *r5900:
3080 // end-sanitize-r5900
3081 *r3900:
3082 // start-sanitize-tx19
3083 *tx19:
3084 // end-sanitize-tx19
3085 {
3086   do_srlv (SD_, RS, RT, RD);
3087 }
3088
3089
3090 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3091 "sub r<RD>, r<RS>, r<RT>"
3092 *mipsI,mipsII,mipsIII,mipsIV:
3093 *vr5000:
3094 // start-sanitize-vr4320
3095 *vr4320:
3096 // end-sanitize-vr4320
3097 // start-sanitize-vr5400
3098 *vr5400:
3099 // end-sanitize-vr5400
3100 // start-sanitize-r5900
3101 *r5900:
3102 // end-sanitize-r5900
3103 *r3900:
3104 // start-sanitize-tx19
3105 *tx19:
3106 // end-sanitize-tx19
3107 {
3108   ALU32_BEGIN (GPR[RS]);
3109   ALU32_SUB (GPR[RT]);
3110   ALU32_END (GPR[RD]);
3111 }
3112
3113
3114 :function:::void:do_subu:int rs, int rt, int rd
3115 {
3116   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3117   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3118   TRACE_ALU_RESULT (GPR[rd]);
3119 }
3120
3121 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3122 "subu r<RD>, r<RS>, r<RT>"
3123 *mipsI,mipsII,mipsIII,mipsIV:
3124 *vr5000:
3125 // start-sanitize-vr4320
3126 *vr4320:
3127 // end-sanitize-vr4320
3128 // start-sanitize-vr5400
3129 *vr5400:
3130 // end-sanitize-vr5400
3131 // start-sanitize-r5900
3132 *r5900:
3133 // end-sanitize-r5900
3134 *r3900:
3135 // start-sanitize-tx19
3136 *tx19:
3137 // end-sanitize-tx19
3138 {
3139   do_subu (SD_, RS, RT, RD);
3140 }
3141
3142
3143 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3144 "sw r<RT>, <OFFSET>(r<BASE>)"
3145 *mipsI,mipsII,mipsIII,mipsIV:
3146 // start-sanitize-tx19
3147 *tx19:
3148 // end-sanitize-tx19
3149 *r3900:
3150 // start-sanitize-vr4320
3151 *vr4320:
3152 // end-sanitize-vr4320
3153 *vr5000:
3154 // start-sanitize-vr5400
3155 *vr5400:
3156 // end-sanitize-vr5400
3157 // start-sanitize-r5900
3158 *r5900:
3159 // end-sanitize-r5900
3160 {
3161   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3162 }
3163
3164
3165 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3166 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3167 *mipsI,mipsII,mipsIII,mipsIV:
3168 *vr5000:
3169 // start-sanitize-vr4320
3170 *vr4320:
3171 // end-sanitize-vr4320
3172 // start-sanitize-vr5400
3173 *vr5400:
3174 // end-sanitize-vr5400
3175 *r3900:
3176 // start-sanitize-tx19
3177 *tx19:
3178 // end-sanitize-tx19
3179 {
3180   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3181 }
3182
3183
3184
3185 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3186 {
3187   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3188   address_word reverseendian = (ReverseEndian ? -1 : 0);
3189   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3190   unsigned int byte;
3191   address_word paddr;
3192   int uncached;
3193   unsigned64 memval;
3194   address_word vaddr;
3195
3196   vaddr = base + offset;
3197   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3198   paddr = (paddr ^ (reverseendian & mask));
3199   if (BigEndianMem == 0)
3200     paddr = paddr & ~access;
3201   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3202   if ((byte & ~access) == 0)
3203     memval = (rt >> (8 * (access - byte)));
3204   else
3205     memval = (rt << (8 * (mask - byte)));
3206   StoreMemory (uncached, byte & access, memval, 0, paddr, vaddr, isREAL);
3207 }
3208
3209
3210 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3211 "swl r<RT>, <OFFSET>(r<BASE>)"
3212 *mipsI,mipsII,mipsIII,mipsIV:
3213 *vr5000:
3214 // start-sanitize-vr4320
3215 *vr4320:
3216 // end-sanitize-vr4320
3217 // start-sanitize-vr5400
3218 *vr5400:
3219 // end-sanitize-vr5400
3220 // start-sanitize-r5900
3221 *r5900:
3222 // end-sanitize-r5900
3223 *r3900:
3224 // start-sanitize-tx19
3225 *tx19:
3226 // end-sanitize-tx19
3227 {
3228   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3229 }
3230
3231
3232 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3233 {
3234   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3235   address_word reverseendian = (ReverseEndian ? -1 : 0);
3236   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3237   unsigned int byte;
3238   address_word paddr;
3239   int uncached;
3240   unsigned64 memval;
3241   address_word vaddr;
3242
3243   vaddr = base + offset;
3244   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3245   paddr = (paddr ^ (reverseendian & mask));
3246   if (BigEndianMem != 0)
3247     paddr &= ~access;
3248   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3249   memval = (rt << (byte * 8));
3250   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3251 }
3252
3253 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3254 "swr r<RT>, <OFFSET>(r<BASE>)"
3255 *mipsI,mipsII,mipsIII,mipsIV:
3256 *vr5000:
3257 // start-sanitize-vr4320
3258 *vr4320:
3259 // end-sanitize-vr4320
3260 // start-sanitize-vr5400
3261 *vr5400:
3262 // end-sanitize-vr5400
3263 // start-sanitize-r5900
3264 *r5900:
3265 // end-sanitize-r5900
3266 *r3900:
3267 // start-sanitize-tx19
3268 *tx19:
3269 // end-sanitize-tx19
3270 {
3271   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3272 }
3273
3274
3275 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3276 "sync":STYPE == 0
3277 "sync <STYPE>"
3278 *mipsII:
3279 *mipsIII:
3280 *mipsIV:
3281 *vr5000:
3282 // start-sanitize-vr4320
3283 *vr4320:
3284 // end-sanitize-vr4320
3285 // start-sanitize-vr5400
3286 *vr5400:
3287 // end-sanitize-vr5400
3288 // start-sanitize-r5900
3289 *r5900:
3290 // end-sanitize-r5900
3291 *r3900:
3292 // start-sanitize-tx19
3293 *tx19:
3294 // end-sanitize-tx19
3295 {
3296   SyncOperation (STYPE);
3297 }
3298
3299
3300 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3301 "syscall <CODE>"
3302 *mipsI,mipsII,mipsIII,mipsIV:
3303 *vr5000:
3304 // start-sanitize-vr4320
3305 *vr4320:
3306 // end-sanitize-vr4320
3307 // start-sanitize-vr5400
3308 *vr5400:
3309 // end-sanitize-vr5400
3310 // start-sanitize-r5900
3311 *r5900:
3312 // end-sanitize-r5900
3313 *r3900:
3314 // start-sanitize-tx19
3315 *tx19:
3316 // end-sanitize-tx19
3317 {
3318   SignalException(SystemCall, instruction_0);
3319 }
3320
3321
3322 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3323 "teq r<RS>, r<RT>"
3324 *mipsII:
3325 *mipsIII:
3326 *mipsIV:
3327 *vr5000:
3328 // start-sanitize-vr4320
3329 *vr4320:
3330 // end-sanitize-vr4320
3331 // start-sanitize-vr5400
3332 *vr5400:
3333 // end-sanitize-vr5400
3334 // start-sanitize-r5900
3335 *r5900:
3336 // end-sanitize-r5900
3337 // start-sanitize-tx19
3338 *tx19:
3339 // end-sanitize-tx19
3340 {
3341   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3342     SignalException(Trap, instruction_0);
3343 }
3344
3345
3346 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3347 "teqi r<RS>, <IMMEDIATE>"
3348 *mipsII:
3349 *mipsIII:
3350 *mipsIV:
3351 *vr5000:
3352 // start-sanitize-vr4320
3353 *vr4320:
3354 // end-sanitize-vr4320
3355 // start-sanitize-vr5400
3356 *vr5400:
3357 // end-sanitize-vr5400
3358 // start-sanitize-r5900
3359 *r5900:
3360 // end-sanitize-r5900
3361 // start-sanitize-tx19
3362 *tx19:
3363 // end-sanitize-tx19
3364 {
3365   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3366     SignalException(Trap, instruction_0);
3367 }
3368
3369
3370 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3371 "tge r<RS>, r<RT>"
3372 *mipsII:
3373 *mipsIII:
3374 *mipsIV:
3375 *vr5000:
3376 // start-sanitize-vr4320
3377 *vr4320:
3378 // end-sanitize-vr4320
3379 // start-sanitize-vr5400
3380 *vr5400:
3381 // end-sanitize-vr5400
3382 // start-sanitize-r5900
3383 *r5900:
3384 // end-sanitize-r5900
3385 // start-sanitize-tx19
3386 *tx19:
3387 // end-sanitize-tx19
3388 {
3389   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3390     SignalException(Trap, instruction_0);
3391 }
3392
3393
3394 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3395 "tgei r<RS>, <IMMEDIATE>"
3396 *mipsII:
3397 *mipsIII:
3398 *mipsIV:
3399 *vr5000:
3400 // start-sanitize-vr4320
3401 *vr4320:
3402 // end-sanitize-vr4320
3403 // start-sanitize-vr5400
3404 *vr5400:
3405 // end-sanitize-vr5400
3406 // start-sanitize-r5900
3407 *r5900:
3408 // end-sanitize-r5900
3409 // start-sanitize-tx19
3410 *tx19:
3411 // end-sanitize-tx19
3412 {
3413   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3414     SignalException(Trap, instruction_0);
3415 }
3416
3417
3418 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3419 "tgeiu r<RS>, <IMMEDIATE>"
3420 *mipsII:
3421 *mipsIII:
3422 *mipsIV:
3423 *vr5000:
3424 // start-sanitize-vr4320
3425 *vr4320:
3426 // end-sanitize-vr4320
3427 // start-sanitize-vr5400
3428 *vr5400:
3429 // end-sanitize-vr5400
3430 // start-sanitize-r5900
3431 *r5900:
3432 // end-sanitize-r5900
3433 // start-sanitize-tx19
3434 *tx19:
3435 // end-sanitize-tx19
3436 {
3437   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3438     SignalException(Trap, instruction_0);
3439 }
3440
3441
3442 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3443 "tgeu r<RS>, r<RT>"
3444 *mipsII:
3445 *mipsIII:
3446 *mipsIV:
3447 *vr5000:
3448 // start-sanitize-vr4320
3449 *vr4320:
3450 // end-sanitize-vr4320
3451 // start-sanitize-vr5400
3452 *vr5400:
3453 // end-sanitize-vr5400
3454 // start-sanitize-r5900
3455 *r5900:
3456 // end-sanitize-r5900
3457 // start-sanitize-tx19
3458 *tx19:
3459 // end-sanitize-tx19
3460 {
3461   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3462     SignalException(Trap, instruction_0);
3463 }
3464
3465
3466 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3467 "tlt r<RS>, r<RT>"
3468 *mipsII:
3469 *mipsIII:
3470 *mipsIV:
3471 *vr5000:
3472 // start-sanitize-vr4320
3473 *vr4320:
3474 // end-sanitize-vr4320
3475 // start-sanitize-vr5400
3476 *vr5400:
3477 // end-sanitize-vr5400
3478 // start-sanitize-r5900
3479 *r5900:
3480 // end-sanitize-r5900
3481 // start-sanitize-tx19
3482 *tx19:
3483 // end-sanitize-tx19
3484 {
3485   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3486     SignalException(Trap, instruction_0);
3487 }
3488
3489
3490 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3491 "tlti r<RS>, <IMMEDIATE>"
3492 *mipsII:
3493 *mipsIII:
3494 *mipsIV:
3495 *vr5000:
3496 // start-sanitize-vr4320
3497 *vr4320:
3498 // end-sanitize-vr4320
3499 // start-sanitize-vr5400
3500 *vr5400:
3501 // end-sanitize-vr5400
3502 // start-sanitize-r5900
3503 *r5900:
3504 // end-sanitize-r5900
3505 // start-sanitize-tx19
3506 *tx19:
3507 // end-sanitize-tx19
3508 {
3509   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3510     SignalException(Trap, instruction_0);
3511 }
3512
3513
3514 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3515 "tltiu r<RS>, <IMMEDIATE>"
3516 *mipsII:
3517 *mipsIII:
3518 *mipsIV:
3519 *vr5000:
3520 // start-sanitize-vr4320
3521 *vr4320:
3522 // end-sanitize-vr4320
3523 // start-sanitize-vr5400
3524 *vr5400:
3525 // end-sanitize-vr5400
3526 // start-sanitize-r5900
3527 *r5900:
3528 // end-sanitize-r5900
3529 // start-sanitize-tx19
3530 *tx19:
3531 // end-sanitize-tx19
3532 {
3533   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3534     SignalException(Trap, instruction_0);
3535 }
3536
3537
3538 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3539 "tltu r<RS>, r<RT>"
3540 *mipsII:
3541 *mipsIII:
3542 *mipsIV:
3543 *vr5000:
3544 // start-sanitize-vr4320
3545 *vr4320:
3546 // end-sanitize-vr4320
3547 // start-sanitize-vr5400
3548 *vr5400:
3549 // end-sanitize-vr5400
3550 // start-sanitize-r5900
3551 *r5900:
3552 // end-sanitize-r5900
3553 // start-sanitize-tx19
3554 *tx19:
3555 // end-sanitize-tx19
3556 {
3557   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3558     SignalException(Trap, instruction_0);
3559 }
3560
3561
3562 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3563 "tne r<RS>, r<RT>"
3564 *mipsII:
3565 *mipsIII:
3566 *mipsIV:
3567 *vr5000:
3568 // start-sanitize-vr4320
3569 *vr4320:
3570 // end-sanitize-vr4320
3571 // start-sanitize-vr5400
3572 *vr5400:
3573 // end-sanitize-vr5400
3574 // start-sanitize-r5900
3575 *r5900:
3576 // end-sanitize-r5900
3577 // start-sanitize-tx19
3578 *tx19:
3579 // end-sanitize-tx19
3580 {
3581   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3582     SignalException(Trap, instruction_0);
3583 }
3584
3585
3586 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3587 "tne r<RS>, <IMMEDIATE>"
3588 *mipsII:
3589 *mipsIII:
3590 *mipsIV:
3591 *vr5000:
3592 // start-sanitize-vr4320
3593 *vr4320:
3594 // end-sanitize-vr4320
3595 // start-sanitize-vr5400
3596 *vr5400:
3597 // end-sanitize-vr5400
3598 // start-sanitize-r5900
3599 *r5900:
3600 // end-sanitize-r5900
3601 // start-sanitize-tx19
3602 *tx19:
3603 // end-sanitize-tx19
3604 {
3605   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3606     SignalException(Trap, instruction_0);
3607 }
3608
3609
3610 :function:::void:do_xor:int rs, int rt, int rd
3611 {
3612   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3613   GPR[rd] = GPR[rs] ^ GPR[rt];
3614   TRACE_ALU_RESULT (GPR[rd]);
3615 }
3616
3617 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3618 "xor r<RD>, r<RS>, r<RT>"
3619 *mipsI,mipsII,mipsIII,mipsIV:
3620 *vr5000:
3621 // start-sanitize-vr4320
3622 *vr4320:
3623 // end-sanitize-vr4320
3624 // start-sanitize-vr5400
3625 *vr5400:
3626 // end-sanitize-vr5400
3627 // start-sanitize-r5900
3628 *r5900:
3629 // end-sanitize-r5900
3630 *r3900:
3631 // start-sanitize-tx19
3632 *tx19:
3633 // end-sanitize-tx19
3634 {
3635   do_xor (SD_, RS, RT, RD);
3636 }
3637
3638
3639 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3640 {
3641   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3642   GPR[rt] = GPR[rs] ^ immediate;
3643   TRACE_ALU_RESULT (GPR[rt]);
3644 }
3645
3646 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3647 "xori r<RT>, r<RS>, <IMMEDIATE>"
3648 *mipsI,mipsII,mipsIII,mipsIV:
3649 *vr5000:
3650 // start-sanitize-vr4320
3651 *vr4320:
3652 // end-sanitize-vr4320
3653 // start-sanitize-vr5400
3654 *vr5400:
3655 // end-sanitize-vr5400
3656 // start-sanitize-r5900
3657 *r5900:
3658 // end-sanitize-r5900
3659 *r3900:
3660 // start-sanitize-tx19
3661 *tx19:
3662 // end-sanitize-tx19
3663 {
3664   do_xori (SD_, RS, RT, IMMEDIATE);
3665 }
3666
3667 \f
3668 //
3669 // MIPS Architecture:
3670 //
3671 //        FPU Instruction Set (COP1 & COP1X)
3672 //
3673
3674
3675 :%s::::FMT:int fmt
3676 {
3677   switch (fmt)
3678     {
3679     case fmt_single: return "s";
3680     case fmt_double: return "d";
3681     case fmt_word: return "w";
3682     case fmt_long: return "l";
3683     default: return "?";
3684     }
3685 }
3686
3687 :%s::::X:int x
3688 {
3689   switch (x)
3690     {
3691     case 0: return "f";
3692     case 1: return "t";
3693     default: return "?";
3694     }
3695 }
3696
3697 :%s::::TF:int tf
3698 {
3699   if (tf)
3700     return "t";
3701   else
3702     return "f";
3703 }
3704
3705 :%s::::ND:int nd
3706 {
3707   if (nd)
3708     return "l";
3709   else
3710     return "";
3711 }
3712
3713 :%s::::COND:int cond
3714 {
3715   switch (cond)
3716     {
3717     case 00: return "f";
3718     case 01: return "un";
3719     case 02: return "eq";
3720     case 03: return "ueq";
3721     case 04: return "olt";
3722     case 05: return "ult";
3723     case 06: return "ole";
3724     case 07: return "ule";
3725     case 010: return "sf";
3726     case 011: return "ngle";
3727     case 012: return "seq";
3728     case 013: return "ngl";
3729     case 014: return "lt";
3730     case 015: return "nge";
3731     case 016: return "le";
3732     case 017: return "ngt";
3733     default: return "?";
3734     }
3735 }
3736
3737
3738 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3739 "abs.%s<FMT> f<FD>, f<FS>"
3740 *mipsI,mipsII,mipsIII,mipsIV:
3741 *vr5000:
3742 // start-sanitize-vr4320
3743 *vr4320:
3744 // end-sanitize-vr4320
3745 // start-sanitize-vr5400
3746 *vr5400:
3747 // end-sanitize-vr5400
3748 *r3900:
3749 // start-sanitize-tx19
3750 *tx19:
3751 // end-sanitize-tx19
3752 {
3753   unsigned32 instruction = instruction_0;
3754   int destreg = ((instruction >> 6) & 0x0000001F);
3755   int fs = ((instruction >> 11) & 0x0000001F);
3756   int format = ((instruction >> 21) & 0x00000007);
3757   {
3758     if ((format != fmt_single) && (format != fmt_double))
3759       SignalException(ReservedInstruction,instruction);
3760     else
3761       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3762   }
3763 }
3764
3765
3766
3767 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3768 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3769 *mipsI,mipsII,mipsIII,mipsIV:
3770 *vr5000:
3771 // start-sanitize-vr4320
3772 *vr4320:
3773 // end-sanitize-vr4320
3774 // start-sanitize-vr5400
3775 *vr5400:
3776 // end-sanitize-vr5400
3777 *r3900:
3778 // start-sanitize-tx19
3779 *tx19:
3780 // end-sanitize-tx19
3781 {
3782   unsigned32 instruction = instruction_0;
3783   int destreg = ((instruction >> 6) & 0x0000001F);
3784   int fs = ((instruction >> 11) & 0x0000001F);
3785   int ft = ((instruction >> 16) & 0x0000001F);
3786   int format = ((instruction >> 21) & 0x00000007);
3787   {
3788     if ((format != fmt_single) && (format != fmt_double))
3789       SignalException(ReservedInstruction, instruction);
3790     else
3791       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3792   }
3793 }
3794
3795
3796
3797 // BC1F
3798 // BC1FL
3799 // BC1T
3800 // BC1TL
3801
3802 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3803 "bc1%s<TF>%s<ND> <OFFSET>"
3804 *mipsI,mipsII,mipsIII:
3805 // start-sanitize-r5900
3806 *r5900:
3807 // end-sanitize-r5900
3808 {
3809   TRACE_BRANCH_INPUT (PREVCOC1());
3810   if (PREVCOC1() == TF)
3811     {
3812       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3813       TRACE_BRANCH_RESULT (dest);
3814       DELAY_SLOT (dest);
3815     }
3816   else if (ND)
3817     {
3818       TRACE_BRANCH_RESULT (0);
3819       NULLIFY_NEXT_INSTRUCTION ();
3820     }
3821   else
3822     {
3823       TRACE_BRANCH_RESULT (NIA);
3824     }
3825 }
3826
3827 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3828 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3829 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3830 *mipsIV:
3831 *vr5000:
3832 // start-sanitize-vr4320
3833 *vr4320:
3834 // end-sanitize-vr4320
3835 // start-sanitize-vr5400
3836 *vr5400:
3837 // end-sanitize-vr5400
3838 *r3900:
3839 // start-sanitize-tx19
3840 *tx19:
3841 // end-sanitize-tx19
3842 {
3843   if (GETFCC(CC) == TF)
3844     {
3845       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3846     }
3847   else if (ND)
3848     {
3849       NULLIFY_NEXT_INSTRUCTION ();
3850     }
3851 }
3852
3853
3854
3855 // C.EQ.S
3856 // C.EQ.D
3857 // ...
3858
3859 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3860 {
3861   if ((fmt != fmt_single) && (fmt != fmt_double))
3862     SignalException (ReservedInstruction, insn);
3863   else
3864     {
3865       int less;
3866       int equal;
3867       int unordered;
3868       int condition;
3869       unsigned64 ofs = ValueFPR (fs, fmt);
3870       unsigned64 oft = ValueFPR (ft, fmt);
3871       if (NaN (ofs, fmt) || NaN (oft, fmt))
3872         {
3873           if (FCSR & FP_ENABLE (IO))
3874             {
3875               FCSR |= FP_CAUSE (IO);
3876               SignalExceptionFPE ();
3877             }
3878           less = 0;
3879           equal = 0;
3880           unordered = 1;
3881         }
3882       else
3883         {
3884           less = Less (ofs, oft, fmt);
3885           equal = Equal (ofs, oft, fmt);
3886           unordered = 0;
3887         }
3888       condition = (((cond & (1 << 2)) && less)
3889                    || ((cond & (1 << 1)) && equal)
3890                    || ((cond & (1 << 0)) && unordered));
3891       SETFCC (cc, condition);
3892     }
3893 }
3894
3895 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3896 *mipsI,mipsII,mipsIII:
3897 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3898 {
3899   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3900 }
3901
3902 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3903 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3904 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3905 *mipsIV:
3906 *vr5000:
3907 // start-sanitize-vr4320
3908 *vr4320:
3909 // end-sanitize-vr4320
3910 // start-sanitize-vr5400
3911 *vr5400:
3912 // end-sanitize-vr5400
3913 *r3900:
3914 // start-sanitize-tx19
3915 *tx19:
3916 // end-sanitize-tx19
3917 {
3918   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3919 }
3920
3921
3922 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3923 "ceil.l.%s<FMT> f<FD>, f<FS>"
3924 *mipsIII:
3925 *mipsIV:
3926 *vr5000:
3927 // start-sanitize-vr4320
3928 *vr4320:
3929 // end-sanitize-vr4320
3930 // start-sanitize-vr5400
3931 *vr5400:
3932 // end-sanitize-vr5400
3933 // start-sanitize-r5900
3934 *r5900:
3935 // end-sanitize-r5900
3936 *r3900:
3937 // start-sanitize-tx19
3938 *tx19:
3939 // end-sanitize-tx19
3940 {
3941   unsigned32 instruction = instruction_0;
3942   int destreg = ((instruction >> 6) & 0x0000001F);
3943   int fs = ((instruction >> 11) & 0x0000001F);
3944   int format = ((instruction >> 21) & 0x00000007);
3945   {
3946     if ((format != fmt_single) && (format != fmt_double))
3947       SignalException(ReservedInstruction,instruction);
3948     else
3949       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3950   }
3951 }
3952
3953
3954 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3955 *mipsII:
3956 *mipsIII:
3957 *mipsIV:
3958 *vr5000:
3959 // start-sanitize-vr4320
3960 *vr4320:
3961 // end-sanitize-vr4320
3962 // start-sanitize-vr5400
3963 *vr5400:
3964 // end-sanitize-vr5400
3965 // start-sanitize-r5900
3966 *r5900:
3967 // end-sanitize-r5900
3968 *r3900:
3969 // start-sanitize-tx19
3970 *tx19:
3971 // end-sanitize-tx19
3972 {
3973   unsigned32 instruction = instruction_0;
3974   int destreg = ((instruction >> 6) & 0x0000001F);
3975   int fs = ((instruction >> 11) & 0x0000001F);
3976   int format = ((instruction >> 21) & 0x00000007);
3977   {
3978   if ((format != fmt_single) && (format != fmt_double))
3979    SignalException(ReservedInstruction,instruction);
3980   else
3981    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3982   }
3983 }
3984
3985
3986 // CFC1
3987 // CTC1
3988 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3989 "c%s<X>c1 r<RT>, f<FS>"
3990 *mipsI:
3991 *mipsII:
3992 *mipsIII:
3993 {
3994   if (X)
3995     {
3996       if (FS == 0)
3997         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3998       else if (FS == 31)
3999         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4000       /* else NOP */
4001       PENDING_FILL(COCIDX,0); /* special case */
4002     }
4003   else
4004     { /* control from */
4005       if (FS == 0)
4006         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4007       else if (FS == 31)
4008         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4009       /* else NOP */
4010     }
4011 }
4012 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4013 "c%s<X>c1 r<RT>, f<FS>"
4014 *mipsIV:
4015 *vr5000:
4016 // start-sanitize-vr4320
4017 *vr4320:
4018 // end-sanitize-vr4320
4019 // start-sanitize-vr5400
4020 *vr5400:
4021 // end-sanitize-vr5400
4022 *r3900:
4023 // start-sanitize-tx19
4024 *tx19:
4025 // end-sanitize-tx19
4026 {
4027   if (X)
4028     {
4029       /* control to */
4030       TRACE_ALU_INPUT1 (GPR[RT]);
4031       if (FS == 0)
4032         {
4033           FCR0 = VL4_8(GPR[RT]);
4034           TRACE_ALU_RESULT (FCR0);
4035         }
4036       else if (FS == 31)
4037         {
4038           FCR31 = VL4_8(GPR[RT]);
4039           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4040           TRACE_ALU_RESULT (FCR31);
4041         }
4042       else
4043         {
4044           TRACE_ALU_RESULT0 ();
4045         }
4046       /* else NOP */
4047     }
4048   else
4049     { /* control from */
4050       if (FS == 0)
4051         {
4052           TRACE_ALU_INPUT1 (FCR0);
4053           GPR[RT] = SIGNEXTEND (FCR0, 32);
4054         }
4055       else if (FS == 31)
4056         {
4057           TRACE_ALU_INPUT1 (FCR31);
4058           GPR[RT] = SIGNEXTEND (FCR31, 32);
4059         }
4060       TRACE_ALU_RESULT (GPR[RT]);
4061       /* else NOP */
4062     }
4063 }
4064
4065
4066 //
4067 // FIXME: Does not correctly differentiate between mips*
4068 //
4069 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4070 "cvt.d.%s<FMT> f<FD>, f<FS>"
4071 *mipsI,mipsII,mipsIII,mipsIV:
4072 *vr5000:
4073 // start-sanitize-vr4320
4074 *vr4320:
4075 // end-sanitize-vr4320
4076 // start-sanitize-vr5400
4077 *vr5400:
4078 // end-sanitize-vr5400
4079 *r3900:
4080 // start-sanitize-tx19
4081 *tx19:
4082 // end-sanitize-tx19
4083 {
4084   unsigned32 instruction = instruction_0;
4085   int destreg = ((instruction >> 6) & 0x0000001F);
4086   int fs = ((instruction >> 11) & 0x0000001F);
4087   int format = ((instruction >> 21) & 0x00000007);
4088   {
4089     if ((format == fmt_double) | 0)
4090       SignalException(ReservedInstruction,instruction);
4091     else
4092       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4093   }
4094 }
4095
4096
4097 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4098 "cvt.l.%s<FMT> f<FD>, f<FS>"
4099 *mipsIII:
4100 *mipsIV:
4101 *vr5000:
4102 // start-sanitize-vr4320
4103 *vr4320:
4104 // end-sanitize-vr4320
4105 // start-sanitize-vr5400
4106 *vr5400:
4107 // end-sanitize-vr5400
4108 *r3900:
4109 // start-sanitize-tx19
4110 *tx19:
4111 // end-sanitize-tx19
4112 {
4113   unsigned32 instruction = instruction_0;
4114   int destreg = ((instruction >> 6) & 0x0000001F);
4115   int fs = ((instruction >> 11) & 0x0000001F);
4116   int format = ((instruction >> 21) & 0x00000007);
4117   {
4118     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4119       SignalException(ReservedInstruction,instruction);
4120     else
4121       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4122   }
4123 }
4124
4125
4126 //
4127 // FIXME: Does not correctly differentiate between mips*
4128 //
4129 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4130 "cvt.s.%s<FMT> f<FD>, f<FS>"
4131 *mipsI,mipsII,mipsIII,mipsIV:
4132 *vr5000:
4133 // start-sanitize-vr4320
4134 *vr4320:
4135 // end-sanitize-vr4320
4136 // start-sanitize-vr5400
4137 *vr5400:
4138 // end-sanitize-vr5400
4139 *r3900:
4140 // start-sanitize-tx19
4141 *tx19:
4142 // end-sanitize-tx19
4143 {
4144   unsigned32 instruction = instruction_0;
4145   int destreg = ((instruction >> 6) & 0x0000001F);
4146   int fs = ((instruction >> 11) & 0x0000001F);
4147   int format = ((instruction >> 21) & 0x00000007);
4148   {
4149     if ((format == fmt_single) | 0)
4150       SignalException(ReservedInstruction,instruction);
4151     else
4152       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4153   }
4154 }
4155
4156
4157 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4158 "cvt.w.%s<FMT> f<FD>, f<FS>"
4159 *mipsI,mipsII,mipsIII,mipsIV:
4160 *vr5000:
4161 // start-sanitize-vr4320
4162 *vr4320:
4163 // end-sanitize-vr4320
4164 // start-sanitize-vr5400
4165 *vr5400:
4166 // end-sanitize-vr5400
4167 *r3900:
4168 // start-sanitize-tx19
4169 *tx19:
4170 // end-sanitize-tx19
4171 {
4172   unsigned32 instruction = instruction_0;
4173   int destreg = ((instruction >> 6) & 0x0000001F);
4174   int fs = ((instruction >> 11) & 0x0000001F);
4175   int format = ((instruction >> 21) & 0x00000007);
4176   {
4177     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4178       SignalException(ReservedInstruction,instruction);
4179     else
4180       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4181   }
4182 }
4183
4184
4185 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4186 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4187 *mipsI,mipsII,mipsIII,mipsIV:
4188 *vr5000:
4189 // start-sanitize-vr4320
4190 *vr4320:
4191 // end-sanitize-vr4320
4192 // start-sanitize-vr5400
4193 *vr5400:
4194 // end-sanitize-vr5400
4195 *r3900:
4196 // start-sanitize-tx19
4197 *tx19:
4198 // end-sanitize-tx19
4199 {
4200   unsigned32 instruction = instruction_0;
4201   int destreg = ((instruction >> 6) & 0x0000001F);
4202   int fs = ((instruction >> 11) & 0x0000001F);
4203   int ft = ((instruction >> 16) & 0x0000001F);
4204   int format = ((instruction >> 21) & 0x00000007);
4205   {
4206     if ((format != fmt_single) && (format != fmt_double))
4207       SignalException(ReservedInstruction,instruction);
4208     else
4209       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4210   }
4211 }
4212
4213
4214 // DMFC1
4215 // DMTC1
4216 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4217 "dm%s<X>c1 r<RT>, f<FS>"
4218 *mipsIII:
4219 {
4220   if (X)
4221     {
4222       if (SizeFGR() == 64)
4223         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4224       else if ((FS & 0x1) == 0)
4225         {
4226           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4227           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4228         }
4229     }
4230   else
4231     {
4232       if (SizeFGR() == 64)
4233         PENDING_FILL(RT,FGR[FS]);
4234       else if ((FS & 0x1) == 0)
4235         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4236       else
4237         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4238     }
4239 }
4240 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4241 "dm%s<X>c1 r<RT>, f<FS>"
4242 *mipsIV:
4243 *vr5000:
4244 // start-sanitize-vr4320
4245 *vr4320:
4246 // end-sanitize-vr4320
4247 // start-sanitize-vr5400
4248 *vr5400:
4249 // end-sanitize-vr5400
4250 // start-sanitize-r5900
4251 *r5900:
4252 // end-sanitize-r5900
4253 *r3900:
4254 // start-sanitize-tx19
4255 *tx19:
4256 // end-sanitize-tx19
4257 {
4258   if (X)
4259     {
4260       if (SizeFGR() == 64)
4261         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4262       else if ((FS & 0x1) == 0)
4263         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4264     }
4265   else
4266     {
4267       if (SizeFGR() == 64)
4268         GPR[RT] = FGR[FS];
4269       else if ((FS & 0x1) == 0)
4270         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4271       else
4272         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4273     }
4274 }
4275
4276
4277 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4278 "floor.l.%s<FMT> f<FD>, f<FS>"
4279 *mipsIII:
4280 *mipsIV:
4281 *vr5000:
4282 // start-sanitize-vr4320
4283 *vr4320:
4284 // end-sanitize-vr4320
4285 // start-sanitize-vr5400
4286 *vr5400:
4287 // end-sanitize-vr5400
4288 // start-sanitize-r5900
4289 *r5900:
4290 // end-sanitize-r5900
4291 *r3900:
4292 // start-sanitize-tx19
4293 *tx19:
4294 // end-sanitize-tx19
4295 {
4296   unsigned32 instruction = instruction_0;
4297   int destreg = ((instruction >> 6) & 0x0000001F);
4298   int fs = ((instruction >> 11) & 0x0000001F);
4299   int format = ((instruction >> 21) & 0x00000007);
4300   {
4301     if ((format != fmt_single) && (format != fmt_double))
4302       SignalException(ReservedInstruction,instruction);
4303     else
4304       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4305   }
4306 }
4307
4308
4309 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4310 "floor.w.%s<FMT> f<FD>, f<FS>"
4311 *mipsII:
4312 *mipsIII:
4313 *mipsIV:
4314 *vr5000:
4315 // start-sanitize-vr4320
4316 *vr4320:
4317 // end-sanitize-vr4320
4318 // start-sanitize-vr5400
4319 *vr5400:
4320 // end-sanitize-vr5400
4321 // start-sanitize-r5900
4322 *r5900:
4323 // end-sanitize-r5900
4324 *r3900:
4325 // start-sanitize-tx19
4326 *tx19:
4327 // end-sanitize-tx19
4328 {
4329   unsigned32 instruction = instruction_0;
4330   int destreg = ((instruction >> 6) & 0x0000001F);
4331   int fs = ((instruction >> 11) & 0x0000001F);
4332   int format = ((instruction >> 21) & 0x00000007);
4333   {
4334     if ((format != fmt_single) && (format != fmt_double))
4335       SignalException(ReservedInstruction,instruction);
4336     else
4337       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4338   }
4339 }
4340
4341
4342 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4343 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4344 *mipsII:
4345 *mipsIII:
4346 *mipsIV:
4347 *vr5000:
4348 // start-sanitize-vr4320
4349 *vr4320:
4350 // end-sanitize-vr4320
4351 // start-sanitize-vr5400
4352 *vr5400:
4353 // end-sanitize-vr5400
4354 *r3900:
4355 // start-sanitize-tx19
4356 *tx19:
4357 // end-sanitize-tx19
4358 {
4359   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4360 }
4361
4362
4363 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4364 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4365 *mipsIV:
4366 *vr5000:
4367 // start-sanitize-vr4320
4368 *vr4320:
4369 // end-sanitize-vr4320
4370 // start-sanitize-vr5400
4371 *vr5400:
4372 // end-sanitize-vr5400
4373 {
4374   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4375 }
4376
4377
4378
4379 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4380 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4381 *mipsI,mipsII,mipsIII,mipsIV:
4382 *vr5000:
4383 // start-sanitize-vr4320
4384 *vr4320:
4385 // end-sanitize-vr4320
4386 // start-sanitize-vr5400
4387 *vr5400:
4388 // end-sanitize-vr5400
4389 // start-sanitize-r5900
4390 *r5900:
4391 // end-sanitize-r5900
4392 *r3900:
4393 // start-sanitize-tx19
4394 *tx19:
4395 // end-sanitize-tx19
4396 {
4397   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4398 }
4399
4400
4401 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4402 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4403 *mipsIV:
4404 *vr5000:
4405 // start-sanitize-vr4320
4406 *vr4320:
4407 // end-sanitize-vr4320
4408 // start-sanitize-vr5400
4409 *vr5400:
4410 // end-sanitize-vr5400
4411 {
4412   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4413 }
4414
4415
4416
4417 //
4418 // FIXME: Not correct for mips*
4419 //
4420 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4421 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4422 *mipsIV:
4423 *vr5000:
4424 // start-sanitize-vr4320
4425 *vr4320:
4426 // end-sanitize-vr4320
4427 // start-sanitize-vr5400
4428 *vr5400:
4429 // end-sanitize-vr5400
4430 {
4431   unsigned32 instruction = instruction_0;
4432   int destreg = ((instruction >> 6) & 0x0000001F);
4433   int fs = ((instruction >> 11) & 0x0000001F);
4434   int ft = ((instruction >> 16) & 0x0000001F);
4435   int fr = ((instruction >> 21) & 0x0000001F);
4436   {
4437     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4438   }
4439 }
4440
4441
4442 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4443 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4444 *mipsIV:
4445 *vr5000:
4446 // start-sanitize-vr4320
4447 *vr4320:
4448 // end-sanitize-vr4320
4449 // start-sanitize-vr5400
4450 *vr5400:
4451 // end-sanitize-vr5400
4452 {
4453   unsigned32 instruction = instruction_0;
4454   int destreg = ((instruction >> 6) & 0x0000001F);
4455   int fs = ((instruction >> 11) & 0x0000001F);
4456   int ft = ((instruction >> 16) & 0x0000001F);
4457   int fr = ((instruction >> 21) & 0x0000001F);
4458   {
4459     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4460   }
4461 }
4462
4463
4464 // MFC1
4465 // MTC1
4466 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4467 "m%s<X>c1 r<RT>, f<FS>"
4468 *mipsI:
4469 *mipsII:
4470 *mipsIII:
4471 {
4472   if (X)
4473     { /*MTC1*/
4474       if (SizeFGR() == 64)
4475         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4476       else
4477         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4478     }
4479   else /*MFC1*/
4480     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4481 }
4482 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4483 "m%s<X>c1 r<RT>, f<FS>"
4484 *mipsIV:
4485 *vr5000:
4486 // start-sanitize-vr4320
4487 *vr4320:
4488 // end-sanitize-vr4320
4489 // start-sanitize-vr5400
4490 *vr5400:
4491 // end-sanitize-vr5400
4492 *r3900:
4493 // start-sanitize-tx19
4494 *tx19:
4495 // end-sanitize-tx19
4496 {
4497   if (X)
4498     /*MTC1*/
4499     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4500   else /*MFC1*/
4501     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4502 }
4503
4504
4505 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4506 "mov.%s<FMT> f<FD>, f<FS>"
4507 *mipsI,mipsII,mipsIII,mipsIV:
4508 *vr5000:
4509 // start-sanitize-vr4320
4510 *vr4320:
4511 // end-sanitize-vr4320
4512 // start-sanitize-vr5400
4513 *vr5400:
4514 // end-sanitize-vr5400
4515 *r3900:
4516 // start-sanitize-tx19
4517 *tx19:
4518 // end-sanitize-tx19
4519 {
4520   unsigned32 instruction = instruction_0;
4521   int destreg = ((instruction >> 6) & 0x0000001F);
4522   int fs = ((instruction >> 11) & 0x0000001F);
4523   int format = ((instruction >> 21) & 0x00000007);
4524   {
4525     StoreFPR(destreg,format,ValueFPR(fs,format));
4526   }
4527 }
4528
4529
4530 // MOVF
4531 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4532 "mov%s<TF> r<RD>, r<RS>, <CC>"
4533 *mipsIV:
4534 *vr5000:
4535 // start-sanitize-vr4320
4536 *vr4320:
4537 // end-sanitize-vr4320
4538 // start-sanitize-vr5400
4539 *vr5400:
4540 // end-sanitize-vr5400
4541 // start-sanitize-r5900
4542 *r5900:
4543 // end-sanitize-r5900
4544 {
4545   if (GETFCC(CC) == TF)
4546     GPR[RD] = GPR[RS];
4547 }
4548
4549
4550 // MOVF.fmt
4551 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4552 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4553 *mipsIV:
4554 *vr5000:
4555 // start-sanitize-vr4320
4556 *vr4320:
4557 // end-sanitize-vr4320
4558 // start-sanitize-vr5400
4559 *vr5400:
4560 // end-sanitize-vr5400
4561 // start-sanitize-r5900
4562 *r5900:
4563 // end-sanitize-r5900
4564 {
4565   unsigned32 instruction = instruction_0;
4566   int format = ((instruction >> 21) & 0x00000007);
4567   {
4568    if (GETFCC(CC) == TF)
4569      StoreFPR (FD, format, ValueFPR (FS, format));
4570    else
4571      StoreFPR (FD, format, ValueFPR (FD, format));
4572   }
4573 }
4574
4575
4576 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4577 *mipsIV:
4578 *vr5000:
4579 // start-sanitize-vr4320
4580 *vr4320:
4581 // end-sanitize-vr4320
4582 // start-sanitize-vr5400
4583 *vr5400:
4584 // end-sanitize-vr5400
4585 // start-sanitize-r5900
4586 *r5900:
4587 // end-sanitize-r5900
4588 {
4589   unsigned32 instruction = instruction_0;
4590   int destreg = ((instruction >> 6) & 0x0000001F);
4591   int fs = ((instruction >> 11) & 0x0000001F);
4592   int format = ((instruction >> 21) & 0x00000007);
4593   {
4594     StoreFPR(destreg,format,ValueFPR(fs,format));
4595   }
4596 }
4597
4598
4599 // MOVT see MOVtf
4600
4601
4602 // MOVT.fmt see MOVtf.fmt
4603
4604
4605
4606 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4607 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4608 *mipsIV:
4609 *vr5000:
4610 // start-sanitize-vr4320
4611 *vr4320:
4612 // end-sanitize-vr4320
4613 // start-sanitize-vr5400
4614 *vr5400:
4615 // end-sanitize-vr5400
4616 // start-sanitize-r5900
4617 *r5900:
4618 // end-sanitize-r5900
4619 {
4620   unsigned32 instruction = instruction_0;
4621   int destreg = ((instruction >> 6) & 0x0000001F);
4622   int fs = ((instruction >> 11) & 0x0000001F);
4623   int format = ((instruction >> 21) & 0x00000007);
4624   {
4625    StoreFPR(destreg,format,ValueFPR(fs,format));
4626   }
4627 }
4628
4629
4630 // MSUB.fmt
4631 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4632 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4633 *mipsIV:
4634 *vr5000:
4635 // start-sanitize-vr4320
4636 *vr4320:
4637 // end-sanitize-vr4320
4638 // start-sanitize-vr5400
4639 *vr5400:
4640 // end-sanitize-vr5400
4641 // start-sanitize-r5900
4642 *r5900:
4643 // end-sanitize-r5900
4644 {
4645   unsigned32 instruction = instruction_0;
4646   int destreg = ((instruction >> 6) & 0x0000001F);
4647   int fs = ((instruction >> 11) & 0x0000001F);
4648   int ft = ((instruction >> 16) & 0x0000001F);
4649   int fr = ((instruction >> 21) & 0x0000001F);
4650   {
4651     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4652   }
4653 }
4654
4655
4656 // MSUB.fmt
4657 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4658 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4659 *mipsIV:
4660 *vr5000:
4661 // start-sanitize-vr4320
4662 *vr4320:
4663 // end-sanitize-vr4320
4664 // start-sanitize-vr5400
4665 *vr5400:
4666 // end-sanitize-vr5400
4667 // start-sanitize-r5900
4668 *r5900:
4669 // end-sanitize-r5900
4670 {
4671   unsigned32 instruction = instruction_0;
4672   int destreg = ((instruction >> 6) & 0x0000001F);
4673   int fs = ((instruction >> 11) & 0x0000001F);
4674   int ft = ((instruction >> 16) & 0x0000001F);
4675   int fr = ((instruction >> 21) & 0x0000001F);
4676   {
4677    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4678   }
4679 }
4680
4681
4682 // MTC1 see MxC1
4683
4684
4685 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4686 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4687 *mipsI,mipsII,mipsIII,mipsIV:
4688 *vr5000:
4689 // start-sanitize-vr4320
4690 *vr4320:
4691 // end-sanitize-vr4320
4692 // start-sanitize-vr5400
4693 *vr5400:
4694 // end-sanitize-vr5400
4695 *r3900:
4696 // start-sanitize-tx19
4697 *tx19:
4698 // end-sanitize-tx19
4699 {
4700   unsigned32 instruction = instruction_0;
4701   int destreg = ((instruction >> 6) & 0x0000001F);
4702   int fs = ((instruction >> 11) & 0x0000001F);
4703   int ft = ((instruction >> 16) & 0x0000001F);
4704   int format = ((instruction >> 21) & 0x00000007);
4705   {
4706     if ((format != fmt_single) && (format != fmt_double))
4707       SignalException(ReservedInstruction,instruction);
4708     else
4709       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4710   }
4711 }
4712
4713
4714 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4715 "neg.%s<FMT> f<FD>, f<FS>"
4716 *mipsI,mipsII,mipsIII,mipsIV:
4717 *vr5000:
4718 // start-sanitize-vr4320
4719 *vr4320:
4720 // end-sanitize-vr4320
4721 // start-sanitize-vr5400
4722 *vr5400:
4723 // end-sanitize-vr5400
4724 *r3900:
4725 // start-sanitize-tx19
4726 *tx19:
4727 // end-sanitize-tx19
4728 {
4729   unsigned32 instruction = instruction_0;
4730   int destreg = ((instruction >> 6) & 0x0000001F);
4731   int fs = ((instruction >> 11) & 0x0000001F);
4732   int format = ((instruction >> 21) & 0x00000007);
4733   {
4734     if ((format != fmt_single) && (format != fmt_double))
4735       SignalException(ReservedInstruction,instruction);
4736     else
4737       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4738   }
4739 }
4740
4741
4742 // NMADD.fmt
4743 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4744 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4745 *mipsIV:
4746 *vr5000:
4747 // start-sanitize-vr4320
4748 *vr4320:
4749 // end-sanitize-vr4320
4750 // start-sanitize-vr5400
4751 *vr5400:
4752 // end-sanitize-vr5400
4753 {
4754   unsigned32 instruction = instruction_0;
4755   int destreg = ((instruction >> 6) & 0x0000001F);
4756   int fs = ((instruction >> 11) & 0x0000001F);
4757   int ft = ((instruction >> 16) & 0x0000001F);
4758   int fr = ((instruction >> 21) & 0x0000001F);
4759   {
4760    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4761   }
4762 }
4763
4764
4765 // NMADD.fmt
4766 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4767 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4768 *mipsIV:
4769 *vr5000:
4770 // start-sanitize-vr4320
4771 *vr4320:
4772 // end-sanitize-vr4320
4773 // start-sanitize-vr5400
4774 *vr5400:
4775 // end-sanitize-vr5400
4776 {
4777   unsigned32 instruction = instruction_0;
4778   int destreg = ((instruction >> 6) & 0x0000001F);
4779   int fs = ((instruction >> 11) & 0x0000001F);
4780   int ft = ((instruction >> 16) & 0x0000001F);
4781   int fr = ((instruction >> 21) & 0x0000001F);
4782   {
4783    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4784   }
4785 }
4786
4787
4788 // NMSUB.fmt
4789 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4790 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4791 *mipsIV:
4792 *vr5000:
4793 // start-sanitize-vr4320
4794 *vr4320:
4795 // end-sanitize-vr4320
4796 // start-sanitize-vr5400
4797 *vr5400:
4798 // end-sanitize-vr5400
4799 {
4800   unsigned32 instruction = instruction_0;
4801   int destreg = ((instruction >> 6) & 0x0000001F);
4802   int fs = ((instruction >> 11) & 0x0000001F);
4803   int ft = ((instruction >> 16) & 0x0000001F);
4804   int fr = ((instruction >> 21) & 0x0000001F);
4805   {
4806    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4807   }
4808 }
4809
4810
4811 // NMSUB.fmt
4812 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4813 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4814 *mipsIV:
4815 *vr5000:
4816 // start-sanitize-vr4320
4817 *vr4320:
4818 // end-sanitize-vr4320
4819 // start-sanitize-vr5400
4820 *vr5400:
4821 // end-sanitize-vr5400
4822 {
4823   unsigned32 instruction = instruction_0;
4824   int destreg = ((instruction >> 6) & 0x0000001F);
4825   int fs = ((instruction >> 11) & 0x0000001F);
4826   int ft = ((instruction >> 16) & 0x0000001F);
4827   int fr = ((instruction >> 21) & 0x0000001F);
4828   {
4829     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4830   }
4831 }
4832
4833
4834 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4835 "prefx <HINT>, r<INDEX>(r<BASE>)"
4836 *mipsIV:
4837 *vr5000:
4838 // start-sanitize-vr4320
4839 *vr4320:
4840 // end-sanitize-vr4320
4841 // start-sanitize-vr5400
4842 *vr5400:
4843 // end-sanitize-vr5400
4844 {
4845   unsigned32 instruction = instruction_0;
4846   int fs = ((instruction >> 11) & 0x0000001F);
4847   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4848   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4849   {
4850     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4851     address_word paddr;
4852     int uncached;
4853     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4854       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4855   }
4856 }
4857
4858 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4859 *mipsIV:
4860 "recip.%s<FMT> f<FD>, f<FS>"
4861 *vr5000:
4862 // start-sanitize-vr4320
4863 *vr4320:
4864 // end-sanitize-vr4320
4865 // start-sanitize-vr5400
4866 *vr5400:
4867 // end-sanitize-vr5400
4868 {
4869   unsigned32 instruction = instruction_0;
4870   int destreg = ((instruction >> 6) & 0x0000001F);
4871   int fs = ((instruction >> 11) & 0x0000001F);
4872   int format = ((instruction >> 21) & 0x00000007);
4873   {
4874   if ((format != fmt_single) && (format != fmt_double))
4875    SignalException(ReservedInstruction,instruction);
4876   else
4877    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4878   }
4879 }
4880
4881
4882 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4883 "round.l.%s<FMT> f<FD>, f<FS>"
4884 *mipsIII:
4885 *mipsIV:
4886 *vr5000:
4887 // start-sanitize-vr4320
4888 *vr4320:
4889 // end-sanitize-vr4320
4890 // start-sanitize-vr5400
4891 *vr5400:
4892 // end-sanitize-vr5400
4893 // start-sanitize-r5900
4894 *r5900:
4895 // end-sanitize-r5900
4896 *r3900:
4897 // start-sanitize-tx19
4898 *tx19:
4899 // end-sanitize-tx19
4900 {
4901   unsigned32 instruction = instruction_0;
4902   int destreg = ((instruction >> 6) & 0x0000001F);
4903   int fs = ((instruction >> 11) & 0x0000001F);
4904   int format = ((instruction >> 21) & 0x00000007);
4905   {
4906     if ((format != fmt_single) && (format != fmt_double))
4907       SignalException(ReservedInstruction,instruction);
4908     else
4909       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4910   }
4911 }
4912
4913
4914 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4915 "round.w.%s<FMT> f<FD>, f<FS>"
4916 *mipsII:
4917 *mipsIII:
4918 *mipsIV:
4919 *vr5000:
4920 // start-sanitize-vr4320
4921 *vr4320:
4922 // end-sanitize-vr4320
4923 // start-sanitize-vr5400
4924 *vr5400:
4925 // end-sanitize-vr5400
4926 // start-sanitize-r5900
4927 *r5900:
4928 // end-sanitize-r5900
4929 *r3900:
4930 // start-sanitize-tx19
4931 *tx19:
4932 // end-sanitize-tx19
4933 {
4934   unsigned32 instruction = instruction_0;
4935   int destreg = ((instruction >> 6) & 0x0000001F);
4936   int fs = ((instruction >> 11) & 0x0000001F);
4937   int format = ((instruction >> 21) & 0x00000007);
4938   {
4939   if ((format != fmt_single) && (format != fmt_double))
4940    SignalException(ReservedInstruction,instruction);
4941   else
4942    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4943   }
4944 }
4945
4946
4947 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4948 *mipsIV:
4949 "rsqrt.%s<FMT> f<FD>, f<FS>"
4950 *vr5000:
4951 // start-sanitize-vr4320
4952 *vr4320:
4953 // end-sanitize-vr4320
4954 // start-sanitize-vr5400
4955 *vr5400:
4956 // end-sanitize-vr5400
4957 {
4958   unsigned32 instruction = instruction_0;
4959   int destreg = ((instruction >> 6) & 0x0000001F);
4960   int fs = ((instruction >> 11) & 0x0000001F);
4961   int format = ((instruction >> 21) & 0x00000007);
4962   {
4963   if ((format != fmt_single) && (format != fmt_double))
4964    SignalException(ReservedInstruction,instruction);
4965   else
4966    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4967   }
4968 }
4969
4970
4971 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4972 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4973 *mipsII:
4974 *mipsIII:
4975 *mipsIV:
4976 *vr5000:
4977 // start-sanitize-vr4320
4978 *vr4320:
4979 // end-sanitize-vr4320
4980 // start-sanitize-vr5400
4981 *vr5400:
4982 // end-sanitize-vr5400
4983 *r3900:
4984 // start-sanitize-tx19
4985 *tx19:
4986 // end-sanitize-tx19
4987 {
4988   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4989 }
4990
4991
4992 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
4993 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
4994 *mipsIV:
4995 *vr5000:
4996 // start-sanitize-vr4320
4997 *vr4320:
4998 // end-sanitize-vr4320
4999 // start-sanitize-vr5400
5000 *vr5400:
5001 // end-sanitize-vr5400
5002 {
5003   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5004 }
5005
5006
5007 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5008 "sqrt.%s<FMT> f<FD>, f<FS>"
5009 *mipsII:
5010 *mipsIII:
5011 *mipsIV:
5012 *vr5000:
5013 // start-sanitize-vr4320
5014 *vr4320:
5015 // end-sanitize-vr4320
5016 // start-sanitize-vr5400
5017 *vr5400:
5018 // end-sanitize-vr5400
5019 *r3900:
5020 // start-sanitize-tx19
5021 *tx19:
5022 // end-sanitize-tx19
5023 {
5024   unsigned32 instruction = instruction_0;
5025   int destreg = ((instruction >> 6) & 0x0000001F);
5026   int fs = ((instruction >> 11) & 0x0000001F);
5027   int format = ((instruction >> 21) & 0x00000007);
5028   {
5029     if ((format != fmt_single) && (format != fmt_double))
5030       SignalException(ReservedInstruction,instruction);
5031     else
5032       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5033   }
5034 }
5035
5036
5037 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5038 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5039 *mipsI,mipsII,mipsIII,mipsIV:
5040 *vr5000:
5041 // start-sanitize-vr4320
5042 *vr4320:
5043 // end-sanitize-vr4320
5044 // start-sanitize-vr5400
5045 *vr5400:
5046 // end-sanitize-vr5400
5047 *r3900:
5048 // start-sanitize-tx19
5049 *tx19:
5050 // end-sanitize-tx19
5051 {
5052   unsigned32 instruction = instruction_0;
5053   int destreg = ((instruction >> 6) & 0x0000001F);
5054   int fs = ((instruction >> 11) & 0x0000001F);
5055   int ft = ((instruction >> 16) & 0x0000001F);
5056   int format = ((instruction >> 21) & 0x00000007);
5057   {
5058     if ((format != fmt_single) && (format != fmt_double))
5059       SignalException(ReservedInstruction,instruction);
5060     else
5061       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5062   }
5063 }
5064
5065
5066
5067 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5068 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5069 *mipsI,mipsII,mipsIII,mipsIV:
5070 *vr5000:
5071 // start-sanitize-vr4320
5072 *vr4320:
5073 // end-sanitize-vr4320
5074 // start-sanitize-vr5400
5075 *vr5400:
5076 // end-sanitize-vr5400
5077 // start-sanitize-r5900
5078 *r5900:
5079 // end-sanitize-r5900
5080 *r3900:
5081 // start-sanitize-tx19
5082 *tx19:
5083 // end-sanitize-tx19
5084 {
5085   unsigned32 instruction = instruction_0;
5086   signed_word offset = EXTEND16 (OFFSET);
5087   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5088   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5089   {
5090     address_word vaddr = ((uword64)op1 + offset);
5091     address_word paddr;
5092     int uncached;
5093     if ((vaddr & 3) != 0)
5094       SignalExceptionAddressStore();
5095     else
5096       {
5097         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5098           {
5099             uword64 memval = 0;
5100             uword64 memval1 = 0;
5101             uword64 mask = 0x7;
5102             unsigned int byte;
5103             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5104             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5105             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5106             {
5107               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5108             }
5109           }
5110       }
5111   }
5112 }
5113
5114
5115 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5116 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5117 *mipsIV:
5118 *vr5000:
5119 // start-sanitize-vr4320
5120 *vr4320:
5121 // end-sanitize-vr4320
5122 // start-sanitize-vr5400
5123 *vr5400:
5124 // end-sanitize-vr5400
5125 {
5126   unsigned32 instruction = instruction_0;
5127   int fs = ((instruction >> 11) & 0x0000001F);
5128   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5129   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5130   {
5131    address_word vaddr = ((unsigned64)op1 + op2);
5132    address_word paddr;
5133    int uncached;
5134    if ((vaddr & 3) != 0)
5135     SignalExceptionAddressStore();
5136    else
5137    {
5138     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5139     {
5140      unsigned64 memval = 0;
5141      unsigned64 memval1 = 0;
5142      unsigned64 mask = 0x7;
5143      unsigned int byte;
5144      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5145      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5146      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5147       {
5148        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5149       }
5150     }
5151    }
5152   }
5153 }
5154
5155
5156 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5157 "trunc.l.%s<FMT> f<FD>, f<FS>"
5158 *mipsIII:
5159 *mipsIV:
5160 *vr5000:
5161 // start-sanitize-vr4320
5162 *vr4320:
5163 // end-sanitize-vr4320
5164 // start-sanitize-vr5400
5165 *vr5400:
5166 // end-sanitize-vr5400
5167 // start-sanitize-r5900
5168 *r5900:
5169 // end-sanitize-r5900
5170 *r3900:
5171 // start-sanitize-tx19
5172 *tx19:
5173 // end-sanitize-tx19
5174 {
5175   unsigned32 instruction = instruction_0;
5176   int destreg = ((instruction >> 6) & 0x0000001F);
5177   int fs = ((instruction >> 11) & 0x0000001F);
5178   int format = ((instruction >> 21) & 0x00000007);
5179   {
5180   if ((format != fmt_single) && (format != fmt_double))
5181    SignalException(ReservedInstruction,instruction);
5182   else
5183    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5184   }
5185 }
5186
5187
5188 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5189 "trunc.w.%s<FMT> f<FD>, f<FS>"
5190 *mipsII:
5191 *mipsIII:
5192 *mipsIV:
5193 *vr5000:
5194 // start-sanitize-vr4320
5195 *vr4320:
5196 // end-sanitize-vr4320
5197 // start-sanitize-vr5400
5198 *vr5400:
5199 // end-sanitize-vr5400
5200 // start-sanitize-r5900
5201 *r5900:
5202 // end-sanitize-r5900
5203 *r3900:
5204 // start-sanitize-tx19
5205 *tx19:
5206 // end-sanitize-tx19
5207 {
5208   unsigned32 instruction = instruction_0;
5209   int destreg = ((instruction >> 6) & 0x0000001F);
5210   int fs = ((instruction >> 11) & 0x0000001F);
5211   int format = ((instruction >> 21) & 0x00000007);
5212   {
5213   if ((format != fmt_single) && (format != fmt_double))
5214    SignalException(ReservedInstruction,instruction);
5215   else
5216    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5217   }
5218 }
5219
5220 \f
5221 //
5222 // MIPS Architecture:
5223 //
5224 //        System Control Instruction Set (COP0)
5225 //
5226
5227
5228 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5229 "bc0f <OFFSET>"
5230 *mipsI,mipsII,mipsIII,mipsIV:
5231 *vr5000:
5232 // start-sanitize-vr4320
5233 *vr4320:
5234 // end-sanitize-vr4320
5235 // start-sanitize-vr5400
5236 *vr5400:
5237 // end-sanitize-vr5400
5238 // start-sanitize-r5900
5239 *r5900:
5240 // end-sanitize-r5900
5241
5242
5243 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5244 "bc0fl <OFFSET>"
5245 *mipsI,mipsII,mipsIII,mipsIV:
5246 *vr5000:
5247 // start-sanitize-vr4320
5248 *vr4320:
5249 // end-sanitize-vr4320
5250 // start-sanitize-vr5400
5251 *vr5400:
5252 // end-sanitize-vr5400
5253 // start-sanitize-r5900
5254 *r5900:
5255 // end-sanitize-r5900
5256
5257
5258 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5259 "bc0t <OFFSET>"
5260 *mipsI,mipsII,mipsIII,mipsIV:
5261 // start-sanitize-r5900
5262 *r5900:
5263 // end-sanitize-r5900
5264
5265
5266
5267 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5268 "bc0tl <OFFSET>"
5269 *mipsI,mipsII,mipsIII,mipsIV:
5270 *vr5000:
5271 // start-sanitize-vr4320
5272 *vr4320:
5273 // end-sanitize-vr4320
5274 // start-sanitize-vr5400
5275 *vr5400:
5276 // end-sanitize-vr5400
5277 // start-sanitize-r5900
5278 *r5900:
5279 // end-sanitize-r5900
5280
5281
5282 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5283 *mipsIII:
5284 *mipsIV:
5285 *vr5000:
5286 // start-sanitize-vr4320
5287 *vr4320:
5288 // end-sanitize-vr4320
5289 // start-sanitize-vr5400
5290 *vr5400:
5291 // end-sanitize-vr5400
5292 // start-sanitize-r5900
5293 *r5900:
5294 // end-sanitize-r5900
5295 *r3900:
5296 // start-sanitize-tx19
5297 *tx19:
5298 // end-sanitize-tx19
5299 {
5300   unsigned32 instruction = instruction_0;
5301   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5302   int hint = ((instruction >> 16) & 0x0000001F);
5303   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5304   {
5305     address_word vaddr = (op1 + offset);
5306     address_word paddr;
5307     int uncached;
5308     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5309       CacheOp(hint,vaddr,paddr,instruction);
5310   }
5311 }
5312
5313
5314 010000,10000,000000000000000,111001:COP0:32::DI
5315 "di"
5316 *mipsI,mipsII,mipsIII,mipsIV:
5317 *vr5000:
5318 // start-sanitize-vr4320
5319 *vr4320:
5320 // end-sanitize-vr4320
5321 // start-sanitize-vr5400
5322 *vr5400:
5323 // end-sanitize-vr5400
5324 // start-sanitize-r5900
5325 *r5900:
5326 // end-sanitize-r5900
5327
5328
5329 010000,10000,000000000000000,111000:COP0:32::EI
5330 "ei"
5331 *mipsI,mipsII,mipsIII,mipsIV:
5332 *vr5000:
5333 // start-sanitize-vr4320
5334 *vr4320:
5335 // end-sanitize-vr4320
5336 // start-sanitize-vr5400
5337 *vr5400:
5338 // end-sanitize-vr5400
5339 // start-sanitize-r5900
5340 *r5900:
5341 // end-sanitize-r5900
5342
5343
5344 010000,10000,000000000000000,011000:COP0:32::ERET
5345 "eret"
5346 *mipsIII:
5347 *mipsIV:
5348 *vr5000:
5349 // start-sanitize-vr4320
5350 *vr4320:
5351 // end-sanitize-vr4320
5352 // start-sanitize-vr5400
5353 *vr5400:
5354 // end-sanitize-vr5400
5355 // start-sanitize-r5900
5356 *r5900:
5357 // end-sanitize-r5900
5358 {
5359   if (SR & status_ERL)
5360     {
5361       /* Oops, not yet available */
5362       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5363       NIA = EPC;
5364       SR &= ~status_ERL;
5365     }
5366   else
5367     {
5368       NIA = EPC;
5369       SR &= ~status_EXL;
5370     }
5371 }
5372
5373
5374 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5375 "mfc0 r<RT>, r<RD> # <REGX>"
5376 *mipsI,mipsII,mipsIII,mipsIV:
5377 *r3900:
5378 *vr5000:
5379 // start-sanitize-vr4320
5380 *vr4320:
5381 // end-sanitize-vr4320
5382 // start-sanitize-vr5400
5383 *vr5400:
5384 // end-sanitize-vr5400
5385 // start-sanitize-r5900
5386 *r5900:
5387 // end-sanitize-r5900
5388 {
5389   TRACE_ALU_INPUT0 ();
5390   DecodeCoproc (instruction_0);
5391   TRACE_ALU_RESULT (GPR[RT]);
5392 }
5393
5394 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5395 "mtc0 r<RT>, r<RD> # <REGX>"
5396 *mipsI,mipsII,mipsIII,mipsIV:
5397 // start-sanitize-tx19
5398 *tx19:
5399 // end-sanitize-tx19
5400 *r3900:
5401 // start-sanitize-vr4320
5402 *vr4320:
5403 // end-sanitize-vr4320
5404 *vr5000:
5405 // start-sanitize-vr5400
5406 *vr5400:
5407 // end-sanitize-vr5400
5408 // start-sanitize-r5900
5409 *r5900:
5410 // end-sanitize-r5900
5411 {
5412   DecodeCoproc (instruction_0);
5413 }
5414
5415
5416 010000,10000,000000000000000,010000:COP0:32::RFE
5417 "rfe"
5418 *mipsI,mipsII,mipsIII,mipsIV:
5419 // start-sanitize-tx19
5420 *tx19:
5421 // end-sanitize-tx19
5422 *r3900:
5423 // start-sanitize-vr4320
5424 *vr4320:
5425 // end-sanitize-vr4320
5426 *vr5000:
5427 // start-sanitize-vr5400
5428 *vr5400:
5429 // end-sanitize-vr5400
5430 // start-sanitize-r5900
5431 *r5900:
5432 // end-sanitize-r5900
5433 {
5434   DecodeCoproc (instruction_0);
5435 }
5436
5437
5438 010000,10000,000000000000000,001000:COP0:32::TLBP
5439 "tlbp"
5440 *mipsI,mipsII,mipsIII,mipsIV:
5441 *vr5000:
5442 // start-sanitize-vr4320
5443 *vr4320:
5444 // end-sanitize-vr4320
5445 // start-sanitize-vr5400
5446 *vr5400:
5447 // end-sanitize-vr5400
5448 // start-sanitize-r5900
5449 *r5900:
5450 // end-sanitize-r5900
5451
5452
5453 010000,10000,000000000000000,000001:COP0:32::TLBR
5454 "tlbr"
5455 *mipsI,mipsII,mipsIII,mipsIV:
5456 *vr5000:
5457 // start-sanitize-vr4320
5458 *vr4320:
5459 // end-sanitize-vr4320
5460 // start-sanitize-vr5400
5461 *vr5400:
5462 // end-sanitize-vr5400
5463 // start-sanitize-r5900
5464 *r5900:
5465 // end-sanitize-r5900
5466
5467
5468 010000,10000,000000000000000,000010:COP0:32::TLBWI
5469 "tlbwi"
5470 *mipsI,mipsII,mipsIII,mipsIV:
5471 *vr5000:
5472 // start-sanitize-vr4320
5473 *vr4320:
5474 // end-sanitize-vr4320
5475 // start-sanitize-vr5400
5476 *vr5400:
5477 // end-sanitize-vr5400
5478 // start-sanitize-r5900
5479 *r5900:
5480 // end-sanitize-r5900
5481
5482
5483 010000,10000,000000000000000,000110:COP0:32::TLBWR
5484 "tlbwr"
5485 *mipsI,mipsII,mipsIII,mipsIV:
5486 *vr5000:
5487 // start-sanitize-vr4320
5488 *vr4320:
5489 // end-sanitize-vr4320
5490 // start-sanitize-vr5400
5491 *vr5400:
5492 // end-sanitize-vr5400
5493 // start-sanitize-r5900
5494 *r5900:
5495 // end-sanitize-r5900
5496
5497 \f
5498 :include:::m16.igen
5499 // start-sanitize-vr4320
5500 :include::vr4320:vr4320.igen
5501 // end-sanitize-vr4320
5502 // start-sanitize-vr5400
5503 :include::vr5400:vr5400.igen
5504 :include:64,f::mdmx.igen
5505 // end-sanitize-vr5400
5506 // start-sanitize-r5900
5507 :include::r5900:r5900.igen
5508 // end-sanitize-r5900
5509 :include:::tx.igen
5510 \f
5511 // start-sanitize-cygnus-never
5512
5513 // // FIXME FIXME FIXME What is this instruction?
5514 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5515 // *mipsI:
5516 // *mipsII:
5517 // *mipsIII:
5518 // *mipsIV:
5519 // // start-sanitize-r5900
5520 // *r5900:
5521 // // end-sanitize-r5900
5522 // *r3900:
5523 // // start-sanitize-tx19
5524 // *tx19:
5525 // // end-sanitize-tx19
5526 // {
5527 //   unsigned32 instruction = instruction_0;
5528 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5529 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5530 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5531 //   {
5532 //     if (CoProcPresent(3))
5533 //       SignalException(CoProcessorUnusable);
5534 //     else
5535 //       SignalException(ReservedInstruction,instruction);
5536 //   }
5537 // }
5538
5539 // end-sanitize-cygnus-never
5540 // start-sanitize-cygnus-never
5541
5542 // // FIXME FIXME FIXME What is this?
5543 // 11100,******,00001:RR:16::SDBBP
5544 // *mips16:
5545 // {
5546 //   unsigned32 instruction = instruction_0;
5547 //   if (have_extendval)
5548 //     SignalException (ReservedInstruction, instruction);
5549 //   {
5550 //     SignalException(DebugBreakPoint,instruction);
5551 //   }
5552 // }
5553
5554 // end-sanitize-cygnus-never
5555 // start-sanitize-cygnus-never
5556
5557 // // FIXME FIXME FIXME What is this?
5558 // 000000,********************,001110:SPECIAL:32::SDBBP
5559 // *r3900:
5560 // {
5561 //   unsigned32 instruction = instruction_0;
5562 //   {
5563 //     SignalException(DebugBreakPoint,instruction);
5564 //   }
5565 // }
5566
5567 // end-sanitize-cygnus-never
5568 // start-sanitize-cygnus-never
5569
5570 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5571 // // isn't yet reconized by this simulator.
5572 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5573 // *vr4100:
5574 // {
5575 //   unsigned32 instruction = instruction_0;
5576 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5577 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5578 //   {
5579 //     CHECKHILO("Multiply-Add");
5580 //     {
5581 //       unsigned64 temp = (op1 * op2);
5582 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5583 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5584 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5585 //     }
5586 //   }
5587 // }
5588
5589 // end-sanitize-cygnus-never
5590 // start-sanitize-cygnus-never
5591
5592 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5593 // // isn't yet reconized by this simulator.
5594 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5595 // *vr4100:
5596 // {
5597 //   unsigned32 instruction = instruction_0;
5598 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5599 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5600 //   {
5601 //     CHECKHILO("Multiply-Add");
5602 //     {
5603 //       unsigned64 temp = (op1 * op2);
5604 //       LO = LO + temp;
5605 //     }
5606 //   }
5607 // }
5608
5609 // end-sanitize-cygnus-never