sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips64:mipsisa64:
  49
  50 //  Vendor ISAs:
  51 //
  52 //  Standard MIPS ISA instructions used for these models are listed here,
  53 //  as are functions needed by those standard instructions.  Instructions
  54 //  which are model-dependent and which are not in the standard MIPS ISAs
  55 //  (or which pre-date or use different encodings than the standard
  56 //  instructions) are (for the most part) in separate .igen files.
  57 :model:::vr4100:mips4100:               // vr.igen
  58 :model:::vr5000:mips5000:
  59 :model:::r3900:mips3900:                // tx.igen
  60
  61 //  MIPS Application Specific Extensions (ASEs)
  62 //
  63 //  Instructions for the ASEs are in separate .igen files.
  64 //  ASEs add instructions on to a base ISA.
  65 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  66 :model:::mdmx:mdmx:                     // mdmx.igen
  67
  68 //  Vendor Extensions
  69 //
  70 //  Instructions specific to these extensions are in separate .igen files.
  71 //  Extensions add instructions on to a base ISA.
  72 :model:::sb1:sb1:                       // sb1.igen
  73
  74
  75 // Pseudo instructions known by IGEN
  76 :internal::::illegal:
  77 {
  78   SignalException (ReservedInstruction, 0);
  79 }
  80
  81
  82 // Pseudo instructions known by interp.c
  83 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  84 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  85 "rsvd <OP>"
  86 {
  87   SignalException (ReservedInstruction, instruction_0);
  88 }
  89
  90
  91
  92 // Helper:
  93 //
  94 // Simulate a 32 bit delayslot instruction
  95 //
  96
  97 :function:::address_word:delayslot32:address_word target
  98 {
  99   instruction_word delay_insn;
 100   sim_events_slip (SD, 1);
 101   DSPC = CIA;
 102   CIA = CIA + 4; /* NOTE not mips16 */
 103   STATE |= simDELAYSLOT;
 104   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 105   ENGINE_ISSUE_PREFIX_HOOK();
 106   idecode_issue (CPU_, delay_insn, (CIA));
 107   STATE &= ~simDELAYSLOT;
 108   return target;
 109 }
 110
 111 :function:::address_word:nullify_next_insn32:
 112 {
 113   sim_events_slip (SD, 1);
 114   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 115   return CIA + 8;
 116 }
 117
 118
 119 // Helper:
 120 //
 121 // Calculate an effective address given a base and an offset.
 122 //
 123
 124 :function:::address_word:loadstore_ea:address_word base, address_word offset
 125 *mipsI:
 126 *mipsII:
 127 *mipsIII:
 128 *mipsIV:
 129 *mipsV:
 130 *mips32:
 131 *vr4100:
 132 *vr5000:
 133 *r3900:
 134 {
 135   return base + offset;
 136 }
 137
 138 :function:::address_word:loadstore_ea:address_word base, address_word offset
 139 *mips64:
 140 {
 141 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 142   /* If in user mode and UX is not set, use 32-bit compatibility effective
 143      address computations as defined in the MIPS64 Architecture for
 144      Programmers Volume III, Revision 0.95, section 4.9.  */
 145   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 146       == (ksu_user << status_KSU_shift))
 147     return (address_word)((signed32)base + (signed32)offset);
 148 #endif
 149   return base + offset;
 150 }
 151
 152
 153 // Helper:
 154 //
 155 // Check that a 32-bit register value is properly sign-extended.
 156 // (See NotWordValue in ISA spec.)
 157 //
 158
 159 :function:::int:not_word_value:unsigned_word value
 160 *mipsI:
 161 *mipsII:
 162 *mipsIII:
 163 *mipsIV:
 164 *mipsV:
 165 *vr4100:
 166 *vr5000:
 167 *r3900:
 168 {
 169   /* For historical simulator compatibility (until documentation is
 170      found that makes these operations unpredictable on some of these
 171      architectures), this check never returns true.  */
 172   return 0;
 173 }
 174
 175 :function:::int:not_word_value:unsigned_word value
 176 *mips32:
 177 {
 178   /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
 179   return 0;
 180 }
 181
 182 :function:::int:not_word_value:unsigned_word value
 183 *mips64:
 184 {
 185   return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
 186 }
 187
 188
 189 // Helper:
 190 //
 191 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 192 // theoretically portable code which invokes non-portable behaviour from
 193 // running with no indication of the portability issue.
 194 // (See definition of UNPREDICTABLE in ISA spec.)
 195 //
 196
 197 :function:::void:unpredictable:
 198 *mipsI:
 199 *mipsII:
 200 *mipsIII:
 201 *mipsIV:
 202 *mipsV:
 203 *vr4100:
 204 *vr5000:
 205 *r3900:
 206 {
 207 }
 208
 209 :function:::void:unpredictable:
 210 *mips32:
 211 *mips64:
 212 {
 213   unpredictable_action (CPU, CIA);
 214 }
 215
 216
 217 // Helper:
 218 //
 219 // Check that an access to a HI/LO register meets timing requirements
 220 //
 221 // The following requirements exist:
 222 //
 223 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 224 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 225 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 226 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 227 //
 228
 229 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 230 {
 231   if (history->mf.timestamp + 3 > time)
 232     {
 233       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 234                         itable[MY_INDEX].name,
 235                         new, (long) CIA,
 236                         (long) history->mf.cia);
 237       return 0;
 238     }
 239   return 1;
 240 }
 241
 242 :function:::int:check_mt_hilo:hilo_history *history
 243 *mipsI:
 244 *mipsII:
 245 *mipsIII:
 246 *mipsIV:
 247 *mipsV:
 248 *vr4100:
 249 *vr5000:
 250 {
 251   signed64 time = sim_events_time (SD);
 252   int ok = check_mf_cycles (SD_, history, time, "MT");
 253   history->mt.timestamp = time;
 254   history->mt.cia = CIA;
 255   return ok;
 256 }
 257
 258 :function:::int:check_mt_hilo:hilo_history *history
 259 *mips32:
 260 *mips64:
 261 *r3900:
 262 {
 263   signed64 time = sim_events_time (SD);
 264   history->mt.timestamp = time;
 265   history->mt.cia = CIA;
 266   return 1;
 267 }
 268
 269
 270 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 271 *mipsI:
 272 *mipsII:
 273 *mipsIII:
 274 *mipsIV:
 275 *mipsV:
 276 *mips32:
 277 *mips64:
 278 *vr4100:
 279 *vr5000:
 280 *r3900:
 281 {
 282   signed64 time = sim_events_time (SD);
 283   int ok = 1;
 284   if (peer != NULL
 285       && peer->mt.timestamp > history->op.timestamp
 286       && history->mt.timestamp < history->op.timestamp
 287       && ! (history->mf.timestamp > history->op.timestamp
 288             && history->mf.timestamp < peer->mt.timestamp)
 289       && ! (peer->mf.timestamp > history->op.timestamp
 290             && peer->mf.timestamp < peer->mt.timestamp))
 291     {
 292       /* The peer has been written to since the last OP yet we have
 293          not */
 294       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 295                         itable[MY_INDEX].name,
 296                         (long) CIA,
 297                         (long) history->op.cia,
 298                         (long) peer->mt.cia);
 299       ok = 0;
 300     }
 301   history->mf.timestamp = time;
 302   history->mf.cia = CIA;
 303   return ok;
 304 }
 305
 306
 307
 308 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 309 *mipsI:
 310 *mipsII:
 311 *mipsIII:
 312 *mipsIV:
 313 *mipsV:
 314 *vr4100:
 315 *vr5000:
 316 {
 317   signed64 time = sim_events_time (SD);
 318   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 319             && check_mf_cycles (SD_, lo, time, "OP"));
 320   hi->op.timestamp = time;
 321   lo->op.timestamp = time;
 322   hi->op.cia = CIA;
 323   lo->op.cia = CIA;
 324   return ok;
 325 }
 326
 327 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 328 // a mf{hi,lo}
 329 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 330 *mips32:
 331 *mips64:
 332 *r3900:
 333 {
 334   /* FIXME: could record the fact that a stall occured if we want */
 335   signed64 time = sim_events_time (SD);
 336   hi->op.timestamp = time;
 337   lo->op.timestamp = time;
 338   hi->op.cia = CIA;
 339   lo->op.cia = CIA;
 340   return 1;
 341 }
 342
 343
 344 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 345 *mipsI:
 346 *mipsII:
 347 *mipsIII:
 348 *mipsIV:
 349 *mipsV:
 350 *mips32:
 351 *mips64:
 352 *vr4100:
 353 *vr5000:
 354 *r3900:
 355 {
 356   signed64 time = sim_events_time (SD);
 357   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 358             && check_mf_cycles (SD_, lo, time, "OP"));
 359   hi->op.timestamp = time;
 360   lo->op.timestamp = time;
 361   hi->op.cia = CIA;
 362   lo->op.cia = CIA;
 363   return ok;
 364 }
 365
 366
 367 // Helper:
 368 //
 369 // Check that the 64-bit instruction can currently be used, and signal
 370 // a ReservedInstruction exception if not.
 371 //
 372
 373 :function:::void:check_u64:instruction_word insn
 374 *mipsIII:
 375 *mipsIV:
 376 *mipsV:
 377 *vr4100:
 378 *vr5000:
 379 {
 380   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 381 }
 382
 383 :function:::void:check_u64:instruction_word insn
 384 *mips64:
 385 {
 386 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 387   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 388     SignalException (ReservedInstruction, insn);
 389 #endif
 390 }
 391
 392
 393
 394 //
 395 // MIPS Architecture:
 396 //
 397 //        CPU Instruction Set (mipsI - mipsV, mips32, mips64)
 398 //
 399
 400
 401
 402 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 403 "add r<RD>, r<RS>, r<RT>"
 404 *mipsI:
 405 *mipsII:
 406 *mipsIII:
 407 *mipsIV:
 408 *mipsV:
 409 *mips32:
 410 *mips64:
 411 *vr4100:
 412 *vr5000:
 413 *r3900:
 414 {
 415   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 416     Unpredictable ();
 417   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 418   {
 419     ALU32_BEGIN (GPR[RS]);
 420     ALU32_ADD (GPR[RT]);
 421     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 422   }
 423   TRACE_ALU_RESULT (GPR[RD]);
 424 }
 425
 426
 427
 428 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 429 "addi r<RT>, r<RS>, <IMMEDIATE>"
 430 *mipsI:
 431 *mipsII:
 432 *mipsIII:
 433 *mipsIV:
 434 *mipsV:
 435 *mips32:
 436 *mips64:
 437 *vr4100:
 438 *vr5000:
 439 *r3900:
 440 {
 441   if (NotWordValue (GPR[RS]))
 442     Unpredictable ();
 443   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 444   {
 445     ALU32_BEGIN (GPR[RS]);
 446     ALU32_ADD (EXTEND16 (IMMEDIATE));
 447     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 448   }
 449   TRACE_ALU_RESULT (GPR[RT]);
 450 }
 451
 452
 453
 454 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 455 {
 456   if (NotWordValue (GPR[rs]))
 457     Unpredictable ();
 458   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 459   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 460   TRACE_ALU_RESULT (GPR[rt]);
 461 }
 462
 463 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 464 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 465 *mipsI:
 466 *mipsII:
 467 *mipsIII:
 468 *mipsIV:
 469 *mipsV:
 470 *mips32:
 471 *mips64:
 472 *vr4100:
 473 *vr5000:
 474 *r3900:
 475 {
 476   do_addiu (SD_, RS, RT, IMMEDIATE);
 477 }
 478
 479
 480
 481 :function:::void:do_addu:int rs, int rt, int rd
 482 {
 483   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 484     Unpredictable ();
 485   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 486   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 487   TRACE_ALU_RESULT (GPR[rd]);
 488 }
 489
 490 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 491 "addu r<RD>, r<RS>, r<RT>"
 492 *mipsI:
 493 *mipsII:
 494 *mipsIII:
 495 *mipsIV:
 496 *mipsV:
 497 *mips32:
 498 *mips64:
 499 *vr4100:
 500 *vr5000:
 501 *r3900:
 502 {
 503   do_addu (SD_, RS, RT, RD);
 504 }
 505
 506
 507
 508 :function:::void:do_and:int rs, int rt, int rd
 509 {
 510   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 511   GPR[rd] = GPR[rs] & GPR[rt];
 512   TRACE_ALU_RESULT (GPR[rd]);
 513 }
 514
 515 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 516 "and r<RD>, r<RS>, r<RT>"
 517 *mipsI:
 518 *mipsII:
 519 *mipsIII:
 520 *mipsIV:
 521 *mipsV:
 522 *mips32:
 523 *mips64:
 524 *vr4100:
 525 *vr5000:
 526 *r3900:
 527 {
 528   do_and (SD_, RS, RT, RD);
 529 }
 530
 531
 532
 533 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 534 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 535 *mipsI:
 536 *mipsII:
 537 *mipsIII:
 538 *mipsIV:
 539 *mipsV:
 540 *mips32:
 541 *mips64:
 542 *vr4100:
 543 *vr5000:
 544 *r3900:
 545 {
 546   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 547   GPR[RT] = GPR[RS] & IMMEDIATE;
 548   TRACE_ALU_RESULT (GPR[RT]);
 549 }
 550
 551
 552
 553 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 554 "beq r<RS>, r<RT>, <OFFSET>"
 555 *mipsI:
 556 *mipsII:
 557 *mipsIII:
 558 *mipsIV:
 559 *mipsV:
 560 *mips32:
 561 *mips64:
 562 *vr4100:
 563 *vr5000:
 564 *r3900:
 565 {
 566   address_word offset = EXTEND16 (OFFSET) << 2;
 567   check_branch_bug ();
 568   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 569     {
 570       mark_branch_bug (NIA+offset);
 571       DELAY_SLOT (NIA + offset);
 572     }
 573 }
 574
 575
 576
 577 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 578 "beql r<RS>, r<RT>, <OFFSET>"
 579 *mipsII:
 580 *mipsIII:
 581 *mipsIV:
 582 *mipsV:
 583 *mips32:
 584 *mips64:
 585 *vr4100:
 586 *vr5000:
 587 *r3900:
 588 {
 589   address_word offset = EXTEND16 (OFFSET) << 2;
 590   check_branch_bug ();
 591   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 592     {
 593       mark_branch_bug (NIA+offset);
 594       DELAY_SLOT (NIA + offset);
 595     }
 596   else
 597     NULLIFY_NEXT_INSTRUCTION ();
 598 }
 599
 600
 601
 602 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 603 "bgez r<RS>, <OFFSET>"
 604 *mipsI:
 605 *mipsII:
 606 *mipsIII:
 607 *mipsIV:
 608 *mipsV:
 609 *mips32:
 610 *mips64:
 611 *vr4100:
 612 *vr5000:
 613 *r3900:
 614 {
 615   address_word offset = EXTEND16 (OFFSET) << 2;
 616   check_branch_bug ();
 617   if ((signed_word) GPR[RS] >= 0)
 618     {
 619       mark_branch_bug (NIA+offset);
 620       DELAY_SLOT (NIA + offset);
 621     }
 622 }
 623
 624
 625
 626 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 627 "bgezal r<RS>, <OFFSET>"
 628 *mipsI:
 629 *mipsII:
 630 *mipsIII:
 631 *mipsIV:
 632 *mipsV:
 633 *mips32:
 634 *mips64:
 635 *vr4100:
 636 *vr5000:
 637 *r3900:
 638 {
 639   address_word offset = EXTEND16 (OFFSET) << 2;
 640   check_branch_bug ();
 641   if (RS == 31)
 642     Unpredictable ();
 643   RA = (CIA + 8);
 644   if ((signed_word) GPR[RS] >= 0)
 645     {
 646       mark_branch_bug (NIA+offset);
 647       DELAY_SLOT (NIA + offset);
 648     }
 649 }
 650
 651
 652
 653 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 654 "bgezall r<RS>, <OFFSET>"
 655 *mipsII:
 656 *mipsIII:
 657 *mipsIV:
 658 *mipsV:
 659 *mips32:
 660 *mips64:
 661 *vr4100:
 662 *vr5000:
 663 *r3900:
 664 {
 665   address_word offset = EXTEND16 (OFFSET) << 2;
 666   check_branch_bug ();
 667   if (RS == 31)
 668     Unpredictable ();
 669   RA = (CIA + 8);
 670   /* NOTE: The branch occurs AFTER the next instruction has been
 671      executed */
 672   if ((signed_word) GPR[RS] >= 0)
 673     {
 674       mark_branch_bug (NIA+offset);
 675       DELAY_SLOT (NIA + offset);
 676     }
 677   else
 678     NULLIFY_NEXT_INSTRUCTION ();
 679 }
 680
 681
 682
 683 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 684 "bgezl r<RS>, <OFFSET>"
 685 *mipsII:
 686 *mipsIII:
 687 *mipsIV:
 688 *mipsV:
 689 *mips32:
 690 *mips64:
 691 *vr4100:
 692 *vr5000:
 693 *r3900:
 694 {
 695   address_word offset = EXTEND16 (OFFSET) << 2;
 696   check_branch_bug ();
 697   if ((signed_word) GPR[RS] >= 0)
 698     {
 699       mark_branch_bug (NIA+offset);
 700       DELAY_SLOT (NIA + offset);
 701     }
 702   else
 703     NULLIFY_NEXT_INSTRUCTION ();
 704 }
 705
 706
 707
 708 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 709 "bgtz r<RS>, <OFFSET>"
 710 *mipsI:
 711 *mipsII:
 712 *mipsIII:
 713 *mipsIV:
 714 *mipsV:
 715 *mips32:
 716 *mips64:
 717 *vr4100:
 718 *vr5000:
 719 *r3900:
 720 {
 721   address_word offset = EXTEND16 (OFFSET) << 2;
 722   check_branch_bug ();
 723   if ((signed_word) GPR[RS] > 0)
 724     {
 725       mark_branch_bug (NIA+offset);
 726       DELAY_SLOT (NIA + offset);
 727     }
 728 }
 729
 730
 731
 732 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 733 "bgtzl r<RS>, <OFFSET>"
 734 *mipsII:
 735 *mipsIII:
 736 *mipsIV:
 737 *mipsV:
 738 *mips32:
 739 *mips64:
 740 *vr4100:
 741 *vr5000:
 742 *r3900:
 743 {
 744   address_word offset = EXTEND16 (OFFSET) << 2;
 745   check_branch_bug ();
 746   /* NOTE: The branch occurs AFTER the next instruction has been
 747      executed */
 748   if ((signed_word) GPR[RS] > 0)
 749     {
 750       mark_branch_bug (NIA+offset);
 751       DELAY_SLOT (NIA + offset);
 752     }
 753   else
 754     NULLIFY_NEXT_INSTRUCTION ();
 755 }
 756
 757
 758
 759 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 760 "blez r<RS>, <OFFSET>"
 761 *mipsI:
 762 *mipsII:
 763 *mipsIII:
 764 *mipsIV:
 765 *mipsV:
 766 *mips32:
 767 *mips64:
 768 *vr4100:
 769 *vr5000:
 770 *r3900:
 771 {
 772   address_word offset = EXTEND16 (OFFSET) << 2;
 773   check_branch_bug ();
 774   /* NOTE: The branch occurs AFTER the next instruction has been
 775      executed */
 776   if ((signed_word) GPR[RS] <= 0)
 777     {
 778       mark_branch_bug (NIA+offset);
 779       DELAY_SLOT (NIA + offset);
 780     }
 781 }
 782
 783
 784
 785 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 786 "bgezl r<RS>, <OFFSET>"
 787 *mipsII:
 788 *mipsIII:
 789 *mipsIV:
 790 *mipsV:
 791 *mips32:
 792 *mips64:
 793 *vr4100:
 794 *vr5000:
 795 *r3900:
 796 {
 797   address_word offset = EXTEND16 (OFFSET) << 2;
 798   check_branch_bug ();
 799   if ((signed_word) GPR[RS] <= 0)
 800     {
 801       mark_branch_bug (NIA+offset);
 802       DELAY_SLOT (NIA + offset);
 803     }
 804   else
 805     NULLIFY_NEXT_INSTRUCTION ();
 806 }
 807
 808
 809
 810 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 811 "bltz r<RS>, <OFFSET>"
 812 *mipsI:
 813 *mipsII:
 814 *mipsIII:
 815 *mipsIV:
 816 *mipsV:
 817 *mips32:
 818 *mips64:
 819 *vr4100:
 820 *vr5000:
 821 *r3900:
 822 {
 823   address_word offset = EXTEND16 (OFFSET) << 2;
 824   check_branch_bug ();
 825   if ((signed_word) GPR[RS] < 0)
 826     {
 827       mark_branch_bug (NIA+offset);
 828       DELAY_SLOT (NIA + offset);
 829     }
 830 }
 831
 832
 833
 834 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 835 "bltzal r<RS>, <OFFSET>"
 836 *mipsI:
 837 *mipsII:
 838 *mipsIII:
 839 *mipsIV:
 840 *mipsV:
 841 *mips32:
 842 *mips64:
 843 *vr4100:
 844 *vr5000:
 845 *r3900:
 846 {
 847   address_word offset = EXTEND16 (OFFSET) << 2;
 848   check_branch_bug ();
 849   if (RS == 31)
 850     Unpredictable ();
 851   RA = (CIA + 8);
 852   /* NOTE: The branch occurs AFTER the next instruction has been
 853      executed */
 854   if ((signed_word) GPR[RS] < 0)
 855     {
 856       mark_branch_bug (NIA+offset);
 857       DELAY_SLOT (NIA + offset);
 858     }
 859 }
 860
 861
 862
 863 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 864 "bltzall r<RS>, <OFFSET>"
 865 *mipsII:
 866 *mipsIII:
 867 *mipsIV:
 868 *mipsV:
 869 *mips32:
 870 *mips64:
 871 *vr4100:
 872 *vr5000:
 873 *r3900:
 874 {
 875   address_word offset = EXTEND16 (OFFSET) << 2;
 876   check_branch_bug ();
 877   if (RS == 31)
 878     Unpredictable ();
 879   RA = (CIA + 8);
 880   if ((signed_word) GPR[RS] < 0)
 881     {
 882       mark_branch_bug (NIA+offset);
 883       DELAY_SLOT (NIA + offset);
 884     }
 885   else
 886     NULLIFY_NEXT_INSTRUCTION ();
 887 }
 888
 889
 890
 891 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 892 "bltzl r<RS>, <OFFSET>"
 893 *mipsII:
 894 *mipsIII:
 895 *mipsIV:
 896 *mipsV:
 897 *mips32:
 898 *mips64:
 899 *vr4100:
 900 *vr5000:
 901 *r3900:
 902 {
 903   address_word offset = EXTEND16 (OFFSET) << 2;
 904   check_branch_bug ();
 905   /* NOTE: The branch occurs AFTER the next instruction has been
 906      executed */
 907   if ((signed_word) GPR[RS] < 0)
 908     {
 909       mark_branch_bug (NIA+offset);
 910       DELAY_SLOT (NIA + offset);
 911     }
 912   else
 913     NULLIFY_NEXT_INSTRUCTION ();
 914 }
 915
 916
 917
 918 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 919 "bne r<RS>, r<RT>, <OFFSET>"
 920 *mipsI:
 921 *mipsII:
 922 *mipsIII:
 923 *mipsIV:
 924 *mipsV:
 925 *mips32:
 926 *mips64:
 927 *vr4100:
 928 *vr5000:
 929 *r3900:
 930 {
 931   address_word offset = EXTEND16 (OFFSET) << 2;
 932   check_branch_bug ();
 933   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 934     {
 935       mark_branch_bug (NIA+offset);
 936       DELAY_SLOT (NIA + offset);
 937     }
 938 }
 939
 940
 941
 942 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 943 "bnel r<RS>, r<RT>, <OFFSET>"
 944 *mipsII:
 945 *mipsIII:
 946 *mipsIV:
 947 *mipsV:
 948 *mips32:
 949 *mips64:
 950 *vr4100:
 951 *vr5000:
 952 *r3900:
 953 {
 954   address_word offset = EXTEND16 (OFFSET) << 2;
 955   check_branch_bug ();
 956   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 957     {
 958       mark_branch_bug (NIA+offset);
 959       DELAY_SLOT (NIA + offset);
 960     }
 961   else
 962     NULLIFY_NEXT_INSTRUCTION ();
 963 }
 964
 965
 966
 967 000000,20.CODE,001101:SPECIAL:32::BREAK
 968 "break %#lx<CODE>"
 969 *mipsI:
 970 *mipsII:
 971 *mipsIII:
 972 *mipsIV:
 973 *mipsV:
 974 *mips32:
 975 *mips64:
 976 *vr4100:
 977 *vr5000:
 978 *r3900:
 979 {
 980   /* Check for some break instruction which are reserved for use by the simulator.  */
 981   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 982   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 983       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 984     {
 985       sim_engine_halt (SD, CPU, NULL, cia,
 986                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 987     }
 988   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 989            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 990     {
 991       if (STATE & simDELAYSLOT)
 992         PC = cia - 4; /* reference the branch instruction */
 993       else
 994         PC = cia;
 995       SignalException (BreakPoint, instruction_0);
 996     }
 997
 998   else
 999     {
1000       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1001          the exception. */
1002       SignalException (BreakPoint, instruction_0);
1003     }
1004 }
1005
1006
1007
1008 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1009 "clo r<RD>, r<RS>"
1010 *mips32:
1011 *mips64:
1012 {
1013   unsigned32 temp = GPR[RS];
1014   unsigned32 i, mask;
1015   if (RT != RD)
1016     Unpredictable ();
1017   if (NotWordValue (GPR[RS]))
1018     Unpredictable ();
1019   TRACE_ALU_INPUT1 (GPR[RS]);
1020   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1021     {
1022       if ((temp & mask) == 0)
1023         break;
1024       mask >>= 1;
1025     }
1026   GPR[RD] = EXTEND32 (i);
1027   TRACE_ALU_RESULT (GPR[RD]);
1028 }
1029
1030
1031
1032 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1033 "clz r<RD>, r<RS>"
1034 *mips32:
1035 *mips64:
1036 {
1037   unsigned32 temp = GPR[RS];
1038   unsigned32 i, mask;
1039   if (RT != RD)
1040     Unpredictable ();
1041   if (NotWordValue (GPR[RS]))
1042     Unpredictable ();
1043   TRACE_ALU_INPUT1 (GPR[RS]);
1044   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1045     {
1046       if ((temp & mask) != 0)
1047         break;
1048       mask >>= 1;
1049     }
1050   GPR[RD] = EXTEND32 (i);
1051   TRACE_ALU_RESULT (GPR[RD]);
1052 }
1053
1054
1055
1056 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1057 "dadd r<RD>, r<RS>, r<RT>"
1058 *mipsIII:
1059 *mipsIV:
1060 *mipsV:
1061 *mips64:
1062 *vr4100:
1063 *vr5000:
1064 {
1065   check_u64 (SD_, instruction_0);
1066   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1067   {
1068     ALU64_BEGIN (GPR[RS]);
1069     ALU64_ADD (GPR[RT]);
1070     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1071   }
1072   TRACE_ALU_RESULT (GPR[RD]);
1073 }
1074
1075
1076
1077 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1078 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1079 *mipsIII:
1080 *mipsIV:
1081 *mipsV:
1082 *mips64:
1083 *vr4100:
1084 *vr5000:
1085 {
1086   check_u64 (SD_, instruction_0);
1087   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1088   {
1089     ALU64_BEGIN (GPR[RS]);
1090     ALU64_ADD (EXTEND16 (IMMEDIATE));
1091     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1092   }
1093   TRACE_ALU_RESULT (GPR[RT]);
1094 }
1095
1096
1097
1098 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1099 {
1100   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1101   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1102   TRACE_ALU_RESULT (GPR[rt]);
1103 }
1104
1105 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1106 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1107 *mipsIII:
1108 *mipsIV:
1109 *mipsV:
1110 *mips64:
1111 *vr4100:
1112 *vr5000:
1113 {
1114   check_u64 (SD_, instruction_0);
1115   do_daddiu (SD_, RS, RT, IMMEDIATE);
1116 }
1117
1118
1119
1120 :function:::void:do_daddu:int rs, int rt, int rd
1121 {
1122   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1123   GPR[rd] = GPR[rs] + GPR[rt];
1124   TRACE_ALU_RESULT (GPR[rd]);
1125 }
1126
1127 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1128 "daddu r<RD>, r<RS>, r<RT>"
1129 *mipsIII:
1130 *mipsIV:
1131 *mipsV:
1132 *mips64:
1133 *vr4100:
1134 *vr5000:
1135 {
1136   check_u64 (SD_, instruction_0);
1137   do_daddu (SD_, RS, RT, RD);
1138 }
1139
1140
1141
1142 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1143 "dclo r<RD>, r<RS>"
1144 *mips64:
1145 {
1146   unsigned64 temp = GPR[RS];
1147   unsigned32 i;
1148   unsigned64 mask;
1149   check_u64 (SD_, instruction_0);
1150   if (RT != RD)
1151     Unpredictable ();
1152   TRACE_ALU_INPUT1 (GPR[RS]);
1153   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1154     {
1155       if ((temp & mask) == 0)
1156         break;
1157       mask >>= 1;
1158     }
1159   GPR[RD] = EXTEND32 (i);
1160   TRACE_ALU_RESULT (GPR[RD]);
1161 }
1162
1163
1164
1165 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1166 "dclz r<RD>, r<RS>"
1167 *mips64:
1168 {
1169   unsigned64 temp = GPR[RS];
1170   unsigned32 i;
1171   unsigned64 mask;
1172   check_u64 (SD_, instruction_0);
1173   if (RT != RD)
1174     Unpredictable ();
1175   TRACE_ALU_INPUT1 (GPR[RS]);
1176   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1177     {
1178       if ((temp & mask) != 0)
1179         break;
1180       mask >>= 1;
1181     }
1182   GPR[RD] = EXTEND32 (i);
1183   TRACE_ALU_RESULT (GPR[RD]);
1184 }
1185
1186
1187
1188 :function:::void:do_ddiv:int rs, int rt
1189 {
1190   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1191   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1192   {
1193     signed64 n = GPR[rs];
1194     signed64 d = GPR[rt];
1195     signed64 hi;
1196     signed64 lo;
1197     if (d == 0)
1198       {
1199         lo = SIGNED64 (0x8000000000000000);
1200         hi = 0;
1201       }
1202     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1203       {
1204         lo = SIGNED64 (0x8000000000000000);
1205         hi = 0;
1206       }
1207     else
1208       {
1209         lo = (n / d);
1210         hi = (n % d);
1211       }
1212     HI = hi;
1213     LO = lo;
1214   }
1215   TRACE_ALU_RESULT2 (HI, LO);
1216 }
1217
1218 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1219 "ddiv r<RS>, r<RT>"
1220 *mipsIII:
1221 *mipsIV:
1222 *mipsV:
1223 *mips64:
1224 *vr4100:
1225 *vr5000:
1226 {
1227   check_u64 (SD_, instruction_0);
1228   do_ddiv (SD_, RS, RT);
1229 }
1230
1231
1232
1233 :function:::void:do_ddivu:int rs, int rt
1234 {
1235   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1236   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1237   {
1238     unsigned64 n = GPR[rs];
1239     unsigned64 d = GPR[rt];
1240     unsigned64 hi;
1241     unsigned64 lo;
1242     if (d == 0)
1243       {
1244         lo = SIGNED64 (0x8000000000000000);
1245         hi = 0;
1246       }
1247     else
1248       {
1249         lo = (n / d);
1250         hi = (n % d);
1251       }
1252     HI = hi;
1253     LO = lo;
1254   }
1255   TRACE_ALU_RESULT2 (HI, LO);
1256 }
1257
1258 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1259 "ddivu r<RS>, r<RT>"
1260 *mipsIII:
1261 *mipsIV:
1262 *mipsV:
1263 *mips64:
1264 *vr4100:
1265 *vr5000:
1266 {
1267   check_u64 (SD_, instruction_0);
1268   do_ddivu (SD_, RS, RT);
1269 }
1270
1271
1272
1273 :function:::void:do_div:int rs, int rt
1274 {
1275   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1276   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1277   {
1278     signed32 n = GPR[rs];
1279     signed32 d = GPR[rt];
1280     if (d == 0)
1281       {
1282         LO = EXTEND32 (0x80000000);
1283         HI = EXTEND32 (0);
1284       }
1285     else if (n == SIGNED32 (0x80000000) && d == -1)
1286       {
1287         LO = EXTEND32 (0x80000000);
1288         HI = EXTEND32 (0);
1289       }
1290     else
1291       {
1292         LO = EXTEND32 (n / d);
1293         HI = EXTEND32 (n % d);
1294       }
1295   }
1296   TRACE_ALU_RESULT2 (HI, LO);
1297 }
1298
1299 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1300 "div r<RS>, r<RT>"
1301 *mipsI:
1302 *mipsII:
1303 *mipsIII:
1304 *mipsIV:
1305 *mipsV:
1306 *mips32:
1307 *mips64:
1308 *vr4100:
1309 *vr5000:
1310 *r3900:
1311 {
1312   do_div (SD_, RS, RT);
1313 }
1314
1315
1316
1317 :function:::void:do_divu:int rs, int rt
1318 {
1319   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1320   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1321   {
1322     unsigned32 n = GPR[rs];
1323     unsigned32 d = GPR[rt];
1324     if (d == 0)
1325       {
1326         LO = EXTEND32 (0x80000000);
1327         HI = EXTEND32 (0);
1328       }
1329     else
1330       {
1331         LO = EXTEND32 (n / d);
1332         HI = EXTEND32 (n % d);
1333       }
1334   }
1335   TRACE_ALU_RESULT2 (HI, LO);
1336 }
1337
1338 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1339 "divu r<RS>, r<RT>"
1340 *mipsI:
1341 *mipsII:
1342 *mipsIII:
1343 *mipsIV:
1344 *mipsV:
1345 *mips32:
1346 *mips64:
1347 *vr4100:
1348 *vr5000:
1349 *r3900:
1350 {
1351   do_divu (SD_, RS, RT);
1352 }
1353
1354
1355
1356 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1357 {
1358   unsigned64 lo;
1359   unsigned64 hi;
1360   unsigned64 m00;
1361   unsigned64 m01;
1362   unsigned64 m10;
1363   unsigned64 m11;
1364   unsigned64 mid;
1365   int sign;
1366   unsigned64 op1 = GPR[rs];
1367   unsigned64 op2 = GPR[rt];
1368   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1369   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1370   /* make signed multiply unsigned */
1371   sign = 0;
1372   if (signed_p)
1373     {
1374       if (op1 < 0)
1375         {
1376           op1 = - op1;
1377           ++sign;
1378         }
1379       if (op2 < 0)
1380         {
1381           op2 = - op2;
1382           ++sign;
1383         }
1384     }
1385   /* multiply out the 4 sub products */
1386   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1387   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1388   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1389   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1390   /* add the products */
1391   mid = ((unsigned64) VH4_8 (m00)
1392          + (unsigned64) VL4_8 (m10)
1393          + (unsigned64) VL4_8 (m01));
1394   lo = U8_4 (mid, m00);
1395   hi = (m11
1396         + (unsigned64) VH4_8 (mid)
1397         + (unsigned64) VH4_8 (m01)
1398         + (unsigned64) VH4_8 (m10));
1399   /* fix the sign */
1400   if (sign & 1)
1401     {
1402       lo = -lo;
1403       if (lo == 0)
1404         hi = -hi;
1405       else
1406         hi = -hi - 1;
1407     }
1408   /* save the result HI/LO (and a gpr) */
1409   LO = lo;
1410   HI = hi;
1411   if (rd != 0)
1412     GPR[rd] = lo;
1413   TRACE_ALU_RESULT2 (HI, LO);
1414 }
1415
1416 :function:::void:do_dmult:int rs, int rt, int rd
1417 {
1418   do_dmultx (SD_, rs, rt, rd, 1);
1419 }
1420
1421 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1422 "dmult r<RS>, r<RT>"
1423 *mipsIII:
1424 *mipsIV:
1425 *mipsV:
1426 *mips64:
1427 *vr4100:
1428 {
1429   check_u64 (SD_, instruction_0);
1430   do_dmult (SD_, RS, RT, 0);
1431 }
1432
1433 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1434 "dmult r<RS>, r<RT>":RD == 0
1435 "dmult r<RD>, r<RS>, r<RT>"
1436 *vr5000:
1437 {
1438   check_u64 (SD_, instruction_0);
1439   do_dmult (SD_, RS, RT, RD);
1440 }
1441
1442
1443
1444 :function:::void:do_dmultu:int rs, int rt, int rd
1445 {
1446   do_dmultx (SD_, rs, rt, rd, 0);
1447 }
1448
1449 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1450 "dmultu r<RS>, r<RT>"
1451 *mipsIII:
1452 *mipsIV:
1453 *mipsV:
1454 *mips64:
1455 *vr4100:
1456 {
1457   check_u64 (SD_, instruction_0);
1458   do_dmultu (SD_, RS, RT, 0);
1459 }
1460
1461 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1462 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1463 "dmultu r<RS>, r<RT>"
1464 *vr5000:
1465 {
1466   check_u64 (SD_, instruction_0);
1467   do_dmultu (SD_, RS, RT, RD);
1468 }
1469
1470 :function:::void:do_dsll:int rt, int rd, int shift
1471 {
1472   TRACE_ALU_INPUT2 (GPR[rt], shift);
1473   GPR[rd] = GPR[rt] << shift;
1474   TRACE_ALU_RESULT (GPR[rd]);
1475 }
1476
1477 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1478 "dsll r<RD>, r<RT>, <SHIFT>"
1479 *mipsIII:
1480 *mipsIV:
1481 *mipsV:
1482 *mips64:
1483 *vr4100:
1484 *vr5000:
1485 {
1486   check_u64 (SD_, instruction_0);
1487   do_dsll (SD_, RT, RD, SHIFT);
1488 }
1489
1490
1491 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1492 "dsll32 r<RD>, r<RT>, <SHIFT>"
1493 *mipsIII:
1494 *mipsIV:
1495 *mipsV:
1496 *mips64:
1497 *vr4100:
1498 *vr5000:
1499 {
1500   int s = 32 + SHIFT;
1501   check_u64 (SD_, instruction_0);
1502   TRACE_ALU_INPUT2 (GPR[RT], s);
1503   GPR[RD] = GPR[RT] << s;
1504   TRACE_ALU_RESULT (GPR[RD]);
1505 }
1506
1507 :function:::void:do_dsllv:int rs, int rt, int rd
1508 {
1509   int s = MASKED64 (GPR[rs], 5, 0);
1510   TRACE_ALU_INPUT2 (GPR[rt], s);
1511   GPR[rd] = GPR[rt] << s;
1512   TRACE_ALU_RESULT (GPR[rd]);
1513 }
1514
1515 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1516 "dsllv r<RD>, r<RT>, r<RS>"
1517 *mipsIII:
1518 *mipsIV:
1519 *mipsV:
1520 *mips64:
1521 *vr4100:
1522 *vr5000:
1523 {
1524   check_u64 (SD_, instruction_0);
1525   do_dsllv (SD_, RS, RT, RD);
1526 }
1527
1528 :function:::void:do_dsra:int rt, int rd, int shift
1529 {
1530   TRACE_ALU_INPUT2 (GPR[rt], shift);
1531   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1532   TRACE_ALU_RESULT (GPR[rd]);
1533 }
1534
1535
1536 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1537 "dsra r<RD>, r<RT>, <SHIFT>"
1538 *mipsIII:
1539 *mipsIV:
1540 *mipsV:
1541 *mips64:
1542 *vr4100:
1543 *vr5000:
1544 {
1545   check_u64 (SD_, instruction_0);
1546   do_dsra (SD_, RT, RD, SHIFT);
1547 }
1548
1549
1550 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1551 "dsra32 r<RD>, r<RT>, <SHIFT>"
1552 *mipsIII:
1553 *mipsIV:
1554 *mipsV:
1555 *mips64:
1556 *vr4100:
1557 *vr5000:
1558 {
1559   int s = 32 + SHIFT;
1560   check_u64 (SD_, instruction_0);
1561   TRACE_ALU_INPUT2 (GPR[RT], s);
1562   GPR[RD] = ((signed64) GPR[RT]) >> s;
1563   TRACE_ALU_RESULT (GPR[RD]);
1564 }
1565
1566
1567 :function:::void:do_dsrav:int rs, int rt, int rd
1568 {
1569   int s = MASKED64 (GPR[rs], 5, 0);
1570   TRACE_ALU_INPUT2 (GPR[rt], s);
1571   GPR[rd] = ((signed64) GPR[rt]) >> s;
1572   TRACE_ALU_RESULT (GPR[rd]);
1573 }
1574
1575 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1576 "dsrav r<RD>, r<RT>, r<RS>"
1577 *mipsIII:
1578 *mipsIV:
1579 *mipsV:
1580 *mips64:
1581 *vr4100:
1582 *vr5000:
1583 {
1584   check_u64 (SD_, instruction_0);
1585   do_dsrav (SD_, RS, RT, RD);
1586 }
1587
1588 :function:::void:do_dsrl:int rt, int rd, int shift
1589 {
1590   TRACE_ALU_INPUT2 (GPR[rt], shift);
1591   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1592   TRACE_ALU_RESULT (GPR[rd]);
1593 }
1594
1595
1596 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1597 "dsrl r<RD>, r<RT>, <SHIFT>"
1598 *mipsIII:
1599 *mipsIV:
1600 *mipsV:
1601 *mips64:
1602 *vr4100:
1603 *vr5000:
1604 {
1605   check_u64 (SD_, instruction_0);
1606   do_dsrl (SD_, RT, RD, SHIFT);
1607 }
1608
1609
1610 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1611 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1612 *mipsIII:
1613 *mipsIV:
1614 *mipsV:
1615 *mips64:
1616 *vr4100:
1617 *vr5000:
1618 {
1619   int s = 32 + SHIFT;
1620   check_u64 (SD_, instruction_0);
1621   TRACE_ALU_INPUT2 (GPR[RT], s);
1622   GPR[RD] = (unsigned64) GPR[RT] >> s;
1623   TRACE_ALU_RESULT (GPR[RD]);
1624 }
1625
1626
1627 :function:::void:do_dsrlv:int rs, int rt, int rd
1628 {
1629   int s = MASKED64 (GPR[rs], 5, 0);
1630   TRACE_ALU_INPUT2 (GPR[rt], s);
1631   GPR[rd] = (unsigned64) GPR[rt] >> s;
1632   TRACE_ALU_RESULT (GPR[rd]);
1633 }
1634
1635
1636
1637 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1638 "dsrlv r<RD>, r<RT>, r<RS>"
1639 *mipsIII:
1640 *mipsIV:
1641 *mipsV:
1642 *mips64:
1643 *vr4100:
1644 *vr5000:
1645 {
1646   check_u64 (SD_, instruction_0);
1647   do_dsrlv (SD_, RS, RT, RD);
1648 }
1649
1650
1651 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1652 "dsub r<RD>, r<RS>, r<RT>"
1653 *mipsIII:
1654 *mipsIV:
1655 *mipsV:
1656 *mips64:
1657 *vr4100:
1658 *vr5000:
1659 {
1660   check_u64 (SD_, instruction_0);
1661   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1662   {
1663     ALU64_BEGIN (GPR[RS]);
1664     ALU64_SUB (GPR[RT]);
1665     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1666   }
1667   TRACE_ALU_RESULT (GPR[RD]);
1668 }
1669
1670
1671 :function:::void:do_dsubu:int rs, int rt, int rd
1672 {
1673   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1674   GPR[rd] = GPR[rs] - GPR[rt];
1675   TRACE_ALU_RESULT (GPR[rd]);
1676 }
1677
1678 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1679 "dsubu r<RD>, r<RS>, r<RT>"
1680 *mipsIII:
1681 *mipsIV:
1682 *mipsV:
1683 *mips64:
1684 *vr4100:
1685 *vr5000:
1686 {
1687   check_u64 (SD_, instruction_0);
1688   do_dsubu (SD_, RS, RT, RD);
1689 }
1690
1691
1692 000010,26.INSTR_INDEX:NORMAL:32::J
1693 "j <INSTR_INDEX>"
1694 *mipsI:
1695 *mipsII:
1696 *mipsIII:
1697 *mipsIV:
1698 *mipsV:
1699 *mips32:
1700 *mips64:
1701 *vr4100:
1702 *vr5000:
1703 *r3900:
1704 {
1705   /* NOTE: The region used is that of the delay slot NIA and NOT the
1706      current instruction */
1707   address_word region = (NIA & MASK (63, 28));
1708   DELAY_SLOT (region | (INSTR_INDEX << 2));
1709 }
1710
1711
1712 000011,26.INSTR_INDEX:NORMAL:32::JAL
1713 "jal <INSTR_INDEX>"
1714 *mipsI:
1715 *mipsII:
1716 *mipsIII:
1717 *mipsIV:
1718 *mipsV:
1719 *mips32:
1720 *mips64:
1721 *vr4100:
1722 *vr5000:
1723 *r3900:
1724 {
1725   /* NOTE: The region used is that of the delay slot and NOT the
1726      current instruction */
1727   address_word region = (NIA & MASK (63, 28));
1728   GPR[31] = CIA + 8;
1729   DELAY_SLOT (region | (INSTR_INDEX << 2));
1730 }
1731
1732 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1733 "jalr r<RS>":RD == 31
1734 "jalr r<RD>, r<RS>"
1735 *mipsI:
1736 *mipsII:
1737 *mipsIII:
1738 *mipsIV:
1739 *mipsV:
1740 *mips32:
1741 *mips64:
1742 *vr4100:
1743 *vr5000:
1744 *r3900:
1745 {
1746   address_word temp = GPR[RS];
1747   GPR[RD] = CIA + 8;
1748   DELAY_SLOT (temp);
1749 }
1750
1751
1752 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1753 "jr r<RS>"
1754 *mipsI:
1755 *mipsII:
1756 *mipsIII:
1757 *mipsIV:
1758 *mipsV:
1759 *mips32:
1760 *mips64:
1761 *vr4100:
1762 *vr5000:
1763 *r3900:
1764 {
1765   DELAY_SLOT (GPR[RS]);
1766 }
1767
1768
1769 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1770 {
1771   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1772   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1773   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1774   unsigned int byte;
1775   address_word paddr;
1776   int uncached;
1777   unsigned64 memval;
1778   address_word vaddr;
1779
1780   vaddr = loadstore_ea (SD_, base, offset);
1781   if ((vaddr & access) != 0)
1782     {
1783       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1784     }
1785   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1786   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1787   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1788   byte = ((vaddr & mask) ^ bigendiancpu);
1789   return (memval >> (8 * byte));
1790 }
1791
1792 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1793 {
1794   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1795   address_word reverseendian = (ReverseEndian ? -1 : 0);
1796   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1797   unsigned int byte;
1798   unsigned int word;
1799   address_word paddr;
1800   int uncached;
1801   unsigned64 memval;
1802   address_word vaddr;
1803   int nr_lhs_bits;
1804   int nr_rhs_bits;
1805   unsigned_word lhs_mask;
1806   unsigned_word temp;
1807
1808   vaddr = loadstore_ea (SD_, base, offset);
1809   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1810   paddr = (paddr ^ (reverseendian & mask));
1811   if (BigEndianMem == 0)
1812     paddr = paddr & ~access;
1813
1814   /* compute where within the word/mem we are */
1815   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1816   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1817   nr_lhs_bits = 8 * byte + 8;
1818   nr_rhs_bits = 8 * access - 8 * byte;
1819   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1820
1821   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1822            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1823            (long) ((unsigned64) paddr >> 32), (long) paddr,
1824            word, byte, nr_lhs_bits, nr_rhs_bits); */
1825
1826   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1827   if (word == 0)
1828     {
1829       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1830       temp = (memval << nr_rhs_bits);
1831     }
1832   else
1833     {
1834       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1835       temp = (memval >> nr_lhs_bits);
1836     }
1837   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1838   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1839
1840   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1841            (long) ((unsigned64) memval >> 32), (long) memval,
1842            (long) ((unsigned64) temp >> 32), (long) temp,
1843            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1844            (long) (rt >> 32), (long) rt); */
1845   return rt;
1846 }
1847
1848 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1849 {
1850   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1851   address_word reverseendian = (ReverseEndian ? -1 : 0);
1852   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1853   unsigned int byte;
1854   address_word paddr;
1855   int uncached;
1856   unsigned64 memval;
1857   address_word vaddr;
1858
1859   vaddr = loadstore_ea (SD_, base, offset);
1860   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1861   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1862   paddr = (paddr ^ (reverseendian & mask));
1863   if (BigEndianMem != 0)
1864     paddr = paddr & ~access;
1865   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1866   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1867   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1868   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1869      (long) paddr, byte, (long) paddr, (long) memval); */
1870   {
1871     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1872     rt &= ~screen;
1873     rt |= (memval >> (8 * byte)) & screen;
1874   }
1875   return rt;
1876 }
1877
1878
1879 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1880 "lb r<RT>, <OFFSET>(r<BASE>)"
1881 *mipsI:
1882 *mipsII:
1883 *mipsIII:
1884 *mipsIV:
1885 *mipsV:
1886 *mips32:
1887 *mips64:
1888 *vr4100:
1889 *vr5000:
1890 *r3900:
1891 {
1892   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1893 }
1894
1895
1896 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1897 "lbu r<RT>, <OFFSET>(r<BASE>)"
1898 *mipsI:
1899 *mipsII:
1900 *mipsIII:
1901 *mipsIV:
1902 *mipsV:
1903 *mips32:
1904 *mips64:
1905 *vr4100:
1906 *vr5000:
1907 *r3900:
1908 {
1909   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1910 }
1911
1912
1913 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1914 "ld r<RT>, <OFFSET>(r<BASE>)"
1915 *mipsIII:
1916 *mipsIV:
1917 *mipsV:
1918 *mips64:
1919 *vr4100:
1920 *vr5000:
1921 {
1922   check_u64 (SD_, instruction_0);
1923   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1924 }
1925
1926
1927 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1928 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1929 *mipsII:
1930 *mipsIII:
1931 *mipsIV:
1932 *mipsV:
1933 *mips32:
1934 *mips64:
1935 *vr4100:
1936 *vr5000:
1937 *r3900:
1938 {
1939   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1940 }
1941
1942
1943
1944
1945 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1946 "ldl r<RT>, <OFFSET>(r<BASE>)"
1947 *mipsIII:
1948 *mipsIV:
1949 *mipsV:
1950 *mips64:
1951 *vr4100:
1952 *vr5000:
1953 {
1954   check_u64 (SD_, instruction_0);
1955   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1956 }
1957
1958
1959 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1960 "ldr r<RT>, <OFFSET>(r<BASE>)"
1961 *mipsIII:
1962 *mipsIV:
1963 *mipsV:
1964 *mips64:
1965 *vr4100:
1966 *vr5000:
1967 {
1968   check_u64 (SD_, instruction_0);
1969   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1970 }
1971
1972
1973 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1974 "lh r<RT>, <OFFSET>(r<BASE>)"
1975 *mipsI:
1976 *mipsII:
1977 *mipsIII:
1978 *mipsIV:
1979 *mipsV:
1980 *mips32:
1981 *mips64:
1982 *vr4100:
1983 *vr5000:
1984 *r3900:
1985 {
1986   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1987 }
1988
1989
1990 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1991 "lhu r<RT>, <OFFSET>(r<BASE>)"
1992 *mipsI:
1993 *mipsII:
1994 *mipsIII:
1995 *mipsIV:
1996 *mipsV:
1997 *mips32:
1998 *mips64:
1999 *vr4100:
2000 *vr5000:
2001 *r3900:
2002 {
2003   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2004 }
2005
2006
2007 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2008 "ll r<RT>, <OFFSET>(r<BASE>)"
2009 *mipsII:
2010 *mipsIII:
2011 *mipsIV:
2012 *mipsV:
2013 *mips32:
2014 *mips64:
2015 *vr4100:
2016 *vr5000:
2017 {
2018   address_word base = GPR[BASE];
2019   address_word offset = EXTEND16 (OFFSET);
2020   {
2021     address_word vaddr = loadstore_ea (SD_, base, offset);
2022     address_word paddr;
2023     int uncached;
2024     if ((vaddr & 3) != 0)
2025       {
2026         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2027       }
2028     else
2029       {
2030         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2031           {
2032             unsigned64 memval = 0;
2033             unsigned64 memval1 = 0;
2034             unsigned64 mask = 0x7;
2035             unsigned int shift = 2;
2036             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2037             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2038             unsigned int byte;
2039             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2040             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2041             byte = ((vaddr & mask) ^ (bigend << shift));
2042             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2043             LLBIT = 1;
2044           }
2045       }
2046   }
2047 }
2048
2049
2050 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2051 "lld r<RT>, <OFFSET>(r<BASE>)"
2052 *mipsIII:
2053 *mipsIV:
2054 *mipsV:
2055 *mips64:
2056 *vr4100:
2057 *vr5000:
2058 {
2059   address_word base = GPR[BASE];
2060   address_word offset = EXTEND16 (OFFSET);
2061   check_u64 (SD_, instruction_0);
2062   {
2063     address_word vaddr = loadstore_ea (SD_, base, offset);
2064     address_word paddr;
2065     int uncached;
2066     if ((vaddr & 7) != 0)
2067       {
2068         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2069       }
2070     else
2071       {
2072         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2073           {
2074             unsigned64 memval = 0;
2075             unsigned64 memval1 = 0;
2076             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2077             GPR[RT] = memval;
2078             LLBIT = 1;
2079           }
2080       }
2081   }
2082 }
2083
2084
2085 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2086 "lui r<RT>, %#lx<IMMEDIATE>"
2087 *mipsI:
2088 *mipsII:
2089 *mipsIII:
2090 *mipsIV:
2091 *mipsV:
2092 *mips32:
2093 *mips64:
2094 *vr4100:
2095 *vr5000:
2096 *r3900:
2097 {
2098   TRACE_ALU_INPUT1 (IMMEDIATE);
2099   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2100   TRACE_ALU_RESULT (GPR[RT]);
2101 }
2102
2103
2104 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2105 "lw r<RT>, <OFFSET>(r<BASE>)"
2106 *mipsI:
2107 *mipsII:
2108 *mipsIII:
2109 *mipsIV:
2110 *mipsV:
2111 *mips32:
2112 *mips64:
2113 *vr4100:
2114 *vr5000:
2115 *r3900:
2116 {
2117   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2118 }
2119
2120
2121 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2122 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2123 *mipsI:
2124 *mipsII:
2125 *mipsIII:
2126 *mipsIV:
2127 *mipsV:
2128 *mips32:
2129 *mips64:
2130 *vr4100:
2131 *vr5000:
2132 *r3900:
2133 {
2134   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2135 }
2136
2137
2138 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2139 "lwl r<RT>, <OFFSET>(r<BASE>)"
2140 *mipsI:
2141 *mipsII:
2142 *mipsIII:
2143 *mipsIV:
2144 *mipsV:
2145 *mips32:
2146 *mips64:
2147 *vr4100:
2148 *vr5000:
2149 *r3900:
2150 {
2151   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2152 }
2153
2154
2155 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2156 "lwr r<RT>, <OFFSET>(r<BASE>)"
2157 *mipsI:
2158 *mipsII:
2159 *mipsIII:
2160 *mipsIV:
2161 *mipsV:
2162 *mips32:
2163 *mips64:
2164 *vr4100:
2165 *vr5000:
2166 *r3900:
2167 {
2168   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2169 }
2170
2171
2172 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2173 "lwu r<RT>, <OFFSET>(r<BASE>)"
2174 *mipsIII:
2175 *mipsIV:
2176 *mipsV:
2177 *mips64:
2178 *vr4100:
2179 *vr5000:
2180 {
2181   check_u64 (SD_, instruction_0);
2182   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2183 }
2184
2185
2186
2187 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2188 "madd r<RS>, r<RT>"
2189 *mips32:
2190 *mips64:
2191 {
2192   signed64 temp;
2193   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2194   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2195     Unpredictable ();
2196   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2197   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2198           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2199   LO = EXTEND32 (temp);
2200   HI = EXTEND32 (VH4_8 (temp));
2201   TRACE_ALU_RESULT2 (HI, LO);
2202 }
2203
2204
2205
2206 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2207 "maddu r<RS>, r<RT>"
2208 *mips32:
2209 *mips64:
2210 {
2211   unsigned64 temp;
2212   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2213   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2214     Unpredictable ();
2215   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2216   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2217           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2218   LO = EXTEND32 (temp);
2219   HI = EXTEND32 (VH4_8 (temp));
2220   TRACE_ALU_RESULT2 (HI, LO);
2221 }
2222
2223
2224 :function:::void:do_mfhi:int rd
2225 {
2226   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2227   TRACE_ALU_INPUT1 (HI);
2228   GPR[rd] = HI;
2229   TRACE_ALU_RESULT (GPR[rd]);
2230 }
2231
2232 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2233 "mfhi r<RD>"
2234 *mipsI:
2235 *mipsII:
2236 *mipsIII:
2237 *mipsIV:
2238 *mipsV:
2239 *mips32:
2240 *mips64:
2241 *vr4100:
2242 *vr5000:
2243 *r3900:
2244 {
2245   do_mfhi (SD_, RD);
2246 }
2247
2248
2249
2250 :function:::void:do_mflo:int rd
2251 {
2252   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2253   TRACE_ALU_INPUT1 (LO);
2254   GPR[rd] = LO;
2255   TRACE_ALU_RESULT (GPR[rd]);
2256 }
2257
2258 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2259 "mflo r<RD>"
2260 *mipsI:
2261 *mipsII:
2262 *mipsIII:
2263 *mipsIV:
2264 *mipsV:
2265 *mips32:
2266 *mips64:
2267 *vr4100:
2268 *vr5000:
2269 *r3900:
2270 {
2271   do_mflo (SD_, RD);
2272 }
2273
2274
2275
2276 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2277 "movn r<RD>, r<RS>, r<RT>"
2278 *mipsIV:
2279 *mipsV:
2280 *mips32:
2281 *mips64:
2282 *vr5000:
2283 {
2284   if (GPR[RT] != 0)
2285     {
2286       GPR[RD] = GPR[RS];
2287       TRACE_ALU_RESULT (GPR[RD]);
2288     }
2289 }
2290
2291
2292
2293 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2294 "movz r<RD>, r<RS>, r<RT>"
2295 *mipsIV:
2296 *mipsV:
2297 *mips32:
2298 *mips64:
2299 *vr5000:
2300 {
2301   if (GPR[RT] == 0)
2302     {
2303       GPR[RD] = GPR[RS];
2304       TRACE_ALU_RESULT (GPR[RD]);
2305     }
2306 }
2307
2308
2309
2310 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2311 "msub r<RS>, r<RT>"
2312 *mips32:
2313 *mips64:
2314 {
2315   signed64 temp;
2316   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2317   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2318     Unpredictable ();
2319   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2320   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2321           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2322   LO = EXTEND32 (temp);
2323   HI = EXTEND32 (VH4_8 (temp));
2324   TRACE_ALU_RESULT2 (HI, LO);
2325 }
2326
2327
2328
2329 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2330 "msubu r<RS>, r<RT>"
2331 *mips32:
2332 *mips64:
2333 {
2334   unsigned64 temp;
2335   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2336   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2337     Unpredictable ();
2338   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2339   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2340           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2341   LO = EXTEND32 (temp);
2342   HI = EXTEND32 (VH4_8 (temp));
2343   TRACE_ALU_RESULT2 (HI, LO);
2344 }
2345
2346
2347
2348 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2349 "mthi r<RS>"
2350 *mipsI:
2351 *mipsII:
2352 *mipsIII:
2353 *mipsIV:
2354 *mipsV:
2355 *mips32:
2356 *mips64:
2357 *vr4100:
2358 *vr5000:
2359 *r3900:
2360 {
2361   check_mt_hilo (SD_, HIHISTORY);
2362   HI = GPR[RS];
2363 }
2364
2365
2366
2367 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2368 "mtlo r<RS>"
2369 *mipsI:
2370 *mipsII:
2371 *mipsIII:
2372 *mipsIV:
2373 *mipsV:
2374 *mips32:
2375 *mips64:
2376 *vr4100:
2377 *vr5000:
2378 *r3900:
2379 {
2380   check_mt_hilo (SD_, LOHISTORY);
2381   LO = GPR[RS];
2382 }
2383
2384
2385
2386 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2387 "mul r<RD>, r<RS>, r<RT>"
2388 *mips32:
2389 *mips64:
2390 {
2391   signed64 prod;
2392   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2393     Unpredictable ();
2394   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2395   prod = (((signed64)(signed32) GPR[RS])
2396           * ((signed64)(signed32) GPR[RT]));
2397   GPR[RD] = EXTEND32 (VL4_8 (prod));
2398   TRACE_ALU_RESULT (GPR[RD]);
2399 }
2400
2401
2402
2403 :function:::void:do_mult:int rs, int rt, int rd
2404 {
2405   signed64 prod;
2406   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2407   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2408     Unpredictable ();
2409   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2410   prod = (((signed64)(signed32) GPR[rs])
2411           * ((signed64)(signed32) GPR[rt]));
2412   LO = EXTEND32 (VL4_8 (prod));
2413   HI = EXTEND32 (VH4_8 (prod));
2414   if (rd != 0)
2415     GPR[rd] = LO;
2416   TRACE_ALU_RESULT2 (HI, LO);
2417 }
2418
2419 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2420 "mult r<RS>, r<RT>"
2421 *mipsI:
2422 *mipsII:
2423 *mipsIII:
2424 *mipsIV:
2425 *mipsV:
2426 *mips32:
2427 *mips64:
2428 *vr4100:
2429 {
2430   do_mult (SD_, RS, RT, 0);
2431 }
2432
2433
2434 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2435 "mult r<RS>, r<RT>":RD == 0
2436 "mult r<RD>, r<RS>, r<RT>"
2437 *vr5000:
2438 *r3900:
2439 {
2440   do_mult (SD_, RS, RT, RD);
2441 }
2442
2443
2444 :function:::void:do_multu:int rs, int rt, int rd
2445 {
2446   unsigned64 prod;
2447   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2448   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2449     Unpredictable ();
2450   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2451   prod = (((unsigned64)(unsigned32) GPR[rs])
2452           * ((unsigned64)(unsigned32) GPR[rt]));
2453   LO = EXTEND32 (VL4_8 (prod));
2454   HI = EXTEND32 (VH4_8 (prod));
2455   if (rd != 0)
2456     GPR[rd] = LO;
2457   TRACE_ALU_RESULT2 (HI, LO);
2458 }
2459
2460 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2461 "multu r<RS>, r<RT>"
2462 *mipsI:
2463 *mipsII:
2464 *mipsIII:
2465 *mipsIV:
2466 *mipsV:
2467 *mips32:
2468 *mips64:
2469 *vr4100:
2470 {
2471   do_multu (SD_, RS, RT, 0);
2472 }
2473
2474 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2475 "multu r<RS>, r<RT>":RD == 0
2476 "multu r<RD>, r<RS>, r<RT>"
2477 *vr5000:
2478 *r3900:
2479 {
2480   do_multu (SD_, RS, RT, RD);
2481 }
2482
2483
2484 :function:::void:do_nor:int rs, int rt, int rd
2485 {
2486   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2487   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2488   TRACE_ALU_RESULT (GPR[rd]);
2489 }
2490
2491 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2492 "nor r<RD>, r<RS>, r<RT>"
2493 *mipsI:
2494 *mipsII:
2495 *mipsIII:
2496 *mipsIV:
2497 *mipsV:
2498 *mips32:
2499 *mips64:
2500 *vr4100:
2501 *vr5000:
2502 *r3900:
2503 {
2504   do_nor (SD_, RS, RT, RD);
2505 }
2506
2507
2508 :function:::void:do_or:int rs, int rt, int rd
2509 {
2510   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2511   GPR[rd] = (GPR[rs] | GPR[rt]);
2512   TRACE_ALU_RESULT (GPR[rd]);
2513 }
2514
2515 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2516 "or r<RD>, r<RS>, r<RT>"
2517 *mipsI:
2518 *mipsII:
2519 *mipsIII:
2520 *mipsIV:
2521 *mipsV:
2522 *mips32:
2523 *mips64:
2524 *vr4100:
2525 *vr5000:
2526 *r3900:
2527 {
2528   do_or (SD_, RS, RT, RD);
2529 }
2530
2531
2532
2533 :function:::void:do_ori:int rs, int rt, unsigned immediate
2534 {
2535   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2536   GPR[rt] = (GPR[rs] | immediate);
2537   TRACE_ALU_RESULT (GPR[rt]);
2538 }
2539
2540 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2541 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2542 *mipsI:
2543 *mipsII:
2544 *mipsIII:
2545 *mipsIV:
2546 *mipsV:
2547 *mips32:
2548 *mips64:
2549 *vr4100:
2550 *vr5000:
2551 *r3900:
2552 {
2553   do_ori (SD_, RS, RT, IMMEDIATE);
2554 }
2555
2556
2557 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2558 "pref <HINT>, <OFFSET>(r<BASE>)"
2559 *mipsIV:
2560 *mipsV:
2561 *mips32:
2562 *mips64:
2563 *vr5000:
2564 {
2565   address_word base = GPR[BASE];
2566   address_word offset = EXTEND16 (OFFSET);
2567   {
2568     address_word vaddr = loadstore_ea (SD_, base, offset);
2569     address_word paddr;
2570     int uncached;
2571     {
2572       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2573         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2574     }
2575   }
2576 }
2577
2578
2579 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2580 {
2581   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2582   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2583   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2584   unsigned int byte;
2585   address_word paddr;
2586   int uncached;
2587   unsigned64 memval;
2588   address_word vaddr;
2589
2590   vaddr = loadstore_ea (SD_, base, offset);
2591   if ((vaddr & access) != 0)
2592     {
2593       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2594     }
2595   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2596   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2597   byte = ((vaddr & mask) ^ bigendiancpu);
2598   memval = (word << (8 * byte));
2599   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2600 }
2601
2602 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2603 {
2604   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2605   address_word reverseendian = (ReverseEndian ? -1 : 0);
2606   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2607   unsigned int byte;
2608   unsigned int word;
2609   address_word paddr;
2610   int uncached;
2611   unsigned64 memval;
2612   address_word vaddr;
2613   int nr_lhs_bits;
2614   int nr_rhs_bits;
2615
2616   vaddr = loadstore_ea (SD_, base, offset);
2617   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2618   paddr = (paddr ^ (reverseendian & mask));
2619   if (BigEndianMem == 0)
2620     paddr = paddr & ~access;
2621
2622   /* compute where within the word/mem we are */
2623   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2624   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2625   nr_lhs_bits = 8 * byte + 8;
2626   nr_rhs_bits = 8 * access - 8 * byte;
2627   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2628   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2629            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2630            (long) ((unsigned64) paddr >> 32), (long) paddr,
2631            word, byte, nr_lhs_bits, nr_rhs_bits); */
2632
2633   if (word == 0)
2634     {
2635       memval = (rt >> nr_rhs_bits);
2636     }
2637   else
2638     {
2639       memval = (rt << nr_lhs_bits);
2640     }
2641   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2642            (long) ((unsigned64) rt >> 32), (long) rt,
2643            (long) ((unsigned64) memval >> 32), (long) memval); */
2644   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2645 }
2646
2647 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2648 {
2649   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2650   address_word reverseendian = (ReverseEndian ? -1 : 0);
2651   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2652   unsigned int byte;
2653   address_word paddr;
2654   int uncached;
2655   unsigned64 memval;
2656   address_word vaddr;
2657
2658   vaddr = loadstore_ea (SD_, base, offset);
2659   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2660   paddr = (paddr ^ (reverseendian & mask));
2661   if (BigEndianMem != 0)
2662     paddr &= ~access;
2663   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2664   memval = (rt << (byte * 8));
2665   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2666 }
2667
2668
2669 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2670 "sb r<RT>, <OFFSET>(r<BASE>)"
2671 *mipsI:
2672 *mipsII:
2673 *mipsIII:
2674 *mipsIV:
2675 *mipsV:
2676 *mips32:
2677 *mips64:
2678 *vr4100:
2679 *vr5000:
2680 *r3900:
2681 {
2682   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2683 }
2684
2685
2686 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2687 "sc r<RT>, <OFFSET>(r<BASE>)"
2688 *mipsII:
2689 *mipsIII:
2690 *mipsIV:
2691 *mipsV:
2692 *mips32:
2693 *mips64:
2694 *vr4100:
2695 *vr5000:
2696 {
2697   unsigned32 instruction = instruction_0;
2698   address_word base = GPR[BASE];
2699   address_word offset = EXTEND16 (OFFSET);
2700   {
2701     address_word vaddr = loadstore_ea (SD_, base, offset);
2702     address_word paddr;
2703     int uncached;
2704     if ((vaddr & 3) != 0)
2705       {
2706         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2707       }
2708     else
2709       {
2710         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2711           {
2712             unsigned64 memval = 0;
2713             unsigned64 memval1 = 0;
2714             unsigned64 mask = 0x7;
2715             unsigned int byte;
2716             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2717             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2718             memval = ((unsigned64) GPR[RT] << (8 * byte));
2719             if (LLBIT)
2720               {
2721                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2722               }
2723             GPR[RT] = LLBIT;
2724           }
2725       }
2726   }
2727 }
2728
2729
2730 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2731 "scd r<RT>, <OFFSET>(r<BASE>)"
2732 *mipsIII:
2733 *mipsIV:
2734 *mipsV:
2735 *mips64:
2736 *vr4100:
2737 *vr5000:
2738 {
2739   address_word base = GPR[BASE];
2740   address_word offset = EXTEND16 (OFFSET);
2741   check_u64 (SD_, instruction_0);
2742   {
2743     address_word vaddr = loadstore_ea (SD_, base, offset);
2744     address_word paddr;
2745     int uncached;
2746     if ((vaddr & 7) != 0)
2747       {
2748         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2749       }
2750     else
2751       {
2752         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2753           {
2754             unsigned64 memval = 0;
2755             unsigned64 memval1 = 0;
2756             memval = GPR[RT];
2757             if (LLBIT)
2758               {
2759                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2760               }
2761             GPR[RT] = LLBIT;
2762           }
2763       }
2764   }
2765 }
2766
2767
2768 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2769 "sd r<RT>, <OFFSET>(r<BASE>)"
2770 *mipsIII:
2771 *mipsIV:
2772 *mipsV:
2773 *mips64:
2774 *vr4100:
2775 *vr5000:
2776 {
2777   check_u64 (SD_, instruction_0);
2778   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2779 }
2780
2781
2782 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2783 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2784 *mipsII:
2785 *mipsIII:
2786 *mipsIV:
2787 *mipsV:
2788 *mips32:
2789 *mips64:
2790 *vr4100:
2791 *vr5000:
2792 {
2793   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2794 }
2795
2796
2797 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2798 "sdl r<RT>, <OFFSET>(r<BASE>)"
2799 *mipsIII:
2800 *mipsIV:
2801 *mipsV:
2802 *mips64:
2803 *vr4100:
2804 *vr5000:
2805 {
2806   check_u64 (SD_, instruction_0);
2807   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2808 }
2809
2810
2811 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2812 "sdr r<RT>, <OFFSET>(r<BASE>)"
2813 *mipsIII:
2814 *mipsIV:
2815 *mipsV:
2816 *mips64:
2817 *vr4100:
2818 *vr5000:
2819 {
2820   check_u64 (SD_, instruction_0);
2821   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2822 }
2823
2824
2825 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2826 "sh r<RT>, <OFFSET>(r<BASE>)"
2827 *mipsI:
2828 *mipsII:
2829 *mipsIII:
2830 *mipsIV:
2831 *mipsV:
2832 *mips32:
2833 *mips64:
2834 *vr4100:
2835 *vr5000:
2836 *r3900:
2837 {
2838   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2839 }
2840
2841
2842 :function:::void:do_sll:int rt, int rd, int shift
2843 {
2844   unsigned32 temp = (GPR[rt] << shift);
2845   TRACE_ALU_INPUT2 (GPR[rt], shift);
2846   GPR[rd] = EXTEND32 (temp);
2847   TRACE_ALU_RESULT (GPR[rd]);
2848 }
2849
2850 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2851 "nop":RD == 0 && RT == 0 && SHIFT == 0
2852 "sll r<RD>, r<RT>, <SHIFT>"
2853 *mipsI:
2854 *mipsII:
2855 *mipsIII:
2856 *mipsIV:
2857 *mipsV:
2858 *vr4100:
2859 *vr5000:
2860 *r3900:
2861 {
2862   /* Skip shift for NOP, so that there won't be lots of extraneous
2863      trace output.  */
2864   if (RD != 0 || RT != 0 || SHIFT != 0)
2865     do_sll (SD_, RT, RD, SHIFT);
2866 }
2867
2868 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2869 "nop":RD == 0 && RT == 0 && SHIFT == 0
2870 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2871 "sll r<RD>, r<RT>, <SHIFT>"
2872 *mips32:
2873 *mips64:
2874 {
2875   /* Skip shift for NOP and SSNOP, so that there won't be lots of
2876      extraneous trace output.  */
2877   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2878     do_sll (SD_, RT, RD, SHIFT);
2879 }
2880
2881
2882 :function:::void:do_sllv:int rs, int rt, int rd
2883 {
2884   int s = MASKED (GPR[rs], 4, 0);
2885   unsigned32 temp = (GPR[rt] << s);
2886   TRACE_ALU_INPUT2 (GPR[rt], s);
2887   GPR[rd] = EXTEND32 (temp);
2888   TRACE_ALU_RESULT (GPR[rd]);
2889 }
2890
2891 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2892 "sllv r<RD>, r<RT>, r<RS>"
2893 *mipsI:
2894 *mipsII:
2895 *mipsIII:
2896 *mipsIV:
2897 *mipsV:
2898 *mips32:
2899 *mips64:
2900 *vr4100:
2901 *vr5000:
2902 *r3900:
2903 {
2904   do_sllv (SD_, RS, RT, RD);
2905 }
2906
2907
2908 :function:::void:do_slt:int rs, int rt, int rd
2909 {
2910   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2911   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2912   TRACE_ALU_RESULT (GPR[rd]);
2913 }
2914
2915 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2916 "slt r<RD>, r<RS>, r<RT>"
2917 *mipsI:
2918 *mipsII:
2919 *mipsIII:
2920 *mipsIV:
2921 *mipsV:
2922 *mips32:
2923 *mips64:
2924 *vr4100:
2925 *vr5000:
2926 *r3900:
2927 {
2928   do_slt (SD_, RS, RT, RD);
2929 }
2930
2931
2932 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2933 {
2934   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2935   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2936   TRACE_ALU_RESULT (GPR[rt]);
2937 }
2938
2939 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2940 "slti r<RT>, r<RS>, <IMMEDIATE>"
2941 *mipsI:
2942 *mipsII:
2943 *mipsIII:
2944 *mipsIV:
2945 *mipsV:
2946 *mips32:
2947 *mips64:
2948 *vr4100:
2949 *vr5000:
2950 *r3900:
2951 {
2952   do_slti (SD_, RS, RT, IMMEDIATE);
2953 }
2954
2955
2956 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2957 {
2958   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2959   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2960   TRACE_ALU_RESULT (GPR[rt]);
2961 }
2962
2963 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2964 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2965 *mipsI:
2966 *mipsII:
2967 *mipsIII:
2968 *mipsIV:
2969 *mipsV:
2970 *mips32:
2971 *mips64:
2972 *vr4100:
2973 *vr5000:
2974 *r3900:
2975 {
2976   do_sltiu (SD_, RS, RT, IMMEDIATE);
2977 }
2978
2979
2980
2981 :function:::void:do_sltu:int rs, int rt, int rd
2982 {
2983   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2984   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2985   TRACE_ALU_RESULT (GPR[rd]);
2986 }
2987
2988 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2989 "sltu r<RD>, r<RS>, r<RT>"
2990 *mipsI:
2991 *mipsII:
2992 *mipsIII:
2993 *mipsIV:
2994 *mipsV:
2995 *mips32:
2996 *mips64:
2997 *vr4100:
2998 *vr5000:
2999 *r3900:
3000 {
3001   do_sltu (SD_, RS, RT, RD);
3002 }
3003
3004
3005 :function:::void:do_sra:int rt, int rd, int shift
3006 {
3007   signed32 temp = (signed32) GPR[rt] >> shift;
3008   if (NotWordValue (GPR[rt]))
3009     Unpredictable ();
3010   TRACE_ALU_INPUT2 (GPR[rt], shift);
3011   GPR[rd] = EXTEND32 (temp);
3012   TRACE_ALU_RESULT (GPR[rd]);
3013 }
3014
3015 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3016 "sra r<RD>, r<RT>, <SHIFT>"
3017 *mipsI:
3018 *mipsII:
3019 *mipsIII:
3020 *mipsIV:
3021 *mipsV:
3022 *mips32:
3023 *mips64:
3024 *vr4100:
3025 *vr5000:
3026 *r3900:
3027 {
3028   do_sra (SD_, RT, RD, SHIFT);
3029 }
3030
3031
3032
3033 :function:::void:do_srav:int rs, int rt, int rd
3034 {
3035   int s = MASKED (GPR[rs], 4, 0);
3036   signed32 temp = (signed32) GPR[rt] >> s;
3037   if (NotWordValue (GPR[rt]))
3038     Unpredictable ();
3039   TRACE_ALU_INPUT2 (GPR[rt], s);
3040   GPR[rd] = EXTEND32 (temp);
3041   TRACE_ALU_RESULT (GPR[rd]);
3042 }
3043
3044 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3045 "srav r<RD>, r<RT>, r<RS>"
3046 *mipsI:
3047 *mipsII:
3048 *mipsIII:
3049 *mipsIV:
3050 *mipsV:
3051 *mips32:
3052 *mips64:
3053 *vr4100:
3054 *vr5000:
3055 *r3900:
3056 {
3057   do_srav (SD_, RS, RT, RD);
3058 }
3059
3060
3061
3062 :function:::void:do_srl:int rt, int rd, int shift
3063 {
3064   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3065   if (NotWordValue (GPR[rt]))
3066     Unpredictable ();
3067   TRACE_ALU_INPUT2 (GPR[rt], shift);
3068   GPR[rd] = EXTEND32 (temp);
3069   TRACE_ALU_RESULT (GPR[rd]);
3070 }
3071
3072 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3073 "srl r<RD>, r<RT>, <SHIFT>"
3074 *mipsI:
3075 *mipsII:
3076 *mipsIII:
3077 *mipsIV:
3078 *mipsV:
3079 *mips32:
3080 *mips64:
3081 *vr4100:
3082 *vr5000:
3083 *r3900:
3084 {
3085   do_srl (SD_, RT, RD, SHIFT);
3086 }
3087
3088
3089 :function:::void:do_srlv:int rs, int rt, int rd
3090 {
3091   int s = MASKED (GPR[rs], 4, 0);
3092   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3093   if (NotWordValue (GPR[rt]))
3094     Unpredictable ();
3095   TRACE_ALU_INPUT2 (GPR[rt], s);
3096   GPR[rd] = EXTEND32 (temp);
3097   TRACE_ALU_RESULT (GPR[rd]);
3098 }
3099
3100 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3101 "srlv r<RD>, r<RT>, r<RS>"
3102 *mipsI:
3103 *mipsII:
3104 *mipsIII:
3105 *mipsIV:
3106 *mipsV:
3107 *mips32:
3108 *mips64:
3109 *vr4100:
3110 *vr5000:
3111 *r3900:
3112 {
3113   do_srlv (SD_, RS, RT, RD);
3114 }
3115
3116
3117 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3118 "sub r<RD>, r<RS>, r<RT>"
3119 *mipsI:
3120 *mipsII:
3121 *mipsIII:
3122 *mipsIV:
3123 *mipsV:
3124 *mips32:
3125 *mips64:
3126 *vr4100:
3127 *vr5000:
3128 *r3900:
3129 {
3130   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3131     Unpredictable ();
3132   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3133   {
3134     ALU32_BEGIN (GPR[RS]);
3135     ALU32_SUB (GPR[RT]);
3136     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3137   }
3138   TRACE_ALU_RESULT (GPR[RD]);
3139 }
3140
3141
3142 :function:::void:do_subu:int rs, int rt, int rd
3143 {
3144   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3145     Unpredictable ();
3146   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3147   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3148   TRACE_ALU_RESULT (GPR[rd]);
3149 }
3150
3151 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3152 "subu r<RD>, r<RS>, r<RT>"
3153 *mipsI:
3154 *mipsII:
3155 *mipsIII:
3156 *mipsIV:
3157 *mipsV:
3158 *mips32:
3159 *mips64:
3160 *vr4100:
3161 *vr5000:
3162 *r3900:
3163 {
3164   do_subu (SD_, RS, RT, RD);
3165 }
3166
3167
3168 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3169 "sw r<RT>, <OFFSET>(r<BASE>)"
3170 *mipsI:
3171 *mipsII:
3172 *mipsIII:
3173 *mipsIV:
3174 *mipsV:
3175 *mips32:
3176 *mips64:
3177 *vr4100:
3178 *r3900:
3179 *vr5000:
3180 {
3181   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3182 }
3183
3184
3185 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3186 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3187 *mipsI:
3188 *mipsII:
3189 *mipsIII:
3190 *mipsIV:
3191 *mipsV:
3192 *mips32:
3193 *mips64:
3194 *vr4100:
3195 *vr5000:
3196 *r3900:
3197 {
3198   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3199 }
3200
3201
3202 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3203 "swl r<RT>, <OFFSET>(r<BASE>)"
3204 *mipsI:
3205 *mipsII:
3206 *mipsIII:
3207 *mipsIV:
3208 *mipsV:
3209 *mips32:
3210 *mips64:
3211 *vr4100:
3212 *vr5000:
3213 *r3900:
3214 {
3215   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3216 }
3217
3218
3219 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3220 "swr r<RT>, <OFFSET>(r<BASE>)"
3221 *mipsI:
3222 *mipsII:
3223 *mipsIII:
3224 *mipsIV:
3225 *mipsV:
3226 *mips32:
3227 *mips64:
3228 *vr4100:
3229 *vr5000:
3230 *r3900:
3231 {
3232   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3233 }
3234
3235
3236 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3237 "sync":STYPE == 0
3238 "sync <STYPE>"
3239 *mipsII:
3240 *mipsIII:
3241 *mipsIV:
3242 *mipsV:
3243 *mips32:
3244 *mips64:
3245 *vr4100:
3246 *vr5000:
3247 *r3900:
3248 {
3249   SyncOperation (STYPE);
3250 }
3251
3252
3253 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3254 "syscall %#lx<CODE>"
3255 *mipsI:
3256 *mipsII:
3257 *mipsIII:
3258 *mipsIV:
3259 *mipsV:
3260 *mips32:
3261 *mips64:
3262 *vr4100:
3263 *vr5000:
3264 *r3900:
3265 {
3266   SignalException (SystemCall, instruction_0);
3267 }
3268
3269
3270 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3271 "teq r<RS>, r<RT>"
3272 *mipsII:
3273 *mipsIII:
3274 *mipsIV:
3275 *mipsV:
3276 *mips32:
3277 *mips64:
3278 *vr4100:
3279 *vr5000:
3280 {
3281   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3282     SignalException (Trap, instruction_0);
3283 }
3284
3285
3286 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3287 "teqi r<RS>, <IMMEDIATE>"
3288 *mipsII:
3289 *mipsIII:
3290 *mipsIV:
3291 *mipsV:
3292 *mips32:
3293 *mips64:
3294 *vr4100:
3295 *vr5000:
3296 {
3297   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3298     SignalException (Trap, instruction_0);
3299 }
3300
3301
3302 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3303 "tge r<RS>, r<RT>"
3304 *mipsII:
3305 *mipsIII:
3306 *mipsIV:
3307 *mipsV:
3308 *mips32:
3309 *mips64:
3310 *vr4100:
3311 *vr5000:
3312 {
3313   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3314     SignalException (Trap, instruction_0);
3315 }
3316
3317
3318 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3319 "tgei r<RS>, <IMMEDIATE>"
3320 *mipsII:
3321 *mipsIII:
3322 *mipsIV:
3323 *mipsV:
3324 *mips32:
3325 *mips64:
3326 *vr4100:
3327 *vr5000:
3328 {
3329   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3330     SignalException (Trap, instruction_0);
3331 }
3332
3333
3334 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3335 "tgeiu r<RS>, <IMMEDIATE>"
3336 *mipsII:
3337 *mipsIII:
3338 *mipsIV:
3339 *mipsV:
3340 *mips32:
3341 *mips64:
3342 *vr4100:
3343 *vr5000:
3344 {
3345   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3346     SignalException (Trap, instruction_0);
3347 }
3348
3349
3350 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3351 "tgeu r<RS>, r<RT>"
3352 *mipsII:
3353 *mipsIII:
3354 *mipsIV:
3355 *mipsV:
3356 *mips32:
3357 *mips64:
3358 *vr4100:
3359 *vr5000:
3360 {
3361   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3362     SignalException (Trap, instruction_0);
3363 }
3364
3365
3366 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3367 "tlt r<RS>, r<RT>"
3368 *mipsII:
3369 *mipsIII:
3370 *mipsIV:
3371 *mipsV:
3372 *mips32:
3373 *mips64:
3374 *vr4100:
3375 *vr5000:
3376 {
3377   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3378     SignalException (Trap, instruction_0);
3379 }
3380
3381
3382 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3383 "tlti r<RS>, <IMMEDIATE>"
3384 *mipsII:
3385 *mipsIII:
3386 *mipsIV:
3387 *mipsV:
3388 *mips32:
3389 *mips64:
3390 *vr4100:
3391 *vr5000:
3392 {
3393   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3394     SignalException (Trap, instruction_0);
3395 }
3396
3397
3398 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3399 "tltiu r<RS>, <IMMEDIATE>"
3400 *mipsII:
3401 *mipsIII:
3402 *mipsIV:
3403 *mipsV:
3404 *mips32:
3405 *mips64:
3406 *vr4100:
3407 *vr5000:
3408 {
3409   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3410     SignalException (Trap, instruction_0);
3411 }
3412
3413
3414 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3415 "tltu r<RS>, r<RT>"
3416 *mipsII:
3417 *mipsIII:
3418 *mipsIV:
3419 *mipsV:
3420 *mips32:
3421 *mips64:
3422 *vr4100:
3423 *vr5000:
3424 {
3425   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3426     SignalException (Trap, instruction_0);
3427 }
3428
3429
3430 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3431 "tne r<RS>, r<RT>"
3432 *mipsII:
3433 *mipsIII:
3434 *mipsIV:
3435 *mipsV:
3436 *mips32:
3437 *mips64:
3438 *vr4100:
3439 *vr5000:
3440 {
3441   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3442     SignalException (Trap, instruction_0);
3443 }
3444
3445
3446 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3447 "tnei r<RS>, <IMMEDIATE>"
3448 *mipsII:
3449 *mipsIII:
3450 *mipsIV:
3451 *mipsV:
3452 *mips32:
3453 *mips64:
3454 *vr4100:
3455 *vr5000:
3456 {
3457   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3458     SignalException (Trap, instruction_0);
3459 }
3460
3461
3462 :function:::void:do_xor:int rs, int rt, int rd
3463 {
3464   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3465   GPR[rd] = GPR[rs] ^ GPR[rt];
3466   TRACE_ALU_RESULT (GPR[rd]);
3467 }
3468
3469 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3470 "xor r<RD>, r<RS>, r<RT>"
3471 *mipsI:
3472 *mipsII:
3473 *mipsIII:
3474 *mipsIV:
3475 *mipsV:
3476 *mips32:
3477 *mips64:
3478 *vr4100:
3479 *vr5000:
3480 *r3900:
3481 {
3482   do_xor (SD_, RS, RT, RD);
3483 }
3484
3485
3486 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3487 {
3488   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3489   GPR[rt] = GPR[rs] ^ immediate;
3490   TRACE_ALU_RESULT (GPR[rt]);
3491 }
3492
3493 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3494 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3495 *mipsI:
3496 *mipsII:
3497 *mipsIII:
3498 *mipsIV:
3499 *mipsV:
3500 *mips32:
3501 *mips64:
3502 *vr4100:
3503 *vr5000:
3504 *r3900:
3505 {
3506   do_xori (SD_, RS, RT, IMMEDIATE);
3507 }
3508
3509 \f
3510 //
3511 // MIPS Architecture:
3512 //
3513 //        FPU Instruction Set (COP1 & COP1X)
3514 //
3515
3516
3517 :%s::::FMT:int fmt
3518 {
3519   switch (fmt)
3520     {
3521     case fmt_single: return "s";
3522     case fmt_double: return "d";
3523     case fmt_word: return "w";
3524     case fmt_long: return "l";
3525     case fmt_ps: return "ps";
3526     default: return "?";
3527     }
3528 }
3529
3530 :%s::::TF:int tf
3531 {
3532   if (tf)
3533     return "t";
3534   else
3535     return "f";
3536 }
3537
3538 :%s::::ND:int nd
3539 {
3540   if (nd)
3541     return "l";
3542   else
3543     return "";
3544 }
3545
3546 :%s::::COND:int cond
3547 {
3548   switch (cond)
3549     {
3550     case 00: return "f";
3551     case 01: return "un";
3552     case 02: return "eq";
3553     case 03: return "ueq";
3554     case 04: return "olt";
3555     case 05: return "ult";
3556     case 06: return "ole";
3557     case 07: return "ule";
3558     case 010: return "sf";
3559     case 011: return "ngle";
3560     case 012: return "seq";
3561     case 013: return "ngl";
3562     case 014: return "lt";
3563     case 015: return "nge";
3564     case 016: return "le";
3565     case 017: return "ngt";
3566     default: return "?";
3567     }
3568 }
3569
3570
3571 // Helpers:
3572 //
3573 // Check that the given FPU format is usable, and signal a
3574 // ReservedInstruction exception if not.
3575 //
3576
3577 // check_fmt checks that the format is single or double.
3578 :function:::void:check_fmt:int fmt, instruction_word insn
3579 *mipsI:
3580 *mipsII:
3581 *mipsIII:
3582 *mipsIV:
3583 *mipsV:
3584 *mips32:
3585 *mips64:
3586 *vr4100:
3587 *vr5000:
3588 *r3900:
3589 {
3590   if ((fmt != fmt_single) && (fmt != fmt_double))
3591     SignalException (ReservedInstruction, insn);
3592 }
3593
3594 // check_fmt_p checks that the format is single, double, or paired single.
3595 :function:::void:check_fmt_p:int fmt, instruction_word insn
3596 *mipsI:
3597 *mipsII:
3598 *mipsIII:
3599 *mipsIV:
3600 *mips32:
3601 *vr4100:
3602 *vr5000:
3603 *r3900:
3604 {
3605   /* None of these ISAs support Paired Single, so just fall back to
3606      the single/double check.  */
3607   check_fmt (SD_, fmt, insn);
3608 }
3609
3610 :function:::void:check_fmt_p:int fmt, instruction_word insn
3611 *mipsV:
3612 *mips64:
3613 {
3614   if ((fmt != fmt_single) && (fmt != fmt_double)
3615       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3616     SignalException (ReservedInstruction, insn);
3617 }
3618
3619
3620 // Helper:
3621 //
3622 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3623 // exception if not.
3624 //
3625
3626 :function:::void:check_fpu:
3627 *mipsI:
3628 *mipsII:
3629 *mipsIII:
3630 *mipsIV:
3631 *mipsV:
3632 *mips32:
3633 *mips64:
3634 *vr4100:
3635 *vr5000:
3636 *r3900:
3637 {
3638   if (! COP_Usable (1))
3639     SignalExceptionCoProcessorUnusable (1);
3640 }
3641
3642
3643 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3644 "abs.%s<FMT> f<FD>, f<FS>"
3645 *mipsI:
3646 *mipsII:
3647 *mipsIII:
3648 *mipsIV:
3649 *mipsV:
3650 *mips32:
3651 *mips64:
3652 *vr4100:
3653 *vr5000:
3654 *r3900:
3655 {
3656   int fmt = FMT;
3657   check_fpu (SD_);
3658   check_fmt_p (SD_, fmt, instruction_0);
3659   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
3660 }
3661
3662
3663
3664 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3665 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3666 *mipsI:
3667 *mipsII:
3668 *mipsIII:
3669 *mipsIV:
3670 *mipsV:
3671 *mips32:
3672 *mips64:
3673 *vr4100:
3674 *vr5000:
3675 *r3900:
3676 {
3677   int fmt = FMT;
3678   check_fpu (SD_);
3679   check_fmt_p (SD_, fmt, instruction_0);
3680   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
3681 }
3682
3683
3684 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
3685 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
3686 *mipsV:
3687 *mips64:
3688 {
3689   unsigned64 fs;
3690   unsigned64 ft;
3691   unsigned64 fd;
3692   check_fpu (SD_);
3693   check_u64 (SD_, instruction_0);
3694   fs = ValueFPR (FS, fmt_ps);
3695   if ((GPR[RS] & 0x3) != 0)
3696     Unpredictable ();
3697   if ((GPR[RS] & 0x4) == 0)
3698     fd = fs;
3699   else
3700     {
3701       ft = ValueFPR (FT, fmt_ps);
3702       if (BigEndianCPU)
3703         fd = PackPS (PSLower (fs), PSUpper (ft));
3704       else
3705         fd = PackPS (PSLower (ft), PSUpper (fs));
3706     }
3707   StoreFPR (FD, fmt_ps, fd);
3708 }
3709
3710
3711 // BC1F
3712 // BC1FL
3713 // BC1T
3714 // BC1TL
3715
3716 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3717 "bc1%s<TF>%s<ND> <OFFSET>"
3718 *mipsI:
3719 *mipsII:
3720 *mipsIII:
3721 {
3722   check_fpu (SD_);
3723   check_branch_bug ();
3724   TRACE_BRANCH_INPUT (PREVCOC1());
3725   if (PREVCOC1() == TF)
3726     {
3727       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3728       TRACE_BRANCH_RESULT (dest);
3729       mark_branch_bug (dest);
3730       DELAY_SLOT (dest);
3731     }
3732   else if (ND)
3733     {
3734       TRACE_BRANCH_RESULT (0);
3735       NULLIFY_NEXT_INSTRUCTION ();
3736     }
3737   else
3738     {
3739       TRACE_BRANCH_RESULT (NIA);
3740     }
3741 }
3742
3743 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3744 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3745 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3746 *mipsIV:
3747 *mipsV:
3748 *mips32:
3749 *mips64:
3750 #*vr4100:
3751 *vr5000:
3752 *r3900:
3753 {
3754   check_fpu (SD_);
3755   check_branch_bug ();
3756   if (GETFCC(CC) == TF)
3757     {
3758       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3759       mark_branch_bug (dest);
3760       DELAY_SLOT (dest);
3761     }
3762   else if (ND)
3763     {
3764       NULLIFY_NEXT_INSTRUCTION ();
3765     }
3766 }
3767
3768
3769 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3770 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3771 *mipsI:
3772 *mipsII:
3773 *mipsIII:
3774 {
3775   int fmt = FMT;
3776   check_fpu (SD_);
3777   check_fmt_p (SD_, fmt, instruction_0);
3778   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
3779   TRACE_ALU_RESULT (ValueFCR (31));
3780 }
3781
3782 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3783 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3784 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3785 *mipsIV:
3786 *mipsV:
3787 *mips32:
3788 *mips64:
3789 *vr4100:
3790 *vr5000:
3791 *r3900:
3792 {
3793   int fmt = FMT;
3794   check_fpu (SD_);
3795   check_fmt_p (SD_, fmt, instruction_0);
3796   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
3797   TRACE_ALU_RESULT (ValueFCR (31));
3798 }
3799
3800
3801 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3802 "ceil.l.%s<FMT> f<FD>, f<FS>"
3803 *mipsIII:
3804 *mipsIV:
3805 *mipsV:
3806 *mips64:
3807 *vr4100:
3808 *vr5000:
3809 *r3900:
3810 {
3811   int fmt = FMT;
3812   check_fpu (SD_);
3813   check_fmt (SD_, fmt, instruction_0);
3814   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3815             fmt_long));
3816 }
3817
3818
3819 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3820 "ceil.w.%s<FMT> f<FD>, f<FS>"
3821 *mipsII:
3822 *mipsIII:
3823 *mipsIV:
3824 *mipsV:
3825 *mips32:
3826 *mips64:
3827 *vr4100:
3828 *vr5000:
3829 *r3900:
3830 {
3831   int fmt = FMT;
3832   check_fpu (SD_);
3833   check_fmt (SD_, fmt, instruction_0);
3834   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3835             fmt_word));
3836 }
3837
3838
3839 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
3840 "cfc1 r<RT>, f<FS>"
3841 *mipsI:
3842 *mipsII:
3843 *mipsIII:
3844 {
3845   check_fpu (SD_);
3846   if (FS == 0)
3847     PENDING_FILL (RT, EXTEND32 (FCR0));
3848   else if (FS == 31)
3849     PENDING_FILL (RT, EXTEND32 (FCR31));
3850   /* else NOP */
3851 }
3852
3853 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
3854 "cfc1 r<RT>, f<FS>"
3855 *mipsIV:
3856 *vr4100:
3857 *vr5000:
3858 *r3900:
3859 {
3860   check_fpu (SD_);
3861   if (FS == 0 || FS == 31)
3862     {
3863       unsigned_word  fcr = ValueFCR (FS);
3864       TRACE_ALU_INPUT1 (fcr);
3865       GPR[RT] = fcr;
3866     }
3867   /* else NOP */
3868   TRACE_ALU_RESULT (GPR[RT]);
3869 }
3870
3871 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
3872 "cfc1 r<RT>, f<FS>"
3873 *mipsV:
3874 *mips32:
3875 *mips64:
3876 {
3877   check_fpu (SD_);
3878   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
3879     {
3880       unsigned_word  fcr = ValueFCR (FS);
3881       TRACE_ALU_INPUT1 (fcr);
3882       GPR[RT] = fcr;
3883     }
3884   /* else NOP */
3885   TRACE_ALU_RESULT (GPR[RT]);
3886 }
3887
3888 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
3889 "ctc1 r<RT>, f<FS>"
3890 *mipsI:
3891 *mipsII:
3892 *mipsIII:
3893 {
3894   check_fpu (SD_);
3895   if (FS == 31)
3896     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
3897   /* else NOP */
3898 }
3899
3900 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
3901 "ctc1 r<RT>, f<FS>"
3902 *mipsIV:
3903 *vr4100:
3904 *vr5000:
3905 *r3900:
3906 {
3907   check_fpu (SD_);
3908   TRACE_ALU_INPUT1 (GPR[RT]);
3909   if (FS == 31)
3910     StoreFCR (FS, GPR[RT]);
3911   /* else NOP */
3912 }
3913
3914 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
3915 "ctc1 r<RT>, f<FS>"
3916 *mipsV:
3917 *mips32:
3918 *mips64:
3919 {
3920   check_fpu (SD_);
3921   TRACE_ALU_INPUT1 (GPR[RT]);
3922   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
3923       StoreFCR (FS, GPR[RT]);
3924   /* else NOP */
3925 }
3926
3927
3928 //
3929 // FIXME: Does not correctly differentiate between mips*
3930 //
3931 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3932 "cvt.d.%s<FMT> f<FD>, f<FS>"
3933 *mipsI:
3934 *mipsII:
3935 *mipsIII:
3936 *mipsIV:
3937 *mipsV:
3938 *mips32:
3939 *mips64:
3940 *vr4100:
3941 *vr5000:
3942 *r3900:
3943 {
3944   int fmt = FMT;
3945   check_fpu (SD_);
3946   if ((fmt == fmt_double) | 0)
3947     SignalException (ReservedInstruction, instruction_0);
3948   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
3949             fmt_double));
3950 }
3951
3952
3953 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3954 "cvt.l.%s<FMT> f<FD>, f<FS>"
3955 *mipsIII:
3956 *mipsIV:
3957 *mipsV:
3958 *mips64:
3959 *vr4100:
3960 *vr5000:
3961 *r3900:
3962 {
3963   int fmt = FMT;
3964   check_fpu (SD_);
3965   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3966     SignalException (ReservedInstruction, instruction_0);
3967   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
3968             fmt_long));
3969 }
3970
3971
3972 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
3973 "cvt.ps.s f<FD>, f<FS>, f<FT>"
3974 *mipsV:
3975 *mips64:
3976 {
3977   check_fpu (SD_);
3978   check_u64 (SD_, instruction_0);
3979   StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
3980                                 ValueFPR (FT, fmt_single)));
3981 }
3982
3983
3984 //
3985 // FIXME: Does not correctly differentiate between mips*
3986 //
3987 010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3988 "cvt.s.%s<FMT> f<FD>, f<FS>"
3989 *mipsI:
3990 *mipsII:
3991 *mipsIII:
3992 *mipsIV:
3993 *mipsV:
3994 *mips32:
3995 *mips64:
3996 *vr4100:
3997 *vr5000:
3998 *r3900:
3999 {
4000   int fmt = FMT;
4001   check_fpu (SD_);
4002   if ((fmt == fmt_single) | 0)
4003     SignalException (ReservedInstruction, instruction_0);
4004   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4005             fmt_single));
4006 }
4007
4008
4009 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4010 "cvt.s.pl f<FD>, f<FS>"
4011 *mipsV:
4012 *mips64:
4013 {
4014   check_fpu (SD_);
4015   check_u64 (SD_, instruction_0);
4016   StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4017 }
4018
4019
4020 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4021 "cvt.s.pu f<FD>, f<FS>"
4022 *mipsV:
4023 *mips64:
4024 {
4025   check_fpu (SD_);
4026   check_u64 (SD_, instruction_0);
4027   StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4028 }
4029
4030
4031 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4032 "cvt.w.%s<FMT> f<FD>, f<FS>"
4033 *mipsI:
4034 *mipsII:
4035 *mipsIII:
4036 *mipsIV:
4037 *mipsV:
4038 *mips32:
4039 *mips64:
4040 *vr4100:
4041 *vr5000:
4042 *r3900:
4043 {
4044   int fmt = FMT;
4045   check_fpu (SD_);
4046   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4047     SignalException (ReservedInstruction, instruction_0);
4048   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4049             fmt_word));
4050 }
4051
4052
4053 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4054 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4055 *mipsI:
4056 *mipsII:
4057 *mipsIII:
4058 *mipsIV:
4059 *mipsV:
4060 *mips32:
4061 *mips64:
4062 *vr4100:
4063 *vr5000:
4064 *r3900:
4065 {
4066   int fmt = FMT;
4067   check_fpu (SD_);
4068   check_fmt (SD_, fmt, instruction_0);
4069   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4070 }
4071
4072
4073 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4074 "dmfc1 r<RT>, f<FS>"
4075 *mipsIII:
4076 {
4077   unsigned64 v;
4078   check_fpu (SD_);
4079   check_u64 (SD_, instruction_0);
4080   if (SizeFGR () == 64)
4081     v = FGR[FS];
4082   else if ((FS & 0x1) == 0)
4083     v = SET64HI (FGR[FS+1]) | FGR[FS];
4084   else
4085     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4086   PENDING_FILL (RT, v);
4087   TRACE_ALU_RESULT (v);
4088 }
4089
4090 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4091 "dmfc1 r<RT>, f<FS>"
4092 *mipsIV:
4093 *mipsV:
4094 *mips64:
4095 *vr4100:
4096 *vr5000:
4097 *r3900:
4098 {
4099   check_fpu (SD_);
4100   check_u64 (SD_, instruction_0);
4101   if (SizeFGR () == 64)
4102     GPR[RT] = FGR[FS];
4103   else if ((FS & 0x1) == 0)
4104     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4105   else
4106     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4107   TRACE_ALU_RESULT (GPR[RT]);
4108 }
4109
4110
4111 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4112 "dmtc1 r<RT>, f<FS>"
4113 *mipsIII:
4114 {
4115   unsigned64 v;
4116   check_fpu (SD_);
4117   check_u64 (SD_, instruction_0);
4118   if (SizeFGR () == 64)
4119     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4120   else if ((FS & 0x1) == 0)
4121     {
4122       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4123       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4124     }
4125   else
4126     Unpredictable ();
4127   TRACE_FP_RESULT (GPR[RT]);
4128 }
4129
4130 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4131 "dmtc1 r<RT>, f<FS>"
4132 *mipsIV:
4133 *mipsV:
4134 *mips64:
4135 *vr4100:
4136 *vr5000:
4137 *r3900:
4138 {
4139   check_fpu (SD_);
4140   check_u64 (SD_, instruction_0);
4141   if (SizeFGR () == 64)
4142     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4143   else if ((FS & 0x1) == 0)
4144     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4145   else
4146     Unpredictable ();
4147 }
4148
4149
4150 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4151 "floor.l.%s<FMT> f<FD>, f<FS>"
4152 *mipsIII:
4153 *mipsIV:
4154 *mipsV:
4155 *mips64:
4156 *vr4100:
4157 *vr5000:
4158 *r3900:
4159 {
4160   int fmt = FMT;
4161   check_fpu (SD_);
4162   check_fmt (SD_, fmt, instruction_0);
4163   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4164             fmt_long));
4165 }
4166
4167
4168 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4169 "floor.w.%s<FMT> f<FD>, f<FS>"
4170 *mipsII:
4171 *mipsIII:
4172 *mipsIV:
4173 *mipsV:
4174 *mips32:
4175 *mips64:
4176 *vr4100:
4177 *vr5000:
4178 *r3900:
4179 {
4180   int fmt = FMT;
4181   check_fpu (SD_);
4182   check_fmt (SD_, fmt, instruction_0);
4183   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4184             fmt_word));
4185 }
4186
4187
4188 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
4189 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4190 *mipsII:
4191 *mipsIII:
4192 *mipsIV:
4193 *mipsV:
4194 *mips32:
4195 *mips64:
4196 *vr4100:
4197 *vr5000:
4198 *r3900:
4199 {
4200   check_fpu (SD_);
4201   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4202 }
4203
4204
4205 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4206 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4207 *mipsIV:
4208 *mipsV:
4209 *mips64:
4210 *vr5000:
4211 {
4212   check_fpu (SD_);
4213   check_u64 (SD_, instruction_0);
4214   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4215 }
4216
4217
4218
4219 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4220 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4221 *mipsI:
4222 *mipsII:
4223 *mipsIII:
4224 *mipsIV:
4225 *mipsV:
4226 *mips32:
4227 *mips64:
4228 *vr4100:
4229 *vr5000:
4230 *r3900:
4231 {
4232   check_fpu (SD_);
4233   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4234 }
4235
4236
4237 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4238 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4239 *mipsIV:
4240 *mipsV:
4241 *mips64:
4242 *vr5000:
4243 {
4244   check_fpu (SD_);
4245   check_u64 (SD_, instruction_0);
4246   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4247 }
4248
4249
4250
4251 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
4252 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4253 *mipsIV:
4254 *mipsV:
4255 *mips64:
4256 *vr5000:
4257 {
4258   int fmt = FMT;
4259   check_fpu (SD_);
4260   check_u64 (SD_, instruction_0);
4261   check_fmt_p (SD_, fmt, instruction_0);
4262   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4263                                   ValueFPR (FR, fmt), fmt));
4264 }
4265
4266
4267 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4268 "mfc1 r<RT>, f<FS>"
4269 *mipsI:
4270 *mipsII:
4271 *mipsIII:
4272 {
4273   unsigned64 v;
4274   check_fpu (SD_);
4275   v = EXTEND32 (FGR[FS]);
4276   PENDING_FILL (RT, v);
4277   TRACE_ALU_RESULT (v);
4278 }
4279
4280 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4281 "mfc1 r<RT>, f<FS>"
4282 *mipsIV:
4283 *mipsV:
4284 *mips32:
4285 *mips64:
4286 *vr4100:
4287 *vr5000:
4288 *r3900:
4289 {
4290   check_fpu (SD_);
4291   GPR[RT] = EXTEND32 (FGR[FS]);
4292   TRACE_ALU_RESULT (GPR[RT]);
4293 }
4294
4295
4296 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4297 "mov.%s<FMT> f<FD>, f<FS>"
4298 *mipsI:
4299 *mipsII:
4300 *mipsIII:
4301 *mipsIV:
4302 *mipsV:
4303 *mips32:
4304 *mips64:
4305 *vr4100:
4306 *vr5000:
4307 *r3900:
4308 {
4309   int fmt = FMT;
4310   check_fpu (SD_);
4311   check_fmt_p (SD_, fmt, instruction_0);
4312   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4313 }
4314
4315
4316 // MOVF
4317 // MOVT
4318 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4319 "mov%s<TF> r<RD>, r<RS>, <CC>"
4320 *mipsIV:
4321 *mipsV:
4322 *mips32:
4323 *mips64:
4324 *vr5000:
4325 {
4326   check_fpu (SD_);
4327   if (GETFCC(CC) == TF)
4328     GPR[RD] = GPR[RS];
4329 }
4330
4331
4332 // MOVF.fmt
4333 // MOVT.fmt
4334 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4335 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4336 *mipsIV:
4337 *mipsV:
4338 *mips32:
4339 *mips64:
4340 *vr5000:
4341 {
4342   int fmt = FMT;
4343   check_fpu (SD_);
4344   if (fmt != fmt_ps)
4345     {
4346       if (GETFCC(CC) == TF)
4347         StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4348       else
4349         StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
4350     }
4351   else
4352     {
4353       unsigned64 fd;
4354       fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4355                                       fmt_ps)),
4356                    PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4357                                       fmt_ps)));
4358       StoreFPR (FD, fmt_ps, fd);
4359     }
4360 }
4361
4362
4363 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4364 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4365 *mipsIV:
4366 *mipsV:
4367 *mips32:
4368 *mips64:
4369 *vr5000:
4370 {
4371   check_fpu (SD_);
4372   if (GPR[RT] != 0)
4373     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4374   else
4375     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4376 }
4377
4378
4379 // MOVT see MOVtf
4380
4381
4382 // MOVT.fmt see MOVtf.fmt
4383
4384
4385
4386 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4387 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4388 *mipsIV:
4389 *mipsV:
4390 *mips32:
4391 *mips64:
4392 *vr5000:
4393 {
4394   check_fpu (SD_);
4395   if (GPR[RT] == 0)
4396     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4397   else
4398     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4399 }
4400
4401
4402 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
4403 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4404 *mipsIV:
4405 *mipsV:
4406 *mips64:
4407 *vr5000:
4408 {
4409   int fmt = FMT;
4410   check_fpu (SD_);
4411   check_u64 (SD_, instruction_0);
4412   check_fmt_p (SD_, fmt, instruction_0);
4413   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4414                                   ValueFPR (FR, fmt), fmt));
4415 }
4416
4417
4418 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4419 "mtc1 r<RT>, f<FS>"
4420 *mipsI:
4421 *mipsII:
4422 *mipsIII:
4423 {
4424   check_fpu (SD_);
4425   if (SizeFGR () == 64)
4426     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4427   else
4428     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4429   TRACE_FP_RESULT (GPR[RT]);
4430 }
4431
4432 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4433 "mtc1 r<RT>, f<FS>"
4434 *mipsIV:
4435 *mipsV:
4436 *mips32:
4437 *mips64:
4438 *vr4100:
4439 *vr5000:
4440 *r3900:
4441 {
4442   check_fpu (SD_);
4443   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4444 }
4445
4446
4447 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4448 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4449 *mipsI:
4450 *mipsII:
4451 *mipsIII:
4452 *mipsIV:
4453 *mipsV:
4454 *mips32:
4455 *mips64:
4456 *vr4100:
4457 *vr5000:
4458 *r3900:
4459 {
4460   int fmt = FMT;
4461   check_fpu (SD_);
4462   check_fmt_p (SD_, fmt, instruction_0);
4463   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4464 }
4465
4466
4467 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4468 "neg.%s<FMT> f<FD>, f<FS>"
4469 *mipsI:
4470 *mipsII:
4471 *mipsIII:
4472 *mipsIV:
4473 *mipsV:
4474 *mips32:
4475 *mips64:
4476 *vr4100:
4477 *vr5000:
4478 *r3900:
4479 {
4480   int fmt = FMT;
4481   check_fpu (SD_);
4482   check_fmt_p (SD_, fmt, instruction_0);
4483   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4484 }
4485
4486
4487 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
4488 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4489 *mipsIV:
4490 *mipsV:
4491 *mips64:
4492 *vr5000:
4493 {
4494   int fmt = FMT;
4495   check_fpu (SD_);
4496   check_u64 (SD_, instruction_0);
4497   check_fmt_p (SD_, fmt, instruction_0);
4498   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4499                                      ValueFPR (FR, fmt), fmt));
4500 }
4501
4502
4503 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
4504 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4505 *mipsIV:
4506 *mipsV:
4507 *mips64:
4508 *vr5000:
4509 {
4510   int fmt = FMT;
4511   check_fpu (SD_);
4512   check_u64 (SD_, instruction_0);
4513   check_fmt_p (SD_, fmt, instruction_0);
4514   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4515                                      ValueFPR (FR, fmt), fmt));
4516 }
4517
4518
4519 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
4520 "pll.ps f<FD>, f<FS>, f<FT>"
4521 *mipsV:
4522 *mips64:
4523 {
4524   check_fpu (SD_);
4525   check_u64 (SD_, instruction_0);
4526   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4527                                 PSLower (ValueFPR (FT, fmt_ps))));
4528 }
4529
4530
4531 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
4532 "plu.ps f<FD>, f<FS>, f<FT>"
4533 *mipsV:
4534 *mips64:
4535 {
4536   check_fpu (SD_);
4537   check_u64 (SD_, instruction_0);
4538   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4539                                 PSUpper (ValueFPR (FT, fmt_ps))));
4540 }
4541
4542
4543 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4544 "prefx <HINT>, r<INDEX>(r<BASE>)"
4545 *mipsIV:
4546 *mipsV:
4547 *mips64:
4548 *vr5000:
4549 {
4550   address_word base = GPR[BASE];
4551   address_word index = GPR[INDEX];
4552   {
4553     address_word vaddr = loadstore_ea (SD_, base, index);
4554     address_word paddr;
4555     int uncached;
4556     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4557       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4558   }
4559 }
4560
4561
4562 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
4563 "pul.ps f<FD>, f<FS>, f<FT>"
4564 *mipsV:
4565 *mips64:
4566 {
4567   check_fpu (SD_);
4568   check_u64 (SD_, instruction_0);
4569   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4570                                 PSLower (ValueFPR (FT, fmt_ps))));
4571 }
4572
4573
4574 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
4575 "puu.ps f<FD>, f<FS>, f<FT>"
4576 *mipsV:
4577 *mips64:
4578 {
4579   check_fpu (SD_);
4580   check_u64 (SD_, instruction_0);
4581   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4582                                 PSUpper (ValueFPR (FT, fmt_ps))));
4583 }
4584
4585
4586 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4587 "recip.%s<FMT> f<FD>, f<FS>"
4588 *mipsIV:
4589 *mipsV:
4590 *mips64:
4591 *vr5000:
4592 {
4593   int fmt = FMT;
4594   check_fpu (SD_);
4595   check_fmt (SD_, fmt, instruction_0);
4596   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
4597 }
4598
4599
4600 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4601 "round.l.%s<FMT> f<FD>, f<FS>"
4602 *mipsIII:
4603 *mipsIV:
4604 *mipsV:
4605 *mips64:
4606 *vr4100:
4607 *vr5000:
4608 *r3900:
4609 {
4610   int fmt = FMT;
4611   check_fpu (SD_);
4612   check_fmt (SD_, fmt, instruction_0);
4613   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4614             fmt_long));
4615 }
4616
4617
4618 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4619 "round.w.%s<FMT> f<FD>, f<FS>"
4620 *mipsII:
4621 *mipsIII:
4622 *mipsIV:
4623 *mipsV:
4624 *mips32:
4625 *mips64:
4626 *vr4100:
4627 *vr5000:
4628 *r3900:
4629 {
4630   int fmt = FMT;
4631   check_fpu (SD_);
4632   check_fmt (SD_, fmt, instruction_0);
4633   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4634             fmt_word));
4635 }
4636
4637
4638 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4639 "rsqrt.%s<FMT> f<FD>, f<FS>"
4640 *mipsIV:
4641 *mipsV:
4642 *mips64:
4643 *vr5000:
4644 {
4645   int fmt = FMT;
4646   check_fpu (SD_);
4647   check_fmt (SD_, fmt, instruction_0);
4648   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
4649 }
4650
4651
4652 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
4653 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4654 *mipsII:
4655 *mipsIII:
4656 *mipsIV:
4657 *mipsV:
4658 *mips32:
4659 *mips64:
4660 *vr4100:
4661 *vr5000:
4662 *r3900:
4663 {
4664   check_fpu (SD_);
4665   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4666 }
4667
4668
4669 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4670 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4671 *mipsIV:
4672 *mipsV:
4673 *mips64:
4674 *vr5000:
4675 {
4676   check_fpu (SD_);
4677   check_u64 (SD_, instruction_0);
4678   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4679 }
4680
4681
4682 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4683 "sqrt.%s<FMT> f<FD>, f<FS>"
4684 *mipsII:
4685 *mipsIII:
4686 *mipsIV:
4687 *mipsV:
4688 *mips32:
4689 *mips64:
4690 *vr4100:
4691 *vr5000:
4692 *r3900:
4693 {
4694   int fmt = FMT;
4695   check_fpu (SD_);
4696   check_fmt (SD_, fmt, instruction_0);
4697   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
4698 }
4699
4700
4701 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4702 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4703 *mipsI:
4704 *mipsII:
4705 *mipsIII:
4706 *mipsIV:
4707 *mipsV:
4708 *mips32:
4709 *mips64:
4710 *vr4100:
4711 *vr5000:
4712 *r3900:
4713 {
4714   int fmt = FMT;
4715   check_fpu (SD_);
4716   check_fmt_p (SD_, fmt, instruction_0);
4717   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4718 }
4719
4720
4721
4722 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4723 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4724 *mipsI:
4725 *mipsII:
4726 *mipsIII:
4727 *mipsIV:
4728 *mipsV:
4729 *mips32:
4730 *mips64:
4731 *vr4100:
4732 *vr5000:
4733 *r3900:
4734 {
4735   address_word base = GPR[BASE];
4736   address_word offset = EXTEND16 (OFFSET);
4737   check_fpu (SD_);
4738   {
4739     address_word vaddr = loadstore_ea (SD_, base, offset);
4740     address_word paddr;
4741     int uncached;
4742     if ((vaddr & 3) != 0)
4743       {
4744         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4745       }
4746     else
4747       {
4748         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4749           {
4750             uword64 memval = 0;
4751             uword64 memval1 = 0;
4752             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4753             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4754             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4755             unsigned int byte;
4756             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4757             byte = ((vaddr & mask) ^ bigendiancpu);
4758             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4759             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4760           }
4761       }
4762   }
4763 }
4764
4765
4766 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4767 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4768 *mipsIV:
4769 *mipsV:
4770 *mips64:
4771 *vr5000:
4772 {
4773
4774   address_word base = GPR[BASE];
4775   address_word index = GPR[INDEX];
4776   check_fpu (SD_);
4777   check_u64 (SD_, instruction_0);
4778   {
4779    address_word vaddr = loadstore_ea (SD_, base, index);
4780    address_word paddr;
4781    int uncached;
4782    if ((vaddr & 3) != 0)
4783      {
4784        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4785      }
4786    else
4787    {
4788     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4789     {
4790      unsigned64 memval = 0;
4791      unsigned64 memval1 = 0;
4792      unsigned64 mask = 0x7;
4793      unsigned int byte;
4794      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4795      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4796      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4797       {
4798        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4799       }
4800     }
4801    }
4802   }
4803 }
4804
4805
4806 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4807 "trunc.l.%s<FMT> f<FD>, f<FS>"
4808 *mipsIII:
4809 *mipsIV:
4810 *mipsV:
4811 *mips64:
4812 *vr4100:
4813 *vr5000:
4814 *r3900:
4815 {
4816   int fmt = FMT;
4817   check_fpu (SD_);
4818   check_fmt (SD_, fmt, instruction_0);
4819   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4820             fmt_long));
4821 }
4822
4823
4824 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4825 "trunc.w.%s<FMT> f<FD>, f<FS>"
4826 *mipsII:
4827 *mipsIII:
4828 *mipsIV:
4829 *mipsV:
4830 *mips32:
4831 *mips64:
4832 *vr4100:
4833 *vr5000:
4834 *r3900:
4835 {
4836   int fmt = FMT;
4837   check_fpu (SD_);
4838   check_fmt (SD_, fmt, instruction_0);
4839   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4840             fmt_word));
4841 }
4842
4843 \f
4844 //
4845 // MIPS Architecture:
4846 //
4847 //        System Control Instruction Set (COP0)
4848 //
4849
4850
4851 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4852 "bc0f <OFFSET>"
4853 *mipsI:
4854 *mipsII:
4855 *mipsIII:
4856 *mipsIV:
4857 *mipsV:
4858 *mips32:
4859 *mips64:
4860 *vr4100:
4861 *vr5000:
4862
4863 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4864 "bc0f <OFFSET>"
4865 // stub needed for eCos as tx39 hardware bug workaround
4866 *r3900:
4867 {
4868   /* do nothing */
4869 }
4870
4871
4872 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4873 "bc0fl <OFFSET>"
4874 *mipsI:
4875 *mipsII:
4876 *mipsIII:
4877 *mipsIV:
4878 *mipsV:
4879 *mips32:
4880 *mips64:
4881 *vr4100:
4882 *vr5000:
4883
4884
4885 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4886 "bc0t <OFFSET>"
4887 *mipsI:
4888 *mipsII:
4889 *mipsIII:
4890 *mipsIV:
4891 *mipsV:
4892 *mips32:
4893 *mips64:
4894 *vr4100:
4895
4896
4897 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4898 "bc0tl <OFFSET>"
4899 *mipsI:
4900 *mipsII:
4901 *mipsIII:
4902 *mipsIV:
4903 *mipsV:
4904 *mips32:
4905 *mips64:
4906 *vr4100:
4907 *vr5000:
4908
4909
4910 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4911 "cache <OP>, <OFFSET>(r<BASE>)"
4912 *mipsIII:
4913 *mipsIV:
4914 *mipsV:
4915 *mips32:
4916 *mips64:
4917 *vr4100:
4918 *vr5000:
4919 *r3900:
4920 {
4921   address_word base = GPR[BASE];
4922   address_word offset = EXTEND16 (OFFSET);
4923   {
4924     address_word vaddr = loadstore_ea (SD_, base, offset);
4925     address_word paddr;
4926     int uncached;
4927     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4928       CacheOp(OP,vaddr,paddr,instruction_0);
4929   }
4930 }
4931
4932
4933 010000,1,0000000000000000000,111001:COP0:32::DI
4934 "di"
4935 *mipsI:
4936 *mipsII:
4937 *mipsIII:
4938 *mipsIV:
4939 *mipsV:
4940 *vr4100:
4941 *vr5000:
4942
4943
4944 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4945 "dmfc0 r<RT>, r<RD>"
4946 *mipsIII:
4947 *mipsIV:
4948 *mipsV:
4949 *mips64:
4950 {
4951   check_u64 (SD_, instruction_0);
4952   DecodeCoproc (instruction_0);
4953 }
4954
4955
4956 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4957 "dmtc0 r<RT>, r<RD>"
4958 *mipsIII:
4959 *mipsIV:
4960 *mipsV:
4961 *mips64:
4962 {
4963   check_u64 (SD_, instruction_0);
4964   DecodeCoproc (instruction_0);
4965 }
4966
4967
4968 010000,1,0000000000000000000,111000:COP0:32::EI
4969 "ei"
4970 *mipsI:
4971 *mipsII:
4972 *mipsIII:
4973 *mipsIV:
4974 *mipsV:
4975 *mips64:
4976 *vr4100:
4977 *vr5000:
4978
4979
4980 010000,1,0000000000000000000,011000:COP0:32::ERET
4981 "eret"
4982 *mipsIII:
4983 *mipsIV:
4984 *mipsV:
4985 *mips32:
4986 *mips64:
4987 *vr4100:
4988 *vr5000:
4989 {
4990   if (SR & status_ERL)
4991     {
4992       /* Oops, not yet available */
4993       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4994       NIA = EPC;
4995       SR &= ~status_ERL;
4996     }
4997   else
4998     {
4999       NIA = EPC;
5000       SR &= ~status_EXL;
5001     }
5002 }
5003
5004
5005 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5006 "mfc0 r<RT>, r<RD> # <REGX>"
5007 *mipsI:
5008 *mipsII:
5009 *mipsIII:
5010 *mipsIV:
5011 *mipsV:
5012 *mips32:
5013 *mips64:
5014 *vr4100:
5015 *vr5000:
5016 *r3900:
5017 {
5018   TRACE_ALU_INPUT0 ();
5019   DecodeCoproc (instruction_0);
5020   TRACE_ALU_RESULT (GPR[RT]);
5021 }
5022
5023 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5024 "mtc0 r<RT>, r<RD> # <REGX>"
5025 *mipsI:
5026 *mipsII:
5027 *mipsIII:
5028 *mipsIV:
5029 *mipsV:
5030 *mips32:
5031 *mips64:
5032 *vr4100:
5033 *vr5000:
5034 *r3900:
5035 {
5036   DecodeCoproc (instruction_0);
5037 }
5038
5039
5040 010000,1,0000000000000000000,010000:COP0:32::RFE
5041 "rfe"
5042 *mipsI:
5043 *mipsII:
5044 *mipsIII:
5045 *mipsIV:
5046 *mipsV:
5047 *vr4100:
5048 *vr5000:
5049 *r3900:
5050 {
5051   DecodeCoproc (instruction_0);
5052 }
5053
5054
5055 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5056 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5057 *mipsI:
5058 *mipsII:
5059 *mipsIII:
5060 *mipsIV:
5061 *mipsV:
5062 *mips32:
5063 *mips64:
5064 *vr4100:
5065 *r3900:
5066 {
5067   DecodeCoproc (instruction_0);
5068 }
5069
5070
5071
5072 010000,1,0000000000000000000,001000:COP0:32::TLBP
5073 "tlbp"
5074 *mipsI:
5075 *mipsII:
5076 *mipsIII:
5077 *mipsIV:
5078 *mipsV:
5079 *mips32:
5080 *mips64:
5081 *vr4100:
5082 *vr5000:
5083
5084
5085 010000,1,0000000000000000000,000001:COP0:32::TLBR
5086 "tlbr"
5087 *mipsI:
5088 *mipsII:
5089 *mipsIII:
5090 *mipsIV:
5091 *mipsV:
5092 *mips32:
5093 *mips64:
5094 *vr4100:
5095 *vr5000:
5096
5097
5098 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5099 "tlbwi"
5100 *mipsI:
5101 *mipsII:
5102 *mipsIII:
5103 *mipsIV:
5104 *mipsV:
5105 *mips32:
5106 *mips64:
5107 *vr4100:
5108 *vr5000:
5109
5110
5111 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5112 "tlbwr"
5113 *mipsI:
5114 *mipsII:
5115 *mipsIII:
5116 *mipsIV:
5117 *mipsV:
5118 *mips32:
5119 *mips64:
5120 *vr4100:
5121 *vr5000:
5122
5123 \f
5124 :include:::m16.igen
5125 :include:::mdmx.igen
5126 :include:::sb1.igen
5127 :include:::tx.igen
5128 :include:::vr.igen
5129 \f