4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator are defined below.
35 // When placing models in the instruction descriptions, please place
36 // them one per line, in the order given here.
40 // Instructions and related functions for these models are included in
42 :model:::mipsI:mips3000:
43 :model:::mipsII:mips6000:
44 :model:::mipsIII:mips4000:
45 :model:::mipsIV:mips8000:
46 :model:::mipsV:mipsisaV:
47 :model:::mips32:mipsisa32:
48 :model:::mips64:mipsisa64:
52 // Standard MIPS ISA instructions used for these models are listed here,
53 // as are functions needed by those standard instructions. Instructions
54 // which are model-dependent and which are not in the standard MIPS ISAs
55 // (or which pre-date or use different encodings than the standard
56 // instructions) are (for the most part) in separate .igen files.
57 :model:::vr4100:mips4100: // vr.igen
58 :model:::vr4120:mips4120:
59 :model:::vr5000:mips5000:
60 :model:::vr5400:mips5400:
61 :model:::vr5500:mips5500:
62 :model:::r3900:mips3900: // tx.igen
64 // MIPS Application Specific Extensions (ASEs)
66 // Instructions for the ASEs are in separate .igen files.
67 // ASEs add instructions on to a base ISA.
68 :model:::mips16:mips16: // m16.igen (and m16.dc)
69 :model:::mips3d:mips3d: // mips3d.igen
70 :model:::mdmx:mdmx: // mdmx.igen
74 // Instructions specific to these extensions are in separate .igen files.
75 // Extensions add instructions on to a base ISA.
76 :model:::sb1:sb1: // sb1.igen
79 // Pseudo instructions known by IGEN
82 SignalException (ReservedInstruction, 0);
86 // Pseudo instructions known by interp.c
87 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
88 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
91 SignalException (ReservedInstruction, instruction_0);
98 // Simulate a 32 bit delayslot instruction
101 :function:::address_word:delayslot32:address_word target
103 instruction_word delay_insn;
104 sim_events_slip (SD, 1);
106 CIA = CIA + 4; /* NOTE not mips16 */
107 STATE |= simDELAYSLOT;
108 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
109 ENGINE_ISSUE_PREFIX_HOOK();
110 idecode_issue (CPU_, delay_insn, (CIA));
111 STATE &= ~simDELAYSLOT;
115 :function:::address_word:nullify_next_insn32:
117 sim_events_slip (SD, 1);
118 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
125 // Calculate an effective address given a base and an offset.
128 :function:::address_word:loadstore_ea:address_word base, address_word offset
139 return base + offset;
142 :function:::address_word:loadstore_ea:address_word base, address_word offset
145 #if 0 /* XXX FIXME: enable this only after some additional testing. */
146 /* If in user mode and UX is not set, use 32-bit compatibility effective
147 address computations as defined in the MIPS64 Architecture for
148 Programmers Volume III, Revision 0.95, section 4.9. */
149 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
150 == (ksu_user << status_KSU_shift))
151 return (address_word)((signed32)base + (signed32)offset);
153 return base + offset;
159 // Check that a 32-bit register value is properly sign-extended.
160 // (See NotWordValue in ISA spec.)
163 :function:::int:not_word_value:unsigned_word value
173 /* For historical simulator compatibility (until documentation is
174 found that makes these operations unpredictable on some of these
175 architectures), this check never returns true. */
179 :function:::int:not_word_value:unsigned_word value
182 /* On MIPS32, since registers are 32-bits, there's no check to be done. */
186 :function:::int:not_word_value:unsigned_word value
189 return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
195 // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
196 // theoretically portable code which invokes non-portable behaviour from
197 // running with no indication of the portability issue.
198 // (See definition of UNPREDICTABLE in ISA spec.)
201 :function:::void:unpredictable:
213 :function:::void:unpredictable:
217 unpredictable_action (CPU, CIA);
223 // Check that an access to a HI/LO register meets timing requirements
227 // OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
228 // makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
230 // The following restrictions exist for MIPS I - MIPS III:
232 // MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
233 // in between makes MF UNPREDICTABLE. (2)
235 // MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
236 // in between makes MF UNPREDICTABLE. (3)
238 // On the r3900, restriction (2) is not present, and restriction (3) is not
239 // present for multiplication.
241 // Unfortunately, there seems to be some confusion about whether the last
242 // two restrictions should apply to "MIPS IV" as well. One edition of
243 // the MIPS IV ISA says they do, but references in later ISA documents
244 // suggest they don't.
246 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
247 // these restrictions, while others, like the VR5500, don't. To accomodate
248 // such differences, the MIPS IV and MIPS V version of these helper functions
249 // use auxillary routines to determine whether the restriction applies.
253 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
254 // to check for restrictions (2) and (3) above.
256 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
258 if (history->mf.timestamp + 3 > time)
260 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
261 itable[MY_INDEX].name,
263 (long) history->mf.cia);
272 // Check for restriction (2) above (for ISAs/processors that have it),
273 // and record timestamps for restriction (1) above.
275 :function:::int:check_mt_hilo:hilo_history *history
282 signed64 time = sim_events_time (SD);
283 int ok = check_mf_cycles (SD_, history, time, "MT");
284 history->mt.timestamp = time;
285 history->mt.cia = CIA;
289 :function:::int:check_mt_hilo:hilo_history *history
293 signed64 time = sim_events_time (SD);
294 int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
295 || check_mf_cycles (SD_, history, time, "MT"));
296 history->mt.timestamp = time;
297 history->mt.cia = CIA;
301 :function:::int:check_mt_hilo:hilo_history *history
306 signed64 time = sim_events_time (SD);
307 history->mt.timestamp = time;
308 history->mt.cia = CIA;
315 // Check for restriction (1) above, and record timestamps for
316 // restriction (2) and (3) above.
318 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
330 signed64 time = sim_events_time (SD);
333 && peer->mt.timestamp > history->op.timestamp
334 && history->mt.timestamp < history->op.timestamp
335 && ! (history->mf.timestamp > history->op.timestamp
336 && history->mf.timestamp < peer->mt.timestamp)
337 && ! (peer->mf.timestamp > history->op.timestamp
338 && peer->mf.timestamp < peer->mt.timestamp))
340 /* The peer has been written to since the last OP yet we have
342 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
343 itable[MY_INDEX].name,
345 (long) history->op.cia,
346 (long) peer->mt.cia);
349 history->mf.timestamp = time;
350 history->mf.cia = CIA;
358 // Check for restriction (3) above (for ISAs/processors that have it)
359 // for MULT ops, and record timestamps for restriction (1) above.
361 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
368 signed64 time = sim_events_time (SD);
369 int ok = (check_mf_cycles (SD_, hi, time, "OP")
370 && check_mf_cycles (SD_, lo, time, "OP"));
371 hi->op.timestamp = time;
372 lo->op.timestamp = time;
378 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
382 signed64 time = sim_events_time (SD);
383 int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
384 || (check_mf_cycles (SD_, hi, time, "OP")
385 && check_mf_cycles (SD_, lo, time, "OP")));
386 hi->op.timestamp = time;
387 lo->op.timestamp = time;
393 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
398 /* FIXME: could record the fact that a stall occured if we want */
399 signed64 time = sim_events_time (SD);
400 hi->op.timestamp = time;
401 lo->op.timestamp = time;
410 // Check for restriction (3) above (for ISAs/processors that have it)
411 // for DIV ops, and record timestamps for restriction (1) above.
413 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
421 signed64 time = sim_events_time (SD);
422 int ok = (check_mf_cycles (SD_, hi, time, "OP")
423 && check_mf_cycles (SD_, lo, time, "OP"));
424 hi->op.timestamp = time;
425 lo->op.timestamp = time;
431 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
435 signed64 time = sim_events_time (SD);
436 int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
437 || (check_mf_cycles (SD_, hi, time, "OP")
438 && check_mf_cycles (SD_, lo, time, "OP")));
439 hi->op.timestamp = time;
440 lo->op.timestamp = time;
446 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
450 signed64 time = sim_events_time (SD);
451 hi->op.timestamp = time;
452 lo->op.timestamp = time;
461 // Check that the 64-bit instruction can currently be used, and signal
462 // a ReservedInstruction exception if not.
465 :function:::void:check_u64:instruction_word insn
472 // The check should be similar to mips64 for any with PX/UX bit equivalents.
475 :function:::void:check_u64:instruction_word insn
478 #if 0 /* XXX FIXME: enable this only after some additional testing. */
479 if (UserMode && (SR & (status_UX|status_PX)) == 0)
480 SignalException (ReservedInstruction, insn);
487 // MIPS Architecture:
489 // CPU Instruction Set (mipsI - mipsV, mips32, mips64)
494 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
495 "add r<RD>, r<RS>, r<RT>"
507 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
509 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
511 ALU32_BEGIN (GPR[RS]);
513 ALU32_END (GPR[RD]); /* This checks for overflow. */
515 TRACE_ALU_RESULT (GPR[RD]);
520 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
521 "addi r<RT>, r<RS>, <IMMEDIATE>"
533 if (NotWordValue (GPR[RS]))
535 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
537 ALU32_BEGIN (GPR[RS]);
538 ALU32_ADD (EXTEND16 (IMMEDIATE));
539 ALU32_END (GPR[RT]); /* This checks for overflow. */
541 TRACE_ALU_RESULT (GPR[RT]);
546 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
548 if (NotWordValue (GPR[rs]))
550 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
551 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
552 TRACE_ALU_RESULT (GPR[rt]);
555 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
556 "addiu r<RT>, r<RS>, <IMMEDIATE>"
568 do_addiu (SD_, RS, RT, IMMEDIATE);
573 :function:::void:do_addu:int rs, int rt, int rd
575 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
577 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
578 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
579 TRACE_ALU_RESULT (GPR[rd]);
582 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
583 "addu r<RD>, r<RS>, r<RT>"
595 do_addu (SD_, RS, RT, RD);
600 :function:::void:do_and:int rs, int rt, int rd
602 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
603 GPR[rd] = GPR[rs] & GPR[rt];
604 TRACE_ALU_RESULT (GPR[rd]);
607 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
608 "and r<RD>, r<RS>, r<RT>"
620 do_and (SD_, RS, RT, RD);
625 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
626 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
638 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
639 GPR[RT] = GPR[RS] & IMMEDIATE;
640 TRACE_ALU_RESULT (GPR[RT]);
645 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
646 "beq r<RS>, r<RT>, <OFFSET>"
658 address_word offset = EXTEND16 (OFFSET) << 2;
659 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
661 DELAY_SLOT (NIA + offset);
667 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
668 "beql r<RS>, r<RT>, <OFFSET>"
679 address_word offset = EXTEND16 (OFFSET) << 2;
680 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
682 DELAY_SLOT (NIA + offset);
685 NULLIFY_NEXT_INSTRUCTION ();
690 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
691 "bgez r<RS>, <OFFSET>"
703 address_word offset = EXTEND16 (OFFSET) << 2;
704 if ((signed_word) GPR[RS] >= 0)
706 DELAY_SLOT (NIA + offset);
712 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
713 "bgezal r<RS>, <OFFSET>"
725 address_word offset = EXTEND16 (OFFSET) << 2;
729 if ((signed_word) GPR[RS] >= 0)
731 DELAY_SLOT (NIA + offset);
737 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
738 "bgezall r<RS>, <OFFSET>"
749 address_word offset = EXTEND16 (OFFSET) << 2;
753 /* NOTE: The branch occurs AFTER the next instruction has been
755 if ((signed_word) GPR[RS] >= 0)
757 DELAY_SLOT (NIA + offset);
760 NULLIFY_NEXT_INSTRUCTION ();
765 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
766 "bgezl r<RS>, <OFFSET>"
777 address_word offset = EXTEND16 (OFFSET) << 2;
778 if ((signed_word) GPR[RS] >= 0)
780 DELAY_SLOT (NIA + offset);
783 NULLIFY_NEXT_INSTRUCTION ();
788 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
789 "bgtz r<RS>, <OFFSET>"
801 address_word offset = EXTEND16 (OFFSET) << 2;
802 if ((signed_word) GPR[RS] > 0)
804 DELAY_SLOT (NIA + offset);
810 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
811 "bgtzl r<RS>, <OFFSET>"
822 address_word offset = EXTEND16 (OFFSET) << 2;
823 /* NOTE: The branch occurs AFTER the next instruction has been
825 if ((signed_word) GPR[RS] > 0)
827 DELAY_SLOT (NIA + offset);
830 NULLIFY_NEXT_INSTRUCTION ();
835 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
836 "blez r<RS>, <OFFSET>"
848 address_word offset = EXTEND16 (OFFSET) << 2;
849 /* NOTE: The branch occurs AFTER the next instruction has been
851 if ((signed_word) GPR[RS] <= 0)
853 DELAY_SLOT (NIA + offset);
859 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
860 "bgezl r<RS>, <OFFSET>"
871 address_word offset = EXTEND16 (OFFSET) << 2;
872 if ((signed_word) GPR[RS] <= 0)
874 DELAY_SLOT (NIA + offset);
877 NULLIFY_NEXT_INSTRUCTION ();
882 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
883 "bltz r<RS>, <OFFSET>"
895 address_word offset = EXTEND16 (OFFSET) << 2;
896 if ((signed_word) GPR[RS] < 0)
898 DELAY_SLOT (NIA + offset);
904 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
905 "bltzal r<RS>, <OFFSET>"
917 address_word offset = EXTEND16 (OFFSET) << 2;
921 /* NOTE: The branch occurs AFTER the next instruction has been
923 if ((signed_word) GPR[RS] < 0)
925 DELAY_SLOT (NIA + offset);
931 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
932 "bltzall r<RS>, <OFFSET>"
943 address_word offset = EXTEND16 (OFFSET) << 2;
947 if ((signed_word) GPR[RS] < 0)
949 DELAY_SLOT (NIA + offset);
952 NULLIFY_NEXT_INSTRUCTION ();
957 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
958 "bltzl r<RS>, <OFFSET>"
969 address_word offset = EXTEND16 (OFFSET) << 2;
970 /* NOTE: The branch occurs AFTER the next instruction has been
972 if ((signed_word) GPR[RS] < 0)
974 DELAY_SLOT (NIA + offset);
977 NULLIFY_NEXT_INSTRUCTION ();
982 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
983 "bne r<RS>, r<RT>, <OFFSET>"
995 address_word offset = EXTEND16 (OFFSET) << 2;
996 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
998 DELAY_SLOT (NIA + offset);
1004 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1005 "bnel r<RS>, r<RT>, <OFFSET>"
1016 address_word offset = EXTEND16 (OFFSET) << 2;
1017 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1019 DELAY_SLOT (NIA + offset);
1022 NULLIFY_NEXT_INSTRUCTION ();
1027 000000,20.CODE,001101:SPECIAL:32::BREAK
1040 /* Check for some break instruction which are reserved for use by the simulator. */
1041 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1042 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1043 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1045 sim_engine_halt (SD, CPU, NULL, cia,
1046 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1048 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1049 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1051 if (STATE & simDELAYSLOT)
1052 PC = cia - 4; /* reference the branch instruction */
1055 SignalException (BreakPoint, instruction_0);
1060 /* If we get this far, we're not an instruction reserved by the sim. Raise
1062 SignalException (BreakPoint, instruction_0);
1068 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1074 unsigned32 temp = GPR[RS];
1078 if (NotWordValue (GPR[RS]))
1080 TRACE_ALU_INPUT1 (GPR[RS]);
1081 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1083 if ((temp & mask) == 0)
1087 GPR[RD] = EXTEND32 (i);
1088 TRACE_ALU_RESULT (GPR[RD]);
1093 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1099 unsigned32 temp = GPR[RS];
1103 if (NotWordValue (GPR[RS]))
1105 TRACE_ALU_INPUT1 (GPR[RS]);
1106 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1108 if ((temp & mask) != 0)
1112 GPR[RD] = EXTEND32 (i);
1113 TRACE_ALU_RESULT (GPR[RD]);
1118 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1119 "dadd r<RD>, r<RS>, r<RT>"
1127 check_u64 (SD_, instruction_0);
1128 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1130 ALU64_BEGIN (GPR[RS]);
1131 ALU64_ADD (GPR[RT]);
1132 ALU64_END (GPR[RD]); /* This checks for overflow. */
1134 TRACE_ALU_RESULT (GPR[RD]);
1139 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1140 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1148 check_u64 (SD_, instruction_0);
1149 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1151 ALU64_BEGIN (GPR[RS]);
1152 ALU64_ADD (EXTEND16 (IMMEDIATE));
1153 ALU64_END (GPR[RT]); /* This checks for overflow. */
1155 TRACE_ALU_RESULT (GPR[RT]);
1160 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1162 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1163 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1164 TRACE_ALU_RESULT (GPR[rt]);
1167 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1168 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1176 check_u64 (SD_, instruction_0);
1177 do_daddiu (SD_, RS, RT, IMMEDIATE);
1182 :function:::void:do_daddu:int rs, int rt, int rd
1184 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1185 GPR[rd] = GPR[rs] + GPR[rt];
1186 TRACE_ALU_RESULT (GPR[rd]);
1189 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1190 "daddu r<RD>, r<RS>, r<RT>"
1198 check_u64 (SD_, instruction_0);
1199 do_daddu (SD_, RS, RT, RD);
1204 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1209 unsigned64 temp = GPR[RS];
1212 check_u64 (SD_, instruction_0);
1215 TRACE_ALU_INPUT1 (GPR[RS]);
1216 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1218 if ((temp & mask) == 0)
1222 GPR[RD] = EXTEND32 (i);
1223 TRACE_ALU_RESULT (GPR[RD]);
1228 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1233 unsigned64 temp = GPR[RS];
1236 check_u64 (SD_, instruction_0);
1239 TRACE_ALU_INPUT1 (GPR[RS]);
1240 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1242 if ((temp & mask) != 0)
1246 GPR[RD] = EXTEND32 (i);
1247 TRACE_ALU_RESULT (GPR[RD]);
1252 :function:::void:do_ddiv:int rs, int rt
1254 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1255 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1257 signed64 n = GPR[rs];
1258 signed64 d = GPR[rt];
1263 lo = SIGNED64 (0x8000000000000000);
1266 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1268 lo = SIGNED64 (0x8000000000000000);
1279 TRACE_ALU_RESULT2 (HI, LO);
1282 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1291 check_u64 (SD_, instruction_0);
1292 do_ddiv (SD_, RS, RT);
1297 :function:::void:do_ddivu:int rs, int rt
1299 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1300 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1302 unsigned64 n = GPR[rs];
1303 unsigned64 d = GPR[rt];
1308 lo = SIGNED64 (0x8000000000000000);
1319 TRACE_ALU_RESULT2 (HI, LO);
1322 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1323 "ddivu r<RS>, r<RT>"
1331 check_u64 (SD_, instruction_0);
1332 do_ddivu (SD_, RS, RT);
1337 :function:::void:do_div:int rs, int rt
1339 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1340 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1342 signed32 n = GPR[rs];
1343 signed32 d = GPR[rt];
1346 LO = EXTEND32 (0x80000000);
1349 else if (n == SIGNED32 (0x80000000) && d == -1)
1351 LO = EXTEND32 (0x80000000);
1356 LO = EXTEND32 (n / d);
1357 HI = EXTEND32 (n % d);
1360 TRACE_ALU_RESULT2 (HI, LO);
1363 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1376 do_div (SD_, RS, RT);
1381 :function:::void:do_divu:int rs, int rt
1383 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1384 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1386 unsigned32 n = GPR[rs];
1387 unsigned32 d = GPR[rt];
1390 LO = EXTEND32 (0x80000000);
1395 LO = EXTEND32 (n / d);
1396 HI = EXTEND32 (n % d);
1399 TRACE_ALU_RESULT2 (HI, LO);
1402 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1415 do_divu (SD_, RS, RT);
1420 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1430 unsigned64 op1 = GPR[rs];
1431 unsigned64 op2 = GPR[rt];
1432 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1433 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1434 /* make signed multiply unsigned */
1438 if ((signed64) op1 < 0)
1443 if ((signed64) op2 < 0)
1449 /* multiply out the 4 sub products */
1450 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1451 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1452 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1453 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1454 /* add the products */
1455 mid = ((unsigned64) VH4_8 (m00)
1456 + (unsigned64) VL4_8 (m10)
1457 + (unsigned64) VL4_8 (m01));
1458 lo = U8_4 (mid, m00);
1460 + (unsigned64) VH4_8 (mid)
1461 + (unsigned64) VH4_8 (m01)
1462 + (unsigned64) VH4_8 (m10));
1472 /* save the result HI/LO (and a gpr) */
1477 TRACE_ALU_RESULT2 (HI, LO);
1480 :function:::void:do_dmult:int rs, int rt, int rd
1482 do_dmultx (SD_, rs, rt, rd, 1);
1485 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1486 "dmult r<RS>, r<RT>"
1493 check_u64 (SD_, instruction_0);
1494 do_dmult (SD_, RS, RT, 0);
1497 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1498 "dmult r<RS>, r<RT>":RD == 0
1499 "dmult r<RD>, r<RS>, r<RT>"
1502 check_u64 (SD_, instruction_0);
1503 do_dmult (SD_, RS, RT, RD);
1508 :function:::void:do_dmultu:int rs, int rt, int rd
1510 do_dmultx (SD_, rs, rt, rd, 0);
1513 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1514 "dmultu r<RS>, r<RT>"
1521 check_u64 (SD_, instruction_0);
1522 do_dmultu (SD_, RS, RT, 0);
1525 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1526 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1527 "dmultu r<RS>, r<RT>"
1530 check_u64 (SD_, instruction_0);
1531 do_dmultu (SD_, RS, RT, RD);
1534 :function:::void:do_dsll:int rt, int rd, int shift
1536 TRACE_ALU_INPUT2 (GPR[rt], shift);
1537 GPR[rd] = GPR[rt] << shift;
1538 TRACE_ALU_RESULT (GPR[rd]);
1541 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1542 "dsll r<RD>, r<RT>, <SHIFT>"
1550 check_u64 (SD_, instruction_0);
1551 do_dsll (SD_, RT, RD, SHIFT);
1555 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1556 "dsll32 r<RD>, r<RT>, <SHIFT>"
1565 check_u64 (SD_, instruction_0);
1566 TRACE_ALU_INPUT2 (GPR[RT], s);
1567 GPR[RD] = GPR[RT] << s;
1568 TRACE_ALU_RESULT (GPR[RD]);
1571 :function:::void:do_dsllv:int rs, int rt, int rd
1573 int s = MASKED64 (GPR[rs], 5, 0);
1574 TRACE_ALU_INPUT2 (GPR[rt], s);
1575 GPR[rd] = GPR[rt] << s;
1576 TRACE_ALU_RESULT (GPR[rd]);
1579 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1580 "dsllv r<RD>, r<RT>, r<RS>"
1588 check_u64 (SD_, instruction_0);
1589 do_dsllv (SD_, RS, RT, RD);
1592 :function:::void:do_dsra:int rt, int rd, int shift
1594 TRACE_ALU_INPUT2 (GPR[rt], shift);
1595 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1596 TRACE_ALU_RESULT (GPR[rd]);
1600 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1601 "dsra r<RD>, r<RT>, <SHIFT>"
1609 check_u64 (SD_, instruction_0);
1610 do_dsra (SD_, RT, RD, SHIFT);
1614 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1615 "dsra32 r<RD>, r<RT>, <SHIFT>"
1624 check_u64 (SD_, instruction_0);
1625 TRACE_ALU_INPUT2 (GPR[RT], s);
1626 GPR[RD] = ((signed64) GPR[RT]) >> s;
1627 TRACE_ALU_RESULT (GPR[RD]);
1631 :function:::void:do_dsrav:int rs, int rt, int rd
1633 int s = MASKED64 (GPR[rs], 5, 0);
1634 TRACE_ALU_INPUT2 (GPR[rt], s);
1635 GPR[rd] = ((signed64) GPR[rt]) >> s;
1636 TRACE_ALU_RESULT (GPR[rd]);
1639 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1640 "dsrav r<RD>, r<RT>, r<RS>"
1648 check_u64 (SD_, instruction_0);
1649 do_dsrav (SD_, RS, RT, RD);
1652 :function:::void:do_dsrl:int rt, int rd, int shift
1654 TRACE_ALU_INPUT2 (GPR[rt], shift);
1655 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1656 TRACE_ALU_RESULT (GPR[rd]);
1660 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1661 "dsrl r<RD>, r<RT>, <SHIFT>"
1669 check_u64 (SD_, instruction_0);
1670 do_dsrl (SD_, RT, RD, SHIFT);
1674 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1675 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1684 check_u64 (SD_, instruction_0);
1685 TRACE_ALU_INPUT2 (GPR[RT], s);
1686 GPR[RD] = (unsigned64) GPR[RT] >> s;
1687 TRACE_ALU_RESULT (GPR[RD]);
1691 :function:::void:do_dsrlv:int rs, int rt, int rd
1693 int s = MASKED64 (GPR[rs], 5, 0);
1694 TRACE_ALU_INPUT2 (GPR[rt], s);
1695 GPR[rd] = (unsigned64) GPR[rt] >> s;
1696 TRACE_ALU_RESULT (GPR[rd]);
1701 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1702 "dsrlv r<RD>, r<RT>, r<RS>"
1710 check_u64 (SD_, instruction_0);
1711 do_dsrlv (SD_, RS, RT, RD);
1715 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1716 "dsub r<RD>, r<RS>, r<RT>"
1724 check_u64 (SD_, instruction_0);
1725 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1727 ALU64_BEGIN (GPR[RS]);
1728 ALU64_SUB (GPR[RT]);
1729 ALU64_END (GPR[RD]); /* This checks for overflow. */
1731 TRACE_ALU_RESULT (GPR[RD]);
1735 :function:::void:do_dsubu:int rs, int rt, int rd
1737 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1738 GPR[rd] = GPR[rs] - GPR[rt];
1739 TRACE_ALU_RESULT (GPR[rd]);
1742 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1743 "dsubu r<RD>, r<RS>, r<RT>"
1751 check_u64 (SD_, instruction_0);
1752 do_dsubu (SD_, RS, RT, RD);
1756 000010,26.INSTR_INDEX:NORMAL:32::J
1769 /* NOTE: The region used is that of the delay slot NIA and NOT the
1770 current instruction */
1771 address_word region = (NIA & MASK (63, 28));
1772 DELAY_SLOT (region | (INSTR_INDEX << 2));
1776 000011,26.INSTR_INDEX:NORMAL:32::JAL
1789 /* NOTE: The region used is that of the delay slot and NOT the
1790 current instruction */
1791 address_word region = (NIA & MASK (63, 28));
1793 DELAY_SLOT (region | (INSTR_INDEX << 2));
1796 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1797 "jalr r<RS>":RD == 31
1810 address_word temp = GPR[RS];
1816 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1829 DELAY_SLOT (GPR[RS]);
1833 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1835 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1836 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1837 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1844 vaddr = loadstore_ea (SD_, base, offset);
1845 if ((vaddr & access) != 0)
1847 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1849 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1850 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1851 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1852 byte = ((vaddr & mask) ^ bigendiancpu);
1853 return (memval >> (8 * byte));
1856 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1858 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1859 address_word reverseendian = (ReverseEndian ? -1 : 0);
1860 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1869 unsigned_word lhs_mask;
1872 vaddr = loadstore_ea (SD_, base, offset);
1873 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1874 paddr = (paddr ^ (reverseendian & mask));
1875 if (BigEndianMem == 0)
1876 paddr = paddr & ~access;
1878 /* compute where within the word/mem we are */
1879 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1880 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1881 nr_lhs_bits = 8 * byte + 8;
1882 nr_rhs_bits = 8 * access - 8 * byte;
1883 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1885 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1886 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1887 (long) ((unsigned64) paddr >> 32), (long) paddr,
1888 word, byte, nr_lhs_bits, nr_rhs_bits); */
1890 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1893 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1894 temp = (memval << nr_rhs_bits);
1898 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1899 temp = (memval >> nr_lhs_bits);
1901 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1902 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1904 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1905 (long) ((unsigned64) memval >> 32), (long) memval,
1906 (long) ((unsigned64) temp >> 32), (long) temp,
1907 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1908 (long) (rt >> 32), (long) rt); */
1912 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1914 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1915 address_word reverseendian = (ReverseEndian ? -1 : 0);
1916 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1923 vaddr = loadstore_ea (SD_, base, offset);
1924 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1925 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1926 paddr = (paddr ^ (reverseendian & mask));
1927 if (BigEndianMem != 0)
1928 paddr = paddr & ~access;
1929 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1930 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1931 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1932 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1933 (long) paddr, byte, (long) paddr, (long) memval); */
1935 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1937 rt |= (memval >> (8 * byte)) & screen;
1943 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1944 "lb r<RT>, <OFFSET>(r<BASE>)"
1956 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1960 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1961 "lbu r<RT>, <OFFSET>(r<BASE>)"
1973 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1977 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1978 "ld r<RT>, <OFFSET>(r<BASE>)"
1986 check_u64 (SD_, instruction_0);
1987 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1991 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1992 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2003 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2009 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2010 "ldl r<RT>, <OFFSET>(r<BASE>)"
2018 check_u64 (SD_, instruction_0);
2019 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2023 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2024 "ldr r<RT>, <OFFSET>(r<BASE>)"
2032 check_u64 (SD_, instruction_0);
2033 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2037 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2038 "lh r<RT>, <OFFSET>(r<BASE>)"
2050 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2054 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2055 "lhu r<RT>, <OFFSET>(r<BASE>)"
2067 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2071 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2072 "ll r<RT>, <OFFSET>(r<BASE>)"
2082 address_word base = GPR[BASE];
2083 address_word offset = EXTEND16 (OFFSET);
2085 address_word vaddr = loadstore_ea (SD_, base, offset);
2088 if ((vaddr & 3) != 0)
2090 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2094 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2096 unsigned64 memval = 0;
2097 unsigned64 memval1 = 0;
2098 unsigned64 mask = 0x7;
2099 unsigned int shift = 2;
2100 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2101 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2103 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2104 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2105 byte = ((vaddr & mask) ^ (bigend << shift));
2106 GPR[RT] = EXTEND32 (memval >> (8 * byte));
2114 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2115 "lld r<RT>, <OFFSET>(r<BASE>)"
2123 address_word base = GPR[BASE];
2124 address_word offset = EXTEND16 (OFFSET);
2125 check_u64 (SD_, instruction_0);
2127 address_word vaddr = loadstore_ea (SD_, base, offset);
2130 if ((vaddr & 7) != 0)
2132 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2136 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2138 unsigned64 memval = 0;
2139 unsigned64 memval1 = 0;
2140 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2149 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2150 "lui r<RT>, %#lx<IMMEDIATE>"
2162 TRACE_ALU_INPUT1 (IMMEDIATE);
2163 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2164 TRACE_ALU_RESULT (GPR[RT]);
2168 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2169 "lw r<RT>, <OFFSET>(r<BASE>)"
2181 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2185 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2186 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2198 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2202 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2203 "lwl r<RT>, <OFFSET>(r<BASE>)"
2215 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2219 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2220 "lwr r<RT>, <OFFSET>(r<BASE>)"
2232 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2236 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2237 "lwu r<RT>, <OFFSET>(r<BASE>)"
2245 check_u64 (SD_, instruction_0);
2246 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2251 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2258 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2259 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2261 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2262 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2263 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2264 LO = EXTEND32 (temp);
2265 HI = EXTEND32 (VH4_8 (temp));
2266 TRACE_ALU_RESULT2 (HI, LO);
2271 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2272 "maddu r<RS>, r<RT>"
2278 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2279 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2281 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2282 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2283 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2284 LO = EXTEND32 (temp);
2285 HI = EXTEND32 (VH4_8 (temp));
2286 TRACE_ALU_RESULT2 (HI, LO);
2290 :function:::void:do_mfhi:int rd
2292 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2293 TRACE_ALU_INPUT1 (HI);
2295 TRACE_ALU_RESULT (GPR[rd]);
2298 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2316 :function:::void:do_mflo:int rd
2318 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2319 TRACE_ALU_INPUT1 (LO);
2321 TRACE_ALU_RESULT (GPR[rd]);
2324 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2342 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2343 "movn r<RD>, r<RS>, r<RT>"
2353 TRACE_ALU_RESULT (GPR[RD]);
2359 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2360 "movz r<RD>, r<RS>, r<RT>"
2370 TRACE_ALU_RESULT (GPR[RD]);
2376 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2383 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2384 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2386 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2387 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2388 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2389 LO = EXTEND32 (temp);
2390 HI = EXTEND32 (VH4_8 (temp));
2391 TRACE_ALU_RESULT2 (HI, LO);
2396 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2397 "msubu r<RS>, r<RT>"
2403 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2404 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2406 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2407 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2408 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2409 LO = EXTEND32 (temp);
2410 HI = EXTEND32 (VH4_8 (temp));
2411 TRACE_ALU_RESULT2 (HI, LO);
2416 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2429 check_mt_hilo (SD_, HIHISTORY);
2435 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2448 check_mt_hilo (SD_, LOHISTORY);
2454 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2455 "mul r<RD>, r<RS>, r<RT>"
2461 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2463 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2464 prod = (((signed64)(signed32) GPR[RS])
2465 * ((signed64)(signed32) GPR[RT]));
2466 GPR[RD] = EXTEND32 (VL4_8 (prod));
2467 TRACE_ALU_RESULT (GPR[RD]);
2472 :function:::void:do_mult:int rs, int rt, int rd
2475 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2476 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2478 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2479 prod = (((signed64)(signed32) GPR[rs])
2480 * ((signed64)(signed32) GPR[rt]));
2481 LO = EXTEND32 (VL4_8 (prod));
2482 HI = EXTEND32 (VH4_8 (prod));
2485 TRACE_ALU_RESULT2 (HI, LO);
2488 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2499 do_mult (SD_, RS, RT, 0);
2503 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2504 "mult r<RS>, r<RT>":RD == 0
2505 "mult r<RD>, r<RS>, r<RT>"
2509 do_mult (SD_, RS, RT, RD);
2513 :function:::void:do_multu:int rs, int rt, int rd
2516 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2517 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2519 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2520 prod = (((unsigned64)(unsigned32) GPR[rs])
2521 * ((unsigned64)(unsigned32) GPR[rt]));
2522 LO = EXTEND32 (VL4_8 (prod));
2523 HI = EXTEND32 (VH4_8 (prod));
2526 TRACE_ALU_RESULT2 (HI, LO);
2529 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2530 "multu r<RS>, r<RT>"
2540 do_multu (SD_, RS, RT, 0);
2543 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2544 "multu r<RS>, r<RT>":RD == 0
2545 "multu r<RD>, r<RS>, r<RT>"
2549 do_multu (SD_, RS, RT, RD);
2553 :function:::void:do_nor:int rs, int rt, int rd
2555 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2556 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2557 TRACE_ALU_RESULT (GPR[rd]);
2560 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2561 "nor r<RD>, r<RS>, r<RT>"
2573 do_nor (SD_, RS, RT, RD);
2577 :function:::void:do_or:int rs, int rt, int rd
2579 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2580 GPR[rd] = (GPR[rs] | GPR[rt]);
2581 TRACE_ALU_RESULT (GPR[rd]);
2584 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2585 "or r<RD>, r<RS>, r<RT>"
2597 do_or (SD_, RS, RT, RD);
2602 :function:::void:do_ori:int rs, int rt, unsigned immediate
2604 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2605 GPR[rt] = (GPR[rs] | immediate);
2606 TRACE_ALU_RESULT (GPR[rt]);
2609 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2610 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2622 do_ori (SD_, RS, RT, IMMEDIATE);
2626 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2627 "pref <HINT>, <OFFSET>(r<BASE>)"
2634 address_word base = GPR[BASE];
2635 address_word offset = EXTEND16 (OFFSET);
2637 address_word vaddr = loadstore_ea (SD_, base, offset);
2641 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2642 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2648 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2650 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2651 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2652 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2659 vaddr = loadstore_ea (SD_, base, offset);
2660 if ((vaddr & access) != 0)
2662 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2664 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2665 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2666 byte = ((vaddr & mask) ^ bigendiancpu);
2667 memval = (word << (8 * byte));
2668 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2671 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2673 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2674 address_word reverseendian = (ReverseEndian ? -1 : 0);
2675 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2685 vaddr = loadstore_ea (SD_, base, offset);
2686 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2687 paddr = (paddr ^ (reverseendian & mask));
2688 if (BigEndianMem == 0)
2689 paddr = paddr & ~access;
2691 /* compute where within the word/mem we are */
2692 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2693 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2694 nr_lhs_bits = 8 * byte + 8;
2695 nr_rhs_bits = 8 * access - 8 * byte;
2696 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2697 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2698 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2699 (long) ((unsigned64) paddr >> 32), (long) paddr,
2700 word, byte, nr_lhs_bits, nr_rhs_bits); */
2704 memval = (rt >> nr_rhs_bits);
2708 memval = (rt << nr_lhs_bits);
2710 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2711 (long) ((unsigned64) rt >> 32), (long) rt,
2712 (long) ((unsigned64) memval >> 32), (long) memval); */
2713 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2716 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2718 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2719 address_word reverseendian = (ReverseEndian ? -1 : 0);
2720 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2727 vaddr = loadstore_ea (SD_, base, offset);
2728 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2729 paddr = (paddr ^ (reverseendian & mask));
2730 if (BigEndianMem != 0)
2732 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2733 memval = (rt << (byte * 8));
2734 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2738 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2739 "sb r<RT>, <OFFSET>(r<BASE>)"
2751 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2755 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2756 "sc r<RT>, <OFFSET>(r<BASE>)"
2766 unsigned32 instruction = instruction_0;
2767 address_word base = GPR[BASE];
2768 address_word offset = EXTEND16 (OFFSET);
2770 address_word vaddr = loadstore_ea (SD_, base, offset);
2773 if ((vaddr & 3) != 0)
2775 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2779 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2781 unsigned64 memval = 0;
2782 unsigned64 memval1 = 0;
2783 unsigned64 mask = 0x7;
2785 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2786 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2787 memval = ((unsigned64) GPR[RT] << (8 * byte));
2790 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2799 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2800 "scd r<RT>, <OFFSET>(r<BASE>)"
2808 address_word base = GPR[BASE];
2809 address_word offset = EXTEND16 (OFFSET);
2810 check_u64 (SD_, instruction_0);
2812 address_word vaddr = loadstore_ea (SD_, base, offset);
2815 if ((vaddr & 7) != 0)
2817 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2821 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2823 unsigned64 memval = 0;
2824 unsigned64 memval1 = 0;
2828 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2837 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2838 "sd r<RT>, <OFFSET>(r<BASE>)"
2846 check_u64 (SD_, instruction_0);
2847 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2851 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2852 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2862 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2866 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2867 "sdl r<RT>, <OFFSET>(r<BASE>)"
2875 check_u64 (SD_, instruction_0);
2876 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2880 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2881 "sdr r<RT>, <OFFSET>(r<BASE>)"
2889 check_u64 (SD_, instruction_0);
2890 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2894 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2895 "sh r<RT>, <OFFSET>(r<BASE>)"
2907 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2911 :function:::void:do_sll:int rt, int rd, int shift
2913 unsigned32 temp = (GPR[rt] << shift);
2914 TRACE_ALU_INPUT2 (GPR[rt], shift);
2915 GPR[rd] = EXTEND32 (temp);
2916 TRACE_ALU_RESULT (GPR[rd]);
2919 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2920 "nop":RD == 0 && RT == 0 && SHIFT == 0
2921 "sll r<RD>, r<RT>, <SHIFT>"
2931 /* Skip shift for NOP, so that there won't be lots of extraneous
2933 if (RD != 0 || RT != 0 || SHIFT != 0)
2934 do_sll (SD_, RT, RD, SHIFT);
2937 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2938 "nop":RD == 0 && RT == 0 && SHIFT == 0
2939 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2940 "sll r<RD>, r<RT>, <SHIFT>"
2944 /* Skip shift for NOP and SSNOP, so that there won't be lots of
2945 extraneous trace output. */
2946 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2947 do_sll (SD_, RT, RD, SHIFT);
2951 :function:::void:do_sllv:int rs, int rt, int rd
2953 int s = MASKED (GPR[rs], 4, 0);
2954 unsigned32 temp = (GPR[rt] << s);
2955 TRACE_ALU_INPUT2 (GPR[rt], s);
2956 GPR[rd] = EXTEND32 (temp);
2957 TRACE_ALU_RESULT (GPR[rd]);
2960 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2961 "sllv r<RD>, r<RT>, r<RS>"
2973 do_sllv (SD_, RS, RT, RD);
2977 :function:::void:do_slt:int rs, int rt, int rd
2979 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2980 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2981 TRACE_ALU_RESULT (GPR[rd]);
2984 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2985 "slt r<RD>, r<RS>, r<RT>"
2997 do_slt (SD_, RS, RT, RD);
3001 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3003 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3004 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3005 TRACE_ALU_RESULT (GPR[rt]);
3008 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3009 "slti r<RT>, r<RS>, <IMMEDIATE>"
3021 do_slti (SD_, RS, RT, IMMEDIATE);
3025 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3027 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3028 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3029 TRACE_ALU_RESULT (GPR[rt]);
3032 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3033 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3045 do_sltiu (SD_, RS, RT, IMMEDIATE);
3050 :function:::void:do_sltu:int rs, int rt, int rd
3052 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3053 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3054 TRACE_ALU_RESULT (GPR[rd]);
3057 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3058 "sltu r<RD>, r<RS>, r<RT>"
3070 do_sltu (SD_, RS, RT, RD);
3074 :function:::void:do_sra:int rt, int rd, int shift
3076 signed32 temp = (signed32) GPR[rt] >> shift;
3077 if (NotWordValue (GPR[rt]))
3079 TRACE_ALU_INPUT2 (GPR[rt], shift);
3080 GPR[rd] = EXTEND32 (temp);
3081 TRACE_ALU_RESULT (GPR[rd]);
3084 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3085 "sra r<RD>, r<RT>, <SHIFT>"
3097 do_sra (SD_, RT, RD, SHIFT);
3102 :function:::void:do_srav:int rs, int rt, int rd
3104 int s = MASKED (GPR[rs], 4, 0);
3105 signed32 temp = (signed32) GPR[rt] >> s;
3106 if (NotWordValue (GPR[rt]))
3108 TRACE_ALU_INPUT2 (GPR[rt], s);
3109 GPR[rd] = EXTEND32 (temp);
3110 TRACE_ALU_RESULT (GPR[rd]);
3113 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3114 "srav r<RD>, r<RT>, r<RS>"
3126 do_srav (SD_, RS, RT, RD);
3131 :function:::void:do_srl:int rt, int rd, int shift
3133 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3134 if (NotWordValue (GPR[rt]))
3136 TRACE_ALU_INPUT2 (GPR[rt], shift);
3137 GPR[rd] = EXTEND32 (temp);
3138 TRACE_ALU_RESULT (GPR[rd]);
3141 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3142 "srl r<RD>, r<RT>, <SHIFT>"
3154 do_srl (SD_, RT, RD, SHIFT);
3158 :function:::void:do_srlv:int rs, int rt, int rd
3160 int s = MASKED (GPR[rs], 4, 0);
3161 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3162 if (NotWordValue (GPR[rt]))
3164 TRACE_ALU_INPUT2 (GPR[rt], s);
3165 GPR[rd] = EXTEND32 (temp);
3166 TRACE_ALU_RESULT (GPR[rd]);
3169 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3170 "srlv r<RD>, r<RT>, r<RS>"
3182 do_srlv (SD_, RS, RT, RD);
3186 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3187 "sub r<RD>, r<RS>, r<RT>"
3199 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3201 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3203 ALU32_BEGIN (GPR[RS]);
3204 ALU32_SUB (GPR[RT]);
3205 ALU32_END (GPR[RD]); /* This checks for overflow. */
3207 TRACE_ALU_RESULT (GPR[RD]);
3211 :function:::void:do_subu:int rs, int rt, int rd
3213 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3215 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3216 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3217 TRACE_ALU_RESULT (GPR[rd]);
3220 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3221 "subu r<RD>, r<RS>, r<RT>"
3233 do_subu (SD_, RS, RT, RD);
3237 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3238 "sw r<RT>, <OFFSET>(r<BASE>)"
3250 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3254 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3255 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3267 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3271 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3272 "swl r<RT>, <OFFSET>(r<BASE>)"
3284 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3288 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3289 "swr r<RT>, <OFFSET>(r<BASE>)"
3301 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3305 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3318 SyncOperation (STYPE);
3322 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3323 "syscall %#lx<CODE>"
3335 SignalException (SystemCall, instruction_0);
3339 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3350 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3351 SignalException (Trap, instruction_0);
3355 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3356 "teqi r<RS>, <IMMEDIATE>"
3366 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3367 SignalException (Trap, instruction_0);
3371 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3382 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3383 SignalException (Trap, instruction_0);
3387 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3388 "tgei r<RS>, <IMMEDIATE>"
3398 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3399 SignalException (Trap, instruction_0);
3403 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3404 "tgeiu r<RS>, <IMMEDIATE>"
3414 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3415 SignalException (Trap, instruction_0);
3419 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3430 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3431 SignalException (Trap, instruction_0);
3435 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3446 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3447 SignalException (Trap, instruction_0);
3451 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3452 "tlti r<RS>, <IMMEDIATE>"
3462 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3463 SignalException (Trap, instruction_0);
3467 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3468 "tltiu r<RS>, <IMMEDIATE>"
3478 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3479 SignalException (Trap, instruction_0);
3483 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3494 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3495 SignalException (Trap, instruction_0);
3499 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3510 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3511 SignalException (Trap, instruction_0);
3515 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3516 "tnei r<RS>, <IMMEDIATE>"
3526 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3527 SignalException (Trap, instruction_0);
3531 :function:::void:do_xor:int rs, int rt, int rd
3533 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3534 GPR[rd] = GPR[rs] ^ GPR[rt];
3535 TRACE_ALU_RESULT (GPR[rd]);
3538 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3539 "xor r<RD>, r<RS>, r<RT>"
3551 do_xor (SD_, RS, RT, RD);
3555 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3557 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3558 GPR[rt] = GPR[rs] ^ immediate;
3559 TRACE_ALU_RESULT (GPR[rt]);
3562 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3563 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3575 do_xori (SD_, RS, RT, IMMEDIATE);
3580 // MIPS Architecture:
3582 // FPU Instruction Set (COP1 & COP1X)
3590 case fmt_single: return "s";
3591 case fmt_double: return "d";
3592 case fmt_word: return "w";
3593 case fmt_long: return "l";
3594 case fmt_ps: return "ps";
3595 default: return "?";
3615 :%s::::COND:int cond
3619 case 00: return "f";
3620 case 01: return "un";
3621 case 02: return "eq";
3622 case 03: return "ueq";
3623 case 04: return "olt";
3624 case 05: return "ult";
3625 case 06: return "ole";
3626 case 07: return "ule";
3627 case 010: return "sf";
3628 case 011: return "ngle";
3629 case 012: return "seq";
3630 case 013: return "ngl";
3631 case 014: return "lt";
3632 case 015: return "nge";
3633 case 016: return "le";
3634 case 017: return "ngt";
3635 default: return "?";
3642 // Check that the given FPU format is usable, and signal a
3643 // ReservedInstruction exception if not.
3646 // check_fmt_p checks that the format is single, double, or paired single.
3647 :function:::void:check_fmt_p:int fmt, instruction_word insn
3657 /* None of these ISAs support Paired Single, so just fall back to
3658 the single/double check. */
3659 if ((fmt != fmt_single) && (fmt != fmt_double))
3660 SignalException (ReservedInstruction, insn);
3663 :function:::void:check_fmt_p:int fmt, instruction_word insn
3667 if ((fmt != fmt_single) && (fmt != fmt_double)
3668 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3669 SignalException (ReservedInstruction, insn);
3675 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3676 // exception if not.
3679 :function:::void:check_fpu:
3691 if (! COP_Usable (1))
3692 SignalExceptionCoProcessorUnusable (1);
3698 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
3699 // or MIPS32. do_load cannot be used instead because it returns an
3700 // unsigned_word, which is limited to the size of the machine's registers.
3703 :function:::unsigned64:do_load_double:address_word base, address_word offset
3707 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3714 vaddr = loadstore_ea (SD_, base, offset);
3715 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3717 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
3718 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
3719 sim_core_unaligned_signal);
3721 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
3723 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
3725 v = (unsigned64)memval;
3726 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
3728 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
3734 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
3735 // or MIPS32. do_load cannot be used instead because it returns an
3736 // unsigned_word, which is limited to the size of the machine's registers.
3739 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
3743 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3749 vaddr = loadstore_ea (SD_, base, offset);
3750 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3752 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
3753 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
3754 sim_core_unaligned_signal);
3756 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
3758 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
3759 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
3761 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
3762 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
3767 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3768 "abs.%s<FMT> f<FD>, f<FS>"
3782 check_fmt_p (SD_, fmt, instruction_0);
3783 StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
3788 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3789 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3803 check_fmt_p (SD_, fmt, instruction_0);
3804 StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
3808 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
3809 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
3817 check_u64 (SD_, instruction_0);
3818 fs = ValueFPR (FS, fmt_ps);
3819 if ((GPR[RS] & 0x3) != 0)
3821 if ((GPR[RS] & 0x4) == 0)
3825 ft = ValueFPR (FT, fmt_ps);
3827 fd = PackPS (PSLower (fs), PSUpper (ft));
3829 fd = PackPS (PSLower (ft), PSUpper (fs));
3831 StoreFPR (FD, fmt_ps, fd);
3840 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3841 "bc1%s<TF>%s<ND> <OFFSET>"
3847 TRACE_BRANCH_INPUT (PREVCOC1());
3848 if (PREVCOC1() == TF)
3850 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3851 TRACE_BRANCH_RESULT (dest);
3856 TRACE_BRANCH_RESULT (0);
3857 NULLIFY_NEXT_INSTRUCTION ();
3861 TRACE_BRANCH_RESULT (NIA);
3865 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3866 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3867 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3877 if (GETFCC(CC) == TF)
3879 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3884 NULLIFY_NEXT_INSTRUCTION ();
3889 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3890 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3897 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
3898 TRACE_ALU_RESULT (ValueFCR (31));
3901 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3902 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3903 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3914 check_fmt_p (SD_, fmt, instruction_0);
3915 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
3916 TRACE_ALU_RESULT (ValueFCR (31));
3920 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3921 "ceil.l.%s<FMT> f<FD>, f<FS>"
3932 StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3937 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3938 "ceil.w.%s<FMT> f<FD>, f<FS>"
3951 StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3956 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
3964 PENDING_FILL (RT, EXTEND32 (FCR0));
3966 PENDING_FILL (RT, EXTEND32 (FCR31));
3970 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
3978 if (FS == 0 || FS == 31)
3980 unsigned_word fcr = ValueFCR (FS);
3981 TRACE_ALU_INPUT1 (fcr);
3985 TRACE_ALU_RESULT (GPR[RT]);
3988 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
3995 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
3997 unsigned_word fcr = ValueFCR (FS);
3998 TRACE_ALU_INPUT1 (fcr);
4002 TRACE_ALU_RESULT (GPR[RT]);
4005 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4013 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4017 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4025 TRACE_ALU_INPUT1 (GPR[RT]);
4027 StoreFCR (FS, GPR[RT]);
4031 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4038 TRACE_ALU_INPUT1 (GPR[RT]);
4039 if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4040 StoreFCR (FS, GPR[RT]);
4046 // FIXME: Does not correctly differentiate between mips*
4048 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4049 "cvt.d.%s<FMT> f<FD>, f<FS>"
4063 if ((fmt == fmt_double) | 0)
4064 SignalException (ReservedInstruction, instruction_0);
4065 StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4070 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4071 "cvt.l.%s<FMT> f<FD>, f<FS>"
4082 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4083 SignalException (ReservedInstruction, instruction_0);
4084 StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4089 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4090 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4095 check_u64 (SD_, instruction_0);
4096 StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4097 ValueFPR (FT, fmt_single)));
4102 // FIXME: Does not correctly differentiate between mips*
4104 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4105 "cvt.s.%s<FMT> f<FD>, f<FS>"
4119 if ((fmt == fmt_single) | 0)
4120 SignalException (ReservedInstruction, instruction_0);
4121 StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4126 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4127 "cvt.s.pl f<FD>, f<FS>"
4132 check_u64 (SD_, instruction_0);
4133 StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4137 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4138 "cvt.s.pu f<FD>, f<FS>"
4143 check_u64 (SD_, instruction_0);
4144 StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4148 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4149 "cvt.w.%s<FMT> f<FD>, f<FS>"
4163 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4164 SignalException (ReservedInstruction, instruction_0);
4165 StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4170 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4171 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4185 StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4189 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4190 "dmfc1 r<RT>, f<FS>"
4195 check_u64 (SD_, instruction_0);
4196 if (SizeFGR () == 64)
4198 else if ((FS & 0x1) == 0)
4199 v = SET64HI (FGR[FS+1]) | FGR[FS];
4201 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4202 PENDING_FILL (RT, v);
4203 TRACE_ALU_RESULT (v);
4206 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4207 "dmfc1 r<RT>, f<FS>"
4216 check_u64 (SD_, instruction_0);
4217 if (SizeFGR () == 64)
4219 else if ((FS & 0x1) == 0)
4220 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4222 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4223 TRACE_ALU_RESULT (GPR[RT]);
4227 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4228 "dmtc1 r<RT>, f<FS>"
4233 check_u64 (SD_, instruction_0);
4234 if (SizeFGR () == 64)
4235 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4236 else if ((FS & 0x1) == 0)
4238 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4239 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4243 TRACE_FP_RESULT (GPR[RT]);
4246 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4247 "dmtc1 r<RT>, f<FS>"
4256 check_u64 (SD_, instruction_0);
4257 if (SizeFGR () == 64)
4258 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4259 else if ((FS & 0x1) == 0)
4260 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4266 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4267 "floor.l.%s<FMT> f<FD>, f<FS>"
4278 StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4283 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4284 "floor.w.%s<FMT> f<FD>, f<FS>"
4297 StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4302 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4303 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4308 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4312 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4313 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4323 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4327 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4328 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4335 check_u64 (SD_, instruction_0);
4336 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4340 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4341 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4345 address_word base = GPR[BASE];
4346 address_word index = GPR[INDEX];
4347 address_word vaddr = base + index;
4349 check_u64 (SD_, instruction_0);
4350 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
4351 if ((vaddr & 0x7) != 0)
4352 index -= (vaddr & 0x7);
4353 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4357 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4358 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4371 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4375 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4376 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4383 check_u64 (SD_, instruction_0);
4384 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4389 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
4390 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4398 check_u64 (SD_, instruction_0);
4399 check_fmt_p (SD_, fmt, instruction_0);
4400 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4401 ValueFPR (FR, fmt), fmt));
4405 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4413 v = EXTEND32 (FGR[FS]);
4414 PENDING_FILL (RT, v);
4415 TRACE_ALU_RESULT (v);
4418 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4429 GPR[RT] = EXTEND32 (FGR[FS]);
4430 TRACE_ALU_RESULT (GPR[RT]);
4434 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4435 "mov.%s<FMT> f<FD>, f<FS>"
4449 check_fmt_p (SD_, fmt, instruction_0);
4450 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4456 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4457 "mov%s<TF> r<RD>, r<RS>, <CC>"
4465 if (GETFCC(CC) == TF)
4472 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4473 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4484 if (GETFCC(CC) == TF)
4485 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4487 StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
4492 fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4494 PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4496 StoreFPR (FD, fmt_ps, fd);
4501 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4502 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4511 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4513 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4520 // MOVT.fmt see MOVtf.fmt
4524 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4525 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4534 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4536 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4540 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
4541 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4549 check_u64 (SD_, instruction_0);
4550 check_fmt_p (SD_, fmt, instruction_0);
4551 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4552 ValueFPR (FR, fmt), fmt));
4556 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4563 if (SizeFGR () == 64)
4564 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4566 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4567 TRACE_FP_RESULT (GPR[RT]);
4570 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4581 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4585 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4586 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4600 check_fmt_p (SD_, fmt, instruction_0);
4601 StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4605 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4606 "neg.%s<FMT> f<FD>, f<FS>"
4620 check_fmt_p (SD_, fmt, instruction_0);
4621 StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4625 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
4626 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4634 check_u64 (SD_, instruction_0);
4635 check_fmt_p (SD_, fmt, instruction_0);
4636 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4637 ValueFPR (FR, fmt), fmt));
4641 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
4642 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4650 check_u64 (SD_, instruction_0);
4651 check_fmt_p (SD_, fmt, instruction_0);
4652 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4653 ValueFPR (FR, fmt), fmt));
4657 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
4658 "pll.ps f<FD>, f<FS>, f<FT>"
4663 check_u64 (SD_, instruction_0);
4664 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4665 PSLower (ValueFPR (FT, fmt_ps))));
4669 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
4670 "plu.ps f<FD>, f<FS>, f<FT>"
4675 check_u64 (SD_, instruction_0);
4676 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4677 PSUpper (ValueFPR (FT, fmt_ps))));
4681 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4682 "prefx <HINT>, r<INDEX>(r<BASE>)"
4688 address_word base = GPR[BASE];
4689 address_word index = GPR[INDEX];
4691 address_word vaddr = loadstore_ea (SD_, base, index);
4694 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4695 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4700 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
4701 "pul.ps f<FD>, f<FS>, f<FT>"
4706 check_u64 (SD_, instruction_0);
4707 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4708 PSLower (ValueFPR (FT, fmt_ps))));
4712 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
4713 "puu.ps f<FD>, f<FS>, f<FT>"
4718 check_u64 (SD_, instruction_0);
4719 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4720 PSUpper (ValueFPR (FT, fmt_ps))));
4724 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4725 "recip.%s<FMT> f<FD>, f<FS>"
4733 StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
4737 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4738 "round.l.%s<FMT> f<FD>, f<FS>"
4749 StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4754 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4755 "round.w.%s<FMT> f<FD>, f<FS>"
4768 StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4773 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4774 "rsqrt.%s<FMT> f<FD>, f<FS>"
4782 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
4786 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
4787 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4792 do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4796 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
4797 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4807 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4811 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4812 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4819 check_u64 (SD_, instruction_0);
4820 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4824 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
4825 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
4830 address_word base = GPR[BASE];
4831 address_word index = GPR[INDEX];
4832 address_word vaddr = base + index;
4834 check_u64 (SD_, instruction_0);
4835 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
4836 if ((vaddr & 0x7) != 0)
4837 index -= (vaddr & 0x7);
4838 do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
4842 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4843 "sqrt.%s<FMT> f<FD>, f<FS>"
4856 StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
4860 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4861 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4875 check_fmt_p (SD_, fmt, instruction_0);
4876 StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4881 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4882 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4894 address_word base = GPR[BASE];
4895 address_word offset = EXTEND16 (OFFSET);
4898 address_word vaddr = loadstore_ea (SD_, base, offset);
4901 if ((vaddr & 3) != 0)
4903 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4907 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4910 uword64 memval1 = 0;
4911 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4912 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4913 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4915 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4916 byte = ((vaddr & mask) ^ bigendiancpu);
4917 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4918 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4925 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4926 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4933 address_word base = GPR[BASE];
4934 address_word index = GPR[INDEX];
4936 check_u64 (SD_, instruction_0);
4938 address_word vaddr = loadstore_ea (SD_, base, index);
4941 if ((vaddr & 3) != 0)
4943 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4947 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4949 unsigned64 memval = 0;
4950 unsigned64 memval1 = 0;
4951 unsigned64 mask = 0x7;
4953 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4954 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4955 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4957 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4965 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4966 "trunc.l.%s<FMT> f<FD>, f<FS>"
4977 StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4982 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4983 "trunc.w.%s<FMT> f<FD>, f<FS>"
4996 StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5002 // MIPS Architecture:
5004 // System Control Instruction Set (COP0)
5008 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5020 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5022 // stub needed for eCos as tx39 hardware bug workaround
5029 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5042 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5054 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5067 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5068 "cache <OP>, <OFFSET>(r<BASE>)"
5078 address_word base = GPR[BASE];
5079 address_word offset = EXTEND16 (OFFSET);
5081 address_word vaddr = loadstore_ea (SD_, base, offset);
5084 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5085 CacheOp(OP,vaddr,paddr,instruction_0);
5090 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5091 "dmfc0 r<RT>, r<RD>"
5097 check_u64 (SD_, instruction_0);
5098 DecodeCoproc (instruction_0);
5102 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5103 "dmtc0 r<RT>, r<RD>"
5109 check_u64 (SD_, instruction_0);
5110 DecodeCoproc (instruction_0);
5114 010000,1,0000000000000000000,011000:COP0:32::ERET
5124 if (SR & status_ERL)
5126 /* Oops, not yet available */
5127 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5139 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5140 "mfc0 r<RT>, r<RD> # <REGX>"
5152 TRACE_ALU_INPUT0 ();
5153 DecodeCoproc (instruction_0);
5154 TRACE_ALU_RESULT (GPR[RT]);
5157 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5158 "mtc0 r<RT>, r<RD> # <REGX>"
5170 DecodeCoproc (instruction_0);
5174 010000,1,0000000000000000000,010000:COP0:32::RFE
5185 DecodeCoproc (instruction_0);
5189 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5190 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5201 DecodeCoproc (instruction_0);
5206 010000,1,0000000000000000000,001000:COP0:32::TLBP
5219 010000,1,0000000000000000000,000001:COP0:32::TLBR
5232 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5245 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5259 :include:::mdmx.igen
5260 :include:::mips3d.igen