sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 // start-sanitize-vr4320
  47 :model:::vr4320:mips4320:
  48 // end-sanitize-vr4320
  49 // start-sanitize-vr5400
  50 :model:::vr5400:mips5400:
  51 :model:::mdmx:mdmx:
  52 // end-sanitize-vr5400
  53 :model:::vr5000:mips5000:
  54
  55
  56
  57 // Pseudo instructions known by IGEN
  58 :internal::::illegal:
  59 {
  60   SignalException (ReservedInstruction, 0);
  61 }
  62
  63
  64 // Pseudo instructions known by interp.c
  65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  67 "rsvd <OP>"
  68 {
  69   SignalException (ReservedInstruction, instruction_0);
  70 }
  71
  72
  73
  74 // Helper:
  75 //
  76 // Simulate a 32 bit delayslot instruction
  77 //
  78
  79 :function:::address_word:delayslot32:address_word target
  80 {
  81   instruction_word delay_insn;
  82   sim_events_slip (SD, 1);
  83   DSPC = CIA;
  84   CIA = CIA + 4; /* NOTE not mips16 */
  85   STATE |= simDELAYSLOT;
  86   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  87   idecode_issue (CPU_, delay_insn, (CIA));
  88   STATE &= ~simDELAYSLOT;
  89   return target;
  90 }
  91
  92 :function:::address_word:nullify_next_insn32:
  93 {
  94   sim_events_slip (SD, 1);
  95   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  96   return CIA + 8;
  97 }
  98
  99
 100
 101 //
 102 // Mips Architecture:
 103 //
 104 //        CPU Instruction Set (mipsI - mipsIV)
 105 //
 106
 107
 108
 109 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 110 "add r<RD>, r<RS>, r<RT>"
 111 *mipsI,mipsII,mipsIII,mipsIV:
 112 *vr5000:
 113 // start-sanitize-vr4320
 114 *vr4320:
 115 // end-sanitize-vr4320
 116 // start-sanitize-vr5400
 117 *vr5400:
 118 // end-sanitize-vr5400
 119 // start-sanitize-r5900
 120 *r5900:
 121 // end-sanitize-r5900
 122 *r3900:
 123 // start-sanitize-tx19
 124 *tx19:
 125 // end-sanitize-tx19
 126 {
 127   ALU32_BEGIN (GPR[RS]);
 128   ALU32_ADD (GPR[RT]);
 129   ALU32_END (GPR[RD]);
 130 }
 131
 132
 133
 134 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 135 "addi r<RT>, r<RS>, IMMEDIATE"
 136 *mipsI,mipsII,mipsIII,mipsIV:
 137 *vr5000:
 138 // start-sanitize-vr4320
 139 *vr4320:
 140 // end-sanitize-vr4320
 141 // start-sanitize-vr5400
 142 *vr5400:
 143 // end-sanitize-vr5400
 144 // start-sanitize-r5900
 145 *r5900:
 146 // end-sanitize-r5900
 147 *r3900:
 148 // start-sanitize-tx19
 149 *tx19:
 150 // end-sanitize-tx19
 151 {
 152   ALU32_BEGIN (GPR[RS]);
 153   ALU32_ADD (EXTEND16 (IMMEDIATE));
 154   ALU32_END (GPR[RT]);
 155 }
 156
 157
 158
 159 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 160 {
 161   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 162   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 163   TRACE_ALU_RESULT (GPR[rt]);
 164 }
 165
 166 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 167 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 168 *mipsI,mipsII,mipsIII,mipsIV:
 169 *vr5000:
 170 // start-sanitize-vr4320
 171 *vr4320:
 172 // end-sanitize-vr4320
 173 // start-sanitize-vr5400
 174 *vr5400:
 175 // end-sanitize-vr5400
 176 // start-sanitize-r5900
 177 *r5900:
 178 // end-sanitize-r5900
 179 *r3900:
 180 // start-sanitize-tx19
 181 *tx19:
 182 // end-sanitize-tx19
 183 {
 184   do_addiu (SD_, RS, RT, IMMEDIATE);
 185 }
 186
 187
 188
 189 :function:::void:do_addu:int rs, int rt, int rd
 190 {
 191   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 192   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 193   TRACE_ALU_RESULT (GPR[rd]);
 194 }
 195
 196 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 197 "addu r<RD>, r<RS>, r<RT>"
 198 *mipsI,mipsII,mipsIII,mipsIV:
 199 *vr5000:
 200 // start-sanitize-vr4320
 201 *vr4320:
 202 // end-sanitize-vr4320
 203 // start-sanitize-vr5400
 204 *vr5400:
 205 // end-sanitize-vr5400
 206 // start-sanitize-r5900
 207 *r5900:
 208 // end-sanitize-r5900
 209 *r3900:
 210 // start-sanitize-tx19
 211 *tx19:
 212 // end-sanitize-tx19
 213 {
 214   do_addu (SD_, RS, RT, RD);
 215 }
 216
 217
 218
 219 :function:::void:do_and:int rs, int rt, int rd
 220 {
 221   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 222   GPR[rd] = GPR[rs] & GPR[rt];
 223   TRACE_ALU_RESULT (GPR[rd]);
 224 }
 225
 226 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 227 "and r<RD>, r<RS>, r<RT>"
 228 *mipsI,mipsII,mipsIII,mipsIV:
 229 *vr5000:
 230 // start-sanitize-vr4320
 231 *vr4320:
 232 // end-sanitize-vr4320
 233 // start-sanitize-vr5400
 234 *vr5400:
 235 // end-sanitize-vr5400
 236 // start-sanitize-r5900
 237 *r5900:
 238 // end-sanitize-r5900
 239 *r3900:
 240 // start-sanitize-tx19
 241 *tx19:
 242 // end-sanitize-tx19
 243 {
 244   do_and (SD_, RS, RT, RD);
 245 }
 246
 247
 248
 249 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 250 "and r<RT>, r<RS>, <IMMEDIATE>"
 251 *mipsI,mipsII,mipsIII,mipsIV:
 252 *vr5000:
 253 // start-sanitize-vr4320
 254 *vr4320:
 255 // end-sanitize-vr4320
 256 // start-sanitize-vr5400
 257 *vr5400:
 258 // end-sanitize-vr5400
 259 // start-sanitize-r5900
 260 *r5900:
 261 // end-sanitize-r5900
 262 *r3900:
 263 // start-sanitize-tx19
 264 *tx19:
 265 // end-sanitize-tx19
 266 {
 267   GPR[RT] = GPR[RS] & IMMEDIATE;
 268 }
 269
 270
 271
 272 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 273 "beq r<RS>, r<RT>, <OFFSET>"
 274 *mipsI,mipsII,mipsIII,mipsIV:
 275 *vr5000:
 276 // start-sanitize-vr4320
 277 *vr4320:
 278 // end-sanitize-vr4320
 279 // start-sanitize-vr5400
 280 *vr5400:
 281 // end-sanitize-vr5400
 282 // start-sanitize-r5900
 283 *r5900:
 284 // end-sanitize-r5900
 285 *r3900:
 286 // start-sanitize-tx19
 287 *tx19:
 288 // end-sanitize-tx19
 289 {
 290   address_word offset = EXTEND16 (OFFSET) << 2;
 291   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 292     DELAY_SLOT (NIA + offset);
 293 }
 294
 295
 296
 297 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 298 "beql r<RS>, r<RT>, <OFFSET>"
 299 *mipsII:
 300 *mipsIII:
 301 *mipsIV:
 302 *vr5000:
 303 // start-sanitize-vr4320
 304 *vr4320:
 305 // end-sanitize-vr4320
 306 // start-sanitize-vr5400
 307 *vr5400:
 308 // end-sanitize-vr5400
 309 // start-sanitize-r5900
 310 *r5900:
 311 // end-sanitize-r5900
 312 *r3900:
 313 // start-sanitize-tx19
 314 *tx19:
 315 // end-sanitize-tx19
 316 {
 317   address_word offset = EXTEND16 (OFFSET) << 2;
 318   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 319     DELAY_SLOT (NIA + offset);
 320   else
 321     NULLIFY_NEXT_INSTRUCTION ();
 322 }
 323
 324
 325
 326 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 327 "bgez r<RS>, <OFFSET>"
 328 *mipsI,mipsII,mipsIII,mipsIV:
 329 *vr5000:
 330 // start-sanitize-vr4320
 331 *vr4320:
 332 // end-sanitize-vr4320
 333 // start-sanitize-vr5400
 334 *vr5400:
 335 // end-sanitize-vr5400
 336 // start-sanitize-r5900
 337 *r5900:
 338 // end-sanitize-r5900
 339 *r3900:
 340 // start-sanitize-tx19
 341 *tx19:
 342 // end-sanitize-tx19
 343 {
 344   address_word offset = EXTEND16 (OFFSET) << 2;
 345   if ((signed_word) GPR[RS] >= 0)
 346     DELAY_SLOT (NIA + offset);
 347 }
 348
 349
 350
 351 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 352 "bgezal r<RS>, <OFFSET>"
 353 *mipsI,mipsII,mipsIII,mipsIV:
 354 *vr5000:
 355 // start-sanitize-vr4320
 356 *vr4320:
 357 // end-sanitize-vr4320
 358 // start-sanitize-vr5400
 359 *vr5400:
 360 // end-sanitize-vr5400
 361 // start-sanitize-r5900
 362 *r5900:
 363 // end-sanitize-r5900
 364 *r3900:
 365 // start-sanitize-tx19
 366 *tx19:
 367 // end-sanitize-tx19
 368 {
 369   address_word offset = EXTEND16 (OFFSET) << 2;
 370   RA = (CIA + 8);
 371   if ((signed_word) GPR[RS] >= 0)
 372     DELAY_SLOT (NIA + offset);
 373 }
 374
 375
 376
 377 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 378 "bgezall r<RS>, <OFFSET>"
 379 *mipsII:
 380 *mipsIII:
 381 *mipsIV:
 382 *vr5000:
 383 // start-sanitize-vr4320
 384 *vr4320:
 385 // end-sanitize-vr4320
 386 // start-sanitize-vr5400
 387 *vr5400:
 388 // end-sanitize-vr5400
 389 // start-sanitize-r5900
 390 *r5900:
 391 // end-sanitize-r5900
 392 *r3900:
 393 // start-sanitize-tx19
 394 *tx19:
 395 // end-sanitize-tx19
 396 {
 397   address_word offset = EXTEND16 (OFFSET) << 2;
 398   RA = (CIA + 8);
 399   /* NOTE: The branch occurs AFTER the next instruction has been
 400      executed */
 401   if ((signed_word) GPR[RS] >= 0)
 402     DELAY_SLOT (NIA + offset);
 403   else
 404     NULLIFY_NEXT_INSTRUCTION ();
 405 }
 406
 407
 408
 409 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 410 "bgezl r<RS>, <OFFSET>"
 411 *mipsII:
 412 *mipsIII:
 413 *mipsIV:
 414 *vr5000:
 415 // start-sanitize-vr4320
 416 *vr4320:
 417 // end-sanitize-vr4320
 418 // start-sanitize-vr5400
 419 *vr5400:
 420 // end-sanitize-vr5400
 421 // start-sanitize-r5900
 422 *r5900:
 423 // end-sanitize-r5900
 424 *r3900:
 425 // start-sanitize-tx19
 426 *tx19:
 427 // end-sanitize-tx19
 428 {
 429   address_word offset = EXTEND16 (OFFSET) << 2;
 430   if ((signed_word) GPR[RS] >= 0)
 431     DELAY_SLOT (NIA + offset);
 432   else
 433     NULLIFY_NEXT_INSTRUCTION ();
 434 }
 435
 436
 437
 438 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 439 "bgtz r<RS>, <OFFSET>"
 440 *mipsI,mipsII,mipsIII,mipsIV:
 441 *vr5000:
 442 // start-sanitize-vr4320
 443 *vr4320:
 444 // end-sanitize-vr4320
 445 // start-sanitize-vr5400
 446 *vr5400:
 447 // end-sanitize-vr5400
 448 // start-sanitize-r5900
 449 *r5900:
 450 // end-sanitize-r5900
 451 *r3900:
 452 // start-sanitize-tx19
 453 *tx19:
 454 // end-sanitize-tx19
 455 {
 456   address_word offset = EXTEND16 (OFFSET) << 2;
 457   if ((signed_word) GPR[RS] > 0)
 458     DELAY_SLOT (NIA + offset);
 459 }
 460
 461
 462
 463 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 464 "bgtzl r<RS>, <OFFSET>"
 465 *mipsII:
 466 *mipsIII:
 467 *mipsIV:
 468 *vr5000:
 469 // start-sanitize-vr4320
 470 *vr4320:
 471 // end-sanitize-vr4320
 472 // start-sanitize-vr5400
 473 *vr5400:
 474 // end-sanitize-vr5400
 475 // start-sanitize-r5900
 476 *r5900:
 477 // end-sanitize-r5900
 478 *r3900:
 479 // start-sanitize-tx19
 480 *tx19:
 481 // end-sanitize-tx19
 482 {
 483   address_word offset = EXTEND16 (OFFSET) << 2;
 484   /* NOTE: The branch occurs AFTER the next instruction has been
 485      executed */
 486   if ((signed_word) GPR[RS] > 0)
 487     DELAY_SLOT (NIA + offset);
 488   else
 489     NULLIFY_NEXT_INSTRUCTION ();
 490 }
 491
 492
 493
 494 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 495 "blez r<RS>, <OFFSET>"
 496 *mipsI,mipsII,mipsIII,mipsIV:
 497 *vr5000:
 498 // start-sanitize-vr4320
 499 *vr4320:
 500 // end-sanitize-vr4320
 501 // start-sanitize-vr5400
 502 *vr5400:
 503 // end-sanitize-vr5400
 504 // start-sanitize-r5900
 505 *r5900:
 506 // end-sanitize-r5900
 507 *r3900:
 508 // start-sanitize-tx19
 509 *tx19:
 510 // end-sanitize-tx19
 511 {
 512   address_word offset = EXTEND16 (OFFSET) << 2;
 513   /* NOTE: The branch occurs AFTER the next instruction has been
 514      executed */
 515   if ((signed_word) GPR[RS] <= 0)
 516     DELAY_SLOT (NIA + offset);
 517 }
 518
 519
 520
 521 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 522 "bgezl r<RS>, <OFFSET>"
 523 *mipsII:
 524 *mipsIII:
 525 *mipsIV:
 526 *vr5000:
 527 // start-sanitize-vr4320
 528 *vr4320:
 529 // end-sanitize-vr4320
 530 // start-sanitize-vr5400
 531 *vr5400:
 532 // end-sanitize-vr5400
 533 // start-sanitize-r5900
 534 *r5900:
 535 // end-sanitize-r5900
 536 *r3900:
 537 // start-sanitize-tx19
 538 *tx19:
 539 // end-sanitize-tx19
 540 {
 541   address_word offset = EXTEND16 (OFFSET) << 2;
 542   if ((signed_word) GPR[RS] <= 0)
 543     DELAY_SLOT (NIA + offset);
 544   else
 545     NULLIFY_NEXT_INSTRUCTION ();
 546 }
 547
 548
 549
 550 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 551 "bltz r<RS>, <OFFSET>"
 552 *mipsI,mipsII,mipsIII,mipsIV:
 553 *vr5000:
 554 // start-sanitize-vr4320
 555 *vr4320:
 556 // end-sanitize-vr4320
 557 // start-sanitize-vr5400
 558 *vr5400:
 559 // end-sanitize-vr5400
 560 // start-sanitize-r5900
 561 *r5900:
 562 // end-sanitize-r5900
 563 *r3900:
 564 // start-sanitize-tx19
 565 *tx19:
 566 // end-sanitize-tx19
 567 {
 568   address_word offset = EXTEND16 (OFFSET) << 2;
 569   if ((signed_word) GPR[RS] < 0)
 570     DELAY_SLOT (NIA + offset);
 571 }
 572
 573
 574
 575 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 576 "bltzal r<RS>, <OFFSET>"
 577 *mipsI,mipsII,mipsIII,mipsIV:
 578 *vr5000:
 579 // start-sanitize-vr4320
 580 *vr4320:
 581 // end-sanitize-vr4320
 582 // start-sanitize-vr5400
 583 *vr5400:
 584 // end-sanitize-vr5400
 585 // start-sanitize-r5900
 586 *r5900:
 587 // end-sanitize-r5900
 588 *r3900:
 589 // start-sanitize-tx19
 590 *tx19:
 591 // end-sanitize-tx19
 592 {
 593   address_word offset = EXTEND16 (OFFSET) << 2;
 594   RA = (CIA + 8);
 595   /* NOTE: The branch occurs AFTER the next instruction has been
 596      executed */
 597   if ((signed_word) GPR[RS] < 0)
 598     DELAY_SLOT (NIA + offset);
 599 }
 600
 601
 602
 603 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 604 "bltzall r<RS>, <OFFSET>"
 605 *mipsII:
 606 *mipsIII:
 607 *mipsIV:
 608 *vr5000:
 609 // start-sanitize-vr4320
 610 *vr4320:
 611 // end-sanitize-vr4320
 612 // start-sanitize-vr5400
 613 *vr5400:
 614 // end-sanitize-vr5400
 615 // start-sanitize-r5900
 616 *r5900:
 617 // end-sanitize-r5900
 618 *r3900:
 619 // start-sanitize-tx19
 620 *tx19:
 621 // end-sanitize-tx19
 622 {
 623   address_word offset = EXTEND16 (OFFSET) << 2;
 624   RA = (CIA + 8);
 625   if ((signed_word) GPR[RS] < 0)
 626     DELAY_SLOT (NIA + offset);
 627   else
 628     NULLIFY_NEXT_INSTRUCTION ();
 629 }
 630
 631
 632
 633 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 634 "bltzl r<RS>, <OFFSET>"
 635 *mipsII:
 636 *mipsIII:
 637 *mipsIV:
 638 *vr5000:
 639 // start-sanitize-vr4320
 640 *vr4320:
 641 // end-sanitize-vr4320
 642 // start-sanitize-vr5400
 643 *vr5400:
 644 // end-sanitize-vr5400
 645 // start-sanitize-r5900
 646 *r5900:
 647 // end-sanitize-r5900
 648 *r3900:
 649 // start-sanitize-tx19
 650 *tx19:
 651 // end-sanitize-tx19
 652 {
 653   address_word offset = EXTEND16 (OFFSET) << 2;
 654   /* NOTE: The branch occurs AFTER the next instruction has been
 655      executed */
 656   if ((signed_word) GPR[RS] < 0)
 657     DELAY_SLOT (NIA + offset);
 658   else
 659     NULLIFY_NEXT_INSTRUCTION ();
 660 }
 661
 662
 663
 664 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 665 "bne r<RS>, r<RT>, <OFFSET>"
 666 *mipsI,mipsII,mipsIII,mipsIV:
 667 *vr5000:
 668 // start-sanitize-vr4320
 669 *vr4320:
 670 // end-sanitize-vr4320
 671 // start-sanitize-vr5400
 672 *vr5400:
 673 // end-sanitize-vr5400
 674 // start-sanitize-r5900
 675 *r5900:
 676 // end-sanitize-r5900
 677 *r3900:
 678 // start-sanitize-tx19
 679 *tx19:
 680 // end-sanitize-tx19
 681 {
 682   address_word offset = EXTEND16 (OFFSET) << 2;
 683   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 684     DELAY_SLOT (NIA + offset);
 685 }
 686
 687
 688
 689 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 690 "bnel r<RS>, r<RT>, <OFFSET>"
 691 *mipsII:
 692 *mipsIII:
 693 *mipsIV:
 694 *vr5000:
 695 // start-sanitize-vr4320
 696 *vr4320:
 697 // end-sanitize-vr4320
 698 // start-sanitize-vr5400
 699 *vr5400:
 700 // end-sanitize-vr5400
 701 // start-sanitize-r5900
 702 *r5900:
 703 // end-sanitize-r5900
 704 *r3900:
 705 // start-sanitize-tx19
 706 *tx19:
 707 // end-sanitize-tx19
 708 {
 709   address_word offset = EXTEND16 (OFFSET) << 2;
 710   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 711     DELAY_SLOT (NIA + offset);
 712   else
 713     NULLIFY_NEXT_INSTRUCTION ();
 714 }
 715
 716
 717
 718 000000,20.CODE,001101:SPECIAL:32::BREAK
 719 "break"
 720 *mipsI,mipsII,mipsIII,mipsIV:
 721 *vr5000:
 722 // start-sanitize-vr4320
 723 *vr4320:
 724 // end-sanitize-vr4320
 725 // start-sanitize-vr5400
 726 *vr5400:
 727 // end-sanitize-vr5400
 728 // start-sanitize-r5900
 729 *r5900:
 730 // end-sanitize-r5900
 731 *r3900:
 732 // start-sanitize-tx19
 733 *tx19:
 734 // end-sanitize-tx19
 735 {
 736   SignalException(BreakPoint, instruction_0);
 737 }
 738
 739
 740
 741 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 742 "cop<ZZ> <COP_FUN>"
 743 *mipsI,mipsII,mipsIII,mipsIV:
 744 // start-sanitize-r5900
 745 *r5900:
 746 // end-sanitize-r5900
 747 *r3900:
 748 // start-sanitize-tx19
 749 *tx19:
 750 // end-sanitize-tx19
 751 {
 752   DecodeCoproc (instruction_0);
 753 }
 754
 755
 756
 757 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 758 "dadd r<RD>, r<RS>, r<RT>"
 759 *mipsIII:
 760 *mipsIV:
 761 *vr5000:
 762 // start-sanitize-vr4320
 763 *vr4320:
 764 // end-sanitize-vr4320
 765 // start-sanitize-vr5400
 766 *vr5400:
 767 // end-sanitize-vr5400
 768 // start-sanitize-r5900
 769 *r5900:
 770 // end-sanitize-r5900
 771 // start-sanitize-tx19
 772 *tx19:
 773 // end-sanitize-tx19
 774 {
 775   /* this check's for overflow */
 776   ALU64_BEGIN (GPR[RS]);
 777   ALU64_ADD (GPR[RT]);
 778   ALU64_END (GPR[RD]);
 779 }
 780
 781
 782
 783 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 784 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 785 *mipsIII:
 786 *mipsIV:
 787 *vr5000:
 788 // start-sanitize-vr4320
 789 *vr4320:
 790 // end-sanitize-vr4320
 791 // start-sanitize-vr5400
 792 *vr5400:
 793 // end-sanitize-vr5400
 794 // start-sanitize-r5900
 795 *r5900:
 796 // end-sanitize-r5900
 797 // start-sanitize-tx19
 798 *tx19:
 799 // end-sanitize-tx19
 800 {
 801   ALU64_BEGIN (GPR[RS]);
 802   ALU64_ADD (EXTEND16 (IMMEDIATE));
 803   ALU64_END (GPR[RT]);
 804 }
 805
 806
 807
 808 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
 809 {
 810   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 811   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
 812   TRACE_ALU_RESULT (GPR[rt]);
 813 }
 814
 815 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 816 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 817 *mipsIII:
 818 *mipsIV:
 819 *vr5000:
 820 // start-sanitize-vr4320
 821 *vr4320:
 822 // end-sanitize-vr4320
 823 // start-sanitize-vr5400
 824 *vr5400:
 825 // end-sanitize-vr5400
 826 // start-sanitize-r5900
 827 *r5900:
 828 // end-sanitize-r5900
 829 // start-sanitize-tx19
 830 *tx19:
 831 // end-sanitize-tx19
 832 {
 833   do_daddiu (SD_, RS, RT, IMMEDIATE);
 834 }
 835
 836
 837
 838 :function:::void:do_daddu:int rs, int rt, int rd
 839 {
 840   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 841   GPR[rd] = GPR[rs] + GPR[rt];
 842   TRACE_ALU_RESULT (GPR[rd]);
 843 }
 844
 845 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 846 "daddu r<RD>, r<RS>, r<RT>"
 847 *mipsIII:
 848 *mipsIV:
 849 *vr5000:
 850 // start-sanitize-vr4320
 851 *vr4320:
 852 // end-sanitize-vr4320
 853 // start-sanitize-vr5400
 854 *vr5400:
 855 // end-sanitize-vr5400
 856 // start-sanitize-r5900
 857 *r5900:
 858 // end-sanitize-r5900
 859 // start-sanitize-tx19
 860 *tx19:
 861 // end-sanitize-tx19
 862 {
 863   do_daddu (SD_, RS, RT, RD);
 864 }
 865
 866
 867
 868 :function:64::void:do_ddiv:int rs, int rt
 869 {
 870   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 871   CHECKHILO ("Division");
 872   {
 873     signed64 n = GPR[rs];
 874     signed64 d = GPR[rt];
 875     if (d == 0)
 876       {
 877         LO = SIGNED64 (0x8000000000000000);
 878         HI = 0;
 879       }
 880     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 881       {
 882         LO = SIGNED64 (0x8000000000000000);
 883         HI = 0;
 884       }
 885     else
 886       {
 887         LO = (n / d);
 888         HI = (n % d);
 889       }
 890   }
 891   TRACE_ALU_RESULT2 (HI, LO);
 892 }
 893
 894 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 895 "ddiv r<RS>, r<RT>"
 896 *mipsIII:
 897 *mipsIV:
 898 *vr5000:
 899 // start-sanitize-vr4320
 900 *vr4320:
 901 // end-sanitize-vr4320
 902 // start-sanitize-vr5400
 903 *vr5400:
 904 // end-sanitize-vr5400
 905 // start-sanitize-r5900
 906 *r5900:
 907 // end-sanitize-r5900
 908 // start-sanitize-tx19
 909 *tx19:
 910 // end-sanitize-tx19
 911 {
 912   do_ddiv (SD_, RS, RT);
 913 }
 914
 915
 916
 917 :function:64::void:do_ddivu:int rs, int rt
 918 {
 919   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 920   CHECKHILO ("Division");
 921   {
 922     unsigned64 n = GPR[rs];
 923     unsigned64 d = GPR[rt];
 924     if (d == 0)
 925       {
 926         LO = SIGNED64 (0x8000000000000000);
 927         HI = 0;
 928       }
 929     else
 930       {
 931         LO = (n / d);
 932         HI = (n % d);
 933       }
 934   }
 935   TRACE_ALU_RESULT2 (HI, LO);
 936 }
 937
 938 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 939 "ddivu r<RS>, r<RT>"
 940 *mipsIII:
 941 *mipsIV:
 942 *vr5000:
 943 // start-sanitize-vr4320
 944 *vr4320:
 945 // end-sanitize-vr4320
 946 // start-sanitize-vr5400
 947 *vr5400:
 948 // end-sanitize-vr5400
 949 // start-sanitize-tx19
 950 *tx19:
 951 // end-sanitize-tx19
 952 {
 953   do_ddivu (SD_, RS, RT);
 954 }
 955
 956
 957
 958 :function:::void:do_div:int rs, int rt
 959 {
 960   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 961   CHECKHILO("Division");
 962   {
 963     signed32 n = GPR[rs];
 964     signed32 d = GPR[rt];
 965     if (d == 0)
 966       {
 967         LO = EXTEND32 (0x80000000);
 968         HI = EXTEND32 (0);
 969       }
 970     else if (n == SIGNED32 (0x80000000) && d == -1)
 971       {
 972         LO = EXTEND32 (0x80000000);
 973         HI = EXTEND32 (0);
 974       }
 975     else
 976       {
 977         LO = EXTEND32 (n / d);
 978         HI = EXTEND32 (n % d);
 979       }
 980   }
 981   TRACE_ALU_RESULT2 (HI, LO);
 982 }
 983
 984 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 985 "div r<RS>, r<RT>"
 986 *mipsI,mipsII,mipsIII,mipsIV:
 987 *vr5000:
 988 // start-sanitize-vr4320
 989 *vr4320:
 990 // end-sanitize-vr4320
 991 // start-sanitize-vr5400
 992 *vr5400:
 993 // end-sanitize-vr5400
 994 // start-sanitize-r5900
 995 *r5900:
 996 // end-sanitize-r5900
 997 *r3900:
 998 // start-sanitize-tx19
 999 *tx19:
1000 // end-sanitize-tx19
1001 {
1002   do_div (SD_, RS, RT);
1003 }
1004
1005
1006
1007 :function:::void:do_divu:int rs, int rt
1008 {
1009   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1010   CHECKHILO ("Division");
1011   {
1012     unsigned32 n = GPR[rs];
1013     unsigned32 d = GPR[rt];
1014     if (d == 0)
1015       {
1016         LO = EXTEND32 (0x80000000);
1017         HI = EXTEND32 (0);
1018       }
1019    else
1020      {
1021        LO = EXTEND32 (n / d);
1022        HI = EXTEND32 (n % d);
1023      }
1024   }
1025   TRACE_ALU_RESULT2 (HI, LO);
1026 }
1027
1028 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1029 "divu r<RS>, r<RT>"
1030 *mipsI,mipsII,mipsIII,mipsIV:
1031 *vr5000:
1032 // start-sanitize-vr4320
1033 *vr4320:
1034 // end-sanitize-vr4320
1035 // start-sanitize-vr5400
1036 *vr5400:
1037 // end-sanitize-vr5400
1038 // start-sanitize-r5900
1039 *r5900:
1040 // end-sanitize-r5900
1041 *r3900:
1042 // start-sanitize-tx19
1043 *tx19:
1044 // end-sanitize-tx19
1045 {
1046   do_divu (SD_, RS, RT);
1047 }
1048
1049
1050
1051 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1052 {
1053   unsigned64 lo;
1054   unsigned64 hi;
1055   unsigned64 m00;
1056   unsigned64 m01;
1057   unsigned64 m10;
1058   unsigned64 m11;
1059   unsigned64 mid;
1060   int sign;
1061   unsigned64 op1 = GPR[rs];
1062   unsigned64 op2 = GPR[rt];
1063   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1064   CHECKHILO ("Multiplication");
1065   /* make signed multiply unsigned */
1066   sign = 0;
1067   if (signed_p)
1068     {
1069       if (op1 < 0)
1070         {
1071           op1 = - op1;
1072           ++sign;
1073         }
1074       if (op2 < 0)
1075         {
1076           op2 = - op2;
1077           ++sign;
1078         }
1079     }
1080   /* multuply out the 4 sub products */
1081   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1082   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1083   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1084   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1085   /* add the products */
1086   mid = ((unsigned64) VH4_8 (m00)
1087          + (unsigned64) VL4_8 (m10)
1088          + (unsigned64) VL4_8 (m01));
1089   lo = U8_4 (mid, m00);
1090   hi = (m11
1091         + (unsigned64) VH4_8 (mid)
1092         + (unsigned64) VH4_8 (m01)
1093         + (unsigned64) VH4_8 (m10));
1094   /* fix the sign */
1095   if (sign & 1)
1096     {
1097       lo = -lo;
1098       if (lo == 0)
1099         hi = -hi;
1100       else
1101         hi = -hi - 1;
1102     }
1103   /* save the result HI/LO (and a gpr) */
1104   LO = lo;
1105   HI = hi;
1106   if (rd != 0)
1107     GPR[rd] = lo;
1108   TRACE_ALU_RESULT2 (HI, LO);
1109 }
1110
1111 :function:::void:do_dmult:int rs, int rt, int rd
1112 {
1113   do_dmultx (SD_, rs, rt, rd, 1);
1114 }
1115
1116 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1117 "dmult r<RS>, r<RT>"
1118 *mipsIII,mipsIV:
1119 // start-sanitize-tx19
1120 *tx19:
1121 // end-sanitize-tx19
1122 // start-sanitize-vr4320
1123 *vr4320:
1124 // end-sanitize-vr4320
1125 {
1126   do_dmult (SD_, RS, RT, 0);
1127 }
1128
1129 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1130 "dmult r<RS>, r<RT>":RD == 0
1131 "dmult r<RD>, r<RS>, r<RT>"
1132 *vr5000:
1133 // start-sanitize-vr5400
1134 *vr5400:
1135 // end-sanitize-vr5400
1136 {
1137   do_dmult (SD_, RS, RT, RD);
1138 }
1139
1140
1141
1142 :function:::void:do_dmultu:int rs, int rt, int rd
1143 {
1144   do_dmultx (SD_, rs, rt, rd, 0);
1145 }
1146
1147 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1148 "dmultu r<RS>, r<RT>"
1149 *mipsIII,mipsIV:
1150 // start-sanitize-tx19
1151 *tx19:
1152 // end-sanitize-tx19
1153 // start-sanitize-vr4320
1154 *vr4320:
1155 // end-sanitize-vr4320
1156 {
1157   do_dmultu (SD_, RS, RT, 0);
1158 }
1159
1160 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1161 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1162 "dmultu r<RS>, r<RT>"
1163 *vr5000:
1164 // start-sanitize-vr5400
1165 *vr5400:
1166 // end-sanitize-vr5400
1167 {
1168   do_dmultu (SD_, RS, RT, RD);
1169 }
1170
1171
1172
1173 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1174 "dsll r<RD>, r<RT>, <SHIFT>"
1175 *mipsIII:
1176 *mipsIV:
1177 *vr5000:
1178 // start-sanitize-vr4320
1179 *vr4320:
1180 // end-sanitize-vr4320
1181 // start-sanitize-vr5400
1182 *vr5400:
1183 // end-sanitize-vr5400
1184 // start-sanitize-r5900
1185 *r5900:
1186 // end-sanitize-r5900
1187 // start-sanitize-tx19
1188 *tx19:
1189 // end-sanitize-tx19
1190 {
1191   int s = SHIFT;
1192   GPR[RD] = GPR[RT] << s;
1193 }
1194
1195
1196 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1197 "dsll32 r<RD>, r<RT>, <SHIFT>"
1198 *mipsIII:
1199 *mipsIV:
1200 *vr5000:
1201 // start-sanitize-vr4320
1202 *vr4320:
1203 // end-sanitize-vr4320
1204 // start-sanitize-vr5400
1205 *vr5400:
1206 // end-sanitize-vr5400
1207 // start-sanitize-r5900
1208 *r5900:
1209 // end-sanitize-r5900
1210 // start-sanitize-tx19
1211 *tx19:
1212 // end-sanitize-tx19
1213 {
1214   int s = 32 + SHIFT;
1215   GPR[RD] = GPR[RT] << s;
1216 }
1217
1218
1219
1220 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1221 "dsllv r<RD>, r<RT>, r<RS>"
1222 *mipsIII:
1223 *mipsIV:
1224 *vr5000:
1225 // start-sanitize-vr4320
1226 *vr4320:
1227 // end-sanitize-vr4320
1228 // start-sanitize-vr5400
1229 *vr5400:
1230 // end-sanitize-vr5400
1231 // start-sanitize-r5900
1232 *r5900:
1233 // end-sanitize-r5900
1234 // start-sanitize-tx19
1235 *tx19:
1236 // end-sanitize-tx19
1237 {
1238   int s = MASKED64 (GPR[RS], 5, 0);
1239   GPR[RD] = GPR[RT] << s;
1240 }
1241
1242
1243
1244 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1245 "dsra r<RD>, r<RT>, <SHIFT>"
1246 *mipsIII:
1247 *mipsIV:
1248 *vr5000:
1249 // start-sanitize-vr4320
1250 *vr4320:
1251 // end-sanitize-vr4320
1252 // start-sanitize-vr5400
1253 *vr5400:
1254 // end-sanitize-vr5400
1255 // start-sanitize-r5900
1256 *r5900:
1257 // end-sanitize-r5900
1258 // start-sanitize-tx19
1259 *tx19:
1260 // end-sanitize-tx19
1261 {
1262   int s = SHIFT;
1263   GPR[RD] = ((signed64) GPR[RT]) >> s;
1264 }
1265
1266
1267 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1268 "dsra32 r<RT>, r<RD>, <SHIFT>"
1269 *mipsIII:
1270 *mipsIV:
1271 *vr5000:
1272 // start-sanitize-vr4320
1273 *vr4320:
1274 // end-sanitize-vr4320
1275 // start-sanitize-vr5400
1276 *vr5400:
1277 // end-sanitize-vr5400
1278 // start-sanitize-r5900
1279 *r5900:
1280 // end-sanitize-r5900
1281 // start-sanitize-tx19
1282 *tx19:
1283 // end-sanitize-tx19
1284 {
1285   int s = 32 + SHIFT;
1286   GPR[RD] = ((signed64) GPR[RT]) >> s;
1287 }
1288
1289
1290 :function:::void:do_srav:int rs, int rt, int rd
1291 {
1292   int s = MASKED64 (GPR[rs], 5, 0);
1293   TRACE_ALU_INPUT2 (GPR[rt], s);
1294   GPR[rd] = ((signed64) GPR[rt]) >> s;
1295   TRACE_ALU_RESULT (GPR[rd]);
1296 }
1297
1298 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1299 "dsra32 r<RT>, r<RD>, r<RS>"
1300 *mipsIII:
1301 *mipsIV:
1302 *vr5000:
1303 // start-sanitize-vr4320
1304 *vr4320:
1305 // end-sanitize-vr4320
1306 // start-sanitize-vr5400
1307 *vr5400:
1308 // end-sanitize-vr5400
1309 // start-sanitize-r5900
1310 *r5900:
1311 // end-sanitize-r5900
1312 // start-sanitize-tx19
1313 *tx19:
1314 // end-sanitize-tx19
1315 {
1316   do_srav (SD_, RS, RT, RD);
1317 }
1318
1319
1320 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1321 "dsrav r<RD>, r<RT>, <SHIFT>"
1322 *mipsIII:
1323 *mipsIV:
1324 *vr5000:
1325 // start-sanitize-vr4320
1326 *vr4320:
1327 // end-sanitize-vr4320
1328 // start-sanitize-vr5400
1329 *vr5400:
1330 // end-sanitize-vr5400
1331 // start-sanitize-r5900
1332 *r5900:
1333 // end-sanitize-r5900
1334 // start-sanitize-tx19
1335 *tx19:
1336 // end-sanitize-tx19
1337 {
1338   int s = SHIFT;
1339   GPR[RD] = (unsigned64) GPR[RT] >> s;
1340 }
1341
1342
1343 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1344 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1345 *mipsIII:
1346 *mipsIV:
1347 *vr5000:
1348 // start-sanitize-vr4320
1349 *vr4320:
1350 // end-sanitize-vr4320
1351 // start-sanitize-vr5400
1352 *vr5400:
1353 // end-sanitize-vr5400
1354 // start-sanitize-r5900
1355 *r5900:
1356 // end-sanitize-r5900
1357 // start-sanitize-tx19
1358 *tx19:
1359 // end-sanitize-tx19
1360 {
1361   int s = 32 + SHIFT;
1362   GPR[RD] = (unsigned64) GPR[RT] >> s;
1363 }
1364
1365
1366 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1367 "dsrl32 r<RD>, r<RT>, r<RS>"
1368 *mipsIII:
1369 *mipsIV:
1370 *vr5000:
1371 // start-sanitize-vr4320
1372 *vr4320:
1373 // end-sanitize-vr4320
1374 // start-sanitize-vr5400
1375 *vr5400:
1376 // end-sanitize-vr5400
1377 // start-sanitize-r5900
1378 *r5900:
1379 // end-sanitize-r5900
1380 // start-sanitize-tx19
1381 *tx19:
1382 // end-sanitize-tx19
1383 {
1384   int s = MASKED64 (GPR[RS], 5, 0);
1385   GPR[RD] = (unsigned64) GPR[RT] >> s;
1386 }
1387
1388
1389 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1390 "dsub r<RD>, r<RS>, r<RT>"
1391 *mipsIII:
1392 *mipsIV:
1393 *vr5000:
1394 // start-sanitize-vr4320
1395 *vr4320:
1396 // end-sanitize-vr4320
1397 // start-sanitize-vr5400
1398 *vr5400:
1399 // end-sanitize-vr5400
1400 // start-sanitize-r5900
1401 *r5900:
1402 // end-sanitize-r5900
1403 // start-sanitize-tx19
1404 *tx19:
1405 // end-sanitize-tx19
1406 {
1407   ALU64_BEGIN (GPR[RS]);
1408   ALU64_SUB (GPR[RT]);
1409   ALU64_END (GPR[RD]);
1410 }
1411
1412
1413 :function:::void:do_dsubu:int rs, int rt, int rd
1414 {
1415   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1416   GPR[rd] = GPR[rs] - GPR[rt];
1417   TRACE_ALU_RESULT (GPR[rd]);
1418 }
1419
1420 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1421 "dsubu r<RD>, r<RS>, r<RT>"
1422 *mipsIII:
1423 *mipsIV:
1424 *vr5000:
1425 // start-sanitize-vr4320
1426 *vr4320:
1427 // end-sanitize-vr4320
1428 // start-sanitize-vr5400
1429 *vr5400:
1430 // end-sanitize-vr5400
1431 // start-sanitize-r5900
1432 *r5900:
1433 // end-sanitize-r5900
1434 // start-sanitize-tx19
1435 *tx19:
1436 // end-sanitize-tx19
1437 {
1438   do_dsubu (SD_, RS, RT, RD);
1439 }
1440
1441
1442 000010,26.INSTR_INDEX:NORMAL:32::J
1443 "j <INSTR_INDEX>"
1444 *mipsI,mipsII,mipsIII,mipsIV:
1445 *vr5000:
1446 // start-sanitize-vr4320
1447 *vr4320:
1448 // end-sanitize-vr4320
1449 // start-sanitize-vr5400
1450 *vr5400:
1451 // end-sanitize-vr5400
1452 // start-sanitize-r5900
1453 *r5900:
1454 // end-sanitize-r5900
1455 *r3900:
1456 // start-sanitize-tx19
1457 *tx19:
1458 // end-sanitize-tx19
1459 {
1460   /* NOTE: The region used is that of the delay slot NIA and NOT the
1461      current instruction */
1462   address_word region = (NIA & MASK (63, 28));
1463   DELAY_SLOT (region | (INSTR_INDEX << 2));
1464 }
1465
1466
1467 000011,26.INSTR_INDEX:NORMAL:32::JAL
1468 "jal <INSTR_INDEX>"
1469 *mipsI,mipsII,mipsIII,mipsIV:
1470 *vr5000:
1471 // start-sanitize-vr4320
1472 *vr4320:
1473 // end-sanitize-vr4320
1474 // start-sanitize-vr5400
1475 *vr5400:
1476 // end-sanitize-vr5400
1477 // start-sanitize-r5900
1478 *r5900:
1479 // end-sanitize-r5900
1480 *r3900:
1481 // start-sanitize-tx19
1482 *tx19:
1483 // end-sanitize-tx19
1484 {
1485   /* NOTE: The region used is that of the delay slot and NOT the
1486      current instruction */
1487   address_word region = (NIA & MASK (63, 28));
1488   GPR[31] = CIA + 8;
1489   DELAY_SLOT (region | (INSTR_INDEX << 2));
1490 }
1491
1492
1493 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1494 "jalr r<RS>":RD == 31
1495 "jalr r<RD>, r<RS>"
1496 *mipsI,mipsII,mipsIII,mipsIV:
1497 *vr5000:
1498 // start-sanitize-vr4320
1499 *vr4320:
1500 // end-sanitize-vr4320
1501 // start-sanitize-vr5400
1502 *vr5400:
1503 // end-sanitize-vr5400
1504 // start-sanitize-r5900
1505 *r5900:
1506 // end-sanitize-r5900
1507 *r3900:
1508 // start-sanitize-tx19
1509 *tx19:
1510 // end-sanitize-tx19
1511 {
1512   address_word temp = GPR[RS];
1513   GPR[RD] = CIA + 8;
1514   DELAY_SLOT (temp);
1515 }
1516
1517
1518 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1519 "jr r<RS>"
1520 *mipsI,mipsII,mipsIII,mipsIV:
1521 *vr5000:
1522 // start-sanitize-vr4320
1523 *vr4320:
1524 // end-sanitize-vr4320
1525 // start-sanitize-vr5400
1526 *vr5400:
1527 // end-sanitize-vr5400
1528 // start-sanitize-r5900
1529 *r5900:
1530 // end-sanitize-r5900
1531 *r3900:
1532 // start-sanitize-tx19
1533 *tx19:
1534 // end-sanitize-tx19
1535 {
1536   DELAY_SLOT (GPR[RS]);
1537 }
1538
1539
1540 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1541 {
1542   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1543   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1544   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1545   unsigned int byte;
1546   address_word paddr;
1547   int uncached;
1548   unsigned64 memval;
1549   address_word vaddr;
1550
1551   vaddr = base + offset;
1552   if ((vaddr & access) != 0)
1553     SignalExceptionAddressLoad ();
1554   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1555   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1556   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1557   byte = ((vaddr & mask) ^ bigendiancpu);
1558   return (memval >> (8 * byte));
1559 }
1560
1561
1562 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1563 "lb r<RT>, <OFFSET>(r<BASE>)"
1564 *mipsI,mipsII,mipsIII,mipsIV:
1565 *vr5000:
1566 // start-sanitize-vr4320
1567 *vr4320:
1568 // end-sanitize-vr4320
1569 // start-sanitize-vr5400
1570 *vr5400:
1571 // end-sanitize-vr5400
1572 // start-sanitize-r5900
1573 *r5900:
1574 // end-sanitize-r5900
1575 *r3900:
1576 // start-sanitize-tx19
1577 *tx19:
1578 // end-sanitize-tx19
1579 {
1580   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1581 }
1582
1583
1584 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1585 "lbu r<RT>, <OFFSET>(r<BASE>)"
1586 *mipsI,mipsII,mipsIII,mipsIV:
1587 *vr5000:
1588 // start-sanitize-vr4320
1589 *vr4320:
1590 // end-sanitize-vr4320
1591 // start-sanitize-vr5400
1592 *vr5400:
1593 // end-sanitize-vr5400
1594 // start-sanitize-r5900
1595 *r5900:
1596 // end-sanitize-r5900
1597 *r3900:
1598 // start-sanitize-tx19
1599 *tx19:
1600 // end-sanitize-tx19
1601 {
1602   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1603 }
1604
1605
1606 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1607 "ld r<RT>, <OFFSET>(r<BASE>)"
1608 *mipsIII:
1609 *mipsIV:
1610 *vr5000:
1611 // start-sanitize-vr4320
1612 *vr4320:
1613 // end-sanitize-vr4320
1614 // start-sanitize-vr5400
1615 *vr5400:
1616 // end-sanitize-vr5400
1617 // start-sanitize-r5900
1618 *r5900:
1619 // end-sanitize-r5900
1620 // start-sanitize-tx19
1621 *tx19:
1622 // end-sanitize-tx19
1623 {
1624   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1625 }
1626
1627
1628 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1629 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1630 *mipsII:
1631 *mipsIII:
1632 *mipsIV:
1633 *vr5000:
1634 // start-sanitize-vr4320
1635 *vr4320:
1636 // end-sanitize-vr4320
1637 // start-sanitize-vr5400
1638 *vr5400:
1639 // end-sanitize-vr5400
1640 *r3900:
1641 // start-sanitize-tx19
1642 *tx19:
1643 // end-sanitize-tx19
1644 {
1645   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1646 }
1647
1648
1649
1650
1651 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1652 "ldl r<RT>, <OFFSET>(r<BASE>)"
1653 *mipsIII:
1654 *mipsIV:
1655 *vr5000:
1656 // start-sanitize-vr4320
1657 *vr4320:
1658 // end-sanitize-vr4320
1659 // start-sanitize-vr5400
1660 *vr5400:
1661 // end-sanitize-vr5400
1662 // start-sanitize-r5900
1663 *r5900:
1664 // end-sanitize-r5900
1665 // start-sanitize-tx19
1666 *tx19:
1667 // end-sanitize-tx19
1668 {
1669   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1670 }
1671
1672
1673 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1674 "ldr r<RT>, <OFFSET>(r<BASE>)"
1675 *mipsIII:
1676 *mipsIV:
1677 *vr5000:
1678 // start-sanitize-vr4320
1679 *vr4320:
1680 // end-sanitize-vr4320
1681 // start-sanitize-vr5400
1682 *vr5400:
1683 // end-sanitize-vr5400
1684 // start-sanitize-r5900
1685 *r5900:
1686 // end-sanitize-r5900
1687 // start-sanitize-tx19
1688 *tx19:
1689 // end-sanitize-tx19
1690 {
1691   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1692 }
1693
1694
1695 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1696 "lh r<RT>, <OFFSET>(r<BASE>)"
1697 *mipsI,mipsII,mipsIII,mipsIV:
1698 *vr5000:
1699 // start-sanitize-vr4320
1700 *vr4320:
1701 // end-sanitize-vr4320
1702 // start-sanitize-vr5400
1703 *vr5400:
1704 // end-sanitize-vr5400
1705 // start-sanitize-r5900
1706 *r5900:
1707 // end-sanitize-r5900
1708 *r3900:
1709 // start-sanitize-tx19
1710 *tx19:
1711 // end-sanitize-tx19
1712 {
1713   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1714 }
1715
1716
1717 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1718 "lhu r<RT>, <OFFSET>(r<BASE>)"
1719 *mipsI,mipsII,mipsIII,mipsIV:
1720 *vr5000:
1721 // start-sanitize-vr4320
1722 *vr4320:
1723 // end-sanitize-vr4320
1724 // start-sanitize-vr5400
1725 *vr5400:
1726 // end-sanitize-vr5400
1727 // start-sanitize-r5900
1728 *r5900:
1729 // end-sanitize-r5900
1730 *r3900:
1731 // start-sanitize-tx19
1732 *tx19:
1733 // end-sanitize-tx19
1734 {
1735   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1736 }
1737
1738
1739 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1740 "ll r<RT>, <OFFSET>(r<BASE>)"
1741 *mipsII:
1742 *mipsIII:
1743 *mipsIV:
1744 *vr5000:
1745 // start-sanitize-vr4320
1746 *vr4320:
1747 // end-sanitize-vr4320
1748 // start-sanitize-vr5400
1749 *vr5400:
1750 // end-sanitize-vr5400
1751 // start-sanitize-r5900
1752 *r5900:
1753 // end-sanitize-r5900
1754 // start-sanitize-tx19
1755 *tx19:
1756 // end-sanitize-tx19
1757 {
1758   unsigned32 instruction = instruction_0;
1759   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1760   int destreg = ((instruction >> 16) & 0x0000001F);
1761   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1762   {
1763     address_word vaddr = ((unsigned64)op1 + offset);
1764     address_word paddr;
1765     int uncached;
1766     if ((vaddr & 3) != 0)
1767       SignalExceptionAddressLoad();
1768     else
1769       {
1770         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1771           {
1772             unsigned64 memval = 0;
1773             unsigned64 memval1 = 0;
1774             unsigned64 mask = 0x7;
1775             unsigned int shift = 2;
1776             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1777             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1778             unsigned int byte;
1779             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1780             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1781             byte = ((vaddr & mask) ^ (bigend << shift));
1782             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1783             LLBIT = 1;
1784           }
1785       }
1786   }
1787 }
1788
1789
1790 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1791 "lld r<RT>, <OFFSET>(r<BASE>)"
1792 *mipsIII:
1793 *mipsIV:
1794 *vr5000:
1795 // start-sanitize-vr4320
1796 *vr4320:
1797 // end-sanitize-vr4320
1798 // start-sanitize-vr5400
1799 *vr5400:
1800 // end-sanitize-vr5400
1801 // start-sanitize-r5900
1802 *r5900:
1803 // end-sanitize-r5900
1804 // start-sanitize-tx19
1805 *tx19:
1806 // end-sanitize-tx19
1807 {
1808   unsigned32 instruction = instruction_0;
1809   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1810   int destreg = ((instruction >> 16) & 0x0000001F);
1811   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1812   {
1813     address_word vaddr = ((unsigned64)op1 + offset);
1814     address_word paddr;
1815     int uncached;
1816     if ((vaddr & 7) != 0)
1817       SignalExceptionAddressLoad();
1818     else
1819       {
1820         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1821           {
1822             unsigned64 memval = 0;
1823             unsigned64 memval1 = 0;
1824             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1825             GPR[destreg] = memval;
1826             LLBIT = 1;
1827           }
1828       }
1829   }
1830 }
1831
1832
1833 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1834 "lui r<RT>, <IMMEDIATE>"
1835 *mipsI,mipsII,mipsIII,mipsIV:
1836 *vr5000:
1837 // start-sanitize-vr4320
1838 *vr4320:
1839 // end-sanitize-vr4320
1840 // start-sanitize-vr5400
1841 *vr5400:
1842 // end-sanitize-vr5400
1843 // start-sanitize-r5900
1844 *r5900:
1845 // end-sanitize-r5900
1846 *r3900:
1847 // start-sanitize-tx19
1848 *tx19:
1849 // end-sanitize-tx19
1850 {
1851   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1852 }
1853
1854
1855 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1856 "lw r<RT>, <OFFSET>(r<BASE>)"
1857 *mipsI,mipsII,mipsIII,mipsIV:
1858 *vr5000:
1859 // start-sanitize-vr4320
1860 *vr4320:
1861 // end-sanitize-vr4320
1862 // start-sanitize-vr5400
1863 *vr5400:
1864 // end-sanitize-vr5400
1865 // start-sanitize-r5900
1866 *r5900:
1867 // end-sanitize-r5900
1868 *r3900:
1869 // start-sanitize-tx19
1870 *tx19:
1871 // end-sanitize-tx19
1872 {
1873   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1874 }
1875
1876
1877 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1878 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1879 *mipsI,mipsII,mipsIII,mipsIV:
1880 *vr5000:
1881 // start-sanitize-vr4320
1882 *vr4320:
1883 // end-sanitize-vr4320
1884 // start-sanitize-vr5400
1885 *vr5400:
1886 // end-sanitize-vr5400
1887 // start-sanitize-r5900
1888 *r5900:
1889 // end-sanitize-r5900
1890 *r3900:
1891 // start-sanitize-tx19
1892 *tx19:
1893 // end-sanitize-tx19
1894 {
1895   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1896 }
1897
1898
1899 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1900 {
1901   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1902   address_word reverseendian = (ReverseEndian ? -1 : 0);
1903   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1904   unsigned int byte;
1905   address_word paddr;
1906   int uncached;
1907   unsigned64 memval;
1908   address_word vaddr;
1909
1910   vaddr = base + offset;
1911   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1912   paddr = (paddr ^ (reverseendian & mask));
1913   if (BigEndianMem == 0)
1914     paddr = paddr & ~access;
1915   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1916   LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
1917   /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
1918      (long) vaddr, byte, (long) paddr, (long) memval); */
1919   if ((byte & ~access) == 0)
1920     {
1921       int bits = 8 * (access - byte);
1922       unsigned_word screen = LSMASK (bits - 1, 0);
1923       rt &= screen;
1924       rt |= ((memval << bits) & ~screen);
1925     }
1926   else
1927     {
1928       unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
1929       rt &= screen;
1930       rt |= ((memval >> (8 * (mask - byte))) & ~screen);
1931     }
1932   return rt;
1933 }
1934
1935
1936 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1937 "lwl r<RT>, <OFFSET>(r<BASE>)"
1938 *mipsI,mipsII,mipsIII,mipsIV:
1939 *vr5000:
1940 // start-sanitize-vr4320
1941 *vr4320:
1942 // end-sanitize-vr4320
1943 // start-sanitize-vr5400
1944 *vr5400:
1945 // end-sanitize-vr5400
1946 // start-sanitize-r5900
1947 *r5900:
1948 // end-sanitize-r5900
1949 *r3900:
1950 // start-sanitize-tx19
1951 *tx19:
1952 // end-sanitize-tx19
1953 {
1954   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
1955 }
1956
1957
1958 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1959 {
1960   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1961   address_word reverseendian = (ReverseEndian ? -1 : 0);
1962   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1963   unsigned int byte;
1964   address_word paddr;
1965   int uncached;
1966   unsigned64 memval;
1967   address_word vaddr;
1968
1969   vaddr = base + offset;
1970   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1971   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1972   paddr = (paddr ^ (reverseendian & mask));
1973   if (BigEndianMem != 0)
1974     paddr = paddr & ~access;
1975   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1976   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1977   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1978   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1979      (long) paddr, byte, (long) paddr, (long) memval); */
1980   {
1981     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1982     rt &= ~screen;
1983     rt |= (memval >> (8 * byte)) & screen;
1984   }
1985   return rt;
1986 }
1987
1988
1989 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1990 "lwr r<RT>, <OFFSET>(r<BASE>)"
1991 *mipsI,mipsII,mipsIII,mipsIV:
1992 *vr5000:
1993 // start-sanitize-vr4320
1994 *vr4320:
1995 // end-sanitize-vr4320
1996 // start-sanitize-vr5400
1997 *vr5400:
1998 // end-sanitize-vr5400
1999 // start-sanitize-r5900
2000 *r5900:
2001 // end-sanitize-r5900
2002 *r3900:
2003 // start-sanitize-tx19
2004 *tx19:
2005 // end-sanitize-tx19
2006 {
2007   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2008 }
2009
2010
2011 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2012 "lwu r<RT>, <OFFSET>(r<BASE>)"
2013 *mipsIII:
2014 *mipsIV:
2015 *vr5000:
2016 // start-sanitize-vr4320
2017 *vr4320:
2018 // end-sanitize-vr4320
2019 // start-sanitize-vr5400
2020 *vr5400:
2021 // end-sanitize-vr5400
2022 // start-sanitize-r5900
2023 *r5900:
2024 // end-sanitize-r5900
2025 // start-sanitize-tx19
2026 *tx19:
2027 // end-sanitize-tx19
2028 {
2029   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2030 }
2031
2032
2033 :function:::void:do_mfhi:int rd
2034 {
2035   TRACE_ALU_INPUT1 (HI);
2036   GPR[rd] = HI;
2037   TRACE_ALU_RESULT (GPR[rd]);
2038 #if 0
2039   HIACCESS = 3;
2040 #endif
2041 }
2042
2043 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2044 "mfhi r<RD>"
2045 *mipsI,mipsII,mipsIII,mipsIV:
2046 *vr5000:
2047 // start-sanitize-vr4320
2048 *vr4320:
2049 // end-sanitize-vr4320
2050 // start-sanitize-vr5400
2051 *vr5400:
2052 // end-sanitize-vr5400
2053 // start-sanitize-r5900
2054 *r5900:
2055 // end-sanitize-r5900
2056 *r3900:
2057 // start-sanitize-tx19
2058 *tx19:
2059 // end-sanitize-tx19
2060 {
2061   do_mfhi (SD_, RD);
2062 }
2063
2064
2065
2066 :function:::void:do_mflo:int rd
2067 {
2068   TRACE_ALU_INPUT1 (LO);
2069   GPR[rd] = LO;
2070   TRACE_ALU_RESULT (GPR[rd]);
2071 #if 0
2072   LOACCESS = 3; /* 3rd instruction will be safe */
2073 #endif
2074 }
2075
2076 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2077 "mflo r<RD>"
2078 *mipsI,mipsII,mipsIII,mipsIV:
2079 *vr5000:
2080 // start-sanitize-vr4320
2081 *vr4320:
2082 // end-sanitize-vr4320
2083 // start-sanitize-vr5400
2084 *vr5400:
2085 // end-sanitize-vr5400
2086 // start-sanitize-r5900
2087 *r5900:
2088 // end-sanitize-r5900
2089 *r3900:
2090 // start-sanitize-tx19
2091 *tx19:
2092 // end-sanitize-tx19
2093 {
2094   do_mflo (SD_, RD);
2095 }
2096
2097
2098
2099 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2100 "movn r<RD>, r<RS>, r<RT>"
2101 *mipsIV:
2102 *vr5000:
2103 // start-sanitize-vr4320
2104 *vr4320:
2105 // end-sanitize-vr4320
2106 // start-sanitize-vr5400
2107 *vr5400:
2108 // end-sanitize-vr5400
2109 // start-sanitize-r5900
2110 *r5900:
2111 // end-sanitize-r5900
2112 {
2113   if (GPR[RT] != 0)
2114     GPR[RD] = GPR[RS];
2115 }
2116
2117
2118
2119 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2120 "movz r<RD>, r<RS>, r<RT>"
2121 *mipsIV:
2122 *vr5000:
2123 // start-sanitize-vr4320
2124 *vr4320:
2125 // end-sanitize-vr4320
2126 // start-sanitize-vr5400
2127 *vr5400:
2128 // end-sanitize-vr5400
2129 // start-sanitize-r5900
2130 *r5900:
2131 // end-sanitize-r5900
2132 {
2133   if (GPR[RT] == 0)
2134     GPR[RD] = GPR[RS];
2135 }
2136
2137
2138
2139 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2140 "mthi r<RS>"
2141 *mipsI,mipsII,mipsIII,mipsIV:
2142 *vr5000:
2143 // start-sanitize-vr4320
2144 *vr4320:
2145 // end-sanitize-vr4320
2146 // start-sanitize-vr5400
2147 *vr5400:
2148 // end-sanitize-vr5400
2149 // start-sanitize-r5900
2150 *r5900:
2151 // end-sanitize-r5900
2152 *r3900:
2153 // start-sanitize-tx19
2154 *tx19:
2155 // end-sanitize-tx19
2156 {
2157 #if 0
2158   if (HIACCESS != 0)
2159     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2160 #endif
2161   HI = GPR[RS];
2162 #if 0
2163   HIACCESS = 3; /* 3rd instruction will be safe */
2164 #endif
2165 }
2166
2167
2168
2169 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2170 "mtlo r<RS>"
2171 *mipsI,mipsII,mipsIII,mipsIV:
2172 *vr5000:
2173 // start-sanitize-vr4320
2174 *vr4320:
2175 // end-sanitize-vr4320
2176 // start-sanitize-vr5400
2177 *vr5400:
2178 // end-sanitize-vr5400
2179 // start-sanitize-r5900
2180 *r5900:
2181 // end-sanitize-r5900
2182 *r3900:
2183 // start-sanitize-tx19
2184 *tx19:
2185 // end-sanitize-tx19
2186 {
2187 #if 0
2188   if (LOACCESS != 0)
2189     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2190 #endif
2191   LO = GPR[RS];
2192 #if 0
2193   LOACCESS = 3; /* 3rd instruction will be safe */
2194 #endif
2195 }
2196
2197
2198
2199 :function:::void:do_mult:int rs, int rt, int rd
2200 {
2201   signed64 prod;
2202   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2203   CHECKHILO ("Multiplication");
2204   prod = (((signed64)(signed32) GPR[rs])
2205           * ((signed64)(signed32) GPR[rt]));
2206   LO = EXTEND32 (VL4_8 (prod));
2207   HI = EXTEND32 (VH4_8 (prod));
2208   if (rd != 0)
2209     GPR[rd] = LO;
2210   TRACE_ALU_RESULT2 (HI, LO);
2211 }
2212
2213 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2214 "mult r<RS>, r<RT>"
2215 *mipsI,mipsII,mipsIII,mipsIV:
2216 // start-sanitize-vr4320
2217 *vr4320:
2218 // end-sanitize-vr4320
2219 {
2220   do_mult (SD_, RS, RT, 0);
2221 }
2222
2223
2224 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2225 "mult r<RD>, r<RS>, r<RT>"
2226 *vr5000:
2227 // start-sanitize-vr5400
2228 *vr5400:
2229 // end-sanitize-vr5400
2230 // start-sanitize-r5900
2231 *r5900:
2232 // end-sanitize-r5900
2233 *r3900:
2234 // start-sanitize-tx19
2235 *tx19:
2236 // end-sanitize-tx19
2237 {
2238   do_mult (SD_, RS, RT, RD);
2239 }
2240
2241
2242 :function:::void:do_multu:int rs, int rt, int rd
2243 {
2244   unsigned64 prod;
2245   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2246   CHECKHILO ("Multiplication");
2247   prod = (((unsigned64)(unsigned32) GPR[rs])
2248           * ((unsigned64)(unsigned32) GPR[rt]));
2249   LO = EXTEND32 (VL4_8 (prod));
2250   HI = EXTEND32 (VH4_8 (prod));
2251   if (rd != 0)
2252     GPR[rd] = LO;
2253   TRACE_ALU_RESULT2 (HI, LO);
2254 }
2255
2256 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2257 "multu r<RS>, r<RT>"
2258 *mipsI,mipsII,mipsIII,mipsIV:
2259 // start-sanitize-vr4320
2260 *vr4320:
2261 // end-sanitize-vr4320
2262 {
2263   do_multu (SD_, RS, RT, 0);
2264 }
2265
2266 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2267 "multu r<RD>, r<RS>, r<RT>"
2268 *vr5000:
2269 // start-sanitize-vr5400
2270 *vr5400:
2271 // end-sanitize-vr5400
2272 // start-sanitize-r5900
2273 *r5900:
2274 // end-sanitize-r5900
2275 *r3900:
2276 // start-sanitize-tx19
2277 *tx19:
2278 // end-sanitize-tx19
2279 {
2280   do_multu (SD_, RS, RT, 0);
2281 }
2282
2283
2284 :function:::void:do_nor:int rs, int rt, int rd
2285 {
2286   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2287   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2288   TRACE_ALU_RESULT (GPR[rd]);
2289 }
2290
2291 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2292 "nor r<RD>, r<RS>, r<RT>"
2293 *mipsI,mipsII,mipsIII,mipsIV:
2294 *vr5000:
2295 // start-sanitize-vr4320
2296 *vr4320:
2297 // end-sanitize-vr4320
2298 // start-sanitize-vr5400
2299 *vr5400:
2300 // end-sanitize-vr5400
2301 // start-sanitize-r5900
2302 *r5900:
2303 // end-sanitize-r5900
2304 *r3900:
2305 // start-sanitize-tx19
2306 *tx19:
2307 // end-sanitize-tx19
2308 {
2309   do_nor (SD_, RS, RT, RD);
2310 }
2311
2312
2313 :function:::void:do_or:int rs, int rt, int rd
2314 {
2315   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2316   GPR[rd] = (GPR[rs] | GPR[rt]);
2317   TRACE_ALU_RESULT (GPR[rd]);
2318 }
2319
2320 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2321 "or r<RD>, r<RS>, r<RT>"
2322 *mipsI,mipsII,mipsIII,mipsIV:
2323 *vr5000:
2324 // start-sanitize-vr4320
2325 *vr4320:
2326 // end-sanitize-vr4320
2327 // start-sanitize-vr5400
2328 *vr5400:
2329 // end-sanitize-vr5400
2330 // start-sanitize-r5900
2331 *r5900:
2332 // end-sanitize-r5900
2333 *r3900:
2334 // start-sanitize-tx19
2335 *tx19:
2336 // end-sanitize-tx19
2337 {
2338   do_or (SD_, RS, RT, RD);
2339 }
2340
2341
2342
2343 :function:::void:do_ori:int rs, int rt, unsigned immediate
2344 {
2345   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2346   GPR[rt] = (GPR[rs] | immediate);
2347   TRACE_ALU_RESULT (GPR[rt]);
2348 }
2349
2350 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2351 "ori r<RT>, r<RS>, <IMMEDIATE>"
2352 *mipsI,mipsII,mipsIII,mipsIV:
2353 *vr5000:
2354 // start-sanitize-vr4320
2355 *vr4320:
2356 // end-sanitize-vr4320
2357 // start-sanitize-vr5400
2358 *vr5400:
2359 // end-sanitize-vr5400
2360 // start-sanitize-r5900
2361 *r5900:
2362 // end-sanitize-r5900
2363 *r3900:
2364 // start-sanitize-tx19
2365 *tx19:
2366 // end-sanitize-tx19
2367 {
2368   do_ori (SD_, RS, RT, IMMEDIATE);
2369 }
2370
2371
2372 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2373 *mipsIV:
2374 *vr5000:
2375 // start-sanitize-vr4320
2376 *vr4320:
2377 // end-sanitize-vr4320
2378 // start-sanitize-vr5400
2379 *vr5400:
2380 // end-sanitize-vr5400
2381 // start-sanitize-r5900
2382 *r5900:
2383 // end-sanitize-r5900
2384 {
2385   unsigned32 instruction = instruction_0;
2386   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2387   int hint = ((instruction >> 16) & 0x0000001F);
2388   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2389   {
2390     address_word vaddr = ((unsigned64)op1 + offset);
2391     address_word paddr;
2392     int uncached;
2393     {
2394       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2395         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2396     }
2397   }
2398 }
2399
2400 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2401 {
2402   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2403   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2404   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2405   unsigned int byte;
2406   address_word paddr;
2407   int uncached;
2408   unsigned64 memval;
2409   address_word vaddr;
2410
2411   vaddr = base + offset;
2412   if ((vaddr & access) != 0)
2413     SignalExceptionAddressStore ();
2414   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2415   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2416   byte = ((vaddr & mask) ^ bigendiancpu);
2417   memval = (word << (8 * byte));
2418   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2419 }
2420
2421
2422 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2423 "sb r<RT>, <OFFSET>(r<BASE>)"
2424 *mipsI,mipsII,mipsIII,mipsIV:
2425 *vr5000:
2426 // start-sanitize-vr4320
2427 *vr4320:
2428 // end-sanitize-vr4320
2429 // start-sanitize-vr5400
2430 *vr5400:
2431 // end-sanitize-vr5400
2432 // start-sanitize-r5900
2433 *r5900:
2434 // end-sanitize-r5900
2435 *r3900:
2436 // start-sanitize-tx19
2437 *tx19:
2438 // end-sanitize-tx19
2439 {
2440   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2441 }
2442
2443
2444 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2445 "sc r<RT>, <OFFSET>(r<BASE>)"
2446 *mipsII:
2447 *mipsIII:
2448 *mipsIV:
2449 *vr5000:
2450 // start-sanitize-vr4320
2451 *vr4320:
2452 // end-sanitize-vr4320
2453 // start-sanitize-vr5400
2454 *vr5400:
2455 // end-sanitize-vr5400
2456 // start-sanitize-r5900
2457 *r5900:
2458 // end-sanitize-r5900
2459 // start-sanitize-tx19
2460 *tx19:
2461 // end-sanitize-tx19
2462 {
2463   unsigned32 instruction = instruction_0;
2464   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2465   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2466   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2467   {
2468     address_word vaddr = ((unsigned64)op1 + offset);
2469     address_word paddr;
2470     int uncached;
2471     if ((vaddr & 3) != 0)
2472       SignalExceptionAddressStore();
2473     else
2474       {
2475         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2476           {
2477             unsigned64 memval = 0;
2478             unsigned64 memval1 = 0;
2479             unsigned64 mask = 0x7;
2480             unsigned int byte;
2481             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2482             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2483             memval = ((unsigned64) op2 << (8 * byte));
2484             if (LLBIT)
2485               {
2486                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2487               }
2488             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2489           }
2490       }
2491   }
2492 }
2493
2494
2495 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2496 "scd r<RT>, <OFFSET>(r<BASE>)"
2497 *mipsIII:
2498 *mipsIV:
2499 *vr5000:
2500 // start-sanitize-vr4320
2501 *vr4320:
2502 // end-sanitize-vr4320
2503 // start-sanitize-vr5400
2504 *vr5400:
2505 // end-sanitize-vr5400
2506 // start-sanitize-r5900
2507 *r5900:
2508 // end-sanitize-r5900
2509 // start-sanitize-tx19
2510 *tx19:
2511 // end-sanitize-tx19
2512 {
2513   unsigned32 instruction = instruction_0;
2514   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2515   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2516   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2517   {
2518     address_word vaddr = ((unsigned64)op1 + offset);
2519     address_word paddr;
2520     int uncached;
2521     if ((vaddr & 7) != 0)
2522       SignalExceptionAddressStore();
2523     else
2524       {
2525         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2526           {
2527             unsigned64 memval = 0;
2528             unsigned64 memval1 = 0;
2529             memval = op2;
2530             if (LLBIT)
2531               {
2532                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2533               }
2534             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2535           }
2536       }
2537   }
2538 }
2539
2540
2541 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2542 "sd r<RT>, <OFFSET>(r<BASE>)"
2543 *mipsIII:
2544 *mipsIV:
2545 *vr5000:
2546 // start-sanitize-vr4320
2547 *vr4320:
2548 // end-sanitize-vr4320
2549 // start-sanitize-vr5400
2550 *vr5400:
2551 // end-sanitize-vr5400
2552 // start-sanitize-r5900
2553 *r5900:
2554 // end-sanitize-r5900
2555 // start-sanitize-tx19
2556 *tx19:
2557 // end-sanitize-tx19
2558 {
2559   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2560 }
2561
2562
2563 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2564 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2565 *mipsII:
2566 *mipsIII:
2567 *mipsIV:
2568 *vr5000:
2569 // start-sanitize-vr4320
2570 *vr4320:
2571 // end-sanitize-vr4320
2572 // start-sanitize-vr5400
2573 *vr5400:
2574 // end-sanitize-vr5400
2575 // start-sanitize-r5900
2576 *r5900:
2577 // end-sanitize-r5900
2578 // start-sanitize-tx19
2579 *tx19:
2580 // end-sanitize-tx19
2581 {
2582   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2583 }
2584
2585
2586 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2587 "sdl r<RT>, <OFFSET>(r<BASE>)"
2588 *mipsIII:
2589 *mipsIV:
2590 *vr5000:
2591 // start-sanitize-vr4320
2592 *vr4320:
2593 // end-sanitize-vr4320
2594 // start-sanitize-vr5400
2595 *vr5400:
2596 // end-sanitize-vr5400
2597 // start-sanitize-r5900
2598 *r5900:
2599 // end-sanitize-r5900
2600 // start-sanitize-tx19
2601 *tx19:
2602 // end-sanitize-tx19
2603 {
2604   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2605 }
2606
2607
2608 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2609 "sdr r<RT>, <OFFSET>(r<BASE>)"
2610 *mipsIII:
2611 *mipsIV:
2612 *vr5000:
2613 // start-sanitize-vr4320
2614 *vr4320:
2615 // end-sanitize-vr4320
2616 // start-sanitize-vr5400
2617 *vr5400:
2618 // end-sanitize-vr5400
2619 // start-sanitize-r5900
2620 *r5900:
2621 // end-sanitize-r5900
2622 // start-sanitize-tx19
2623 *tx19:
2624 // end-sanitize-tx19
2625 {
2626   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2627 }
2628
2629
2630 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2631 "sh r<RT>, <OFFSET>(r<BASE>)"
2632 *mipsI,mipsII,mipsIII,mipsIV:
2633 *vr5000:
2634 // start-sanitize-vr4320
2635 *vr4320:
2636 // end-sanitize-vr4320
2637 // start-sanitize-vr5400
2638 *vr5400:
2639 // end-sanitize-vr5400
2640 // start-sanitize-r5900
2641 *r5900:
2642 // end-sanitize-r5900
2643 *r3900:
2644 // start-sanitize-tx19
2645 *tx19:
2646 // end-sanitize-tx19
2647 {
2648   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2649 }
2650
2651
2652 :function:::void:do_sll:int rt, int rd, int shift
2653 {
2654   unsigned32 temp = (GPR[rt] << shift);
2655   TRACE_ALU_INPUT2 (GPR[rt], shift);
2656   GPR[rd] = EXTEND32 (temp);
2657   TRACE_ALU_RESULT (GPR[rd]);
2658 }
2659
2660 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2661 "sll r<RD>, r<RT>, <SHIFT>"
2662 *mipsI,mipsII,mipsIII,mipsIV:
2663 *vr5000:
2664 // start-sanitize-vr4320
2665 *vr4320:
2666 // end-sanitize-vr4320
2667 // start-sanitize-vr5400
2668 *vr5400:
2669 // end-sanitize-vr5400
2670 // start-sanitize-r5900
2671 *r5900:
2672 // end-sanitize-r5900
2673 *r3900:
2674 // start-sanitize-tx19
2675 *tx19:
2676 // end-sanitize-tx19
2677 {
2678   do_sll (SD_, RT, RD, SHIFT);
2679 }
2680
2681
2682 :function:::void:do_sllv:int rs, int rt, int rd
2683 {
2684   int s = MASKED (GPR[rs], 4, 0);
2685   unsigned32 temp = (GPR[rt] << s);
2686   TRACE_ALU_INPUT2 (GPR[rt], s);
2687   GPR[rd] = EXTEND32 (temp);
2688   TRACE_ALU_RESULT (GPR[rd]);
2689 }
2690
2691 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2692 "sllv r<RD>, r<RT>, r<RS>"
2693 *mipsI,mipsII,mipsIII,mipsIV:
2694 *vr5000:
2695 // start-sanitize-vr4320
2696 *vr4320:
2697 // end-sanitize-vr4320
2698 // start-sanitize-vr5400
2699 *vr5400:
2700 // end-sanitize-vr5400
2701 // start-sanitize-r5900
2702 *r5900:
2703 // end-sanitize-r5900
2704 *r3900:
2705 // start-sanitize-tx19
2706 *tx19:
2707 // end-sanitize-tx19
2708 {
2709   do_sllv (SD_, RS, RT, RD);
2710 }
2711
2712
2713 :function:::void:do_slt:int rs, int rt, int rd
2714 {
2715   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2716   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2717   TRACE_ALU_RESULT (GPR[rd]);
2718 }
2719
2720 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2721 "slt r<RD>, r<RS>, r<RT>"
2722 *mipsI,mipsII,mipsIII,mipsIV:
2723 *vr5000:
2724 // start-sanitize-vr4320
2725 *vr4320:
2726 // end-sanitize-vr4320
2727 // start-sanitize-vr5400
2728 *vr5400:
2729 // end-sanitize-vr5400
2730 // start-sanitize-r5900
2731 *r5900:
2732 // end-sanitize-r5900
2733 *r3900:
2734 // start-sanitize-tx19
2735 *tx19:
2736 // end-sanitize-tx19
2737 {
2738   do_slt (SD_, RS, RT, RD);
2739 }
2740
2741
2742 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2743 {
2744   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2745   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2746   TRACE_ALU_RESULT (GPR[rt]);
2747 }
2748
2749 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2750 "slti r<RT>, r<RS>, <IMMEDIATE>"
2751 *mipsI,mipsII,mipsIII,mipsIV:
2752 *vr5000:
2753 // start-sanitize-vr4320
2754 *vr4320:
2755 // end-sanitize-vr4320
2756 // start-sanitize-vr5400
2757 *vr5400:
2758 // end-sanitize-vr5400
2759 // start-sanitize-r5900
2760 *r5900:
2761 // end-sanitize-r5900
2762 *r3900:
2763 // start-sanitize-tx19
2764 *tx19:
2765 // end-sanitize-tx19
2766 {
2767   do_slti (SD_, RS, RT, IMMEDIATE);
2768 }
2769
2770
2771 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2772 {
2773   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2774   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2775   TRACE_ALU_RESULT (GPR[rt]);
2776 }
2777
2778 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2779 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2780 *mipsI,mipsII,mipsIII,mipsIV:
2781 *vr5000:
2782 // start-sanitize-vr4320
2783 *vr4320:
2784 // end-sanitize-vr4320
2785 // start-sanitize-vr5400
2786 *vr5400:
2787 // end-sanitize-vr5400
2788 // start-sanitize-r5900
2789 *r5900:
2790 // end-sanitize-r5900
2791 *r3900:
2792 // start-sanitize-tx19
2793 *tx19:
2794 // end-sanitize-tx19
2795 {
2796   do_sltiu (SD_, RS, RT, IMMEDIATE);
2797 }
2798
2799
2800
2801 :function:::void:do_sltu:int rs, int rt, int rd
2802 {
2803   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2804   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2805   TRACE_ALU_RESULT (GPR[rd]);
2806 }
2807
2808 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2809 "sltu r<RD>, r<RS>, r<RT>"
2810 *mipsI,mipsII,mipsIII,mipsIV:
2811 *vr5000:
2812 // start-sanitize-vr4320
2813 *vr4320:
2814 // end-sanitize-vr4320
2815 // start-sanitize-vr5400
2816 *vr5400:
2817 // end-sanitize-vr5400
2818 // start-sanitize-r5900
2819 *r5900:
2820 // end-sanitize-r5900
2821 *r3900:
2822 // start-sanitize-tx19
2823 *tx19:
2824 // end-sanitize-tx19
2825 {
2826   do_sltu (SD_, RS, RT, RD);
2827 }
2828
2829
2830 :function:::void:do_sra:int rt, int rd, int shift
2831 {
2832   signed32 temp = (signed32) GPR[rt] >> shift;
2833   TRACE_ALU_INPUT2 (GPR[rt], shift);
2834   GPR[rd] = EXTEND32 (temp);
2835   TRACE_ALU_RESULT (GPR[rd]);
2836 }
2837
2838 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2839 "sra r<RD>, r<RT>, <SHIFT>"
2840 *mipsI,mipsII,mipsIII,mipsIV:
2841 *vr5000:
2842 // start-sanitize-vr4320
2843 *vr4320:
2844 // end-sanitize-vr4320
2845 // start-sanitize-vr5400
2846 *vr5400:
2847 // end-sanitize-vr5400
2848 // start-sanitize-r5900
2849 *r5900:
2850 // end-sanitize-r5900
2851 *r3900:
2852 // start-sanitize-tx19
2853 *tx19:
2854 // end-sanitize-tx19
2855 {
2856   do_sra (SD_, RT, RD, SHIFT);
2857 }
2858
2859
2860 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2861 "srav r<RD>, r<RT>, r<RS>"
2862 *mipsI,mipsII,mipsIII,mipsIV:
2863 *vr5000:
2864 // start-sanitize-vr4320
2865 *vr4320:
2866 // end-sanitize-vr4320
2867 // start-sanitize-vr5400
2868 *vr5400:
2869 // end-sanitize-vr5400
2870 // start-sanitize-r5900
2871 *r5900:
2872 // end-sanitize-r5900
2873 *r3900:
2874 // start-sanitize-tx19
2875 *tx19:
2876 // end-sanitize-tx19
2877 {
2878   int s = MASKED (GPR[RS], 4, 0);
2879   signed32 temp = (signed32) GPR[RT] >> s;
2880   GPR[RD] = EXTEND32 (temp);
2881 }
2882
2883
2884 :function:::void:do_srl:int rt, int rd, int shift
2885 {
2886   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2887   TRACE_ALU_INPUT2 (GPR[rt], shift);
2888   GPR[rd] = EXTEND32 (temp);
2889   TRACE_ALU_RESULT (GPR[rd]);
2890 }
2891
2892 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2893 "srl r<RD>, r<RT>, <SHIFT>"
2894 *mipsI,mipsII,mipsIII,mipsIV:
2895 *vr5000:
2896 // start-sanitize-vr4320
2897 *vr4320:
2898 // end-sanitize-vr4320
2899 // start-sanitize-vr5400
2900 *vr5400:
2901 // end-sanitize-vr5400
2902 // start-sanitize-r5900
2903 *r5900:
2904 // end-sanitize-r5900
2905 *r3900:
2906 // start-sanitize-tx19
2907 *tx19:
2908 // end-sanitize-tx19
2909 {
2910   do_srl (SD_, RT, RD, SHIFT);
2911 }
2912
2913
2914 :function:::void:do_srlv:int rs, int rt, int rd
2915 {
2916   int s = MASKED (GPR[rs], 4, 0);
2917   unsigned32 temp = (unsigned32) GPR[rt] >> s;
2918   TRACE_ALU_INPUT2 (GPR[rt], s);
2919   GPR[rd] = EXTEND32 (temp);
2920   TRACE_ALU_RESULT (GPR[rd]);
2921 }
2922
2923 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2924 "srlv r<RD>, r<RT>, r<RS>"
2925 *mipsI,mipsII,mipsIII,mipsIV:
2926 *vr5000:
2927 // start-sanitize-vr4320
2928 *vr4320:
2929 // end-sanitize-vr4320
2930 // start-sanitize-vr5400
2931 *vr5400:
2932 // end-sanitize-vr5400
2933 // start-sanitize-r5900
2934 *r5900:
2935 // end-sanitize-r5900
2936 *r3900:
2937 // start-sanitize-tx19
2938 *tx19:
2939 // end-sanitize-tx19
2940 {
2941   do_srlv (SD_, RS, RT, RD);
2942 }
2943
2944
2945 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2946 "sub r<RD>, r<RS>, r<RT>"
2947 *mipsI,mipsII,mipsIII,mipsIV:
2948 *vr5000:
2949 // start-sanitize-vr4320
2950 *vr4320:
2951 // end-sanitize-vr4320
2952 // start-sanitize-vr5400
2953 *vr5400:
2954 // end-sanitize-vr5400
2955 // start-sanitize-r5900
2956 *r5900:
2957 // end-sanitize-r5900
2958 *r3900:
2959 // start-sanitize-tx19
2960 *tx19:
2961 // end-sanitize-tx19
2962 {
2963   ALU32_BEGIN (GPR[RS]);
2964   ALU32_SUB (GPR[RT]);
2965   ALU32_END (GPR[RD]);
2966 }
2967
2968
2969 :function:::void:do_subu:int rs, int rt, int rd
2970 {
2971   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2972   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2973   TRACE_ALU_RESULT (GPR[rd]);
2974 }
2975
2976 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2977 "subu r<RD>, r<RS>, r<RT>"
2978 *mipsI,mipsII,mipsIII,mipsIV:
2979 *vr5000:
2980 // start-sanitize-vr4320
2981 *vr4320:
2982 // end-sanitize-vr4320
2983 // start-sanitize-vr5400
2984 *vr5400:
2985 // end-sanitize-vr5400
2986 // start-sanitize-r5900
2987 *r5900:
2988 // end-sanitize-r5900
2989 *r3900:
2990 // start-sanitize-tx19
2991 *tx19:
2992 // end-sanitize-tx19
2993 {
2994   do_subu (SD_, RS, RT, RD);
2995 }
2996
2997
2998 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2999 "sw r<RT>, <OFFSET>(r<BASE>)"
3000 *mipsI,mipsII,mipsIII,mipsIV:
3001 // start-sanitize-tx19
3002 *tx19:
3003 // end-sanitize-tx19
3004 *r3900:
3005 // start-sanitize-vr4320
3006 *vr4320:
3007 // end-sanitize-vr4320
3008 *vr5000:
3009 // start-sanitize-vr5400
3010 *vr5400:
3011 // end-sanitize-vr5400
3012 // start-sanitize-r5900
3013 *r5900:
3014 // end-sanitize-r5900
3015 {
3016   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3017 }
3018
3019
3020 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3021 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3022 *mipsI,mipsII,mipsIII,mipsIV:
3023 *vr5000:
3024 // start-sanitize-vr4320
3025 *vr4320:
3026 // end-sanitize-vr4320
3027 // start-sanitize-vr5400
3028 *vr5400:
3029 // end-sanitize-vr5400
3030 *r3900:
3031 // start-sanitize-tx19
3032 *tx19:
3033 // end-sanitize-tx19
3034 {
3035   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3036 }
3037
3038
3039
3040 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3041 {
3042   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3043   address_word reverseendian = (ReverseEndian ? -1 : 0);
3044   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3045   unsigned int byte;
3046   address_word paddr;
3047   int uncached;
3048   unsigned64 memval;
3049   address_word vaddr;
3050
3051   vaddr = base + offset;
3052   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3053   paddr = (paddr ^ (reverseendian & mask));
3054   if (BigEndianMem == 0)
3055     paddr = paddr & ~access;
3056   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3057   if ((byte & ~access) == 0)
3058     memval = (rt >> (8 * (access - byte)));
3059   else
3060     memval = (rt << (8 * (mask - byte)));
3061   StoreMemory (uncached, byte & access, memval, NULL, paddr, vaddr, isREAL);
3062 }
3063
3064
3065 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3066 "swl r<RT>, <OFFSET>(r<BASE>)"
3067 *mipsI,mipsII,mipsIII,mipsIV:
3068 *vr5000:
3069 // start-sanitize-vr4320
3070 *vr4320:
3071 // end-sanitize-vr4320
3072 // start-sanitize-vr5400
3073 *vr5400:
3074 // end-sanitize-vr5400
3075 // start-sanitize-r5900
3076 *r5900:
3077 // end-sanitize-r5900
3078 *r3900:
3079 // start-sanitize-tx19
3080 *tx19:
3081 // end-sanitize-tx19
3082 {
3083   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3084 }
3085
3086
3087 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3088 {
3089   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3090   address_word reverseendian = (ReverseEndian ? -1 : 0);
3091   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3092   unsigned int byte;
3093   address_word paddr;
3094   int uncached;
3095   unsigned64 memval;
3096   address_word vaddr;
3097
3098   vaddr = base + offset;
3099   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3100   paddr = (paddr ^ (reverseendian & mask));
3101   if (BigEndianMem != 0)
3102     paddr &= ~access;
3103   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3104   memval = (rt << (byte * 8));
3105   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3106 }
3107
3108 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3109 "swr r<RT>, <OFFSET>(r<BASE>)"
3110 *mipsI,mipsII,mipsIII,mipsIV:
3111 *vr5000:
3112 // start-sanitize-vr4320
3113 *vr4320:
3114 // end-sanitize-vr4320
3115 // start-sanitize-vr5400
3116 *vr5400:
3117 // end-sanitize-vr5400
3118 // start-sanitize-r5900
3119 *r5900:
3120 // end-sanitize-r5900
3121 *r3900:
3122 // start-sanitize-tx19
3123 *tx19:
3124 // end-sanitize-tx19
3125 {
3126   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3127 }
3128
3129
3130 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3131 "sync":STYPE == 0
3132 "sync <STYPE>"
3133 *mipsII:
3134 *mipsIII:
3135 *mipsIV:
3136 *vr5000:
3137 // start-sanitize-vr4320
3138 *vr4320:
3139 // end-sanitize-vr4320
3140 // start-sanitize-vr5400
3141 *vr5400:
3142 // end-sanitize-vr5400
3143 // start-sanitize-r5900
3144 *r5900:
3145 // end-sanitize-r5900
3146 *r3900:
3147 // start-sanitize-tx19
3148 *tx19:
3149 // end-sanitize-tx19
3150 {
3151   SyncOperation (STYPE);
3152 }
3153
3154
3155 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3156 "syscall <CODE>"
3157 *mipsI,mipsII,mipsIII,mipsIV:
3158 *vr5000:
3159 // start-sanitize-vr4320
3160 *vr4320:
3161 // end-sanitize-vr4320
3162 // start-sanitize-vr5400
3163 *vr5400:
3164 // end-sanitize-vr5400
3165 // start-sanitize-r5900
3166 *r5900:
3167 // end-sanitize-r5900
3168 *r3900:
3169 // start-sanitize-tx19
3170 *tx19:
3171 // end-sanitize-tx19
3172 {
3173   SignalException(SystemCall, instruction_0);
3174 }
3175
3176
3177 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3178 "teq r<RS>, r<RT>"
3179 *mipsII:
3180 *mipsIII:
3181 *mipsIV:
3182 *vr5000:
3183 // start-sanitize-vr4320
3184 *vr4320:
3185 // end-sanitize-vr4320
3186 // start-sanitize-vr5400
3187 *vr5400:
3188 // end-sanitize-vr5400
3189 // start-sanitize-r5900
3190 *r5900:
3191 // end-sanitize-r5900
3192 // start-sanitize-tx19
3193 *tx19:
3194 // end-sanitize-tx19
3195 {
3196   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3197     SignalException(Trap, instruction_0);
3198 }
3199
3200
3201 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3202 "teqi r<RS>, <IMMEDIATE>"
3203 *mipsII:
3204 *mipsIII:
3205 *mipsIV:
3206 *vr5000:
3207 // start-sanitize-vr4320
3208 *vr4320:
3209 // end-sanitize-vr4320
3210 // start-sanitize-vr5400
3211 *vr5400:
3212 // end-sanitize-vr5400
3213 // start-sanitize-r5900
3214 *r5900:
3215 // end-sanitize-r5900
3216 // start-sanitize-tx19
3217 *tx19:
3218 // end-sanitize-tx19
3219 {
3220   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3221     SignalException(Trap, instruction_0);
3222 }
3223
3224
3225 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3226 "tge r<RS>, r<RT>"
3227 *mipsII:
3228 *mipsIII:
3229 *mipsIV:
3230 *vr5000:
3231 // start-sanitize-vr4320
3232 *vr4320:
3233 // end-sanitize-vr4320
3234 // start-sanitize-vr5400
3235 *vr5400:
3236 // end-sanitize-vr5400
3237 // start-sanitize-r5900
3238 *r5900:
3239 // end-sanitize-r5900
3240 // start-sanitize-tx19
3241 *tx19:
3242 // end-sanitize-tx19
3243 {
3244   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3245     SignalException(Trap, instruction_0);
3246 }
3247
3248
3249 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3250 "tgei r<RS>, <IMMEDIATE>"
3251 *mipsII:
3252 *mipsIII:
3253 *mipsIV:
3254 *vr5000:
3255 // start-sanitize-vr4320
3256 *vr4320:
3257 // end-sanitize-vr4320
3258 // start-sanitize-vr5400
3259 *vr5400:
3260 // end-sanitize-vr5400
3261 // start-sanitize-r5900
3262 *r5900:
3263 // end-sanitize-r5900
3264 // start-sanitize-tx19
3265 *tx19:
3266 // end-sanitize-tx19
3267 {
3268   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3269     SignalException(Trap, instruction_0);
3270 }
3271
3272
3273 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3274 "tgeiu r<RS>, <IMMEDIATE>"
3275 *mipsII:
3276 *mipsIII:
3277 *mipsIV:
3278 *vr5000:
3279 // start-sanitize-vr4320
3280 *vr4320:
3281 // end-sanitize-vr4320
3282 // start-sanitize-vr5400
3283 *vr5400:
3284 // end-sanitize-vr5400
3285 // start-sanitize-r5900
3286 *r5900:
3287 // end-sanitize-r5900
3288 // start-sanitize-tx19
3289 *tx19:
3290 // end-sanitize-tx19
3291 {
3292   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3293     SignalException(Trap, instruction_0);
3294 }
3295
3296
3297 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3298 "tgeu r<RS>, r<RT>"
3299 *mipsII:
3300 *mipsIII:
3301 *mipsIV:
3302 *vr5000:
3303 // start-sanitize-vr4320
3304 *vr4320:
3305 // end-sanitize-vr4320
3306 // start-sanitize-vr5400
3307 *vr5400:
3308 // end-sanitize-vr5400
3309 // start-sanitize-r5900
3310 *r5900:
3311 // end-sanitize-r5900
3312 // start-sanitize-tx19
3313 *tx19:
3314 // end-sanitize-tx19
3315 {
3316   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3317     SignalException(Trap, instruction_0);
3318 }
3319
3320
3321 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3322 "tlt r<RS>, r<RT>"
3323 *mipsII:
3324 *mipsIII:
3325 *mipsIV:
3326 *vr5000:
3327 // start-sanitize-vr4320
3328 *vr4320:
3329 // end-sanitize-vr4320
3330 // start-sanitize-vr5400
3331 *vr5400:
3332 // end-sanitize-vr5400
3333 // start-sanitize-r5900
3334 *r5900:
3335 // end-sanitize-r5900
3336 // start-sanitize-tx19
3337 *tx19:
3338 // end-sanitize-tx19
3339 {
3340   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3341     SignalException(Trap, instruction_0);
3342 }
3343
3344
3345 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3346 "tlti r<RS>, <IMMEDIATE>"
3347 *mipsII:
3348 *mipsIII:
3349 *mipsIV:
3350 *vr5000:
3351 // start-sanitize-vr4320
3352 *vr4320:
3353 // end-sanitize-vr4320
3354 // start-sanitize-vr5400
3355 *vr5400:
3356 // end-sanitize-vr5400
3357 // start-sanitize-r5900
3358 *r5900:
3359 // end-sanitize-r5900
3360 // start-sanitize-tx19
3361 *tx19:
3362 // end-sanitize-tx19
3363 {
3364   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3365     SignalException(Trap, instruction_0);
3366 }
3367
3368
3369 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3370 "tltiu r<RS>, <IMMEDIATE>"
3371 *mipsII:
3372 *mipsIII:
3373 *mipsIV:
3374 *vr5000:
3375 // start-sanitize-vr4320
3376 *vr4320:
3377 // end-sanitize-vr4320
3378 // start-sanitize-vr5400
3379 *vr5400:
3380 // end-sanitize-vr5400
3381 // start-sanitize-r5900
3382 *r5900:
3383 // end-sanitize-r5900
3384 // start-sanitize-tx19
3385 *tx19:
3386 // end-sanitize-tx19
3387 {
3388   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3389     SignalException(Trap, instruction_0);
3390 }
3391
3392
3393 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3394 "tltu r<RS>, r<RT>"
3395 *mipsII:
3396 *mipsIII:
3397 *mipsIV:
3398 *vr5000:
3399 // start-sanitize-vr4320
3400 *vr4320:
3401 // end-sanitize-vr4320
3402 // start-sanitize-vr5400
3403 *vr5400:
3404 // end-sanitize-vr5400
3405 // start-sanitize-r5900
3406 *r5900:
3407 // end-sanitize-r5900
3408 // start-sanitize-tx19
3409 *tx19:
3410 // end-sanitize-tx19
3411 {
3412   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3413     SignalException(Trap, instruction_0);
3414 }
3415
3416
3417 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3418 "tne r<RS>, r<RT>"
3419 *mipsII:
3420 *mipsIII:
3421 *mipsIV:
3422 *vr5000:
3423 // start-sanitize-vr4320
3424 *vr4320:
3425 // end-sanitize-vr4320
3426 // start-sanitize-vr5400
3427 *vr5400:
3428 // end-sanitize-vr5400
3429 // start-sanitize-r5900
3430 *r5900:
3431 // end-sanitize-r5900
3432 // start-sanitize-tx19
3433 *tx19:
3434 // end-sanitize-tx19
3435 {
3436   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3437     SignalException(Trap, instruction_0);
3438 }
3439
3440
3441 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3442 "tne r<RS>, <IMMEDIATE>"
3443 *mipsII:
3444 *mipsIII:
3445 *mipsIV:
3446 *vr5000:
3447 // start-sanitize-vr4320
3448 *vr4320:
3449 // end-sanitize-vr4320
3450 // start-sanitize-vr5400
3451 *vr5400:
3452 // end-sanitize-vr5400
3453 // start-sanitize-r5900
3454 *r5900:
3455 // end-sanitize-r5900
3456 // start-sanitize-tx19
3457 *tx19:
3458 // end-sanitize-tx19
3459 {
3460   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3461     SignalException(Trap, instruction_0);
3462 }
3463
3464
3465 :function:::void:do_xor:int rs, int rt, int rd
3466 {
3467   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3468   GPR[rd] = GPR[rs] ^ GPR[rt];
3469   TRACE_ALU_RESULT (GPR[rd]);
3470 }
3471
3472 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3473 "xor r<RD>, r<RS>, r<RT>"
3474 *mipsI,mipsII,mipsIII,mipsIV:
3475 *vr5000:
3476 // start-sanitize-vr4320
3477 *vr4320:
3478 // end-sanitize-vr4320
3479 // start-sanitize-vr5400
3480 *vr5400:
3481 // end-sanitize-vr5400
3482 // start-sanitize-r5900
3483 *r5900:
3484 // end-sanitize-r5900
3485 *r3900:
3486 // start-sanitize-tx19
3487 *tx19:
3488 // end-sanitize-tx19
3489 {
3490   do_xor (SD_, RS, RT, RD);
3491 }
3492
3493
3494 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3495 {
3496   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3497   GPR[rt] = GPR[rs] ^ immediate;
3498   TRACE_ALU_RESULT (GPR[rt]);
3499 }
3500
3501 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3502 "xori r<RT>, r<RS>, <IMMEDIATE>"
3503 *mipsI,mipsII,mipsIII,mipsIV:
3504 *vr5000:
3505 // start-sanitize-vr4320
3506 *vr4320:
3507 // end-sanitize-vr4320
3508 // start-sanitize-vr5400
3509 *vr5400:
3510 // end-sanitize-vr5400
3511 // start-sanitize-r5900
3512 *r5900:
3513 // end-sanitize-r5900
3514 *r3900:
3515 // start-sanitize-tx19
3516 *tx19:
3517 // end-sanitize-tx19
3518 {
3519   do_xori (SD_, RS, RT, IMMEDIATE);
3520 }
3521
3522 \f
3523 //
3524 // MIPS Architecture:
3525 //
3526 //        FPU Instruction Set (COP1 & COP1X)
3527 //
3528
3529
3530 :%s::::FMT:int fmt
3531 {
3532   switch (fmt)
3533     {
3534     case fmt_single: return "s";
3535     case fmt_double: return "d";
3536     case fmt_word: return "w";
3537     case fmt_long: return "l";
3538     default: return "?";
3539     }
3540 }
3541
3542 :%s::::X:int x
3543 {
3544   switch (x)
3545     {
3546     case 0: return "f";
3547     case 1: return "t";
3548     default: return "?";
3549     }
3550 }
3551
3552 :%s::::TF:int tf
3553 {
3554   if (tf)
3555     return "t";
3556   else
3557     return "f";
3558 }
3559
3560 :%s::::ND:int nd
3561 {
3562   if (nd)
3563     return "l";
3564   else
3565     return "";
3566 }
3567
3568 :%s::::COND:int cond
3569 {
3570   switch (cond)
3571     {
3572     case 00: return "f";
3573     case 01: return "un";
3574     case 02: return "eq";
3575     case 03: return "ueq";
3576     case 04: return "olt";
3577     case 05: return "ult";
3578     case 06: return "ole";
3579     case 07: return "ule";
3580     case 010: return "sf";
3581     case 011: return "ngle";
3582     case 012: return "seq";
3583     case 013: return "ngl";
3584     case 014: return "lt";
3585     case 015: return "nge";
3586     case 016: return "le";
3587     case 017: return "ngt";
3588     default: return "?";
3589     }
3590 }
3591
3592
3593 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3594 "abs.%s<FMT> f<FD>, f<FS>"
3595 *mipsI,mipsII,mipsIII,mipsIV:
3596 *vr5000:
3597 // start-sanitize-vr4320
3598 *vr4320:
3599 // end-sanitize-vr4320
3600 // start-sanitize-vr5400
3601 *vr5400:
3602 // end-sanitize-vr5400
3603 *r3900:
3604 // start-sanitize-tx19
3605 *tx19:
3606 // end-sanitize-tx19
3607 {
3608   unsigned32 instruction = instruction_0;
3609   int destreg = ((instruction >> 6) & 0x0000001F);
3610   int fs = ((instruction >> 11) & 0x0000001F);
3611   int format = ((instruction >> 21) & 0x00000007);
3612   {
3613     if ((format != fmt_single) && (format != fmt_double))
3614       SignalException(ReservedInstruction,instruction);
3615     else
3616       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3617   }
3618 }
3619
3620
3621
3622 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3623 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3624 *mipsI,mipsII,mipsIII,mipsIV:
3625 *vr5000:
3626 // start-sanitize-vr4320
3627 *vr4320:
3628 // end-sanitize-vr4320
3629 // start-sanitize-vr5400
3630 *vr5400:
3631 // end-sanitize-vr5400
3632 *r3900:
3633 // start-sanitize-tx19
3634 *tx19:
3635 // end-sanitize-tx19
3636 {
3637   unsigned32 instruction = instruction_0;
3638   int destreg = ((instruction >> 6) & 0x0000001F);
3639   int fs = ((instruction >> 11) & 0x0000001F);
3640   int ft = ((instruction >> 16) & 0x0000001F);
3641   int format = ((instruction >> 21) & 0x00000007);
3642   {
3643     if ((format != fmt_single) && (format != fmt_double))
3644       SignalException(ReservedInstruction, instruction);
3645     else
3646       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3647   }
3648 }
3649
3650
3651
3652 // BC1F
3653 // BC1FL
3654 // BC1T
3655 // BC1TL
3656
3657 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3658 "bc1%s<TF>%s<ND> <OFFSET>"
3659 *mipsI,mipsII,mipsIII:
3660 // start-sanitize-r5900
3661 *r5900:
3662 // end-sanitize-r5900
3663 {
3664   TRACE_BRANCH_INPUT (PREVCOC1());
3665   if (PREVCOC1() == TF)
3666     {
3667       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3668       TRACE_BRANCH_RESULT (dest);
3669       DELAY_SLOT (dest);
3670     }
3671   else if (ND)
3672     {
3673       TRACE_BRANCH_RESULT (0);
3674       NULLIFY_NEXT_INSTRUCTION ();
3675     }
3676   else
3677     {
3678       TRACE_BRANCH_RESULT (NIA);
3679     }
3680 }
3681
3682 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3683 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3684 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3685 *mipsIV:
3686 *vr5000:
3687 // start-sanitize-vr4320
3688 *vr4320:
3689 // end-sanitize-vr4320
3690 // start-sanitize-vr5400
3691 *vr5400:
3692 // end-sanitize-vr5400
3693 *r3900:
3694 // start-sanitize-tx19
3695 *tx19:
3696 // end-sanitize-tx19
3697 {
3698   if (GETFCC(CC) == TF)
3699     {
3700       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3701     }
3702   else if (ND)
3703     {
3704       NULLIFY_NEXT_INSTRUCTION ();
3705     }
3706 }
3707
3708
3709
3710 // C.EQ.S
3711 // C.EQ.D
3712 // ...
3713
3714 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3715 {
3716   if ((fmt != fmt_single) && (fmt != fmt_double))
3717     SignalException (ReservedInstruction, insn);
3718   else
3719     {
3720       int less;
3721       int equal;
3722       int unordered;
3723       int condition;
3724       unsigned64 ofs = ValueFPR (fs, fmt);
3725       unsigned64 oft = ValueFPR (ft, fmt);
3726       if (NaN (ofs, fmt) || NaN (oft, fmt))
3727         {
3728           if (FCSR & FP_ENABLE (IO))
3729             {
3730               FCSR |= FP_CAUSE (IO);
3731               SignalExceptionFPE ();
3732             }
3733           less = 0;
3734           equal = 0;
3735           unordered = 1;
3736         }
3737       else
3738         {
3739           less = Less (ofs, oft, fmt);
3740           equal = Equal (ofs, oft, fmt);
3741           unordered = 0;
3742         }
3743       condition = (((cond & (1 << 2)) && less)
3744                    || ((cond & (1 << 1)) && equal)
3745                    || ((cond & (1 << 0)) && unordered));
3746       SETFCC (cc, condition);
3747     }
3748 }
3749
3750 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3751 *mipsI,mipsII,mipsIII:
3752 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3753 {
3754   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3755 }
3756
3757 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3758 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3759 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3760 *mipsIV:
3761 *vr5000:
3762 // start-sanitize-vr4320
3763 *vr4320:
3764 // end-sanitize-vr4320
3765 // start-sanitize-vr5400
3766 *vr5400:
3767 // end-sanitize-vr5400
3768 *r3900:
3769 // start-sanitize-tx19
3770 *tx19:
3771 // end-sanitize-tx19
3772 {
3773   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3774 }
3775
3776
3777 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3778 "ceil.l.%s<FMT> f<FD>, f<FS>"
3779 *mipsIII:
3780 *mipsIV:
3781 *vr5000:
3782 // start-sanitize-vr4320
3783 *vr4320:
3784 // end-sanitize-vr4320
3785 // start-sanitize-vr5400
3786 *vr5400:
3787 // end-sanitize-vr5400
3788 // start-sanitize-r5900
3789 *r5900:
3790 // end-sanitize-r5900
3791 *r3900:
3792 // start-sanitize-tx19
3793 *tx19:
3794 // end-sanitize-tx19
3795 {
3796   unsigned32 instruction = instruction_0;
3797   int destreg = ((instruction >> 6) & 0x0000001F);
3798   int fs = ((instruction >> 11) & 0x0000001F);
3799   int format = ((instruction >> 21) & 0x00000007);
3800   {
3801     if ((format != fmt_single) && (format != fmt_double))
3802       SignalException(ReservedInstruction,instruction);
3803     else
3804       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3805   }
3806 }
3807
3808
3809 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3810 *mipsII:
3811 *mipsIII:
3812 *mipsIV:
3813 *vr5000:
3814 // start-sanitize-vr4320
3815 *vr4320:
3816 // end-sanitize-vr4320
3817 // start-sanitize-vr5400
3818 *vr5400:
3819 // end-sanitize-vr5400
3820 // start-sanitize-r5900
3821 *r5900:
3822 // end-sanitize-r5900
3823 *r3900:
3824 // start-sanitize-tx19
3825 *tx19:
3826 // end-sanitize-tx19
3827 {
3828   unsigned32 instruction = instruction_0;
3829   int destreg = ((instruction >> 6) & 0x0000001F);
3830   int fs = ((instruction >> 11) & 0x0000001F);
3831   int format = ((instruction >> 21) & 0x00000007);
3832   {
3833   if ((format != fmt_single) && (format != fmt_double))
3834    SignalException(ReservedInstruction,instruction);
3835   else
3836    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3837   }
3838 }
3839
3840
3841 // CFC1
3842 // CTC1
3843 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3844 "c%s<X>c1 r<RT>, f<FS>"
3845 *mipsI:
3846 *mipsII:
3847 *mipsIII:
3848 {
3849   if (X)
3850     {
3851       if (FS == 0)
3852         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3853       else if (FS == 31)
3854         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
3855       /* else NOP */
3856       PENDING_FILL(COCIDX,0); /* special case */
3857     }
3858   else
3859     { /* control from */
3860       if (FS == 0)
3861         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3862       else if (FS == 31)
3863         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3864       /* else NOP */
3865     }
3866 }
3867 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3868 "c%s<X>c1 r<RT>, f<FS>"
3869 *mipsIV:
3870 *vr5000:
3871 // start-sanitize-vr4320
3872 *vr4320:
3873 // end-sanitize-vr4320
3874 // start-sanitize-vr5400
3875 *vr5400:
3876 // end-sanitize-vr5400
3877 // start-sanitize-r5900
3878 *r5900:
3879 // end-sanitize-r5900
3880 *r3900:
3881 // start-sanitize-tx19
3882 *tx19:
3883 // end-sanitize-tx19
3884 {
3885   if (X)
3886     {
3887       /* control to */
3888       TRACE_ALU_INPUT1 (GPR[RT]);
3889       if (FS == 0)
3890         {
3891           FCR0 = VL4_8(GPR[RT]);
3892           TRACE_ALU_RESULT (FCR0);
3893         }
3894       else if (FS == 31)
3895         {
3896           FCR31 = VL4_8(GPR[RT]);
3897           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3898           TRACE_ALU_RESULT (FCR31);
3899         }
3900       else
3901         {
3902           TRACE_ALU_RESULT0 ();
3903         }
3904       /* else NOP */
3905     }
3906   else
3907     { /* control from */
3908       if (FS == 0)
3909         {
3910           TRACE_ALU_INPUT1 (FCR0);
3911           GPR[RT] = SIGNEXTEND (FCR0, 32);
3912         }
3913       else if (FS == 31)
3914         {
3915           TRACE_ALU_INPUT1 (FCR31);
3916           GPR[RT] = SIGNEXTEND (FCR31, 32);
3917         }
3918       TRACE_ALU_RESULT (GPR[RT]);
3919       /* else NOP */
3920     }
3921 }
3922
3923
3924 //
3925 // FIXME: Does not correctly differentiate between mips*
3926 //
3927 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3928 "cvt.d.%s<FMT> f<FD>, f<FS>"
3929 *mipsI,mipsII,mipsIII,mipsIV:
3930 *vr5000:
3931 // start-sanitize-vr4320
3932 *vr4320:
3933 // end-sanitize-vr4320
3934 // start-sanitize-vr5400
3935 *vr5400:
3936 // end-sanitize-vr5400
3937 *r3900:
3938 // start-sanitize-tx19
3939 *tx19:
3940 // end-sanitize-tx19
3941 {
3942   unsigned32 instruction = instruction_0;
3943   int destreg = ((instruction >> 6) & 0x0000001F);
3944   int fs = ((instruction >> 11) & 0x0000001F);
3945   int format = ((instruction >> 21) & 0x00000007);
3946   {
3947     if ((format == fmt_double) | 0)
3948       SignalException(ReservedInstruction,instruction);
3949     else
3950       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3951   }
3952 }
3953
3954
3955 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3956 "cvt.l.%s<FMT> f<FD>, f<FS>"
3957 *mipsIII:
3958 *mipsIV:
3959 *vr5000:
3960 // start-sanitize-vr4320
3961 *vr4320:
3962 // end-sanitize-vr4320
3963 // start-sanitize-vr5400
3964 *vr5400:
3965 // end-sanitize-vr5400
3966 *r3900:
3967 // start-sanitize-tx19
3968 *tx19:
3969 // end-sanitize-tx19
3970 {
3971   unsigned32 instruction = instruction_0;
3972   int destreg = ((instruction >> 6) & 0x0000001F);
3973   int fs = ((instruction >> 11) & 0x0000001F);
3974   int format = ((instruction >> 21) & 0x00000007);
3975   {
3976     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3977       SignalException(ReservedInstruction,instruction);
3978     else
3979       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3980   }
3981 }
3982
3983
3984 //
3985 // FIXME: Does not correctly differentiate between mips*
3986 //
3987 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3988 "cvt.s.%s<FMT> f<FD>, f<FS>"
3989 *mipsI,mipsII,mipsIII,mipsIV:
3990 *vr5000:
3991 // start-sanitize-vr4320
3992 *vr4320:
3993 // end-sanitize-vr4320
3994 // start-sanitize-vr5400
3995 *vr5400:
3996 // end-sanitize-vr5400
3997 *r3900:
3998 // start-sanitize-tx19
3999 *tx19:
4000 // end-sanitize-tx19
4001 {
4002   unsigned32 instruction = instruction_0;
4003   int destreg = ((instruction >> 6) & 0x0000001F);
4004   int fs = ((instruction >> 11) & 0x0000001F);
4005   int format = ((instruction >> 21) & 0x00000007);
4006   {
4007     if ((format == fmt_single) | 0)
4008       SignalException(ReservedInstruction,instruction);
4009     else
4010       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4011   }
4012 }
4013
4014
4015 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4016 "cvt.w.%s<FMT> f<FD>, f<FS>"
4017 *mipsI,mipsII,mipsIII,mipsIV:
4018 *vr5000:
4019 // start-sanitize-vr4320
4020 *vr4320:
4021 // end-sanitize-vr4320
4022 // start-sanitize-vr5400
4023 *vr5400:
4024 // end-sanitize-vr5400
4025 *r3900:
4026 // start-sanitize-tx19
4027 *tx19:
4028 // end-sanitize-tx19
4029 {
4030   unsigned32 instruction = instruction_0;
4031   int destreg = ((instruction >> 6) & 0x0000001F);
4032   int fs = ((instruction >> 11) & 0x0000001F);
4033   int format = ((instruction >> 21) & 0x00000007);
4034   {
4035     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4036       SignalException(ReservedInstruction,instruction);
4037     else
4038       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4039   }
4040 }
4041
4042
4043 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4044 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4045 *mipsI,mipsII,mipsIII,mipsIV:
4046 *vr5000:
4047 // start-sanitize-vr4320
4048 *vr4320:
4049 // end-sanitize-vr4320
4050 // start-sanitize-vr5400
4051 *vr5400:
4052 // end-sanitize-vr5400
4053 *r3900:
4054 // start-sanitize-tx19
4055 *tx19:
4056 // end-sanitize-tx19
4057 {
4058   unsigned32 instruction = instruction_0;
4059   int destreg = ((instruction >> 6) & 0x0000001F);
4060   int fs = ((instruction >> 11) & 0x0000001F);
4061   int ft = ((instruction >> 16) & 0x0000001F);
4062   int format = ((instruction >> 21) & 0x00000007);
4063   {
4064     if ((format != fmt_single) && (format != fmt_double))
4065       SignalException(ReservedInstruction,instruction);
4066     else
4067       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4068   }
4069 }
4070
4071
4072 // DMFC1
4073 // DMTC1
4074 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4075 "dm%s<X>c1 r<RT>, f<FS>"
4076 *mipsIII:
4077 {
4078   if (X)
4079     {
4080       if (SizeFGR() == 64)
4081         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4082       else if ((FS & 0x1) == 0)
4083         {
4084           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4085           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4086         }
4087     }
4088   else
4089     {
4090       if (SizeFGR() == 64)
4091         PENDING_FILL(RT,FGR[FS]);
4092       else if ((FS & 0x1) == 0)
4093         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4094       else
4095         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4096     }
4097 }
4098 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4099 "dm%s<X>c1 r<RT>, f<FS>"
4100 *mipsIV:
4101 *vr5000:
4102 // start-sanitize-vr4320
4103 *vr4320:
4104 // end-sanitize-vr4320
4105 // start-sanitize-vr5400
4106 *vr5400:
4107 // end-sanitize-vr5400
4108 // start-sanitize-r5900
4109 *r5900:
4110 // end-sanitize-r5900
4111 *r3900:
4112 // start-sanitize-tx19
4113 *tx19:
4114 // end-sanitize-tx19
4115 {
4116   if (X)
4117     {
4118       if (SizeFGR() == 64)
4119         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4120       else if ((FS & 0x1) == 0)
4121         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4122     }
4123   else
4124     {
4125       if (SizeFGR() == 64)
4126         GPR[RT] = FGR[FS];
4127       else if ((FS & 0x1) == 0)
4128         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4129       else
4130         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4131     }
4132 }
4133
4134
4135 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4136 "floor.l.%s<FMT> f<FD>, f<FS>"
4137 *mipsIII:
4138 *mipsIV:
4139 *vr5000:
4140 // start-sanitize-vr4320
4141 *vr4320:
4142 // end-sanitize-vr4320
4143 // start-sanitize-vr5400
4144 *vr5400:
4145 // end-sanitize-vr5400
4146 // start-sanitize-r5900
4147 *r5900:
4148 // end-sanitize-r5900
4149 *r3900:
4150 // start-sanitize-tx19
4151 *tx19:
4152 // end-sanitize-tx19
4153 {
4154   unsigned32 instruction = instruction_0;
4155   int destreg = ((instruction >> 6) & 0x0000001F);
4156   int fs = ((instruction >> 11) & 0x0000001F);
4157   int format = ((instruction >> 21) & 0x00000007);
4158   {
4159     if ((format != fmt_single) && (format != fmt_double))
4160       SignalException(ReservedInstruction,instruction);
4161     else
4162       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4163   }
4164 }
4165
4166
4167 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4168 "floor.w.%s<FMT> f<FD>, f<FS>"
4169 *mipsII:
4170 *mipsIII:
4171 *mipsIV:
4172 *vr5000:
4173 // start-sanitize-vr4320
4174 *vr4320:
4175 // end-sanitize-vr4320
4176 // start-sanitize-vr5400
4177 *vr5400:
4178 // end-sanitize-vr5400
4179 // start-sanitize-r5900
4180 *r5900:
4181 // end-sanitize-r5900
4182 *r3900:
4183 // start-sanitize-tx19
4184 *tx19:
4185 // end-sanitize-tx19
4186 {
4187   unsigned32 instruction = instruction_0;
4188   int destreg = ((instruction >> 6) & 0x0000001F);
4189   int fs = ((instruction >> 11) & 0x0000001F);
4190   int format = ((instruction >> 21) & 0x00000007);
4191   {
4192     if ((format != fmt_single) && (format != fmt_double))
4193       SignalException(ReservedInstruction,instruction);
4194     else
4195       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4196   }
4197 }
4198
4199
4200 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4201 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4202 *mipsII:
4203 *mipsIII:
4204 *mipsIV:
4205 *vr5000:
4206 // start-sanitize-vr4320
4207 *vr4320:
4208 // end-sanitize-vr4320
4209 // start-sanitize-vr5400
4210 *vr5400:
4211 // end-sanitize-vr5400
4212 *r3900:
4213 // start-sanitize-tx19
4214 *tx19:
4215 // end-sanitize-tx19
4216 {
4217   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4218 }
4219
4220
4221 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4222 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4223 *mipsIV:
4224 *vr5000:
4225 // start-sanitize-vr4320
4226 *vr4320:
4227 // end-sanitize-vr4320
4228 // start-sanitize-vr5400
4229 *vr5400:
4230 // end-sanitize-vr5400
4231 {
4232   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4233 }
4234
4235
4236
4237 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4238 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4239 *mipsI,mipsII,mipsIII,mipsIV:
4240 *vr5000:
4241 // start-sanitize-vr4320
4242 *vr4320:
4243 // end-sanitize-vr4320
4244 // start-sanitize-vr5400
4245 *vr5400:
4246 // end-sanitize-vr5400
4247 // start-sanitize-r5900
4248 *r5900:
4249 // end-sanitize-r5900
4250 *r3900:
4251 // start-sanitize-tx19
4252 *tx19:
4253 // end-sanitize-tx19
4254 {
4255   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4256 }
4257
4258
4259 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4260 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4261 *mipsIV:
4262 *vr5000:
4263 // start-sanitize-vr4320
4264 *vr4320:
4265 // end-sanitize-vr4320
4266 // start-sanitize-vr5400
4267 *vr5400:
4268 // end-sanitize-vr5400
4269 {
4270   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4271 }
4272
4273
4274
4275 //
4276 // FIXME: Not correct for mips*
4277 //
4278 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4279 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4280 *mipsIV:
4281 *vr5000:
4282 // start-sanitize-vr4320
4283 *vr4320:
4284 // end-sanitize-vr4320
4285 // start-sanitize-vr5400
4286 *vr5400:
4287 // end-sanitize-vr5400
4288 {
4289   unsigned32 instruction = instruction_0;
4290   int destreg = ((instruction >> 6) & 0x0000001F);
4291   int fs = ((instruction >> 11) & 0x0000001F);
4292   int ft = ((instruction >> 16) & 0x0000001F);
4293   int fr = ((instruction >> 21) & 0x0000001F);
4294   {
4295     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4296   }
4297 }
4298
4299
4300 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4301 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4302 *mipsIV:
4303 *vr5000:
4304 // start-sanitize-vr4320
4305 *vr4320:
4306 // end-sanitize-vr4320
4307 // start-sanitize-vr5400
4308 *vr5400:
4309 // end-sanitize-vr5400
4310 {
4311   unsigned32 instruction = instruction_0;
4312   int destreg = ((instruction >> 6) & 0x0000001F);
4313   int fs = ((instruction >> 11) & 0x0000001F);
4314   int ft = ((instruction >> 16) & 0x0000001F);
4315   int fr = ((instruction >> 21) & 0x0000001F);
4316   {
4317     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4318   }
4319 }
4320
4321
4322 // MFC1
4323 // MTC1
4324 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4325 "m%s<X>c1 r<RT>, f<FS>"
4326 *mipsI:
4327 *mipsII:
4328 *mipsIII:
4329 {
4330   if (X)
4331     { /*MTC1*/
4332       if (SizeFGR() == 64)
4333         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4334       else
4335         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4336     }
4337   else /*MFC1*/
4338     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4339 }
4340 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4341 "m%s<X>c1 r<RT>, f<FS>"
4342 *mipsIV:
4343 *vr5000:
4344 // start-sanitize-vr4320
4345 *vr4320:
4346 // end-sanitize-vr4320
4347 // start-sanitize-vr5400
4348 *vr5400:
4349 // end-sanitize-vr5400
4350 *r3900:
4351 // start-sanitize-tx19
4352 *tx19:
4353 // end-sanitize-tx19
4354 {
4355   if (X)
4356     /*MTC1*/
4357     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4358   else /*MFC1*/
4359     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4360 }
4361
4362
4363 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4364 "mov.%s<FMT> f<FD>, f<FS>"
4365 *mipsI,mipsII,mipsIII,mipsIV:
4366 *vr5000:
4367 // start-sanitize-vr4320
4368 *vr4320:
4369 // end-sanitize-vr4320
4370 // start-sanitize-vr5400
4371 *vr5400:
4372 // end-sanitize-vr5400
4373 *r3900:
4374 // start-sanitize-tx19
4375 *tx19:
4376 // end-sanitize-tx19
4377 {
4378   unsigned32 instruction = instruction_0;
4379   int destreg = ((instruction >> 6) & 0x0000001F);
4380   int fs = ((instruction >> 11) & 0x0000001F);
4381   int format = ((instruction >> 21) & 0x00000007);
4382   {
4383     StoreFPR(destreg,format,ValueFPR(fs,format));
4384   }
4385 }
4386
4387
4388 // MOVF
4389 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4390 "mov%s<TF> r<RD>, r<RS>, <CC>"
4391 *mipsIV:
4392 *vr5000:
4393 // start-sanitize-vr4320
4394 *vr4320:
4395 // end-sanitize-vr4320
4396 // start-sanitize-vr5400
4397 *vr5400:
4398 // end-sanitize-vr5400
4399 // start-sanitize-r5900
4400 *r5900:
4401 // end-sanitize-r5900
4402 {
4403   if (GETFCC(CC) == TF)
4404     GPR[RD] = GPR[RS];
4405 }
4406
4407
4408 // MOVF.fmt
4409 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4410 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4411 *mipsIV:
4412 *vr5000:
4413 // start-sanitize-vr4320
4414 *vr4320:
4415 // end-sanitize-vr4320
4416 // start-sanitize-vr5400
4417 *vr5400:
4418 // end-sanitize-vr5400
4419 // start-sanitize-r5900
4420 *r5900:
4421 // end-sanitize-r5900
4422 {
4423   unsigned32 instruction = instruction_0;
4424   int format = ((instruction >> 21) & 0x00000007);
4425   {
4426    if (GETFCC(CC) == TF)
4427      StoreFPR (FD, format, ValueFPR (FS, format));
4428    else
4429      StoreFPR (FD, format, ValueFPR (FD, format));
4430   }
4431 }
4432
4433
4434 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4435 *mipsIV:
4436 *vr5000:
4437 // start-sanitize-vr4320
4438 *vr4320:
4439 // end-sanitize-vr4320
4440 // start-sanitize-vr5400
4441 *vr5400:
4442 // end-sanitize-vr5400
4443 // start-sanitize-r5900
4444 *r5900:
4445 // end-sanitize-r5900
4446 {
4447   unsigned32 instruction = instruction_0;
4448   int destreg = ((instruction >> 6) & 0x0000001F);
4449   int fs = ((instruction >> 11) & 0x0000001F);
4450   int format = ((instruction >> 21) & 0x00000007);
4451   {
4452     StoreFPR(destreg,format,ValueFPR(fs,format));
4453   }
4454 }
4455
4456
4457 // MOVT see MOVtf
4458
4459
4460 // MOVT.fmt see MOVtf.fmt
4461
4462
4463
4464 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4465 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4466 *mipsIV:
4467 *vr5000:
4468 // start-sanitize-vr4320
4469 *vr4320:
4470 // end-sanitize-vr4320
4471 // start-sanitize-vr5400
4472 *vr5400:
4473 // end-sanitize-vr5400
4474 // start-sanitize-r5900
4475 *r5900:
4476 // end-sanitize-r5900
4477 {
4478   unsigned32 instruction = instruction_0;
4479   int destreg = ((instruction >> 6) & 0x0000001F);
4480   int fs = ((instruction >> 11) & 0x0000001F);
4481   int format = ((instruction >> 21) & 0x00000007);
4482   {
4483    StoreFPR(destreg,format,ValueFPR(fs,format));
4484   }
4485 }
4486
4487
4488 // MSUB.fmt
4489 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4490 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4491 *mipsIV:
4492 *vr5000:
4493 // start-sanitize-vr4320
4494 *vr4320:
4495 // end-sanitize-vr4320
4496 // start-sanitize-vr5400
4497 *vr5400:
4498 // end-sanitize-vr5400
4499 // start-sanitize-r5900
4500 *r5900:
4501 // end-sanitize-r5900
4502 {
4503   unsigned32 instruction = instruction_0;
4504   int destreg = ((instruction >> 6) & 0x0000001F);
4505   int fs = ((instruction >> 11) & 0x0000001F);
4506   int ft = ((instruction >> 16) & 0x0000001F);
4507   int fr = ((instruction >> 21) & 0x0000001F);
4508   {
4509     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4510   }
4511 }
4512
4513
4514 // MSUB.fmt
4515 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4516 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4517 *mipsIV:
4518 *vr5000:
4519 // start-sanitize-vr4320
4520 *vr4320:
4521 // end-sanitize-vr4320
4522 // start-sanitize-vr5400
4523 *vr5400:
4524 // end-sanitize-vr5400
4525 // start-sanitize-r5900
4526 *r5900:
4527 // end-sanitize-r5900
4528 {
4529   unsigned32 instruction = instruction_0;
4530   int destreg = ((instruction >> 6) & 0x0000001F);
4531   int fs = ((instruction >> 11) & 0x0000001F);
4532   int ft = ((instruction >> 16) & 0x0000001F);
4533   int fr = ((instruction >> 21) & 0x0000001F);
4534   {
4535    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4536   }
4537 }
4538
4539
4540 // MTC1 see MxC1
4541
4542
4543 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4544 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4545 *mipsI,mipsII,mipsIII,mipsIV:
4546 *vr5000:
4547 // start-sanitize-vr4320
4548 *vr4320:
4549 // end-sanitize-vr4320
4550 // start-sanitize-vr5400
4551 *vr5400:
4552 // end-sanitize-vr5400
4553 *r3900:
4554 // start-sanitize-tx19
4555 *tx19:
4556 // end-sanitize-tx19
4557 {
4558   unsigned32 instruction = instruction_0;
4559   int destreg = ((instruction >> 6) & 0x0000001F);
4560   int fs = ((instruction >> 11) & 0x0000001F);
4561   int ft = ((instruction >> 16) & 0x0000001F);
4562   int format = ((instruction >> 21) & 0x00000007);
4563   {
4564     if ((format != fmt_single) && (format != fmt_double))
4565       SignalException(ReservedInstruction,instruction);
4566     else
4567       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4568   }
4569 }
4570
4571
4572 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4573 "neg.%s<FMT> f<FD>, f<FS>"
4574 *mipsI,mipsII,mipsIII,mipsIV:
4575 *vr5000:
4576 // start-sanitize-vr4320
4577 *vr4320:
4578 // end-sanitize-vr4320
4579 // start-sanitize-vr5400
4580 *vr5400:
4581 // end-sanitize-vr5400
4582 *r3900:
4583 // start-sanitize-tx19
4584 *tx19:
4585 // end-sanitize-tx19
4586 {
4587   unsigned32 instruction = instruction_0;
4588   int destreg = ((instruction >> 6) & 0x0000001F);
4589   int fs = ((instruction >> 11) & 0x0000001F);
4590   int format = ((instruction >> 21) & 0x00000007);
4591   {
4592     if ((format != fmt_single) && (format != fmt_double))
4593       SignalException(ReservedInstruction,instruction);
4594     else
4595       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4596   }
4597 }
4598
4599
4600 // NMADD.fmt
4601 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4602 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4603 *mipsIV:
4604 *vr5000:
4605 // start-sanitize-vr4320
4606 *vr4320:
4607 // end-sanitize-vr4320
4608 // start-sanitize-vr5400
4609 *vr5400:
4610 // end-sanitize-vr5400
4611 {
4612   unsigned32 instruction = instruction_0;
4613   int destreg = ((instruction >> 6) & 0x0000001F);
4614   int fs = ((instruction >> 11) & 0x0000001F);
4615   int ft = ((instruction >> 16) & 0x0000001F);
4616   int fr = ((instruction >> 21) & 0x0000001F);
4617   {
4618    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4619   }
4620 }
4621
4622
4623 // NMADD.fmt
4624 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4625 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4626 *mipsIV:
4627 *vr5000:
4628 // start-sanitize-vr4320
4629 *vr4320:
4630 // end-sanitize-vr4320
4631 // start-sanitize-vr5400
4632 *vr5400:
4633 // end-sanitize-vr5400
4634 {
4635   unsigned32 instruction = instruction_0;
4636   int destreg = ((instruction >> 6) & 0x0000001F);
4637   int fs = ((instruction >> 11) & 0x0000001F);
4638   int ft = ((instruction >> 16) & 0x0000001F);
4639   int fr = ((instruction >> 21) & 0x0000001F);
4640   {
4641    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4642   }
4643 }
4644
4645
4646 // NMSUB.fmt
4647 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4648 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4649 *mipsIV:
4650 *vr5000:
4651 // start-sanitize-vr4320
4652 *vr4320:
4653 // end-sanitize-vr4320
4654 // start-sanitize-vr5400
4655 *vr5400:
4656 // end-sanitize-vr5400
4657 {
4658   unsigned32 instruction = instruction_0;
4659   int destreg = ((instruction >> 6) & 0x0000001F);
4660   int fs = ((instruction >> 11) & 0x0000001F);
4661   int ft = ((instruction >> 16) & 0x0000001F);
4662   int fr = ((instruction >> 21) & 0x0000001F);
4663   {
4664    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4665   }
4666 }
4667
4668
4669 // NMSUB.fmt
4670 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4671 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4672 *mipsIV:
4673 *vr5000:
4674 // start-sanitize-vr4320
4675 *vr4320:
4676 // end-sanitize-vr4320
4677 // start-sanitize-vr5400
4678 *vr5400:
4679 // end-sanitize-vr5400
4680 {
4681   unsigned32 instruction = instruction_0;
4682   int destreg = ((instruction >> 6) & 0x0000001F);
4683   int fs = ((instruction >> 11) & 0x0000001F);
4684   int ft = ((instruction >> 16) & 0x0000001F);
4685   int fr = ((instruction >> 21) & 0x0000001F);
4686   {
4687     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4688   }
4689 }
4690
4691
4692 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4693 "prefx <HINT>, r<INDEX>(r<BASE>)"
4694 *mipsIV:
4695 *vr5000:
4696 // start-sanitize-vr4320
4697 *vr4320:
4698 // end-sanitize-vr4320
4699 // start-sanitize-vr5400
4700 *vr5400:
4701 // end-sanitize-vr5400
4702 {
4703   unsigned32 instruction = instruction_0;
4704   int fs = ((instruction >> 11) & 0x0000001F);
4705   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4706   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4707   {
4708     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4709     address_word paddr;
4710     int uncached;
4711     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4712       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4713   }
4714 }
4715
4716 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4717 *mipsIV:
4718 "recip.%s<FMT> f<FD>, f<FS>"
4719 *vr5000:
4720 // start-sanitize-vr4320
4721 *vr4320:
4722 // end-sanitize-vr4320
4723 // start-sanitize-vr5400
4724 *vr5400:
4725 // end-sanitize-vr5400
4726 {
4727   unsigned32 instruction = instruction_0;
4728   int destreg = ((instruction >> 6) & 0x0000001F);
4729   int fs = ((instruction >> 11) & 0x0000001F);
4730   int format = ((instruction >> 21) & 0x00000007);
4731   {
4732   if ((format != fmt_single) && (format != fmt_double))
4733    SignalException(ReservedInstruction,instruction);
4734   else
4735    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4736   }
4737 }
4738
4739
4740 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4741 "round.l.%s<FMT> f<FD>, f<FS>"
4742 *mipsIII:
4743 *mipsIV:
4744 *vr5000:
4745 // start-sanitize-vr4320
4746 *vr4320:
4747 // end-sanitize-vr4320
4748 // start-sanitize-vr5400
4749 *vr5400:
4750 // end-sanitize-vr5400
4751 // start-sanitize-r5900
4752 *r5900:
4753 // end-sanitize-r5900
4754 *r3900:
4755 // start-sanitize-tx19
4756 *tx19:
4757 // end-sanitize-tx19
4758 {
4759   unsigned32 instruction = instruction_0;
4760   int destreg = ((instruction >> 6) & 0x0000001F);
4761   int fs = ((instruction >> 11) & 0x0000001F);
4762   int format = ((instruction >> 21) & 0x00000007);
4763   {
4764     if ((format != fmt_single) && (format != fmt_double))
4765       SignalException(ReservedInstruction,instruction);
4766     else
4767       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4768   }
4769 }
4770
4771
4772 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4773 "round.w.%s<FMT> f<FD>, f<FS>"
4774 *mipsII:
4775 *mipsIII:
4776 *mipsIV:
4777 *vr5000:
4778 // start-sanitize-vr4320
4779 *vr4320:
4780 // end-sanitize-vr4320
4781 // start-sanitize-vr5400
4782 *vr5400:
4783 // end-sanitize-vr5400
4784 // start-sanitize-r5900
4785 *r5900:
4786 // end-sanitize-r5900
4787 *r3900:
4788 // start-sanitize-tx19
4789 *tx19:
4790 // end-sanitize-tx19
4791 {
4792   unsigned32 instruction = instruction_0;
4793   int destreg = ((instruction >> 6) & 0x0000001F);
4794   int fs = ((instruction >> 11) & 0x0000001F);
4795   int format = ((instruction >> 21) & 0x00000007);
4796   {
4797   if ((format != fmt_single) && (format != fmt_double))
4798    SignalException(ReservedInstruction,instruction);
4799   else
4800    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4801   }
4802 }
4803
4804
4805 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4806 *mipsIV:
4807 "rsqrt.%s<FMT> f<FD>, f<FS>"
4808 *vr5000:
4809 // start-sanitize-vr4320
4810 *vr4320:
4811 // end-sanitize-vr4320
4812 // start-sanitize-vr5400
4813 *vr5400:
4814 // end-sanitize-vr5400
4815 {
4816   unsigned32 instruction = instruction_0;
4817   int destreg = ((instruction >> 6) & 0x0000001F);
4818   int fs = ((instruction >> 11) & 0x0000001F);
4819   int format = ((instruction >> 21) & 0x00000007);
4820   {
4821   if ((format != fmt_single) && (format != fmt_double))
4822    SignalException(ReservedInstruction,instruction);
4823   else
4824    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4825   }
4826 }
4827
4828
4829 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4830 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4831 *mipsII:
4832 *mipsIII:
4833 *mipsIV:
4834 *vr5000:
4835 // start-sanitize-vr4320
4836 *vr4320:
4837 // end-sanitize-vr4320
4838 // start-sanitize-vr5400
4839 *vr5400:
4840 // end-sanitize-vr5400
4841 *r3900:
4842 // start-sanitize-tx19
4843 *tx19:
4844 // end-sanitize-tx19
4845 {
4846   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4847 }
4848
4849
4850 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
4851 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
4852 *mipsIV:
4853 *vr5000:
4854 // start-sanitize-vr4320
4855 *vr4320:
4856 // end-sanitize-vr4320
4857 // start-sanitize-vr5400
4858 *vr5400:
4859 // end-sanitize-vr5400
4860 {
4861   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4862 }
4863
4864
4865 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4866 "sqrt.%s<FMT> f<FD>, f<FS>"
4867 *mipsII:
4868 *mipsIII:
4869 *mipsIV:
4870 *vr5000:
4871 // start-sanitize-vr4320
4872 *vr4320:
4873 // end-sanitize-vr4320
4874 // start-sanitize-vr5400
4875 *vr5400:
4876 // end-sanitize-vr5400
4877 *r3900:
4878 // start-sanitize-tx19
4879 *tx19:
4880 // end-sanitize-tx19
4881 {
4882   unsigned32 instruction = instruction_0;
4883   int destreg = ((instruction >> 6) & 0x0000001F);
4884   int fs = ((instruction >> 11) & 0x0000001F);
4885   int format = ((instruction >> 21) & 0x00000007);
4886   {
4887     if ((format != fmt_single) && (format != fmt_double))
4888       SignalException(ReservedInstruction,instruction);
4889     else
4890       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4891   }
4892 }
4893
4894
4895 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4896 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4897 *mipsI,mipsII,mipsIII,mipsIV:
4898 *vr5000:
4899 // start-sanitize-vr4320
4900 *vr4320:
4901 // end-sanitize-vr4320
4902 // start-sanitize-vr5400
4903 *vr5400:
4904 // end-sanitize-vr5400
4905 *r3900:
4906 // start-sanitize-tx19
4907 *tx19:
4908 // end-sanitize-tx19
4909 {
4910   unsigned32 instruction = instruction_0;
4911   int destreg = ((instruction >> 6) & 0x0000001F);
4912   int fs = ((instruction >> 11) & 0x0000001F);
4913   int ft = ((instruction >> 16) & 0x0000001F);
4914   int format = ((instruction >> 21) & 0x00000007);
4915   {
4916     if ((format != fmt_single) && (format != fmt_double))
4917       SignalException(ReservedInstruction,instruction);
4918     else
4919       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4920   }
4921 }
4922
4923
4924
4925 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
4926 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4927 *mipsI,mipsII,mipsIII,mipsIV:
4928 *vr5000:
4929 // start-sanitize-vr4320
4930 *vr4320:
4931 // end-sanitize-vr4320
4932 // start-sanitize-vr5400
4933 *vr5400:
4934 // end-sanitize-vr5400
4935 // start-sanitize-r5900
4936 *r5900:
4937 // end-sanitize-r5900
4938 *r3900:
4939 // start-sanitize-tx19
4940 *tx19:
4941 // end-sanitize-tx19
4942 {
4943   unsigned32 instruction = instruction_0;
4944   signed_word offset = EXTEND16 (OFFSET);
4945   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4946   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4947   {
4948     address_word vaddr = ((uword64)op1 + offset);
4949     address_word paddr;
4950     int uncached;
4951     if ((vaddr & 3) != 0)
4952       SignalExceptionAddressStore();
4953     else
4954       {
4955         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4956           {
4957             uword64 memval = 0;
4958             uword64 memval1 = 0;
4959             uword64 mask = 0x7;
4960             unsigned int byte;
4961             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4962             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4963             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
4964             {
4965               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4966             }
4967           }
4968       }
4969   }
4970 }
4971
4972
4973 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4974 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4975 *mipsIV:
4976 *vr5000:
4977 // start-sanitize-vr4320
4978 *vr4320:
4979 // end-sanitize-vr4320
4980 // start-sanitize-vr5400
4981 *vr5400:
4982 // end-sanitize-vr5400
4983 {
4984   unsigned32 instruction = instruction_0;
4985   int fs = ((instruction >> 11) & 0x0000001F);
4986   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4987   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4988   {
4989    address_word vaddr = ((unsigned64)op1 + op2);
4990    address_word paddr;
4991    int uncached;
4992    if ((vaddr & 3) != 0)
4993     SignalExceptionAddressStore();
4994    else
4995    {
4996     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4997     {
4998      unsigned64 memval = 0;
4999      unsigned64 memval1 = 0;
5000      unsigned64 mask = 0x7;
5001      unsigned int byte;
5002      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5003      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5004      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5005       {
5006        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5007       }
5008     }
5009    }
5010   }
5011 }
5012
5013
5014 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5015 "trunc.l.%s<FMT> f<FD>, f<FS>"
5016 *mipsIII:
5017 *mipsIV:
5018 *vr5000:
5019 // start-sanitize-vr4320
5020 *vr4320:
5021 // end-sanitize-vr4320
5022 // start-sanitize-vr5400
5023 *vr5400:
5024 // end-sanitize-vr5400
5025 // start-sanitize-r5900
5026 *r5900:
5027 // end-sanitize-r5900
5028 *r3900:
5029 // start-sanitize-tx19
5030 *tx19:
5031 // end-sanitize-tx19
5032 {
5033   unsigned32 instruction = instruction_0;
5034   int destreg = ((instruction >> 6) & 0x0000001F);
5035   int fs = ((instruction >> 11) & 0x0000001F);
5036   int format = ((instruction >> 21) & 0x00000007);
5037   {
5038   if ((format != fmt_single) && (format != fmt_double))
5039    SignalException(ReservedInstruction,instruction);
5040   else
5041    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5042   }
5043 }
5044
5045
5046 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5047 "trunc.w.%s<FMT> f<FD>, f<FS>"
5048 *mipsII:
5049 *mipsIII:
5050 *mipsIV:
5051 *vr5000:
5052 // start-sanitize-vr4320
5053 *vr4320:
5054 // end-sanitize-vr4320
5055 // start-sanitize-vr5400
5056 *vr5400:
5057 // end-sanitize-vr5400
5058 // start-sanitize-r5900
5059 *r5900:
5060 // end-sanitize-r5900
5061 *r3900:
5062 // start-sanitize-tx19
5063 *tx19:
5064 // end-sanitize-tx19
5065 {
5066   unsigned32 instruction = instruction_0;
5067   int destreg = ((instruction >> 6) & 0x0000001F);
5068   int fs = ((instruction >> 11) & 0x0000001F);
5069   int format = ((instruction >> 21) & 0x00000007);
5070   {
5071   if ((format != fmt_single) && (format != fmt_double))
5072    SignalException(ReservedInstruction,instruction);
5073   else
5074    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5075   }
5076 }
5077
5078 \f
5079 //
5080 // MIPS Architecture:
5081 //
5082 //        System Control Instruction Set (COP0)
5083 //
5084
5085
5086 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5087 "bc0f <OFFSET>"
5088 *mipsI,mipsII,mipsIII,mipsIV:
5089 *vr5000:
5090 // start-sanitize-vr4320
5091 *vr4320:
5092 // end-sanitize-vr4320
5093 // start-sanitize-vr5400
5094 *vr5400:
5095 // end-sanitize-vr5400
5096 // start-sanitize-r5900
5097 *r5900:
5098 // end-sanitize-r5900
5099
5100
5101 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5102 "bc0fl <OFFSET>"
5103 *mipsI,mipsII,mipsIII,mipsIV:
5104 *vr5000:
5105 // start-sanitize-vr4320
5106 *vr4320:
5107 // end-sanitize-vr4320
5108 // start-sanitize-vr5400
5109 *vr5400:
5110 // end-sanitize-vr5400
5111 // start-sanitize-r5900
5112 *r5900:
5113 // end-sanitize-r5900
5114
5115
5116 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5117 "bc0t <OFFSET>"
5118 *mipsI,mipsII,mipsIII,mipsIV:
5119 // start-sanitize-r5900
5120 *r5900:
5121 // end-sanitize-r5900
5122
5123
5124
5125 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5126 "bc0tl <OFFSET>"
5127 *mipsI,mipsII,mipsIII,mipsIV:
5128 *vr5000:
5129 // start-sanitize-vr4320
5130 *vr4320:
5131 // end-sanitize-vr4320
5132 // start-sanitize-vr5400
5133 *vr5400:
5134 // end-sanitize-vr5400
5135 // start-sanitize-r5900
5136 *r5900:
5137 // end-sanitize-r5900
5138
5139
5140 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5141 *mipsIII:
5142 *mipsIV:
5143 *vr5000:
5144 // start-sanitize-vr4320
5145 *vr4320:
5146 // end-sanitize-vr4320
5147 // start-sanitize-vr5400
5148 *vr5400:
5149 // end-sanitize-vr5400
5150 // start-sanitize-r5900
5151 *r5900:
5152 // end-sanitize-r5900
5153 *r3900:
5154 // start-sanitize-tx19
5155 *tx19:
5156 // end-sanitize-tx19
5157 {
5158   unsigned32 instruction = instruction_0;
5159   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5160   int hint = ((instruction >> 16) & 0x0000001F);
5161   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5162   {
5163     address_word vaddr = (op1 + offset);
5164     address_word paddr;
5165     int uncached;
5166     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5167       CacheOp(hint,vaddr,paddr,instruction);
5168   }
5169 }
5170
5171
5172 010000,10000,000000000000000,111001:COP0:32::DI
5173 "di"
5174 *mipsI,mipsII,mipsIII,mipsIV:
5175 *vr5000:
5176 // start-sanitize-vr4320
5177 *vr4320:
5178 // end-sanitize-vr4320
5179 // start-sanitize-vr5400
5180 *vr5400:
5181 // end-sanitize-vr5400
5182 // start-sanitize-r5900
5183 *r5900:
5184 // end-sanitize-r5900
5185
5186
5187 010000,10000,000000000000000,111000:COP0:32::EI
5188 "ei"
5189 *mipsI,mipsII,mipsIII,mipsIV:
5190 *vr5000:
5191 // start-sanitize-vr4320
5192 *vr4320:
5193 // end-sanitize-vr4320
5194 // start-sanitize-vr5400
5195 *vr5400:
5196 // end-sanitize-vr5400
5197 // start-sanitize-r5900
5198 *r5900:
5199 // end-sanitize-r5900
5200
5201
5202 010000,10000,000000000000000,011000:COP0:32::ERET
5203 "eret"
5204 *mipsIII:
5205 *mipsIV:
5206 *vr5000:
5207 // start-sanitize-vr4320
5208 *vr4320:
5209 // end-sanitize-vr4320
5210 // start-sanitize-vr5400
5211 *vr5400:
5212 // end-sanitize-vr5400
5213 // start-sanitize-r5900
5214 *r5900:
5215 // end-sanitize-r5900
5216
5217
5218 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5219 "mfc0 r<RT>, r<RD> # <REGX>"
5220 *mipsI,mipsII,mipsIII,mipsIV:
5221 *vr5000:
5222 // start-sanitize-vr4320
5223 *vr4320:
5224 // end-sanitize-vr4320
5225 // start-sanitize-vr5400
5226 *vr5400:
5227 // end-sanitize-vr5400
5228 // start-sanitize-r5900
5229 *r5900:
5230 // end-sanitize-r5900
5231 {
5232   DecodeCoproc (instruction_0);
5233 }
5234
5235 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5236 "mtc0 r<RT>, r<RD> # <REGX>"
5237 *mipsI,mipsII,mipsIII,mipsIV:
5238 // start-sanitize-tx19
5239 *tx19:
5240 // end-sanitize-tx19
5241 *r3900:
5242 // start-sanitize-vr4320
5243 *vr4320:
5244 // end-sanitize-vr4320
5245 *vr5000:
5246 // start-sanitize-vr5400
5247 *vr5400:
5248 // end-sanitize-vr5400
5249 // start-sanitize-r5900
5250 *r5900:
5251 // end-sanitize-r5900
5252 {
5253   DecodeCoproc (instruction_0);
5254 }
5255
5256
5257 010000,10000,000000000000000,001000:COP0:32::TLBP
5258 "tlbp"
5259 *mipsI,mipsII,mipsIII,mipsIV:
5260 *vr5000:
5261 // start-sanitize-vr4320
5262 *vr4320:
5263 // end-sanitize-vr4320
5264 // start-sanitize-vr5400
5265 *vr5400:
5266 // end-sanitize-vr5400
5267 // start-sanitize-r5900
5268 *r5900:
5269 // end-sanitize-r5900
5270
5271
5272 010000,10000,000000000000000,000001:COP0:32::TLBR
5273 "tlbr"
5274 *mipsI,mipsII,mipsIII,mipsIV:
5275 *vr5000:
5276 // start-sanitize-vr4320
5277 *vr4320:
5278 // end-sanitize-vr4320
5279 // start-sanitize-vr5400
5280 *vr5400:
5281 // end-sanitize-vr5400
5282 // start-sanitize-r5900
5283 *r5900:
5284 // end-sanitize-r5900
5285
5286
5287 010000,10000,000000000000000,000010:COP0:32::TLBWI
5288 "tlbwi"
5289 *mipsI,mipsII,mipsIII,mipsIV:
5290 *vr5000:
5291 // start-sanitize-vr4320
5292 *vr4320:
5293 // end-sanitize-vr4320
5294 // start-sanitize-vr5400
5295 *vr5400:
5296 // end-sanitize-vr5400
5297 // start-sanitize-r5900
5298 *r5900:
5299 // end-sanitize-r5900
5300
5301
5302 010000,10000,000000000000000,000110:COP0:32::TLBWR
5303 "tlbwr"
5304 *mipsI,mipsII,mipsIII,mipsIV:
5305 *vr5000:
5306 // start-sanitize-vr4320
5307 *vr4320:
5308 // end-sanitize-vr4320
5309 // start-sanitize-vr5400
5310 *vr5400:
5311 // end-sanitize-vr5400
5312 // start-sanitize-r5900
5313 *r5900:
5314 // end-sanitize-r5900
5315
5316 \f
5317 :include:::m16.igen
5318 // start-sanitize-vr4320
5319 :include::vr4320:vr4320.igen
5320 // end-sanitize-vr4320
5321 // start-sanitize-vr5400
5322 :include::vr5400:vr5400.igen
5323 :include:64,f::mdmx.igen
5324 // end-sanitize-vr5400
5325 // start-sanitize-r5900
5326 :include::r5900:r5900.igen
5327 // end-sanitize-r5900
5328 :include:::tx.igen
5329 \f
5330 // start-sanitize-cygnus-never
5331
5332 // // FIXME FIXME FIXME What is this instruction?
5333 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5334 // *mipsI:
5335 // *mipsII:
5336 // *mipsIII:
5337 // *mipsIV:
5338 // // start-sanitize-r5900
5339 // *r5900:
5340 // // end-sanitize-r5900
5341 // *r3900:
5342 // // start-sanitize-tx19
5343 // *tx19:
5344 // // end-sanitize-tx19
5345 // {
5346 //   unsigned32 instruction = instruction_0;
5347 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5348 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5349 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5350 //   {
5351 //     if (CoProcPresent(3))
5352 //       SignalException(CoProcessorUnusable);
5353 //     else
5354 //       SignalException(ReservedInstruction,instruction);
5355 //   }
5356 // }
5357
5358 // end-sanitize-cygnus-never
5359 // start-sanitize-cygnus-never
5360
5361 // // FIXME FIXME FIXME What is this?
5362 // 11100,******,00001:RR:16::SDBBP
5363 // *mips16:
5364 // {
5365 //   unsigned32 instruction = instruction_0;
5366 //   if (have_extendval)
5367 //     SignalException (ReservedInstruction, instruction);
5368 //   {
5369 //     SignalException(DebugBreakPoint,instruction);
5370 //   }
5371 // }
5372
5373 // end-sanitize-cygnus-never
5374 // start-sanitize-cygnus-never
5375
5376 // // FIXME FIXME FIXME What is this?
5377 // 000000,********************,001110:SPECIAL:32::SDBBP
5378 // *r3900:
5379 // {
5380 //   unsigned32 instruction = instruction_0;
5381 //   {
5382 //     SignalException(DebugBreakPoint,instruction);
5383 //   }
5384 // }
5385
5386 // end-sanitize-cygnus-never
5387 // start-sanitize-cygnus-never
5388
5389 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5390 // // isn't yet reconized by this simulator.
5391 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5392 // *vr4100:
5393 // {
5394 //   unsigned32 instruction = instruction_0;
5395 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5396 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5397 //   {
5398 //     CHECKHILO("Multiply-Add");
5399 //     {
5400 //       unsigned64 temp = (op1 * op2);
5401 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5402 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5403 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5404 //     }
5405 //   }
5406 // }
5407
5408 // end-sanitize-cygnus-never
5409 // start-sanitize-cygnus-never
5410
5411 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5412 // // isn't yet reconized by this simulator.
5413 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5414 // *vr4100:
5415 // {
5416 //   unsigned32 instruction = instruction_0;
5417 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5418 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5419 //   {
5420 //     CHECKHILO("Multiply-Add");
5421 //     {
5422 //       unsigned64 temp = (op1 * op2);
5423 //       LO = LO + temp;
5424 //     }
5425 //   }
5426 // }
5427
5428 // end-sanitize-cygnus-never