4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator
34 :model:::mipsI:mips3000:
35 :model:::mipsII:mips6000:
36 :model:::mipsIII:mips4000:
37 :model:::mipsIV:mips8000:
38 :model:::mips16:mips16:
39 // start-sanitize-r5900
40 :model:::r5900:mips5900:
42 :model:::r3900:mips3900:
43 // start-sanitize-tx19
46 // start-sanitize-vr4320
47 :model:::vr4320:mips4320:
48 // end-sanitize-vr4320
49 // start-sanitize-vr5400
50 :model:::vr5400:mips5400:
52 // end-sanitize-vr5400
53 :model:::vr5000:mips5000:
57 // Pseudo instructions known by IGEN
60 SignalException (ReservedInstruction, 0);
64 // Pseudo instructions known by interp.c
65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
69 SignalException (ReservedInstruction, instruction_0);
76 // Simulate a 32 bit delayslot instruction
79 :function:::address_word:delayslot32:address_word target
81 instruction_word delay_insn;
82 sim_events_slip (SD, 1);
84 CIA = CIA + 4; /* NOTE not mips16 */
85 STATE |= simDELAYSLOT;
86 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
87 idecode_issue (CPU_, delay_insn, (CIA));
88 STATE &= ~simDELAYSLOT;
92 :function:::address_word:nullify_next_insn32:
94 sim_events_slip (SD, 1);
95 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
102 // Mips Architecture:
104 // CPU Instruction Set (mipsI - mipsIV)
109 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
110 "add r<RD>, r<RS>, r<RT>"
111 *mipsI,mipsII,mipsIII,mipsIV:
113 // start-sanitize-vr4320
115 // end-sanitize-vr4320
116 // start-sanitize-vr5400
118 // end-sanitize-vr5400
119 // start-sanitize-r5900
121 // end-sanitize-r5900
123 // start-sanitize-tx19
127 ALU32_BEGIN (GPR[RS]);
134 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
135 "addi r<RT>, r<RS>, IMMEDIATE"
136 *mipsI,mipsII,mipsIII,mipsIV:
138 // start-sanitize-vr4320
140 // end-sanitize-vr4320
141 // start-sanitize-vr5400
143 // end-sanitize-vr5400
144 // start-sanitize-r5900
146 // end-sanitize-r5900
148 // start-sanitize-tx19
152 ALU32_BEGIN (GPR[RS]);
153 ALU32_ADD (EXTEND16 (IMMEDIATE));
159 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
161 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
162 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
163 TRACE_ALU_RESULT (GPR[rt]);
166 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
167 "addiu r<RT>, r<RS>, <IMMEDIATE>"
168 *mipsI,mipsII,mipsIII,mipsIV:
170 // start-sanitize-vr4320
172 // end-sanitize-vr4320
173 // start-sanitize-vr5400
175 // end-sanitize-vr5400
176 // start-sanitize-r5900
178 // end-sanitize-r5900
180 // start-sanitize-tx19
184 do_addiu (SD_, RS, RT, IMMEDIATE);
189 :function:::void:do_addu:int rs, int rt, int rd
191 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
192 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
193 TRACE_ALU_RESULT (GPR[rd]);
196 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
197 "addu r<RD>, r<RS>, r<RT>"
198 *mipsI,mipsII,mipsIII,mipsIV:
200 // start-sanitize-vr4320
202 // end-sanitize-vr4320
203 // start-sanitize-vr5400
205 // end-sanitize-vr5400
206 // start-sanitize-r5900
208 // end-sanitize-r5900
210 // start-sanitize-tx19
214 do_addu (SD_, RS, RT, RD);
219 :function:::void:do_and:int rs, int rt, int rd
221 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
222 GPR[rd] = GPR[rs] & GPR[rt];
223 TRACE_ALU_RESULT (GPR[rd]);
226 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
227 "and r<RD>, r<RS>, r<RT>"
228 *mipsI,mipsII,mipsIII,mipsIV:
230 // start-sanitize-vr4320
232 // end-sanitize-vr4320
233 // start-sanitize-vr5400
235 // end-sanitize-vr5400
236 // start-sanitize-r5900
238 // end-sanitize-r5900
240 // start-sanitize-tx19
244 do_and (SD_, RS, RT, RD);
249 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
250 "and r<RT>, r<RS>, <IMMEDIATE>"
251 *mipsI,mipsII,mipsIII,mipsIV:
253 // start-sanitize-vr4320
255 // end-sanitize-vr4320
256 // start-sanitize-vr5400
258 // end-sanitize-vr5400
259 // start-sanitize-r5900
261 // end-sanitize-r5900
263 // start-sanitize-tx19
267 GPR[RT] = GPR[RS] & IMMEDIATE;
272 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
273 "beq r<RS>, r<RT>, <OFFSET>"
274 *mipsI,mipsII,mipsIII,mipsIV:
276 // start-sanitize-vr4320
278 // end-sanitize-vr4320
279 // start-sanitize-vr5400
281 // end-sanitize-vr5400
282 // start-sanitize-r5900
284 // end-sanitize-r5900
286 // start-sanitize-tx19
290 address_word offset = EXTEND16 (OFFSET) << 2;
291 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
292 DELAY_SLOT (NIA + offset);
297 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
298 "beql r<RS>, r<RT>, <OFFSET>"
303 // start-sanitize-vr4320
305 // end-sanitize-vr4320
306 // start-sanitize-vr5400
308 // end-sanitize-vr5400
309 // start-sanitize-r5900
311 // end-sanitize-r5900
313 // start-sanitize-tx19
317 address_word offset = EXTEND16 (OFFSET) << 2;
318 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
319 DELAY_SLOT (NIA + offset);
321 NULLIFY_NEXT_INSTRUCTION ();
326 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
327 "bgez r<RS>, <OFFSET>"
328 *mipsI,mipsII,mipsIII,mipsIV:
330 // start-sanitize-vr4320
332 // end-sanitize-vr4320
333 // start-sanitize-vr5400
335 // end-sanitize-vr5400
336 // start-sanitize-r5900
338 // end-sanitize-r5900
340 // start-sanitize-tx19
344 address_word offset = EXTEND16 (OFFSET) << 2;
345 if ((signed_word) GPR[RS] >= 0)
346 DELAY_SLOT (NIA + offset);
351 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
352 "bgezal r<RS>, <OFFSET>"
353 *mipsI,mipsII,mipsIII,mipsIV:
355 // start-sanitize-vr4320
357 // end-sanitize-vr4320
358 // start-sanitize-vr5400
360 // end-sanitize-vr5400
361 // start-sanitize-r5900
363 // end-sanitize-r5900
365 // start-sanitize-tx19
369 address_word offset = EXTEND16 (OFFSET) << 2;
371 if ((signed_word) GPR[RS] >= 0)
372 DELAY_SLOT (NIA + offset);
377 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
378 "bgezall r<RS>, <OFFSET>"
383 // start-sanitize-vr4320
385 // end-sanitize-vr4320
386 // start-sanitize-vr5400
388 // end-sanitize-vr5400
389 // start-sanitize-r5900
391 // end-sanitize-r5900
393 // start-sanitize-tx19
397 address_word offset = EXTEND16 (OFFSET) << 2;
399 /* NOTE: The branch occurs AFTER the next instruction has been
401 if ((signed_word) GPR[RS] >= 0)
402 DELAY_SLOT (NIA + offset);
404 NULLIFY_NEXT_INSTRUCTION ();
409 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
410 "bgezl r<RS>, <OFFSET>"
415 // start-sanitize-vr4320
417 // end-sanitize-vr4320
418 // start-sanitize-vr5400
420 // end-sanitize-vr5400
421 // start-sanitize-r5900
423 // end-sanitize-r5900
425 // start-sanitize-tx19
429 address_word offset = EXTEND16 (OFFSET) << 2;
430 if ((signed_word) GPR[RS] >= 0)
431 DELAY_SLOT (NIA + offset);
433 NULLIFY_NEXT_INSTRUCTION ();
438 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
439 "bgtz r<RS>, <OFFSET>"
440 *mipsI,mipsII,mipsIII,mipsIV:
442 // start-sanitize-vr4320
444 // end-sanitize-vr4320
445 // start-sanitize-vr5400
447 // end-sanitize-vr5400
448 // start-sanitize-r5900
450 // end-sanitize-r5900
452 // start-sanitize-tx19
456 address_word offset = EXTEND16 (OFFSET) << 2;
457 if ((signed_word) GPR[RS] > 0)
458 DELAY_SLOT (NIA + offset);
463 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
464 "bgtzl r<RS>, <OFFSET>"
469 // start-sanitize-vr4320
471 // end-sanitize-vr4320
472 // start-sanitize-vr5400
474 // end-sanitize-vr5400
475 // start-sanitize-r5900
477 // end-sanitize-r5900
479 // start-sanitize-tx19
483 address_word offset = EXTEND16 (OFFSET) << 2;
484 /* NOTE: The branch occurs AFTER the next instruction has been
486 if ((signed_word) GPR[RS] > 0)
487 DELAY_SLOT (NIA + offset);
489 NULLIFY_NEXT_INSTRUCTION ();
494 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
495 "blez r<RS>, <OFFSET>"
496 *mipsI,mipsII,mipsIII,mipsIV:
498 // start-sanitize-vr4320
500 // end-sanitize-vr4320
501 // start-sanitize-vr5400
503 // end-sanitize-vr5400
504 // start-sanitize-r5900
506 // end-sanitize-r5900
508 // start-sanitize-tx19
512 address_word offset = EXTEND16 (OFFSET) << 2;
513 /* NOTE: The branch occurs AFTER the next instruction has been
515 if ((signed_word) GPR[RS] <= 0)
516 DELAY_SLOT (NIA + offset);
521 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
522 "bgezl r<RS>, <OFFSET>"
527 // start-sanitize-vr4320
529 // end-sanitize-vr4320
530 // start-sanitize-vr5400
532 // end-sanitize-vr5400
533 // start-sanitize-r5900
535 // end-sanitize-r5900
537 // start-sanitize-tx19
541 address_word offset = EXTEND16 (OFFSET) << 2;
542 if ((signed_word) GPR[RS] <= 0)
543 DELAY_SLOT (NIA + offset);
545 NULLIFY_NEXT_INSTRUCTION ();
550 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
551 "bltz r<RS>, <OFFSET>"
552 *mipsI,mipsII,mipsIII,mipsIV:
554 // start-sanitize-vr4320
556 // end-sanitize-vr4320
557 // start-sanitize-vr5400
559 // end-sanitize-vr5400
560 // start-sanitize-r5900
562 // end-sanitize-r5900
564 // start-sanitize-tx19
568 address_word offset = EXTEND16 (OFFSET) << 2;
569 if ((signed_word) GPR[RS] < 0)
570 DELAY_SLOT (NIA + offset);
575 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
576 "bltzal r<RS>, <OFFSET>"
577 *mipsI,mipsII,mipsIII,mipsIV:
579 // start-sanitize-vr4320
581 // end-sanitize-vr4320
582 // start-sanitize-vr5400
584 // end-sanitize-vr5400
585 // start-sanitize-r5900
587 // end-sanitize-r5900
589 // start-sanitize-tx19
593 address_word offset = EXTEND16 (OFFSET) << 2;
595 /* NOTE: The branch occurs AFTER the next instruction has been
597 if ((signed_word) GPR[RS] < 0)
598 DELAY_SLOT (NIA + offset);
603 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
604 "bltzall r<RS>, <OFFSET>"
609 // start-sanitize-vr4320
611 // end-sanitize-vr4320
612 // start-sanitize-vr5400
614 // end-sanitize-vr5400
615 // start-sanitize-r5900
617 // end-sanitize-r5900
619 // start-sanitize-tx19
623 address_word offset = EXTEND16 (OFFSET) << 2;
625 if ((signed_word) GPR[RS] < 0)
626 DELAY_SLOT (NIA + offset);
628 NULLIFY_NEXT_INSTRUCTION ();
633 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
634 "bltzl r<RS>, <OFFSET>"
639 // start-sanitize-vr4320
641 // end-sanitize-vr4320
642 // start-sanitize-vr5400
644 // end-sanitize-vr5400
645 // start-sanitize-r5900
647 // end-sanitize-r5900
649 // start-sanitize-tx19
653 address_word offset = EXTEND16 (OFFSET) << 2;
654 /* NOTE: The branch occurs AFTER the next instruction has been
656 if ((signed_word) GPR[RS] < 0)
657 DELAY_SLOT (NIA + offset);
659 NULLIFY_NEXT_INSTRUCTION ();
664 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
665 "bne r<RS>, r<RT>, <OFFSET>"
666 *mipsI,mipsII,mipsIII,mipsIV:
668 // start-sanitize-vr4320
670 // end-sanitize-vr4320
671 // start-sanitize-vr5400
673 // end-sanitize-vr5400
674 // start-sanitize-r5900
676 // end-sanitize-r5900
678 // start-sanitize-tx19
682 address_word offset = EXTEND16 (OFFSET) << 2;
683 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
684 DELAY_SLOT (NIA + offset);
689 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
690 "bnel r<RS>, r<RT>, <OFFSET>"
695 // start-sanitize-vr4320
697 // end-sanitize-vr4320
698 // start-sanitize-vr5400
700 // end-sanitize-vr5400
701 // start-sanitize-r5900
703 // end-sanitize-r5900
705 // start-sanitize-tx19
709 address_word offset = EXTEND16 (OFFSET) << 2;
710 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
711 DELAY_SLOT (NIA + offset);
713 NULLIFY_NEXT_INSTRUCTION ();
718 000000,20.CODE,001101:SPECIAL:32::BREAK
720 *mipsI,mipsII,mipsIII,mipsIV:
722 // start-sanitize-vr4320
724 // end-sanitize-vr4320
725 // start-sanitize-vr5400
727 // end-sanitize-vr5400
728 // start-sanitize-r5900
730 // end-sanitize-r5900
732 // start-sanitize-tx19
736 SignalException(BreakPoint, instruction_0);
741 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
743 *mipsI,mipsII,mipsIII,mipsIV:
744 // start-sanitize-r5900
746 // end-sanitize-r5900
748 // start-sanitize-tx19
752 DecodeCoproc (instruction_0);
757 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
758 "dadd r<RD>, r<RS>, r<RT>"
762 // start-sanitize-vr4320
764 // end-sanitize-vr4320
765 // start-sanitize-vr5400
767 // end-sanitize-vr5400
768 // start-sanitize-r5900
770 // end-sanitize-r5900
771 // start-sanitize-tx19
775 /* this check's for overflow */
776 ALU64_BEGIN (GPR[RS]);
783 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
784 "daddi r<RT>, r<RS>, <IMMEDIATE>"
788 // start-sanitize-vr4320
790 // end-sanitize-vr4320
791 // start-sanitize-vr5400
793 // end-sanitize-vr5400
794 // start-sanitize-r5900
796 // end-sanitize-r5900
797 // start-sanitize-tx19
801 ALU64_BEGIN (GPR[RS]);
802 ALU64_ADD (EXTEND16 (IMMEDIATE));
808 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
810 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
811 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
812 TRACE_ALU_RESULT (GPR[rt]);
815 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
816 "daddu r<RT>, r<RS>, <IMMEDIATE>"
820 // start-sanitize-vr4320
822 // end-sanitize-vr4320
823 // start-sanitize-vr5400
825 // end-sanitize-vr5400
826 // start-sanitize-r5900
828 // end-sanitize-r5900
829 // start-sanitize-tx19
833 do_daddiu (SD_, RS, RT, IMMEDIATE);
838 :function:::void:do_daddu:int rs, int rt, int rd
840 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
841 GPR[rd] = GPR[rs] + GPR[rt];
842 TRACE_ALU_RESULT (GPR[rd]);
845 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
846 "daddu r<RD>, r<RS>, r<RT>"
850 // start-sanitize-vr4320
852 // end-sanitize-vr4320
853 // start-sanitize-vr5400
855 // end-sanitize-vr5400
856 // start-sanitize-r5900
858 // end-sanitize-r5900
859 // start-sanitize-tx19
863 do_daddu (SD_, RS, RT, RD);
868 :function:64::void:do_ddiv:int rs, int rt
870 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
871 CHECKHILO ("Division");
873 signed64 n = GPR[rs];
874 signed64 d = GPR[rt];
877 LO = SIGNED64 (0x8000000000000000);
880 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
882 LO = SIGNED64 (0x8000000000000000);
891 TRACE_ALU_RESULT2 (HI, LO);
894 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
899 // start-sanitize-vr4320
901 // end-sanitize-vr4320
902 // start-sanitize-vr5400
904 // end-sanitize-vr5400
905 // start-sanitize-r5900
907 // end-sanitize-r5900
908 // start-sanitize-tx19
912 do_ddiv (SD_, RS, RT);
917 :function:64::void:do_ddivu:int rs, int rt
919 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
920 CHECKHILO ("Division");
922 unsigned64 n = GPR[rs];
923 unsigned64 d = GPR[rt];
926 LO = SIGNED64 (0x8000000000000000);
935 TRACE_ALU_RESULT2 (HI, LO);
938 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
943 // start-sanitize-vr4320
945 // end-sanitize-vr4320
946 // start-sanitize-vr5400
948 // end-sanitize-vr5400
949 // start-sanitize-tx19
953 do_ddivu (SD_, RS, RT);
958 :function:::void:do_div:int rs, int rt
960 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
961 CHECKHILO("Division");
963 signed32 n = GPR[rs];
964 signed32 d = GPR[rt];
967 LO = EXTEND32 (0x80000000);
970 else if (n == SIGNED32 (0x80000000) && d == -1)
972 LO = EXTEND32 (0x80000000);
977 LO = EXTEND32 (n / d);
978 HI = EXTEND32 (n % d);
981 TRACE_ALU_RESULT2 (HI, LO);
984 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
986 *mipsI,mipsII,mipsIII,mipsIV:
988 // start-sanitize-vr4320
990 // end-sanitize-vr4320
991 // start-sanitize-vr5400
993 // end-sanitize-vr5400
994 // start-sanitize-r5900
996 // end-sanitize-r5900
998 // start-sanitize-tx19
1000 // end-sanitize-tx19
1002 do_div (SD_, RS, RT);
1007 :function:::void:do_divu:int rs, int rt
1009 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1010 CHECKHILO ("Division");
1012 unsigned32 n = GPR[rs];
1013 unsigned32 d = GPR[rt];
1016 LO = EXTEND32 (0x80000000);
1021 LO = EXTEND32 (n / d);
1022 HI = EXTEND32 (n % d);
1025 TRACE_ALU_RESULT2 (HI, LO);
1028 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1030 *mipsI,mipsII,mipsIII,mipsIV:
1032 // start-sanitize-vr4320
1034 // end-sanitize-vr4320
1035 // start-sanitize-vr5400
1037 // end-sanitize-vr5400
1038 // start-sanitize-r5900
1040 // end-sanitize-r5900
1042 // start-sanitize-tx19
1044 // end-sanitize-tx19
1046 do_divu (SD_, RS, RT);
1051 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1061 unsigned64 op1 = GPR[rs];
1062 unsigned64 op2 = GPR[rt];
1063 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1064 CHECKHILO ("Multiplication");
1065 /* make signed multiply unsigned */
1080 /* multuply out the 4 sub products */
1081 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1082 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1083 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1084 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1085 /* add the products */
1086 mid = ((unsigned64) VH4_8 (m00)
1087 + (unsigned64) VL4_8 (m10)
1088 + (unsigned64) VL4_8 (m01));
1089 lo = U8_4 (mid, m00);
1091 + (unsigned64) VH4_8 (mid)
1092 + (unsigned64) VH4_8 (m01)
1093 + (unsigned64) VH4_8 (m10));
1103 /* save the result HI/LO (and a gpr) */
1108 TRACE_ALU_RESULT2 (HI, LO);
1111 :function:::void:do_dmult:int rs, int rt, int rd
1113 do_dmultx (SD_, rs, rt, rd, 1);
1116 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1117 "dmult r<RS>, r<RT>"
1119 // start-sanitize-tx19
1121 // end-sanitize-tx19
1122 // start-sanitize-vr4320
1124 // end-sanitize-vr4320
1126 do_dmult (SD_, RS, RT, 0);
1129 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1130 "dmult r<RS>, r<RT>":RD == 0
1131 "dmult r<RD>, r<RS>, r<RT>"
1133 // start-sanitize-vr5400
1135 // end-sanitize-vr5400
1137 do_dmult (SD_, RS, RT, RD);
1142 :function:::void:do_dmultu:int rs, int rt, int rd
1144 do_dmultx (SD_, rs, rt, rd, 0);
1147 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1148 "dmultu r<RS>, r<RT>"
1150 // start-sanitize-tx19
1152 // end-sanitize-tx19
1153 // start-sanitize-vr4320
1155 // end-sanitize-vr4320
1157 do_dmultu (SD_, RS, RT, 0);
1160 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1161 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1162 "dmultu r<RS>, r<RT>"
1164 // start-sanitize-vr5400
1166 // end-sanitize-vr5400
1168 do_dmultu (SD_, RS, RT, RD);
1173 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1174 "dsll r<RD>, r<RT>, <SHIFT>"
1178 // start-sanitize-vr4320
1180 // end-sanitize-vr4320
1181 // start-sanitize-vr5400
1183 // end-sanitize-vr5400
1184 // start-sanitize-r5900
1186 // end-sanitize-r5900
1187 // start-sanitize-tx19
1189 // end-sanitize-tx19
1192 GPR[RD] = GPR[RT] << s;
1196 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1197 "dsll32 r<RD>, r<RT>, <SHIFT>"
1201 // start-sanitize-vr4320
1203 // end-sanitize-vr4320
1204 // start-sanitize-vr5400
1206 // end-sanitize-vr5400
1207 // start-sanitize-r5900
1209 // end-sanitize-r5900
1210 // start-sanitize-tx19
1212 // end-sanitize-tx19
1215 GPR[RD] = GPR[RT] << s;
1220 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1221 "dsllv r<RD>, r<RT>, r<RS>"
1225 // start-sanitize-vr4320
1227 // end-sanitize-vr4320
1228 // start-sanitize-vr5400
1230 // end-sanitize-vr5400
1231 // start-sanitize-r5900
1233 // end-sanitize-r5900
1234 // start-sanitize-tx19
1236 // end-sanitize-tx19
1238 int s = MASKED64 (GPR[RS], 5, 0);
1239 GPR[RD] = GPR[RT] << s;
1244 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1245 "dsra r<RD>, r<RT>, <SHIFT>"
1249 // start-sanitize-vr4320
1251 // end-sanitize-vr4320
1252 // start-sanitize-vr5400
1254 // end-sanitize-vr5400
1255 // start-sanitize-r5900
1257 // end-sanitize-r5900
1258 // start-sanitize-tx19
1260 // end-sanitize-tx19
1263 GPR[RD] = ((signed64) GPR[RT]) >> s;
1267 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1268 "dsra32 r<RT>, r<RD>, <SHIFT>"
1272 // start-sanitize-vr4320
1274 // end-sanitize-vr4320
1275 // start-sanitize-vr5400
1277 // end-sanitize-vr5400
1278 // start-sanitize-r5900
1280 // end-sanitize-r5900
1281 // start-sanitize-tx19
1283 // end-sanitize-tx19
1286 GPR[RD] = ((signed64) GPR[RT]) >> s;
1290 :function:::void:do_srav:int rs, int rt, int rd
1292 int s = MASKED64 (GPR[rs], 5, 0);
1293 TRACE_ALU_INPUT2 (GPR[rt], s);
1294 GPR[rd] = ((signed64) GPR[rt]) >> s;
1295 TRACE_ALU_RESULT (GPR[rd]);
1298 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1299 "dsra32 r<RT>, r<RD>, r<RS>"
1303 // start-sanitize-vr4320
1305 // end-sanitize-vr4320
1306 // start-sanitize-vr5400
1308 // end-sanitize-vr5400
1309 // start-sanitize-r5900
1311 // end-sanitize-r5900
1312 // start-sanitize-tx19
1314 // end-sanitize-tx19
1316 do_srav (SD_, RS, RT, RD);
1320 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1321 "dsrav r<RD>, r<RT>, <SHIFT>"
1325 // start-sanitize-vr4320
1327 // end-sanitize-vr4320
1328 // start-sanitize-vr5400
1330 // end-sanitize-vr5400
1331 // start-sanitize-r5900
1333 // end-sanitize-r5900
1334 // start-sanitize-tx19
1336 // end-sanitize-tx19
1339 GPR[RD] = (unsigned64) GPR[RT] >> s;
1343 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1344 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1348 // start-sanitize-vr4320
1350 // end-sanitize-vr4320
1351 // start-sanitize-vr5400
1353 // end-sanitize-vr5400
1354 // start-sanitize-r5900
1356 // end-sanitize-r5900
1357 // start-sanitize-tx19
1359 // end-sanitize-tx19
1362 GPR[RD] = (unsigned64) GPR[RT] >> s;
1366 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1367 "dsrl32 r<RD>, r<RT>, r<RS>"
1371 // start-sanitize-vr4320
1373 // end-sanitize-vr4320
1374 // start-sanitize-vr5400
1376 // end-sanitize-vr5400
1377 // start-sanitize-r5900
1379 // end-sanitize-r5900
1380 // start-sanitize-tx19
1382 // end-sanitize-tx19
1384 int s = MASKED64 (GPR[RS], 5, 0);
1385 GPR[RD] = (unsigned64) GPR[RT] >> s;
1389 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1390 "dsub r<RD>, r<RS>, r<RT>"
1394 // start-sanitize-vr4320
1396 // end-sanitize-vr4320
1397 // start-sanitize-vr5400
1399 // end-sanitize-vr5400
1400 // start-sanitize-r5900
1402 // end-sanitize-r5900
1403 // start-sanitize-tx19
1405 // end-sanitize-tx19
1407 ALU64_BEGIN (GPR[RS]);
1408 ALU64_SUB (GPR[RT]);
1409 ALU64_END (GPR[RD]);
1413 :function:::void:do_dsubu:int rs, int rt, int rd
1415 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1416 GPR[rd] = GPR[rs] - GPR[rt];
1417 TRACE_ALU_RESULT (GPR[rd]);
1420 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1421 "dsubu r<RD>, r<RS>, r<RT>"
1425 // start-sanitize-vr4320
1427 // end-sanitize-vr4320
1428 // start-sanitize-vr5400
1430 // end-sanitize-vr5400
1431 // start-sanitize-r5900
1433 // end-sanitize-r5900
1434 // start-sanitize-tx19
1436 // end-sanitize-tx19
1438 do_dsubu (SD_, RS, RT, RD);
1442 000010,26.INSTR_INDEX:NORMAL:32::J
1444 *mipsI,mipsII,mipsIII,mipsIV:
1446 // start-sanitize-vr4320
1448 // end-sanitize-vr4320
1449 // start-sanitize-vr5400
1451 // end-sanitize-vr5400
1452 // start-sanitize-r5900
1454 // end-sanitize-r5900
1456 // start-sanitize-tx19
1458 // end-sanitize-tx19
1460 /* NOTE: The region used is that of the delay slot NIA and NOT the
1461 current instruction */
1462 address_word region = (NIA & MASK (63, 28));
1463 DELAY_SLOT (region | (INSTR_INDEX << 2));
1467 000011,26.INSTR_INDEX:NORMAL:32::JAL
1469 *mipsI,mipsII,mipsIII,mipsIV:
1471 // start-sanitize-vr4320
1473 // end-sanitize-vr4320
1474 // start-sanitize-vr5400
1476 // end-sanitize-vr5400
1477 // start-sanitize-r5900
1479 // end-sanitize-r5900
1481 // start-sanitize-tx19
1483 // end-sanitize-tx19
1485 /* NOTE: The region used is that of the delay slot and NOT the
1486 current instruction */
1487 address_word region = (NIA & MASK (63, 28));
1489 DELAY_SLOT (region | (INSTR_INDEX << 2));
1493 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1494 "jalr r<RS>":RD == 31
1496 *mipsI,mipsII,mipsIII,mipsIV:
1498 // start-sanitize-vr4320
1500 // end-sanitize-vr4320
1501 // start-sanitize-vr5400
1503 // end-sanitize-vr5400
1504 // start-sanitize-r5900
1506 // end-sanitize-r5900
1508 // start-sanitize-tx19
1510 // end-sanitize-tx19
1512 address_word temp = GPR[RS];
1518 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1520 *mipsI,mipsII,mipsIII,mipsIV:
1522 // start-sanitize-vr4320
1524 // end-sanitize-vr4320
1525 // start-sanitize-vr5400
1527 // end-sanitize-vr5400
1528 // start-sanitize-r5900
1530 // end-sanitize-r5900
1532 // start-sanitize-tx19
1534 // end-sanitize-tx19
1536 DELAY_SLOT (GPR[RS]);
1540 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1542 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1543 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1544 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1551 vaddr = base + offset;
1552 if ((vaddr & access) != 0)
1553 SignalExceptionAddressLoad ();
1554 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1555 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1556 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1557 byte = ((vaddr & mask) ^ bigendiancpu);
1558 return (memval >> (8 * byte));
1562 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1563 "lb r<RT>, <OFFSET>(r<BASE>)"
1564 *mipsI,mipsII,mipsIII,mipsIV:
1566 // start-sanitize-vr4320
1568 // end-sanitize-vr4320
1569 // start-sanitize-vr5400
1571 // end-sanitize-vr5400
1572 // start-sanitize-r5900
1574 // end-sanitize-r5900
1576 // start-sanitize-tx19
1578 // end-sanitize-tx19
1580 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1584 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1585 "lbu r<RT>, <OFFSET>(r<BASE>)"
1586 *mipsI,mipsII,mipsIII,mipsIV:
1588 // start-sanitize-vr4320
1590 // end-sanitize-vr4320
1591 // start-sanitize-vr5400
1593 // end-sanitize-vr5400
1594 // start-sanitize-r5900
1596 // end-sanitize-r5900
1598 // start-sanitize-tx19
1600 // end-sanitize-tx19
1602 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1606 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1607 "ld r<RT>, <OFFSET>(r<BASE>)"
1611 // start-sanitize-vr4320
1613 // end-sanitize-vr4320
1614 // start-sanitize-vr5400
1616 // end-sanitize-vr5400
1617 // start-sanitize-r5900
1619 // end-sanitize-r5900
1620 // start-sanitize-tx19
1622 // end-sanitize-tx19
1624 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1628 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1629 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1634 // start-sanitize-vr4320
1636 // end-sanitize-vr4320
1637 // start-sanitize-vr5400
1639 // end-sanitize-vr5400
1641 // start-sanitize-tx19
1643 // end-sanitize-tx19
1645 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1651 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1652 "ldl r<RT>, <OFFSET>(r<BASE>)"
1656 // start-sanitize-vr4320
1658 // end-sanitize-vr4320
1659 // start-sanitize-vr5400
1661 // end-sanitize-vr5400
1662 // start-sanitize-r5900
1664 // end-sanitize-r5900
1665 // start-sanitize-tx19
1667 // end-sanitize-tx19
1669 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1673 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1674 "ldr r<RT>, <OFFSET>(r<BASE>)"
1678 // start-sanitize-vr4320
1680 // end-sanitize-vr4320
1681 // start-sanitize-vr5400
1683 // end-sanitize-vr5400
1684 // start-sanitize-r5900
1686 // end-sanitize-r5900
1687 // start-sanitize-tx19
1689 // end-sanitize-tx19
1691 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1695 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1696 "lh r<RT>, <OFFSET>(r<BASE>)"
1697 *mipsI,mipsII,mipsIII,mipsIV:
1699 // start-sanitize-vr4320
1701 // end-sanitize-vr4320
1702 // start-sanitize-vr5400
1704 // end-sanitize-vr5400
1705 // start-sanitize-r5900
1707 // end-sanitize-r5900
1709 // start-sanitize-tx19
1711 // end-sanitize-tx19
1713 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1717 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1718 "lhu r<RT>, <OFFSET>(r<BASE>)"
1719 *mipsI,mipsII,mipsIII,mipsIV:
1721 // start-sanitize-vr4320
1723 // end-sanitize-vr4320
1724 // start-sanitize-vr5400
1726 // end-sanitize-vr5400
1727 // start-sanitize-r5900
1729 // end-sanitize-r5900
1731 // start-sanitize-tx19
1733 // end-sanitize-tx19
1735 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1739 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1740 "ll r<RT>, <OFFSET>(r<BASE>)"
1745 // start-sanitize-vr4320
1747 // end-sanitize-vr4320
1748 // start-sanitize-vr5400
1750 // end-sanitize-vr5400
1751 // start-sanitize-r5900
1753 // end-sanitize-r5900
1754 // start-sanitize-tx19
1756 // end-sanitize-tx19
1758 unsigned32 instruction = instruction_0;
1759 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1760 int destreg = ((instruction >> 16) & 0x0000001F);
1761 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1763 address_word vaddr = ((unsigned64)op1 + offset);
1766 if ((vaddr & 3) != 0)
1767 SignalExceptionAddressLoad();
1770 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1772 unsigned64 memval = 0;
1773 unsigned64 memval1 = 0;
1774 unsigned64 mask = 0x7;
1775 unsigned int shift = 2;
1776 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1777 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1779 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1780 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1781 byte = ((vaddr & mask) ^ (bigend << shift));
1782 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1790 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1791 "lld r<RT>, <OFFSET>(r<BASE>)"
1795 // start-sanitize-vr4320
1797 // end-sanitize-vr4320
1798 // start-sanitize-vr5400
1800 // end-sanitize-vr5400
1801 // start-sanitize-r5900
1803 // end-sanitize-r5900
1804 // start-sanitize-tx19
1806 // end-sanitize-tx19
1808 unsigned32 instruction = instruction_0;
1809 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1810 int destreg = ((instruction >> 16) & 0x0000001F);
1811 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1813 address_word vaddr = ((unsigned64)op1 + offset);
1816 if ((vaddr & 7) != 0)
1817 SignalExceptionAddressLoad();
1820 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1822 unsigned64 memval = 0;
1823 unsigned64 memval1 = 0;
1824 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1825 GPR[destreg] = memval;
1833 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1834 "lui r<RT>, <IMMEDIATE>"
1835 *mipsI,mipsII,mipsIII,mipsIV:
1837 // start-sanitize-vr4320
1839 // end-sanitize-vr4320
1840 // start-sanitize-vr5400
1842 // end-sanitize-vr5400
1843 // start-sanitize-r5900
1845 // end-sanitize-r5900
1847 // start-sanitize-tx19
1849 // end-sanitize-tx19
1851 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1855 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1856 "lw r<RT>, <OFFSET>(r<BASE>)"
1857 *mipsI,mipsII,mipsIII,mipsIV:
1859 // start-sanitize-vr4320
1861 // end-sanitize-vr4320
1862 // start-sanitize-vr5400
1864 // end-sanitize-vr5400
1865 // start-sanitize-r5900
1867 // end-sanitize-r5900
1869 // start-sanitize-tx19
1871 // end-sanitize-tx19
1873 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1877 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1878 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1879 *mipsI,mipsII,mipsIII,mipsIV:
1881 // start-sanitize-vr4320
1883 // end-sanitize-vr4320
1884 // start-sanitize-vr5400
1886 // end-sanitize-vr5400
1887 // start-sanitize-r5900
1889 // end-sanitize-r5900
1891 // start-sanitize-tx19
1893 // end-sanitize-tx19
1895 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1899 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1901 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1902 address_word reverseendian = (ReverseEndian ? -1 : 0);
1903 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1910 vaddr = base + offset;
1911 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1912 paddr = (paddr ^ (reverseendian & mask));
1913 if (BigEndianMem == 0)
1914 paddr = paddr & ~access;
1915 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1916 LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
1917 /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
1918 (long) vaddr, byte, (long) paddr, (long) memval); */
1919 if ((byte & ~access) == 0)
1921 int bits = 8 * (access - byte);
1922 unsigned_word screen = LSMASK (bits - 1, 0);
1924 rt |= ((memval << bits) & ~screen);
1928 unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
1930 rt |= ((memval >> (8 * (mask - byte))) & ~screen);
1936 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1937 "lwl r<RT>, <OFFSET>(r<BASE>)"
1938 *mipsI,mipsII,mipsIII,mipsIV:
1940 // start-sanitize-vr4320
1942 // end-sanitize-vr4320
1943 // start-sanitize-vr5400
1945 // end-sanitize-vr5400
1946 // start-sanitize-r5900
1948 // end-sanitize-r5900
1950 // start-sanitize-tx19
1952 // end-sanitize-tx19
1954 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
1958 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1960 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1961 address_word reverseendian = (ReverseEndian ? -1 : 0);
1962 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1969 vaddr = base + offset;
1970 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1971 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1972 paddr = (paddr ^ (reverseendian & mask));
1973 if (BigEndianMem != 0)
1974 paddr = paddr & ~access;
1975 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1976 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1977 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1978 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1979 (long) paddr, byte, (long) paddr, (long) memval); */
1981 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1983 rt |= (memval >> (8 * byte)) & screen;
1989 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1990 "lwr r<RT>, <OFFSET>(r<BASE>)"
1991 *mipsI,mipsII,mipsIII,mipsIV:
1993 // start-sanitize-vr4320
1995 // end-sanitize-vr4320
1996 // start-sanitize-vr5400
1998 // end-sanitize-vr5400
1999 // start-sanitize-r5900
2001 // end-sanitize-r5900
2003 // start-sanitize-tx19
2005 // end-sanitize-tx19
2007 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2011 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2012 "lwu r<RT>, <OFFSET>(r<BASE>)"
2016 // start-sanitize-vr4320
2018 // end-sanitize-vr4320
2019 // start-sanitize-vr5400
2021 // end-sanitize-vr5400
2022 // start-sanitize-r5900
2024 // end-sanitize-r5900
2025 // start-sanitize-tx19
2027 // end-sanitize-tx19
2029 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2033 :function:::void:do_mfhi:int rd
2035 TRACE_ALU_INPUT1 (HI);
2037 TRACE_ALU_RESULT (GPR[rd]);
2043 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2045 *mipsI,mipsII,mipsIII,mipsIV:
2047 // start-sanitize-vr4320
2049 // end-sanitize-vr4320
2050 // start-sanitize-vr5400
2052 // end-sanitize-vr5400
2053 // start-sanitize-r5900
2055 // end-sanitize-r5900
2057 // start-sanitize-tx19
2059 // end-sanitize-tx19
2066 :function:::void:do_mflo:int rd
2068 TRACE_ALU_INPUT1 (LO);
2070 TRACE_ALU_RESULT (GPR[rd]);
2072 LOACCESS = 3; /* 3rd instruction will be safe */
2076 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2078 *mipsI,mipsII,mipsIII,mipsIV:
2080 // start-sanitize-vr4320
2082 // end-sanitize-vr4320
2083 // start-sanitize-vr5400
2085 // end-sanitize-vr5400
2086 // start-sanitize-r5900
2088 // end-sanitize-r5900
2090 // start-sanitize-tx19
2092 // end-sanitize-tx19
2099 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2100 "movn r<RD>, r<RS>, r<RT>"
2103 // start-sanitize-vr4320
2105 // end-sanitize-vr4320
2106 // start-sanitize-vr5400
2108 // end-sanitize-vr5400
2109 // start-sanitize-r5900
2111 // end-sanitize-r5900
2119 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2120 "movz r<RD>, r<RS>, r<RT>"
2123 // start-sanitize-vr4320
2125 // end-sanitize-vr4320
2126 // start-sanitize-vr5400
2128 // end-sanitize-vr5400
2129 // start-sanitize-r5900
2131 // end-sanitize-r5900
2139 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2141 *mipsI,mipsII,mipsIII,mipsIV:
2143 // start-sanitize-vr4320
2145 // end-sanitize-vr4320
2146 // start-sanitize-vr5400
2148 // end-sanitize-vr5400
2149 // start-sanitize-r5900
2151 // end-sanitize-r5900
2153 // start-sanitize-tx19
2155 // end-sanitize-tx19
2159 sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2163 HIACCESS = 3; /* 3rd instruction will be safe */
2169 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2171 *mipsI,mipsII,mipsIII,mipsIV:
2173 // start-sanitize-vr4320
2175 // end-sanitize-vr4320
2176 // start-sanitize-vr5400
2178 // end-sanitize-vr5400
2179 // start-sanitize-r5900
2181 // end-sanitize-r5900
2183 // start-sanitize-tx19
2185 // end-sanitize-tx19
2189 sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2193 LOACCESS = 3; /* 3rd instruction will be safe */
2199 :function:::void:do_mult:int rs, int rt, int rd
2202 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2203 CHECKHILO ("Multiplication");
2204 prod = (((signed64)(signed32) GPR[rs])
2205 * ((signed64)(signed32) GPR[rt]));
2206 LO = EXTEND32 (VL4_8 (prod));
2207 HI = EXTEND32 (VH4_8 (prod));
2210 TRACE_ALU_RESULT2 (HI, LO);
2213 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2215 *mipsI,mipsII,mipsIII,mipsIV:
2216 // start-sanitize-vr4320
2218 // end-sanitize-vr4320
2220 do_mult (SD_, RS, RT, 0);
2224 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2225 "mult r<RD>, r<RS>, r<RT>"
2227 // start-sanitize-vr5400
2229 // end-sanitize-vr5400
2230 // start-sanitize-r5900
2232 // end-sanitize-r5900
2234 // start-sanitize-tx19
2236 // end-sanitize-tx19
2238 do_mult (SD_, RS, RT, RD);
2242 :function:::void:do_multu:int rs, int rt, int rd
2245 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2246 CHECKHILO ("Multiplication");
2247 prod = (((unsigned64)(unsigned32) GPR[rs])
2248 * ((unsigned64)(unsigned32) GPR[rt]));
2249 LO = EXTEND32 (VL4_8 (prod));
2250 HI = EXTEND32 (VH4_8 (prod));
2253 TRACE_ALU_RESULT2 (HI, LO);
2256 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2257 "multu r<RS>, r<RT>"
2258 *mipsI,mipsII,mipsIII,mipsIV:
2259 // start-sanitize-vr4320
2261 // end-sanitize-vr4320
2263 do_multu (SD_, RS, RT, 0);
2266 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2267 "multu r<RD>, r<RS>, r<RT>"
2269 // start-sanitize-vr5400
2271 // end-sanitize-vr5400
2272 // start-sanitize-r5900
2274 // end-sanitize-r5900
2276 // start-sanitize-tx19
2278 // end-sanitize-tx19
2280 do_multu (SD_, RS, RT, 0);
2284 :function:::void:do_nor:int rs, int rt, int rd
2286 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2287 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2288 TRACE_ALU_RESULT (GPR[rd]);
2291 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2292 "nor r<RD>, r<RS>, r<RT>"
2293 *mipsI,mipsII,mipsIII,mipsIV:
2295 // start-sanitize-vr4320
2297 // end-sanitize-vr4320
2298 // start-sanitize-vr5400
2300 // end-sanitize-vr5400
2301 // start-sanitize-r5900
2303 // end-sanitize-r5900
2305 // start-sanitize-tx19
2307 // end-sanitize-tx19
2309 do_nor (SD_, RS, RT, RD);
2313 :function:::void:do_or:int rs, int rt, int rd
2315 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2316 GPR[rd] = (GPR[rs] | GPR[rt]);
2317 TRACE_ALU_RESULT (GPR[rd]);
2320 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2321 "or r<RD>, r<RS>, r<RT>"
2322 *mipsI,mipsII,mipsIII,mipsIV:
2324 // start-sanitize-vr4320
2326 // end-sanitize-vr4320
2327 // start-sanitize-vr5400
2329 // end-sanitize-vr5400
2330 // start-sanitize-r5900
2332 // end-sanitize-r5900
2334 // start-sanitize-tx19
2336 // end-sanitize-tx19
2338 do_or (SD_, RS, RT, RD);
2343 :function:::void:do_ori:int rs, int rt, unsigned immediate
2345 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2346 GPR[rt] = (GPR[rs] | immediate);
2347 TRACE_ALU_RESULT (GPR[rt]);
2350 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2351 "ori r<RT>, r<RS>, <IMMEDIATE>"
2352 *mipsI,mipsII,mipsIII,mipsIV:
2354 // start-sanitize-vr4320
2356 // end-sanitize-vr4320
2357 // start-sanitize-vr5400
2359 // end-sanitize-vr5400
2360 // start-sanitize-r5900
2362 // end-sanitize-r5900
2364 // start-sanitize-tx19
2366 // end-sanitize-tx19
2368 do_ori (SD_, RS, RT, IMMEDIATE);
2372 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2375 // start-sanitize-vr4320
2377 // end-sanitize-vr4320
2378 // start-sanitize-vr5400
2380 // end-sanitize-vr5400
2381 // start-sanitize-r5900
2383 // end-sanitize-r5900
2385 unsigned32 instruction = instruction_0;
2386 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2387 int hint = ((instruction >> 16) & 0x0000001F);
2388 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2390 address_word vaddr = ((unsigned64)op1 + offset);
2394 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2395 Prefetch(uncached,paddr,vaddr,isDATA,hint);
2400 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2402 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2403 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2404 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2411 vaddr = base + offset;
2412 if ((vaddr & access) != 0)
2413 SignalExceptionAddressStore ();
2414 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2415 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2416 byte = ((vaddr & mask) ^ bigendiancpu);
2417 memval = (word << (8 * byte));
2418 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2422 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2423 "sb r<RT>, <OFFSET>(r<BASE>)"
2424 *mipsI,mipsII,mipsIII,mipsIV:
2426 // start-sanitize-vr4320
2428 // end-sanitize-vr4320
2429 // start-sanitize-vr5400
2431 // end-sanitize-vr5400
2432 // start-sanitize-r5900
2434 // end-sanitize-r5900
2436 // start-sanitize-tx19
2438 // end-sanitize-tx19
2440 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2444 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2445 "sc r<RT>, <OFFSET>(r<BASE>)"
2450 // start-sanitize-vr4320
2452 // end-sanitize-vr4320
2453 // start-sanitize-vr5400
2455 // end-sanitize-vr5400
2456 // start-sanitize-r5900
2458 // end-sanitize-r5900
2459 // start-sanitize-tx19
2461 // end-sanitize-tx19
2463 unsigned32 instruction = instruction_0;
2464 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2465 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2466 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2468 address_word vaddr = ((unsigned64)op1 + offset);
2471 if ((vaddr & 3) != 0)
2472 SignalExceptionAddressStore();
2475 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2477 unsigned64 memval = 0;
2478 unsigned64 memval1 = 0;
2479 unsigned64 mask = 0x7;
2481 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2482 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2483 memval = ((unsigned64) op2 << (8 * byte));
2486 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2488 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2495 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2496 "scd r<RT>, <OFFSET>(r<BASE>)"
2500 // start-sanitize-vr4320
2502 // end-sanitize-vr4320
2503 // start-sanitize-vr5400
2505 // end-sanitize-vr5400
2506 // start-sanitize-r5900
2508 // end-sanitize-r5900
2509 // start-sanitize-tx19
2511 // end-sanitize-tx19
2513 unsigned32 instruction = instruction_0;
2514 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2515 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2516 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2518 address_word vaddr = ((unsigned64)op1 + offset);
2521 if ((vaddr & 7) != 0)
2522 SignalExceptionAddressStore();
2525 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2527 unsigned64 memval = 0;
2528 unsigned64 memval1 = 0;
2532 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2534 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2541 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2542 "sd r<RT>, <OFFSET>(r<BASE>)"
2546 // start-sanitize-vr4320
2548 // end-sanitize-vr4320
2549 // start-sanitize-vr5400
2551 // end-sanitize-vr5400
2552 // start-sanitize-r5900
2554 // end-sanitize-r5900
2555 // start-sanitize-tx19
2557 // end-sanitize-tx19
2559 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2563 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2564 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2569 // start-sanitize-vr4320
2571 // end-sanitize-vr4320
2572 // start-sanitize-vr5400
2574 // end-sanitize-vr5400
2575 // start-sanitize-r5900
2577 // end-sanitize-r5900
2578 // start-sanitize-tx19
2580 // end-sanitize-tx19
2582 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2586 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2587 "sdl r<RT>, <OFFSET>(r<BASE>)"
2591 // start-sanitize-vr4320
2593 // end-sanitize-vr4320
2594 // start-sanitize-vr5400
2596 // end-sanitize-vr5400
2597 // start-sanitize-r5900
2599 // end-sanitize-r5900
2600 // start-sanitize-tx19
2602 // end-sanitize-tx19
2604 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2608 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2609 "sdr r<RT>, <OFFSET>(r<BASE>)"
2613 // start-sanitize-vr4320
2615 // end-sanitize-vr4320
2616 // start-sanitize-vr5400
2618 // end-sanitize-vr5400
2619 // start-sanitize-r5900
2621 // end-sanitize-r5900
2622 // start-sanitize-tx19
2624 // end-sanitize-tx19
2626 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2630 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2631 "sh r<RT>, <OFFSET>(r<BASE>)"
2632 *mipsI,mipsII,mipsIII,mipsIV:
2634 // start-sanitize-vr4320
2636 // end-sanitize-vr4320
2637 // start-sanitize-vr5400
2639 // end-sanitize-vr5400
2640 // start-sanitize-r5900
2642 // end-sanitize-r5900
2644 // start-sanitize-tx19
2646 // end-sanitize-tx19
2648 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2652 :function:::void:do_sll:int rt, int rd, int shift
2654 unsigned32 temp = (GPR[rt] << shift);
2655 TRACE_ALU_INPUT2 (GPR[rt], shift);
2656 GPR[rd] = EXTEND32 (temp);
2657 TRACE_ALU_RESULT (GPR[rd]);
2660 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2661 "sll r<RD>, r<RT>, <SHIFT>"
2662 *mipsI,mipsII,mipsIII,mipsIV:
2664 // start-sanitize-vr4320
2666 // end-sanitize-vr4320
2667 // start-sanitize-vr5400
2669 // end-sanitize-vr5400
2670 // start-sanitize-r5900
2672 // end-sanitize-r5900
2674 // start-sanitize-tx19
2676 // end-sanitize-tx19
2678 do_sll (SD_, RT, RD, SHIFT);
2682 :function:::void:do_sllv:int rs, int rt, int rd
2684 int s = MASKED (GPR[rs], 4, 0);
2685 unsigned32 temp = (GPR[rt] << s);
2686 TRACE_ALU_INPUT2 (GPR[rt], s);
2687 GPR[rd] = EXTEND32 (temp);
2688 TRACE_ALU_RESULT (GPR[rd]);
2691 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2692 "sllv r<RD>, r<RT>, r<RS>"
2693 *mipsI,mipsII,mipsIII,mipsIV:
2695 // start-sanitize-vr4320
2697 // end-sanitize-vr4320
2698 // start-sanitize-vr5400
2700 // end-sanitize-vr5400
2701 // start-sanitize-r5900
2703 // end-sanitize-r5900
2705 // start-sanitize-tx19
2707 // end-sanitize-tx19
2709 do_sllv (SD_, RS, RT, RD);
2713 :function:::void:do_slt:int rs, int rt, int rd
2715 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2716 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2717 TRACE_ALU_RESULT (GPR[rd]);
2720 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2721 "slt r<RD>, r<RS>, r<RT>"
2722 *mipsI,mipsII,mipsIII,mipsIV:
2724 // start-sanitize-vr4320
2726 // end-sanitize-vr4320
2727 // start-sanitize-vr5400
2729 // end-sanitize-vr5400
2730 // start-sanitize-r5900
2732 // end-sanitize-r5900
2734 // start-sanitize-tx19
2736 // end-sanitize-tx19
2738 do_slt (SD_, RS, RT, RD);
2742 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2744 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2745 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2746 TRACE_ALU_RESULT (GPR[rt]);
2749 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2750 "slti r<RT>, r<RS>, <IMMEDIATE>"
2751 *mipsI,mipsII,mipsIII,mipsIV:
2753 // start-sanitize-vr4320
2755 // end-sanitize-vr4320
2756 // start-sanitize-vr5400
2758 // end-sanitize-vr5400
2759 // start-sanitize-r5900
2761 // end-sanitize-r5900
2763 // start-sanitize-tx19
2765 // end-sanitize-tx19
2767 do_slti (SD_, RS, RT, IMMEDIATE);
2771 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2773 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2774 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2775 TRACE_ALU_RESULT (GPR[rt]);
2778 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2779 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2780 *mipsI,mipsII,mipsIII,mipsIV:
2782 // start-sanitize-vr4320
2784 // end-sanitize-vr4320
2785 // start-sanitize-vr5400
2787 // end-sanitize-vr5400
2788 // start-sanitize-r5900
2790 // end-sanitize-r5900
2792 // start-sanitize-tx19
2794 // end-sanitize-tx19
2796 do_sltiu (SD_, RS, RT, IMMEDIATE);
2801 :function:::void:do_sltu:int rs, int rt, int rd
2803 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2804 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2805 TRACE_ALU_RESULT (GPR[rd]);
2808 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2809 "sltu r<RD>, r<RS>, r<RT>"
2810 *mipsI,mipsII,mipsIII,mipsIV:
2812 // start-sanitize-vr4320
2814 // end-sanitize-vr4320
2815 // start-sanitize-vr5400
2817 // end-sanitize-vr5400
2818 // start-sanitize-r5900
2820 // end-sanitize-r5900
2822 // start-sanitize-tx19
2824 // end-sanitize-tx19
2826 do_sltu (SD_, RS, RT, RD);
2830 :function:::void:do_sra:int rt, int rd, int shift
2832 signed32 temp = (signed32) GPR[rt] >> shift;
2833 TRACE_ALU_INPUT2 (GPR[rt], shift);
2834 GPR[rd] = EXTEND32 (temp);
2835 TRACE_ALU_RESULT (GPR[rd]);
2838 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2839 "sra r<RD>, r<RT>, <SHIFT>"
2840 *mipsI,mipsII,mipsIII,mipsIV:
2842 // start-sanitize-vr4320
2844 // end-sanitize-vr4320
2845 // start-sanitize-vr5400
2847 // end-sanitize-vr5400
2848 // start-sanitize-r5900
2850 // end-sanitize-r5900
2852 // start-sanitize-tx19
2854 // end-sanitize-tx19
2856 do_sra (SD_, RT, RD, SHIFT);
2860 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2861 "srav r<RD>, r<RT>, r<RS>"
2862 *mipsI,mipsII,mipsIII,mipsIV:
2864 // start-sanitize-vr4320
2866 // end-sanitize-vr4320
2867 // start-sanitize-vr5400
2869 // end-sanitize-vr5400
2870 // start-sanitize-r5900
2872 // end-sanitize-r5900
2874 // start-sanitize-tx19
2876 // end-sanitize-tx19
2878 int s = MASKED (GPR[RS], 4, 0);
2879 signed32 temp = (signed32) GPR[RT] >> s;
2880 GPR[RD] = EXTEND32 (temp);
2884 :function:::void:do_srl:int rt, int rd, int shift
2886 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2887 TRACE_ALU_INPUT2 (GPR[rt], shift);
2888 GPR[rd] = EXTEND32 (temp);
2889 TRACE_ALU_RESULT (GPR[rd]);
2892 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2893 "srl r<RD>, r<RT>, <SHIFT>"
2894 *mipsI,mipsII,mipsIII,mipsIV:
2896 // start-sanitize-vr4320
2898 // end-sanitize-vr4320
2899 // start-sanitize-vr5400
2901 // end-sanitize-vr5400
2902 // start-sanitize-r5900
2904 // end-sanitize-r5900
2906 // start-sanitize-tx19
2908 // end-sanitize-tx19
2910 do_srl (SD_, RT, RD, SHIFT);
2914 :function:::void:do_srlv:int rs, int rt, int rd
2916 int s = MASKED (GPR[rs], 4, 0);
2917 unsigned32 temp = (unsigned32) GPR[rt] >> s;
2918 TRACE_ALU_INPUT2 (GPR[rt], s);
2919 GPR[rd] = EXTEND32 (temp);
2920 TRACE_ALU_RESULT (GPR[rd]);
2923 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2924 "srlv r<RD>, r<RT>, r<RS>"
2925 *mipsI,mipsII,mipsIII,mipsIV:
2927 // start-sanitize-vr4320
2929 // end-sanitize-vr4320
2930 // start-sanitize-vr5400
2932 // end-sanitize-vr5400
2933 // start-sanitize-r5900
2935 // end-sanitize-r5900
2937 // start-sanitize-tx19
2939 // end-sanitize-tx19
2941 do_srlv (SD_, RS, RT, RD);
2945 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2946 "sub r<RD>, r<RS>, r<RT>"
2947 *mipsI,mipsII,mipsIII,mipsIV:
2949 // start-sanitize-vr4320
2951 // end-sanitize-vr4320
2952 // start-sanitize-vr5400
2954 // end-sanitize-vr5400
2955 // start-sanitize-r5900
2957 // end-sanitize-r5900
2959 // start-sanitize-tx19
2961 // end-sanitize-tx19
2963 ALU32_BEGIN (GPR[RS]);
2964 ALU32_SUB (GPR[RT]);
2965 ALU32_END (GPR[RD]);
2969 :function:::void:do_subu:int rs, int rt, int rd
2971 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2972 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2973 TRACE_ALU_RESULT (GPR[rd]);
2976 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2977 "subu r<RD>, r<RS>, r<RT>"
2978 *mipsI,mipsII,mipsIII,mipsIV:
2980 // start-sanitize-vr4320
2982 // end-sanitize-vr4320
2983 // start-sanitize-vr5400
2985 // end-sanitize-vr5400
2986 // start-sanitize-r5900
2988 // end-sanitize-r5900
2990 // start-sanitize-tx19
2992 // end-sanitize-tx19
2994 do_subu (SD_, RS, RT, RD);
2998 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2999 "sw r<RT>, <OFFSET>(r<BASE>)"
3000 *mipsI,mipsII,mipsIII,mipsIV:
3001 // start-sanitize-tx19
3003 // end-sanitize-tx19
3005 // start-sanitize-vr4320
3007 // end-sanitize-vr4320
3009 // start-sanitize-vr5400
3011 // end-sanitize-vr5400
3012 // start-sanitize-r5900
3014 // end-sanitize-r5900
3016 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3020 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3021 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3022 *mipsI,mipsII,mipsIII,mipsIV:
3024 // start-sanitize-vr4320
3026 // end-sanitize-vr4320
3027 // start-sanitize-vr5400
3029 // end-sanitize-vr5400
3031 // start-sanitize-tx19
3033 // end-sanitize-tx19
3035 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3040 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3042 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3043 address_word reverseendian = (ReverseEndian ? -1 : 0);
3044 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3051 vaddr = base + offset;
3052 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3053 paddr = (paddr ^ (reverseendian & mask));
3054 if (BigEndianMem == 0)
3055 paddr = paddr & ~access;
3056 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3057 if ((byte & ~access) == 0)
3058 memval = (rt >> (8 * (access - byte)));
3060 memval = (rt << (8 * (mask - byte)));
3061 StoreMemory (uncached, byte & access, memval, NULL, paddr, vaddr, isREAL);
3065 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3066 "swl r<RT>, <OFFSET>(r<BASE>)"
3067 *mipsI,mipsII,mipsIII,mipsIV:
3069 // start-sanitize-vr4320
3071 // end-sanitize-vr4320
3072 // start-sanitize-vr5400
3074 // end-sanitize-vr5400
3075 // start-sanitize-r5900
3077 // end-sanitize-r5900
3079 // start-sanitize-tx19
3081 // end-sanitize-tx19
3083 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3087 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3089 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3090 address_word reverseendian = (ReverseEndian ? -1 : 0);
3091 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3098 vaddr = base + offset;
3099 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3100 paddr = (paddr ^ (reverseendian & mask));
3101 if (BigEndianMem != 0)
3103 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3104 memval = (rt << (byte * 8));
3105 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3108 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3109 "swr r<RT>, <OFFSET>(r<BASE>)"
3110 *mipsI,mipsII,mipsIII,mipsIV:
3112 // start-sanitize-vr4320
3114 // end-sanitize-vr4320
3115 // start-sanitize-vr5400
3117 // end-sanitize-vr5400
3118 // start-sanitize-r5900
3120 // end-sanitize-r5900
3122 // start-sanitize-tx19
3124 // end-sanitize-tx19
3126 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3130 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3137 // start-sanitize-vr4320
3139 // end-sanitize-vr4320
3140 // start-sanitize-vr5400
3142 // end-sanitize-vr5400
3143 // start-sanitize-r5900
3145 // end-sanitize-r5900
3147 // start-sanitize-tx19
3149 // end-sanitize-tx19
3151 SyncOperation (STYPE);
3155 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3157 *mipsI,mipsII,mipsIII,mipsIV:
3159 // start-sanitize-vr4320
3161 // end-sanitize-vr4320
3162 // start-sanitize-vr5400
3164 // end-sanitize-vr5400
3165 // start-sanitize-r5900
3167 // end-sanitize-r5900
3169 // start-sanitize-tx19
3171 // end-sanitize-tx19
3173 SignalException(SystemCall, instruction_0);
3177 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3183 // start-sanitize-vr4320
3185 // end-sanitize-vr4320
3186 // start-sanitize-vr5400
3188 // end-sanitize-vr5400
3189 // start-sanitize-r5900
3191 // end-sanitize-r5900
3192 // start-sanitize-tx19
3194 // end-sanitize-tx19
3196 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3197 SignalException(Trap, instruction_0);
3201 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3202 "teqi r<RS>, <IMMEDIATE>"
3207 // start-sanitize-vr4320
3209 // end-sanitize-vr4320
3210 // start-sanitize-vr5400
3212 // end-sanitize-vr5400
3213 // start-sanitize-r5900
3215 // end-sanitize-r5900
3216 // start-sanitize-tx19
3218 // end-sanitize-tx19
3220 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3221 SignalException(Trap, instruction_0);
3225 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3231 // start-sanitize-vr4320
3233 // end-sanitize-vr4320
3234 // start-sanitize-vr5400
3236 // end-sanitize-vr5400
3237 // start-sanitize-r5900
3239 // end-sanitize-r5900
3240 // start-sanitize-tx19
3242 // end-sanitize-tx19
3244 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3245 SignalException(Trap, instruction_0);
3249 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3250 "tgei r<RS>, <IMMEDIATE>"
3255 // start-sanitize-vr4320
3257 // end-sanitize-vr4320
3258 // start-sanitize-vr5400
3260 // end-sanitize-vr5400
3261 // start-sanitize-r5900
3263 // end-sanitize-r5900
3264 // start-sanitize-tx19
3266 // end-sanitize-tx19
3268 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3269 SignalException(Trap, instruction_0);
3273 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3274 "tgeiu r<RS>, <IMMEDIATE>"
3279 // start-sanitize-vr4320
3281 // end-sanitize-vr4320
3282 // start-sanitize-vr5400
3284 // end-sanitize-vr5400
3285 // start-sanitize-r5900
3287 // end-sanitize-r5900
3288 // start-sanitize-tx19
3290 // end-sanitize-tx19
3292 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3293 SignalException(Trap, instruction_0);
3297 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3303 // start-sanitize-vr4320
3305 // end-sanitize-vr4320
3306 // start-sanitize-vr5400
3308 // end-sanitize-vr5400
3309 // start-sanitize-r5900
3311 // end-sanitize-r5900
3312 // start-sanitize-tx19
3314 // end-sanitize-tx19
3316 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3317 SignalException(Trap, instruction_0);
3321 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3327 // start-sanitize-vr4320
3329 // end-sanitize-vr4320
3330 // start-sanitize-vr5400
3332 // end-sanitize-vr5400
3333 // start-sanitize-r5900
3335 // end-sanitize-r5900
3336 // start-sanitize-tx19
3338 // end-sanitize-tx19
3340 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3341 SignalException(Trap, instruction_0);
3345 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3346 "tlti r<RS>, <IMMEDIATE>"
3351 // start-sanitize-vr4320
3353 // end-sanitize-vr4320
3354 // start-sanitize-vr5400
3356 // end-sanitize-vr5400
3357 // start-sanitize-r5900
3359 // end-sanitize-r5900
3360 // start-sanitize-tx19
3362 // end-sanitize-tx19
3364 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3365 SignalException(Trap, instruction_0);
3369 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3370 "tltiu r<RS>, <IMMEDIATE>"
3375 // start-sanitize-vr4320
3377 // end-sanitize-vr4320
3378 // start-sanitize-vr5400
3380 // end-sanitize-vr5400
3381 // start-sanitize-r5900
3383 // end-sanitize-r5900
3384 // start-sanitize-tx19
3386 // end-sanitize-tx19
3388 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3389 SignalException(Trap, instruction_0);
3393 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3399 // start-sanitize-vr4320
3401 // end-sanitize-vr4320
3402 // start-sanitize-vr5400
3404 // end-sanitize-vr5400
3405 // start-sanitize-r5900
3407 // end-sanitize-r5900
3408 // start-sanitize-tx19
3410 // end-sanitize-tx19
3412 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3413 SignalException(Trap, instruction_0);
3417 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3423 // start-sanitize-vr4320
3425 // end-sanitize-vr4320
3426 // start-sanitize-vr5400
3428 // end-sanitize-vr5400
3429 // start-sanitize-r5900
3431 // end-sanitize-r5900
3432 // start-sanitize-tx19
3434 // end-sanitize-tx19
3436 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3437 SignalException(Trap, instruction_0);
3441 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3442 "tne r<RS>, <IMMEDIATE>"
3447 // start-sanitize-vr4320
3449 // end-sanitize-vr4320
3450 // start-sanitize-vr5400
3452 // end-sanitize-vr5400
3453 // start-sanitize-r5900
3455 // end-sanitize-r5900
3456 // start-sanitize-tx19
3458 // end-sanitize-tx19
3460 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3461 SignalException(Trap, instruction_0);
3465 :function:::void:do_xor:int rs, int rt, int rd
3467 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3468 GPR[rd] = GPR[rs] ^ GPR[rt];
3469 TRACE_ALU_RESULT (GPR[rd]);
3472 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3473 "xor r<RD>, r<RS>, r<RT>"
3474 *mipsI,mipsII,mipsIII,mipsIV:
3476 // start-sanitize-vr4320
3478 // end-sanitize-vr4320
3479 // start-sanitize-vr5400
3481 // end-sanitize-vr5400
3482 // start-sanitize-r5900
3484 // end-sanitize-r5900
3486 // start-sanitize-tx19
3488 // end-sanitize-tx19
3490 do_xor (SD_, RS, RT, RD);
3494 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3496 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3497 GPR[rt] = GPR[rs] ^ immediate;
3498 TRACE_ALU_RESULT (GPR[rt]);
3501 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3502 "xori r<RT>, r<RS>, <IMMEDIATE>"
3503 *mipsI,mipsII,mipsIII,mipsIV:
3505 // start-sanitize-vr4320
3507 // end-sanitize-vr4320
3508 // start-sanitize-vr5400
3510 // end-sanitize-vr5400
3511 // start-sanitize-r5900
3513 // end-sanitize-r5900
3515 // start-sanitize-tx19
3517 // end-sanitize-tx19
3519 do_xori (SD_, RS, RT, IMMEDIATE);
3524 // MIPS Architecture:
3526 // FPU Instruction Set (COP1 & COP1X)
3534 case fmt_single: return "s";
3535 case fmt_double: return "d";
3536 case fmt_word: return "w";
3537 case fmt_long: return "l";
3538 default: return "?";
3548 default: return "?";
3568 :%s::::COND:int cond
3572 case 00: return "f";
3573 case 01: return "un";
3574 case 02: return "eq";
3575 case 03: return "ueq";
3576 case 04: return "olt";
3577 case 05: return "ult";
3578 case 06: return "ole";
3579 case 07: return "ule";
3580 case 010: return "sf";
3581 case 011: return "ngle";
3582 case 012: return "seq";
3583 case 013: return "ngl";
3584 case 014: return "lt";
3585 case 015: return "nge";
3586 case 016: return "le";
3587 case 017: return "ngt";
3588 default: return "?";
3593 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3594 "abs.%s<FMT> f<FD>, f<FS>"
3595 *mipsI,mipsII,mipsIII,mipsIV:
3597 // start-sanitize-vr4320
3599 // end-sanitize-vr4320
3600 // start-sanitize-vr5400
3602 // end-sanitize-vr5400
3604 // start-sanitize-tx19
3606 // end-sanitize-tx19
3608 unsigned32 instruction = instruction_0;
3609 int destreg = ((instruction >> 6) & 0x0000001F);
3610 int fs = ((instruction >> 11) & 0x0000001F);
3611 int format = ((instruction >> 21) & 0x00000007);
3613 if ((format != fmt_single) && (format != fmt_double))
3614 SignalException(ReservedInstruction,instruction);
3616 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3622 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3623 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3624 *mipsI,mipsII,mipsIII,mipsIV:
3626 // start-sanitize-vr4320
3628 // end-sanitize-vr4320
3629 // start-sanitize-vr5400
3631 // end-sanitize-vr5400
3633 // start-sanitize-tx19
3635 // end-sanitize-tx19
3637 unsigned32 instruction = instruction_0;
3638 int destreg = ((instruction >> 6) & 0x0000001F);
3639 int fs = ((instruction >> 11) & 0x0000001F);
3640 int ft = ((instruction >> 16) & 0x0000001F);
3641 int format = ((instruction >> 21) & 0x00000007);
3643 if ((format != fmt_single) && (format != fmt_double))
3644 SignalException(ReservedInstruction, instruction);
3646 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3657 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3658 "bc1%s<TF>%s<ND> <OFFSET>"
3659 *mipsI,mipsII,mipsIII:
3660 // start-sanitize-r5900
3662 // end-sanitize-r5900
3664 TRACE_BRANCH_INPUT (PREVCOC1());
3665 if (PREVCOC1() == TF)
3667 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3668 TRACE_BRANCH_RESULT (dest);
3673 TRACE_BRANCH_RESULT (0);
3674 NULLIFY_NEXT_INSTRUCTION ();
3678 TRACE_BRANCH_RESULT (NIA);
3682 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3683 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3684 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3687 // start-sanitize-vr4320
3689 // end-sanitize-vr4320
3690 // start-sanitize-vr5400
3692 // end-sanitize-vr5400
3694 // start-sanitize-tx19
3696 // end-sanitize-tx19
3698 if (GETFCC(CC) == TF)
3700 DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3704 NULLIFY_NEXT_INSTRUCTION ();
3714 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3716 if ((fmt != fmt_single) && (fmt != fmt_double))
3717 SignalException (ReservedInstruction, insn);
3724 unsigned64 ofs = ValueFPR (fs, fmt);
3725 unsigned64 oft = ValueFPR (ft, fmt);
3726 if (NaN (ofs, fmt) || NaN (oft, fmt))
3728 if (FCSR & FP_ENABLE (IO))
3730 FCSR |= FP_CAUSE (IO);
3731 SignalExceptionFPE ();
3739 less = Less (ofs, oft, fmt);
3740 equal = Equal (ofs, oft, fmt);
3743 condition = (((cond & (1 << 2)) && less)
3744 || ((cond & (1 << 1)) && equal)
3745 || ((cond & (1 << 0)) && unordered));
3746 SETFCC (cc, condition);
3750 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
3751 *mipsI,mipsII,mipsIII:
3752 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
3754 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3757 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3758 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3759 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3762 // start-sanitize-vr4320
3764 // end-sanitize-vr4320
3765 // start-sanitize-vr5400
3767 // end-sanitize-vr5400
3769 // start-sanitize-tx19
3771 // end-sanitize-tx19
3773 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3777 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3778 "ceil.l.%s<FMT> f<FD>, f<FS>"
3782 // start-sanitize-vr4320
3784 // end-sanitize-vr4320
3785 // start-sanitize-vr5400
3787 // end-sanitize-vr5400
3788 // start-sanitize-r5900
3790 // end-sanitize-r5900
3792 // start-sanitize-tx19
3794 // end-sanitize-tx19
3796 unsigned32 instruction = instruction_0;
3797 int destreg = ((instruction >> 6) & 0x0000001F);
3798 int fs = ((instruction >> 11) & 0x0000001F);
3799 int format = ((instruction >> 21) & 0x00000007);
3801 if ((format != fmt_single) && (format != fmt_double))
3802 SignalException(ReservedInstruction,instruction);
3804 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3809 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3814 // start-sanitize-vr4320
3816 // end-sanitize-vr4320
3817 // start-sanitize-vr5400
3819 // end-sanitize-vr5400
3820 // start-sanitize-r5900
3822 // end-sanitize-r5900
3824 // start-sanitize-tx19
3826 // end-sanitize-tx19
3828 unsigned32 instruction = instruction_0;
3829 int destreg = ((instruction >> 6) & 0x0000001F);
3830 int fs = ((instruction >> 11) & 0x0000001F);
3831 int format = ((instruction >> 21) & 0x00000007);
3833 if ((format != fmt_single) && (format != fmt_double))
3834 SignalException(ReservedInstruction,instruction);
3836 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3843 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3844 "c%s<X>c1 r<RT>, f<FS>"
3852 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
3854 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
3856 PENDING_FILL(COCIDX,0); /* special case */
3859 { /* control from */
3861 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3863 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3867 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
3868 "c%s<X>c1 r<RT>, f<FS>"
3871 // start-sanitize-vr4320
3873 // end-sanitize-vr4320
3874 // start-sanitize-vr5400
3876 // end-sanitize-vr5400
3877 // start-sanitize-r5900
3879 // end-sanitize-r5900
3881 // start-sanitize-tx19
3883 // end-sanitize-tx19
3888 TRACE_ALU_INPUT1 (GPR[RT]);
3891 FCR0 = VL4_8(GPR[RT]);
3892 TRACE_ALU_RESULT (FCR0);
3896 FCR31 = VL4_8(GPR[RT]);
3897 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3898 TRACE_ALU_RESULT (FCR31);
3902 TRACE_ALU_RESULT0 ();
3907 { /* control from */
3910 TRACE_ALU_INPUT1 (FCR0);
3911 GPR[RT] = SIGNEXTEND (FCR0, 32);
3915 TRACE_ALU_INPUT1 (FCR31);
3916 GPR[RT] = SIGNEXTEND (FCR31, 32);
3918 TRACE_ALU_RESULT (GPR[RT]);
3925 // FIXME: Does not correctly differentiate between mips*
3927 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3928 "cvt.d.%s<FMT> f<FD>, f<FS>"
3929 *mipsI,mipsII,mipsIII,mipsIV:
3931 // start-sanitize-vr4320
3933 // end-sanitize-vr4320
3934 // start-sanitize-vr5400
3936 // end-sanitize-vr5400
3938 // start-sanitize-tx19
3940 // end-sanitize-tx19
3942 unsigned32 instruction = instruction_0;
3943 int destreg = ((instruction >> 6) & 0x0000001F);
3944 int fs = ((instruction >> 11) & 0x0000001F);
3945 int format = ((instruction >> 21) & 0x00000007);
3947 if ((format == fmt_double) | 0)
3948 SignalException(ReservedInstruction,instruction);
3950 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3955 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3956 "cvt.l.%s<FMT> f<FD>, f<FS>"
3960 // start-sanitize-vr4320
3962 // end-sanitize-vr4320
3963 // start-sanitize-vr5400
3965 // end-sanitize-vr5400
3967 // start-sanitize-tx19
3969 // end-sanitize-tx19
3971 unsigned32 instruction = instruction_0;
3972 int destreg = ((instruction >> 6) & 0x0000001F);
3973 int fs = ((instruction >> 11) & 0x0000001F);
3974 int format = ((instruction >> 21) & 0x00000007);
3976 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3977 SignalException(ReservedInstruction,instruction);
3979 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3985 // FIXME: Does not correctly differentiate between mips*
3987 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3988 "cvt.s.%s<FMT> f<FD>, f<FS>"
3989 *mipsI,mipsII,mipsIII,mipsIV:
3991 // start-sanitize-vr4320
3993 // end-sanitize-vr4320
3994 // start-sanitize-vr5400
3996 // end-sanitize-vr5400
3998 // start-sanitize-tx19
4000 // end-sanitize-tx19
4002 unsigned32 instruction = instruction_0;
4003 int destreg = ((instruction >> 6) & 0x0000001F);
4004 int fs = ((instruction >> 11) & 0x0000001F);
4005 int format = ((instruction >> 21) & 0x00000007);
4007 if ((format == fmt_single) | 0)
4008 SignalException(ReservedInstruction,instruction);
4010 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4015 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4016 "cvt.w.%s<FMT> f<FD>, f<FS>"
4017 *mipsI,mipsII,mipsIII,mipsIV:
4019 // start-sanitize-vr4320
4021 // end-sanitize-vr4320
4022 // start-sanitize-vr5400
4024 // end-sanitize-vr5400
4026 // start-sanitize-tx19
4028 // end-sanitize-tx19
4030 unsigned32 instruction = instruction_0;
4031 int destreg = ((instruction >> 6) & 0x0000001F);
4032 int fs = ((instruction >> 11) & 0x0000001F);
4033 int format = ((instruction >> 21) & 0x00000007);
4035 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4036 SignalException(ReservedInstruction,instruction);
4038 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4043 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4044 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4045 *mipsI,mipsII,mipsIII,mipsIV:
4047 // start-sanitize-vr4320
4049 // end-sanitize-vr4320
4050 // start-sanitize-vr5400
4052 // end-sanitize-vr5400
4054 // start-sanitize-tx19
4056 // end-sanitize-tx19
4058 unsigned32 instruction = instruction_0;
4059 int destreg = ((instruction >> 6) & 0x0000001F);
4060 int fs = ((instruction >> 11) & 0x0000001F);
4061 int ft = ((instruction >> 16) & 0x0000001F);
4062 int format = ((instruction >> 21) & 0x00000007);
4064 if ((format != fmt_single) && (format != fmt_double))
4065 SignalException(ReservedInstruction,instruction);
4067 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4074 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4075 "dm%s<X>c1 r<RT>, f<FS>"
4080 if (SizeFGR() == 64)
4081 PENDING_FILL((FS + FGRIDX),GPR[RT]);
4082 else if ((FS & 0x1) == 0)
4084 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4085 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4090 if (SizeFGR() == 64)
4091 PENDING_FILL(RT,FGR[FS]);
4092 else if ((FS & 0x1) == 0)
4093 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4095 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4098 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4099 "dm%s<X>c1 r<RT>, f<FS>"
4102 // start-sanitize-vr4320
4104 // end-sanitize-vr4320
4105 // start-sanitize-vr5400
4107 // end-sanitize-vr5400
4108 // start-sanitize-r5900
4110 // end-sanitize-r5900
4112 // start-sanitize-tx19
4114 // end-sanitize-tx19
4118 if (SizeFGR() == 64)
4119 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4120 else if ((FS & 0x1) == 0)
4121 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4125 if (SizeFGR() == 64)
4127 else if ((FS & 0x1) == 0)
4128 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4130 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4135 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4136 "floor.l.%s<FMT> f<FD>, f<FS>"
4140 // start-sanitize-vr4320
4142 // end-sanitize-vr4320
4143 // start-sanitize-vr5400
4145 // end-sanitize-vr5400
4146 // start-sanitize-r5900
4148 // end-sanitize-r5900
4150 // start-sanitize-tx19
4152 // end-sanitize-tx19
4154 unsigned32 instruction = instruction_0;
4155 int destreg = ((instruction >> 6) & 0x0000001F);
4156 int fs = ((instruction >> 11) & 0x0000001F);
4157 int format = ((instruction >> 21) & 0x00000007);
4159 if ((format != fmt_single) && (format != fmt_double))
4160 SignalException(ReservedInstruction,instruction);
4162 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4167 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4168 "floor.w.%s<FMT> f<FD>, f<FS>"
4173 // start-sanitize-vr4320
4175 // end-sanitize-vr4320
4176 // start-sanitize-vr5400
4178 // end-sanitize-vr5400
4179 // start-sanitize-r5900
4181 // end-sanitize-r5900
4183 // start-sanitize-tx19
4185 // end-sanitize-tx19
4187 unsigned32 instruction = instruction_0;
4188 int destreg = ((instruction >> 6) & 0x0000001F);
4189 int fs = ((instruction >> 11) & 0x0000001F);
4190 int format = ((instruction >> 21) & 0x00000007);
4192 if ((format != fmt_single) && (format != fmt_double))
4193 SignalException(ReservedInstruction,instruction);
4195 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4200 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4201 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4206 // start-sanitize-vr4320
4208 // end-sanitize-vr4320
4209 // start-sanitize-vr5400
4211 // end-sanitize-vr5400
4213 // start-sanitize-tx19
4215 // end-sanitize-tx19
4217 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4221 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4222 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4225 // start-sanitize-vr4320
4227 // end-sanitize-vr4320
4228 // start-sanitize-vr5400
4230 // end-sanitize-vr5400
4232 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4237 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4238 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4239 *mipsI,mipsII,mipsIII,mipsIV:
4241 // start-sanitize-vr4320
4243 // end-sanitize-vr4320
4244 // start-sanitize-vr5400
4246 // end-sanitize-vr5400
4247 // start-sanitize-r5900
4249 // end-sanitize-r5900
4251 // start-sanitize-tx19
4253 // end-sanitize-tx19
4255 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4259 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4260 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4263 // start-sanitize-vr4320
4265 // end-sanitize-vr4320
4266 // start-sanitize-vr5400
4268 // end-sanitize-vr5400
4270 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4276 // FIXME: Not correct for mips*
4278 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4279 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4282 // start-sanitize-vr4320
4284 // end-sanitize-vr4320
4285 // start-sanitize-vr5400
4287 // end-sanitize-vr5400
4289 unsigned32 instruction = instruction_0;
4290 int destreg = ((instruction >> 6) & 0x0000001F);
4291 int fs = ((instruction >> 11) & 0x0000001F);
4292 int ft = ((instruction >> 16) & 0x0000001F);
4293 int fr = ((instruction >> 21) & 0x0000001F);
4295 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4300 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4301 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4304 // start-sanitize-vr4320
4306 // end-sanitize-vr4320
4307 // start-sanitize-vr5400
4309 // end-sanitize-vr5400
4311 unsigned32 instruction = instruction_0;
4312 int destreg = ((instruction >> 6) & 0x0000001F);
4313 int fs = ((instruction >> 11) & 0x0000001F);
4314 int ft = ((instruction >> 16) & 0x0000001F);
4315 int fr = ((instruction >> 21) & 0x0000001F);
4317 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4324 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4325 "m%s<X>c1 r<RT>, f<FS>"
4332 if (SizeFGR() == 64)
4333 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4335 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4338 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4340 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4341 "m%s<X>c1 r<RT>, f<FS>"
4344 // start-sanitize-vr4320
4346 // end-sanitize-vr4320
4347 // start-sanitize-vr5400
4349 // end-sanitize-vr5400
4351 // start-sanitize-tx19
4353 // end-sanitize-tx19
4357 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4359 GPR[RT] = SIGNEXTEND(FGR[FS],32);
4363 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4364 "mov.%s<FMT> f<FD>, f<FS>"
4365 *mipsI,mipsII,mipsIII,mipsIV:
4367 // start-sanitize-vr4320
4369 // end-sanitize-vr4320
4370 // start-sanitize-vr5400
4372 // end-sanitize-vr5400
4374 // start-sanitize-tx19
4376 // end-sanitize-tx19
4378 unsigned32 instruction = instruction_0;
4379 int destreg = ((instruction >> 6) & 0x0000001F);
4380 int fs = ((instruction >> 11) & 0x0000001F);
4381 int format = ((instruction >> 21) & 0x00000007);
4383 StoreFPR(destreg,format,ValueFPR(fs,format));
4389 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4390 "mov%s<TF> r<RD>, r<RS>, <CC>"
4393 // start-sanitize-vr4320
4395 // end-sanitize-vr4320
4396 // start-sanitize-vr5400
4398 // end-sanitize-vr5400
4399 // start-sanitize-r5900
4401 // end-sanitize-r5900
4403 if (GETFCC(CC) == TF)
4409 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4410 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4413 // start-sanitize-vr4320
4415 // end-sanitize-vr4320
4416 // start-sanitize-vr5400
4418 // end-sanitize-vr5400
4419 // start-sanitize-r5900
4421 // end-sanitize-r5900
4423 unsigned32 instruction = instruction_0;
4424 int format = ((instruction >> 21) & 0x00000007);
4426 if (GETFCC(CC) == TF)
4427 StoreFPR (FD, format, ValueFPR (FS, format));
4429 StoreFPR (FD, format, ValueFPR (FD, format));
4434 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4437 // start-sanitize-vr4320
4439 // end-sanitize-vr4320
4440 // start-sanitize-vr5400
4442 // end-sanitize-vr5400
4443 // start-sanitize-r5900
4445 // end-sanitize-r5900
4447 unsigned32 instruction = instruction_0;
4448 int destreg = ((instruction >> 6) & 0x0000001F);
4449 int fs = ((instruction >> 11) & 0x0000001F);
4450 int format = ((instruction >> 21) & 0x00000007);
4452 StoreFPR(destreg,format,ValueFPR(fs,format));
4460 // MOVT.fmt see MOVtf.fmt
4464 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4465 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4468 // start-sanitize-vr4320
4470 // end-sanitize-vr4320
4471 // start-sanitize-vr5400
4473 // end-sanitize-vr5400
4474 // start-sanitize-r5900
4476 // end-sanitize-r5900
4478 unsigned32 instruction = instruction_0;
4479 int destreg = ((instruction >> 6) & 0x0000001F);
4480 int fs = ((instruction >> 11) & 0x0000001F);
4481 int format = ((instruction >> 21) & 0x00000007);
4483 StoreFPR(destreg,format,ValueFPR(fs,format));
4489 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4490 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4493 // start-sanitize-vr4320
4495 // end-sanitize-vr4320
4496 // start-sanitize-vr5400
4498 // end-sanitize-vr5400
4499 // start-sanitize-r5900
4501 // end-sanitize-r5900
4503 unsigned32 instruction = instruction_0;
4504 int destreg = ((instruction >> 6) & 0x0000001F);
4505 int fs = ((instruction >> 11) & 0x0000001F);
4506 int ft = ((instruction >> 16) & 0x0000001F);
4507 int fr = ((instruction >> 21) & 0x0000001F);
4509 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4515 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4516 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4519 // start-sanitize-vr4320
4521 // end-sanitize-vr4320
4522 // start-sanitize-vr5400
4524 // end-sanitize-vr5400
4525 // start-sanitize-r5900
4527 // end-sanitize-r5900
4529 unsigned32 instruction = instruction_0;
4530 int destreg = ((instruction >> 6) & 0x0000001F);
4531 int fs = ((instruction >> 11) & 0x0000001F);
4532 int ft = ((instruction >> 16) & 0x0000001F);
4533 int fr = ((instruction >> 21) & 0x0000001F);
4535 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4543 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4544 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4545 *mipsI,mipsII,mipsIII,mipsIV:
4547 // start-sanitize-vr4320
4549 // end-sanitize-vr4320
4550 // start-sanitize-vr5400
4552 // end-sanitize-vr5400
4554 // start-sanitize-tx19
4556 // end-sanitize-tx19
4558 unsigned32 instruction = instruction_0;
4559 int destreg = ((instruction >> 6) & 0x0000001F);
4560 int fs = ((instruction >> 11) & 0x0000001F);
4561 int ft = ((instruction >> 16) & 0x0000001F);
4562 int format = ((instruction >> 21) & 0x00000007);
4564 if ((format != fmt_single) && (format != fmt_double))
4565 SignalException(ReservedInstruction,instruction);
4567 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4572 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4573 "neg.%s<FMT> f<FD>, f<FS>"
4574 *mipsI,mipsII,mipsIII,mipsIV:
4576 // start-sanitize-vr4320
4578 // end-sanitize-vr4320
4579 // start-sanitize-vr5400
4581 // end-sanitize-vr5400
4583 // start-sanitize-tx19
4585 // end-sanitize-tx19
4587 unsigned32 instruction = instruction_0;
4588 int destreg = ((instruction >> 6) & 0x0000001F);
4589 int fs = ((instruction >> 11) & 0x0000001F);
4590 int format = ((instruction >> 21) & 0x00000007);
4592 if ((format != fmt_single) && (format != fmt_double))
4593 SignalException(ReservedInstruction,instruction);
4595 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4601 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4602 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4605 // start-sanitize-vr4320
4607 // end-sanitize-vr4320
4608 // start-sanitize-vr5400
4610 // end-sanitize-vr5400
4612 unsigned32 instruction = instruction_0;
4613 int destreg = ((instruction >> 6) & 0x0000001F);
4614 int fs = ((instruction >> 11) & 0x0000001F);
4615 int ft = ((instruction >> 16) & 0x0000001F);
4616 int fr = ((instruction >> 21) & 0x0000001F);
4618 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4624 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4625 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4628 // start-sanitize-vr4320
4630 // end-sanitize-vr4320
4631 // start-sanitize-vr5400
4633 // end-sanitize-vr5400
4635 unsigned32 instruction = instruction_0;
4636 int destreg = ((instruction >> 6) & 0x0000001F);
4637 int fs = ((instruction >> 11) & 0x0000001F);
4638 int ft = ((instruction >> 16) & 0x0000001F);
4639 int fr = ((instruction >> 21) & 0x0000001F);
4641 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4647 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4648 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4651 // start-sanitize-vr4320
4653 // end-sanitize-vr4320
4654 // start-sanitize-vr5400
4656 // end-sanitize-vr5400
4658 unsigned32 instruction = instruction_0;
4659 int destreg = ((instruction >> 6) & 0x0000001F);
4660 int fs = ((instruction >> 11) & 0x0000001F);
4661 int ft = ((instruction >> 16) & 0x0000001F);
4662 int fr = ((instruction >> 21) & 0x0000001F);
4664 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4670 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4671 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4674 // start-sanitize-vr4320
4676 // end-sanitize-vr4320
4677 // start-sanitize-vr5400
4679 // end-sanitize-vr5400
4681 unsigned32 instruction = instruction_0;
4682 int destreg = ((instruction >> 6) & 0x0000001F);
4683 int fs = ((instruction >> 11) & 0x0000001F);
4684 int ft = ((instruction >> 16) & 0x0000001F);
4685 int fr = ((instruction >> 21) & 0x0000001F);
4687 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4692 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4693 "prefx <HINT>, r<INDEX>(r<BASE>)"
4696 // start-sanitize-vr4320
4698 // end-sanitize-vr4320
4699 // start-sanitize-vr5400
4701 // end-sanitize-vr5400
4703 unsigned32 instruction = instruction_0;
4704 int fs = ((instruction >> 11) & 0x0000001F);
4705 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4706 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4708 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4711 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4712 Prefetch(uncached,paddr,vaddr,isDATA,fs);
4716 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4718 "recip.%s<FMT> f<FD>, f<FS>"
4720 // start-sanitize-vr4320
4722 // end-sanitize-vr4320
4723 // start-sanitize-vr5400
4725 // end-sanitize-vr5400
4727 unsigned32 instruction = instruction_0;
4728 int destreg = ((instruction >> 6) & 0x0000001F);
4729 int fs = ((instruction >> 11) & 0x0000001F);
4730 int format = ((instruction >> 21) & 0x00000007);
4732 if ((format != fmt_single) && (format != fmt_double))
4733 SignalException(ReservedInstruction,instruction);
4735 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4740 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4741 "round.l.%s<FMT> f<FD>, f<FS>"
4745 // start-sanitize-vr4320
4747 // end-sanitize-vr4320
4748 // start-sanitize-vr5400
4750 // end-sanitize-vr5400
4751 // start-sanitize-r5900
4753 // end-sanitize-r5900
4755 // start-sanitize-tx19
4757 // end-sanitize-tx19
4759 unsigned32 instruction = instruction_0;
4760 int destreg = ((instruction >> 6) & 0x0000001F);
4761 int fs = ((instruction >> 11) & 0x0000001F);
4762 int format = ((instruction >> 21) & 0x00000007);
4764 if ((format != fmt_single) && (format != fmt_double))
4765 SignalException(ReservedInstruction,instruction);
4767 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4772 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4773 "round.w.%s<FMT> f<FD>, f<FS>"
4778 // start-sanitize-vr4320
4780 // end-sanitize-vr4320
4781 // start-sanitize-vr5400
4783 // end-sanitize-vr5400
4784 // start-sanitize-r5900
4786 // end-sanitize-r5900
4788 // start-sanitize-tx19
4790 // end-sanitize-tx19
4792 unsigned32 instruction = instruction_0;
4793 int destreg = ((instruction >> 6) & 0x0000001F);
4794 int fs = ((instruction >> 11) & 0x0000001F);
4795 int format = ((instruction >> 21) & 0x00000007);
4797 if ((format != fmt_single) && (format != fmt_double))
4798 SignalException(ReservedInstruction,instruction);
4800 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4805 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4807 "rsqrt.%s<FMT> f<FD>, f<FS>"
4809 // start-sanitize-vr4320
4811 // end-sanitize-vr4320
4812 // start-sanitize-vr5400
4814 // end-sanitize-vr5400
4816 unsigned32 instruction = instruction_0;
4817 int destreg = ((instruction >> 6) & 0x0000001F);
4818 int fs = ((instruction >> 11) & 0x0000001F);
4819 int format = ((instruction >> 21) & 0x00000007);
4821 if ((format != fmt_single) && (format != fmt_double))
4822 SignalException(ReservedInstruction,instruction);
4824 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4829 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
4830 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4835 // start-sanitize-vr4320
4837 // end-sanitize-vr4320
4838 // start-sanitize-vr5400
4840 // end-sanitize-vr5400
4842 // start-sanitize-tx19
4844 // end-sanitize-tx19
4846 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4850 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
4851 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
4854 // start-sanitize-vr4320
4856 // end-sanitize-vr4320
4857 // start-sanitize-vr5400
4859 // end-sanitize-vr5400
4861 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4865 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4866 "sqrt.%s<FMT> f<FD>, f<FS>"
4871 // start-sanitize-vr4320
4873 // end-sanitize-vr4320
4874 // start-sanitize-vr5400
4876 // end-sanitize-vr5400
4878 // start-sanitize-tx19
4880 // end-sanitize-tx19
4882 unsigned32 instruction = instruction_0;
4883 int destreg = ((instruction >> 6) & 0x0000001F);
4884 int fs = ((instruction >> 11) & 0x0000001F);
4885 int format = ((instruction >> 21) & 0x00000007);
4887 if ((format != fmt_single) && (format != fmt_double))
4888 SignalException(ReservedInstruction,instruction);
4890 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4895 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4896 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4897 *mipsI,mipsII,mipsIII,mipsIV:
4899 // start-sanitize-vr4320
4901 // end-sanitize-vr4320
4902 // start-sanitize-vr5400
4904 // end-sanitize-vr5400
4906 // start-sanitize-tx19
4908 // end-sanitize-tx19
4910 unsigned32 instruction = instruction_0;
4911 int destreg = ((instruction >> 6) & 0x0000001F);
4912 int fs = ((instruction >> 11) & 0x0000001F);
4913 int ft = ((instruction >> 16) & 0x0000001F);
4914 int format = ((instruction >> 21) & 0x00000007);
4916 if ((format != fmt_single) && (format != fmt_double))
4917 SignalException(ReservedInstruction,instruction);
4919 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4925 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
4926 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4927 *mipsI,mipsII,mipsIII,mipsIV:
4929 // start-sanitize-vr4320
4931 // end-sanitize-vr4320
4932 // start-sanitize-vr5400
4934 // end-sanitize-vr5400
4935 // start-sanitize-r5900
4937 // end-sanitize-r5900
4939 // start-sanitize-tx19
4941 // end-sanitize-tx19
4943 unsigned32 instruction = instruction_0;
4944 signed_word offset = EXTEND16 (OFFSET);
4945 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4946 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4948 address_word vaddr = ((uword64)op1 + offset);
4951 if ((vaddr & 3) != 0)
4952 SignalExceptionAddressStore();
4955 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4958 uword64 memval1 = 0;
4961 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4962 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4963 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
4965 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4973 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4974 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4977 // start-sanitize-vr4320
4979 // end-sanitize-vr4320
4980 // start-sanitize-vr5400
4982 // end-sanitize-vr5400
4984 unsigned32 instruction = instruction_0;
4985 int fs = ((instruction >> 11) & 0x0000001F);
4986 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4987 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4989 address_word vaddr = ((unsigned64)op1 + op2);
4992 if ((vaddr & 3) != 0)
4993 SignalExceptionAddressStore();
4996 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4998 unsigned64 memval = 0;
4999 unsigned64 memval1 = 0;
5000 unsigned64 mask = 0x7;
5002 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5003 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5004 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5006 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5014 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5015 "trunc.l.%s<FMT> f<FD>, f<FS>"
5019 // start-sanitize-vr4320
5021 // end-sanitize-vr4320
5022 // start-sanitize-vr5400
5024 // end-sanitize-vr5400
5025 // start-sanitize-r5900
5027 // end-sanitize-r5900
5029 // start-sanitize-tx19
5031 // end-sanitize-tx19
5033 unsigned32 instruction = instruction_0;
5034 int destreg = ((instruction >> 6) & 0x0000001F);
5035 int fs = ((instruction >> 11) & 0x0000001F);
5036 int format = ((instruction >> 21) & 0x00000007);
5038 if ((format != fmt_single) && (format != fmt_double))
5039 SignalException(ReservedInstruction,instruction);
5041 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5046 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5047 "trunc.w.%s<FMT> f<FD>, f<FS>"
5052 // start-sanitize-vr4320
5054 // end-sanitize-vr4320
5055 // start-sanitize-vr5400
5057 // end-sanitize-vr5400
5058 // start-sanitize-r5900
5060 // end-sanitize-r5900
5062 // start-sanitize-tx19
5064 // end-sanitize-tx19
5066 unsigned32 instruction = instruction_0;
5067 int destreg = ((instruction >> 6) & 0x0000001F);
5068 int fs = ((instruction >> 11) & 0x0000001F);
5069 int format = ((instruction >> 21) & 0x00000007);
5071 if ((format != fmt_single) && (format != fmt_double))
5072 SignalException(ReservedInstruction,instruction);
5074 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5080 // MIPS Architecture:
5082 // System Control Instruction Set (COP0)
5086 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5088 *mipsI,mipsII,mipsIII,mipsIV:
5090 // start-sanitize-vr4320
5092 // end-sanitize-vr4320
5093 // start-sanitize-vr5400
5095 // end-sanitize-vr5400
5096 // start-sanitize-r5900
5098 // end-sanitize-r5900
5101 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5103 *mipsI,mipsII,mipsIII,mipsIV:
5105 // start-sanitize-vr4320
5107 // end-sanitize-vr4320
5108 // start-sanitize-vr5400
5110 // end-sanitize-vr5400
5111 // start-sanitize-r5900
5113 // end-sanitize-r5900
5116 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5118 *mipsI,mipsII,mipsIII,mipsIV:
5119 // start-sanitize-r5900
5121 // end-sanitize-r5900
5125 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5127 *mipsI,mipsII,mipsIII,mipsIV:
5129 // start-sanitize-vr4320
5131 // end-sanitize-vr4320
5132 // start-sanitize-vr5400
5134 // end-sanitize-vr5400
5135 // start-sanitize-r5900
5137 // end-sanitize-r5900
5140 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5144 // start-sanitize-vr4320
5146 // end-sanitize-vr4320
5147 // start-sanitize-vr5400
5149 // end-sanitize-vr5400
5150 // start-sanitize-r5900
5152 // end-sanitize-r5900
5154 // start-sanitize-tx19
5156 // end-sanitize-tx19
5158 unsigned32 instruction = instruction_0;
5159 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5160 int hint = ((instruction >> 16) & 0x0000001F);
5161 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5163 address_word vaddr = (op1 + offset);
5166 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5167 CacheOp(hint,vaddr,paddr,instruction);
5172 010000,10000,000000000000000,111001:COP0:32::DI
5174 *mipsI,mipsII,mipsIII,mipsIV:
5176 // start-sanitize-vr4320
5178 // end-sanitize-vr4320
5179 // start-sanitize-vr5400
5181 // end-sanitize-vr5400
5182 // start-sanitize-r5900
5184 // end-sanitize-r5900
5187 010000,10000,000000000000000,111000:COP0:32::EI
5189 *mipsI,mipsII,mipsIII,mipsIV:
5191 // start-sanitize-vr4320
5193 // end-sanitize-vr4320
5194 // start-sanitize-vr5400
5196 // end-sanitize-vr5400
5197 // start-sanitize-r5900
5199 // end-sanitize-r5900
5202 010000,10000,000000000000000,011000:COP0:32::ERET
5207 // start-sanitize-vr4320
5209 // end-sanitize-vr4320
5210 // start-sanitize-vr5400
5212 // end-sanitize-vr5400
5213 // start-sanitize-r5900
5215 // end-sanitize-r5900
5218 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5219 "mfc0 r<RT>, r<RD> # <REGX>"
5220 *mipsI,mipsII,mipsIII,mipsIV:
5222 // start-sanitize-vr4320
5224 // end-sanitize-vr4320
5225 // start-sanitize-vr5400
5227 // end-sanitize-vr5400
5228 // start-sanitize-r5900
5230 // end-sanitize-r5900
5232 DecodeCoproc (instruction_0);
5235 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5236 "mtc0 r<RT>, r<RD> # <REGX>"
5237 *mipsI,mipsII,mipsIII,mipsIV:
5238 // start-sanitize-tx19
5240 // end-sanitize-tx19
5242 // start-sanitize-vr4320
5244 // end-sanitize-vr4320
5246 // start-sanitize-vr5400
5248 // end-sanitize-vr5400
5249 // start-sanitize-r5900
5251 // end-sanitize-r5900
5253 DecodeCoproc (instruction_0);
5257 010000,10000,000000000000000,001000:COP0:32::TLBP
5259 *mipsI,mipsII,mipsIII,mipsIV:
5261 // start-sanitize-vr4320
5263 // end-sanitize-vr4320
5264 // start-sanitize-vr5400
5266 // end-sanitize-vr5400
5267 // start-sanitize-r5900
5269 // end-sanitize-r5900
5272 010000,10000,000000000000000,000001:COP0:32::TLBR
5274 *mipsI,mipsII,mipsIII,mipsIV:
5276 // start-sanitize-vr4320
5278 // end-sanitize-vr4320
5279 // start-sanitize-vr5400
5281 // end-sanitize-vr5400
5282 // start-sanitize-r5900
5284 // end-sanitize-r5900
5287 010000,10000,000000000000000,000010:COP0:32::TLBWI
5289 *mipsI,mipsII,mipsIII,mipsIV:
5291 // start-sanitize-vr4320
5293 // end-sanitize-vr4320
5294 // start-sanitize-vr5400
5296 // end-sanitize-vr5400
5297 // start-sanitize-r5900
5299 // end-sanitize-r5900
5302 010000,10000,000000000000000,000110:COP0:32::TLBWR
5304 *mipsI,mipsII,mipsIII,mipsIV:
5306 // start-sanitize-vr4320
5308 // end-sanitize-vr4320
5309 // start-sanitize-vr5400
5311 // end-sanitize-vr5400
5312 // start-sanitize-r5900
5314 // end-sanitize-r5900
5318 // start-sanitize-vr4320
5319 :include::vr4320:vr4320.igen
5320 // end-sanitize-vr4320
5321 // start-sanitize-vr5400
5322 :include::vr5400:vr5400.igen
5323 :include:64,f::mdmx.igen
5324 // end-sanitize-vr5400
5325 // start-sanitize-r5900
5326 :include::r5900:r5900.igen
5327 // end-sanitize-r5900
5330 // start-sanitize-cygnus-never
5332 // // FIXME FIXME FIXME What is this instruction?
5333 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5338 // // start-sanitize-r5900
5340 // // end-sanitize-r5900
5342 // // start-sanitize-tx19
5344 // // end-sanitize-tx19
5346 // unsigned32 instruction = instruction_0;
5347 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5348 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5349 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5351 // if (CoProcPresent(3))
5352 // SignalException(CoProcessorUnusable);
5354 // SignalException(ReservedInstruction,instruction);
5358 // end-sanitize-cygnus-never
5359 // start-sanitize-cygnus-never
5361 // // FIXME FIXME FIXME What is this?
5362 // 11100,******,00001:RR:16::SDBBP
5365 // unsigned32 instruction = instruction_0;
5366 // if (have_extendval)
5367 // SignalException (ReservedInstruction, instruction);
5369 // SignalException(DebugBreakPoint,instruction);
5373 // end-sanitize-cygnus-never
5374 // start-sanitize-cygnus-never
5376 // // FIXME FIXME FIXME What is this?
5377 // 000000,********************,001110:SPECIAL:32::SDBBP
5380 // unsigned32 instruction = instruction_0;
5382 // SignalException(DebugBreakPoint,instruction);
5386 // end-sanitize-cygnus-never
5387 // start-sanitize-cygnus-never
5389 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5390 // // isn't yet reconized by this simulator.
5391 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5394 // unsigned32 instruction = instruction_0;
5395 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5396 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5398 // CHECKHILO("Multiply-Add");
5400 // unsigned64 temp = (op1 * op2);
5401 // temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5402 // LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5403 // HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5408 // end-sanitize-cygnus-never
5409 // start-sanitize-cygnus-never
5411 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5412 // // isn't yet reconized by this simulator.
5413 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5416 // unsigned32 instruction = instruction_0;
5417 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5418 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5420 // CHECKHILO("Multiply-Add");
5422 // unsigned64 temp = (op1 * op2);
5428 // end-sanitize-cygnus-never