4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator are defined below.
35 // When placing models in the instruction descriptions, please place
36 // them one per line, in the order given here.
40 // Instructions and related functions for these models are included in
42 :model:::mipsI:mips3000:
43 :model:::mipsII:mips6000:
44 :model:::mipsIII:mips4000:
45 :model:::mipsIV:mips8000:
46 :model:::mipsV:mipsisaV:
50 // Standard MIPS ISA instructions used for these models are listed here,
51 // as are functions needed by those standard instructions. Instructions
52 // which are model-dependent and which are not in the standard MIPS ISAs
53 // (or which pre-date or use different encodings than the standard
54 // instructions) are (for the most part) in separate .igen files.
55 :model:::vr4100:mips4100: // vr.igen
56 :model:::vr5000:mips5000:
57 :model:::r3900:mips3900: // tx.igen
59 // MIPS Application Specific Extensions (ASEs)
61 // Instructions for the ASEs are in separate .igen files.
62 :model:::mips16:mips16: // m16.igen (and m16.dc)
65 // Pseudo instructions known by IGEN
68 SignalException (ReservedInstruction, 0);
72 // Pseudo instructions known by interp.c
73 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
74 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
77 SignalException (ReservedInstruction, instruction_0);
84 // Simulate a 32 bit delayslot instruction
87 :function:::address_word:delayslot32:address_word target
89 instruction_word delay_insn;
90 sim_events_slip (SD, 1);
92 CIA = CIA + 4; /* NOTE not mips16 */
93 STATE |= simDELAYSLOT;
94 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
95 ENGINE_ISSUE_PREFIX_HOOK();
96 idecode_issue (CPU_, delay_insn, (CIA));
97 STATE &= ~simDELAYSLOT;
101 :function:::address_word:nullify_next_insn32:
103 sim_events_slip (SD, 1);
104 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
111 // Calculate an effective address given a base and an offset.
114 :function:::address_word:loadstore_ea:address_word base, address_word offset
124 return base + offset;
130 // Check that an access to a HI/LO register meets timing requirements
132 // The following requirements exist:
134 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
135 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
136 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
137 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
140 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
142 if (history->mf.timestamp + 3 > time)
144 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
145 itable[MY_INDEX].name,
147 (long) history->mf.cia);
153 :function:::int:check_mt_hilo:hilo_history *history
162 signed64 time = sim_events_time (SD);
163 int ok = check_mf_cycles (SD_, history, time, "MT");
164 history->mt.timestamp = time;
165 history->mt.cia = CIA;
169 :function:::int:check_mt_hilo:hilo_history *history
172 signed64 time = sim_events_time (SD);
173 history->mt.timestamp = time;
174 history->mt.cia = CIA;
179 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
189 signed64 time = sim_events_time (SD);
192 && peer->mt.timestamp > history->op.timestamp
193 && history->mt.timestamp < history->op.timestamp
194 && ! (history->mf.timestamp > history->op.timestamp
195 && history->mf.timestamp < peer->mt.timestamp)
196 && ! (peer->mf.timestamp > history->op.timestamp
197 && peer->mf.timestamp < peer->mt.timestamp))
199 /* The peer has been written to since the last OP yet we have
201 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
202 itable[MY_INDEX].name,
204 (long) history->op.cia,
205 (long) peer->mt.cia);
208 history->mf.timestamp = time;
209 history->mf.cia = CIA;
215 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
224 signed64 time = sim_events_time (SD);
225 int ok = (check_mf_cycles (SD_, hi, time, "OP")
226 && check_mf_cycles (SD_, lo, time, "OP"));
227 hi->op.timestamp = time;
228 lo->op.timestamp = time;
234 // The r3900 mult and multu insns _can_ be exectuted immediatly after
236 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
239 /* FIXME: could record the fact that a stall occured if we want */
240 signed64 time = sim_events_time (SD);
241 hi->op.timestamp = time;
242 lo->op.timestamp = time;
249 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
259 signed64 time = sim_events_time (SD);
260 int ok = (check_mf_cycles (SD_, hi, time, "OP")
261 && check_mf_cycles (SD_, lo, time, "OP"));
262 hi->op.timestamp = time;
263 lo->op.timestamp = time;
272 // Check that the 64-bit instruction can currently be used, and signal
273 // a ReservedInstruction exception if not.
276 :function:::void:check_u64:instruction_word insn
283 // On mips64, if UserMode check SR:PX & SR:UX bits.
284 // The check should be similar to mips64 for any with PX/UX bit equivalents.
290 // MIPS Architecture:
292 // CPU Instruction Set (mipsI - mipsV)
297 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
298 "add r<RD>, r<RS>, r<RT>"
308 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
310 ALU32_BEGIN (GPR[RS]);
312 ALU32_END (GPR[RD]); /* This checks for overflow. */
314 TRACE_ALU_RESULT (GPR[RD]);
319 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
320 "addi r<RT>, r<RS>, <IMMEDIATE>"
330 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
332 ALU32_BEGIN (GPR[RS]);
333 ALU32_ADD (EXTEND16 (IMMEDIATE));
334 ALU32_END (GPR[RT]); /* This checks for overflow. */
336 TRACE_ALU_RESULT (GPR[RT]);
341 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
343 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
344 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
345 TRACE_ALU_RESULT (GPR[rt]);
348 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
349 "addiu r<RT>, r<RS>, <IMMEDIATE>"
359 do_addiu (SD_, RS, RT, IMMEDIATE);
364 :function:::void:do_addu:int rs, int rt, int rd
366 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
367 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
368 TRACE_ALU_RESULT (GPR[rd]);
371 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
372 "addu r<RD>, r<RS>, r<RT>"
382 do_addu (SD_, RS, RT, RD);
387 :function:::void:do_and:int rs, int rt, int rd
389 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
390 GPR[rd] = GPR[rs] & GPR[rt];
391 TRACE_ALU_RESULT (GPR[rd]);
394 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
395 "and r<RD>, r<RS>, r<RT>"
405 do_and (SD_, RS, RT, RD);
410 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
411 "and r<RT>, r<RS>, <IMMEDIATE>"
421 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
422 GPR[RT] = GPR[RS] & IMMEDIATE;
423 TRACE_ALU_RESULT (GPR[RT]);
428 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
429 "beq r<RS>, r<RT>, <OFFSET>"
439 address_word offset = EXTEND16 (OFFSET) << 2;
441 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
443 mark_branch_bug (NIA+offset);
444 DELAY_SLOT (NIA + offset);
450 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
451 "beql r<RS>, r<RT>, <OFFSET>"
460 address_word offset = EXTEND16 (OFFSET) << 2;
462 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
464 mark_branch_bug (NIA+offset);
465 DELAY_SLOT (NIA + offset);
468 NULLIFY_NEXT_INSTRUCTION ();
473 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
474 "bgez r<RS>, <OFFSET>"
484 address_word offset = EXTEND16 (OFFSET) << 2;
486 if ((signed_word) GPR[RS] >= 0)
488 mark_branch_bug (NIA+offset);
489 DELAY_SLOT (NIA + offset);
495 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
496 "bgezal r<RS>, <OFFSET>"
506 address_word offset = EXTEND16 (OFFSET) << 2;
509 if ((signed_word) GPR[RS] >= 0)
511 mark_branch_bug (NIA+offset);
512 DELAY_SLOT (NIA + offset);
518 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
519 "bgezall r<RS>, <OFFSET>"
528 address_word offset = EXTEND16 (OFFSET) << 2;
531 /* NOTE: The branch occurs AFTER the next instruction has been
533 if ((signed_word) GPR[RS] >= 0)
535 mark_branch_bug (NIA+offset);
536 DELAY_SLOT (NIA + offset);
539 NULLIFY_NEXT_INSTRUCTION ();
544 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
545 "bgezl r<RS>, <OFFSET>"
554 address_word offset = EXTEND16 (OFFSET) << 2;
556 if ((signed_word) GPR[RS] >= 0)
558 mark_branch_bug (NIA+offset);
559 DELAY_SLOT (NIA + offset);
562 NULLIFY_NEXT_INSTRUCTION ();
567 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
568 "bgtz r<RS>, <OFFSET>"
578 address_word offset = EXTEND16 (OFFSET) << 2;
580 if ((signed_word) GPR[RS] > 0)
582 mark_branch_bug (NIA+offset);
583 DELAY_SLOT (NIA + offset);
589 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
590 "bgtzl r<RS>, <OFFSET>"
599 address_word offset = EXTEND16 (OFFSET) << 2;
601 /* NOTE: The branch occurs AFTER the next instruction has been
603 if ((signed_word) GPR[RS] > 0)
605 mark_branch_bug (NIA+offset);
606 DELAY_SLOT (NIA + offset);
609 NULLIFY_NEXT_INSTRUCTION ();
614 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
615 "blez r<RS>, <OFFSET>"
625 address_word offset = EXTEND16 (OFFSET) << 2;
627 /* NOTE: The branch occurs AFTER the next instruction has been
629 if ((signed_word) GPR[RS] <= 0)
631 mark_branch_bug (NIA+offset);
632 DELAY_SLOT (NIA + offset);
638 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
639 "bgezl r<RS>, <OFFSET>"
648 address_word offset = EXTEND16 (OFFSET) << 2;
650 if ((signed_word) GPR[RS] <= 0)
652 mark_branch_bug (NIA+offset);
653 DELAY_SLOT (NIA + offset);
656 NULLIFY_NEXT_INSTRUCTION ();
661 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
662 "bltz r<RS>, <OFFSET>"
672 address_word offset = EXTEND16 (OFFSET) << 2;
674 if ((signed_word) GPR[RS] < 0)
676 mark_branch_bug (NIA+offset);
677 DELAY_SLOT (NIA + offset);
683 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
684 "bltzal r<RS>, <OFFSET>"
694 address_word offset = EXTEND16 (OFFSET) << 2;
697 /* NOTE: The branch occurs AFTER the next instruction has been
699 if ((signed_word) GPR[RS] < 0)
701 mark_branch_bug (NIA+offset);
702 DELAY_SLOT (NIA + offset);
708 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
709 "bltzall r<RS>, <OFFSET>"
718 address_word offset = EXTEND16 (OFFSET) << 2;
721 if ((signed_word) GPR[RS] < 0)
723 mark_branch_bug (NIA+offset);
724 DELAY_SLOT (NIA + offset);
727 NULLIFY_NEXT_INSTRUCTION ();
732 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
733 "bltzl r<RS>, <OFFSET>"
742 address_word offset = EXTEND16 (OFFSET) << 2;
744 /* NOTE: The branch occurs AFTER the next instruction has been
746 if ((signed_word) GPR[RS] < 0)
748 mark_branch_bug (NIA+offset);
749 DELAY_SLOT (NIA + offset);
752 NULLIFY_NEXT_INSTRUCTION ();
757 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
758 "bne r<RS>, r<RT>, <OFFSET>"
768 address_word offset = EXTEND16 (OFFSET) << 2;
770 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
772 mark_branch_bug (NIA+offset);
773 DELAY_SLOT (NIA + offset);
779 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
780 "bnel r<RS>, r<RT>, <OFFSET>"
789 address_word offset = EXTEND16 (OFFSET) << 2;
791 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
793 mark_branch_bug (NIA+offset);
794 DELAY_SLOT (NIA + offset);
797 NULLIFY_NEXT_INSTRUCTION ();
802 000000,20.CODE,001101:SPECIAL:32::BREAK
813 /* Check for some break instruction which are reserved for use by the simulator. */
814 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
815 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
816 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
818 sim_engine_halt (SD, CPU, NULL, cia,
819 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
821 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
822 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
824 if (STATE & simDELAYSLOT)
825 PC = cia - 4; /* reference the branch instruction */
828 SignalException (BreakPoint, instruction_0);
833 /* If we get this far, we're not an instruction reserved by the sim. Raise
835 SignalException (BreakPoint, instruction_0);
841 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
842 "dadd r<RD>, r<RS>, r<RT>"
849 check_u64 (SD_, instruction_0);
850 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
852 ALU64_BEGIN (GPR[RS]);
854 ALU64_END (GPR[RD]); /* This checks for overflow. */
856 TRACE_ALU_RESULT (GPR[RD]);
861 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
862 "daddi r<RT>, r<RS>, <IMMEDIATE>"
869 check_u64 (SD_, instruction_0);
870 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
872 ALU64_BEGIN (GPR[RS]);
873 ALU64_ADD (EXTEND16 (IMMEDIATE));
874 ALU64_END (GPR[RT]); /* This checks for overflow. */
876 TRACE_ALU_RESULT (GPR[RT]);
881 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
883 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
884 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
885 TRACE_ALU_RESULT (GPR[rt]);
888 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
889 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
896 check_u64 (SD_, instruction_0);
897 do_daddiu (SD_, RS, RT, IMMEDIATE);
902 :function:::void:do_daddu:int rs, int rt, int rd
904 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
905 GPR[rd] = GPR[rs] + GPR[rt];
906 TRACE_ALU_RESULT (GPR[rd]);
909 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
910 "daddu r<RD>, r<RS>, r<RT>"
917 check_u64 (SD_, instruction_0);
918 do_daddu (SD_, RS, RT, RD);
923 :function:::void:do_ddiv:int rs, int rt
925 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
926 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
928 signed64 n = GPR[rs];
929 signed64 d = GPR[rt];
934 lo = SIGNED64 (0x8000000000000000);
937 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
939 lo = SIGNED64 (0x8000000000000000);
950 TRACE_ALU_RESULT2 (HI, LO);
953 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
961 check_u64 (SD_, instruction_0);
962 do_ddiv (SD_, RS, RT);
967 :function:::void:do_ddivu:int rs, int rt
969 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
970 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
972 unsigned64 n = GPR[rs];
973 unsigned64 d = GPR[rt];
978 lo = SIGNED64 (0x8000000000000000);
989 TRACE_ALU_RESULT2 (HI, LO);
992 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1000 check_u64 (SD_, instruction_0);
1001 do_ddivu (SD_, RS, RT);
1006 :function:::void:do_div:int rs, int rt
1008 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1009 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1011 signed32 n = GPR[rs];
1012 signed32 d = GPR[rt];
1015 LO = EXTEND32 (0x80000000);
1018 else if (n == SIGNED32 (0x80000000) && d == -1)
1020 LO = EXTEND32 (0x80000000);
1025 LO = EXTEND32 (n / d);
1026 HI = EXTEND32 (n % d);
1029 TRACE_ALU_RESULT2 (HI, LO);
1032 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1043 do_div (SD_, RS, RT);
1048 :function:::void:do_divu:int rs, int rt
1050 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1051 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1053 unsigned32 n = GPR[rs];
1054 unsigned32 d = GPR[rt];
1057 LO = EXTEND32 (0x80000000);
1062 LO = EXTEND32 (n / d);
1063 HI = EXTEND32 (n % d);
1066 TRACE_ALU_RESULT2 (HI, LO);
1069 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1080 do_divu (SD_, RS, RT);
1085 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1095 unsigned64 op1 = GPR[rs];
1096 unsigned64 op2 = GPR[rt];
1097 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1098 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1099 /* make signed multiply unsigned */
1114 /* multiply out the 4 sub products */
1115 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1116 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1117 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1118 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1119 /* add the products */
1120 mid = ((unsigned64) VH4_8 (m00)
1121 + (unsigned64) VL4_8 (m10)
1122 + (unsigned64) VL4_8 (m01));
1123 lo = U8_4 (mid, m00);
1125 + (unsigned64) VH4_8 (mid)
1126 + (unsigned64) VH4_8 (m01)
1127 + (unsigned64) VH4_8 (m10));
1137 /* save the result HI/LO (and a gpr) */
1142 TRACE_ALU_RESULT2 (HI, LO);
1145 :function:::void:do_dmult:int rs, int rt, int rd
1147 do_dmultx (SD_, rs, rt, rd, 1);
1150 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1151 "dmult r<RS>, r<RT>"
1157 check_u64 (SD_, instruction_0);
1158 do_dmult (SD_, RS, RT, 0);
1161 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1162 "dmult r<RS>, r<RT>":RD == 0
1163 "dmult r<RD>, r<RS>, r<RT>"
1166 check_u64 (SD_, instruction_0);
1167 do_dmult (SD_, RS, RT, RD);
1172 :function:::void:do_dmultu:int rs, int rt, int rd
1174 do_dmultx (SD_, rs, rt, rd, 0);
1177 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1178 "dmultu r<RS>, r<RT>"
1184 check_u64 (SD_, instruction_0);
1185 do_dmultu (SD_, RS, RT, 0);
1188 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1189 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1190 "dmultu r<RS>, r<RT>"
1193 check_u64 (SD_, instruction_0);
1194 do_dmultu (SD_, RS, RT, RD);
1197 :function:::void:do_dsll:int rt, int rd, int shift
1199 TRACE_ALU_INPUT2 (GPR[rt], shift);
1200 GPR[rd] = GPR[rt] << shift;
1201 TRACE_ALU_RESULT (GPR[rd]);
1204 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1205 "dsll r<RD>, r<RT>, <SHIFT>"
1212 check_u64 (SD_, instruction_0);
1213 do_dsll (SD_, RT, RD, SHIFT);
1217 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1218 "dsll32 r<RD>, r<RT>, <SHIFT>"
1226 check_u64 (SD_, instruction_0);
1227 TRACE_ALU_INPUT2 (GPR[RT], s);
1228 GPR[RD] = GPR[RT] << s;
1229 TRACE_ALU_RESULT (GPR[RD]);
1232 :function:::void:do_dsllv:int rs, int rt, int rd
1234 int s = MASKED64 (GPR[rs], 5, 0);
1235 TRACE_ALU_INPUT2 (GPR[rt], s);
1236 GPR[rd] = GPR[rt] << s;
1237 TRACE_ALU_RESULT (GPR[rd]);
1240 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1241 "dsllv r<RD>, r<RT>, r<RS>"
1248 check_u64 (SD_, instruction_0);
1249 do_dsllv (SD_, RS, RT, RD);
1252 :function:::void:do_dsra:int rt, int rd, int shift
1254 TRACE_ALU_INPUT2 (GPR[rt], shift);
1255 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1256 TRACE_ALU_RESULT (GPR[rd]);
1260 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1261 "dsra r<RD>, r<RT>, <SHIFT>"
1268 check_u64 (SD_, instruction_0);
1269 do_dsra (SD_, RT, RD, SHIFT);
1273 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1274 "dsra32 r<RD>, r<RT>, <SHIFT>"
1282 check_u64 (SD_, instruction_0);
1283 TRACE_ALU_INPUT2 (GPR[RT], s);
1284 GPR[RD] = ((signed64) GPR[RT]) >> s;
1285 TRACE_ALU_RESULT (GPR[RD]);
1289 :function:::void:do_dsrav:int rs, int rt, int rd
1291 int s = MASKED64 (GPR[rs], 5, 0);
1292 TRACE_ALU_INPUT2 (GPR[rt], s);
1293 GPR[rd] = ((signed64) GPR[rt]) >> s;
1294 TRACE_ALU_RESULT (GPR[rd]);
1297 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1298 "dsrav r<RD>, r<RT>, r<RS>"
1305 check_u64 (SD_, instruction_0);
1306 do_dsrav (SD_, RS, RT, RD);
1309 :function:::void:do_dsrl:int rt, int rd, int shift
1311 TRACE_ALU_INPUT2 (GPR[rt], shift);
1312 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1313 TRACE_ALU_RESULT (GPR[rd]);
1317 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1318 "dsrl r<RD>, r<RT>, <SHIFT>"
1325 check_u64 (SD_, instruction_0);
1326 do_dsrl (SD_, RT, RD, SHIFT);
1330 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1331 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1339 check_u64 (SD_, instruction_0);
1340 TRACE_ALU_INPUT2 (GPR[RT], s);
1341 GPR[RD] = (unsigned64) GPR[RT] >> s;
1342 TRACE_ALU_RESULT (GPR[RD]);
1346 :function:::void:do_dsrlv:int rs, int rt, int rd
1348 int s = MASKED64 (GPR[rs], 5, 0);
1349 TRACE_ALU_INPUT2 (GPR[rt], s);
1350 GPR[rd] = (unsigned64) GPR[rt] >> s;
1351 TRACE_ALU_RESULT (GPR[rd]);
1356 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1357 "dsrlv r<RD>, r<RT>, r<RS>"
1364 check_u64 (SD_, instruction_0);
1365 do_dsrlv (SD_, RS, RT, RD);
1369 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1370 "dsub r<RD>, r<RS>, r<RT>"
1377 check_u64 (SD_, instruction_0);
1378 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1380 ALU64_BEGIN (GPR[RS]);
1381 ALU64_SUB (GPR[RT]);
1382 ALU64_END (GPR[RD]); /* This checks for overflow. */
1384 TRACE_ALU_RESULT (GPR[RD]);
1388 :function:::void:do_dsubu:int rs, int rt, int rd
1390 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1391 GPR[rd] = GPR[rs] - GPR[rt];
1392 TRACE_ALU_RESULT (GPR[rd]);
1395 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1396 "dsubu r<RD>, r<RS>, r<RT>"
1403 check_u64 (SD_, instruction_0);
1404 do_dsubu (SD_, RS, RT, RD);
1408 000010,26.INSTR_INDEX:NORMAL:32::J
1419 /* NOTE: The region used is that of the delay slot NIA and NOT the
1420 current instruction */
1421 address_word region = (NIA & MASK (63, 28));
1422 DELAY_SLOT (region | (INSTR_INDEX << 2));
1426 000011,26.INSTR_INDEX:NORMAL:32::JAL
1437 /* NOTE: The region used is that of the delay slot and NOT the
1438 current instruction */
1439 address_word region = (NIA & MASK (63, 28));
1441 DELAY_SLOT (region | (INSTR_INDEX << 2));
1444 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1445 "jalr r<RS>":RD == 31
1456 address_word temp = GPR[RS];
1462 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1473 DELAY_SLOT (GPR[RS]);
1477 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1479 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1480 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1481 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1488 vaddr = loadstore_ea (SD_, base, offset);
1489 if ((vaddr & access) != 0)
1491 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1493 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1494 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1495 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1496 byte = ((vaddr & mask) ^ bigendiancpu);
1497 return (memval >> (8 * byte));
1500 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1502 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1503 address_word reverseendian = (ReverseEndian ? -1 : 0);
1504 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1513 unsigned_word lhs_mask;
1516 vaddr = loadstore_ea (SD_, base, offset);
1517 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1518 paddr = (paddr ^ (reverseendian & mask));
1519 if (BigEndianMem == 0)
1520 paddr = paddr & ~access;
1522 /* compute where within the word/mem we are */
1523 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1524 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1525 nr_lhs_bits = 8 * byte + 8;
1526 nr_rhs_bits = 8 * access - 8 * byte;
1527 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1529 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1530 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1531 (long) ((unsigned64) paddr >> 32), (long) paddr,
1532 word, byte, nr_lhs_bits, nr_rhs_bits); */
1534 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1537 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1538 temp = (memval << nr_rhs_bits);
1542 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1543 temp = (memval >> nr_lhs_bits);
1545 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1546 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1548 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1549 (long) ((unsigned64) memval >> 32), (long) memval,
1550 (long) ((unsigned64) temp >> 32), (long) temp,
1551 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1552 (long) (rt >> 32), (long) rt); */
1556 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1558 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1559 address_word reverseendian = (ReverseEndian ? -1 : 0);
1560 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1567 vaddr = loadstore_ea (SD_, base, offset);
1568 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1569 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1570 paddr = (paddr ^ (reverseendian & mask));
1571 if (BigEndianMem != 0)
1572 paddr = paddr & ~access;
1573 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1574 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1575 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1576 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1577 (long) paddr, byte, (long) paddr, (long) memval); */
1579 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1581 rt |= (memval >> (8 * byte)) & screen;
1587 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1588 "lb r<RT>, <OFFSET>(r<BASE>)"
1598 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1602 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1603 "lbu r<RT>, <OFFSET>(r<BASE>)"
1613 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1617 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1618 "ld r<RT>, <OFFSET>(r<BASE>)"
1625 check_u64 (SD_, instruction_0);
1626 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1630 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1631 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1640 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1646 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1647 "ldl r<RT>, <OFFSET>(r<BASE>)"
1654 check_u64 (SD_, instruction_0);
1655 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1659 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1660 "ldr r<RT>, <OFFSET>(r<BASE>)"
1667 check_u64 (SD_, instruction_0);
1668 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1672 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1673 "lh r<RT>, <OFFSET>(r<BASE>)"
1683 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1687 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1688 "lhu r<RT>, <OFFSET>(r<BASE>)"
1698 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1702 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1703 "ll r<RT>, <OFFSET>(r<BASE>)"
1711 address_word base = GPR[BASE];
1712 address_word offset = EXTEND16 (OFFSET);
1714 address_word vaddr = loadstore_ea (SD_, base, offset);
1717 if ((vaddr & 3) != 0)
1719 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1723 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1725 unsigned64 memval = 0;
1726 unsigned64 memval1 = 0;
1727 unsigned64 mask = 0x7;
1728 unsigned int shift = 2;
1729 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1730 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1732 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1733 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1734 byte = ((vaddr & mask) ^ (bigend << shift));
1735 GPR[RT] = EXTEND32 (memval >> (8 * byte));
1743 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1744 "lld r<RT>, <OFFSET>(r<BASE>)"
1751 address_word base = GPR[BASE];
1752 address_word offset = EXTEND16 (OFFSET);
1753 check_u64 (SD_, instruction_0);
1755 address_word vaddr = loadstore_ea (SD_, base, offset);
1758 if ((vaddr & 7) != 0)
1760 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1764 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1766 unsigned64 memval = 0;
1767 unsigned64 memval1 = 0;
1768 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1777 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1778 "lui r<RT>, <IMMEDIATE>"
1788 TRACE_ALU_INPUT1 (IMMEDIATE);
1789 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1790 TRACE_ALU_RESULT (GPR[RT]);
1794 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1795 "lw r<RT>, <OFFSET>(r<BASE>)"
1805 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1809 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1810 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1820 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1824 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1825 "lwl r<RT>, <OFFSET>(r<BASE>)"
1835 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1839 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1840 "lwr r<RT>, <OFFSET>(r<BASE>)"
1850 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1854 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
1855 "lwu r<RT>, <OFFSET>(r<BASE>)"
1862 check_u64 (SD_, instruction_0);
1863 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1867 :function:::void:do_mfhi:int rd
1869 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1870 TRACE_ALU_INPUT1 (HI);
1872 TRACE_ALU_RESULT (GPR[rd]);
1875 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1891 :function:::void:do_mflo:int rd
1893 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1894 TRACE_ALU_INPUT1 (LO);
1896 TRACE_ALU_RESULT (GPR[rd]);
1899 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1915 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
1916 "movn r<RD>, r<RS>, r<RT>"
1927 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
1928 "movz r<RD>, r<RS>, r<RT>"
1939 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1950 check_mt_hilo (SD_, HIHISTORY);
1956 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
1967 check_mt_hilo (SD_, LOHISTORY);
1973 :function:::void:do_mult:int rs, int rt, int rd
1976 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1977 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1978 prod = (((signed64)(signed32) GPR[rs])
1979 * ((signed64)(signed32) GPR[rt]));
1980 LO = EXTEND32 (VL4_8 (prod));
1981 HI = EXTEND32 (VH4_8 (prod));
1984 TRACE_ALU_RESULT2 (HI, LO);
1987 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
1996 do_mult (SD_, RS, RT, 0);
2000 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2001 "mult r<RS>, r<RT>":RD == 0
2002 "mult r<RD>, r<RS>, r<RT>"
2006 do_mult (SD_, RS, RT, RD);
2010 :function:::void:do_multu:int rs, int rt, int rd
2013 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2014 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2015 prod = (((unsigned64)(unsigned32) GPR[rs])
2016 * ((unsigned64)(unsigned32) GPR[rt]));
2017 LO = EXTEND32 (VL4_8 (prod));
2018 HI = EXTEND32 (VH4_8 (prod));
2021 TRACE_ALU_RESULT2 (HI, LO);
2024 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2025 "multu r<RS>, r<RT>"
2033 do_multu (SD_, RS, RT, 0);
2036 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2037 "multu r<RS>, r<RT>":RD == 0
2038 "multu r<RD>, r<RS>, r<RT>"
2042 do_multu (SD_, RS, RT, RD);
2046 :function:::void:do_nor:int rs, int rt, int rd
2048 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2049 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2050 TRACE_ALU_RESULT (GPR[rd]);
2053 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2054 "nor r<RD>, r<RS>, r<RT>"
2064 do_nor (SD_, RS, RT, RD);
2068 :function:::void:do_or:int rs, int rt, int rd
2070 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2071 GPR[rd] = (GPR[rs] | GPR[rt]);
2072 TRACE_ALU_RESULT (GPR[rd]);
2075 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2076 "or r<RD>, r<RS>, r<RT>"
2086 do_or (SD_, RS, RT, RD);
2091 :function:::void:do_ori:int rs, int rt, unsigned immediate
2093 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2094 GPR[rt] = (GPR[rs] | immediate);
2095 TRACE_ALU_RESULT (GPR[rt]);
2098 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2099 "ori r<RT>, r<RS>, <IMMEDIATE>"
2109 do_ori (SD_, RS, RT, IMMEDIATE);
2113 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2114 "pref <HINT>, <OFFSET>(r<BASE>)"
2119 address_word base = GPR[BASE];
2120 address_word offset = EXTEND16 (OFFSET);
2122 address_word vaddr = loadstore_ea (SD_, base, offset);
2126 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2127 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2133 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2135 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2136 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2137 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2144 vaddr = loadstore_ea (SD_, base, offset);
2145 if ((vaddr & access) != 0)
2147 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2149 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2150 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2151 byte = ((vaddr & mask) ^ bigendiancpu);
2152 memval = (word << (8 * byte));
2153 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2156 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2158 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2159 address_word reverseendian = (ReverseEndian ? -1 : 0);
2160 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2170 vaddr = loadstore_ea (SD_, base, offset);
2171 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2172 paddr = (paddr ^ (reverseendian & mask));
2173 if (BigEndianMem == 0)
2174 paddr = paddr & ~access;
2176 /* compute where within the word/mem we are */
2177 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2178 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2179 nr_lhs_bits = 8 * byte + 8;
2180 nr_rhs_bits = 8 * access - 8 * byte;
2181 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2182 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2183 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2184 (long) ((unsigned64) paddr >> 32), (long) paddr,
2185 word, byte, nr_lhs_bits, nr_rhs_bits); */
2189 memval = (rt >> nr_rhs_bits);
2193 memval = (rt << nr_lhs_bits);
2195 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2196 (long) ((unsigned64) rt >> 32), (long) rt,
2197 (long) ((unsigned64) memval >> 32), (long) memval); */
2198 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2201 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2203 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2204 address_word reverseendian = (ReverseEndian ? -1 : 0);
2205 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2212 vaddr = loadstore_ea (SD_, base, offset);
2213 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2214 paddr = (paddr ^ (reverseendian & mask));
2215 if (BigEndianMem != 0)
2217 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2218 memval = (rt << (byte * 8));
2219 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2223 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2224 "sb r<RT>, <OFFSET>(r<BASE>)"
2234 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2238 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2239 "sc r<RT>, <OFFSET>(r<BASE>)"
2247 unsigned32 instruction = instruction_0;
2248 address_word base = GPR[BASE];
2249 address_word offset = EXTEND16 (OFFSET);
2251 address_word vaddr = loadstore_ea (SD_, base, offset);
2254 if ((vaddr & 3) != 0)
2256 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2260 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2262 unsigned64 memval = 0;
2263 unsigned64 memval1 = 0;
2264 unsigned64 mask = 0x7;
2266 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2267 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2268 memval = ((unsigned64) GPR[RT] << (8 * byte));
2271 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2280 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2281 "scd r<RT>, <OFFSET>(r<BASE>)"
2288 address_word base = GPR[BASE];
2289 address_word offset = EXTEND16 (OFFSET);
2290 check_u64 (SD_, instruction_0);
2292 address_word vaddr = loadstore_ea (SD_, base, offset);
2295 if ((vaddr & 7) != 0)
2297 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2301 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2303 unsigned64 memval = 0;
2304 unsigned64 memval1 = 0;
2308 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2317 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2318 "sd r<RT>, <OFFSET>(r<BASE>)"
2325 check_u64 (SD_, instruction_0);
2326 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2330 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2331 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2339 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2343 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2344 "sdl r<RT>, <OFFSET>(r<BASE>)"
2351 check_u64 (SD_, instruction_0);
2352 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2356 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2357 "sdr r<RT>, <OFFSET>(r<BASE>)"
2364 check_u64 (SD_, instruction_0);
2365 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2369 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2370 "sh r<RT>, <OFFSET>(r<BASE>)"
2380 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2384 :function:::void:do_sll:int rt, int rd, int shift
2386 unsigned32 temp = (GPR[rt] << shift);
2387 TRACE_ALU_INPUT2 (GPR[rt], shift);
2388 GPR[rd] = EXTEND32 (temp);
2389 TRACE_ALU_RESULT (GPR[rd]);
2392 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2393 "nop":RD == 0 && RT == 0 && SHIFT == 0
2394 "sll r<RD>, r<RT>, <SHIFT>"
2404 /* Skip shift for NOP, so that there won't be lots of extraneous
2406 if (RD != 0 || RT != 0 || SHIFT != 0)
2407 do_sll (SD_, RT, RD, SHIFT);
2411 :function:::void:do_sllv:int rs, int rt, int rd
2413 int s = MASKED (GPR[rs], 4, 0);
2414 unsigned32 temp = (GPR[rt] << s);
2415 TRACE_ALU_INPUT2 (GPR[rt], s);
2416 GPR[rd] = EXTEND32 (temp);
2417 TRACE_ALU_RESULT (GPR[rd]);
2420 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2421 "sllv r<RD>, r<RT>, r<RS>"
2431 do_sllv (SD_, RS, RT, RD);
2435 :function:::void:do_slt:int rs, int rt, int rd
2437 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2438 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2439 TRACE_ALU_RESULT (GPR[rd]);
2442 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2443 "slt r<RD>, r<RS>, r<RT>"
2453 do_slt (SD_, RS, RT, RD);
2457 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2459 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2460 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2461 TRACE_ALU_RESULT (GPR[rt]);
2464 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2465 "slti r<RT>, r<RS>, <IMMEDIATE>"
2475 do_slti (SD_, RS, RT, IMMEDIATE);
2479 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2481 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2482 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2483 TRACE_ALU_RESULT (GPR[rt]);
2486 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2487 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2497 do_sltiu (SD_, RS, RT, IMMEDIATE);
2502 :function:::void:do_sltu:int rs, int rt, int rd
2504 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2505 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2506 TRACE_ALU_RESULT (GPR[rd]);
2509 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2510 "sltu r<RD>, r<RS>, r<RT>"
2520 do_sltu (SD_, RS, RT, RD);
2524 :function:::void:do_sra:int rt, int rd, int shift
2526 signed32 temp = (signed32) GPR[rt] >> shift;
2527 TRACE_ALU_INPUT2 (GPR[rt], shift);
2528 GPR[rd] = EXTEND32 (temp);
2529 TRACE_ALU_RESULT (GPR[rd]);
2532 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2533 "sra r<RD>, r<RT>, <SHIFT>"
2543 do_sra (SD_, RT, RD, SHIFT);
2548 :function:::void:do_srav:int rs, int rt, int rd
2550 int s = MASKED (GPR[rs], 4, 0);
2551 signed32 temp = (signed32) GPR[rt] >> s;
2552 TRACE_ALU_INPUT2 (GPR[rt], s);
2553 GPR[rd] = EXTEND32 (temp);
2554 TRACE_ALU_RESULT (GPR[rd]);
2557 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
2558 "srav r<RD>, r<RT>, r<RS>"
2568 do_srav (SD_, RS, RT, RD);
2573 :function:::void:do_srl:int rt, int rd, int shift
2575 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2576 TRACE_ALU_INPUT2 (GPR[rt], shift);
2577 GPR[rd] = EXTEND32 (temp);
2578 TRACE_ALU_RESULT (GPR[rd]);
2581 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2582 "srl r<RD>, r<RT>, <SHIFT>"
2592 do_srl (SD_, RT, RD, SHIFT);
2596 :function:::void:do_srlv:int rs, int rt, int rd
2598 int s = MASKED (GPR[rs], 4, 0);
2599 unsigned32 temp = (unsigned32) GPR[rt] >> s;
2600 TRACE_ALU_INPUT2 (GPR[rt], s);
2601 GPR[rd] = EXTEND32 (temp);
2602 TRACE_ALU_RESULT (GPR[rd]);
2605 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
2606 "srlv r<RD>, r<RT>, r<RS>"
2616 do_srlv (SD_, RS, RT, RD);
2620 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
2621 "sub r<RD>, r<RS>, r<RT>"
2631 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2633 ALU32_BEGIN (GPR[RS]);
2634 ALU32_SUB (GPR[RT]);
2635 ALU32_END (GPR[RD]); /* This checks for overflow. */
2637 TRACE_ALU_RESULT (GPR[RD]);
2641 :function:::void:do_subu:int rs, int rt, int rd
2643 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2644 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2645 TRACE_ALU_RESULT (GPR[rd]);
2648 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
2649 "subu r<RD>, r<RS>, r<RT>"
2659 do_subu (SD_, RS, RT, RD);
2663 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2664 "sw r<RT>, <OFFSET>(r<BASE>)"
2674 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2678 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2679 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2689 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2693 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2694 "swl r<RT>, <OFFSET>(r<BASE>)"
2704 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2708 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2709 "swr r<RT>, <OFFSET>(r<BASE>)"
2719 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2723 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2734 SyncOperation (STYPE);
2738 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2749 SignalException (SystemCall, instruction_0);
2753 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2762 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2763 SignalException (Trap, instruction_0);
2767 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2768 "teqi r<RS>, <IMMEDIATE>"
2776 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2777 SignalException (Trap, instruction_0);
2781 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2790 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2791 SignalException (Trap, instruction_0);
2795 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2796 "tgei r<RS>, <IMMEDIATE>"
2804 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2805 SignalException (Trap, instruction_0);
2809 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2810 "tgeiu r<RS>, <IMMEDIATE>"
2818 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2819 SignalException (Trap, instruction_0);
2823 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2832 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2833 SignalException (Trap, instruction_0);
2837 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2846 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2847 SignalException (Trap, instruction_0);
2851 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2852 "tlti r<RS>, <IMMEDIATE>"
2860 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2861 SignalException (Trap, instruction_0);
2865 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2866 "tltiu r<RS>, <IMMEDIATE>"
2874 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2875 SignalException (Trap, instruction_0);
2879 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2888 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2889 SignalException (Trap, instruction_0);
2893 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2902 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2903 SignalException (Trap, instruction_0);
2907 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2908 "tne r<RS>, <IMMEDIATE>"
2916 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2917 SignalException (Trap, instruction_0);
2921 :function:::void:do_xor:int rs, int rt, int rd
2923 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2924 GPR[rd] = GPR[rs] ^ GPR[rt];
2925 TRACE_ALU_RESULT (GPR[rd]);
2928 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
2929 "xor r<RD>, r<RS>, r<RT>"
2939 do_xor (SD_, RS, RT, RD);
2943 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
2945 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2946 GPR[rt] = GPR[rs] ^ immediate;
2947 TRACE_ALU_RESULT (GPR[rt]);
2950 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2951 "xori r<RT>, r<RS>, <IMMEDIATE>"
2961 do_xori (SD_, RS, RT, IMMEDIATE);
2966 // MIPS Architecture:
2968 // FPU Instruction Set (COP1 & COP1X)
2976 case fmt_single: return "s";
2977 case fmt_double: return "d";
2978 case fmt_word: return "w";
2979 case fmt_long: return "l";
2980 default: return "?";
2990 default: return "?";
3010 :%s::::COND:int cond
3014 case 00: return "f";
3015 case 01: return "un";
3016 case 02: return "eq";
3017 case 03: return "ueq";
3018 case 04: return "olt";
3019 case 05: return "ult";
3020 case 06: return "ole";
3021 case 07: return "ule";
3022 case 010: return "sf";
3023 case 011: return "ngle";
3024 case 012: return "seq";
3025 case 013: return "ngl";
3026 case 014: return "lt";
3027 case 015: return "nge";
3028 case 016: return "le";
3029 case 017: return "ngt";
3030 default: return "?";
3037 // Check that the given FPU format is usable, and signal a
3038 // ReservedInstruction exception if not.
3041 // check_fmt checks that the format is single or double.
3042 :function:::void:check_fmt:int fmt, instruction_word insn
3052 if ((fmt != fmt_single) && (fmt != fmt_double))
3053 SignalException (ReservedInstruction, insn);
3056 // check_fmt_p checks that the format is single, double, or paired single.
3057 :function:::void:check_fmt_p:int fmt, instruction_word insn
3067 /* None of these ISAs support Paired Single, so just fall back to
3068 the single/double check. */
3069 /* XXX FIXME: not true for mipsV, but we don't support .ps insns yet. */
3070 check_fmt (SD_, fmt, insn);
3076 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3077 // exception if not.
3080 :function:::void:check_fpu:
3090 if (! COP_Usable (1))
3091 SignalExceptionCoProcessorUnusable (1);
3095 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3096 "abs.%s<FMT> f<FD>, f<FS>"
3108 check_fmt_p (SD_, fmt, instruction_0);
3109 StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
3114 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3115 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3127 check_fmt_p (SD_, fmt, instruction_0);
3128 StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3138 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3139 "bc1%s<TF>%s<ND> <OFFSET>"
3145 check_branch_bug ();
3146 TRACE_BRANCH_INPUT (PREVCOC1());
3147 if (PREVCOC1() == TF)
3149 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3150 TRACE_BRANCH_RESULT (dest);
3151 mark_branch_bug (dest);
3156 TRACE_BRANCH_RESULT (0);
3157 NULLIFY_NEXT_INSTRUCTION ();
3161 TRACE_BRANCH_RESULT (NIA);
3165 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3166 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3167 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3175 check_branch_bug ();
3176 if (GETFCC(CC) == TF)
3178 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3179 mark_branch_bug (dest);
3184 NULLIFY_NEXT_INSTRUCTION ();
3197 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3203 unsigned64 ofs = ValueFPR (fs, fmt);
3204 unsigned64 oft = ValueFPR (ft, fmt);
3205 if (NaN (ofs, fmt) || NaN (oft, fmt))
3207 if (FCSR & FP_ENABLE (IO))
3209 FCSR |= FP_CAUSE (IO);
3210 SignalExceptionFPE ();
3218 less = Less (ofs, oft, fmt);
3219 equal = Equal (ofs, oft, fmt);
3222 condition = (((cond & (1 << 2)) && less)
3223 || ((cond & (1 << 1)) && equal)
3224 || ((cond & (1 << 0)) && unordered));
3225 SETFCC (cc, condition);
3228 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3229 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3236 check_fmt_p (SD_, fmt, instruction_0);
3237 do_c_cond_fmt (SD_, fmt, FT, FS, 0, COND, instruction_0);
3240 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3241 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3242 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3251 check_fmt_p (SD_, fmt, instruction_0);
3252 do_c_cond_fmt (SD_, fmt, FT, FS, CC, COND, instruction_0);
3256 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3257 "ceil.l.%s<FMT> f<FD>, f<FS>"
3267 check_fmt (SD_, fmt, instruction_0);
3268 StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
3272 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3283 check_fmt (SD_, fmt, instruction_0);
3284 StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
3290 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
3291 "c%s<X>c1 r<RT>, f<FS>"
3300 PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
3302 PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
3304 PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
3307 { /* control from */
3309 PENDING_FILL(RT, EXTEND32 (FCR0));
3311 PENDING_FILL(RT, EXTEND32 (FCR31));
3315 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
3316 "c%s<X>c1 r<RT>, f<FS>"
3327 TRACE_ALU_INPUT1 (GPR[RT]);
3330 FCR0 = VL4_8(GPR[RT]);
3331 TRACE_ALU_RESULT (FCR0);
3335 FCR31 = VL4_8(GPR[RT]);
3336 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3337 TRACE_ALU_RESULT (FCR31);
3341 TRACE_ALU_RESULT0 ();
3346 { /* control from */
3349 TRACE_ALU_INPUT1 (FCR0);
3350 GPR[RT] = EXTEND32 (FCR0);
3354 TRACE_ALU_INPUT1 (FCR31);
3355 GPR[RT] = EXTEND32 (FCR31);
3357 TRACE_ALU_RESULT (GPR[RT]);
3364 // FIXME: Does not correctly differentiate between mips*
3366 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3367 "cvt.d.%s<FMT> f<FD>, f<FS>"
3380 if ((fmt == fmt_double) | 0)
3381 SignalException (ReservedInstruction, instruction_0);
3383 StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
3388 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3389 "cvt.l.%s<FMT> f<FD>, f<FS>"
3400 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3401 SignalException (ReservedInstruction, instruction_0);
3403 StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
3409 // FIXME: Does not correctly differentiate between mips*
3411 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3412 "cvt.s.%s<FMT> f<FD>, f<FS>"
3425 if ((fmt == fmt_single) | 0)
3426 SignalException (ReservedInstruction, instruction_0);
3428 StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
3433 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
3434 "cvt.w.%s<FMT> f<FD>, f<FS>"
3447 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
3448 SignalException (ReservedInstruction, instruction_0);
3450 StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
3455 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
3456 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3468 check_fmt (SD_, fmt, instruction_0);
3469 StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3475 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
3476 "dm%s<X>c1 r<RT>, f<FS>"
3480 check_u64 (SD_, instruction_0);
3483 if (SizeFGR() == 64)
3484 PENDING_FILL((FS + FGRIDX),GPR[RT]);
3485 else if ((FS & 0x1) == 0)
3487 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3488 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3493 if (SizeFGR() == 64)
3494 PENDING_FILL(RT,FGR[FS]);
3495 else if ((FS & 0x1) == 0)
3496 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3499 if (STATE_VERBOSE_P(SD))
3501 "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
3503 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3507 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
3508 "dm%s<X>c1 r<RT>, f<FS>"
3516 check_u64 (SD_, instruction_0);
3519 if (SizeFGR() == 64)
3520 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3521 else if ((FS & 0x1) == 0)
3522 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3526 if (SizeFGR() == 64)
3528 else if ((FS & 0x1) == 0)
3529 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3532 if (STATE_VERBOSE_P(SD))
3534 "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
3536 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3542 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
3543 "floor.l.%s<FMT> f<FD>, f<FS>"
3553 check_fmt (SD_, fmt, instruction_0);
3554 StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
3558 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
3559 "floor.w.%s<FMT> f<FD>, f<FS>"
3570 check_fmt (SD_, fmt, instruction_0);
3571 StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
3575 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
3576 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
3586 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3590 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
3591 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3597 check_u64 (SD_, instruction_0);
3598 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3603 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
3604 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
3615 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3619 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
3620 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3626 check_u64 (SD_, instruction_0);
3627 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3633 // FIXME: Not correct for mips*
3635 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3636 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3643 StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
3648 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3649 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3656 StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
3663 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
3664 "m%s<X>c1 r<RT>, f<FS>"
3672 if (SizeFGR() == 64)
3674 if (STATE_VERBOSE_P(SD))
3676 "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
3678 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3681 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3684 PENDING_FILL (RT, EXTEND32 (FGR[FS]));
3686 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
3687 "m%s<X>c1 r<RT>, f<FS>"
3698 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3700 GPR[RT] = EXTEND32 (FGR[FS]);
3704 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
3705 "mov.%s<FMT> f<FD>, f<FS>"
3717 check_fmt_p (SD_, fmt, instruction_0);
3718 StoreFPR(FD,fmt,ValueFPR(FS,fmt));
3724 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
3725 "mov%s<TF> r<RD>, r<RS>, <CC>"
3731 if (GETFCC(CC) == TF)
3738 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
3739 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3747 if (GETFCC(CC) == TF)
3748 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
3750 StoreFPR (FD, fmt, ValueFPR (FD, fmt));
3755 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
3756 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
3763 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3765 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3772 // MOVT.fmt see MOVtf.fmt
3776 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
3777 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3784 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3786 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3791 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
3792 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3798 StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
3803 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
3804 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3810 StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
3817 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
3818 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3830 check_fmt_p (SD_, fmt, instruction_0);
3831 StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3835 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
3836 "neg.%s<FMT> f<FD>, f<FS>"
3848 check_fmt_p (SD_, fmt, instruction_0);
3849 StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
3854 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
3855 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3861 StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
3866 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
3867 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3873 StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
3878 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
3879 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3885 StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
3890 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
3891 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3897 StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
3901 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
3902 "prefx <HINT>, r<INDEX>(r<BASE>)"
3907 address_word base = GPR[BASE];
3908 address_word index = GPR[INDEX];
3910 address_word vaddr = loadstore_ea (SD_, base, index);
3913 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3914 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
3918 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
3919 "recip.%s<FMT> f<FD>, f<FS>"
3926 check_fmt (SD_, fmt, instruction_0);
3927 StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
3931 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
3932 "round.l.%s<FMT> f<FD>, f<FS>"
3942 check_fmt (SD_, fmt, instruction_0);
3943 StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
3947 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
3948 "round.w.%s<FMT> f<FD>, f<FS>"
3959 check_fmt (SD_, fmt, instruction_0);
3960 StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
3964 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
3967 "rsqrt.%s<FMT> f<FD>, f<FS>"
3972 check_fmt (SD_, fmt, instruction_0);
3973 StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
3977 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
3978 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
3988 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
3992 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
3993 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
3999 check_u64 (SD_, instruction_0);
4000 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4004 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4005 "sqrt.%s<FMT> f<FD>, f<FS>"
4016 check_fmt (SD_, fmt, instruction_0);
4017 StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
4021 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4022 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4034 check_fmt_p (SD_, fmt, instruction_0);
4035 StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4040 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4041 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4051 address_word base = GPR[BASE];
4052 address_word offset = EXTEND16 (OFFSET);
4055 address_word vaddr = loadstore_ea (SD_, base, offset);
4058 if ((vaddr & 3) != 0)
4060 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4064 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4067 uword64 memval1 = 0;
4068 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4069 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4070 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4072 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4073 byte = ((vaddr & mask) ^ bigendiancpu);
4074 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4075 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4082 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4083 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4089 address_word base = GPR[BASE];
4090 address_word index = GPR[INDEX];
4092 check_u64 (SD_, instruction_0);
4094 address_word vaddr = loadstore_ea (SD_, base, index);
4097 if ((vaddr & 3) != 0)
4099 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4103 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4105 unsigned64 memval = 0;
4106 unsigned64 memval1 = 0;
4107 unsigned64 mask = 0x7;
4109 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4110 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4111 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4113 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4121 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4122 "trunc.l.%s<FMT> f<FD>, f<FS>"
4132 check_fmt (SD_, fmt, instruction_0);
4133 StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
4137 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4138 "trunc.w.%s<FMT> f<FD>, f<FS>"
4149 check_fmt (SD_, fmt, instruction_0);
4150 StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
4155 // MIPS Architecture:
4157 // System Control Instruction Set (COP0)
4161 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4171 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4173 // stub needed for eCos as tx39 hardware bug workaround
4180 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4191 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4201 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4212 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4213 "cache <OP>, <OFFSET>(r<BASE>)"
4221 address_word base = GPR[BASE];
4222 address_word offset = EXTEND16 (OFFSET);
4224 address_word vaddr = loadstore_ea (SD_, base, offset);
4227 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4228 CacheOp(OP,vaddr,paddr,instruction_0);
4233 010000,1,0000000000000000000,111001:COP0:32::DI
4244 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4245 "dmfc0 r<RT>, r<RD>"
4250 check_u64 (SD_, instruction_0);
4251 DecodeCoproc (instruction_0);
4255 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4256 "dmtc0 r<RT>, r<RD>"
4261 check_u64 (SD_, instruction_0);
4262 DecodeCoproc (instruction_0);
4266 010000,1,0000000000000000000,111000:COP0:32::EI
4277 010000,1,0000000000000000000,011000:COP0:32::ERET
4285 if (SR & status_ERL)
4287 /* Oops, not yet available */
4288 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4300 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4301 "mfc0 r<RT>, r<RD> # <REGX>"
4311 TRACE_ALU_INPUT0 ();
4312 DecodeCoproc (instruction_0);
4313 TRACE_ALU_RESULT (GPR[RT]);
4316 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4317 "mtc0 r<RT>, r<RD> # <REGX>"
4327 DecodeCoproc (instruction_0);
4331 010000,1,0000000000000000000,010000:COP0:32::RFE
4342 DecodeCoproc (instruction_0);
4346 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4347 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
4356 DecodeCoproc (instruction_0);
4361 010000,1,0000000000000000000,001000:COP0:32::TLBP
4372 010000,1,0000000000000000000,000001:COP0:32::TLBR
4383 010000,1,0000000000000000000,000010:COP0:32::TLBWI
4394 010000,1,0000000000000000000,000110:COP0:32::TLBWR