sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 // In mips.igen, the semantics for many of the instructions were created
   4 // using code generated by gencode.  Those semantic segments could be
   5 // greatly simplified.
   6 //
   7 //    <insn> ::=
   8 //        <insn-word> { "+" <insn-word> }
   9 //        ":" <format-name>
  10 //        ":" <filter-flags>
  11 //        ":" <options>
  12 //        ":" <name>
  13 //        <nl>
  14 //        { <insn-model> }
  15 //        { <insn-mnemonic> }
  16 //        <code-block>
  17 //
  18
  19
  20 // IGEN config - mips16
  21 // :option:16::insn-bit-size:16
  22 // :option:16::hi-bit-nr:15
  23 :option:16::insn-specifying-widths:true
  24 :option:16::gen-delayed-branch:false
  25
  26 // IGEN config - mips32/64..
  27 // :option:32::insn-bit-size:32
  28 // :option:32::hi-bit-nr:31
  29 :option:32::insn-specifying-widths:true
  30 :option:32::gen-delayed-branch:false
  31
  32
  33 // Generate separate simulators for each target
  34 // :option:::multi-sim:true
  35
  36
  37 // Models known by this simulator are defined below.
  38 //
  39 // When placing models in the instruction descriptions, please place
  40 // them one per line, in the order given here.
  41
  42 //  MIPS ISAs:
  43 //
  44 //  Instructions and related functions for these models are included in
  45 //  this file.
  46 :model:::mipsI:mips3000:
  47 :model:::mipsII:mips6000:
  48 :model:::mipsIII:mips4000:
  49 :model:::mipsIV:mips8000:
  50 :model:::mipsV:mipsisaV:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr5000:mips5000:
  61 :model:::r3900:mips3900:                // tx.igen
  62
  63 //  MIPS Application Specific Extensions (ASEs)
  64 //
  65 //  Instructions for the ASEs are in separate .igen files.
  66 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  67
  68
  69 // Pseudo instructions known by IGEN
  70 :internal::::illegal:
  71 {
  72   SignalException (ReservedInstruction, 0);
  73 }
  74
  75
  76 // Pseudo instructions known by interp.c
  77 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  78 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  79 "rsvd <OP>"
  80 {
  81   SignalException (ReservedInstruction, instruction_0);
  82 }
  83
  84
  85
  86 // Helper:
  87 //
  88 // Simulate a 32 bit delayslot instruction
  89 //
  90
  91 :function:::address_word:delayslot32:address_word target
  92 {
  93   instruction_word delay_insn;
  94   sim_events_slip (SD, 1);
  95   DSPC = CIA;
  96   CIA = CIA + 4; /* NOTE not mips16 */
  97   STATE |= simDELAYSLOT;
  98   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  99   ENGINE_ISSUE_PREFIX_HOOK();
 100   idecode_issue (CPU_, delay_insn, (CIA));
 101   STATE &= ~simDELAYSLOT;
 102   return target;
 103 }
 104
 105 :function:::address_word:nullify_next_insn32:
 106 {
 107   sim_events_slip (SD, 1);
 108   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 109   return CIA + 8;
 110 }
 111
 112
 113 // Helper:
 114 //
 115 // Calculate an effective address given a base and an offset.
 116 //
 117
 118 :function:::address_word:loadstore_ea:address_word base, address_word offset
 119 *mipsI:
 120 *mipsII:
 121 *mipsIII:
 122 *mipsIV:
 123 *mipsV:
 124 *vr4100:
 125 *vr5000:
 126 *r3900:
 127 {
 128   return base + offset;
 129 }
 130
 131
 132 // Helper:
 133 //
 134 // Check that an access to a HI/LO register meets timing requirements
 135 //
 136 // The following requirements exist:
 137 //
 138 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 139 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 140 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 141 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 142 //
 143
 144 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 145 {
 146   if (history->mf.timestamp + 3 > time)
 147     {
 148       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 149                         itable[MY_INDEX].name,
 150                         new, (long) CIA,
 151                         (long) history->mf.cia);
 152       return 0;
 153     }
 154   return 1;
 155 }
 156
 157 :function:::int:check_mt_hilo:hilo_history *history
 158 *mipsI:
 159 *mipsII:
 160 *mipsIII:
 161 *mipsIV:
 162 *mipsV:
 163 *vr4100:
 164 *vr5000:
 165 {
 166   signed64 time = sim_events_time (SD);
 167   int ok = check_mf_cycles (SD_, history, time, "MT");
 168   history->mt.timestamp = time;
 169   history->mt.cia = CIA;
 170   return ok;
 171 }
 172
 173 :function:::int:check_mt_hilo:hilo_history *history
 174 *r3900:
 175 {
 176   signed64 time = sim_events_time (SD);
 177   history->mt.timestamp = time;
 178   history->mt.cia = CIA;
 179   return 1;
 180 }
 181
 182
 183 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 184 *mipsI:
 185 *mipsII:
 186 *mipsIII:
 187 *mipsIV:
 188 *mipsV:
 189 *vr4100:
 190 *vr5000:
 191 *r3900:
 192 {
 193   signed64 time = sim_events_time (SD);
 194   int ok = 1;
 195   if (peer != NULL
 196       && peer->mt.timestamp > history->op.timestamp
 197       && history->mt.timestamp < history->op.timestamp
 198       && ! (history->mf.timestamp > history->op.timestamp
 199             && history->mf.timestamp < peer->mt.timestamp)
 200       && ! (peer->mf.timestamp > history->op.timestamp
 201             && peer->mf.timestamp < peer->mt.timestamp))
 202     {
 203       /* The peer has been written to since the last OP yet we have
 204          not */
 205       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 206                         itable[MY_INDEX].name,
 207                         (long) CIA,
 208                         (long) history->op.cia,
 209                         (long) peer->mt.cia);
 210       ok = 0;
 211     }
 212   history->mf.timestamp = time;
 213   history->mf.cia = CIA;
 214   return ok;
 215 }
 216
 217
 218
 219 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 220 *mipsI:
 221 *mipsII:
 222 *mipsIII:
 223 *mipsIV:
 224 *mipsV:
 225 *vr4100:
 226 *vr5000:
 227 {
 228   signed64 time = sim_events_time (SD);
 229   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 230             && check_mf_cycles (SD_, lo, time, "OP"));
 231   hi->op.timestamp = time;
 232   lo->op.timestamp = time;
 233   hi->op.cia = CIA;
 234   lo->op.cia = CIA;
 235   return ok;
 236 }
 237
 238 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 239 // a mf{hi,lo}
 240 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 241 *r3900:
 242 {
 243   /* FIXME: could record the fact that a stall occured if we want */
 244   signed64 time = sim_events_time (SD);
 245   hi->op.timestamp = time;
 246   lo->op.timestamp = time;
 247   hi->op.cia = CIA;
 248   lo->op.cia = CIA;
 249   return 1;
 250 }
 251
 252
 253 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 254 *mipsI:
 255 *mipsII:
 256 *mipsIII:
 257 *mipsIV:
 258 *mipsV:
 259 *vr4100:
 260 *vr5000:
 261 *r3900:
 262 {
 263   signed64 time = sim_events_time (SD);
 264   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 265             && check_mf_cycles (SD_, lo, time, "OP"));
 266   hi->op.timestamp = time;
 267   lo->op.timestamp = time;
 268   hi->op.cia = CIA;
 269   lo->op.cia = CIA;
 270   return ok;
 271 }
 272
 273
 274 // Helper:
 275 //
 276 // Check that the 64-bit instruction can currently be used, and signal
 277 // an ReservedInstruction exception if not.
 278 //
 279
 280 :function:::void:check_u64:instruction_word insn
 281 *mipsIII:
 282 *mipsIV:
 283 *mipsV:
 284 *vr4100:
 285 *vr5000:
 286 {
 287   // On mips64, if UserMode check SR:PX & SR:UX bits.
 288   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 289 }
 290
 291
 292
 293 //
 294 // MIPS Architecture:
 295 //
 296 //        CPU Instruction Set (mipsI - mipsV)
 297 //
 298
 299
 300
 301 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 302 "add r<RD>, r<RS>, r<RT>"
 303 *mipsI:
 304 *mipsII:
 305 *mipsIII:
 306 *mipsIV:
 307 *mipsV:
 308 *vr4100:
 309 *vr5000:
 310 *r3900:
 311 {
 312   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 313   {
 314     ALU32_BEGIN (GPR[RS]);
 315     ALU32_ADD (GPR[RT]);
 316     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 317   }
 318   TRACE_ALU_RESULT (GPR[RD]);
 319 }
 320
 321
 322
 323 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 324 "addi r<RT>, r<RS>, <IMMEDIATE>"
 325 *mipsI:
 326 *mipsII:
 327 *mipsIII:
 328 *mipsIV:
 329 *mipsV:
 330 *vr4100:
 331 *vr5000:
 332 *r3900:
 333 {
 334   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 335   {
 336     ALU32_BEGIN (GPR[RS]);
 337     ALU32_ADD (EXTEND16 (IMMEDIATE));
 338     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 339   }
 340   TRACE_ALU_RESULT (GPR[RT]);
 341 }
 342
 343
 344
 345 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 346 {
 347   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 348   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 349   TRACE_ALU_RESULT (GPR[rt]);
 350 }
 351
 352 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 353 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 354 *mipsI:
 355 *mipsII:
 356 *mipsIII:
 357 *mipsIV:
 358 *mipsV:
 359 *vr4100:
 360 *vr5000:
 361 *r3900:
 362 {
 363   do_addiu (SD_, RS, RT, IMMEDIATE);
 364 }
 365
 366
 367
 368 :function:::void:do_addu:int rs, int rt, int rd
 369 {
 370   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 371   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 372   TRACE_ALU_RESULT (GPR[rd]);
 373 }
 374
 375 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 376 "addu r<RD>, r<RS>, r<RT>"
 377 *mipsI:
 378 *mipsII:
 379 *mipsIII:
 380 *mipsIV:
 381 *mipsV:
 382 *vr4100:
 383 *vr5000:
 384 *r3900:
 385 {
 386   do_addu (SD_, RS, RT, RD);
 387 }
 388
 389
 390
 391 :function:::void:do_and:int rs, int rt, int rd
 392 {
 393   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 394   GPR[rd] = GPR[rs] & GPR[rt];
 395   TRACE_ALU_RESULT (GPR[rd]);
 396 }
 397
 398 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 399 "and r<RD>, r<RS>, r<RT>"
 400 *mipsI:
 401 *mipsII:
 402 *mipsIII:
 403 *mipsIV:
 404 *mipsV:
 405 *vr4100:
 406 *vr5000:
 407 *r3900:
 408 {
 409   do_and (SD_, RS, RT, RD);
 410 }
 411
 412
 413
 414 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 415 "and r<RT>, r<RS>, <IMMEDIATE>"
 416 *mipsI:
 417 *mipsII:
 418 *mipsIII:
 419 *mipsIV:
 420 *mipsV:
 421 *vr4100:
 422 *vr5000:
 423 *r3900:
 424 {
 425   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 426   GPR[RT] = GPR[RS] & IMMEDIATE;
 427   TRACE_ALU_RESULT (GPR[RT]);
 428 }
 429
 430
 431
 432 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 433 "beq r<RS>, r<RT>, <OFFSET>"
 434 *mipsI:
 435 *mipsII:
 436 *mipsIII:
 437 *mipsIV:
 438 *mipsV:
 439 *vr4100:
 440 *vr5000:
 441 *r3900:
 442 {
 443   address_word offset = EXTEND16 (OFFSET) << 2;
 444   check_branch_bug ();
 445   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 446     {
 447       mark_branch_bug (NIA+offset);
 448       DELAY_SLOT (NIA + offset);
 449     }
 450 }
 451
 452
 453
 454 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 455 "beql r<RS>, r<RT>, <OFFSET>"
 456 *mipsII:
 457 *mipsIII:
 458 *mipsIV:
 459 *mipsV:
 460 *vr4100:
 461 *vr5000:
 462 *r3900:
 463 {
 464   address_word offset = EXTEND16 (OFFSET) << 2;
 465   check_branch_bug ();
 466   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 467     {
 468       mark_branch_bug (NIA+offset);
 469       DELAY_SLOT (NIA + offset);
 470     }
 471   else
 472     NULLIFY_NEXT_INSTRUCTION ();
 473 }
 474
 475
 476
 477 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 478 "bgez r<RS>, <OFFSET>"
 479 *mipsI:
 480 *mipsII:
 481 *mipsIII:
 482 *mipsIV:
 483 *mipsV:
 484 *vr4100:
 485 *vr5000:
 486 *r3900:
 487 {
 488   address_word offset = EXTEND16 (OFFSET) << 2;
 489   check_branch_bug ();
 490   if ((signed_word) GPR[RS] >= 0)
 491     {
 492       mark_branch_bug (NIA+offset);
 493       DELAY_SLOT (NIA + offset);
 494     }
 495 }
 496
 497
 498
 499 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 500 "bgezal r<RS>, <OFFSET>"
 501 *mipsI:
 502 *mipsII:
 503 *mipsIII:
 504 *mipsIV:
 505 *mipsV:
 506 *vr4100:
 507 *vr5000:
 508 *r3900:
 509 {
 510   address_word offset = EXTEND16 (OFFSET) << 2;
 511   check_branch_bug ();
 512   RA = (CIA + 8);
 513   if ((signed_word) GPR[RS] >= 0)
 514     {
 515       mark_branch_bug (NIA+offset);
 516       DELAY_SLOT (NIA + offset);
 517     }
 518 }
 519
 520
 521
 522 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 523 "bgezall r<RS>, <OFFSET>"
 524 *mipsII:
 525 *mipsIII:
 526 *mipsIV:
 527 *mipsV:
 528 *vr4100:
 529 *vr5000:
 530 *r3900:
 531 {
 532   address_word offset = EXTEND16 (OFFSET) << 2;
 533   check_branch_bug ();
 534   RA = (CIA + 8);
 535   /* NOTE: The branch occurs AFTER the next instruction has been
 536      executed */
 537   if ((signed_word) GPR[RS] >= 0)
 538     {
 539       mark_branch_bug (NIA+offset);
 540       DELAY_SLOT (NIA + offset);
 541     }
 542   else
 543     NULLIFY_NEXT_INSTRUCTION ();
 544 }
 545
 546
 547
 548 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 549 "bgezl r<RS>, <OFFSET>"
 550 *mipsII:
 551 *mipsIII:
 552 *mipsIV:
 553 *mipsV:
 554 *vr4100:
 555 *vr5000:
 556 *r3900:
 557 {
 558   address_word offset = EXTEND16 (OFFSET) << 2;
 559   check_branch_bug ();
 560   if ((signed_word) GPR[RS] >= 0)
 561     {
 562       mark_branch_bug (NIA+offset);
 563       DELAY_SLOT (NIA + offset);
 564     }
 565   else
 566     NULLIFY_NEXT_INSTRUCTION ();
 567 }
 568
 569
 570
 571 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 572 "bgtz r<RS>, <OFFSET>"
 573 *mipsI:
 574 *mipsII:
 575 *mipsIII:
 576 *mipsIV:
 577 *mipsV:
 578 *vr4100:
 579 *vr5000:
 580 *r3900:
 581 {
 582   address_word offset = EXTEND16 (OFFSET) << 2;
 583   check_branch_bug ();
 584   if ((signed_word) GPR[RS] > 0)
 585     {
 586       mark_branch_bug (NIA+offset);
 587       DELAY_SLOT (NIA + offset);
 588     }
 589 }
 590
 591
 592
 593 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 594 "bgtzl r<RS>, <OFFSET>"
 595 *mipsII:
 596 *mipsIII:
 597 *mipsIV:
 598 *mipsV:
 599 *vr4100:
 600 *vr5000:
 601 *r3900:
 602 {
 603   address_word offset = EXTEND16 (OFFSET) << 2;
 604   check_branch_bug ();
 605   /* NOTE: The branch occurs AFTER the next instruction has been
 606      executed */
 607   if ((signed_word) GPR[RS] > 0)
 608     {
 609       mark_branch_bug (NIA+offset);
 610       DELAY_SLOT (NIA + offset);
 611     }
 612   else
 613     NULLIFY_NEXT_INSTRUCTION ();
 614 }
 615
 616
 617
 618 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 619 "blez r<RS>, <OFFSET>"
 620 *mipsI:
 621 *mipsII:
 622 *mipsIII:
 623 *mipsIV:
 624 *mipsV:
 625 *vr4100:
 626 *vr5000:
 627 *r3900:
 628 {
 629   address_word offset = EXTEND16 (OFFSET) << 2;
 630   check_branch_bug ();
 631   /* NOTE: The branch occurs AFTER the next instruction has been
 632      executed */
 633   if ((signed_word) GPR[RS] <= 0)
 634     {
 635       mark_branch_bug (NIA+offset);
 636       DELAY_SLOT (NIA + offset);
 637     }
 638 }
 639
 640
 641
 642 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 643 "bgezl r<RS>, <OFFSET>"
 644 *mipsII:
 645 *mipsIII:
 646 *mipsIV:
 647 *mipsV:
 648 *vr4100:
 649 *vr5000:
 650 *r3900:
 651 {
 652   address_word offset = EXTEND16 (OFFSET) << 2;
 653   check_branch_bug ();
 654   if ((signed_word) GPR[RS] <= 0)
 655     {
 656       mark_branch_bug (NIA+offset);
 657       DELAY_SLOT (NIA + offset);
 658     }
 659   else
 660     NULLIFY_NEXT_INSTRUCTION ();
 661 }
 662
 663
 664
 665 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 666 "bltz r<RS>, <OFFSET>"
 667 *mipsI:
 668 *mipsII:
 669 *mipsIII:
 670 *mipsIV:
 671 *mipsV:
 672 *vr4100:
 673 *vr5000:
 674 *r3900:
 675 {
 676   address_word offset = EXTEND16 (OFFSET) << 2;
 677   check_branch_bug ();
 678   if ((signed_word) GPR[RS] < 0)
 679     {
 680       mark_branch_bug (NIA+offset);
 681       DELAY_SLOT (NIA + offset);
 682     }
 683 }
 684
 685
 686
 687 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 688 "bltzal r<RS>, <OFFSET>"
 689 *mipsI:
 690 *mipsII:
 691 *mipsIII:
 692 *mipsIV:
 693 *mipsV:
 694 *vr4100:
 695 *vr5000:
 696 *r3900:
 697 {
 698   address_word offset = EXTEND16 (OFFSET) << 2;
 699   check_branch_bug ();
 700   RA = (CIA + 8);
 701   /* NOTE: The branch occurs AFTER the next instruction has been
 702      executed */
 703   if ((signed_word) GPR[RS] < 0)
 704     {
 705       mark_branch_bug (NIA+offset);
 706       DELAY_SLOT (NIA + offset);
 707     }
 708 }
 709
 710
 711
 712 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 713 "bltzall r<RS>, <OFFSET>"
 714 *mipsII:
 715 *mipsIII:
 716 *mipsIV:
 717 *mipsV:
 718 *vr4100:
 719 *vr5000:
 720 *r3900:
 721 {
 722   address_word offset = EXTEND16 (OFFSET) << 2;
 723   check_branch_bug ();
 724   RA = (CIA + 8);
 725   if ((signed_word) GPR[RS] < 0)
 726     {
 727       mark_branch_bug (NIA+offset);
 728       DELAY_SLOT (NIA + offset);
 729     }
 730   else
 731     NULLIFY_NEXT_INSTRUCTION ();
 732 }
 733
 734
 735
 736 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 737 "bltzl r<RS>, <OFFSET>"
 738 *mipsII:
 739 *mipsIII:
 740 *mipsIV:
 741 *mipsV:
 742 *vr4100:
 743 *vr5000:
 744 *r3900:
 745 {
 746   address_word offset = EXTEND16 (OFFSET) << 2;
 747   check_branch_bug ();
 748   /* NOTE: The branch occurs AFTER the next instruction has been
 749      executed */
 750   if ((signed_word) GPR[RS] < 0)
 751     {
 752       mark_branch_bug (NIA+offset);
 753       DELAY_SLOT (NIA + offset);
 754     }
 755   else
 756     NULLIFY_NEXT_INSTRUCTION ();
 757 }
 758
 759
 760
 761 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 762 "bne r<RS>, r<RT>, <OFFSET>"
 763 *mipsI:
 764 *mipsII:
 765 *mipsIII:
 766 *mipsIV:
 767 *mipsV:
 768 *vr4100:
 769 *vr5000:
 770 *r3900:
 771 {
 772   address_word offset = EXTEND16 (OFFSET) << 2;
 773   check_branch_bug ();
 774   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 775     {
 776       mark_branch_bug (NIA+offset);
 777       DELAY_SLOT (NIA + offset);
 778     }
 779 }
 780
 781
 782
 783 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 784 "bnel r<RS>, r<RT>, <OFFSET>"
 785 *mipsII:
 786 *mipsIII:
 787 *mipsIV:
 788 *mipsV:
 789 *vr4100:
 790 *vr5000:
 791 *r3900:
 792 {
 793   address_word offset = EXTEND16 (OFFSET) << 2;
 794   check_branch_bug ();
 795   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 796     {
 797       mark_branch_bug (NIA+offset);
 798       DELAY_SLOT (NIA + offset);
 799     }
 800   else
 801     NULLIFY_NEXT_INSTRUCTION ();
 802 }
 803
 804
 805
 806 000000,20.CODE,001101:SPECIAL:32::BREAK
 807 "break <CODE>"
 808 *mipsI:
 809 *mipsII:
 810 *mipsIII:
 811 *mipsIV:
 812 *mipsV:
 813 *vr4100:
 814 *vr5000:
 815 *r3900:
 816 {
 817   /* Check for some break instruction which are reserved for use by the simulator.  */
 818   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 819   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 820       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 821     {
 822       sim_engine_halt (SD, CPU, NULL, cia,
 823                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 824     }
 825   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 826            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 827     {
 828       if (STATE & simDELAYSLOT)
 829         PC = cia - 4; /* reference the branch instruction */
 830       else
 831         PC = cia;
 832       SignalException(BreakPoint, instruction_0);
 833     }
 834
 835   else
 836     {
 837       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 838          the exception. */
 839       SignalException(BreakPoint, instruction_0);
 840     }
 841 }
 842
 843
 844
 845 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 846 "dadd r<RD>, r<RS>, r<RT>"
 847 *mipsIII:
 848 *mipsIV:
 849 *mipsV:
 850 *vr4100:
 851 *vr5000:
 852 {
 853   check_u64 (SD_, instruction_0);
 854   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 855   {
 856     ALU64_BEGIN (GPR[RS]);
 857     ALU64_ADD (GPR[RT]);
 858     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
 859   }
 860   TRACE_ALU_RESULT (GPR[RD]);
 861 }
 862
 863
 864
 865 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 866 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 867 *mipsIII:
 868 *mipsIV:
 869 *mipsV:
 870 *vr4100:
 871 *vr5000:
 872 {
 873   check_u64 (SD_, instruction_0);
 874   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 875   {
 876     ALU64_BEGIN (GPR[RS]);
 877     ALU64_ADD (EXTEND16 (IMMEDIATE));
 878     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
 879   }
 880   TRACE_ALU_RESULT (GPR[RT]);
 881 }
 882
 883
 884
 885 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
 886 {
 887   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 888   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
 889   TRACE_ALU_RESULT (GPR[rt]);
 890 }
 891
 892 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 893 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
 894 *mipsIII:
 895 *mipsIV:
 896 *mipsV:
 897 *vr4100:
 898 *vr5000:
 899 {
 900   check_u64 (SD_, instruction_0);
 901   do_daddiu (SD_, RS, RT, IMMEDIATE);
 902 }
 903
 904
 905
 906 :function:::void:do_daddu:int rs, int rt, int rd
 907 {
 908   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 909   GPR[rd] = GPR[rs] + GPR[rt];
 910   TRACE_ALU_RESULT (GPR[rd]);
 911 }
 912
 913 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 914 "daddu r<RD>, r<RS>, r<RT>"
 915 *mipsIII:
 916 *mipsIV:
 917 *mipsV:
 918 *vr4100:
 919 *vr5000:
 920 {
 921   check_u64 (SD_, instruction_0);
 922   do_daddu (SD_, RS, RT, RD);
 923 }
 924
 925
 926
 927 :function:::void:do_ddiv:int rs, int rt
 928 {
 929   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 930   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 931   {
 932     signed64 n = GPR[rs];
 933     signed64 d = GPR[rt];
 934     signed64 hi;
 935     signed64 lo;
 936     if (d == 0)
 937       {
 938         lo = SIGNED64 (0x8000000000000000);
 939         hi = 0;
 940       }
 941     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 942       {
 943         lo = SIGNED64 (0x8000000000000000);
 944         hi = 0;
 945       }
 946     else
 947       {
 948         lo = (n / d);
 949         hi = (n % d);
 950       }
 951     HI = hi;
 952     LO = lo;
 953   }
 954   TRACE_ALU_RESULT2 (HI, LO);
 955 }
 956
 957 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
 958 "ddiv r<RS>, r<RT>"
 959 *mipsIII:
 960 *mipsIV:
 961 *mipsV:
 962 *vr4100:
 963 *vr5000:
 964 {
 965   check_u64 (SD_, instruction_0);
 966   do_ddiv (SD_, RS, RT);
 967 }
 968
 969
 970
 971 :function:::void:do_ddivu:int rs, int rt
 972 {
 973   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 974   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 975   {
 976     unsigned64 n = GPR[rs];
 977     unsigned64 d = GPR[rt];
 978     unsigned64 hi;
 979     unsigned64 lo;
 980     if (d == 0)
 981       {
 982         lo = SIGNED64 (0x8000000000000000);
 983         hi = 0;
 984       }
 985     else
 986       {
 987         lo = (n / d);
 988         hi = (n % d);
 989       }
 990     HI = hi;
 991     LO = lo;
 992   }
 993   TRACE_ALU_RESULT2 (HI, LO);
 994 }
 995
 996 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 997 "ddivu r<RS>, r<RT>"
 998 *mipsIII:
 999 *mipsIV:
1000 *mipsV:
1001 *vr4100:
1002 *vr5000:
1003 {
1004   check_u64 (SD_, instruction_0);
1005   do_ddivu (SD_, RS, RT);
1006 }
1007
1008
1009
1010 :function:::void:do_div:int rs, int rt
1011 {
1012   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1013   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1014   {
1015     signed32 n = GPR[rs];
1016     signed32 d = GPR[rt];
1017     if (d == 0)
1018       {
1019         LO = EXTEND32 (0x80000000);
1020         HI = EXTEND32 (0);
1021       }
1022     else if (n == SIGNED32 (0x80000000) && d == -1)
1023       {
1024         LO = EXTEND32 (0x80000000);
1025         HI = EXTEND32 (0);
1026       }
1027     else
1028       {
1029         LO = EXTEND32 (n / d);
1030         HI = EXTEND32 (n % d);
1031       }
1032   }
1033   TRACE_ALU_RESULT2 (HI, LO);
1034 }
1035
1036 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1037 "div r<RS>, r<RT>"
1038 *mipsI:
1039 *mipsII:
1040 *mipsIII:
1041 *mipsIV:
1042 *mipsV:
1043 *vr4100:
1044 *vr5000:
1045 *r3900:
1046 {
1047   do_div (SD_, RS, RT);
1048 }
1049
1050
1051
1052 :function:::void:do_divu:int rs, int rt
1053 {
1054   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1055   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1056   {
1057     unsigned32 n = GPR[rs];
1058     unsigned32 d = GPR[rt];
1059     if (d == 0)
1060       {
1061         LO = EXTEND32 (0x80000000);
1062         HI = EXTEND32 (0);
1063       }
1064     else
1065       {
1066         LO = EXTEND32 (n / d);
1067         HI = EXTEND32 (n % d);
1068       }
1069   }
1070   TRACE_ALU_RESULT2 (HI, LO);
1071 }
1072
1073 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1074 "divu r<RS>, r<RT>"
1075 *mipsI:
1076 *mipsII:
1077 *mipsIII:
1078 *mipsIV:
1079 *mipsV:
1080 *vr4100:
1081 *vr5000:
1082 *r3900:
1083 {
1084   do_divu (SD_, RS, RT);
1085 }
1086
1087
1088
1089 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1090 {
1091   unsigned64 lo;
1092   unsigned64 hi;
1093   unsigned64 m00;
1094   unsigned64 m01;
1095   unsigned64 m10;
1096   unsigned64 m11;
1097   unsigned64 mid;
1098   int sign;
1099   unsigned64 op1 = GPR[rs];
1100   unsigned64 op2 = GPR[rt];
1101   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1102   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1103   /* make signed multiply unsigned */
1104   sign = 0;
1105   if (signed_p)
1106     {
1107       if (op1 < 0)
1108         {
1109           op1 = - op1;
1110           ++sign;
1111         }
1112       if (op2 < 0)
1113         {
1114           op2 = - op2;
1115           ++sign;
1116         }
1117     }
1118   /* multiply out the 4 sub products */
1119   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1120   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1121   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1122   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1123   /* add the products */
1124   mid = ((unsigned64) VH4_8 (m00)
1125          + (unsigned64) VL4_8 (m10)
1126          + (unsigned64) VL4_8 (m01));
1127   lo = U8_4 (mid, m00);
1128   hi = (m11
1129         + (unsigned64) VH4_8 (mid)
1130         + (unsigned64) VH4_8 (m01)
1131         + (unsigned64) VH4_8 (m10));
1132   /* fix the sign */
1133   if (sign & 1)
1134     {
1135       lo = -lo;
1136       if (lo == 0)
1137         hi = -hi;
1138       else
1139         hi = -hi - 1;
1140     }
1141   /* save the result HI/LO (and a gpr) */
1142   LO = lo;
1143   HI = hi;
1144   if (rd != 0)
1145     GPR[rd] = lo;
1146   TRACE_ALU_RESULT2 (HI, LO);
1147 }
1148
1149 :function:::void:do_dmult:int rs, int rt, int rd
1150 {
1151   do_dmultx (SD_, rs, rt, rd, 1);
1152 }
1153
1154 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1155 "dmult r<RS>, r<RT>"
1156 *mipsIII:
1157 *mipsIV:
1158 *mipsV:
1159 *vr4100:
1160 {
1161   check_u64 (SD_, instruction_0);
1162   do_dmult (SD_, RS, RT, 0);
1163 }
1164
1165 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1166 "dmult r<RS>, r<RT>":RD == 0
1167 "dmult r<RD>, r<RS>, r<RT>"
1168 *vr5000:
1169 {
1170   check_u64 (SD_, instruction_0);
1171   do_dmult (SD_, RS, RT, RD);
1172 }
1173
1174
1175
1176 :function:::void:do_dmultu:int rs, int rt, int rd
1177 {
1178   do_dmultx (SD_, rs, rt, rd, 0);
1179 }
1180
1181 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1182 "dmultu r<RS>, r<RT>"
1183 *mipsIII:
1184 *mipsIV:
1185 *mipsV:
1186 *vr4100:
1187 {
1188   check_u64 (SD_, instruction_0);
1189   do_dmultu (SD_, RS, RT, 0);
1190 }
1191
1192 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1193 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1194 "dmultu r<RS>, r<RT>"
1195 *vr5000:
1196 {
1197   check_u64 (SD_, instruction_0);
1198   do_dmultu (SD_, RS, RT, RD);
1199 }
1200
1201 :function:::void:do_dsll:int rt, int rd, int shift
1202 {
1203   TRACE_ALU_INPUT2 (GPR[rt], shift);
1204   GPR[rd] = GPR[rt] << shift;
1205   TRACE_ALU_RESULT (GPR[rd]);
1206 }
1207
1208 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1209 "dsll r<RD>, r<RT>, <SHIFT>"
1210 *mipsIII:
1211 *mipsIV:
1212 *mipsV:
1213 *vr4100:
1214 *vr5000:
1215 {
1216   check_u64 (SD_, instruction_0);
1217   do_dsll (SD_, RT, RD, SHIFT);
1218 }
1219
1220
1221 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1222 "dsll32 r<RD>, r<RT>, <SHIFT>"
1223 *mipsIII:
1224 *mipsIV:
1225 *mipsV:
1226 *vr4100:
1227 *vr5000:
1228 {
1229   int s = 32 + SHIFT;
1230   check_u64 (SD_, instruction_0);
1231   TRACE_ALU_INPUT2 (GPR[RT], s);
1232   GPR[RD] = GPR[RT] << s;
1233   TRACE_ALU_RESULT (GPR[RD]);
1234 }
1235
1236 :function:::void:do_dsllv:int rs, int rt, int rd
1237 {
1238   int s = MASKED64 (GPR[rs], 5, 0);
1239   TRACE_ALU_INPUT2 (GPR[rt], s);
1240   GPR[rd] = GPR[rt] << s;
1241   TRACE_ALU_RESULT (GPR[rd]);
1242 }
1243
1244 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1245 "dsllv r<RD>, r<RT>, r<RS>"
1246 *mipsIII:
1247 *mipsIV:
1248 *mipsV:
1249 *vr4100:
1250 *vr5000:
1251 {
1252   check_u64 (SD_, instruction_0);
1253   do_dsllv (SD_, RS, RT, RD);
1254 }
1255
1256 :function:::void:do_dsra:int rt, int rd, int shift
1257 {
1258   TRACE_ALU_INPUT2 (GPR[rt], shift);
1259   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1260   TRACE_ALU_RESULT (GPR[rd]);
1261 }
1262
1263
1264 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1265 "dsra r<RD>, r<RT>, <SHIFT>"
1266 *mipsIII:
1267 *mipsIV:
1268 *mipsV:
1269 *vr4100:
1270 *vr5000:
1271 {
1272   check_u64 (SD_, instruction_0);
1273   do_dsra (SD_, RT, RD, SHIFT);
1274 }
1275
1276
1277 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1278 "dsra32 r<RD>, r<RT>, <SHIFT>"
1279 *mipsIII:
1280 *mipsIV:
1281 *mipsV:
1282 *vr4100:
1283 *vr5000:
1284 {
1285   int s = 32 + SHIFT;
1286   check_u64 (SD_, instruction_0);
1287   TRACE_ALU_INPUT2 (GPR[RT], s);
1288   GPR[RD] = ((signed64) GPR[RT]) >> s;
1289   TRACE_ALU_RESULT (GPR[RD]);
1290 }
1291
1292
1293 :function:::void:do_dsrav:int rs, int rt, int rd
1294 {
1295   int s = MASKED64 (GPR[rs], 5, 0);
1296   TRACE_ALU_INPUT2 (GPR[rt], s);
1297   GPR[rd] = ((signed64) GPR[rt]) >> s;
1298   TRACE_ALU_RESULT (GPR[rd]);
1299 }
1300
1301 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1302 "dsrav r<RD>, r<RT>, r<RS>"
1303 *mipsIII:
1304 *mipsIV:
1305 *mipsV:
1306 *vr4100:
1307 *vr5000:
1308 {
1309   check_u64 (SD_, instruction_0);
1310   do_dsrav (SD_, RS, RT, RD);
1311 }
1312
1313 :function:::void:do_dsrl:int rt, int rd, int shift
1314 {
1315   TRACE_ALU_INPUT2 (GPR[rt], shift);
1316   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1317   TRACE_ALU_RESULT (GPR[rd]);
1318 }
1319
1320
1321 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1322 "dsrl r<RD>, r<RT>, <SHIFT>"
1323 *mipsIII:
1324 *mipsIV:
1325 *mipsV:
1326 *vr4100:
1327 *vr5000:
1328 {
1329   check_u64 (SD_, instruction_0);
1330   do_dsrl (SD_, RT, RD, SHIFT);
1331 }
1332
1333
1334 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1335 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1336 *mipsIII:
1337 *mipsIV:
1338 *mipsV:
1339 *vr4100:
1340 *vr5000:
1341 {
1342   int s = 32 + SHIFT;
1343   check_u64 (SD_, instruction_0);
1344   TRACE_ALU_INPUT2 (GPR[RT], s);
1345   GPR[RD] = (unsigned64) GPR[RT] >> s;
1346   TRACE_ALU_RESULT (GPR[RD]);
1347 }
1348
1349
1350 :function:::void:do_dsrlv:int rs, int rt, int rd
1351 {
1352   int s = MASKED64 (GPR[rs], 5, 0);
1353   TRACE_ALU_INPUT2 (GPR[rt], s);
1354   GPR[rd] = (unsigned64) GPR[rt] >> s;
1355   TRACE_ALU_RESULT (GPR[rd]);
1356 }
1357
1358
1359
1360 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1361 "dsrlv r<RD>, r<RT>, r<RS>"
1362 *mipsIII:
1363 *mipsIV:
1364 *mipsV:
1365 *vr4100:
1366 *vr5000:
1367 {
1368   check_u64 (SD_, instruction_0);
1369   do_dsrlv (SD_, RS, RT, RD);
1370 }
1371
1372
1373 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1374 "dsub r<RD>, r<RS>, r<RT>"
1375 *mipsIII:
1376 *mipsIV:
1377 *mipsV:
1378 *vr4100:
1379 *vr5000:
1380 {
1381   check_u64 (SD_, instruction_0);
1382   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1383   {
1384     ALU64_BEGIN (GPR[RS]);
1385     ALU64_SUB (GPR[RT]);
1386     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1387   }
1388   TRACE_ALU_RESULT (GPR[RD]);
1389 }
1390
1391
1392 :function:::void:do_dsubu:int rs, int rt, int rd
1393 {
1394   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1395   GPR[rd] = GPR[rs] - GPR[rt];
1396   TRACE_ALU_RESULT (GPR[rd]);
1397 }
1398
1399 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1400 "dsubu r<RD>, r<RS>, r<RT>"
1401 *mipsIII:
1402 *mipsIV:
1403 *mipsV:
1404 *vr4100:
1405 *vr5000:
1406 {
1407   check_u64 (SD_, instruction_0);
1408   do_dsubu (SD_, RS, RT, RD);
1409 }
1410
1411
1412 000010,26.INSTR_INDEX:NORMAL:32::J
1413 "j <INSTR_INDEX>"
1414 *mipsI:
1415 *mipsII:
1416 *mipsIII:
1417 *mipsIV:
1418 *mipsV:
1419 *vr4100:
1420 *vr5000:
1421 *r3900:
1422 {
1423   /* NOTE: The region used is that of the delay slot NIA and NOT the
1424      current instruction */
1425   address_word region = (NIA & MASK (63, 28));
1426   DELAY_SLOT (region | (INSTR_INDEX << 2));
1427 }
1428
1429
1430 000011,26.INSTR_INDEX:NORMAL:32::JAL
1431 "jal <INSTR_INDEX>"
1432 *mipsI:
1433 *mipsII:
1434 *mipsIII:
1435 *mipsIV:
1436 *mipsV:
1437 *vr4100:
1438 *vr5000:
1439 *r3900:
1440 {
1441   /* NOTE: The region used is that of the delay slot and NOT the
1442      current instruction */
1443   address_word region = (NIA & MASK (63, 28));
1444   GPR[31] = CIA + 8;
1445   DELAY_SLOT (region | (INSTR_INDEX << 2));
1446 }
1447
1448 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1449 "jalr r<RS>":RD == 31
1450 "jalr r<RD>, r<RS>"
1451 *mipsI:
1452 *mipsII:
1453 *mipsIII:
1454 *mipsIV:
1455 *mipsV:
1456 *vr4100:
1457 *vr5000:
1458 *r3900:
1459 {
1460   address_word temp = GPR[RS];
1461   GPR[RD] = CIA + 8;
1462   DELAY_SLOT (temp);
1463 }
1464
1465
1466 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1467 "jr r<RS>"
1468 *mipsI:
1469 *mipsII:
1470 *mipsIII:
1471 *mipsIV:
1472 *mipsV:
1473 *vr4100:
1474 *vr5000:
1475 *r3900:
1476 {
1477   DELAY_SLOT (GPR[RS]);
1478 }
1479
1480
1481 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1482 {
1483   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1484   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1485   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1486   unsigned int byte;
1487   address_word paddr;
1488   int uncached;
1489   unsigned64 memval;
1490   address_word vaddr;
1491
1492   vaddr = loadstore_ea (SD_, base, offset);
1493   if ((vaddr & access) != 0)
1494     {
1495       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1496     }
1497   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1498   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1499   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1500   byte = ((vaddr & mask) ^ bigendiancpu);
1501   return (memval >> (8 * byte));
1502 }
1503
1504 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1505 {
1506   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1507   address_word reverseendian = (ReverseEndian ? -1 : 0);
1508   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1509   unsigned int byte;
1510   unsigned int word;
1511   address_word paddr;
1512   int uncached;
1513   unsigned64 memval;
1514   address_word vaddr;
1515   int nr_lhs_bits;
1516   int nr_rhs_bits;
1517   unsigned_word lhs_mask;
1518   unsigned_word temp;
1519
1520   vaddr = loadstore_ea (SD_, base, offset);
1521   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1522   paddr = (paddr ^ (reverseendian & mask));
1523   if (BigEndianMem == 0)
1524     paddr = paddr & ~access;
1525
1526   /* compute where within the word/mem we are */
1527   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1528   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1529   nr_lhs_bits = 8 * byte + 8;
1530   nr_rhs_bits = 8 * access - 8 * byte;
1531   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1532
1533   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1534            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1535            (long) ((unsigned64) paddr >> 32), (long) paddr,
1536            word, byte, nr_lhs_bits, nr_rhs_bits); */
1537
1538   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1539   if (word == 0)
1540     {
1541       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1542       temp = (memval << nr_rhs_bits);
1543     }
1544   else
1545     {
1546       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1547       temp = (memval >> nr_lhs_bits);
1548     }
1549   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1550   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1551
1552   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1553            (long) ((unsigned64) memval >> 32), (long) memval,
1554            (long) ((unsigned64) temp >> 32), (long) temp,
1555            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1556            (long) (rt >> 32), (long) rt); */
1557   return rt;
1558 }
1559
1560 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1561 {
1562   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1563   address_word reverseendian = (ReverseEndian ? -1 : 0);
1564   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1565   unsigned int byte;
1566   address_word paddr;
1567   int uncached;
1568   unsigned64 memval;
1569   address_word vaddr;
1570
1571   vaddr = loadstore_ea (SD_, base, offset);
1572   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1573   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1574   paddr = (paddr ^ (reverseendian & mask));
1575   if (BigEndianMem != 0)
1576     paddr = paddr & ~access;
1577   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1578   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1579   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1580   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1581      (long) paddr, byte, (long) paddr, (long) memval); */
1582   {
1583     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1584     rt &= ~screen;
1585     rt |= (memval >> (8 * byte)) & screen;
1586   }
1587   return rt;
1588 }
1589
1590
1591 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1592 "lb r<RT>, <OFFSET>(r<BASE>)"
1593 *mipsI:
1594 *mipsII:
1595 *mipsIII:
1596 *mipsIV:
1597 *mipsV:
1598 *vr4100:
1599 *vr5000:
1600 *r3900:
1601 {
1602   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1603 }
1604
1605
1606 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1607 "lbu r<RT>, <OFFSET>(r<BASE>)"
1608 *mipsI:
1609 *mipsII:
1610 *mipsIII:
1611 *mipsIV:
1612 *mipsV:
1613 *vr4100:
1614 *vr5000:
1615 *r3900:
1616 {
1617   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1618 }
1619
1620
1621 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1622 "ld r<RT>, <OFFSET>(r<BASE>)"
1623 *mipsIII:
1624 *mipsIV:
1625 *mipsV:
1626 *vr4100:
1627 *vr5000:
1628 {
1629   check_u64 (SD_, instruction_0);
1630   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1631 }
1632
1633
1634 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1635 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1636 *mipsII:
1637 *mipsIII:
1638 *mipsIV:
1639 *mipsV:
1640 *vr4100:
1641 *vr5000:
1642 *r3900:
1643 {
1644   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1645 }
1646
1647
1648
1649
1650 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1651 "ldl r<RT>, <OFFSET>(r<BASE>)"
1652 *mipsIII:
1653 *mipsIV:
1654 *mipsV:
1655 *vr4100:
1656 *vr5000:
1657 {
1658   check_u64 (SD_, instruction_0);
1659   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1660 }
1661
1662
1663 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1664 "ldr r<RT>, <OFFSET>(r<BASE>)"
1665 *mipsIII:
1666 *mipsIV:
1667 *mipsV:
1668 *vr4100:
1669 *vr5000:
1670 {
1671   check_u64 (SD_, instruction_0);
1672   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1673 }
1674
1675
1676 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1677 "lh r<RT>, <OFFSET>(r<BASE>)"
1678 *mipsI:
1679 *mipsII:
1680 *mipsIII:
1681 *mipsIV:
1682 *mipsV:
1683 *vr4100:
1684 *vr5000:
1685 *r3900:
1686 {
1687   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1688 }
1689
1690
1691 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1692 "lhu r<RT>, <OFFSET>(r<BASE>)"
1693 *mipsI:
1694 *mipsII:
1695 *mipsIII:
1696 *mipsIV:
1697 *mipsV:
1698 *vr4100:
1699 *vr5000:
1700 *r3900:
1701 {
1702   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1703 }
1704
1705
1706 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1707 "ll r<RT>, <OFFSET>(r<BASE>)"
1708 *mipsII:
1709 *mipsIII:
1710 *mipsIV:
1711 *mipsV:
1712 *vr4100:
1713 *vr5000:
1714 {
1715   address_word base = GPR[BASE];
1716   address_word offset = EXTEND16 (OFFSET);
1717   {
1718     address_word vaddr = loadstore_ea (SD_, base, offset);
1719     address_word paddr;
1720     int uncached;
1721     if ((vaddr & 3) != 0)
1722       {
1723         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1724       }
1725     else
1726       {
1727         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1728           {
1729             unsigned64 memval = 0;
1730             unsigned64 memval1 = 0;
1731             unsigned64 mask = 0x7;
1732             unsigned int shift = 2;
1733             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1734             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1735             unsigned int byte;
1736             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1737             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1738             byte = ((vaddr & mask) ^ (bigend << shift));
1739             GPR[RT] = EXTEND32 (memval >> (8 * byte));
1740             LLBIT = 1;
1741           }
1742       }
1743   }
1744 }
1745
1746
1747 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1748 "lld r<RT>, <OFFSET>(r<BASE>)"
1749 *mipsIII:
1750 *mipsIV:
1751 *mipsV:
1752 *vr4100:
1753 *vr5000:
1754 {
1755   address_word base = GPR[BASE];
1756   address_word offset = EXTEND16 (OFFSET);
1757   check_u64 (SD_, instruction_0);
1758   {
1759     address_word vaddr = loadstore_ea (SD_, base, offset);
1760     address_word paddr;
1761     int uncached;
1762     if ((vaddr & 7) != 0)
1763       {
1764         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1765       }
1766     else
1767       {
1768         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1769           {
1770             unsigned64 memval = 0;
1771             unsigned64 memval1 = 0;
1772             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1773             GPR[RT] = memval;
1774             LLBIT = 1;
1775           }
1776       }
1777   }
1778 }
1779
1780
1781 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1782 "lui r<RT>, <IMMEDIATE>"
1783 *mipsI:
1784 *mipsII:
1785 *mipsIII:
1786 *mipsIV:
1787 *mipsV:
1788 *vr4100:
1789 *vr5000:
1790 *r3900:
1791 {
1792   TRACE_ALU_INPUT1 (IMMEDIATE);
1793   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1794   TRACE_ALU_RESULT (GPR[RT]);
1795 }
1796
1797
1798 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1799 "lw r<RT>, <OFFSET>(r<BASE>)"
1800 *mipsI:
1801 *mipsII:
1802 *mipsIII:
1803 *mipsIV:
1804 *mipsV:
1805 *vr4100:
1806 *vr5000:
1807 *r3900:
1808 {
1809   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1810 }
1811
1812
1813 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1814 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1815 *mipsI:
1816 *mipsII:
1817 *mipsIII:
1818 *mipsIV:
1819 *mipsV:
1820 *vr4100:
1821 *vr5000:
1822 *r3900:
1823 {
1824   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1825 }
1826
1827
1828 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1829 "lwl r<RT>, <OFFSET>(r<BASE>)"
1830 *mipsI:
1831 *mipsII:
1832 *mipsIII:
1833 *mipsIV:
1834 *mipsV:
1835 *vr4100:
1836 *vr5000:
1837 *r3900:
1838 {
1839   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1840 }
1841
1842
1843 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1844 "lwr r<RT>, <OFFSET>(r<BASE>)"
1845 *mipsI:
1846 *mipsII:
1847 *mipsIII:
1848 *mipsIV:
1849 *mipsV:
1850 *vr4100:
1851 *vr5000:
1852 *r3900:
1853 {
1854   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1855 }
1856
1857
1858 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
1859 "lwu r<RT>, <OFFSET>(r<BASE>)"
1860 *mipsIII:
1861 *mipsIV:
1862 *mipsV:
1863 *vr4100:
1864 *vr5000:
1865 {
1866   check_u64 (SD_, instruction_0);
1867   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1868 }
1869
1870
1871 :function:::void:do_mfhi:int rd
1872 {
1873   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1874   TRACE_ALU_INPUT1 (HI);
1875   GPR[rd] = HI;
1876   TRACE_ALU_RESULT (GPR[rd]);
1877 }
1878
1879 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1880 "mfhi r<RD>"
1881 *mipsI:
1882 *mipsII:
1883 *mipsIII:
1884 *mipsIV:
1885 *mipsV:
1886 *vr4100:
1887 *vr5000:
1888 *r3900:
1889 {
1890   do_mfhi (SD_, RD);
1891 }
1892
1893
1894
1895 :function:::void:do_mflo:int rd
1896 {
1897   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1898   TRACE_ALU_INPUT1 (LO);
1899   GPR[rd] = LO;
1900   TRACE_ALU_RESULT (GPR[rd]);
1901 }
1902
1903 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1904 "mflo r<RD>"
1905 *mipsI:
1906 *mipsII:
1907 *mipsIII:
1908 *mipsIV:
1909 *mipsV:
1910 *vr4100:
1911 *vr5000:
1912 *r3900:
1913 {
1914   do_mflo (SD_, RD);
1915 }
1916
1917
1918
1919 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
1920 "movn r<RD>, r<RS>, r<RT>"
1921 *mipsIV:
1922 *mipsV:
1923 *vr5000:
1924 {
1925   if (GPR[RT] != 0)
1926     GPR[RD] = GPR[RS];
1927 }
1928
1929
1930
1931 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
1932 "movz r<RD>, r<RS>, r<RT>"
1933 *mipsIV:
1934 *mipsV:
1935 *vr5000:
1936 {
1937   if (GPR[RT] == 0)
1938     GPR[RD] = GPR[RS];
1939 }
1940
1941
1942
1943 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1944 "mthi r<RS>"
1945 *mipsI:
1946 *mipsII:
1947 *mipsIII:
1948 *mipsIV:
1949 *mipsV:
1950 *vr4100:
1951 *vr5000:
1952 *r3900:
1953 {
1954   check_mt_hilo (SD_, HIHISTORY);
1955   HI = GPR[RS];
1956 }
1957
1958
1959
1960 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
1961 "mtlo r<RS>"
1962 *mipsI:
1963 *mipsII:
1964 *mipsIII:
1965 *mipsIV:
1966 *mipsV:
1967 *vr4100:
1968 *vr5000:
1969 *r3900:
1970 {
1971   check_mt_hilo (SD_, LOHISTORY);
1972   LO = GPR[RS];
1973 }
1974
1975
1976
1977 :function:::void:do_mult:int rs, int rt, int rd
1978 {
1979   signed64 prod;
1980   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1981   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1982   prod = (((signed64)(signed32) GPR[rs])
1983           * ((signed64)(signed32) GPR[rt]));
1984   LO = EXTEND32 (VL4_8 (prod));
1985   HI = EXTEND32 (VH4_8 (prod));
1986   if (rd != 0)
1987     GPR[rd] = LO;
1988   TRACE_ALU_RESULT2 (HI, LO);
1989 }
1990
1991 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
1992 "mult r<RS>, r<RT>"
1993 *mipsI:
1994 *mipsII:
1995 *mipsIII:
1996 *mipsIV:
1997 *mipsV:
1998 *vr4100:
1999 {
2000   do_mult (SD_, RS, RT, 0);
2001 }
2002
2003
2004 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2005 "mult r<RS>, r<RT>":RD == 0
2006 "mult r<RD>, r<RS>, r<RT>"
2007 *vr5000:
2008 *r3900:
2009 {
2010   do_mult (SD_, RS, RT, RD);
2011 }
2012
2013
2014 :function:::void:do_multu:int rs, int rt, int rd
2015 {
2016   unsigned64 prod;
2017   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2018   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2019   prod = (((unsigned64)(unsigned32) GPR[rs])
2020           * ((unsigned64)(unsigned32) GPR[rt]));
2021   LO = EXTEND32 (VL4_8 (prod));
2022   HI = EXTEND32 (VH4_8 (prod));
2023   if (rd != 0)
2024     GPR[rd] = LO;
2025   TRACE_ALU_RESULT2 (HI, LO);
2026 }
2027
2028 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2029 "multu r<RS>, r<RT>"
2030 *mipsI:
2031 *mipsII:
2032 *mipsIII:
2033 *mipsIV:
2034 *mipsV:
2035 *vr4100:
2036 {
2037   do_multu (SD_, RS, RT, 0);
2038 }
2039
2040 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2041 "multu r<RS>, r<RT>":RD == 0
2042 "multu r<RD>, r<RS>, r<RT>"
2043 *vr5000:
2044 *r3900:
2045 {
2046   do_multu (SD_, RS, RT, RD);
2047 }
2048
2049
2050 :function:::void:do_nor:int rs, int rt, int rd
2051 {
2052   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2053   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2054   TRACE_ALU_RESULT (GPR[rd]);
2055 }
2056
2057 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2058 "nor r<RD>, r<RS>, r<RT>"
2059 *mipsI:
2060 *mipsII:
2061 *mipsIII:
2062 *mipsIV:
2063 *mipsV:
2064 *vr4100:
2065 *vr5000:
2066 *r3900:
2067 {
2068   do_nor (SD_, RS, RT, RD);
2069 }
2070
2071
2072 :function:::void:do_or:int rs, int rt, int rd
2073 {
2074   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2075   GPR[rd] = (GPR[rs] | GPR[rt]);
2076   TRACE_ALU_RESULT (GPR[rd]);
2077 }
2078
2079 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2080 "or r<RD>, r<RS>, r<RT>"
2081 *mipsI:
2082 *mipsII:
2083 *mipsIII:
2084 *mipsIV:
2085 *mipsV:
2086 *vr4100:
2087 *vr5000:
2088 *r3900:
2089 {
2090   do_or (SD_, RS, RT, RD);
2091 }
2092
2093
2094
2095 :function:::void:do_ori:int rs, int rt, unsigned immediate
2096 {
2097   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2098   GPR[rt] = (GPR[rs] | immediate);
2099   TRACE_ALU_RESULT (GPR[rt]);
2100 }
2101
2102 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2103 "ori r<RT>, r<RS>, <IMMEDIATE>"
2104 *mipsI:
2105 *mipsII:
2106 *mipsIII:
2107 *mipsIV:
2108 *mipsV:
2109 *vr4100:
2110 *vr5000:
2111 *r3900:
2112 {
2113   do_ori (SD_, RS, RT, IMMEDIATE);
2114 }
2115
2116
2117 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2118 "pref <HINT>, <OFFSET>(r<BASE>)"
2119 *mipsIV:
2120 *mipsV:
2121 *vr5000:
2122 {
2123   address_word base = GPR[BASE];
2124   address_word offset = EXTEND16 (OFFSET);
2125   {
2126     address_word vaddr = loadstore_ea (SD_, base, offset);
2127     address_word paddr;
2128     int uncached;
2129     {
2130       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2131         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2132     }
2133   }
2134 }
2135
2136
2137 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2138 {
2139   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2140   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2141   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2142   unsigned int byte;
2143   address_word paddr;
2144   int uncached;
2145   unsigned64 memval;
2146   address_word vaddr;
2147
2148   vaddr = loadstore_ea (SD_, base, offset);
2149   if ((vaddr & access) != 0)
2150     {
2151       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2152     }
2153   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2154   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2155   byte = ((vaddr & mask) ^ bigendiancpu);
2156   memval = (word << (8 * byte));
2157   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2158 }
2159
2160 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2161 {
2162   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2163   address_word reverseendian = (ReverseEndian ? -1 : 0);
2164   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2165   unsigned int byte;
2166   unsigned int word;
2167   address_word paddr;
2168   int uncached;
2169   unsigned64 memval;
2170   address_word vaddr;
2171   int nr_lhs_bits;
2172   int nr_rhs_bits;
2173
2174   vaddr = loadstore_ea (SD_, base, offset);
2175   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2176   paddr = (paddr ^ (reverseendian & mask));
2177   if (BigEndianMem == 0)
2178     paddr = paddr & ~access;
2179
2180   /* compute where within the word/mem we are */
2181   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2182   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2183   nr_lhs_bits = 8 * byte + 8;
2184   nr_rhs_bits = 8 * access - 8 * byte;
2185   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2186   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2187            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2188            (long) ((unsigned64) paddr >> 32), (long) paddr,
2189            word, byte, nr_lhs_bits, nr_rhs_bits); */
2190
2191   if (word == 0)
2192     {
2193       memval = (rt >> nr_rhs_bits);
2194     }
2195   else
2196     {
2197       memval = (rt << nr_lhs_bits);
2198     }
2199   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2200            (long) ((unsigned64) rt >> 32), (long) rt,
2201            (long) ((unsigned64) memval >> 32), (long) memval); */
2202   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2203 }
2204
2205 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2206 {
2207   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2208   address_word reverseendian = (ReverseEndian ? -1 : 0);
2209   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2210   unsigned int byte;
2211   address_word paddr;
2212   int uncached;
2213   unsigned64 memval;
2214   address_word vaddr;
2215
2216   vaddr = loadstore_ea (SD_, base, offset);
2217   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2218   paddr = (paddr ^ (reverseendian & mask));
2219   if (BigEndianMem != 0)
2220     paddr &= ~access;
2221   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2222   memval = (rt << (byte * 8));
2223   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2224 }
2225
2226
2227 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2228 "sb r<RT>, <OFFSET>(r<BASE>)"
2229 *mipsI:
2230 *mipsII:
2231 *mipsIII:
2232 *mipsIV:
2233 *mipsV:
2234 *vr4100:
2235 *vr5000:
2236 *r3900:
2237 {
2238   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2239 }
2240
2241
2242 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2243 "sc r<RT>, <OFFSET>(r<BASE>)"
2244 *mipsII:
2245 *mipsIII:
2246 *mipsIV:
2247 *mipsV:
2248 *vr4100:
2249 *vr5000:
2250 {
2251   unsigned32 instruction = instruction_0;
2252   address_word base = GPR[BASE];
2253   address_word offset = EXTEND16 (OFFSET);
2254   {
2255     address_word vaddr = loadstore_ea (SD_, base, offset);
2256     address_word paddr;
2257     int uncached;
2258     if ((vaddr & 3) != 0)
2259       {
2260         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2261       }
2262     else
2263       {
2264         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2265           {
2266             unsigned64 memval = 0;
2267             unsigned64 memval1 = 0;
2268             unsigned64 mask = 0x7;
2269             unsigned int byte;
2270             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2271             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2272             memval = ((unsigned64) GPR[RT] << (8 * byte));
2273             if (LLBIT)
2274               {
2275                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2276               }
2277             GPR[RT] = LLBIT;
2278           }
2279       }
2280   }
2281 }
2282
2283
2284 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2285 "scd r<RT>, <OFFSET>(r<BASE>)"
2286 *mipsIII:
2287 *mipsIV:
2288 *mipsV:
2289 *vr4100:
2290 *vr5000:
2291 {
2292   address_word base = GPR[BASE];
2293   address_word offset = EXTEND16 (OFFSET);
2294   check_u64 (SD_, instruction_0);
2295   {
2296     address_word vaddr = loadstore_ea (SD_, base, offset);
2297     address_word paddr;
2298     int uncached;
2299     if ((vaddr & 7) != 0)
2300       {
2301         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2302       }
2303     else
2304       {
2305         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2306           {
2307             unsigned64 memval = 0;
2308             unsigned64 memval1 = 0;
2309             memval = GPR[RT];
2310             if (LLBIT)
2311               {
2312                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2313               }
2314             GPR[RT] = LLBIT;
2315           }
2316       }
2317   }
2318 }
2319
2320
2321 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2322 "sd r<RT>, <OFFSET>(r<BASE>)"
2323 *mipsIII:
2324 *mipsIV:
2325 *mipsV:
2326 *vr4100:
2327 *vr5000:
2328 {
2329   check_u64 (SD_, instruction_0);
2330   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2331 }
2332
2333
2334 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2335 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2336 *mipsII:
2337 *mipsIII:
2338 *mipsIV:
2339 *mipsV:
2340 *vr4100:
2341 *vr5000:
2342 {
2343   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2344 }
2345
2346
2347 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2348 "sdl r<RT>, <OFFSET>(r<BASE>)"
2349 *mipsIII:
2350 *mipsIV:
2351 *mipsV:
2352 *vr4100:
2353 *vr5000:
2354 {
2355   check_u64 (SD_, instruction_0);
2356   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2357 }
2358
2359
2360 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2361 "sdr r<RT>, <OFFSET>(r<BASE>)"
2362 *mipsIII:
2363 *mipsIV:
2364 *mipsV:
2365 *vr4100:
2366 *vr5000:
2367 {
2368   check_u64 (SD_, instruction_0);
2369   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2370 }
2371
2372
2373 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2374 "sh r<RT>, <OFFSET>(r<BASE>)"
2375 *mipsI:
2376 *mipsII:
2377 *mipsIII:
2378 *mipsIV:
2379 *mipsV:
2380 *vr4100:
2381 *vr5000:
2382 *r3900:
2383 {
2384   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2385 }
2386
2387
2388 :function:::void:do_sll:int rt, int rd, int shift
2389 {
2390   unsigned32 temp = (GPR[rt] << shift);
2391   TRACE_ALU_INPUT2 (GPR[rt], shift);
2392   GPR[rd] = EXTEND32 (temp);
2393   TRACE_ALU_RESULT (GPR[rd]);
2394 }
2395
2396 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2397 "nop":RD == 0 && RT == 0 && SHIFT == 0
2398 "sll r<RD>, r<RT>, <SHIFT>"
2399 *mipsI:
2400 *mipsII:
2401 *mipsIII:
2402 *mipsIV:
2403 *mipsV:
2404 *vr4100:
2405 *vr5000:
2406 *r3900:
2407 {
2408   /* Skip shift for NOP, so that there won't be lots of extraneous
2409      trace output.  */
2410   if (RD != 0 || RT != 0 || SHIFT != 0)
2411     do_sll (SD_, RT, RD, SHIFT);
2412 }
2413
2414
2415 :function:::void:do_sllv:int rs, int rt, int rd
2416 {
2417   int s = MASKED (GPR[rs], 4, 0);
2418   unsigned32 temp = (GPR[rt] << s);
2419   TRACE_ALU_INPUT2 (GPR[rt], s);
2420   GPR[rd] = EXTEND32 (temp);
2421   TRACE_ALU_RESULT (GPR[rd]);
2422 }
2423
2424 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2425 "sllv r<RD>, r<RT>, r<RS>"
2426 *mipsI:
2427 *mipsII:
2428 *mipsIII:
2429 *mipsIV:
2430 *mipsV:
2431 *vr4100:
2432 *vr5000:
2433 *r3900:
2434 {
2435   do_sllv (SD_, RS, RT, RD);
2436 }
2437
2438
2439 :function:::void:do_slt:int rs, int rt, int rd
2440 {
2441   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2442   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2443   TRACE_ALU_RESULT (GPR[rd]);
2444 }
2445
2446 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2447 "slt r<RD>, r<RS>, r<RT>"
2448 *mipsI:
2449 *mipsII:
2450 *mipsIII:
2451 *mipsIV:
2452 *mipsV:
2453 *vr4100:
2454 *vr5000:
2455 *r3900:
2456 {
2457   do_slt (SD_, RS, RT, RD);
2458 }
2459
2460
2461 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2462 {
2463   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2464   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2465   TRACE_ALU_RESULT (GPR[rt]);
2466 }
2467
2468 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2469 "slti r<RT>, r<RS>, <IMMEDIATE>"
2470 *mipsI:
2471 *mipsII:
2472 *mipsIII:
2473 *mipsIV:
2474 *mipsV:
2475 *vr4100:
2476 *vr5000:
2477 *r3900:
2478 {
2479   do_slti (SD_, RS, RT, IMMEDIATE);
2480 }
2481
2482
2483 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2484 {
2485   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2486   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2487   TRACE_ALU_RESULT (GPR[rt]);
2488 }
2489
2490 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2491 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2492 *mipsI:
2493 *mipsII:
2494 *mipsIII:
2495 *mipsIV:
2496 *mipsV:
2497 *vr4100:
2498 *vr5000:
2499 *r3900:
2500 {
2501   do_sltiu (SD_, RS, RT, IMMEDIATE);
2502 }
2503
2504
2505
2506 :function:::void:do_sltu:int rs, int rt, int rd
2507 {
2508   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2509   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2510   TRACE_ALU_RESULT (GPR[rd]);
2511 }
2512
2513 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2514 "sltu r<RD>, r<RS>, r<RT>"
2515 *mipsI:
2516 *mipsII:
2517 *mipsIII:
2518 *mipsIV:
2519 *mipsV:
2520 *vr4100:
2521 *vr5000:
2522 *r3900:
2523 {
2524   do_sltu (SD_, RS, RT, RD);
2525 }
2526
2527
2528 :function:::void:do_sra:int rt, int rd, int shift
2529 {
2530   signed32 temp = (signed32) GPR[rt] >> shift;
2531   TRACE_ALU_INPUT2 (GPR[rt], shift);
2532   GPR[rd] = EXTEND32 (temp);
2533   TRACE_ALU_RESULT (GPR[rd]);
2534 }
2535
2536 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2537 "sra r<RD>, r<RT>, <SHIFT>"
2538 *mipsI:
2539 *mipsII:
2540 *mipsIII:
2541 *mipsIV:
2542 *mipsV:
2543 *vr4100:
2544 *vr5000:
2545 *r3900:
2546 {
2547   do_sra (SD_, RT, RD, SHIFT);
2548 }
2549
2550
2551
2552 :function:::void:do_srav:int rs, int rt, int rd
2553 {
2554   int s = MASKED (GPR[rs], 4, 0);
2555   signed32 temp = (signed32) GPR[rt] >> s;
2556   TRACE_ALU_INPUT2 (GPR[rt], s);
2557   GPR[rd] = EXTEND32 (temp);
2558   TRACE_ALU_RESULT (GPR[rd]);
2559 }
2560
2561 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
2562 "srav r<RD>, r<RT>, r<RS>"
2563 *mipsI:
2564 *mipsII:
2565 *mipsIII:
2566 *mipsIV:
2567 *mipsV:
2568 *vr4100:
2569 *vr5000:
2570 *r3900:
2571 {
2572   do_srav (SD_, RS, RT, RD);
2573 }
2574
2575
2576
2577 :function:::void:do_srl:int rt, int rd, int shift
2578 {
2579   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2580   TRACE_ALU_INPUT2 (GPR[rt], shift);
2581   GPR[rd] = EXTEND32 (temp);
2582   TRACE_ALU_RESULT (GPR[rd]);
2583 }
2584
2585 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2586 "srl r<RD>, r<RT>, <SHIFT>"
2587 *mipsI:
2588 *mipsII:
2589 *mipsIII:
2590 *mipsIV:
2591 *mipsV:
2592 *vr4100:
2593 *vr5000:
2594 *r3900:
2595 {
2596   do_srl (SD_, RT, RD, SHIFT);
2597 }
2598
2599
2600 :function:::void:do_srlv:int rs, int rt, int rd
2601 {
2602   int s = MASKED (GPR[rs], 4, 0);
2603   unsigned32 temp = (unsigned32) GPR[rt] >> s;
2604   TRACE_ALU_INPUT2 (GPR[rt], s);
2605   GPR[rd] = EXTEND32 (temp);
2606   TRACE_ALU_RESULT (GPR[rd]);
2607 }
2608
2609 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
2610 "srlv r<RD>, r<RT>, r<RS>"
2611 *mipsI:
2612 *mipsII:
2613 *mipsIII:
2614 *mipsIV:
2615 *mipsV:
2616 *vr4100:
2617 *vr5000:
2618 *r3900:
2619 {
2620   do_srlv (SD_, RS, RT, RD);
2621 }
2622
2623
2624 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
2625 "sub r<RD>, r<RS>, r<RT>"
2626 *mipsI:
2627 *mipsII:
2628 *mipsIII:
2629 *mipsIV:
2630 *mipsV:
2631 *vr4100:
2632 *vr5000:
2633 *r3900:
2634 {
2635   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2636   {
2637     ALU32_BEGIN (GPR[RS]);
2638     ALU32_SUB (GPR[RT]);
2639     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
2640   }
2641   TRACE_ALU_RESULT (GPR[RD]);
2642 }
2643
2644
2645 :function:::void:do_subu:int rs, int rt, int rd
2646 {
2647   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2648   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2649   TRACE_ALU_RESULT (GPR[rd]);
2650 }
2651
2652 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
2653 "subu r<RD>, r<RS>, r<RT>"
2654 *mipsI:
2655 *mipsII:
2656 *mipsIII:
2657 *mipsIV:
2658 *mipsV:
2659 *vr4100:
2660 *vr5000:
2661 *r3900:
2662 {
2663   do_subu (SD_, RS, RT, RD);
2664 }
2665
2666
2667 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2668 "sw r<RT>, <OFFSET>(r<BASE>)"
2669 *mipsI:
2670 *mipsII:
2671 *mipsIII:
2672 *mipsIV:
2673 *mipsV:
2674 *vr4100:
2675 *r3900:
2676 *vr5000:
2677 {
2678   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2679 }
2680
2681
2682 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2683 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2684 *mipsI:
2685 *mipsII:
2686 *mipsIII:
2687 *mipsIV:
2688 *mipsV:
2689 *vr4100:
2690 *vr5000:
2691 *r3900:
2692 {
2693   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2694 }
2695
2696
2697 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2698 "swl r<RT>, <OFFSET>(r<BASE>)"
2699 *mipsI:
2700 *mipsII:
2701 *mipsIII:
2702 *mipsIV:
2703 *mipsV:
2704 *vr4100:
2705 *vr5000:
2706 *r3900:
2707 {
2708   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2709 }
2710
2711
2712 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2713 "swr r<RT>, <OFFSET>(r<BASE>)"
2714 *mipsI:
2715 *mipsII:
2716 *mipsIII:
2717 *mipsIV:
2718 *mipsV:
2719 *vr4100:
2720 *vr5000:
2721 *r3900:
2722 {
2723   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2724 }
2725
2726
2727 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2728 "sync":STYPE == 0
2729 "sync <STYPE>"
2730 *mipsII:
2731 *mipsIII:
2732 *mipsIV:
2733 *mipsV:
2734 *vr4100:
2735 *vr5000:
2736 *r3900:
2737 {
2738   SyncOperation (STYPE);
2739 }
2740
2741
2742 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2743 "syscall <CODE>"
2744 *mipsI:
2745 *mipsII:
2746 *mipsIII:
2747 *mipsIV:
2748 *mipsV:
2749 *vr4100:
2750 *vr5000:
2751 *r3900:
2752 {
2753   SignalException(SystemCall, instruction_0);
2754 }
2755
2756
2757 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2758 "teq r<RS>, r<RT>"
2759 *mipsII:
2760 *mipsIII:
2761 *mipsIV:
2762 *mipsV:
2763 *vr4100:
2764 *vr5000:
2765 {
2766   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2767     SignalException(Trap, instruction_0);
2768 }
2769
2770
2771 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2772 "teqi r<RS>, <IMMEDIATE>"
2773 *mipsII:
2774 *mipsIII:
2775 *mipsIV:
2776 *mipsV:
2777 *vr4100:
2778 *vr5000:
2779 {
2780   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2781     SignalException(Trap, instruction_0);
2782 }
2783
2784
2785 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2786 "tge r<RS>, r<RT>"
2787 *mipsII:
2788 *mipsIII:
2789 *mipsIV:
2790 *mipsV:
2791 *vr4100:
2792 *vr5000:
2793 {
2794   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2795     SignalException(Trap, instruction_0);
2796 }
2797
2798
2799 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2800 "tgei r<RS>, <IMMEDIATE>"
2801 *mipsII:
2802 *mipsIII:
2803 *mipsIV:
2804 *mipsV:
2805 *vr4100:
2806 *vr5000:
2807 {
2808   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2809     SignalException(Trap, instruction_0);
2810 }
2811
2812
2813 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2814 "tgeiu r<RS>, <IMMEDIATE>"
2815 *mipsII:
2816 *mipsIII:
2817 *mipsIV:
2818 *mipsV:
2819 *vr4100:
2820 *vr5000:
2821 {
2822   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2823     SignalException(Trap, instruction_0);
2824 }
2825
2826
2827 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2828 "tgeu r<RS>, r<RT>"
2829 *mipsII:
2830 *mipsIII:
2831 *mipsIV:
2832 *mipsV:
2833 *vr4100:
2834 *vr5000:
2835 {
2836   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2837     SignalException(Trap, instruction_0);
2838 }
2839
2840
2841 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2842 "tlt r<RS>, r<RT>"
2843 *mipsII:
2844 *mipsIII:
2845 *mipsIV:
2846 *mipsV:
2847 *vr4100:
2848 *vr5000:
2849 {
2850   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2851     SignalException(Trap, instruction_0);
2852 }
2853
2854
2855 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2856 "tlti r<RS>, <IMMEDIATE>"
2857 *mipsII:
2858 *mipsIII:
2859 *mipsIV:
2860 *mipsV:
2861 *vr4100:
2862 *vr5000:
2863 {
2864   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2865     SignalException(Trap, instruction_0);
2866 }
2867
2868
2869 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2870 "tltiu r<RS>, <IMMEDIATE>"
2871 *mipsII:
2872 *mipsIII:
2873 *mipsIV:
2874 *mipsV:
2875 *vr4100:
2876 *vr5000:
2877 {
2878   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2879     SignalException(Trap, instruction_0);
2880 }
2881
2882
2883 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2884 "tltu r<RS>, r<RT>"
2885 *mipsII:
2886 *mipsIII:
2887 *mipsIV:
2888 *mipsV:
2889 *vr4100:
2890 *vr5000:
2891 {
2892   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2893     SignalException(Trap, instruction_0);
2894 }
2895
2896
2897 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2898 "tne r<RS>, r<RT>"
2899 *mipsII:
2900 *mipsIII:
2901 *mipsIV:
2902 *mipsV:
2903 *vr4100:
2904 *vr5000:
2905 {
2906   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2907     SignalException(Trap, instruction_0);
2908 }
2909
2910
2911 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2912 "tne r<RS>, <IMMEDIATE>"
2913 *mipsII:
2914 *mipsIII:
2915 *mipsIV:
2916 *mipsV:
2917 *vr4100:
2918 *vr5000:
2919 {
2920   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2921     SignalException(Trap, instruction_0);
2922 }
2923
2924
2925 :function:::void:do_xor:int rs, int rt, int rd
2926 {
2927   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2928   GPR[rd] = GPR[rs] ^ GPR[rt];
2929   TRACE_ALU_RESULT (GPR[rd]);
2930 }
2931
2932 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
2933 "xor r<RD>, r<RS>, r<RT>"
2934 *mipsI:
2935 *mipsII:
2936 *mipsIII:
2937 *mipsIV:
2938 *mipsV:
2939 *vr4100:
2940 *vr5000:
2941 *r3900:
2942 {
2943   do_xor (SD_, RS, RT, RD);
2944 }
2945
2946
2947 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
2948 {
2949   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2950   GPR[rt] = GPR[rs] ^ immediate;
2951   TRACE_ALU_RESULT (GPR[rt]);
2952 }
2953
2954 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2955 "xori r<RT>, r<RS>, <IMMEDIATE>"
2956 *mipsI:
2957 *mipsII:
2958 *mipsIII:
2959 *mipsIV:
2960 *mipsV:
2961 *vr4100:
2962 *vr5000:
2963 *r3900:
2964 {
2965   do_xori (SD_, RS, RT, IMMEDIATE);
2966 }
2967
2968 \f
2969 //
2970 // MIPS Architecture:
2971 //
2972 //        FPU Instruction Set (COP1 & COP1X)
2973 //
2974
2975
2976 :%s::::FMT:int fmt
2977 {
2978   switch (fmt)
2979     {
2980     case fmt_single: return "s";
2981     case fmt_double: return "d";
2982     case fmt_word: return "w";
2983     case fmt_long: return "l";
2984     default: return "?";
2985     }
2986 }
2987
2988 :%s::::X:int x
2989 {
2990   switch (x)
2991     {
2992     case 0: return "f";
2993     case 1: return "t";
2994     default: return "?";
2995     }
2996 }
2997
2998 :%s::::TF:int tf
2999 {
3000   if (tf)
3001     return "t";
3002   else
3003     return "f";
3004 }
3005
3006 :%s::::ND:int nd
3007 {
3008   if (nd)
3009     return "l";
3010   else
3011     return "";
3012 }
3013
3014 :%s::::COND:int cond
3015 {
3016   switch (cond)
3017     {
3018     case 00: return "f";
3019     case 01: return "un";
3020     case 02: return "eq";
3021     case 03: return "ueq";
3022     case 04: return "olt";
3023     case 05: return "ult";
3024     case 06: return "ole";
3025     case 07: return "ule";
3026     case 010: return "sf";
3027     case 011: return "ngle";
3028     case 012: return "seq";
3029     case 013: return "ngl";
3030     case 014: return "lt";
3031     case 015: return "nge";
3032     case 016: return "le";
3033     case 017: return "ngt";
3034     default: return "?";
3035     }
3036 }
3037
3038
3039 // Helpers:
3040 //
3041 // Check that the given FPU format is usable, and signal a
3042 // ReservedInstruction exception if not.
3043 //
3044
3045 // check_fmt checks that the format is single or double.
3046 :function:::void:check_fmt:int fmt, instruction_word insn
3047 *mipsI:
3048 *mipsII:
3049 *mipsIII:
3050 *mipsIV:
3051 *mipsV:
3052 *vr4100:
3053 *vr5000:
3054 *r3900:
3055 {
3056   if ((fmt != fmt_single) && (fmt != fmt_double))
3057     SignalException (ReservedInstruction, insn);
3058 }
3059
3060 // check_fmt_p checks that the format is single, double, or paired single.
3061 :function:::void:check_fmt_p:int fmt, instruction_word insn
3062 *mipsI:
3063 *mipsII:
3064 *mipsIII:
3065 *mipsIV:
3066 *mipsV:
3067 *vr4100:
3068 *vr5000:
3069 *r3900:
3070 {
3071   /* None of these ISAs support Paired Single, so just fall back to
3072      the single/double check.  */
3073   /* XXX FIXME: not true for mipsV, but we don't support .ps insns yet.  */
3074   check_fmt (SD_, fmt, insn);
3075 }
3076
3077
3078 // Helper:
3079 //
3080 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3081 // exception if not.
3082 //
3083
3084 :function:::void:check_fpu:
3085 *mipsI:
3086 *mipsII:
3087 *mipsIII:
3088 *mipsIV:
3089 *mipsV:
3090 *vr4100:
3091 *vr5000:
3092 *r3900:
3093 {
3094 #if 0   /* XXX FIXME: For now, never treat the FPU as disabled.  */
3095   if (! COP_Usable (1))
3096     SignalExceptionCoProcessorUnusable (1);
3097 #endif
3098 }
3099
3100
3101 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3102 "abs.%s<FMT> f<FD>, f<FS>"
3103 *mipsI:
3104 *mipsII:
3105 *mipsIII:
3106 *mipsIV:
3107 *mipsV:
3108 *vr4100:
3109 *vr5000:
3110 *r3900:
3111 {
3112   int fmt = FMT;
3113   check_fpu (SD_);
3114   check_fmt_p (SD_, fmt, instruction_0);
3115   StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
3116 }
3117
3118
3119
3120 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3121 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3122 *mipsI:
3123 *mipsII:
3124 *mipsIII:
3125 *mipsIV:
3126 *mipsV:
3127 *vr4100:
3128 *vr5000:
3129 *r3900:
3130 {
3131   int fmt = FMT;
3132   check_fpu (SD_);
3133   check_fmt_p (SD_, fmt, instruction_0);
3134   StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3135 }
3136
3137
3138
3139 // BC1F
3140 // BC1FL
3141 // BC1T
3142 // BC1TL
3143
3144 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3145 "bc1%s<TF>%s<ND> <OFFSET>"
3146 *mipsI:
3147 *mipsII:
3148 *mipsIII:
3149 {
3150   check_fpu (SD_);
3151   check_branch_bug ();
3152   TRACE_BRANCH_INPUT (PREVCOC1());
3153   if (PREVCOC1() == TF)
3154     {
3155       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3156       TRACE_BRANCH_RESULT (dest);
3157       mark_branch_bug (dest);
3158       DELAY_SLOT (dest);
3159     }
3160   else if (ND)
3161     {
3162       TRACE_BRANCH_RESULT (0);
3163       NULLIFY_NEXT_INSTRUCTION ();
3164     }
3165   else
3166     {
3167       TRACE_BRANCH_RESULT (NIA);
3168     }
3169 }
3170
3171 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3172 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3173 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3174 *mipsIV:
3175 *mipsV:
3176 #*vr4100:
3177 *vr5000:
3178 *r3900:
3179 {
3180   check_fpu (SD_);
3181   check_branch_bug ();
3182   if (GETFCC(CC) == TF)
3183     {
3184       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3185       mark_branch_bug (dest);
3186       DELAY_SLOT (dest);
3187     }
3188   else if (ND)
3189     {
3190       NULLIFY_NEXT_INSTRUCTION ();
3191     }
3192 }
3193
3194
3195
3196
3197
3198
3199 // C.EQ.S
3200 // C.EQ.D
3201 // ...
3202
3203 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3204 {
3205   int less;
3206   int equal;
3207   int unordered;
3208   int condition;
3209   unsigned64 ofs = ValueFPR (fs, fmt);
3210   unsigned64 oft = ValueFPR (ft, fmt);
3211   if (NaN (ofs, fmt) || NaN (oft, fmt))
3212     {
3213       if (FCSR & FP_ENABLE (IO))
3214         {
3215           FCSR |= FP_CAUSE (IO);
3216           SignalExceptionFPE ();
3217         }
3218       less = 0;
3219       equal = 0;
3220       unordered = 1;
3221     }
3222   else
3223     {
3224       less = Less (ofs, oft, fmt);
3225       equal = Equal (ofs, oft, fmt);
3226       unordered = 0;
3227     }
3228   condition = (((cond & (1 << 2)) && less)
3229                || ((cond & (1 << 1)) && equal)
3230                || ((cond & (1 << 0)) && unordered));
3231   SETFCC (cc, condition);
3232 }
3233
3234 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3235 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3236 *mipsI:
3237 *mipsII:
3238 *mipsIII:
3239 {
3240   int fmt = FMT;
3241   check_fpu (SD_);
3242   check_fmt_p (SD_, fmt, instruction_0);
3243   do_c_cond_fmt (SD_, fmt, FT, FS, 0, COND, instruction_0);
3244 }
3245
3246 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3247 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3248 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3249 *mipsIV:
3250 *mipsV:
3251 *vr4100:
3252 *vr5000:
3253 *r3900:
3254 {
3255   int fmt = FMT;
3256   check_fpu (SD_);
3257   check_fmt_p (SD_, fmt, instruction_0);
3258   do_c_cond_fmt (SD_, fmt, FT, FS, CC, COND, instruction_0);
3259 }
3260
3261
3262 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3263 "ceil.l.%s<FMT> f<FD>, f<FS>"
3264 *mipsIII:
3265 *mipsIV:
3266 *mipsV:
3267 *vr4100:
3268 *vr5000:
3269 *r3900:
3270 {
3271   int fmt = FMT;
3272   check_fpu (SD_);
3273   check_fmt (SD_, fmt, instruction_0);
3274   StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
3275 }
3276
3277
3278 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3279 *mipsII:
3280 *mipsIII:
3281 *mipsIV:
3282 *mipsV:
3283 *vr4100:
3284 *vr5000:
3285 *r3900:
3286 {
3287   int fmt = FMT;
3288   check_fpu (SD_);
3289   check_fmt (SD_, fmt, instruction_0);
3290   StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
3291 }
3292
3293
3294 // CFC1
3295 // CTC1
3296 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
3297 "c%s<X>c1 r<RT>, f<FS>"
3298 *mipsI:
3299 *mipsII:
3300 *mipsIII:
3301 {
3302   check_fpu (SD_);
3303   if (X)
3304     {
3305       if (FS == 0)
3306         PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
3307       else if (FS == 31)
3308         PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
3309       /* else NOP */
3310       PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
3311     }
3312   else
3313     { /* control from */
3314       if (FS == 0)
3315         PENDING_FILL(RT, EXTEND32 (FCR0));
3316       else if (FS == 31)
3317         PENDING_FILL(RT, EXTEND32 (FCR31));
3318       /* else NOP */
3319     }
3320 }
3321 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
3322 "c%s<X>c1 r<RT>, f<FS>"
3323 *mipsIV:
3324 *mipsV:
3325 *vr4100:
3326 *vr5000:
3327 *r3900:
3328 {
3329   check_fpu (SD_);
3330   if (X)
3331     {
3332       /* control to */
3333       TRACE_ALU_INPUT1 (GPR[RT]);
3334       if (FS == 0)
3335         {
3336           FCR0 = VL4_8(GPR[RT]);
3337           TRACE_ALU_RESULT (FCR0);
3338         }
3339       else if (FS == 31)
3340         {
3341           FCR31 = VL4_8(GPR[RT]);
3342           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3343           TRACE_ALU_RESULT (FCR31);
3344         }
3345       else
3346         {
3347           TRACE_ALU_RESULT0 ();
3348         }
3349       /* else NOP */
3350     }
3351   else
3352     { /* control from */
3353       if (FS == 0)
3354         {
3355           TRACE_ALU_INPUT1 (FCR0);
3356           GPR[RT] = EXTEND32 (FCR0);
3357         }
3358       else if (FS == 31)
3359         {
3360           TRACE_ALU_INPUT1 (FCR31);
3361           GPR[RT] = EXTEND32 (FCR31);
3362         }
3363       TRACE_ALU_RESULT (GPR[RT]);
3364       /* else NOP */
3365     }
3366 }
3367
3368
3369 //
3370 // FIXME: Does not correctly differentiate between mips*
3371 //
3372 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3373 "cvt.d.%s<FMT> f<FD>, f<FS>"
3374 *mipsI:
3375 *mipsII:
3376 *mipsIII:
3377 *mipsIV:
3378 *mipsV:
3379 *vr4100:
3380 *vr5000:
3381 *r3900:
3382 {
3383   int fmt = FMT;
3384   check_fpu (SD_);
3385   {
3386     if ((fmt == fmt_double) | 0)
3387       SignalException(ReservedInstruction,instruction_0);
3388     else
3389       StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
3390   }
3391 }
3392
3393
3394 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3395 "cvt.l.%s<FMT> f<FD>, f<FS>"
3396 *mipsIII:
3397 *mipsIV:
3398 *mipsV:
3399 *vr4100:
3400 *vr5000:
3401 *r3900:
3402 {
3403   int fmt = FMT;
3404   check_fpu (SD_);
3405   {
3406     if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3407       SignalException(ReservedInstruction,instruction_0);
3408     else
3409       StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
3410   }
3411 }
3412
3413
3414 //
3415 // FIXME: Does not correctly differentiate between mips*
3416 //
3417 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3418 "cvt.s.%s<FMT> f<FD>, f<FS>"
3419 *mipsI:
3420 *mipsII:
3421 *mipsIII:
3422 *mipsIV:
3423 *mipsV:
3424 *vr4100:
3425 *vr5000:
3426 *r3900:
3427 {
3428   int fmt = FMT;
3429   check_fpu (SD_);
3430   {
3431     if ((fmt == fmt_single) | 0)
3432       SignalException(ReservedInstruction,instruction_0);
3433     else
3434       StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
3435   }
3436 }
3437
3438
3439 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
3440 "cvt.w.%s<FMT> f<FD>, f<FS>"
3441 *mipsI:
3442 *mipsII:
3443 *mipsIII:
3444 *mipsIV:
3445 *mipsV:
3446 *vr4100:
3447 *vr5000:
3448 *r3900:
3449 {
3450   int fmt = FMT;
3451   check_fpu (SD_);
3452   {
3453     if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
3454       SignalException(ReservedInstruction,instruction_0);
3455     else
3456       StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
3457   }
3458 }
3459
3460
3461 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
3462 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3463 *mipsI:
3464 *mipsII:
3465 *mipsIII:
3466 *mipsIV:
3467 *mipsV:
3468 *vr4100:
3469 *vr5000:
3470 *r3900:
3471 {
3472   int fmt = FMT;
3473   check_fpu (SD_);
3474   check_fmt (SD_, fmt, instruction_0);
3475   StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3476 }
3477
3478
3479 // DMFC1
3480 // DMTC1
3481 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
3482 "dm%s<X>c1 r<RT>, f<FS>"
3483 *mipsIII:
3484 {
3485   check_fpu (SD_);
3486   check_u64 (SD_, instruction_0);
3487   if (X)
3488     {
3489       if (SizeFGR() == 64)
3490         PENDING_FILL((FS + FGRIDX),GPR[RT]);
3491       else if ((FS & 0x1) == 0)
3492         {
3493           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3494           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3495         }
3496     }
3497   else
3498     {
3499       if (SizeFGR() == 64)
3500         PENDING_FILL(RT,FGR[FS]);
3501       else if ((FS & 0x1) == 0)
3502         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3503       else
3504         {
3505           if (STATE_VERBOSE_P(SD))
3506             sim_io_eprintf (SD,
3507               "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
3508               (long) CIA);
3509           PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3510         }
3511     }
3512 }
3513 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
3514 "dm%s<X>c1 r<RT>, f<FS>"
3515 *mipsIV:
3516 *mipsV:
3517 *vr4100:
3518 *vr5000:
3519 *r3900:
3520 {
3521   check_fpu (SD_);
3522   check_u64 (SD_, instruction_0);
3523   if (X)
3524     {
3525       if (SizeFGR() == 64)
3526         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3527       else if ((FS & 0x1) == 0)
3528         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3529     }
3530   else
3531     {
3532       if (SizeFGR() == 64)
3533         GPR[RT] = FGR[FS];
3534       else if ((FS & 0x1) == 0)
3535         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3536       else
3537         {
3538           if (STATE_VERBOSE_P(SD))
3539             sim_io_eprintf (SD,
3540               "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
3541                             (long) CIA);
3542           GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3543         }
3544     }
3545 }
3546
3547
3548 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
3549 "floor.l.%s<FMT> f<FD>, f<FS>"
3550 *mipsIII:
3551 *mipsIV:
3552 *mipsV:
3553 *vr4100:
3554 *vr5000:
3555 *r3900:
3556 {
3557   int fmt = FMT;
3558   check_fpu (SD_);
3559   check_fmt (SD_, fmt, instruction_0);
3560   StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
3561 }
3562
3563
3564 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
3565 "floor.w.%s<FMT> f<FD>, f<FS>"
3566 *mipsII:
3567 *mipsIII:
3568 *mipsIV:
3569 *mipsV:
3570 *vr4100:
3571 *vr5000:
3572 *r3900:
3573 {
3574   int fmt = FMT;
3575   check_fpu (SD_);
3576   check_fmt (SD_, fmt, instruction_0);
3577   StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
3578 }
3579
3580
3581 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
3582 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
3583 *mipsII:
3584 *mipsIII:
3585 *mipsIV:
3586 *mipsV:
3587 *vr4100:
3588 *vr5000:
3589 *r3900:
3590 {
3591   check_fpu (SD_);
3592   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3593 }
3594
3595
3596 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
3597 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3598 *mipsIV:
3599 *mipsV:
3600 *vr5000:
3601 {
3602   check_fpu (SD_);
3603   check_u64 (SD_, instruction_0);
3604   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3605 }
3606
3607
3608
3609 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
3610 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
3611 *mipsI:
3612 *mipsII:
3613 *mipsIII:
3614 *mipsIV:
3615 *mipsV:
3616 *vr4100:
3617 *vr5000:
3618 *r3900:
3619 {
3620   check_fpu (SD_);
3621   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3622 }
3623
3624
3625 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
3626 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3627 *mipsIV:
3628 *mipsV:
3629 *vr5000:
3630 {
3631   check_fpu (SD_);
3632   check_u64 (SD_, instruction_0);
3633   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3634 }
3635
3636
3637
3638 //
3639 // FIXME: Not correct for mips*
3640 //
3641 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3642 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3643 *mipsIV:
3644 *mipsV:
3645 *vr5000:
3646 {
3647   check_fpu (SD_);
3648   {
3649     StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
3650   }
3651 }
3652
3653
3654 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3655 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3656 *mipsIV:
3657 *mipsV:
3658 *vr5000:
3659 {
3660   check_fpu (SD_);
3661   {
3662     StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
3663   }
3664 }
3665
3666
3667 // MFC1
3668 // MTC1
3669 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
3670 "m%s<X>c1 r<RT>, f<FS>"
3671 *mipsI:
3672 *mipsII:
3673 *mipsIII:
3674 {
3675   check_fpu (SD_);
3676   if (X)
3677     { /*MTC1*/
3678       if (SizeFGR() == 64)
3679         {
3680           if (STATE_VERBOSE_P(SD))
3681             sim_io_eprintf (SD,
3682                             "Warning:  PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
3683                             (long) CIA);
3684           PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3685         }
3686       else
3687         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3688     }
3689   else /*MFC1*/
3690     PENDING_FILL (RT, EXTEND32 (FGR[FS]));
3691 }
3692 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
3693 "m%s<X>c1 r<RT>, f<FS>"
3694 *mipsIV:
3695 *mipsV:
3696 *vr4100:
3697 *vr5000:
3698 *r3900:
3699 {
3700   int fs = FS;
3701   check_fpu (SD_);
3702   if (X)
3703     /*MTC1*/
3704     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3705   else /*MFC1*/
3706     GPR[RT] = EXTEND32 (FGR[FS]);
3707 }
3708
3709
3710 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
3711 "mov.%s<FMT> f<FD>, f<FS>"
3712 *mipsI:
3713 *mipsII:
3714 *mipsIII:
3715 *mipsIV:
3716 *mipsV:
3717 *vr4100:
3718 *vr5000:
3719 *r3900:
3720 {
3721   int fmt = FMT;
3722   check_fpu (SD_);
3723   check_fmt_p (SD_, fmt, instruction_0);
3724   StoreFPR(FD,fmt,ValueFPR(FS,fmt));
3725 }
3726
3727
3728 // MOVF
3729 // MOVT
3730 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
3731 "mov%s<TF> r<RD>, r<RS>, <CC>"
3732 *mipsIV:
3733 *mipsV:
3734 *vr5000:
3735 {
3736   check_fpu (SD_);
3737   if (GETFCC(CC) == TF)
3738     GPR[RD] = GPR[RS];
3739 }
3740
3741
3742 // MOVF.fmt
3743 // MOVT.fmt
3744 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
3745 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3746 *mipsIV:
3747 *mipsV:
3748 *vr5000:
3749 {
3750   int fmt = FMT;
3751   check_fpu (SD_);
3752   {
3753    if (GETFCC(CC) == TF)
3754      StoreFPR (FD, fmt, ValueFPR (FS, fmt));
3755    else
3756      StoreFPR (FD, fmt, ValueFPR (FD, fmt));
3757   }
3758 }
3759
3760
3761 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
3762 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
3763 *mipsIV:
3764 *mipsV:
3765 *vr5000:
3766 {
3767   check_fpu (SD_);
3768   if (GPR[RT] != 0)
3769     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3770   else
3771     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3772 }
3773
3774
3775 // MOVT see MOVtf
3776
3777
3778 // MOVT.fmt see MOVtf.fmt
3779
3780
3781
3782 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
3783 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3784 *mipsIV:
3785 *mipsV:
3786 *vr5000:
3787 {
3788   check_fpu (SD_);
3789   if (GPR[RT] == 0)
3790     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3791   else
3792     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3793 }
3794
3795
3796 // MSUB.fmt
3797 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
3798 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3799 *mipsIV:
3800 *mipsV:
3801 *vr5000:
3802 {
3803   check_fpu (SD_);
3804   StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
3805 }
3806
3807
3808 // MSUB.fmt
3809 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
3810 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3811 *mipsIV:
3812 *mipsV:
3813 *vr5000:
3814 {
3815   check_fpu (SD_);
3816   StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
3817 }
3818
3819
3820 // MTC1 see MxC1
3821
3822
3823 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
3824 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3825 *mipsI:
3826 *mipsII:
3827 *mipsIII:
3828 *mipsIV:
3829 *mipsV:
3830 *vr4100:
3831 *vr5000:
3832 *r3900:
3833 {
3834   int fmt = FMT;
3835   check_fpu (SD_);
3836   check_fmt_p (SD_, fmt, instruction_0);
3837   StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3838 }
3839
3840
3841 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
3842 "neg.%s<FMT> f<FD>, f<FS>"
3843 *mipsI:
3844 *mipsII:
3845 *mipsIII:
3846 *mipsIV:
3847 *mipsV:
3848 *vr4100:
3849 *vr5000:
3850 *r3900:
3851 {
3852   int fmt = FMT;
3853   check_fpu (SD_);
3854   check_fmt_p (SD_, fmt, instruction_0);
3855   StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
3856 }
3857
3858
3859 // NMADD.fmt
3860 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
3861 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3862 *mipsIV:
3863 *mipsV:
3864 *vr5000:
3865 {
3866   check_fpu (SD_);
3867   StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
3868 }
3869
3870
3871 // NMADD.fmt
3872 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
3873 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3874 *mipsIV:
3875 *mipsV:
3876 *vr5000:
3877 {
3878   check_fpu (SD_);
3879   StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
3880 }
3881
3882
3883 // NMSUB.fmt
3884 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
3885 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3886 *mipsIV:
3887 *mipsV:
3888 *vr5000:
3889 {
3890   check_fpu (SD_);
3891   StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
3892 }
3893
3894
3895 // NMSUB.fmt
3896 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
3897 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3898 *mipsIV:
3899 *mipsV:
3900 *vr5000:
3901 {
3902   check_fpu (SD_);
3903   StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
3904 }
3905
3906
3907 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
3908 "prefx <HINT>, r<INDEX>(r<BASE>)"
3909 *mipsIV:
3910 *mipsV:
3911 *vr5000:
3912 {
3913   address_word base = GPR[BASE];
3914   address_word index = GPR[INDEX];
3915   {
3916     address_word vaddr = loadstore_ea (SD_, base, index);
3917     address_word paddr;
3918     int uncached;
3919     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3920       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
3921   }
3922 }
3923
3924 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
3925 "recip.%s<FMT> f<FD>, f<FS>"
3926 *mipsIV:
3927 *mipsV:
3928 *vr5000:
3929 {
3930   int fmt = FMT;
3931   check_fpu (SD_);
3932   check_fmt (SD_, fmt, instruction_0);
3933   StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
3934 }
3935
3936
3937 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
3938 "round.l.%s<FMT> f<FD>, f<FS>"
3939 *mipsIII:
3940 *mipsIV:
3941 *mipsV:
3942 *vr4100:
3943 *vr5000:
3944 *r3900:
3945 {
3946   int fmt = FMT;
3947   check_fpu (SD_);
3948   check_fmt (SD_, fmt, instruction_0);
3949   StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
3950 }
3951
3952
3953 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
3954 "round.w.%s<FMT> f<FD>, f<FS>"
3955 *mipsII:
3956 *mipsIII:
3957 *mipsIV:
3958 *mipsV:
3959 *vr4100:
3960 *vr5000:
3961 *r3900:
3962 {
3963   int fmt = FMT;
3964   check_fpu (SD_);
3965   check_fmt (SD_, fmt, instruction_0);
3966   StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
3967 }
3968
3969
3970 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
3971 *mipsIV:
3972 *mipsV:
3973 "rsqrt.%s<FMT> f<FD>, f<FS>"
3974 *vr5000:
3975 {
3976   int fmt = FMT;
3977   check_fpu (SD_);
3978   check_fmt (SD_, fmt, instruction_0);
3979   StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
3980 }
3981
3982
3983 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
3984 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
3985 *mipsII:
3986 *mipsIII:
3987 *mipsIV:
3988 *mipsV:
3989 *vr4100:
3990 *vr5000:
3991 *r3900:
3992 {
3993   check_fpu (SD_);
3994   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
3995 }
3996
3997
3998 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
3999 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4000 *mipsIV:
4001 *mipsV:
4002 *vr5000:
4003 {
4004   check_fpu (SD_);
4005   check_u64 (SD_, instruction_0);
4006   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4007 }
4008
4009
4010 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4011 "sqrt.%s<FMT> f<FD>, f<FS>"
4012 *mipsII:
4013 *mipsIII:
4014 *mipsIV:
4015 *mipsV:
4016 *vr4100:
4017 *vr5000:
4018 *r3900:
4019 {
4020   int fmt = FMT;
4021   check_fpu (SD_);
4022   check_fmt (SD_, fmt, instruction_0);
4023   StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
4024 }
4025
4026
4027 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4028 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4029 *mipsI:
4030 *mipsII:
4031 *mipsIII:
4032 *mipsIV:
4033 *mipsV:
4034 *vr4100:
4035 *vr5000:
4036 *r3900:
4037 {
4038   int fmt = FMT;
4039   check_fpu (SD_);
4040   check_fmt_p (SD_, fmt, instruction_0);
4041   StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4042 }
4043
4044
4045
4046 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4047 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4048 *mipsI:
4049 *mipsII:
4050 *mipsIII:
4051 *mipsIV:
4052 *mipsV:
4053 *vr4100:
4054 *vr5000:
4055 *r3900:
4056 {
4057   address_word base = GPR[BASE];
4058   address_word offset = EXTEND16 (OFFSET);
4059   check_fpu (SD_);
4060   {
4061     address_word vaddr = loadstore_ea (SD_, base, offset);
4062     address_word paddr;
4063     int uncached;
4064     if ((vaddr & 3) != 0)
4065       {
4066         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4067       }
4068     else
4069       {
4070         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4071           {
4072             uword64 memval = 0;
4073             uword64 memval1 = 0;
4074             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4075             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4076             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4077             unsigned int byte;
4078             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4079             byte = ((vaddr & mask) ^ bigendiancpu);
4080             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4081             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4082           }
4083       }
4084   }
4085 }
4086
4087
4088 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4089 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4090 *mipsIV:
4091 *mipsV:
4092 *vr5000:
4093 {
4094
4095   address_word base = GPR[BASE];
4096   address_word index = GPR[INDEX];
4097   check_fpu (SD_);
4098   check_u64 (SD_, instruction_0);
4099   {
4100    address_word vaddr = loadstore_ea (SD_, base, index);
4101    address_word paddr;
4102    int uncached;
4103    if ((vaddr & 3) != 0)
4104      {
4105        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4106      }
4107    else
4108    {
4109     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4110     {
4111      unsigned64 memval = 0;
4112      unsigned64 memval1 = 0;
4113      unsigned64 mask = 0x7;
4114      unsigned int byte;
4115      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4116      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4117      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4118       {
4119        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4120       }
4121     }
4122    }
4123   }
4124 }
4125
4126
4127 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4128 "trunc.l.%s<FMT> f<FD>, f<FS>"
4129 *mipsIII:
4130 *mipsIV:
4131 *mipsV:
4132 *vr4100:
4133 *vr5000:
4134 *r3900:
4135 {
4136   int fmt = FMT;
4137   check_fpu (SD_);
4138   check_fmt (SD_, fmt, instruction_0);
4139   StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
4140 }
4141
4142
4143 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4144 "trunc.w.%s<FMT> f<FD>, f<FS>"
4145 *mipsII:
4146 *mipsIII:
4147 *mipsIV:
4148 *mipsV:
4149 *vr4100:
4150 *vr5000:
4151 *r3900:
4152 {
4153   int fmt = FMT;
4154   check_fpu (SD_);
4155   check_fmt (SD_, fmt, instruction_0);
4156   StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
4157 }
4158
4159 \f
4160 //
4161 // MIPS Architecture:
4162 //
4163 //        System Control Instruction Set (COP0)
4164 //
4165
4166
4167 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4168 "bc0f <OFFSET>"
4169 *mipsI:
4170 *mipsII:
4171 *mipsIII:
4172 *mipsIV:
4173 *mipsV:
4174 *vr4100:
4175 *vr5000:
4176
4177 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4178 "bc0f <OFFSET>"
4179 // stub needed for eCos as tx39 hardware bug workaround
4180 *r3900:
4181 {
4182   /* do nothing */
4183 }
4184
4185
4186 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4187 "bc0fl <OFFSET>"
4188 *mipsI:
4189 *mipsII:
4190 *mipsIII:
4191 *mipsIV:
4192 *mipsV:
4193 *vr4100:
4194 *vr5000:
4195
4196
4197 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4198 "bc0t <OFFSET>"
4199 *mipsI:
4200 *mipsII:
4201 *mipsIII:
4202 *mipsIV:
4203 *mipsV:
4204 *vr4100:
4205
4206
4207 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4208 "bc0tl <OFFSET>"
4209 *mipsI:
4210 *mipsII:
4211 *mipsIII:
4212 *mipsIV:
4213 *mipsV:
4214 *vr4100:
4215 *vr5000:
4216
4217
4218 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4219 "cache <OP>, <OFFSET>(r<BASE>)"
4220 *mipsIII:
4221 *mipsIV:
4222 *mipsV:
4223 *vr4100:
4224 *vr5000:
4225 *r3900:
4226 {
4227   address_word base = GPR[BASE];
4228   address_word offset = EXTEND16 (OFFSET);
4229   {
4230     address_word vaddr = loadstore_ea (SD_, base, offset);
4231     address_word paddr;
4232     int uncached;
4233     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4234       CacheOp(OP,vaddr,paddr,instruction_0);
4235   }
4236 }
4237
4238
4239 010000,1,0000000000000000000,111001:COP0:32::DI
4240 "di"
4241 *mipsI:
4242 *mipsII:
4243 *mipsIII:
4244 *mipsIV:
4245 *mipsV:
4246 *vr4100:
4247 *vr5000:
4248
4249
4250 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4251 "dmfc0 r<RT>, r<RD>"
4252 *mipsIII:
4253 *mipsIV:
4254 *mipsV:
4255 {
4256   check_u64 (SD_, instruction_0);
4257   DecodeCoproc (instruction_0);
4258 }
4259
4260
4261 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4262 "dmtc0 r<RT>, r<RD>"
4263 *mipsIII:
4264 *mipsIV:
4265 *mipsV:
4266 {
4267   check_u64 (SD_, instruction_0);
4268   DecodeCoproc (instruction_0);
4269 }
4270
4271
4272 010000,1,0000000000000000000,111000:COP0:32::EI
4273 "ei"
4274 *mipsI:
4275 *mipsII:
4276 *mipsIII:
4277 *mipsIV:
4278 *mipsV:
4279 *vr4100:
4280 *vr5000:
4281
4282
4283 010000,1,0000000000000000000,011000:COP0:32::ERET
4284 "eret"
4285 *mipsIII:
4286 *mipsIV:
4287 *mipsV:
4288 *vr4100:
4289 *vr5000:
4290 {
4291   if (SR & status_ERL)
4292     {
4293       /* Oops, not yet available */
4294       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4295       NIA = EPC;
4296       SR &= ~status_ERL;
4297     }
4298   else
4299     {
4300       NIA = EPC;
4301       SR &= ~status_EXL;
4302     }
4303 }
4304
4305
4306 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4307 "mfc0 r<RT>, r<RD> # <REGX>"
4308 *mipsI:
4309 *mipsII:
4310 *mipsIII:
4311 *mipsIV:
4312 *mipsV:
4313 *vr4100:
4314 *vr5000:
4315 *r3900:
4316 {
4317   TRACE_ALU_INPUT0 ();
4318   DecodeCoproc (instruction_0);
4319   TRACE_ALU_RESULT (GPR[RT]);
4320 }
4321
4322 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4323 "mtc0 r<RT>, r<RD> # <REGX>"
4324 *mipsI:
4325 *mipsII:
4326 *mipsIII:
4327 *mipsIV:
4328 *mipsV:
4329 *vr4100:
4330 *vr5000:
4331 *r3900:
4332 {
4333   DecodeCoproc (instruction_0);
4334 }
4335
4336
4337 010000,1,0000000000000000000,010000:COP0:32::RFE
4338 "rfe"
4339 *mipsI:
4340 *mipsII:
4341 *mipsIII:
4342 *mipsIV:
4343 *mipsV:
4344 *vr4100:
4345 *vr5000:
4346 *r3900:
4347 {
4348   DecodeCoproc (instruction_0);
4349 }
4350
4351
4352 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4353 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
4354 *mipsI:
4355 *mipsII:
4356 *mipsIII:
4357 *mipsIV:
4358 *mipsV:
4359 *vr4100:
4360 *r3900:
4361 {
4362   DecodeCoproc (instruction_0);
4363 }
4364
4365
4366
4367 010000,1,0000000000000000000,001000:COP0:32::TLBP
4368 "tlbp"
4369 *mipsI:
4370 *mipsII:
4371 *mipsIII:
4372 *mipsIV:
4373 *mipsV:
4374 *vr4100:
4375 *vr5000:
4376
4377
4378 010000,1,0000000000000000000,000001:COP0:32::TLBR
4379 "tlbr"
4380 *mipsI:
4381 *mipsII:
4382 *mipsIII:
4383 *mipsIV:
4384 *mipsV:
4385 *vr4100:
4386 *vr5000:
4387
4388
4389 010000,1,0000000000000000000,000010:COP0:32::TLBWI
4390 "tlbwi"
4391 *mipsI:
4392 *mipsII:
4393 *mipsIII:
4394 *mipsIV:
4395 *mipsV:
4396 *vr4100:
4397 *vr5000:
4398
4399
4400 010000,1,0000000000000000000,000110:COP0:32::TLBWR
4401 "tlbwr"
4402 *mipsI:
4403 *mipsII:
4404 *mipsIII:
4405 *mipsIV:
4406 *mipsV:
4407 *vr4100:
4408 *vr5000:
4409
4410 \f
4411 :include:::m16.igen
4412 :include:::tx.igen
4413 :include:::vr.igen
4414 \f