sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips32r2:mipsisa32r2:
  49 :model:::mips64:mipsisa64:
  50 :model:::mips64r2:mipsisa64r2:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr4120:mips4120:
  61 :model:::vr5000:mips5000:
  62 :model:::vr5400:mips5400:
  63 :model:::vr5500:mips5500:
  64 :model:::r3900:mips3900:                // tx.igen
  65
  66 //  MIPS Application Specific Extensions (ASEs)
  67 //
  68 //  Instructions for the ASEs are in separate .igen files.
  69 //  ASEs add instructions on to a base ISA.
  70 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  71 :model:::mips16e:mips16e:               // m16e.igen
  72 :model:::mips3d:mips3d:                 // mips3d.igen
  73 :model:::mdmx:mdmx:                     // mdmx.igen
  74 :model:::dsp:dsp:                       // dsp.igen
  75
  76 //  Vendor Extensions
  77 //
  78 //  Instructions specific to these extensions are in separate .igen files.
  79 //  Extensions add instructions on to a base ISA.
  80 :model:::sb1:sb1:                       // sb1.igen
  81
  82
  83 // Pseudo instructions known by IGEN
  84 :internal::::illegal:
  85 {
  86   SignalException (ReservedInstruction, 0);
  87 }
  88
  89
  90 // Pseudo instructions known by interp.c
  91 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  92 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  93 "rsvd <OP>"
  94 {
  95   SignalException (ReservedInstruction, instruction_0);
  96 }
  97
  98
  99
 100 // Helper:
 101 //
 102 // Simulate a 32 bit delayslot instruction
 103 //
 104
 105 :function:::address_word:delayslot32:address_word target
 106 {
 107   instruction_word delay_insn;
 108   sim_events_slip (SD, 1);
 109   DSPC = CIA;
 110   CIA = CIA + 4; /* NOTE not mips16 */
 111   STATE |= simDELAYSLOT;
 112   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 113   ENGINE_ISSUE_PREFIX_HOOK();
 114   idecode_issue (CPU_, delay_insn, (CIA));
 115   STATE &= ~simDELAYSLOT;
 116   return target;
 117 }
 118
 119 :function:::address_word:nullify_next_insn32:
 120 {
 121   sim_events_slip (SD, 1);
 122   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 123   return CIA + 8;
 124 }
 125
 126
 127 // Helper:
 128 //
 129 // Calculate an effective address given a base and an offset.
 130 //
 131
 132 :function:::address_word:loadstore_ea:address_word base, address_word offset
 133 *mipsI:
 134 *mipsII:
 135 *mipsIII:
 136 *mipsIV:
 137 *mipsV:
 138 *mips32:
 139 *mips32r2:
 140 *vr4100:
 141 *vr5000:
 142 *r3900:
 143 {
 144   return base + offset;
 145 }
 146
 147 :function:::address_word:loadstore_ea:address_word base, address_word offset
 148 *mips64:
 149 *mips64r2:
 150 {
 151 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 152   /* If in user mode and UX is not set, use 32-bit compatibility effective
 153      address computations as defined in the MIPS64 Architecture for
 154      Programmers Volume III, Revision 0.95, section 4.9.  */
 155   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 156       == (ksu_user << status_KSU_shift))
 157     return (address_word)((signed32)base + (signed32)offset);
 158 #endif
 159   return base + offset;
 160 }
 161
 162
 163 // Helper:
 164 //
 165 // Check that a 32-bit register value is properly sign-extended.
 166 // (See NotWordValue in ISA spec.)
 167 //
 168
 169 :function:::int:not_word_value:unsigned_word value
 170 *mipsI:
 171 *mipsII:
 172 *mipsIII:
 173 *mipsIV:
 174 *mipsV:
 175 *vr4100:
 176 *vr5000:
 177 *r3900:
 178 {
 179   /* For historical simulator compatibility (until documentation is
 180      found that makes these operations unpredictable on some of these
 181      architectures), this check never returns true.  */
 182   return 0;
 183 }
 184
 185 :function:::int:not_word_value:unsigned_word value
 186 *mips32:
 187 *mips32r2:
 188 {
 189   /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
 190   return 0;
 191 }
 192
 193 :function:::int:not_word_value:unsigned_word value
 194 *mips64:
 195 *mips64r2:
 196 {
 197   return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
 198 }
 199
 200
 201 // Helper:
 202 //
 203 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 204 // theoretically portable code which invokes non-portable behaviour from
 205 // running with no indication of the portability issue.
 206 // (See definition of UNPREDICTABLE in ISA spec.)
 207 //
 208
 209 :function:::void:unpredictable:
 210 *mipsI:
 211 *mipsII:
 212 *mipsIII:
 213 *mipsIV:
 214 *mipsV:
 215 *vr4100:
 216 *vr5000:
 217 *r3900:
 218 {
 219 }
 220
 221 :function:::void:unpredictable:
 222 *mips32:
 223 *mips32r2:
 224 *mips64:
 225 *mips64r2:
 226 {
 227   unpredictable_action (CPU, CIA);
 228 }
 229
 230
 231 // Helpers:
 232 //
 233 // Check that an access to a HI/LO register meets timing requirements
 234 //
 235 // In all MIPS ISAs,
 236 //
 237 //      OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
 238 //      makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
 239 //
 240 // The following restrictions exist for MIPS I - MIPS III:
 241 //
 242 //      MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
 243 //      in between makes MF UNPREDICTABLE. (2)
 244 //
 245 //      MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
 246 //      in between makes MF UNPREDICTABLE. (3)
 247 //
 248 // On the r3900, restriction (2) is not present, and restriction (3) is not
 249 // present for multiplication.
 250 //
 251 // Unfortunately, there seems to be some confusion about whether the last
 252 // two restrictions should apply to "MIPS IV" as well.  One edition of
 253 // the MIPS IV ISA says they do, but references in later ISA documents
 254 // suggest they don't.
 255 //
 256 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
 257 // these restrictions, while others, like the VR5500, don't.  To accomodate
 258 // such differences, the MIPS IV and MIPS V version of these helper functions
 259 // use auxillary routines to determine whether the restriction applies.
 260
 261 // check_mf_cycles:
 262 //
 263 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
 264 // to check for restrictions (2) and (3) above.
 265 //
 266 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 267 {
 268   if (history->mf.timestamp + 3 > time)
 269     {
 270       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 271                         itable[MY_INDEX].name,
 272                         new, (long) CIA,
 273                         (long) history->mf.cia);
 274       return 0;
 275     }
 276   return 1;
 277 }
 278
 279
 280 // check_mt_hilo:
 281 //
 282 // Check for restriction (2) above (for ISAs/processors that have it),
 283 // and record timestamps for restriction (1) above.
 284 //
 285 :function:::int:check_mt_hilo:hilo_history *history
 286 *mipsI:
 287 *mipsII:
 288 *mipsIII:
 289 *vr4100:
 290 *vr5000:
 291 {
 292   signed64 time = sim_events_time (SD);
 293   int ok = check_mf_cycles (SD_, history, time, "MT");
 294   history->mt.timestamp = time;
 295   history->mt.cia = CIA;
 296   return ok;
 297 }
 298
 299 :function:::int:check_mt_hilo:hilo_history *history
 300 *mipsIV:
 301 *mipsV:
 302 {
 303   signed64 time = sim_events_time (SD);
 304   int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
 305             || check_mf_cycles (SD_, history, time, "MT"));
 306   history->mt.timestamp = time;
 307   history->mt.cia = CIA;
 308   return ok;
 309 }
 310
 311 :function:::int:check_mt_hilo:hilo_history *history
 312 *mips32:
 313 *mips32r2:
 314 *mips64:
 315 *mips64r2:
 316 *r3900:
 317 {
 318   signed64 time = sim_events_time (SD);
 319   history->mt.timestamp = time;
 320   history->mt.cia = CIA;
 321   return 1;
 322 }
 323
 324
 325 // check_mf_hilo:
 326 //
 327 // Check for restriction (1) above, and record timestamps for
 328 // restriction (2) and (3) above.
 329 //
 330 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 331 *mipsI:
 332 *mipsII:
 333 *mipsIII:
 334 *mipsIV:
 335 *mipsV:
 336 *mips32:
 337 *mips32r2:
 338 *mips64:
 339 *mips64r2:
 340 *vr4100:
 341 *vr5000:
 342 *r3900:
 343 {
 344   signed64 time = sim_events_time (SD);
 345   int ok = 1;
 346   if (peer != NULL
 347       && peer->mt.timestamp > history->op.timestamp
 348       && history->mt.timestamp < history->op.timestamp
 349       && ! (history->mf.timestamp > history->op.timestamp
 350             && history->mf.timestamp < peer->mt.timestamp)
 351       && ! (peer->mf.timestamp > history->op.timestamp
 352             && peer->mf.timestamp < peer->mt.timestamp))
 353     {
 354       /* The peer has been written to since the last OP yet we have
 355          not */
 356       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 357                         itable[MY_INDEX].name,
 358                         (long) CIA,
 359                         (long) history->op.cia,
 360                         (long) peer->mt.cia);
 361       ok = 0;
 362     }
 363   history->mf.timestamp = time;
 364   history->mf.cia = CIA;
 365   return ok;
 366 }
 367
 368
 369
 370 // check_mult_hilo:
 371 //
 372 // Check for restriction (3) above (for ISAs/processors that have it)
 373 // for MULT ops, and record timestamps for restriction (1) above.
 374 //
 375 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 376 *mipsI:
 377 *mipsII:
 378 *mipsIII:
 379 *vr4100:
 380 *vr5000:
 381 {
 382   signed64 time = sim_events_time (SD);
 383   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 384             && check_mf_cycles (SD_, lo, time, "OP"));
 385   hi->op.timestamp = time;
 386   lo->op.timestamp = time;
 387   hi->op.cia = CIA;
 388   lo->op.cia = CIA;
 389   return ok;
 390 }
 391
 392 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 393 *mipsIV:
 394 *mipsV:
 395 {
 396   signed64 time = sim_events_time (SD);
 397   int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
 398             || (check_mf_cycles (SD_, hi, time, "OP")
 399                 && check_mf_cycles (SD_, lo, time, "OP")));
 400   hi->op.timestamp = time;
 401   lo->op.timestamp = time;
 402   hi->op.cia = CIA;
 403   lo->op.cia = CIA;
 404   return ok;
 405 }
 406
 407 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 408 *mips32:
 409 *mips32r2:
 410 *mips64:
 411 *mips64r2:
 412 *r3900:
 413 {
 414   /* FIXME: could record the fact that a stall occured if we want */
 415   signed64 time = sim_events_time (SD);
 416   hi->op.timestamp = time;
 417   lo->op.timestamp = time;
 418   hi->op.cia = CIA;
 419   lo->op.cia = CIA;
 420   return 1;
 421 }
 422
 423
 424 // check_div_hilo:
 425 //
 426 // Check for restriction (3) above (for ISAs/processors that have it)
 427 // for DIV ops, and record timestamps for restriction (1) above.
 428 //
 429 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 430 *mipsI:
 431 *mipsII:
 432 *mipsIII:
 433 *vr4100:
 434 *vr5000:
 435 *r3900:
 436 {
 437   signed64 time = sim_events_time (SD);
 438   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 439             && check_mf_cycles (SD_, lo, time, "OP"));
 440   hi->op.timestamp = time;
 441   lo->op.timestamp = time;
 442   hi->op.cia = CIA;
 443   lo->op.cia = CIA;
 444   return ok;
 445 }
 446
 447 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 448 *mipsIV:
 449 *mipsV:
 450 {
 451   signed64 time = sim_events_time (SD);
 452   int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
 453             || (check_mf_cycles (SD_, hi, time, "OP")
 454                 && check_mf_cycles (SD_, lo, time, "OP")));
 455   hi->op.timestamp = time;
 456   lo->op.timestamp = time;
 457   hi->op.cia = CIA;
 458   lo->op.cia = CIA;
 459   return ok;
 460 }
 461
 462 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 463 *mips32:
 464 *mips32r2:
 465 *mips64:
 466 *mips64r2:
 467 {
 468   signed64 time = sim_events_time (SD);
 469   hi->op.timestamp = time;
 470   lo->op.timestamp = time;
 471   hi->op.cia = CIA;
 472   lo->op.cia = CIA;
 473   return 1;
 474 }
 475
 476
 477 // Helper:
 478 //
 479 // Check that the 64-bit instruction can currently be used, and signal
 480 // a ReservedInstruction exception if not.
 481 //
 482
 483 :function:::void:check_u64:instruction_word insn
 484 *mipsIII:
 485 *mipsIV:
 486 *mipsV:
 487 *vr4100:
 488 *vr5000:
 489 *vr5400:
 490 *vr5500:
 491 {
 492   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 493 }
 494
 495 :function:::void:check_u64:instruction_word insn
 496 *mips16e:
 497 *mips64:
 498 *mips64r2:
 499 {
 500 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 501   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 502     SignalException (ReservedInstruction, insn);
 503 #endif
 504 }
 505
 506
 507
 508 //
 509 // MIPS Architecture:
 510 //
 511 //        CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
 512 //
 513
 514
 515
 516 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 517 "add r<RD>, r<RS>, r<RT>"
 518 *mipsI:
 519 *mipsII:
 520 *mipsIII:
 521 *mipsIV:
 522 *mipsV:
 523 *mips32:
 524 *mips32r2:
 525 *mips64:
 526 *mips64r2:
 527 *vr4100:
 528 *vr5000:
 529 *r3900:
 530 {
 531   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 532     Unpredictable ();
 533   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 534   {
 535     ALU32_BEGIN (GPR[RS]);
 536     ALU32_ADD (GPR[RT]);
 537     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 538   }
 539   TRACE_ALU_RESULT (GPR[RD]);
 540 }
 541
 542
 543
 544 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 545 "addi r<RT>, r<RS>, <IMMEDIATE>"
 546 *mipsI:
 547 *mipsII:
 548 *mipsIII:
 549 *mipsIV:
 550 *mipsV:
 551 *mips32:
 552 *mips32r2:
 553 *mips64:
 554 *mips64r2:
 555 *vr4100:
 556 *vr5000:
 557 *r3900:
 558 {
 559   if (NotWordValue (GPR[RS]))
 560     Unpredictable ();
 561   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 562   {
 563     ALU32_BEGIN (GPR[RS]);
 564     ALU32_ADD (EXTEND16 (IMMEDIATE));
 565     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 566   }
 567   TRACE_ALU_RESULT (GPR[RT]);
 568 }
 569
 570
 571
 572 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 573 {
 574   if (NotWordValue (GPR[rs]))
 575     Unpredictable ();
 576   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 577   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 578   TRACE_ALU_RESULT (GPR[rt]);
 579 }
 580
 581 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 582 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 583 *mipsI:
 584 *mipsII:
 585 *mipsIII:
 586 *mipsIV:
 587 *mipsV:
 588 *mips32:
 589 *mips32r2:
 590 *mips64:
 591 *mips64r2:
 592 *vr4100:
 593 *vr5000:
 594 *r3900:
 595 {
 596   do_addiu (SD_, RS, RT, IMMEDIATE);
 597 }
 598
 599
 600
 601 :function:::void:do_addu:int rs, int rt, int rd
 602 {
 603   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 604     Unpredictable ();
 605   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 606   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 607   TRACE_ALU_RESULT (GPR[rd]);
 608 }
 609
 610 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 611 "addu r<RD>, r<RS>, r<RT>"
 612 *mipsI:
 613 *mipsII:
 614 *mipsIII:
 615 *mipsIV:
 616 *mipsV:
 617 *mips32:
 618 *mips32r2:
 619 *mips64:
 620 *mips64r2:
 621 *vr4100:
 622 *vr5000:
 623 *r3900:
 624 {
 625   do_addu (SD_, RS, RT, RD);
 626 }
 627
 628
 629
 630 :function:::void:do_and:int rs, int rt, int rd
 631 {
 632   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 633   GPR[rd] = GPR[rs] & GPR[rt];
 634   TRACE_ALU_RESULT (GPR[rd]);
 635 }
 636
 637 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 638 "and r<RD>, r<RS>, r<RT>"
 639 *mipsI:
 640 *mipsII:
 641 *mipsIII:
 642 *mipsIV:
 643 *mipsV:
 644 *mips32:
 645 *mips32r2:
 646 *mips64:
 647 *mips64r2:
 648 *vr4100:
 649 *vr5000:
 650 *r3900:
 651 {
 652   do_and (SD_, RS, RT, RD);
 653 }
 654
 655
 656
 657 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 658 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 659 *mipsI:
 660 *mipsII:
 661 *mipsIII:
 662 *mipsIV:
 663 *mipsV:
 664 *mips32:
 665 *mips32r2:
 666 *mips64:
 667 *mips64r2:
 668 *vr4100:
 669 *vr5000:
 670 *r3900:
 671 {
 672   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 673   GPR[RT] = GPR[RS] & IMMEDIATE;
 674   TRACE_ALU_RESULT (GPR[RT]);
 675 }
 676
 677
 678
 679 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 680 "beq r<RS>, r<RT>, <OFFSET>"
 681 *mipsI:
 682 *mipsII:
 683 *mipsIII:
 684 *mipsIV:
 685 *mipsV:
 686 *mips32:
 687 *mips32r2:
 688 *mips64:
 689 *mips64r2:
 690 *vr4100:
 691 *vr5000:
 692 *r3900:
 693 {
 694   address_word offset = EXTEND16 (OFFSET) << 2;
 695   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 696     {
 697       DELAY_SLOT (NIA + offset);
 698     }
 699 }
 700
 701
 702
 703 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 704 "beql r<RS>, r<RT>, <OFFSET>"
 705 *mipsII:
 706 *mipsIII:
 707 *mipsIV:
 708 *mipsV:
 709 *mips32:
 710 *mips32r2:
 711 *mips64:
 712 *mips64r2:
 713 *vr4100:
 714 *vr5000:
 715 *r3900:
 716 {
 717   address_word offset = EXTEND16 (OFFSET) << 2;
 718   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 719     {
 720       DELAY_SLOT (NIA + offset);
 721     }
 722   else
 723     NULLIFY_NEXT_INSTRUCTION ();
 724 }
 725
 726
 727
 728 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 729 "bgez r<RS>, <OFFSET>"
 730 *mipsI:
 731 *mipsII:
 732 *mipsIII:
 733 *mipsIV:
 734 *mipsV:
 735 *mips32:
 736 *mips32r2:
 737 *mips64:
 738 *mips64r2:
 739 *vr4100:
 740 *vr5000:
 741 *r3900:
 742 {
 743   address_word offset = EXTEND16 (OFFSET) << 2;
 744   if ((signed_word) GPR[RS] >= 0)
 745     {
 746       DELAY_SLOT (NIA + offset);
 747     }
 748 }
 749
 750
 751
 752 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 753 "bgezal r<RS>, <OFFSET>"
 754 *mipsI:
 755 *mipsII:
 756 *mipsIII:
 757 *mipsIV:
 758 *mipsV:
 759 *mips32:
 760 *mips32r2:
 761 *mips64:
 762 *mips64r2:
 763 *vr4100:
 764 *vr5000:
 765 *r3900:
 766 {
 767   address_word offset = EXTEND16 (OFFSET) << 2;
 768   if (RS == 31)
 769     Unpredictable ();
 770   RA = (CIA + 8);
 771   if ((signed_word) GPR[RS] >= 0)
 772     {
 773       DELAY_SLOT (NIA + offset);
 774     }
 775 }
 776
 777
 778
 779 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 780 "bgezall r<RS>, <OFFSET>"
 781 *mipsII:
 782 *mipsIII:
 783 *mipsIV:
 784 *mipsV:
 785 *mips32:
 786 *mips32r2:
 787 *mips64:
 788 *mips64r2:
 789 *vr4100:
 790 *vr5000:
 791 *r3900:
 792 {
 793   address_word offset = EXTEND16 (OFFSET) << 2;
 794   if (RS == 31)
 795     Unpredictable ();
 796   RA = (CIA + 8);
 797   /* NOTE: The branch occurs AFTER the next instruction has been
 798      executed */
 799   if ((signed_word) GPR[RS] >= 0)
 800     {
 801       DELAY_SLOT (NIA + offset);
 802     }
 803   else
 804     NULLIFY_NEXT_INSTRUCTION ();
 805 }
 806
 807
 808
 809 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 810 "bgezl r<RS>, <OFFSET>"
 811 *mipsII:
 812 *mipsIII:
 813 *mipsIV:
 814 *mipsV:
 815 *mips32:
 816 *mips32r2:
 817 *mips64:
 818 *mips64r2:
 819 *vr4100:
 820 *vr5000:
 821 *r3900:
 822 {
 823   address_word offset = EXTEND16 (OFFSET) << 2;
 824   if ((signed_word) GPR[RS] >= 0)
 825     {
 826       DELAY_SLOT (NIA + offset);
 827     }
 828   else
 829     NULLIFY_NEXT_INSTRUCTION ();
 830 }
 831
 832
 833
 834 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 835 "bgtz r<RS>, <OFFSET>"
 836 *mipsI:
 837 *mipsII:
 838 *mipsIII:
 839 *mipsIV:
 840 *mipsV:
 841 *mips32:
 842 *mips32r2:
 843 *mips64:
 844 *mips64r2:
 845 *vr4100:
 846 *vr5000:
 847 *r3900:
 848 {
 849   address_word offset = EXTEND16 (OFFSET) << 2;
 850   if ((signed_word) GPR[RS] > 0)
 851     {
 852       DELAY_SLOT (NIA + offset);
 853     }
 854 }
 855
 856
 857
 858 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 859 "bgtzl r<RS>, <OFFSET>"
 860 *mipsII:
 861 *mipsIII:
 862 *mipsIV:
 863 *mipsV:
 864 *mips32:
 865 *mips32r2:
 866 *mips64:
 867 *mips64r2:
 868 *vr4100:
 869 *vr5000:
 870 *r3900:
 871 {
 872   address_word offset = EXTEND16 (OFFSET) << 2;
 873   /* NOTE: The branch occurs AFTER the next instruction has been
 874      executed */
 875   if ((signed_word) GPR[RS] > 0)
 876     {
 877       DELAY_SLOT (NIA + offset);
 878     }
 879   else
 880     NULLIFY_NEXT_INSTRUCTION ();
 881 }
 882
 883
 884
 885 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 886 "blez r<RS>, <OFFSET>"
 887 *mipsI:
 888 *mipsII:
 889 *mipsIII:
 890 *mipsIV:
 891 *mipsV:
 892 *mips32:
 893 *mips32r2:
 894 *mips64:
 895 *mips64r2:
 896 *vr4100:
 897 *vr5000:
 898 *r3900:
 899 {
 900   address_word offset = EXTEND16 (OFFSET) << 2;
 901   /* NOTE: The branch occurs AFTER the next instruction has been
 902      executed */
 903   if ((signed_word) GPR[RS] <= 0)
 904     {
 905       DELAY_SLOT (NIA + offset);
 906     }
 907 }
 908
 909
 910
 911 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 912 "bgezl r<RS>, <OFFSET>"
 913 *mipsII:
 914 *mipsIII:
 915 *mipsIV:
 916 *mipsV:
 917 *mips32:
 918 *mips32r2:
 919 *mips64:
 920 *mips64r2:
 921 *vr4100:
 922 *vr5000:
 923 *r3900:
 924 {
 925   address_word offset = EXTEND16 (OFFSET) << 2;
 926   if ((signed_word) GPR[RS] <= 0)
 927     {
 928       DELAY_SLOT (NIA + offset);
 929     }
 930   else
 931     NULLIFY_NEXT_INSTRUCTION ();
 932 }
 933
 934
 935
 936 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 937 "bltz r<RS>, <OFFSET>"
 938 *mipsI:
 939 *mipsII:
 940 *mipsIII:
 941 *mipsIV:
 942 *mipsV:
 943 *mips32:
 944 *mips32r2:
 945 *mips64:
 946 *mips64r2:
 947 *vr4100:
 948 *vr5000:
 949 *r3900:
 950 {
 951   address_word offset = EXTEND16 (OFFSET) << 2;
 952   if ((signed_word) GPR[RS] < 0)
 953     {
 954       DELAY_SLOT (NIA + offset);
 955     }
 956 }
 957
 958
 959
 960 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 961 "bltzal r<RS>, <OFFSET>"
 962 *mipsI:
 963 *mipsII:
 964 *mipsIII:
 965 *mipsIV:
 966 *mipsV:
 967 *mips32:
 968 *mips32r2:
 969 *mips64:
 970 *mips64r2:
 971 *vr4100:
 972 *vr5000:
 973 *r3900:
 974 {
 975   address_word offset = EXTEND16 (OFFSET) << 2;
 976   if (RS == 31)
 977     Unpredictable ();
 978   RA = (CIA + 8);
 979   /* NOTE: The branch occurs AFTER the next instruction has been
 980      executed */
 981   if ((signed_word) GPR[RS] < 0)
 982     {
 983       DELAY_SLOT (NIA + offset);
 984     }
 985 }
 986
 987
 988
 989 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 990 "bltzall r<RS>, <OFFSET>"
 991 *mipsII:
 992 *mipsIII:
 993 *mipsIV:
 994 *mipsV:
 995 *mips32:
 996 *mips32r2:
 997 *mips64:
 998 *mips64r2:
 999 *vr4100:
1000 *vr5000:
1001 *r3900:
1002 {
1003   address_word offset = EXTEND16 (OFFSET) << 2;
1004   if (RS == 31)
1005     Unpredictable ();
1006   RA = (CIA + 8);
1007   if ((signed_word) GPR[RS] < 0)
1008     {
1009       DELAY_SLOT (NIA + offset);
1010     }
1011   else
1012     NULLIFY_NEXT_INSTRUCTION ();
1013 }
1014
1015
1016
1017 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1018 "bltzl r<RS>, <OFFSET>"
1019 *mipsII:
1020 *mipsIII:
1021 *mipsIV:
1022 *mipsV:
1023 *mips32:
1024 *mips32r2:
1025 *mips64:
1026 *mips64r2:
1027 *vr4100:
1028 *vr5000:
1029 *r3900:
1030 {
1031   address_word offset = EXTEND16 (OFFSET) << 2;
1032   /* NOTE: The branch occurs AFTER the next instruction has been
1033      executed */
1034   if ((signed_word) GPR[RS] < 0)
1035     {
1036       DELAY_SLOT (NIA + offset);
1037     }
1038   else
1039     NULLIFY_NEXT_INSTRUCTION ();
1040 }
1041
1042
1043
1044 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1045 "bne r<RS>, r<RT>, <OFFSET>"
1046 *mipsI:
1047 *mipsII:
1048 *mipsIII:
1049 *mipsIV:
1050 *mipsV:
1051 *mips32:
1052 *mips32r2:
1053 *mips64:
1054 *mips64r2:
1055 *vr4100:
1056 *vr5000:
1057 *r3900:
1058 {
1059   address_word offset = EXTEND16 (OFFSET) << 2;
1060   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1061     {
1062       DELAY_SLOT (NIA + offset);
1063     }
1064 }
1065
1066
1067
1068 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1069 "bnel r<RS>, r<RT>, <OFFSET>"
1070 *mipsII:
1071 *mipsIII:
1072 *mipsIV:
1073 *mipsV:
1074 *mips32:
1075 *mips32r2:
1076 *mips64:
1077 *mips64r2:
1078 *vr4100:
1079 *vr5000:
1080 *r3900:
1081 {
1082   address_word offset = EXTEND16 (OFFSET) << 2;
1083   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1084     {
1085       DELAY_SLOT (NIA + offset);
1086     }
1087   else
1088     NULLIFY_NEXT_INSTRUCTION ();
1089 }
1090
1091
1092
1093 000000,20.CODE,001101:SPECIAL:32::BREAK
1094 "break %#lx<CODE>"
1095 *mipsI:
1096 *mipsII:
1097 *mipsIII:
1098 *mipsIV:
1099 *mipsV:
1100 *mips32:
1101 *mips32r2:
1102 *mips64:
1103 *mips64r2:
1104 *vr4100:
1105 *vr5000:
1106 *r3900:
1107 {
1108   /* Check for some break instruction which are reserved for use by the simulator.  */
1109   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1110   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1111       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1112     {
1113       sim_engine_halt (SD, CPU, NULL, cia,
1114                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1115     }
1116   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1117            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1118     {
1119       if (STATE & simDELAYSLOT)
1120         PC = cia - 4; /* reference the branch instruction */
1121       else
1122         PC = cia;
1123       SignalException (BreakPoint, instruction_0);
1124     }
1125
1126   else
1127     {
1128       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1129          the exception. */
1130       SignalException (BreakPoint, instruction_0);
1131     }
1132 }
1133
1134
1135
1136 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1137 "clo r<RD>, r<RS>"
1138 *mips32:
1139 *mips32r2:
1140 *mips64:
1141 *mips64r2:
1142 *vr5500:
1143 {
1144   unsigned32 temp = GPR[RS];
1145   unsigned32 i, mask;
1146   if (RT != RD)
1147     Unpredictable ();
1148   if (NotWordValue (GPR[RS]))
1149     Unpredictable ();
1150   TRACE_ALU_INPUT1 (GPR[RS]);
1151   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1152     {
1153       if ((temp & mask) == 0)
1154         break;
1155       mask >>= 1;
1156     }
1157   GPR[RD] = EXTEND32 (i);
1158   TRACE_ALU_RESULT (GPR[RD]);
1159 }
1160
1161
1162
1163 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1164 "clz r<RD>, r<RS>"
1165 *mips32:
1166 *mips32r2:
1167 *mips64:
1168 *mips64r2:
1169 *vr5500:
1170 {
1171   unsigned32 temp = GPR[RS];
1172   unsigned32 i, mask;
1173   if (RT != RD)
1174     Unpredictable ();
1175   if (NotWordValue (GPR[RS]))
1176     Unpredictable ();
1177   TRACE_ALU_INPUT1 (GPR[RS]);
1178   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1179     {
1180       if ((temp & mask) != 0)
1181         break;
1182       mask >>= 1;
1183     }
1184   GPR[RD] = EXTEND32 (i);
1185   TRACE_ALU_RESULT (GPR[RD]);
1186 }
1187
1188
1189
1190 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1191 "dadd r<RD>, r<RS>, r<RT>"
1192 *mipsIII:
1193 *mipsIV:
1194 *mipsV:
1195 *mips64:
1196 *mips64r2:
1197 *vr4100:
1198 *vr5000:
1199 {
1200   check_u64 (SD_, instruction_0);
1201   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1202   {
1203     ALU64_BEGIN (GPR[RS]);
1204     ALU64_ADD (GPR[RT]);
1205     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1206   }
1207   TRACE_ALU_RESULT (GPR[RD]);
1208 }
1209
1210
1211
1212 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1213 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1214 *mipsIII:
1215 *mipsIV:
1216 *mipsV:
1217 *mips64:
1218 *mips64r2:
1219 *vr4100:
1220 *vr5000:
1221 {
1222   check_u64 (SD_, instruction_0);
1223   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1224   {
1225     ALU64_BEGIN (GPR[RS]);
1226     ALU64_ADD (EXTEND16 (IMMEDIATE));
1227     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1228   }
1229   TRACE_ALU_RESULT (GPR[RT]);
1230 }
1231
1232
1233
1234 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1235 {
1236   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1237   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1238   TRACE_ALU_RESULT (GPR[rt]);
1239 }
1240
1241 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1242 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1243 *mipsIII:
1244 *mipsIV:
1245 *mipsV:
1246 *mips64:
1247 *mips64r2:
1248 *vr4100:
1249 *vr5000:
1250 {
1251   check_u64 (SD_, instruction_0);
1252   do_daddiu (SD_, RS, RT, IMMEDIATE);
1253 }
1254
1255
1256
1257 :function:::void:do_daddu:int rs, int rt, int rd
1258 {
1259   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1260   GPR[rd] = GPR[rs] + GPR[rt];
1261   TRACE_ALU_RESULT (GPR[rd]);
1262 }
1263
1264 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1265 "daddu r<RD>, r<RS>, r<RT>"
1266 *mipsIII:
1267 *mipsIV:
1268 *mipsV:
1269 *mips64:
1270 *mips64r2:
1271 *vr4100:
1272 *vr5000:
1273 {
1274   check_u64 (SD_, instruction_0);
1275   do_daddu (SD_, RS, RT, RD);
1276 }
1277
1278
1279
1280 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1281 "dclo r<RD>, r<RS>"
1282 *mips64:
1283 *mips64r2:
1284 *vr5500:
1285 {
1286   unsigned64 temp = GPR[RS];
1287   unsigned32 i;
1288   unsigned64 mask;
1289   check_u64 (SD_, instruction_0);
1290   if (RT != RD)
1291     Unpredictable ();
1292   TRACE_ALU_INPUT1 (GPR[RS]);
1293   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1294     {
1295       if ((temp & mask) == 0)
1296         break;
1297       mask >>= 1;
1298     }
1299   GPR[RD] = EXTEND32 (i);
1300   TRACE_ALU_RESULT (GPR[RD]);
1301 }
1302
1303
1304
1305 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1306 "dclz r<RD>, r<RS>"
1307 *mips64:
1308 *mips64r2:
1309 *vr5500:
1310 {
1311   unsigned64 temp = GPR[RS];
1312   unsigned32 i;
1313   unsigned64 mask;
1314   check_u64 (SD_, instruction_0);
1315   if (RT != RD)
1316     Unpredictable ();
1317   TRACE_ALU_INPUT1 (GPR[RS]);
1318   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1319     {
1320       if ((temp & mask) != 0)
1321         break;
1322       mask >>= 1;
1323     }
1324   GPR[RD] = EXTEND32 (i);
1325   TRACE_ALU_RESULT (GPR[RD]);
1326 }
1327
1328
1329
1330 :function:::void:do_ddiv:int rs, int rt
1331 {
1332   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1333   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1334   {
1335     signed64 n = GPR[rs];
1336     signed64 d = GPR[rt];
1337     signed64 hi;
1338     signed64 lo;
1339     if (d == 0)
1340       {
1341         lo = SIGNED64 (0x8000000000000000);
1342         hi = 0;
1343       }
1344     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1345       {
1346         lo = SIGNED64 (0x8000000000000000);
1347         hi = 0;
1348       }
1349     else
1350       {
1351         lo = (n / d);
1352         hi = (n % d);
1353       }
1354     HI = hi;
1355     LO = lo;
1356   }
1357   TRACE_ALU_RESULT2 (HI, LO);
1358 }
1359
1360 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1361 "ddiv r<RS>, r<RT>"
1362 *mipsIII:
1363 *mipsIV:
1364 *mipsV:
1365 *mips64:
1366 *mips64r2:
1367 *vr4100:
1368 *vr5000:
1369 {
1370   check_u64 (SD_, instruction_0);
1371   do_ddiv (SD_, RS, RT);
1372 }
1373
1374
1375
1376 :function:::void:do_ddivu:int rs, int rt
1377 {
1378   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1379   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1380   {
1381     unsigned64 n = GPR[rs];
1382     unsigned64 d = GPR[rt];
1383     unsigned64 hi;
1384     unsigned64 lo;
1385     if (d == 0)
1386       {
1387         lo = SIGNED64 (0x8000000000000000);
1388         hi = 0;
1389       }
1390     else
1391       {
1392         lo = (n / d);
1393         hi = (n % d);
1394       }
1395     HI = hi;
1396     LO = lo;
1397   }
1398   TRACE_ALU_RESULT2 (HI, LO);
1399 }
1400
1401 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1402 "ddivu r<RS>, r<RT>"
1403 *mipsIII:
1404 *mipsIV:
1405 *mipsV:
1406 *mips64:
1407 *mips64r2:
1408 *vr4100:
1409 *vr5000:
1410 {
1411   check_u64 (SD_, instruction_0);
1412   do_ddivu (SD_, RS, RT);
1413 }
1414
1415 :function:::void:do_div:int rs, int rt
1416 {
1417   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1418   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1419   {
1420     signed32 n = GPR[rs];
1421     signed32 d = GPR[rt];
1422     if (d == 0)
1423       {
1424         LO = EXTEND32 (0x80000000);
1425         HI = EXTEND32 (0);
1426       }
1427     else if (n == SIGNED32 (0x80000000) && d == -1)
1428       {
1429         LO = EXTEND32 (0x80000000);
1430         HI = EXTEND32 (0);
1431       }
1432     else
1433       {
1434         LO = EXTEND32 (n / d);
1435         HI = EXTEND32 (n % d);
1436       }
1437   }
1438   TRACE_ALU_RESULT2 (HI, LO);
1439 }
1440
1441 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1442 "div r<RS>, r<RT>"
1443 *mipsI:
1444 *mipsII:
1445 *mipsIII:
1446 *mipsIV:
1447 *mipsV:
1448 *mips32:
1449 *mips32r2:
1450 *mips64:
1451 *mips64r2:
1452 *vr4100:
1453 *vr5000:
1454 *r3900:
1455 {
1456   do_div (SD_, RS, RT);
1457 }
1458
1459
1460
1461 :function:::void:do_divu:int rs, int rt
1462 {
1463   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1464   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1465   {
1466     unsigned32 n = GPR[rs];
1467     unsigned32 d = GPR[rt];
1468     if (d == 0)
1469       {
1470         LO = EXTEND32 (0x80000000);
1471         HI = EXTEND32 (0);
1472       }
1473     else
1474       {
1475         LO = EXTEND32 (n / d);
1476         HI = EXTEND32 (n % d);
1477       }
1478   }
1479   TRACE_ALU_RESULT2 (HI, LO);
1480 }
1481
1482 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1483 "divu r<RS>, r<RT>"
1484 *mipsI:
1485 *mipsII:
1486 *mipsIII:
1487 *mipsIV:
1488 *mipsV:
1489 *mips32:
1490 *mips32r2:
1491 *mips64:
1492 *mips64r2:
1493 *vr4100:
1494 *vr5000:
1495 *r3900:
1496 {
1497   do_divu (SD_, RS, RT);
1498 }
1499
1500
1501 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1502 {
1503   unsigned64 lo;
1504   unsigned64 hi;
1505   unsigned64 m00;
1506   unsigned64 m01;
1507   unsigned64 m10;
1508   unsigned64 m11;
1509   unsigned64 mid;
1510   int sign;
1511   unsigned64 op1 = GPR[rs];
1512   unsigned64 op2 = GPR[rt];
1513   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1514   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1515   /* make signed multiply unsigned */
1516   sign = 0;
1517   if (signed_p)
1518     {
1519       if ((signed64) op1 < 0)
1520         {
1521           op1 = - op1;
1522           ++sign;
1523         }
1524       if ((signed64) op2 < 0)
1525         {
1526           op2 = - op2;
1527           ++sign;
1528         }
1529     }
1530   /* multiply out the 4 sub products */
1531   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1532   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1533   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1534   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1535   /* add the products */
1536   mid = ((unsigned64) VH4_8 (m00)
1537          + (unsigned64) VL4_8 (m10)
1538          + (unsigned64) VL4_8 (m01));
1539   lo = U8_4 (mid, m00);
1540   hi = (m11
1541         + (unsigned64) VH4_8 (mid)
1542         + (unsigned64) VH4_8 (m01)
1543         + (unsigned64) VH4_8 (m10));
1544   /* fix the sign */
1545   if (sign & 1)
1546     {
1547       lo = -lo;
1548       if (lo == 0)
1549         hi = -hi;
1550       else
1551         hi = -hi - 1;
1552     }
1553   /* save the result HI/LO (and a gpr) */
1554   LO = lo;
1555   HI = hi;
1556   if (rd != 0)
1557     GPR[rd] = lo;
1558   TRACE_ALU_RESULT2 (HI, LO);
1559 }
1560
1561 :function:::void:do_dmult:int rs, int rt, int rd
1562 {
1563   do_dmultx (SD_, rs, rt, rd, 1);
1564 }
1565
1566 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1567 "dmult r<RS>, r<RT>"
1568 *mipsIII:
1569 *mipsIV:
1570 *mipsV:
1571 *mips64:
1572 *mips64r2:
1573 *vr4100:
1574 {
1575   check_u64 (SD_, instruction_0);
1576   do_dmult (SD_, RS, RT, 0);
1577 }
1578
1579 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1580 "dmult r<RS>, r<RT>":RD == 0
1581 "dmult r<RD>, r<RS>, r<RT>"
1582 *vr5000:
1583 {
1584   check_u64 (SD_, instruction_0);
1585   do_dmult (SD_, RS, RT, RD);
1586 }
1587
1588
1589
1590 :function:::void:do_dmultu:int rs, int rt, int rd
1591 {
1592   do_dmultx (SD_, rs, rt, rd, 0);
1593 }
1594
1595 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1596 "dmultu r<RS>, r<RT>"
1597 *mipsIII:
1598 *mipsIV:
1599 *mipsV:
1600 *mips64:
1601 *mips64r2:
1602 *vr4100:
1603 {
1604   check_u64 (SD_, instruction_0);
1605   do_dmultu (SD_, RS, RT, 0);
1606 }
1607
1608 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1609 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1610 "dmultu r<RS>, r<RT>"
1611 *vr5000:
1612 {
1613   check_u64 (SD_, instruction_0);
1614   do_dmultu (SD_, RS, RT, RD);
1615 }
1616
1617
1618 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1619 {
1620   unsigned64 result;
1621
1622   y &= 63;
1623   TRACE_ALU_INPUT2 (x, y);
1624   result = ROTR64 (x, y);
1625   TRACE_ALU_RESULT (result);
1626   return result;
1627 }
1628
1629 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1630 "dror r<RD>, r<RT>, <SHIFT>"
1631 *mips64r2:
1632 *vr5400:
1633 *vr5500:
1634 {
1635   check_u64 (SD_, instruction_0);
1636   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1637 }
1638
1639 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1640 "dror32 r<RD>, r<RT>, <SHIFT>"
1641 *mips64r2:
1642 *vr5400:
1643 *vr5500:
1644 {
1645   check_u64 (SD_, instruction_0);
1646   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1647 }
1648
1649 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1650 "drorv r<RD>, r<RT>, r<RS>"
1651 *mips64r2:
1652 *vr5400:
1653 *vr5500:
1654 {
1655   check_u64 (SD_, instruction_0);
1656   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1657 }
1658
1659
1660 :function:::void:do_dsll:int rt, int rd, int shift
1661 {
1662   TRACE_ALU_INPUT2 (GPR[rt], shift);
1663   GPR[rd] = GPR[rt] << shift;
1664   TRACE_ALU_RESULT (GPR[rd]);
1665 }
1666
1667 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1668 "dsll r<RD>, r<RT>, <SHIFT>"
1669 *mipsIII:
1670 *mipsIV:
1671 *mipsV:
1672 *mips64:
1673 *mips64r2:
1674 *vr4100:
1675 *vr5000:
1676 {
1677   check_u64 (SD_, instruction_0);
1678   do_dsll (SD_, RT, RD, SHIFT);
1679 }
1680
1681
1682 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1683 "dsll32 r<RD>, r<RT>, <SHIFT>"
1684 *mipsIII:
1685 *mipsIV:
1686 *mipsV:
1687 *mips64:
1688 *mips64r2:
1689 *vr4100:
1690 *vr5000:
1691 {
1692   int s = 32 + SHIFT;
1693   check_u64 (SD_, instruction_0);
1694   TRACE_ALU_INPUT2 (GPR[RT], s);
1695   GPR[RD] = GPR[RT] << s;
1696   TRACE_ALU_RESULT (GPR[RD]);
1697 }
1698
1699 :function:::void:do_dsllv:int rs, int rt, int rd
1700 {
1701   int s = MASKED64 (GPR[rs], 5, 0);
1702   TRACE_ALU_INPUT2 (GPR[rt], s);
1703   GPR[rd] = GPR[rt] << s;
1704   TRACE_ALU_RESULT (GPR[rd]);
1705 }
1706
1707 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1708 "dsllv r<RD>, r<RT>, r<RS>"
1709 *mipsIII:
1710 *mipsIV:
1711 *mipsV:
1712 *mips64:
1713 *mips64r2:
1714 *vr4100:
1715 *vr5000:
1716 {
1717   check_u64 (SD_, instruction_0);
1718   do_dsllv (SD_, RS, RT, RD);
1719 }
1720
1721 :function:::void:do_dsra:int rt, int rd, int shift
1722 {
1723   TRACE_ALU_INPUT2 (GPR[rt], shift);
1724   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1725   TRACE_ALU_RESULT (GPR[rd]);
1726 }
1727
1728
1729 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1730 "dsra r<RD>, r<RT>, <SHIFT>"
1731 *mipsIII:
1732 *mipsIV:
1733 *mipsV:
1734 *mips64:
1735 *mips64r2:
1736 *vr4100:
1737 *vr5000:
1738 {
1739   check_u64 (SD_, instruction_0);
1740   do_dsra (SD_, RT, RD, SHIFT);
1741 }
1742
1743
1744 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1745 "dsra32 r<RD>, r<RT>, <SHIFT>"
1746 *mipsIII:
1747 *mipsIV:
1748 *mipsV:
1749 *mips64:
1750 *mips64r2:
1751 *vr4100:
1752 *vr5000:
1753 {
1754   int s = 32 + SHIFT;
1755   check_u64 (SD_, instruction_0);
1756   TRACE_ALU_INPUT2 (GPR[RT], s);
1757   GPR[RD] = ((signed64) GPR[RT]) >> s;
1758   TRACE_ALU_RESULT (GPR[RD]);
1759 }
1760
1761
1762 :function:::void:do_dsrav:int rs, int rt, int rd
1763 {
1764   int s = MASKED64 (GPR[rs], 5, 0);
1765   TRACE_ALU_INPUT2 (GPR[rt], s);
1766   GPR[rd] = ((signed64) GPR[rt]) >> s;
1767   TRACE_ALU_RESULT (GPR[rd]);
1768 }
1769
1770 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1771 "dsrav r<RD>, r<RT>, r<RS>"
1772 *mipsIII:
1773 *mipsIV:
1774 *mipsV:
1775 *mips64:
1776 *mips64r2:
1777 *vr4100:
1778 *vr5000:
1779 {
1780   check_u64 (SD_, instruction_0);
1781   do_dsrav (SD_, RS, RT, RD);
1782 }
1783
1784 :function:::void:do_dsrl:int rt, int rd, int shift
1785 {
1786   TRACE_ALU_INPUT2 (GPR[rt], shift);
1787   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1788   TRACE_ALU_RESULT (GPR[rd]);
1789 }
1790
1791
1792 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1793 "dsrl r<RD>, r<RT>, <SHIFT>"
1794 *mipsIII:
1795 *mipsIV:
1796 *mipsV:
1797 *mips64:
1798 *mips64r2:
1799 *vr4100:
1800 *vr5000:
1801 {
1802   check_u64 (SD_, instruction_0);
1803   do_dsrl (SD_, RT, RD, SHIFT);
1804 }
1805
1806
1807 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1808 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1809 *mipsIII:
1810 *mipsIV:
1811 *mipsV:
1812 *mips64:
1813 *mips64r2:
1814 *vr4100:
1815 *vr5000:
1816 {
1817   int s = 32 + SHIFT;
1818   check_u64 (SD_, instruction_0);
1819   TRACE_ALU_INPUT2 (GPR[RT], s);
1820   GPR[RD] = (unsigned64) GPR[RT] >> s;
1821   TRACE_ALU_RESULT (GPR[RD]);
1822 }
1823
1824
1825 :function:::void:do_dsrlv:int rs, int rt, int rd
1826 {
1827   int s = MASKED64 (GPR[rs], 5, 0);
1828   TRACE_ALU_INPUT2 (GPR[rt], s);
1829   GPR[rd] = (unsigned64) GPR[rt] >> s;
1830   TRACE_ALU_RESULT (GPR[rd]);
1831 }
1832
1833
1834
1835 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1836 "dsrlv r<RD>, r<RT>, r<RS>"
1837 *mipsIII:
1838 *mipsIV:
1839 *mipsV:
1840 *mips64:
1841 *mips64r2:
1842 *vr4100:
1843 *vr5000:
1844 {
1845   check_u64 (SD_, instruction_0);
1846   do_dsrlv (SD_, RS, RT, RD);
1847 }
1848
1849
1850 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1851 "dsub r<RD>, r<RS>, r<RT>"
1852 *mipsIII:
1853 *mipsIV:
1854 *mipsV:
1855 *mips64:
1856 *mips64r2:
1857 *vr4100:
1858 *vr5000:
1859 {
1860   check_u64 (SD_, instruction_0);
1861   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1862   {
1863     ALU64_BEGIN (GPR[RS]);
1864     ALU64_SUB (GPR[RT]);
1865     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1866   }
1867   TRACE_ALU_RESULT (GPR[RD]);
1868 }
1869
1870
1871 :function:::void:do_dsubu:int rs, int rt, int rd
1872 {
1873   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1874   GPR[rd] = GPR[rs] - GPR[rt];
1875   TRACE_ALU_RESULT (GPR[rd]);
1876 }
1877
1878 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1879 "dsubu r<RD>, r<RS>, r<RT>"
1880 *mipsIII:
1881 *mipsIV:
1882 *mipsV:
1883 *mips64:
1884 *mips64r2:
1885 *vr4100:
1886 *vr5000:
1887 {
1888   check_u64 (SD_, instruction_0);
1889   do_dsubu (SD_, RS, RT, RD);
1890 }
1891
1892
1893 000010,26.INSTR_INDEX:NORMAL:32::J
1894 "j <INSTR_INDEX>"
1895 *mipsI:
1896 *mipsII:
1897 *mipsIII:
1898 *mipsIV:
1899 *mipsV:
1900 *mips32:
1901 *mips32r2:
1902 *mips64:
1903 *mips64r2:
1904 *vr4100:
1905 *vr5000:
1906 *r3900:
1907 {
1908   /* NOTE: The region used is that of the delay slot NIA and NOT the
1909      current instruction */
1910   address_word region = (NIA & MASK (63, 28));
1911   DELAY_SLOT (region | (INSTR_INDEX << 2));
1912 }
1913
1914
1915 000011,26.INSTR_INDEX:NORMAL:32::JAL
1916 "jal <INSTR_INDEX>"
1917 *mipsI:
1918 *mipsII:
1919 *mipsIII:
1920 *mipsIV:
1921 *mipsV:
1922 *mips32:
1923 *mips32r2:
1924 *mips64:
1925 *mips64r2:
1926 *vr4100:
1927 *vr5000:
1928 *r3900:
1929 {
1930   /* NOTE: The region used is that of the delay slot and NOT the
1931      current instruction */
1932   address_word region = (NIA & MASK (63, 28));
1933   GPR[31] = CIA + 8;
1934   DELAY_SLOT (region | (INSTR_INDEX << 2));
1935 }
1936
1937 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1938 "jalr r<RS>":RD == 31
1939 "jalr r<RD>, r<RS>"
1940 *mipsI:
1941 *mipsII:
1942 *mipsIII:
1943 *mipsIV:
1944 *mipsV:
1945 *mips32:
1946 *mips32r2:
1947 *mips64:
1948 *mips64r2:
1949 *vr4100:
1950 *vr5000:
1951 *r3900:
1952 {
1953   address_word temp = GPR[RS];
1954   GPR[RD] = CIA + 8;
1955   DELAY_SLOT (temp);
1956 }
1957
1958
1959 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1960 "jr r<RS>"
1961 *mipsI:
1962 *mipsII:
1963 *mipsIII:
1964 *mipsIV:
1965 *mipsV:
1966 *mips32:
1967 *mips32r2:
1968 *mips64:
1969 *mips64r2:
1970 *vr4100:
1971 *vr5000:
1972 *r3900:
1973 {
1974   DELAY_SLOT (GPR[RS]);
1975 }
1976
1977
1978 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1979 {
1980   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1981   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1982   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1983   unsigned int byte;
1984   address_word paddr;
1985   int uncached;
1986   unsigned64 memval;
1987   address_word vaddr;
1988
1989   vaddr = loadstore_ea (SD_, base, offset);
1990   if ((vaddr & access) != 0)
1991     {
1992       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1993     }
1994   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1995   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1996   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1997   byte = ((vaddr & mask) ^ bigendiancpu);
1998   return (memval >> (8 * byte));
1999 }
2000
2001 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2002 {
2003   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2004   address_word reverseendian = (ReverseEndian ? -1 : 0);
2005   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2006   unsigned int byte;
2007   unsigned int word;
2008   address_word paddr;
2009   int uncached;
2010   unsigned64 memval;
2011   address_word vaddr;
2012   int nr_lhs_bits;
2013   int nr_rhs_bits;
2014   unsigned_word lhs_mask;
2015   unsigned_word temp;
2016
2017   vaddr = loadstore_ea (SD_, base, offset);
2018   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2019   paddr = (paddr ^ (reverseendian & mask));
2020   if (BigEndianMem == 0)
2021     paddr = paddr & ~access;
2022
2023   /* compute where within the word/mem we are */
2024   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2025   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2026   nr_lhs_bits = 8 * byte + 8;
2027   nr_rhs_bits = 8 * access - 8 * byte;
2028   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2029
2030   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2031            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2032            (long) ((unsigned64) paddr >> 32), (long) paddr,
2033            word, byte, nr_lhs_bits, nr_rhs_bits); */
2034
2035   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2036   if (word == 0)
2037     {
2038       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2039       temp = (memval << nr_rhs_bits);
2040     }
2041   else
2042     {
2043       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2044       temp = (memval >> nr_lhs_bits);
2045     }
2046   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2047   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2048
2049   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2050            (long) ((unsigned64) memval >> 32), (long) memval,
2051            (long) ((unsigned64) temp >> 32), (long) temp,
2052            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2053            (long) (rt >> 32), (long) rt); */
2054   return rt;
2055 }
2056
2057 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2058 {
2059   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2060   address_word reverseendian = (ReverseEndian ? -1 : 0);
2061   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2062   unsigned int byte;
2063   address_word paddr;
2064   int uncached;
2065   unsigned64 memval;
2066   address_word vaddr;
2067
2068   vaddr = loadstore_ea (SD_, base, offset);
2069   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2070   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2071   paddr = (paddr ^ (reverseendian & mask));
2072   if (BigEndianMem != 0)
2073     paddr = paddr & ~access;
2074   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2075   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2076   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2077   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2078      (long) paddr, byte, (long) paddr, (long) memval); */
2079   {
2080     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2081     rt &= ~screen;
2082     rt |= (memval >> (8 * byte)) & screen;
2083   }
2084   return rt;
2085 }
2086
2087
2088 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2089 "lb r<RT>, <OFFSET>(r<BASE>)"
2090 *mipsI:
2091 *mipsII:
2092 *mipsIII:
2093 *mipsIV:
2094 *mipsV:
2095 *mips32:
2096 *mips32r2:
2097 *mips64:
2098 *mips64r2:
2099 *vr4100:
2100 *vr5000:
2101 *r3900:
2102 {
2103   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2104 }
2105
2106
2107 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2108 "lbu r<RT>, <OFFSET>(r<BASE>)"
2109 *mipsI:
2110 *mipsII:
2111 *mipsIII:
2112 *mipsIV:
2113 *mipsV:
2114 *mips32:
2115 *mips32r2:
2116 *mips64:
2117 *mips64r2:
2118 *vr4100:
2119 *vr5000:
2120 *r3900:
2121 {
2122   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2123 }
2124
2125
2126 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2127 "ld r<RT>, <OFFSET>(r<BASE>)"
2128 *mipsIII:
2129 *mipsIV:
2130 *mipsV:
2131 *mips64:
2132 *mips64r2:
2133 *vr4100:
2134 *vr5000:
2135 {
2136   check_u64 (SD_, instruction_0);
2137   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2138 }
2139
2140
2141 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2142 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2143 *mipsII:
2144 *mipsIII:
2145 *mipsIV:
2146 *mipsV:
2147 *mips32:
2148 *mips32r2:
2149 *mips64:
2150 *mips64r2:
2151 *vr4100:
2152 *vr5000:
2153 *r3900:
2154 {
2155   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2156 }
2157
2158
2159
2160
2161 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2162 "ldl r<RT>, <OFFSET>(r<BASE>)"
2163 *mipsIII:
2164 *mipsIV:
2165 *mipsV:
2166 *mips64:
2167 *mips64r2:
2168 *vr4100:
2169 *vr5000:
2170 {
2171   check_u64 (SD_, instruction_0);
2172   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2173 }
2174
2175
2176 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2177 "ldr r<RT>, <OFFSET>(r<BASE>)"
2178 *mipsIII:
2179 *mipsIV:
2180 *mipsV:
2181 *mips64:
2182 *mips64r2:
2183 *vr4100:
2184 *vr5000:
2185 {
2186   check_u64 (SD_, instruction_0);
2187   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2188 }
2189
2190
2191 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2192 "lh r<RT>, <OFFSET>(r<BASE>)"
2193 *mipsI:
2194 *mipsII:
2195 *mipsIII:
2196 *mipsIV:
2197 *mipsV:
2198 *mips32:
2199 *mips32r2:
2200 *mips64:
2201 *mips64r2:
2202 *vr4100:
2203 *vr5000:
2204 *r3900:
2205 {
2206   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2207 }
2208
2209
2210 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2211 "lhu r<RT>, <OFFSET>(r<BASE>)"
2212 *mipsI:
2213 *mipsII:
2214 *mipsIII:
2215 *mipsIV:
2216 *mipsV:
2217 *mips32:
2218 *mips32r2:
2219 *mips64:
2220 *mips64r2:
2221 *vr4100:
2222 *vr5000:
2223 *r3900:
2224 {
2225   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2226 }
2227
2228
2229 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2230 "ll r<RT>, <OFFSET>(r<BASE>)"
2231 *mipsII:
2232 *mipsIII:
2233 *mipsIV:
2234 *mipsV:
2235 *mips32:
2236 *mips32r2:
2237 *mips64:
2238 *mips64r2:
2239 *vr4100:
2240 *vr5000:
2241 {
2242   address_word base = GPR[BASE];
2243   address_word offset = EXTEND16 (OFFSET);
2244   {
2245     address_word vaddr = loadstore_ea (SD_, base, offset);
2246     address_word paddr;
2247     int uncached;
2248     if ((vaddr & 3) != 0)
2249       {
2250         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2251       }
2252     else
2253       {
2254         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2255           {
2256             unsigned64 memval = 0;
2257             unsigned64 memval1 = 0;
2258             unsigned64 mask = 0x7;
2259             unsigned int shift = 2;
2260             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2261             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2262             unsigned int byte;
2263             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2264             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2265             byte = ((vaddr & mask) ^ (bigend << shift));
2266             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2267             LLBIT = 1;
2268           }
2269       }
2270   }
2271 }
2272
2273
2274 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2275 "lld r<RT>, <OFFSET>(r<BASE>)"
2276 *mipsIII:
2277 *mipsIV:
2278 *mipsV:
2279 *mips64:
2280 *mips64r2:
2281 *vr4100:
2282 *vr5000:
2283 {
2284   address_word base = GPR[BASE];
2285   address_word offset = EXTEND16 (OFFSET);
2286   check_u64 (SD_, instruction_0);
2287   {
2288     address_word vaddr = loadstore_ea (SD_, base, offset);
2289     address_word paddr;
2290     int uncached;
2291     if ((vaddr & 7) != 0)
2292       {
2293         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2294       }
2295     else
2296       {
2297         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2298           {
2299             unsigned64 memval = 0;
2300             unsigned64 memval1 = 0;
2301             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2302             GPR[RT] = memval;
2303             LLBIT = 1;
2304           }
2305       }
2306   }
2307 }
2308
2309
2310 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2311 "lui r<RT>, %#lx<IMMEDIATE>"
2312 *mipsI:
2313 *mipsII:
2314 *mipsIII:
2315 *mipsIV:
2316 *mipsV:
2317 *mips32:
2318 *mips32r2:
2319 *mips64:
2320 *mips64r2:
2321 *vr4100:
2322 *vr5000:
2323 *r3900:
2324 {
2325   TRACE_ALU_INPUT1 (IMMEDIATE);
2326   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2327   TRACE_ALU_RESULT (GPR[RT]);
2328 }
2329
2330
2331 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2332 "lw r<RT>, <OFFSET>(r<BASE>)"
2333 *mipsI:
2334 *mipsII:
2335 *mipsIII:
2336 *mipsIV:
2337 *mipsV:
2338 *mips32:
2339 *mips32r2:
2340 *mips64:
2341 *mips64r2:
2342 *vr4100:
2343 *vr5000:
2344 *r3900:
2345 {
2346   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2347 }
2348
2349
2350 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2351 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2352 *mipsI:
2353 *mipsII:
2354 *mipsIII:
2355 *mipsIV:
2356 *mipsV:
2357 *mips32:
2358 *mips32r2:
2359 *mips64:
2360 *mips64r2:
2361 *vr4100:
2362 *vr5000:
2363 *r3900:
2364 {
2365   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2366 }
2367
2368
2369 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2370 "lwl r<RT>, <OFFSET>(r<BASE>)"
2371 *mipsI:
2372 *mipsII:
2373 *mipsIII:
2374 *mipsIV:
2375 *mipsV:
2376 *mips32:
2377 *mips32r2:
2378 *mips64:
2379 *mips64r2:
2380 *vr4100:
2381 *vr5000:
2382 *r3900:
2383 {
2384   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2385 }
2386
2387
2388 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2389 "lwr r<RT>, <OFFSET>(r<BASE>)"
2390 *mipsI:
2391 *mipsII:
2392 *mipsIII:
2393 *mipsIV:
2394 *mipsV:
2395 *mips32:
2396 *mips32r2:
2397 *mips64:
2398 *mips64r2:
2399 *vr4100:
2400 *vr5000:
2401 *r3900:
2402 {
2403   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2404 }
2405
2406
2407 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2408 "lwu r<RT>, <OFFSET>(r<BASE>)"
2409 *mipsIII:
2410 *mipsIV:
2411 *mipsV:
2412 *mips64:
2413 *mips64r2:
2414 *vr4100:
2415 *vr5000:
2416 {
2417   check_u64 (SD_, instruction_0);
2418   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2419 }
2420
2421
2422
2423 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2424 "madd r<RS>, r<RT>"
2425 *mips32:
2426 *mips32r2:
2427 *mips64:
2428 *mips64r2:
2429 *vr5500:
2430 {
2431   signed64 temp;
2432   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2433   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2434     Unpredictable ();
2435   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2436   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2437           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2438   LO = EXTEND32 (temp);
2439   HI = EXTEND32 (VH4_8 (temp));
2440   TRACE_ALU_RESULT2 (HI, LO);
2441 }
2442
2443
2444
2445 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2446 "maddu r<RS>, r<RT>"
2447 *mips32:
2448 *mips32r2:
2449 *mips64:
2450 *mips64r2:
2451 *vr5500:
2452 {
2453   unsigned64 temp;
2454   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2455   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2456     Unpredictable ();
2457   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2458   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2459           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2460   LO = EXTEND32 (temp);
2461   HI = EXTEND32 (VH4_8 (temp));
2462   TRACE_ALU_RESULT2 (HI, LO);
2463 }
2464
2465
2466 :function:::void:do_mfhi:int rd
2467 {
2468   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2469   TRACE_ALU_INPUT1 (HI);
2470   GPR[rd] = HI;
2471   TRACE_ALU_RESULT (GPR[rd]);
2472 }
2473
2474 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2475 "mfhi r<RD>"
2476 *mipsI:
2477 *mipsII:
2478 *mipsIII:
2479 *mipsIV:
2480 *mipsV:
2481 *vr4100:
2482 *vr5000:
2483 *r3900:
2484 {
2485   do_mfhi (SD_, RD);
2486 }
2487
2488
2489
2490 :function:::void:do_mflo:int rd
2491 {
2492   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2493   TRACE_ALU_INPUT1 (LO);
2494   GPR[rd] = LO;
2495   TRACE_ALU_RESULT (GPR[rd]);
2496 }
2497
2498 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2499 "mflo r<RD>"
2500 *mipsI:
2501 *mipsII:
2502 *mipsIII:
2503 *mipsIV:
2504 *mipsV:
2505 *vr4100:
2506 *vr5000:
2507 *r3900:
2508 {
2509   do_mflo (SD_, RD);
2510 }
2511
2512
2513
2514 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2515 "movn r<RD>, r<RS>, r<RT>"
2516 *mipsIV:
2517 *mipsV:
2518 *mips32:
2519 *mips32r2:
2520 *mips64:
2521 *mips64r2:
2522 *vr5000:
2523 {
2524   if (GPR[RT] != 0)
2525     {
2526       GPR[RD] = GPR[RS];
2527       TRACE_ALU_RESULT (GPR[RD]);
2528     }
2529 }
2530
2531
2532
2533 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2534 "movz r<RD>, r<RS>, r<RT>"
2535 *mipsIV:
2536 *mipsV:
2537 *mips32:
2538 *mips32r2:
2539 *mips64:
2540 *mips64r2:
2541 *vr5000:
2542 {
2543   if (GPR[RT] == 0)
2544     {
2545       GPR[RD] = GPR[RS];
2546       TRACE_ALU_RESULT (GPR[RD]);
2547     }
2548 }
2549
2550
2551
2552 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2553 "msub r<RS>, r<RT>"
2554 *mips32:
2555 *mips32r2:
2556 *mips64:
2557 *mips64r2:
2558 *vr5500:
2559 {
2560   signed64 temp;
2561   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2562   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2563     Unpredictable ();
2564   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2565   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2566           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2567   LO = EXTEND32 (temp);
2568   HI = EXTEND32 (VH4_8 (temp));
2569   TRACE_ALU_RESULT2 (HI, LO);
2570 }
2571
2572
2573
2574 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2575 "msubu r<RS>, r<RT>"
2576 *mips32:
2577 *mips32r2:
2578 *mips64:
2579 *mips64r2:
2580 *vr5500:
2581 {
2582   unsigned64 temp;
2583   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2584   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2585     Unpredictable ();
2586   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2587   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2588           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2589   LO = EXTEND32 (temp);
2590   HI = EXTEND32 (VH4_8 (temp));
2591   TRACE_ALU_RESULT2 (HI, LO);
2592 }
2593
2594
2595
2596 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2597 "mthi r<RS>"
2598 *mipsI:
2599 *mipsII:
2600 *mipsIII:
2601 *mipsIV:
2602 *mipsV:
2603 *vr4100:
2604 *vr5000:
2605 *r3900:
2606 {
2607   check_mt_hilo (SD_, HIHISTORY);
2608   HI = GPR[RS];
2609 }
2610
2611
2612
2613 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2614 "mtlo r<RS>"
2615 *mipsI:
2616 *mipsII:
2617 *mipsIII:
2618 *mipsIV:
2619 *mipsV:
2620 *vr4100:
2621 *vr5000:
2622 *r3900:
2623 {
2624   check_mt_hilo (SD_, LOHISTORY);
2625   LO = GPR[RS];
2626 }
2627
2628
2629
2630 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2631 "mul r<RD>, r<RS>, r<RT>"
2632 *mips32:
2633 *mips32r2:
2634 *mips64:
2635 *mips64r2:
2636 *vr5500:
2637 {
2638   signed64 prod;
2639   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2640     Unpredictable ();
2641   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2642   prod = (((signed64)(signed32) GPR[RS])
2643           * ((signed64)(signed32) GPR[RT]));
2644   GPR[RD] = EXTEND32 (VL4_8 (prod));
2645   TRACE_ALU_RESULT (GPR[RD]);
2646 }
2647
2648
2649
2650 :function:::void:do_mult:int rs, int rt, int rd
2651 {
2652   signed64 prod;
2653   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2654   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2655     Unpredictable ();
2656   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2657   prod = (((signed64)(signed32) GPR[rs])
2658           * ((signed64)(signed32) GPR[rt]));
2659   LO = EXTEND32 (VL4_8 (prod));
2660   HI = EXTEND32 (VH4_8 (prod));
2661   if (rd != 0)
2662     GPR[rd] = LO;
2663   TRACE_ALU_RESULT2 (HI, LO);
2664 }
2665
2666 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2667 "mult r<RS>, r<RT>"
2668 *mipsI:
2669 *mipsII:
2670 *mipsIII:
2671 *mipsIV:
2672 *mipsV:
2673 *mips32:
2674 *mips32r2:
2675 *mips64:
2676 *mips64r2:
2677 *vr4100:
2678 {
2679   do_mult (SD_, RS, RT, 0);
2680 }
2681
2682
2683 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2684 "mult r<RS>, r<RT>":RD == 0
2685 "mult r<RD>, r<RS>, r<RT>"
2686 *vr5000:
2687 *r3900:
2688 {
2689   do_mult (SD_, RS, RT, RD);
2690 }
2691
2692
2693 :function:::void:do_multu:int rs, int rt, int rd
2694 {
2695   unsigned64 prod;
2696   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2697   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2698     Unpredictable ();
2699   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2700   prod = (((unsigned64)(unsigned32) GPR[rs])
2701           * ((unsigned64)(unsigned32) GPR[rt]));
2702   LO = EXTEND32 (VL4_8 (prod));
2703   HI = EXTEND32 (VH4_8 (prod));
2704   if (rd != 0)
2705     GPR[rd] = LO;
2706   TRACE_ALU_RESULT2 (HI, LO);
2707 }
2708
2709 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2710 "multu r<RS>, r<RT>"
2711 *mipsI:
2712 *mipsII:
2713 *mipsIII:
2714 *mipsIV:
2715 *mipsV:
2716 *mips32:
2717 *mips32r2:
2718 *mips64:
2719 *mips64r2:
2720 *vr4100:
2721 {
2722   do_multu (SD_, RS, RT, 0);
2723 }
2724
2725 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2726 "multu r<RS>, r<RT>":RD == 0
2727 "multu r<RD>, r<RS>, r<RT>"
2728 *vr5000:
2729 *r3900:
2730 {
2731   do_multu (SD_, RS, RT, RD);
2732 }
2733
2734
2735 :function:::void:do_nor:int rs, int rt, int rd
2736 {
2737   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2738   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2739   TRACE_ALU_RESULT (GPR[rd]);
2740 }
2741
2742 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2743 "nor r<RD>, r<RS>, r<RT>"
2744 *mipsI:
2745 *mipsII:
2746 *mipsIII:
2747 *mipsIV:
2748 *mipsV:
2749 *mips32:
2750 *mips32r2:
2751 *mips64:
2752 *mips64r2:
2753 *vr4100:
2754 *vr5000:
2755 *r3900:
2756 {
2757   do_nor (SD_, RS, RT, RD);
2758 }
2759
2760
2761 :function:::void:do_or:int rs, int rt, int rd
2762 {
2763   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2764   GPR[rd] = (GPR[rs] | GPR[rt]);
2765   TRACE_ALU_RESULT (GPR[rd]);
2766 }
2767
2768 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2769 "or r<RD>, r<RS>, r<RT>"
2770 *mipsI:
2771 *mipsII:
2772 *mipsIII:
2773 *mipsIV:
2774 *mipsV:
2775 *mips32:
2776 *mips32r2:
2777 *mips64:
2778 *mips64r2:
2779 *vr4100:
2780 *vr5000:
2781 *r3900:
2782 {
2783   do_or (SD_, RS, RT, RD);
2784 }
2785
2786
2787
2788 :function:::void:do_ori:int rs, int rt, unsigned immediate
2789 {
2790   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2791   GPR[rt] = (GPR[rs] | immediate);
2792   TRACE_ALU_RESULT (GPR[rt]);
2793 }
2794
2795 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2796 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2797 *mipsI:
2798 *mipsII:
2799 *mipsIII:
2800 *mipsIV:
2801 *mipsV:
2802 *mips32:
2803 *mips32r2:
2804 *mips64:
2805 *mips64r2:
2806 *vr4100:
2807 *vr5000:
2808 *r3900:
2809 {
2810   do_ori (SD_, RS, RT, IMMEDIATE);
2811 }
2812
2813
2814 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2815 "pref <HINT>, <OFFSET>(r<BASE>)"
2816 *mipsIV:
2817 *mipsV:
2818 *mips32:
2819 *mips32r2:
2820 *mips64:
2821 *mips64r2:
2822 *vr5000:
2823 {
2824   address_word base = GPR[BASE];
2825   address_word offset = EXTEND16 (OFFSET);
2826   {
2827     address_word vaddr = loadstore_ea (SD_, base, offset);
2828     address_word paddr;
2829     int uncached;
2830     {
2831       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2832         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2833     }
2834   }
2835 }
2836
2837
2838 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
2839 {
2840   unsigned64 result;
2841
2842   y &= 31;
2843   TRACE_ALU_INPUT2 (x, y);
2844   result = EXTEND32 (ROTR32 (x, y));
2845   TRACE_ALU_RESULT (result);
2846   return result;
2847 }
2848
2849 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
2850 "ror r<RD>, r<RT>, <SHIFT>"
2851 *mips32r2:
2852 *mips64r2:
2853 *vr5400:
2854 *vr5500:
2855 {
2856   GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
2857 }
2858
2859 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
2860 "rorv r<RD>, r<RT>, r<RS>"
2861 *mips32r2:
2862 *mips64r2:
2863 *vr5400:
2864 *vr5500:
2865 {
2866   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
2867 }
2868
2869
2870 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2871 {
2872   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2873   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2874   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2875   unsigned int byte;
2876   address_word paddr;
2877   int uncached;
2878   unsigned64 memval;
2879   address_word vaddr;
2880
2881   vaddr = loadstore_ea (SD_, base, offset);
2882   if ((vaddr & access) != 0)
2883     {
2884       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2885     }
2886   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2887   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2888   byte = ((vaddr & mask) ^ bigendiancpu);
2889   memval = (word << (8 * byte));
2890   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2891 }
2892
2893 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2894 {
2895   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2896   address_word reverseendian = (ReverseEndian ? -1 : 0);
2897   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2898   unsigned int byte;
2899   unsigned int word;
2900   address_word paddr;
2901   int uncached;
2902   unsigned64 memval;
2903   address_word vaddr;
2904   int nr_lhs_bits;
2905   int nr_rhs_bits;
2906
2907   vaddr = loadstore_ea (SD_, base, offset);
2908   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2909   paddr = (paddr ^ (reverseendian & mask));
2910   if (BigEndianMem == 0)
2911     paddr = paddr & ~access;
2912
2913   /* compute where within the word/mem we are */
2914   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2915   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2916   nr_lhs_bits = 8 * byte + 8;
2917   nr_rhs_bits = 8 * access - 8 * byte;
2918   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2919   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2920            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2921            (long) ((unsigned64) paddr >> 32), (long) paddr,
2922            word, byte, nr_lhs_bits, nr_rhs_bits); */
2923
2924   if (word == 0)
2925     {
2926       memval = (rt >> nr_rhs_bits);
2927     }
2928   else
2929     {
2930       memval = (rt << nr_lhs_bits);
2931     }
2932   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2933            (long) ((unsigned64) rt >> 32), (long) rt,
2934            (long) ((unsigned64) memval >> 32), (long) memval); */
2935   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2936 }
2937
2938 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2939 {
2940   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2941   address_word reverseendian = (ReverseEndian ? -1 : 0);
2942   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2943   unsigned int byte;
2944   address_word paddr;
2945   int uncached;
2946   unsigned64 memval;
2947   address_word vaddr;
2948
2949   vaddr = loadstore_ea (SD_, base, offset);
2950   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2951   paddr = (paddr ^ (reverseendian & mask));
2952   if (BigEndianMem != 0)
2953     paddr &= ~access;
2954   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2955   memval = (rt << (byte * 8));
2956   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2957 }
2958
2959
2960 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2961 "sb r<RT>, <OFFSET>(r<BASE>)"
2962 *mipsI:
2963 *mipsII:
2964 *mipsIII:
2965 *mipsIV:
2966 *mipsV:
2967 *mips32:
2968 *mips32r2:
2969 *mips64:
2970 *mips64r2:
2971 *vr4100:
2972 *vr5000:
2973 *r3900:
2974 {
2975   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2976 }
2977
2978
2979 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2980 "sc r<RT>, <OFFSET>(r<BASE>)"
2981 *mipsII:
2982 *mipsIII:
2983 *mipsIV:
2984 *mipsV:
2985 *mips32:
2986 *mips32r2:
2987 *mips64:
2988 *mips64r2:
2989 *vr4100:
2990 *vr5000:
2991 {
2992   unsigned32 instruction = instruction_0;
2993   address_word base = GPR[BASE];
2994   address_word offset = EXTEND16 (OFFSET);
2995   {
2996     address_word vaddr = loadstore_ea (SD_, base, offset);
2997     address_word paddr;
2998     int uncached;
2999     if ((vaddr & 3) != 0)
3000       {
3001         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3002       }
3003     else
3004       {
3005         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3006           {
3007             unsigned64 memval = 0;
3008             unsigned64 memval1 = 0;
3009             unsigned64 mask = 0x7;
3010             unsigned int byte;
3011             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3012             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3013             memval = ((unsigned64) GPR[RT] << (8 * byte));
3014             if (LLBIT)
3015               {
3016                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3017               }
3018             GPR[RT] = LLBIT;
3019           }
3020       }
3021   }
3022 }
3023
3024
3025 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3026 "scd r<RT>, <OFFSET>(r<BASE>)"
3027 *mipsIII:
3028 *mipsIV:
3029 *mipsV:
3030 *mips64:
3031 *mips64r2:
3032 *vr4100:
3033 *vr5000:
3034 {
3035   address_word base = GPR[BASE];
3036   address_word offset = EXTEND16 (OFFSET);
3037   check_u64 (SD_, instruction_0);
3038   {
3039     address_word vaddr = loadstore_ea (SD_, base, offset);
3040     address_word paddr;
3041     int uncached;
3042     if ((vaddr & 7) != 0)
3043       {
3044         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3045       }
3046     else
3047       {
3048         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3049           {
3050             unsigned64 memval = 0;
3051             unsigned64 memval1 = 0;
3052             memval = GPR[RT];
3053             if (LLBIT)
3054               {
3055                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3056               }
3057             GPR[RT] = LLBIT;
3058           }
3059       }
3060   }
3061 }
3062
3063
3064 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3065 "sd r<RT>, <OFFSET>(r<BASE>)"
3066 *mipsIII:
3067 *mipsIV:
3068 *mipsV:
3069 *mips64:
3070 *mips64r2:
3071 *vr4100:
3072 *vr5000:
3073 {
3074   check_u64 (SD_, instruction_0);
3075   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3076 }
3077
3078
3079 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3080 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3081 *mipsII:
3082 *mipsIII:
3083 *mipsIV:
3084 *mipsV:
3085 *mips32:
3086 *mips32r2:
3087 *mips64:
3088 *mips64r2:
3089 *vr4100:
3090 *vr5000:
3091 {
3092   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3093 }
3094
3095
3096 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3097 "sdl r<RT>, <OFFSET>(r<BASE>)"
3098 *mipsIII:
3099 *mipsIV:
3100 *mipsV:
3101 *mips64:
3102 *mips64r2:
3103 *vr4100:
3104 *vr5000:
3105 {
3106   check_u64 (SD_, instruction_0);
3107   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3108 }
3109
3110
3111 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3112 "sdr r<RT>, <OFFSET>(r<BASE>)"
3113 *mipsIII:
3114 *mipsIV:
3115 *mipsV:
3116 *mips64:
3117 *mips64r2:
3118 *vr4100:
3119 *vr5000:
3120 {
3121   check_u64 (SD_, instruction_0);
3122   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3123 }
3124
3125
3126
3127 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3128 "sh r<RT>, <OFFSET>(r<BASE>)"
3129 *mipsI:
3130 *mipsII:
3131 *mipsIII:
3132 *mipsIV:
3133 *mipsV:
3134 *mips32:
3135 *mips32r2:
3136 *mips64:
3137 *mips64r2:
3138 *vr4100:
3139 *vr5000:
3140 *r3900:
3141 {
3142   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3143 }
3144
3145
3146 :function:::void:do_sll:int rt, int rd, int shift
3147 {
3148   unsigned32 temp = (GPR[rt] << shift);
3149   TRACE_ALU_INPUT2 (GPR[rt], shift);
3150   GPR[rd] = EXTEND32 (temp);
3151   TRACE_ALU_RESULT (GPR[rd]);
3152 }
3153
3154 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
3155 "nop":RD == 0 && RT == 0 && SHIFT == 0
3156 "sll r<RD>, r<RT>, <SHIFT>"
3157 *mipsI:
3158 *mipsII:
3159 *mipsIII:
3160 *mipsIV:
3161 *mipsV:
3162 *vr4100:
3163 *vr5000:
3164 *r3900:
3165 {
3166   /* Skip shift for NOP, so that there won't be lots of extraneous
3167      trace output.  */
3168   if (RD != 0 || RT != 0 || SHIFT != 0)
3169     do_sll (SD_, RT, RD, SHIFT);
3170 }
3171
3172 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3173 "nop":RD == 0 && RT == 0 && SHIFT == 0
3174 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
3175 "sll r<RD>, r<RT>, <SHIFT>"
3176 *mips32:
3177 *mips32r2:
3178 *mips64:
3179 *mips64r2:
3180 {
3181   /* Skip shift for NOP and SSNOP, so that there won't be lots of
3182      extraneous trace output.  */
3183   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3184     do_sll (SD_, RT, RD, SHIFT);
3185 }
3186
3187
3188 :function:::void:do_sllv:int rs, int rt, int rd
3189 {
3190   int s = MASKED (GPR[rs], 4, 0);
3191   unsigned32 temp = (GPR[rt] << s);
3192   TRACE_ALU_INPUT2 (GPR[rt], s);
3193   GPR[rd] = EXTEND32 (temp);
3194   TRACE_ALU_RESULT (GPR[rd]);
3195 }
3196
3197 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
3198 "sllv r<RD>, r<RT>, r<RS>"
3199 *mipsI:
3200 *mipsII:
3201 *mipsIII:
3202 *mipsIV:
3203 *mipsV:
3204 *mips32:
3205 *mips32r2:
3206 *mips64:
3207 *mips64r2:
3208 *vr4100:
3209 *vr5000:
3210 *r3900:
3211 {
3212   do_sllv (SD_, RS, RT, RD);
3213 }
3214
3215
3216 :function:::void:do_slt:int rs, int rt, int rd
3217 {
3218   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3219   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3220   TRACE_ALU_RESULT (GPR[rd]);
3221 }
3222
3223 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
3224 "slt r<RD>, r<RS>, r<RT>"
3225 *mipsI:
3226 *mipsII:
3227 *mipsIII:
3228 *mipsIV:
3229 *mipsV:
3230 *mips32:
3231 *mips32r2:
3232 *mips64:
3233 *mips64r2:
3234 *vr4100:
3235 *vr5000:
3236 *r3900:
3237 {
3238   do_slt (SD_, RS, RT, RD);
3239 }
3240
3241
3242 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3243 {
3244   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3245   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3246   TRACE_ALU_RESULT (GPR[rt]);
3247 }
3248
3249 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3250 "slti r<RT>, r<RS>, <IMMEDIATE>"
3251 *mipsI:
3252 *mipsII:
3253 *mipsIII:
3254 *mipsIV:
3255 *mipsV:
3256 *mips32:
3257 *mips32r2:
3258 *mips64:
3259 *mips64r2:
3260 *vr4100:
3261 *vr5000:
3262 *r3900:
3263 {
3264   do_slti (SD_, RS, RT, IMMEDIATE);
3265 }
3266
3267
3268 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3269 {
3270   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3271   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3272   TRACE_ALU_RESULT (GPR[rt]);
3273 }
3274
3275 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3276 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3277 *mipsI:
3278 *mipsII:
3279 *mipsIII:
3280 *mipsIV:
3281 *mipsV:
3282 *mips32:
3283 *mips32r2:
3284 *mips64:
3285 *mips64r2:
3286 *vr4100:
3287 *vr5000:
3288 *r3900:
3289 {
3290   do_sltiu (SD_, RS, RT, IMMEDIATE);
3291 }
3292
3293
3294
3295 :function:::void:do_sltu:int rs, int rt, int rd
3296 {
3297   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3298   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3299   TRACE_ALU_RESULT (GPR[rd]);
3300 }
3301
3302 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3303 "sltu r<RD>, r<RS>, r<RT>"
3304 *mipsI:
3305 *mipsII:
3306 *mipsIII:
3307 *mipsIV:
3308 *mipsV:
3309 *mips32:
3310 *mips32r2:
3311 *mips64:
3312 *mips64r2:
3313 *vr4100:
3314 *vr5000:
3315 *r3900:
3316 {
3317   do_sltu (SD_, RS, RT, RD);
3318 }
3319
3320
3321 :function:::void:do_sra:int rt, int rd, int shift
3322 {
3323   signed32 temp = (signed32) GPR[rt] >> shift;
3324   if (NotWordValue (GPR[rt]))
3325     Unpredictable ();
3326   TRACE_ALU_INPUT2 (GPR[rt], shift);
3327   GPR[rd] = EXTEND32 (temp);
3328   TRACE_ALU_RESULT (GPR[rd]);
3329 }
3330
3331 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3332 "sra r<RD>, r<RT>, <SHIFT>"
3333 *mipsI:
3334 *mipsII:
3335 *mipsIII:
3336 *mipsIV:
3337 *mipsV:
3338 *mips32:
3339 *mips32r2:
3340 *mips64:
3341 *mips64r2:
3342 *vr4100:
3343 *vr5000:
3344 *r3900:
3345 {
3346   do_sra (SD_, RT, RD, SHIFT);
3347 }
3348
3349
3350
3351 :function:::void:do_srav:int rs, int rt, int rd
3352 {
3353   int s = MASKED (GPR[rs], 4, 0);
3354   signed32 temp = (signed32) GPR[rt] >> s;
3355   if (NotWordValue (GPR[rt]))
3356     Unpredictable ();
3357   TRACE_ALU_INPUT2 (GPR[rt], s);
3358   GPR[rd] = EXTEND32 (temp);
3359   TRACE_ALU_RESULT (GPR[rd]);
3360 }
3361
3362 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3363 "srav r<RD>, r<RT>, r<RS>"
3364 *mipsI:
3365 *mipsII:
3366 *mipsIII:
3367 *mipsIV:
3368 *mipsV:
3369 *mips32:
3370 *mips32r2:
3371 *mips64:
3372 *mips64r2:
3373 *vr4100:
3374 *vr5000:
3375 *r3900:
3376 {
3377   do_srav (SD_, RS, RT, RD);
3378 }
3379
3380
3381
3382 :function:::void:do_srl:int rt, int rd, int shift
3383 {
3384   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3385   if (NotWordValue (GPR[rt]))
3386     Unpredictable ();
3387   TRACE_ALU_INPUT2 (GPR[rt], shift);
3388   GPR[rd] = EXTEND32 (temp);
3389   TRACE_ALU_RESULT (GPR[rd]);
3390 }
3391
3392 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3393 "srl r<RD>, r<RT>, <SHIFT>"
3394 *mipsI:
3395 *mipsII:
3396 *mipsIII:
3397 *mipsIV:
3398 *mipsV:
3399 *mips32:
3400 *mips32r2:
3401 *mips64:
3402 *mips64r2:
3403 *vr4100:
3404 *vr5000:
3405 *r3900:
3406 {
3407   do_srl (SD_, RT, RD, SHIFT);
3408 }
3409
3410
3411 :function:::void:do_srlv:int rs, int rt, int rd
3412 {
3413   int s = MASKED (GPR[rs], 4, 0);
3414   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3415   if (NotWordValue (GPR[rt]))
3416     Unpredictable ();
3417   TRACE_ALU_INPUT2 (GPR[rt], s);
3418   GPR[rd] = EXTEND32 (temp);
3419   TRACE_ALU_RESULT (GPR[rd]);
3420 }
3421
3422 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3423 "srlv r<RD>, r<RT>, r<RS>"
3424 *mipsI:
3425 *mipsII:
3426 *mipsIII:
3427 *mipsIV:
3428 *mipsV:
3429 *mips32:
3430 *mips32r2:
3431 *mips64:
3432 *mips64r2:
3433 *vr4100:
3434 *vr5000:
3435 *r3900:
3436 {
3437   do_srlv (SD_, RS, RT, RD);
3438 }
3439
3440
3441 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3442 "sub r<RD>, r<RS>, r<RT>"
3443 *mipsI:
3444 *mipsII:
3445 *mipsIII:
3446 *mipsIV:
3447 *mipsV:
3448 *mips32:
3449 *mips32r2:
3450 *mips64:
3451 *mips64r2:
3452 *vr4100:
3453 *vr5000:
3454 *r3900:
3455 {
3456   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3457     Unpredictable ();
3458   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3459   {
3460     ALU32_BEGIN (GPR[RS]);
3461     ALU32_SUB (GPR[RT]);
3462     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3463   }
3464   TRACE_ALU_RESULT (GPR[RD]);
3465 }
3466
3467
3468 :function:::void:do_subu:int rs, int rt, int rd
3469 {
3470   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3471     Unpredictable ();
3472   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3473   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3474   TRACE_ALU_RESULT (GPR[rd]);
3475 }
3476
3477 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3478 "subu r<RD>, r<RS>, r<RT>"
3479 *mipsI:
3480 *mipsII:
3481 *mipsIII:
3482 *mipsIV:
3483 *mipsV:
3484 *mips32:
3485 *mips32r2:
3486 *mips64:
3487 *mips64r2:
3488 *vr4100:
3489 *vr5000:
3490 *r3900:
3491 {
3492   do_subu (SD_, RS, RT, RD);
3493 }
3494
3495
3496 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3497 "sw r<RT>, <OFFSET>(r<BASE>)"
3498 *mipsI:
3499 *mipsII:
3500 *mipsIII:
3501 *mipsIV:
3502 *mipsV:
3503 *mips32:
3504 *mips32r2:
3505 *mips64:
3506 *mips64r2:
3507 *vr4100:
3508 *r3900:
3509 *vr5000:
3510 {
3511   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3512 }
3513
3514
3515 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3516 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3517 *mipsI:
3518 *mipsII:
3519 *mipsIII:
3520 *mipsIV:
3521 *mipsV:
3522 *mips32:
3523 *mips32r2:
3524 *mips64:
3525 *mips64r2:
3526 *vr4100:
3527 *vr5000:
3528 *r3900:
3529 {
3530   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3531 }
3532
3533
3534 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3535 "swl r<RT>, <OFFSET>(r<BASE>)"
3536 *mipsI:
3537 *mipsII:
3538 *mipsIII:
3539 *mipsIV:
3540 *mipsV:
3541 *mips32:
3542 *mips32r2:
3543 *mips64:
3544 *mips64r2:
3545 *vr4100:
3546 *vr5000:
3547 *r3900:
3548 {
3549   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3550 }
3551
3552
3553 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3554 "swr r<RT>, <OFFSET>(r<BASE>)"
3555 *mipsI:
3556 *mipsII:
3557 *mipsIII:
3558 *mipsIV:
3559 *mipsV:
3560 *mips32:
3561 *mips32r2:
3562 *mips64:
3563 *mips64r2:
3564 *vr4100:
3565 *vr5000:
3566 *r3900:
3567 {
3568   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3569 }
3570
3571
3572 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3573 "sync":STYPE == 0
3574 "sync <STYPE>"
3575 *mipsII:
3576 *mipsIII:
3577 *mipsIV:
3578 *mipsV:
3579 *mips32:
3580 *mips32r2:
3581 *mips64:
3582 *mips64r2:
3583 *vr4100:
3584 *vr5000:
3585 *r3900:
3586 {
3587   SyncOperation (STYPE);
3588 }
3589
3590
3591 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3592 "syscall %#lx<CODE>"
3593 *mipsI:
3594 *mipsII:
3595 *mipsIII:
3596 *mipsIV:
3597 *mipsV:
3598 *mips32:
3599 *mips32r2:
3600 *mips64:
3601 *mips64r2:
3602 *vr4100:
3603 *vr5000:
3604 *r3900:
3605 {
3606   SignalException (SystemCall, instruction_0);
3607 }
3608
3609
3610 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3611 "teq r<RS>, r<RT>"
3612 *mipsII:
3613 *mipsIII:
3614 *mipsIV:
3615 *mipsV:
3616 *mips32:
3617 *mips32r2:
3618 *mips64:
3619 *mips64r2:
3620 *vr4100:
3621 *vr5000:
3622 {
3623   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3624     SignalException (Trap, instruction_0);
3625 }
3626
3627
3628 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3629 "teqi r<RS>, <IMMEDIATE>"
3630 *mipsII:
3631 *mipsIII:
3632 *mipsIV:
3633 *mipsV:
3634 *mips32:
3635 *mips32r2:
3636 *mips64:
3637 *mips64r2:
3638 *vr4100:
3639 *vr5000:
3640 {
3641   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3642     SignalException (Trap, instruction_0);
3643 }
3644
3645
3646 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3647 "tge r<RS>, r<RT>"
3648 *mipsII:
3649 *mipsIII:
3650 *mipsIV:
3651 *mipsV:
3652 *mips32:
3653 *mips32r2:
3654 *mips64:
3655 *mips64r2:
3656 *vr4100:
3657 *vr5000:
3658 {
3659   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3660     SignalException (Trap, instruction_0);
3661 }
3662
3663
3664 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3665 "tgei r<RS>, <IMMEDIATE>"
3666 *mipsII:
3667 *mipsIII:
3668 *mipsIV:
3669 *mipsV:
3670 *mips32:
3671 *mips32r2:
3672 *mips64:
3673 *mips64r2:
3674 *vr4100:
3675 *vr5000:
3676 {
3677   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3678     SignalException (Trap, instruction_0);
3679 }
3680
3681
3682 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3683 "tgeiu r<RS>, <IMMEDIATE>"
3684 *mipsII:
3685 *mipsIII:
3686 *mipsIV:
3687 *mipsV:
3688 *mips32:
3689 *mips32r2:
3690 *mips64:
3691 *mips64r2:
3692 *vr4100:
3693 *vr5000:
3694 {
3695   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3696     SignalException (Trap, instruction_0);
3697 }
3698
3699
3700 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3701 "tgeu r<RS>, r<RT>"
3702 *mipsII:
3703 *mipsIII:
3704 *mipsIV:
3705 *mipsV:
3706 *mips32:
3707 *mips32r2:
3708 *mips64:
3709 *mips64r2:
3710 *vr4100:
3711 *vr5000:
3712 {
3713   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3714     SignalException (Trap, instruction_0);
3715 }
3716
3717
3718 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3719 "tlt r<RS>, r<RT>"
3720 *mipsII:
3721 *mipsIII:
3722 *mipsIV:
3723 *mipsV:
3724 *mips32:
3725 *mips32r2:
3726 *mips64:
3727 *mips64r2:
3728 *vr4100:
3729 *vr5000:
3730 {
3731   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3732     SignalException (Trap, instruction_0);
3733 }
3734
3735
3736 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3737 "tlti r<RS>, <IMMEDIATE>"
3738 *mipsII:
3739 *mipsIII:
3740 *mipsIV:
3741 *mipsV:
3742 *mips32:
3743 *mips32r2:
3744 *mips64:
3745 *mips64r2:
3746 *vr4100:
3747 *vr5000:
3748 {
3749   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3750     SignalException (Trap, instruction_0);
3751 }
3752
3753
3754 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3755 "tltiu r<RS>, <IMMEDIATE>"
3756 *mipsII:
3757 *mipsIII:
3758 *mipsIV:
3759 *mipsV:
3760 *mips32:
3761 *mips32r2:
3762 *mips64:
3763 *mips64r2:
3764 *vr4100:
3765 *vr5000:
3766 {
3767   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3768     SignalException (Trap, instruction_0);
3769 }
3770
3771
3772 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3773 "tltu r<RS>, r<RT>"
3774 *mipsII:
3775 *mipsIII:
3776 *mipsIV:
3777 *mipsV:
3778 *mips32:
3779 *mips32r2:
3780 *mips64:
3781 *mips64r2:
3782 *vr4100:
3783 *vr5000:
3784 {
3785   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3786     SignalException (Trap, instruction_0);
3787 }
3788
3789
3790 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3791 "tne r<RS>, r<RT>"
3792 *mipsII:
3793 *mipsIII:
3794 *mipsIV:
3795 *mipsV:
3796 *mips32:
3797 *mips32r2:
3798 *mips64:
3799 *mips64r2:
3800 *vr4100:
3801 *vr5000:
3802 {
3803   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3804     SignalException (Trap, instruction_0);
3805 }
3806
3807
3808 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3809 "tnei r<RS>, <IMMEDIATE>"
3810 *mipsII:
3811 *mipsIII:
3812 *mipsIV:
3813 *mipsV:
3814 *mips32:
3815 *mips32r2:
3816 *mips64:
3817 *mips64r2:
3818 *vr4100:
3819 *vr5000:
3820 {
3821   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3822     SignalException (Trap, instruction_0);
3823 }
3824
3825
3826 :function:::void:do_xor:int rs, int rt, int rd
3827 {
3828   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3829   GPR[rd] = GPR[rs] ^ GPR[rt];
3830   TRACE_ALU_RESULT (GPR[rd]);
3831 }
3832
3833 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3834 "xor r<RD>, r<RS>, r<RT>"
3835 *mipsI:
3836 *mipsII:
3837 *mipsIII:
3838 *mipsIV:
3839 *mipsV:
3840 *mips32:
3841 *mips32r2:
3842 *mips64:
3843 *mips64r2:
3844 *vr4100:
3845 *vr5000:
3846 *r3900:
3847 {
3848   do_xor (SD_, RS, RT, RD);
3849 }
3850
3851
3852 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3853 {
3854   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3855   GPR[rt] = GPR[rs] ^ immediate;
3856   TRACE_ALU_RESULT (GPR[rt]);
3857 }
3858
3859 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3860 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3861 *mipsI:
3862 *mipsII:
3863 *mipsIII:
3864 *mipsIV:
3865 *mipsV:
3866 *mips32:
3867 *mips32r2:
3868 *mips64:
3869 *mips64r2:
3870 *vr4100:
3871 *vr5000:
3872 *r3900:
3873 {
3874   do_xori (SD_, RS, RT, IMMEDIATE);
3875 }
3876
3877 \f
3878 //
3879 // MIPS Architecture:
3880 //
3881 //        FPU Instruction Set (COP1 & COP1X)
3882 //
3883
3884
3885 :%s::::FMT:int fmt
3886 {
3887   switch (fmt)
3888     {
3889     case fmt_single: return "s";
3890     case fmt_double: return "d";
3891     case fmt_word: return "w";
3892     case fmt_long: return "l";
3893     case fmt_ps: return "ps";
3894     default: return "?";
3895     }
3896 }
3897
3898 :%s::::TF:int tf
3899 {
3900   if (tf)
3901     return "t";
3902   else
3903     return "f";
3904 }
3905
3906 :%s::::ND:int nd
3907 {
3908   if (nd)
3909     return "l";
3910   else
3911     return "";
3912 }
3913
3914 :%s::::COND:int cond
3915 {
3916   switch (cond)
3917     {
3918     case 00: return "f";
3919     case 01: return "un";
3920     case 02: return "eq";
3921     case 03: return "ueq";
3922     case 04: return "olt";
3923     case 05: return "ult";
3924     case 06: return "ole";
3925     case 07: return "ule";
3926     case 010: return "sf";
3927     case 011: return "ngle";
3928     case 012: return "seq";
3929     case 013: return "ngl";
3930     case 014: return "lt";
3931     case 015: return "nge";
3932     case 016: return "le";
3933     case 017: return "ngt";
3934     default: return "?";
3935     }
3936 }
3937
3938
3939 // Helpers:
3940 //
3941 // Check that the given FPU format is usable, and signal a
3942 // ReservedInstruction exception if not.
3943 //
3944
3945 // check_fmt_p checks that the format is single, double, or paired single.
3946 :function:::void:check_fmt_p:int fmt, instruction_word insn
3947 *mipsI:
3948 *mipsII:
3949 *mipsIII:
3950 *mipsIV:
3951 *mips32:
3952 *mips32r2:
3953 *vr4100:
3954 *vr5000:
3955 *r3900:
3956 {
3957   /* None of these ISAs support Paired Single, so just fall back to
3958      the single/double check.  */
3959   if ((fmt != fmt_single) && (fmt != fmt_double))
3960     SignalException (ReservedInstruction, insn);
3961 }
3962
3963 :function:::void:check_fmt_p:int fmt, instruction_word insn
3964 *mipsV:
3965 *mips64:
3966 *mips64r2:
3967 {
3968   if ((fmt != fmt_single) && (fmt != fmt_double)
3969       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3970     SignalException (ReservedInstruction, insn);
3971 }
3972
3973
3974 // Helper:
3975 //
3976 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3977 // exception if not.
3978 //
3979
3980 :function:::void:check_fpu:
3981 *mipsI:
3982 *mipsII:
3983 *mipsIII:
3984 *mipsIV:
3985 *mipsV:
3986 *mips32:
3987 *mips32r2:
3988 *mips64:
3989 *mips64r2:
3990 *vr4100:
3991 *vr5000:
3992 *r3900:
3993 {
3994   if (! COP_Usable (1))
3995     SignalExceptionCoProcessorUnusable (1);
3996 }
3997
3998
3999 // Helper:
4000 //
4001 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
4002 // or MIPS32.  do_load cannot be used instead because it returns an
4003 // unsigned_word, which is limited to the size of the machine's registers.
4004 //
4005
4006 :function:::unsigned64:do_load_double:address_word base, address_word offset
4007 *mipsII:
4008 *mips32:
4009 *mips32r2:
4010 {
4011   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4012   address_word vaddr;
4013   address_word paddr;
4014   int uncached;
4015   unsigned64 memval;
4016   unsigned64 v;
4017
4018   vaddr = loadstore_ea (SD_, base, offset);
4019   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4020     {
4021       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4022                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4023                        sim_core_unaligned_signal);
4024     }
4025   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4026                       isREAL);
4027   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4028               isDATA, isREAL);
4029   v = (unsigned64)memval;
4030   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4031               isDATA, isREAL);
4032   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4033 }
4034
4035
4036 // Helper:
4037 //
4038 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4039 // or MIPS32.  do_load cannot be used instead because it returns an
4040 // unsigned_word, which is limited to the size of the machine's registers.
4041 //
4042
4043 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4044 *mipsII:
4045 *mips32:
4046 *mips32r2:
4047 {
4048   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4049   address_word vaddr;
4050   address_word paddr;
4051   int uncached;
4052   unsigned64 memval;
4053
4054   vaddr = loadstore_ea (SD_, base, offset);
4055   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4056     {
4057       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4058                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4059                        sim_core_unaligned_signal);
4060     }
4061   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4062                       isREAL);
4063   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4064   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4065                isREAL);
4066   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4067   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4068                isREAL);
4069 }
4070
4071
4072 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4073 "abs.%s<FMT> f<FD>, f<FS>"
4074 *mipsI:
4075 *mipsII:
4076 *mipsIII:
4077 *mipsIV:
4078 *mipsV:
4079 *mips32:
4080 *mips32r2:
4081 *mips64:
4082 *mips64r2:
4083 *vr4100:
4084 *vr5000:
4085 *r3900:
4086 {
4087   int fmt = FMT;
4088   check_fpu (SD_);
4089   check_fmt_p (SD_, fmt, instruction_0);
4090   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
4091 }
4092
4093
4094
4095 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4096 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4097 *mipsI:
4098 *mipsII:
4099 *mipsIII:
4100 *mipsIV:
4101 *mipsV:
4102 *mips32:
4103 *mips32r2:
4104 *mips64:
4105 *mips64r2:
4106 *vr4100:
4107 *vr5000:
4108 *r3900:
4109 {
4110   int fmt = FMT;
4111   check_fpu (SD_);
4112   check_fmt_p (SD_, fmt, instruction_0);
4113   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4114 }
4115
4116
4117 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
4118 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4119 *mipsV:
4120 *mips64:
4121 *mips64r2:
4122 {
4123   unsigned64 fs;
4124   unsigned64 ft;
4125   unsigned64 fd;
4126   check_fpu (SD_);
4127   check_u64 (SD_, instruction_0);
4128   fs = ValueFPR (FS, fmt_ps);
4129   if ((GPR[RS] & 0x3) != 0)
4130     Unpredictable ();
4131   if ((GPR[RS] & 0x4) == 0)
4132     fd = fs;
4133   else
4134     {
4135       ft = ValueFPR (FT, fmt_ps);
4136       if (BigEndianCPU)
4137         fd = PackPS (PSLower (fs), PSUpper (ft));
4138       else
4139         fd = PackPS (PSLower (ft), PSUpper (fs));
4140     }
4141   StoreFPR (FD, fmt_ps, fd);
4142 }
4143
4144
4145 // BC1F
4146 // BC1FL
4147 // BC1T
4148 // BC1TL
4149
4150 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4151 "bc1%s<TF>%s<ND> <OFFSET>"
4152 *mipsI:
4153 *mipsII:
4154 *mipsIII:
4155 {
4156   check_fpu (SD_);
4157   TRACE_BRANCH_INPUT (PREVCOC1());
4158   if (PREVCOC1() == TF)
4159     {
4160       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4161       TRACE_BRANCH_RESULT (dest);
4162       DELAY_SLOT (dest);
4163     }
4164   else if (ND)
4165     {
4166       TRACE_BRANCH_RESULT (0);
4167       NULLIFY_NEXT_INSTRUCTION ();
4168     }
4169   else
4170     {
4171       TRACE_BRANCH_RESULT (NIA);
4172     }
4173 }
4174
4175 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4176 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4177 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4178 *mipsIV:
4179 *mipsV:
4180 *mips32:
4181 *mips32r2:
4182 *mips64:
4183 *mips64r2:
4184 #*vr4100:
4185 *vr5000:
4186 *r3900:
4187 {
4188   check_fpu (SD_);
4189   if (GETFCC(CC) == TF)
4190     {
4191       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4192       DELAY_SLOT (dest);
4193     }
4194   else if (ND)
4195     {
4196       NULLIFY_NEXT_INSTRUCTION ();
4197     }
4198 }
4199
4200
4201 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
4202 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4203 *mipsI:
4204 *mipsII:
4205 *mipsIII:
4206 {
4207   int fmt = FMT;
4208   check_fpu (SD_);
4209   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4210   TRACE_ALU_RESULT (ValueFCR (31));
4211 }
4212
4213 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
4214 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4215 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4216 *mipsIV:
4217 *mipsV:
4218 *mips32:
4219 *mips32r2:
4220 *mips64:
4221 *mips64r2:
4222 *vr4100:
4223 *vr5000:
4224 *r3900:
4225 {
4226   int fmt = FMT;
4227   check_fpu (SD_);
4228   check_fmt_p (SD_, fmt, instruction_0);
4229   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4230   TRACE_ALU_RESULT (ValueFCR (31));
4231 }
4232
4233
4234 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
4235 "ceil.l.%s<FMT> f<FD>, f<FS>"
4236 *mipsIII:
4237 *mipsIV:
4238 *mipsV:
4239 *mips64:
4240 *mips64r2:
4241 *vr4100:
4242 *vr5000:
4243 *r3900:
4244 {
4245   int fmt = FMT;
4246   check_fpu (SD_);
4247   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4248             fmt_long));
4249 }
4250
4251
4252 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
4253 "ceil.w.%s<FMT> f<FD>, f<FS>"
4254 *mipsII:
4255 *mipsIII:
4256 *mipsIV:
4257 *mipsV:
4258 *mips32:
4259 *mips32r2:
4260 *mips64:
4261 *mips64r2:
4262 *vr4100:
4263 *vr5000:
4264 *r3900:
4265 {
4266   int fmt = FMT;
4267   check_fpu (SD_);
4268   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4269             fmt_word));
4270 }
4271
4272
4273 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4274 "cfc1 r<RT>, f<FS>"
4275 *mipsI:
4276 *mipsII:
4277 *mipsIII:
4278 {
4279   check_fpu (SD_);
4280   if (FS == 0)
4281     PENDING_FILL (RT, EXTEND32 (FCR0));
4282   else if (FS == 31)
4283     PENDING_FILL (RT, EXTEND32 (FCR31));
4284   /* else NOP */
4285 }
4286
4287 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4288 "cfc1 r<RT>, f<FS>"
4289 *mipsIV:
4290 *vr4100:
4291 *vr5000:
4292 *r3900:
4293 {
4294   check_fpu (SD_);
4295   if (FS == 0 || FS == 31)
4296     {
4297       unsigned_word  fcr = ValueFCR (FS);
4298       TRACE_ALU_INPUT1 (fcr);
4299       GPR[RT] = fcr;
4300     }
4301   /* else NOP */
4302   TRACE_ALU_RESULT (GPR[RT]);
4303 }
4304
4305 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4306 "cfc1 r<RT>, f<FS>"
4307 *mipsV:
4308 *mips32:
4309 *mips32r2:
4310 *mips64:
4311 *mips64r2:
4312 {
4313   check_fpu (SD_);
4314   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4315     {
4316       unsigned_word  fcr = ValueFCR (FS);
4317       TRACE_ALU_INPUT1 (fcr);
4318       GPR[RT] = fcr;
4319     }
4320   /* else NOP */
4321   TRACE_ALU_RESULT (GPR[RT]);
4322 }
4323
4324 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4325 "ctc1 r<RT>, f<FS>"
4326 *mipsI:
4327 *mipsII:
4328 *mipsIII:
4329 {
4330   check_fpu (SD_);
4331   if (FS == 31)
4332     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4333   /* else NOP */
4334 }
4335
4336 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4337 "ctc1 r<RT>, f<FS>"
4338 *mipsIV:
4339 *vr4100:
4340 *vr5000:
4341 *r3900:
4342 {
4343   check_fpu (SD_);
4344   TRACE_ALU_INPUT1 (GPR[RT]);
4345   if (FS == 31)
4346     StoreFCR (FS, GPR[RT]);
4347   /* else NOP */
4348 }
4349
4350 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4351 "ctc1 r<RT>, f<FS>"
4352 *mipsV:
4353 *mips32:
4354 *mips32r2:
4355 *mips64:
4356 *mips64r2:
4357 {
4358   check_fpu (SD_);
4359   TRACE_ALU_INPUT1 (GPR[RT]);
4360   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4361       StoreFCR (FS, GPR[RT]);
4362   /* else NOP */
4363 }
4364
4365
4366 //
4367 // FIXME: Does not correctly differentiate between mips*
4368 //
4369 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4370 "cvt.d.%s<FMT> f<FD>, f<FS>"
4371 *mipsI:
4372 *mipsII:
4373 *mipsIII:
4374 *mipsIV:
4375 *mipsV:
4376 *mips32:
4377 *mips32r2:
4378 *mips64:
4379 *mips64r2:
4380 *vr4100:
4381 *vr5000:
4382 *r3900:
4383 {
4384   int fmt = FMT;
4385   check_fpu (SD_);
4386   if ((fmt == fmt_double) | 0)
4387     SignalException (ReservedInstruction, instruction_0);
4388   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4389             fmt_double));
4390 }
4391
4392
4393 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4394 "cvt.l.%s<FMT> f<FD>, f<FS>"
4395 *mipsIII:
4396 *mipsIV:
4397 *mipsV:
4398 *mips64:
4399 *mips64r2:
4400 *vr4100:
4401 *vr5000:
4402 *r3900:
4403 {
4404   int fmt = FMT;
4405   check_fpu (SD_);
4406   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4407     SignalException (ReservedInstruction, instruction_0);
4408   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4409             fmt_long));
4410 }
4411
4412
4413 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4414 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4415 *mipsV:
4416 *mips64:
4417 *mips64r2:
4418 {
4419   check_fpu (SD_);
4420   check_u64 (SD_, instruction_0);
4421   StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4422                                 ValueFPR (FT, fmt_single)));
4423 }
4424
4425
4426 //
4427 // FIXME: Does not correctly differentiate between mips*
4428 //
4429 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4430 "cvt.s.%s<FMT> f<FD>, f<FS>"
4431 *mipsI:
4432 *mipsII:
4433 *mipsIII:
4434 *mipsIV:
4435 *mipsV:
4436 *mips32:
4437 *mips32r2:
4438 *mips64:
4439 *mips64r2:
4440 *vr4100:
4441 *vr5000:
4442 *r3900:
4443 {
4444   int fmt = FMT;
4445   check_fpu (SD_);
4446   if ((fmt == fmt_single) | 0)
4447     SignalException (ReservedInstruction, instruction_0);
4448   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4449             fmt_single));
4450 }
4451
4452
4453 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4454 "cvt.s.pl f<FD>, f<FS>"
4455 *mipsV:
4456 *mips64:
4457 *mips64r2:
4458 {
4459   check_fpu (SD_);
4460   check_u64 (SD_, instruction_0);
4461   StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4462 }
4463
4464
4465 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4466 "cvt.s.pu f<FD>, f<FS>"
4467 *mipsV:
4468 *mips64:
4469 *mips64r2:
4470 {
4471   check_fpu (SD_);
4472   check_u64 (SD_, instruction_0);
4473   StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4474 }
4475
4476
4477 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4478 "cvt.w.%s<FMT> f<FD>, f<FS>"
4479 *mipsI:
4480 *mipsII:
4481 *mipsIII:
4482 *mipsIV:
4483 *mipsV:
4484 *mips32:
4485 *mips32r2:
4486 *mips64:
4487 *mips64r2:
4488 *vr4100:
4489 *vr5000:
4490 *r3900:
4491 {
4492   int fmt = FMT;
4493   check_fpu (SD_);
4494   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4495     SignalException (ReservedInstruction, instruction_0);
4496   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4497             fmt_word));
4498 }
4499
4500
4501 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4502 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4503 *mipsI:
4504 *mipsII:
4505 *mipsIII:
4506 *mipsIV:
4507 *mipsV:
4508 *mips32:
4509 *mips32r2:
4510 *mips64:
4511 *mips64r2:
4512 *vr4100:
4513 *vr5000:
4514 *r3900:
4515 {
4516   int fmt = FMT;
4517   check_fpu (SD_);
4518   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4519 }
4520
4521
4522 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4523 "dmfc1 r<RT>, f<FS>"
4524 *mipsIII:
4525 {
4526   unsigned64 v;
4527   check_fpu (SD_);
4528   check_u64 (SD_, instruction_0);
4529   if (SizeFGR () == 64)
4530     v = FGR[FS];
4531   else if ((FS & 0x1) == 0)
4532     v = SET64HI (FGR[FS+1]) | FGR[FS];
4533   else
4534     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4535   PENDING_FILL (RT, v);
4536   TRACE_ALU_RESULT (v);
4537 }
4538
4539 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4540 "dmfc1 r<RT>, f<FS>"
4541 *mipsIV:
4542 *mipsV:
4543 *mips64:
4544 *mips64r2:
4545 *vr4100:
4546 *vr5000:
4547 *r3900:
4548 {
4549   check_fpu (SD_);
4550   check_u64 (SD_, instruction_0);
4551   if (SizeFGR () == 64)
4552     GPR[RT] = FGR[FS];
4553   else if ((FS & 0x1) == 0)
4554     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4555   else
4556     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4557   TRACE_ALU_RESULT (GPR[RT]);
4558 }
4559
4560
4561 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4562 "dmtc1 r<RT>, f<FS>"
4563 *mipsIII:
4564 {
4565   unsigned64 v;
4566   check_fpu (SD_);
4567   check_u64 (SD_, instruction_0);
4568   if (SizeFGR () == 64)
4569     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4570   else if ((FS & 0x1) == 0)
4571     {
4572       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4573       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4574     }
4575   else
4576     Unpredictable ();
4577   TRACE_FP_RESULT (GPR[RT]);
4578 }
4579
4580 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4581 "dmtc1 r<RT>, f<FS>"
4582 *mipsIV:
4583 *mipsV:
4584 *mips64:
4585 *mips64r2:
4586 *vr4100:
4587 *vr5000:
4588 *r3900:
4589 {
4590   check_fpu (SD_);
4591   check_u64 (SD_, instruction_0);
4592   if (SizeFGR () == 64)
4593     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4594   else if ((FS & 0x1) == 0)
4595     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4596   else
4597     Unpredictable ();
4598 }
4599
4600
4601 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4602 "floor.l.%s<FMT> f<FD>, f<FS>"
4603 *mipsIII:
4604 *mipsIV:
4605 *mipsV:
4606 *mips64:
4607 *mips64r2:
4608 *vr4100:
4609 *vr5000:
4610 *r3900:
4611 {
4612   int fmt = FMT;
4613   check_fpu (SD_);
4614   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4615             fmt_long));
4616 }
4617
4618
4619 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4620 "floor.w.%s<FMT> f<FD>, f<FS>"
4621 *mipsII:
4622 *mipsIII:
4623 *mipsIV:
4624 *mipsV:
4625 *mips32:
4626 *mips32r2:
4627 *mips64:
4628 *mips64r2:
4629 *vr4100:
4630 *vr5000:
4631 *r3900:
4632 {
4633   int fmt = FMT;
4634   check_fpu (SD_);
4635   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4636             fmt_word));
4637 }
4638
4639
4640 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4641 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4642 *mipsII:
4643 *mips32:
4644 *mips32r2:
4645 {
4646   check_fpu (SD_);
4647   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4648 }
4649
4650
4651 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4652 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4653 *mipsIII:
4654 *mipsIV:
4655 *mipsV:
4656 *mips64:
4657 *mips64r2:
4658 *vr4100:
4659 *vr5000:
4660 *r3900:
4661 {
4662   check_fpu (SD_);
4663   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4664 }
4665
4666
4667 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4668 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4669 *mipsIV:
4670 *mipsV:
4671 *mips64:
4672 *mips64r2:
4673 *vr5000:
4674 {
4675   check_fpu (SD_);
4676   check_u64 (SD_, instruction_0);
4677   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4678 }
4679
4680
4681 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4682 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4683 *mipsV:
4684 *mips64:
4685 *mips64r2:
4686 {
4687   address_word base = GPR[BASE];
4688   address_word index = GPR[INDEX];
4689   address_word vaddr = base + index;
4690   check_fpu (SD_);
4691   check_u64 (SD_, instruction_0);
4692   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
4693   if ((vaddr & 0x7) != 0)
4694     index -= (vaddr & 0x7);
4695   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4696 }
4697
4698
4699 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4700 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4701 *mipsI:
4702 *mipsII:
4703 *mipsIII:
4704 *mipsIV:
4705 *mipsV:
4706 *mips32:
4707 *mips32r2:
4708 *mips64:
4709 *mips64r2:
4710 *vr4100:
4711 *vr5000:
4712 *r3900:
4713 {
4714   check_fpu (SD_);
4715   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4716 }
4717
4718
4719 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4720 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4721 *mipsIV:
4722 *mipsV:
4723 *mips64:
4724 *mips64r2:
4725 *vr5000:
4726 {
4727   check_fpu (SD_);
4728   check_u64 (SD_, instruction_0);
4729   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4730 }
4731
4732
4733
4734 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
4735 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4736 *mipsIV:
4737 *mipsV:
4738 *mips64:
4739 *mips64r2:
4740 *vr5000:
4741 {
4742   int fmt = FMT;
4743   check_fpu (SD_);
4744   check_u64 (SD_, instruction_0);
4745   check_fmt_p (SD_, fmt, instruction_0);
4746   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4747                                   ValueFPR (FR, fmt), fmt));
4748 }
4749
4750
4751 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4752 "mfc1 r<RT>, f<FS>"
4753 *mipsI:
4754 *mipsII:
4755 *mipsIII:
4756 {
4757   unsigned64 v;
4758   check_fpu (SD_);
4759   v = EXTEND32 (FGR[FS]);
4760   PENDING_FILL (RT, v);
4761   TRACE_ALU_RESULT (v);
4762 }
4763
4764 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4765 "mfc1 r<RT>, f<FS>"
4766 *mipsIV:
4767 *mipsV:
4768 *mips32:
4769 *mips32r2:
4770 *mips64:
4771 *mips64r2:
4772 *vr4100:
4773 *vr5000:
4774 *r3900:
4775 {
4776   check_fpu (SD_);
4777   GPR[RT] = EXTEND32 (FGR[FS]);
4778   TRACE_ALU_RESULT (GPR[RT]);
4779 }
4780
4781
4782 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4783 "mov.%s<FMT> f<FD>, f<FS>"
4784 *mipsI:
4785 *mipsII:
4786 *mipsIII:
4787 *mipsIV:
4788 *mipsV:
4789 *mips32:
4790 *mips32r2:
4791 *mips64:
4792 *mips64r2:
4793 *vr4100:
4794 *vr5000:
4795 *r3900:
4796 {
4797   int fmt = FMT;
4798   check_fpu (SD_);
4799   check_fmt_p (SD_, fmt, instruction_0);
4800   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4801 }
4802
4803
4804 // MOVF
4805 // MOVT
4806 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4807 "mov%s<TF> r<RD>, r<RS>, <CC>"
4808 *mipsIV:
4809 *mipsV:
4810 *mips32:
4811 *mips32r2:
4812 *mips64:
4813 *mips64r2:
4814 *vr5000:
4815 {
4816   check_fpu (SD_);
4817   if (GETFCC(CC) == TF)
4818     GPR[RD] = GPR[RS];
4819 }
4820
4821
4822 // MOVF.fmt
4823 // MOVT.fmt
4824 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4825 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4826 *mipsIV:
4827 *mipsV:
4828 *mips32:
4829 *mips32r2:
4830 *mips64:
4831 *mips64r2:
4832 *vr5000:
4833 {
4834   int fmt = FMT;
4835   check_fpu (SD_);
4836   if (fmt != fmt_ps)
4837     {
4838       if (GETFCC(CC) == TF)
4839         StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4840       else
4841         StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
4842     }
4843   else
4844     {
4845       unsigned64 fd;
4846       fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4847                                       fmt_ps)),
4848                    PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4849                                       fmt_ps)));
4850       StoreFPR (FD, fmt_ps, fd);
4851     }
4852 }
4853
4854
4855 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4856 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4857 *mipsIV:
4858 *mipsV:
4859 *mips32:
4860 *mips32r2:
4861 *mips64:
4862 *mips64r2:
4863 *vr5000:
4864 {
4865   check_fpu (SD_);
4866   if (GPR[RT] != 0)
4867     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4868   else
4869     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4870 }
4871
4872
4873 // MOVT see MOVtf
4874
4875
4876 // MOVT.fmt see MOVtf.fmt
4877
4878
4879
4880 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4881 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4882 *mipsIV:
4883 *mipsV:
4884 *mips32:
4885 *mips32r2:
4886 *mips64:
4887 *mips64r2:
4888 *vr5000:
4889 {
4890   check_fpu (SD_);
4891   if (GPR[RT] == 0)
4892     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4893   else
4894     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4895 }
4896
4897
4898 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
4899 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4900 *mipsIV:
4901 *mipsV:
4902 *mips64:
4903 *mips64r2:
4904 *vr5000:
4905 {
4906   int fmt = FMT;
4907   check_fpu (SD_);
4908   check_u64 (SD_, instruction_0);
4909   check_fmt_p (SD_, fmt, instruction_0);
4910   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4911                                   ValueFPR (FR, fmt), fmt));
4912 }
4913
4914
4915 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4916 "mtc1 r<RT>, f<FS>"
4917 *mipsI:
4918 *mipsII:
4919 *mipsIII:
4920 {
4921   check_fpu (SD_);
4922   if (SizeFGR () == 64)
4923     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4924   else
4925     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4926   TRACE_FP_RESULT (GPR[RT]);
4927 }
4928
4929 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4930 "mtc1 r<RT>, f<FS>"
4931 *mipsIV:
4932 *mipsV:
4933 *mips32:
4934 *mips32r2:
4935 *mips64:
4936 *mips64r2:
4937 *vr4100:
4938 *vr5000:
4939 *r3900:
4940 {
4941   check_fpu (SD_);
4942   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4943 }
4944
4945
4946 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4947 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4948 *mipsI:
4949 *mipsII:
4950 *mipsIII:
4951 *mipsIV:
4952 *mipsV:
4953 *mips32:
4954 *mips32r2:
4955 *mips64:
4956 *mips64r2:
4957 *vr4100:
4958 *vr5000:
4959 *r3900:
4960 {
4961   int fmt = FMT;
4962   check_fpu (SD_);
4963   check_fmt_p (SD_, fmt, instruction_0);
4964   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4965 }
4966
4967
4968 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4969 "neg.%s<FMT> f<FD>, f<FS>"
4970 *mipsI:
4971 *mipsII:
4972 *mipsIII:
4973 *mipsIV:
4974 *mipsV:
4975 *mips32:
4976 *mips32r2:
4977 *mips64:
4978 *mips64r2:
4979 *vr4100:
4980 *vr5000:
4981 *r3900:
4982 {
4983   int fmt = FMT;
4984   check_fpu (SD_);
4985   check_fmt_p (SD_, fmt, instruction_0);
4986   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4987 }
4988
4989
4990 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
4991 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4992 *mipsIV:
4993 *mipsV:
4994 *mips64:
4995 *mips64r2:
4996 *vr5000:
4997 {
4998   int fmt = FMT;
4999   check_fpu (SD_);
5000   check_u64 (SD_, instruction_0);
5001   check_fmt_p (SD_, fmt, instruction_0);
5002   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5003                                      ValueFPR (FR, fmt), fmt));
5004 }
5005
5006
5007 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
5008 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5009 *mipsIV:
5010 *mipsV:
5011 *mips64:
5012 *mips64r2:
5013 *vr5000:
5014 {
5015   int fmt = FMT;
5016   check_fpu (SD_);
5017   check_u64 (SD_, instruction_0);
5018   check_fmt_p (SD_, fmt, instruction_0);
5019   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5020                                      ValueFPR (FR, fmt), fmt));
5021 }
5022
5023
5024 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
5025 "pll.ps f<FD>, f<FS>, f<FT>"
5026 *mipsV:
5027 *mips64:
5028 *mips64r2:
5029 {
5030   check_fpu (SD_);
5031   check_u64 (SD_, instruction_0);
5032   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5033                                 PSLower (ValueFPR (FT, fmt_ps))));
5034 }
5035
5036
5037 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
5038 "plu.ps f<FD>, f<FS>, f<FT>"
5039 *mipsV:
5040 *mips64:
5041 *mips64r2:
5042 {
5043   check_fpu (SD_);
5044   check_u64 (SD_, instruction_0);
5045   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5046                                 PSUpper (ValueFPR (FT, fmt_ps))));
5047 }
5048
5049
5050 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
5051 "prefx <HINT>, r<INDEX>(r<BASE>)"
5052 *mipsIV:
5053 *mipsV:
5054 *mips64:
5055 *mips64r2:
5056 *vr5000:
5057 {
5058   address_word base = GPR[BASE];
5059   address_word index = GPR[INDEX];
5060   {
5061     address_word vaddr = loadstore_ea (SD_, base, index);
5062     address_word paddr;
5063     int uncached;
5064     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5065       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
5066   }
5067 }
5068
5069
5070 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
5071 "pul.ps f<FD>, f<FS>, f<FT>"
5072 *mipsV:
5073 *mips64:
5074 *mips64r2:
5075 {
5076   check_fpu (SD_);
5077   check_u64 (SD_, instruction_0);
5078   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5079                                 PSLower (ValueFPR (FT, fmt_ps))));
5080 }
5081
5082
5083 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
5084 "puu.ps f<FD>, f<FS>, f<FT>"
5085 *mipsV:
5086 *mips64:
5087 *mips64r2:
5088 {
5089   check_fpu (SD_);
5090   check_u64 (SD_, instruction_0);
5091   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5092                                 PSUpper (ValueFPR (FT, fmt_ps))));
5093 }
5094
5095
5096 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
5097 "recip.%s<FMT> f<FD>, f<FS>"
5098 *mipsIV:
5099 *mipsV:
5100 *mips64:
5101 *mips64r2:
5102 *vr5000:
5103 {
5104   int fmt = FMT;
5105   check_fpu (SD_);
5106   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
5107 }
5108
5109
5110 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
5111 "round.l.%s<FMT> f<FD>, f<FS>"
5112 *mipsIII:
5113 *mipsIV:
5114 *mipsV:
5115 *mips64:
5116 *mips64r2:
5117 *vr4100:
5118 *vr5000:
5119 *r3900:
5120 {
5121   int fmt = FMT;
5122   check_fpu (SD_);
5123   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5124             fmt_long));
5125 }
5126
5127
5128 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
5129 "round.w.%s<FMT> f<FD>, f<FS>"
5130 *mipsII:
5131 *mipsIII:
5132 *mipsIV:
5133 *mipsV:
5134 *mips32:
5135 *mips32r2:
5136 *mips64:
5137 *mips64r2:
5138 *vr4100:
5139 *vr5000:
5140 *r3900:
5141 {
5142   int fmt = FMT;
5143   check_fpu (SD_);
5144   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5145             fmt_word));
5146 }
5147
5148
5149 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
5150 "rsqrt.%s<FMT> f<FD>, f<FS>"
5151 *mipsIV:
5152 *mipsV:
5153 *mips64:
5154 *mips64r2:
5155 *vr5000:
5156 {
5157   int fmt = FMT;
5158   check_fpu (SD_);
5159   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
5160 }
5161
5162
5163 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
5164 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5165 *mipsII:
5166 *mips32:
5167 *mips32r2:
5168 {
5169   check_fpu (SD_);
5170   do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5171 }
5172
5173
5174 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5175 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5176 *mipsIII:
5177 *mipsIV:
5178 *mipsV:
5179 *mips64:
5180 *mips64r2:
5181 *vr4100:
5182 *vr5000:
5183 *r3900:
5184 {
5185   check_fpu (SD_);
5186   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5187 }
5188
5189
5190 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
5191 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5192 *mipsIV:
5193 *mipsV:
5194 *mips64:
5195 *mips64r2:
5196 *vr5000:
5197 {
5198   check_fpu (SD_);
5199   check_u64 (SD_, instruction_0);
5200   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5201 }
5202
5203
5204 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5205 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5206 *mipsV:
5207 *mips64:
5208 *mips64r2:
5209 {
5210   unsigned64 v;
5211   address_word base = GPR[BASE];
5212   address_word index = GPR[INDEX];
5213   address_word vaddr = base + index;
5214   check_fpu (SD_);
5215   check_u64 (SD_, instruction_0);
5216   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
5217   if ((vaddr & 0x7) != 0)
5218     index -= (vaddr & 0x7);
5219   do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5220 }
5221
5222
5223 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
5224 "sqrt.%s<FMT> f<FD>, f<FS>"
5225 *mipsII:
5226 *mipsIII:
5227 *mipsIV:
5228 *mipsV:
5229 *mips32:
5230 *mips32r2:
5231 *mips64:
5232 *mips64r2:
5233 *vr4100:
5234 *vr5000:
5235 *r3900:
5236 {
5237   int fmt = FMT;
5238   check_fpu (SD_);
5239   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
5240 }
5241
5242
5243 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
5244 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5245 *mipsI:
5246 *mipsII:
5247 *mipsIII:
5248 *mipsIV:
5249 *mipsV:
5250 *mips32:
5251 *mips32r2:
5252 *mips64:
5253 *mips64r2:
5254 *vr4100:
5255 *vr5000:
5256 *r3900:
5257 {
5258   int fmt = FMT;
5259   check_fpu (SD_);
5260   check_fmt_p (SD_, fmt, instruction_0);
5261   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5262 }
5263
5264
5265
5266 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
5267 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5268 *mipsI:
5269 *mipsII:
5270 *mipsIII:
5271 *mipsIV:
5272 *mipsV:
5273 *mips32:
5274 *mips32r2:
5275 *mips64:
5276 *mips64r2:
5277 *vr4100:
5278 *vr5000:
5279 *r3900:
5280 {
5281   address_word base = GPR[BASE];
5282   address_word offset = EXTEND16 (OFFSET);
5283   check_fpu (SD_);
5284   {
5285     address_word vaddr = loadstore_ea (SD_, base, offset);
5286     address_word paddr;
5287     int uncached;
5288     if ((vaddr & 3) != 0)
5289       {
5290         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5291       }
5292     else
5293       {
5294         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5295           {
5296             uword64 memval = 0;
5297             uword64 memval1 = 0;
5298             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5299             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5300             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5301             unsigned int byte;
5302             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5303             byte = ((vaddr & mask) ^ bigendiancpu);
5304             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
5305             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5306           }
5307       }
5308   }
5309 }
5310
5311
5312 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
5313 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5314 *mipsIV:
5315 *mipsV:
5316 *mips64:
5317 *mips64r2:
5318 *vr5000:
5319 {
5320
5321   address_word base = GPR[BASE];
5322   address_word index = GPR[INDEX];
5323   check_fpu (SD_);
5324   check_u64 (SD_, instruction_0);
5325   {
5326    address_word vaddr = loadstore_ea (SD_, base, index);
5327    address_word paddr;
5328    int uncached;
5329    if ((vaddr & 3) != 0)
5330      {
5331        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5332      }
5333    else
5334    {
5335     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5336     {
5337      unsigned64 memval = 0;
5338      unsigned64 memval1 = 0;
5339      unsigned64 mask = 0x7;
5340      unsigned int byte;
5341      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5342      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5343      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
5344       {
5345        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5346       }
5347     }
5348    }
5349   }
5350 }
5351
5352
5353 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
5354 "trunc.l.%s<FMT> f<FD>, f<FS>"
5355 *mipsIII:
5356 *mipsIV:
5357 *mipsV:
5358 *mips64:
5359 *mips64r2:
5360 *vr4100:
5361 *vr5000:
5362 *r3900:
5363 {
5364   int fmt = FMT;
5365   check_fpu (SD_);
5366   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5367             fmt_long));
5368 }
5369
5370
5371 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
5372 "trunc.w.%s<FMT> f<FD>, f<FS>"
5373 *mipsII:
5374 *mipsIII:
5375 *mipsIV:
5376 *mipsV:
5377 *mips32:
5378 *mips32r2:
5379 *mips64:
5380 *mips64r2:
5381 *vr4100:
5382 *vr5000:
5383 *r3900:
5384 {
5385   int fmt = FMT;
5386   check_fpu (SD_);
5387   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5388             fmt_word));
5389 }
5390
5391 \f
5392 //
5393 // MIPS Architecture:
5394 //
5395 //        System Control Instruction Set (COP0)
5396 //
5397
5398
5399 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5400 "bc0f <OFFSET>"
5401 *mipsI:
5402 *mipsII:
5403 *mipsIII:
5404 *mipsIV:
5405 *mipsV:
5406 *mips32:
5407 *mips32r2:
5408 *mips64:
5409 *mips64r2:
5410 *vr4100:
5411 *vr5000:
5412
5413 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5414 "bc0f <OFFSET>"
5415 // stub needed for eCos as tx39 hardware bug workaround
5416 *r3900:
5417 {
5418   /* do nothing */
5419 }
5420
5421
5422 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5423 "bc0fl <OFFSET>"
5424 *mipsI:
5425 *mipsII:
5426 *mipsIII:
5427 *mipsIV:
5428 *mipsV:
5429 *mips32:
5430 *mips32r2:
5431 *mips64:
5432 *mips64r2:
5433 *vr4100:
5434 *vr5000:
5435
5436
5437 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5438 "bc0t <OFFSET>"
5439 *mipsI:
5440 *mipsII:
5441 *mipsIII:
5442 *mipsIV:
5443 *mipsV:
5444 *mips32:
5445 *mips32r2:
5446 *mips64:
5447 *mips64r2:
5448 *vr4100:
5449
5450
5451 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5452 "bc0tl <OFFSET>"
5453 *mipsI:
5454 *mipsII:
5455 *mipsIII:
5456 *mipsIV:
5457 *mipsV:
5458 *mips32:
5459 *mips32r2:
5460 *mips64:
5461 *mips64r2:
5462 *vr4100:
5463 *vr5000:
5464
5465
5466 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5467 "cache <OP>, <OFFSET>(r<BASE>)"
5468 *mipsIII:
5469 *mipsIV:
5470 *mipsV:
5471 *mips32:
5472 *mips32r2:
5473 *mips64:
5474 *mips64r2:
5475 *vr4100:
5476 *vr5000:
5477 *r3900:
5478 {
5479   address_word base = GPR[BASE];
5480   address_word offset = EXTEND16 (OFFSET);
5481   {
5482     address_word vaddr = loadstore_ea (SD_, base, offset);
5483     address_word paddr;
5484     int uncached;
5485     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5486       CacheOp(OP,vaddr,paddr,instruction_0);
5487   }
5488 }
5489
5490
5491 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5492 "dmfc0 r<RT>, r<RD>"
5493 *mipsIII:
5494 *mipsIV:
5495 *mipsV:
5496 *mips64:
5497 *mips64r2:
5498 {
5499   check_u64 (SD_, instruction_0);
5500   DecodeCoproc (instruction_0);
5501 }
5502
5503
5504 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5505 "dmtc0 r<RT>, r<RD>"
5506 *mipsIII:
5507 *mipsIV:
5508 *mipsV:
5509 *mips64:
5510 *mips64r2:
5511 {
5512   check_u64 (SD_, instruction_0);
5513   DecodeCoproc (instruction_0);
5514 }
5515
5516
5517 010000,1,0000000000000000000,011000:COP0:32::ERET
5518 "eret"
5519 *mipsIII:
5520 *mipsIV:
5521 *mipsV:
5522 *mips32:
5523 *mips32r2:
5524 *mips64:
5525 *mips64r2:
5526 *vr4100:
5527 *vr5000:
5528 {
5529   if (SR & status_ERL)
5530     {
5531       /* Oops, not yet available */
5532       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5533       NIA = EPC;
5534       SR &= ~status_ERL;
5535     }
5536   else
5537     {
5538       NIA = EPC;
5539       SR &= ~status_EXL;
5540     }
5541 }
5542
5543
5544 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5545 "mfc0 r<RT>, r<RD> # <REGX>"
5546 *mipsI:
5547 *mipsII:
5548 *mipsIII:
5549 *mipsIV:
5550 *mipsV:
5551 *mips32:
5552 *mips32r2:
5553 *mips64:
5554 *mips64r2:
5555 *vr4100:
5556 *vr5000:
5557 *r3900:
5558 {
5559   TRACE_ALU_INPUT0 ();
5560   DecodeCoproc (instruction_0);
5561   TRACE_ALU_RESULT (GPR[RT]);
5562 }
5563
5564 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5565 "mtc0 r<RT>, r<RD> # <REGX>"
5566 *mipsI:
5567 *mipsII:
5568 *mipsIII:
5569 *mipsIV:
5570 *mipsV:
5571 *mips32:
5572 *mips32r2:
5573 *mips64:
5574 *mips64r2:
5575 *vr4100:
5576 *vr5000:
5577 *r3900:
5578 {
5579   DecodeCoproc (instruction_0);
5580 }
5581
5582
5583 010000,1,0000000000000000000,010000:COP0:32::RFE
5584 "rfe"
5585 *mipsI:
5586 *mipsII:
5587 *mipsIII:
5588 *mipsIV:
5589 *mipsV:
5590 *vr4100:
5591 *vr5000:
5592 *r3900:
5593 {
5594   DecodeCoproc (instruction_0);
5595 }
5596
5597
5598 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5599 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5600 *mipsI:
5601 *mipsII:
5602 *mipsIII:
5603 *mipsIV:
5604 *mipsV:
5605 *mips32:
5606 *mips32r2:
5607 *mips64:
5608 *mips64r2:
5609 *vr4100:
5610 *r3900:
5611 {
5612   DecodeCoproc (instruction_0);
5613 }
5614
5615
5616
5617 010000,1,0000000000000000000,001000:COP0:32::TLBP
5618 "tlbp"
5619 *mipsI:
5620 *mipsII:
5621 *mipsIII:
5622 *mipsIV:
5623 *mipsV:
5624 *mips32:
5625 *mips32r2:
5626 *mips64:
5627 *mips64r2:
5628 *vr4100:
5629 *vr5000:
5630
5631
5632 010000,1,0000000000000000000,000001:COP0:32::TLBR
5633 "tlbr"
5634 *mipsI:
5635 *mipsII:
5636 *mipsIII:
5637 *mipsIV:
5638 *mipsV:
5639 *mips32:
5640 *mips32r2:
5641 *mips64:
5642 *mips64r2:
5643 *vr4100:
5644 *vr5000:
5645
5646
5647 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5648 "tlbwi"
5649 *mipsI:
5650 *mipsII:
5651 *mipsIII:
5652 *mipsIV:
5653 *mipsV:
5654 *mips32:
5655 *mips32r2:
5656 *mips64:
5657 *mips64r2:
5658 *vr4100:
5659 *vr5000:
5660
5661
5662 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5663 "tlbwr"
5664 *mipsI:
5665 *mipsII:
5666 *mipsIII:
5667 *mipsIV:
5668 *mipsV:
5669 *mips32:
5670 *mips32r2:
5671 *mips64:
5672 *mips64r2:
5673 *vr4100:
5674 *vr5000:
5675
5676
5677 :include:::mips3264r2.igen
5678 :include:::m16.igen
5679 :include:::m16e.igen
5680 :include:::mdmx.igen
5681 :include:::mips3d.igen
5682 :include:::sb1.igen
5683 :include:::tx.igen
5684 :include:::vr.igen
5685 :include:::dsp.igen
5686