sim/mips/mips.igen

   1 //    <insn> ::=
   2 //        <insn-word> { "+" <insn-word> }
   3 //        ":" <format-name>
   4 //        ":" <filter-flags>
   5 //        ":" <options>
   6 //        ":" <name>
   7 //        <nl>
   8 //        { <insn-model> }
   9 //        { <insn-mnemonic> }
  10 //        <code-block>
  11 //
  12
  13
  14 // IGEN config - mips16
  15 :option:16::insn-bit-size:16
  16 :option:16::hi-bit-nr:15
  17 :option:16::insn-specifying-widths:true
  18 :option:16::gen-delayed-branch:false
  19
  20 // IGEN config - mips32/64..
  21 :option:32::insn-bit-size:32
  22 :option:32::hi-bit-nr:31
  23 :option:32::insn-specifying-widths:true
  24 :option:32::gen-delayed-branch:false
  25
  26
  27 // Generate separate simulators for each target
  28 // :option:::multi-sim:true
  29
  30
  31 // Models known by this simulator
  32 :model:::mipsI:mipsI:
  33 :model:::mipsII:mipsII:
  34 :model:::mipsIII:mipsIII:
  35 :model:::mipsIV:mipsIV:
  36 :model:::mips16:mips16:
  37 // start-sanitize-r5900
  38 :model:::r5900:r5900:
  39 // end-sanitize-r5900
  40 :model:::r3900:r3900:
  41 // start-sanitize-tx19
  42 :model:::tx19:tx19:
  43 // end-sanitize-tx19
  44 // start-sanitize-vr5400
  45 :model:::vr5400:vr5400:
  46 // end-sanitize-vr5400
  47
  48
  49
  50 // Pseudo instructions known by IGEN
  51 :internal::::illegal:
  52 {
  53   sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
  54                   (unsigned long) CIA);
  55   sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
  56 }
  57
  58
  59
  60
  61 //
  62 // MIPS Architecture:
  63 //
  64 //        CPU Instruction Set (mipsI - mipsIV)
  65 //
  66
  67
  68 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
  69 "add r<RD>, r<RS>, r<RT>"
  70 *mipsI:
  71 *mipsII:
  72 *mipsIII:
  73 *mipsIV:
  74 // start-sanitize-vr5400
  75 *vr5400:
  76 // end-sanitize-vr5400
  77 // start-sanitize-r5900
  78 *r5900:
  79 // end-sanitize-r5900
  80 *r3900:
  81 // start-sanitize-tx19
  82 *tx19:
  83 // end-sanitize-tx19
  84 {
  85   ALU32_BEGIN (GPR[RS]);
  86   ALU32_ADD (GPR[RT]);
  87   ALU32_END (GPR[RD]);
  88 }
  89
  90
  91 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
  92 "addi r<RT>, r<RS>, IMMEDIATE"
  93 *mipsI:
  94 *mipsII:
  95 *mipsIII:
  96 *mipsIV:
  97 // start-sanitize-vr5400
  98 *vr5400:
  99 // end-sanitize-vr5400
 100 // start-sanitize-r5900
 101 *r5900:
 102 // end-sanitize-r5900
 103 *r3900:
 104 // start-sanitize-tx19
 105 *tx19:
 106 // end-sanitize-tx19
 107 {
 108   ALU32_BEGIN (GPR[RS]);
 109   ALU32_ADD (EXTEND16 (IMMEDIATE));
 110   ALU32_END (GPR[RT]);
 111 }
 112
 113
 114 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 115 "add r<RT>, r<RS>, IMMEDIATE"
 116 *mipsI:
 117 *mipsII:
 118 *mipsIII:
 119 *mipsIV:
 120 // start-sanitize-vr5400
 121 *vr5400:
 122 // end-sanitize-vr5400
 123 // start-sanitize-r5900
 124 *r5900:
 125 // end-sanitize-r5900
 126 *r3900:
 127 // start-sanitize-tx19
 128 *tx19:
 129 // end-sanitize-tx19
 130 {
 131   signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
 132   GPR[RT] = EXTEND32 (temp);
 133 }
 134
 135
 136 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 137 *mipsI:
 138 *mipsII:
 139 *mipsIII:
 140 *mipsIV:
 141 // start-sanitize-vr5400
 142 *vr5400:
 143 // end-sanitize-vr5400
 144 // start-sanitize-r5900
 145 *r5900:
 146 // end-sanitize-r5900
 147 *r3900:
 148 // start-sanitize-tx19
 149 *tx19:
 150 // end-sanitize-tx19
 151 {
 152   signed32 temp = GPR[RS] + GPR[RT];
 153   GPR[RD] = EXTEND32 (temp);
 154 }
 155
 156
 157 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 158 "and r<RD>, r<RS>, r<RT>"
 159 *mipsI:
 160 *mipsII:
 161 *mipsIII:
 162 *mipsIV:
 163 // start-sanitize-vr5400
 164 *vr5400:
 165 // end-sanitize-vr5400
 166 // start-sanitize-r5900
 167 *r5900:
 168 // end-sanitize-r5900
 169 *r3900:
 170 // start-sanitize-tx19
 171 *tx19:
 172 // end-sanitize-tx19
 173 {
 174   GPR[RD] = GPR[RS] & GPR[RT];
 175 }
 176
 177
 178 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 179 "and r<RT>, r<RS>, IMMEDIATE"
 180 *mipsI:
 181 *mipsII:
 182 *mipsIII:
 183 // start-sanitize-vr5400
 184 *vr5400:
 185 // end-sanitize-vr5400
 186 // start-sanitize-r5900
 187 *r5900:
 188 // end-sanitize-r5900
 189 *r3900:
 190 // start-sanitize-tx19
 191 *tx19:
 192 // end-sanitize-tx19
 193 {
 194   GPR[RT] = GPR[RS] & IMMEDIATE;
 195 }
 196
 197
 198 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 199 "beq r<RS>, r<RT>, OFFSET"
 200 *mipsI:
 201 *mipsII:
 202 *mipsIII:
 203 *mipsIV:
 204 // start-sanitize-vr5400
 205 *vr5400:
 206 // end-sanitize-vr5400
 207 // start-sanitize-r5900
 208 *r5900:
 209 // end-sanitize-r5900
 210 *r3900:
 211 // start-sanitize-tx19
 212 *tx19:
 213 // end-sanitize-tx19
 214 {
 215   address_word offset = EXTEND16 (OFFSET) << 2;
 216   if (GPR[RS] == GPR[RT])
 217     DELAY_SLOT (PC + offset);
 218 }
 219
 220
 221 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 222 "beql r<RS>, r<RT>, <OFFSET>"
 223 *mipsII:
 224 *mipsIII:
 225 *mipsIV:
 226 // start-sanitize-vr5400
 227 *vr5400:
 228 // end-sanitize-vr5400
 229 // start-sanitize-r5900
 230 *r5900:
 231 // end-sanitize-r5900
 232 *r3900:
 233 // start-sanitize-tx19
 234 *tx19:
 235 // end-sanitize-tx19
 236 {
 237   address_word offset = EXTEND16 (OFFSET) << 2;
 238   if (GPR[RS] == GPR[RT])
 239     DELAY_SLOT (PC + offset);
 240   else
 241     NULLIFY_NEXT_INSTRUCTION ();
 242 }
 243
 244
 245 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 246 "bgez r<RS>, <OFFSET>"
 247 *mipsI:
 248 *mipsII:
 249 *mipsIII:
 250 *mipsIV:
 251 // start-sanitize-vr5400
 252 *vr5400:
 253 // end-sanitize-vr5400
 254 // start-sanitize-r5900
 255 *r5900:
 256 // end-sanitize-r5900
 257 *r3900:
 258 // start-sanitize-tx19
 259 *tx19:
 260 // end-sanitize-tx19
 261 {
 262   address_word offset = EXTEND16 (OFFSET) << 2;
 263   if (GPR[RS] >= 0)
 264     DELAY_SLOT (PC + offset);
 265 }
 266
 267
 268 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 269 "bgezal r<RS>, <OFFSET>"
 270 *mipsI:
 271 *mipsII:
 272 *mipsIII:
 273 *mipsIV:
 274 // start-sanitize-vr5400
 275 *vr5400:
 276 // end-sanitize-vr5400
 277 // start-sanitize-r5900
 278 *r5900:
 279 // end-sanitize-r5900
 280 *r3900:
 281 // start-sanitize-tx19
 282 *tx19:
 283 // end-sanitize-tx19
 284 {
 285   address_word offset = EXTEND16 (OFFSET) << 2;
 286   RA = (CIA + 8);
 287   if (GPR[RS] >= 0)
 288     DELAY_SLOT (PC + offset);
 289 }
 290
 291
 292 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 293 "bgezall r<RS>, <OFFSET>"
 294 *mipsII:
 295 *mipsIII:
 296 *mipsIV:
 297 // start-sanitize-vr5400
 298 *vr5400:
 299 // end-sanitize-vr5400
 300 // start-sanitize-r5900
 301 *r5900:
 302 // end-sanitize-r5900
 303 *r3900:
 304 // start-sanitize-tx19
 305 *tx19:
 306 // end-sanitize-tx19
 307 {
 308   address_word offset = EXTEND16 (OFFSET) << 2;
 309   RA = (CIA + 8);
 310   /* NOTE: The branch occurs AFTER the next instruction has been
 311      executed */
 312   if (GPR[RS] >= 0)
 313     DELAY_SLOT (PC + offset);
 314   else
 315     NULLIFY_NEXT_INSTRUCTION ();
 316 }
 317
 318
 319 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 320 "bgezl r<RS>, <OFFSET>"
 321 *mipsII:
 322 *mipsIII:
 323 *mipsIV:
 324 // start-sanitize-vr5400
 325 *vr5400:
 326 // end-sanitize-vr5400
 327 // start-sanitize-r5900
 328 *r5900:
 329 // end-sanitize-r5900
 330 *r3900:
 331 // start-sanitize-tx19
 332 *tx19:
 333 // end-sanitize-tx19
 334 {
 335   address_word offset = EXTEND16 (OFFSET) << 2;
 336   if (GPR[RS] >= 0)
 337     DELAY_SLOT (PC + offset);
 338   else
 339     NULLIFY_NEXT_INSTRUCTION ();
 340 }
 341
 342
 343 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 344 "bgtz r<RS>, <OFFSET>"
 345 *mipsI:
 346 *mipsII:
 347 *mipsIII:
 348 *mipsIV:
 349 // start-sanitize-vr5400
 350 *vr5400:
 351 // end-sanitize-vr5400
 352 // start-sanitize-r5900
 353 *r5900:
 354 // end-sanitize-r5900
 355 *r3900:
 356 // start-sanitize-tx19
 357 *tx19:
 358 // end-sanitize-tx19
 359 {
 360   address_word offset = EXTEND16 (OFFSET) << 2;
 361   if (GPR[RS] > 0)
 362     DELAY_SLOT (PC + offset);
 363 }
 364
 365
 366 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 367 "bgtzl r<RS>, <OFFSET>"
 368 *mipsII:
 369 *mipsIII:
 370 *mipsIV:
 371 // start-sanitize-vr5400
 372 *vr5400:
 373 // end-sanitize-vr5400
 374 // start-sanitize-r5900
 375 *r5900:
 376 // end-sanitize-r5900
 377 *r3900:
 378 // start-sanitize-tx19
 379 *tx19:
 380 // end-sanitize-tx19
 381 {
 382   address_word offset = EXTEND16 (OFFSET) << 2;
 383   /* NOTE: The branch occurs AFTER the next instruction has been
 384      executed */
 385   if (GPR[RS] > 0)
 386     DELAY_SLOT (PC + offset);
 387   else
 388     NULLIFY_NEXT_INSTRUCTION ();
 389 }
 390
 391
 392 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 393 "blez r<RS>, <OFFSET>"
 394 *mipsI:
 395 *mipsII:
 396 *mipsIII:
 397 *mipsIV:
 398 // start-sanitize-vr5400
 399 *vr5400:
 400 // end-sanitize-vr5400
 401 // start-sanitize-r5900
 402 *r5900:
 403 // end-sanitize-r5900
 404 *r3900:
 405 // start-sanitize-tx19
 406 *tx19:
 407 // end-sanitize-tx19
 408 {
 409   address_word offset = EXTEND16 (OFFSET) << 2;
 410   /* NOTE: The branch occurs AFTER the next instruction has been
 411      executed */
 412   if (GPR[RS] <= 0)
 413     DELAY_SLOT (PC + offset);
 414 }
 415
 416
 417 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 418 "bgezl r<RS>, <OFFSET>"
 419 *mipsII:
 420 *mipsIII:
 421 *mipsIV:
 422 // start-sanitize-vr5400
 423 *vr5400:
 424 // end-sanitize-vr5400
 425 // start-sanitize-r5900
 426 *r5900:
 427 // end-sanitize-r5900
 428 *r3900:
 429 // start-sanitize-tx19
 430 *tx19:
 431 // end-sanitize-tx19
 432 {
 433   address_word offset = EXTEND16 (OFFSET) << 2;
 434   if (GPR[RS] <= 0)
 435     DELAY_SLOT (PC + offset);
 436   else
 437     NULLIFY_NEXT_INSTRUCTION ();
 438 }
 439
 440
 441 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 442 "bltz r<RS>, <OFFSET>"
 443 *mipsI:
 444 *mipsII:
 445 *mipsIII:
 446 *mipsIV:
 447 // start-sanitize-vr5400
 448 *vr5400:
 449 // end-sanitize-vr5400
 450 // start-sanitize-r5900
 451 *r5900:
 452 // end-sanitize-r5900
 453 *r3900:
 454 // start-sanitize-tx19
 455 *tx19:
 456 // end-sanitize-tx19
 457 {
 458   address_word offset = EXTEND16 (OFFSET) << 2;
 459   if (GPR[RS] < 0)
 460     DELAY_SLOT (PC + offset);
 461 }
 462
 463
 464 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 465 "bltzal r<RS>, <OFFSET>"
 466 *mipsI:
 467 *mipsII:
 468 *mipsIII:
 469 *mipsIV:
 470 // start-sanitize-vr5400
 471 *vr5400:
 472 // end-sanitize-vr5400
 473 // start-sanitize-r5900
 474 *r5900:
 475 // end-sanitize-r5900
 476 *r3900:
 477 // start-sanitize-tx19
 478 *tx19:
 479 // end-sanitize-tx19
 480 {
 481   address_word offset = EXTEND16 (OFFSET) << 2;
 482   RA = (CIA + 8);
 483   /* NOTE: The branch occurs AFTER the next instruction has been
 484      executed */
 485   if (GPR[RS] < 0)
 486     DELAY_SLOT (PC + offset);
 487 }
 488
 489
 490 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 491 "bltzall r<RS>, <OFFSET>"
 492 *mipsII:
 493 *mipsIII:
 494 *mipsIV:
 495 // start-sanitize-vr5400
 496 *vr5400:
 497 // end-sanitize-vr5400
 498 // start-sanitize-r5900
 499 *r5900:
 500 // end-sanitize-r5900
 501 *r3900:
 502 // start-sanitize-tx19
 503 *tx19:
 504 // end-sanitize-tx19
 505 {
 506   address_word offset = EXTEND16 (OFFSET) << 2;
 507   RA = (CIA + 8);
 508   if (GPR[RS] < 0)
 509     DELAY_SLOT (PC + offset);
 510   else
 511     NULLIFY_NEXT_INSTRUCTION ();
 512 }
 513
 514
 515 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 516 "bltzl r<RS>, <OFFSET>"
 517 *mipsII:
 518 *mipsIII:
 519 *mipsIV:
 520 // start-sanitize-vr5400
 521 *vr5400:
 522 // end-sanitize-vr5400
 523 // start-sanitize-r5900
 524 *r5900:
 525 // end-sanitize-r5900
 526 *r3900:
 527 // start-sanitize-tx19
 528 *tx19:
 529 // end-sanitize-tx19
 530 {
 531   address_word offset = EXTEND16 (OFFSET) << 2;
 532   /* NOTE: The branch occurs AFTER the next instruction has been
 533      executed */
 534   if (GPR[RS] < 0)
 535     DELAY_SLOT (PC + offset);
 536   else
 537     NULLIFY_NEXT_INSTRUCTION ();
 538 }
 539
 540
 541 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 542 "bne r<RS>, r<RT>, <OFFSET>"
 543 *mipsI:
 544 *mipsII:
 545 *mipsIII:
 546 *mipsIV:
 547 // start-sanitize-vr5400
 548 *vr5400:
 549 // end-sanitize-vr5400
 550 // start-sanitize-r5900
 551 *r5900:
 552 // end-sanitize-r5900
 553 *r3900:
 554 // start-sanitize-tx19
 555 *tx19:
 556 // end-sanitize-tx19
 557 {
 558   address_word offset = EXTEND16 (OFFSET) << 2;
 559   if (GPR[RS] != GPR[RT])
 560     DELAY_SLOT (PC + offset);
 561 }
 562
 563
 564 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 565 "bnel r<RS>, r<RT>, <OFFSET>"
 566 *mipsII:
 567 *mipsIII:
 568 *mipsIV:
 569 // start-sanitize-vr5400
 570 *vr5400:
 571 // end-sanitize-vr5400
 572 // start-sanitize-r5900
 573 *r5900:
 574 // end-sanitize-r5900
 575 *r3900:
 576 // start-sanitize-tx19
 577 *tx19:
 578 // end-sanitize-tx19
 579 {
 580   address_word offset = EXTEND16 (OFFSET) << 2;
 581   if (GPR[RS] != GPR[RT])
 582     DELAY_SLOT (PC + offset);
 583   else
 584     NULLIFY_NEXT_INSTRUCTION ();
 585 }
 586
 587
 588 000000,20.CODE,001101:SPECIAL:32::BREAK
 589 "break"
 590 *mipsI:
 591 *mipsII:
 592 *mipsIII:
 593 *mipsIV:
 594 // start-sanitize-vr5400
 595 *vr5400:
 596 // end-sanitize-vr5400
 597 // start-sanitize-r5900
 598 *r5900:
 599 // end-sanitize-r5900
 600 *r3900:
 601 // start-sanitize-tx19
 602 *tx19:
 603 // end-sanitize-tx19
 604 {
 605   SignalException(BreakPoint, instruction_0);
 606 }
 607
 608
 609 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 610 "cop<ZZ> <COP_FUN>"
 611 *mipsI:
 612 *mipsII:
 613 *mipsIII:
 614 *mipsIV:
 615 // start-sanitize-vr5400
 616 *vr5400:
 617 // end-sanitize-vr5400
 618 // start-sanitize-r5900
 619 *r5900:
 620 // end-sanitize-r5900
 621 *r3900:
 622 // start-sanitize-tx19
 623 *tx19:
 624 // end-sanitize-tx19
 625 {
 626   DecodeCoproc (instruction_0);
 627 }
 628
 629
 630 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 631 "dadd r<RD>, r<RS>, r<RT>"
 632 *mipsIII:
 633 *mipsIV:
 634 // start-sanitize-vr5400
 635 *vr5400:
 636 // end-sanitize-vr5400
 637 // start-sanitize-r5900
 638 *r5900:
 639 // end-sanitize-r5900
 640 *r3900:
 641 // start-sanitize-tx19
 642 *tx19:
 643 // end-sanitize-tx19
 644 {
 645   ALU64_BEGIN (GPR[RS]);
 646   ALU64_ADD (GPR[RT]);
 647   ALU64_END (GPR[RT]);
 648 }
 649
 650
 651 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 652 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 653 *mipsIII:
 654 *mipsIV:
 655 // start-sanitize-vr5400
 656 *vr5400:
 657 // end-sanitize-vr5400
 658 // start-sanitize-r5900
 659 *r5900:
 660 // end-sanitize-r5900
 661 *r3900:
 662 // start-sanitize-tx19
 663 *tx19:
 664 // end-sanitize-tx19
 665 {
 666   ALU64_BEGIN (GPR[RS]);
 667   ALU64_ADD (EXTEND16 (IMMEDIATE));
 668   ALU64_END (GPR[RT]);
 669 }
 670
 671
 672 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 673 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 674 *mipsIII:
 675 *mipsIV:
 676 // start-sanitize-vr5400
 677 *vr5400:
 678 // end-sanitize-vr5400
 679 // start-sanitize-r5900
 680 *r5900:
 681 // end-sanitize-r5900
 682 *r3900:
 683 // start-sanitize-tx19
 684 *tx19:
 685 // end-sanitize-tx19
 686 {
 687   GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
 688 }
 689
 690
 691 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 692 "daddu r<RD>, r<RS>, r<RT>"
 693 *mipsIII:
 694 *mipsIV:
 695 // start-sanitize-vr5400
 696 *vr5400:
 697 // end-sanitize-vr5400
 698 // start-sanitize-r5900
 699 *r5900:
 700 // end-sanitize-r5900
 701 *r3900:
 702 // start-sanitize-tx19
 703 *tx19:
 704 // end-sanitize-tx19
 705 {
 706   GPR[RD] = GPR[RS] + GPR[RT];
 707 }
 708
 709
 710 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 711 "ddiv r<RS>, r<RT>"
 712 *mipsIII:
 713 *mipsIV:
 714 // start-sanitize-vr5400
 715 *vr5400:
 716 // end-sanitize-vr5400
 717 // start-sanitize-r5900
 718 *r5900:
 719 // end-sanitize-r5900
 720 *r3900:
 721 // start-sanitize-tx19
 722 *tx19:
 723 // end-sanitize-tx19
 724 {
 725   CHECKHILO ("Division");
 726   {
 727     signed64 n = GPR[RS];
 728     signed64 d = GPR[RT];
 729     if (d == 0)
 730       {
 731         LO = SIGNED64 (0x8000000000000000);
 732         HI = 0;
 733       }
 734     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 735       {
 736         LO = SIGNED64 (0x8000000000000000);
 737         HI = 0;
 738       }
 739     else
 740       {
 741         LO = (n / d);
 742         HI = (n % d);
 743       }
 744   }
 745 }
 746
 747
 748
 749 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 750 "ddivu r<RS>, r<RT>"
 751 *mipsIII:
 752 *mipsIV:
 753 *r3900:
 754 // start-sanitize-vr5400
 755 *vr5400:
 756 // end-sanitize-vr5400
 757 // start-sanitize-tx19
 758 *tx19:
 759 // end-sanitize-tx19
 760 {
 761   CHECKHILO ("Division");
 762   {
 763     unsigned64 n = GPR[RS];
 764     unsigned64 d = GPR[RT];
 765     if (d == 0)
 766       {
 767         LO = SIGNED64 (0x8000000000000000);
 768         HI = 0;
 769       }
 770     else
 771       {
 772         LO = (n / d);
 773         HI = (n % d);
 774       }
 775   }
 776 }
 777
 778
 779 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 780 "div r<RS>, r<RT>"
 781 *mipsI:
 782 *mipsII:
 783 *mipsIII:
 784 *mipsIV:
 785 // start-sanitize-vr5400
 786 *vr5400:
 787 // end-sanitize-vr5400
 788 // start-sanitize-r5900
 789 *r5900:
 790 // end-sanitize-r5900
 791 *r3900:
 792 // start-sanitize-tx19
 793 *tx19:
 794 // end-sanitize-tx19
 795 {
 796   CHECKHILO("Division");
 797   {
 798     signed32 n = GPR[RS];
 799     signed32 d = GPR[RT];
 800     if (d == 0)
 801       {
 802         LO = EXTEND32 (0x80000000);
 803         HI = EXTEND32 (0);
 804       }
 805     else if (d == -1 && d == 0x80000000)
 806       {
 807         LO = EXTEND32 (0x80000000);
 808         HI = EXTEND32 (0);
 809       }
 810     else
 811       {
 812         LO = EXTEND32 (n / d);
 813         HI = EXTEND32 (n % d);
 814       }
 815   }
 816 }
 817
 818
 819 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 820 "divu r<RS>, r<RT>"
 821 *mipsI:
 822 *mipsII:
 823 *mipsIII:
 824 *mipsIV:
 825 // start-sanitize-vr5400
 826 *vr5400:
 827 // end-sanitize-vr5400
 828 // start-sanitize-r5900
 829 *r5900:
 830 // end-sanitize-r5900
 831 *r3900:
 832 // start-sanitize-tx19
 833 *tx19:
 834 // end-sanitize-tx19
 835 {
 836   CHECKHILO ("Division");
 837   {
 838     unsigned32 n = GPR[RS];
 839     unsigned32 d = GPR[RT];
 840     if (d == 0)
 841       {
 842         LO = EXTEND32 (0x80000000);
 843         HI = EXTEND32 (0);
 844       }
 845    else
 846      {
 847        LO = EXTEND32 (n / d);
 848        HI = EXTEND32 (n % d);
 849      }
 850   }
 851 }
 852
 853
 854 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 855 "dmult r<RS>, r<RT>"
 856 *mipsIII:
 857 *mipsIV:
 858 // start-sanitize-vr5400
 859 *vr5400:
 860 // end-sanitize-vr5400
 861 *r3900:
 862 // start-sanitize-tx19
 863 *tx19:
 864 // end-sanitize-tx19
 865 {
 866   CHECKHILO ("Multiplication");
 867   {
 868     signed64 op1 = GPR[RS];
 869     signed64 op2 = GPR[RT];
 870     unsigned64 lo;
 871     unsigned64 hi;
 872     unsigned64 m00;
 873     unsigned64 m01;
 874     unsigned64 m10;
 875     unsigned64 m11;
 876     unsigned64 mid;
 877     int sign = 0;
 878     /* make it unsigned */
 879     if (op1 < 0)
 880       {
 881         op1 = - op1;
 882         ++sign;
 883       }
 884     if (op2 < 0)
 885       {
 886         op2 = - op2;
 887         ++sign;
 888       }
 889     /* multuply out the 4 sub products */
 890     m00 = (VL4_8 (op1) * VL4_8 (op2));
 891     m10 = (VH4_8 (op1) * VL4_8 (op2));
 892     m01 = (VL4_8 (op1) * VH4_8 (op2));
 893     m11 = (VH4_8 (op1) * VH4_8 (op2));
 894     /* add the products */
 895     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 896     lo = U8_4 (mid, m00);
 897     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 898     /* save the result */
 899     if (sign & 1)
 900       {
 901         LO = -lo;
 902         if (lo == 0)
 903           HI = -hi;
 904         else
 905           HI = -hi - 1;
 906       }
 907     else
 908       {
 909         LO = lo;
 910         HI = hi;
 911       }
 912   }
 913 }
 914
 915
 916 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
 917 "dmultu r<RS>, r<RT>"
 918 *mipsIII:
 919 *mipsIV:
 920 // start-sanitize-vr5400
 921 *vr5400:
 922 // end-sanitize-vr5400
 923 *r3900:
 924 // start-sanitize-tx19
 925 *tx19:
 926 // end-sanitize-tx19
 927 {
 928   CHECKHILO ("Multiplication");
 929   {
 930     signed64 op1 = GPR[RS];
 931     signed64 op2 = GPR[RT];
 932     unsigned64 lo;
 933     unsigned64 hi;
 934     unsigned64 m00;
 935     unsigned64 m01;
 936     unsigned64 m10;
 937     unsigned64 m11;
 938     unsigned64 mid;
 939     /* multuply out the 4 sub products */
 940     m00 = (VL4_8 (op1) * VL4_8 (op2));
 941     m10 = (VH4_8 (op1) * VL4_8 (op2));
 942     m01 = (VL4_8 (op1) * VH4_8 (op2));
 943     m11 = (VH4_8 (op1) * VH4_8 (op2));
 944     /* add the products */
 945     mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
 946     lo = U8_4 (mid, m00);
 947     hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
 948     /* save the result */
 949     LO = lo;
 950     HI = hi;
 951   }
 952 }
 953
 954
 955 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
 956 "dsll r<RD>, r<RT>, <SA>"
 957 *mipsIII:
 958 *mipsIV:
 959 // start-sanitize-vr5400
 960 *vr5400:
 961 // end-sanitize-vr5400
 962 // start-sanitize-r5900
 963 *r5900:
 964 // end-sanitize-r5900
 965 *r3900:
 966 // start-sanitize-tx19
 967 *tx19:
 968 // end-sanitize-tx19
 969 {
 970   int s = SA;
 971   GPR[RD] = GPR[RT] << s;
 972 }
 973
 974
 975 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
 976 "dsll32 r<RD>, r<RT>, <SA>"
 977 *mipsIII:
 978 *mipsIV:
 979 // start-sanitize-vr5400
 980 *vr5400:
 981 // end-sanitize-vr5400
 982 // start-sanitize-r5900
 983 *r5900:
 984 // end-sanitize-r5900
 985 *r3900:
 986 // start-sanitize-tx19
 987 *tx19:
 988 // end-sanitize-tx19
 989 {
 990   int s = 32 + SA;
 991   GPR[RD] = GPR[RT] << s;
 992 }
 993
 994
 995 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
 996 "dsllv r<RD>, r<RT>, r<RS>"
 997 *mipsIII:
 998 *mipsIV:
 999 // start-sanitize-vr5400
1000 *vr5400:
1001 // end-sanitize-vr5400
1002 // start-sanitize-r5900
1003 *r5900:
1004 // end-sanitize-r5900
1005 *r3900:
1006 // start-sanitize-tx19
1007 *tx19:
1008 // end-sanitize-tx19
1009 {
1010   int s = MASKED64 (GPR[RS], 5, 0);
1011   GPR[RD] = GPR[RT] << s;
1012 }
1013
1014
1015 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1016 "dsra r<RD>, r<RT>, <SA>"
1017 *mipsIII:
1018 *mipsIV:
1019 // start-sanitize-vr5400
1020 *vr5400:
1021 // end-sanitize-vr5400
1022 // start-sanitize-r5900
1023 *r5900:
1024 // end-sanitize-r5900
1025 *r3900:
1026 // start-sanitize-tx19
1027 *tx19:
1028 // end-sanitize-tx19
1029 {
1030   int s = SA;
1031   GPR[RD] = ((signed64) GPR[RT]) >> s;
1032 }
1033
1034
1035 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1036 "dsra32 r<RT>, r<RD>, <SA>"
1037 *mipsIII:
1038 *mipsIV:
1039 // start-sanitize-vr5400
1040 *vr5400:
1041 // end-sanitize-vr5400
1042 // start-sanitize-r5900
1043 *r5900:
1044 // end-sanitize-r5900
1045 *r3900:
1046 // start-sanitize-tx19
1047 *tx19:
1048 // end-sanitize-tx19
1049 {
1050   int s = 32 + SA;
1051   GPR[RD] = ((signed64) GPR[RT]) >> s;
1052 }
1053
1054
1055 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1056 "dsra32 r<RT>, r<RD>, r<RS>"
1057 *mipsIII:
1058 *mipsIV:
1059 // start-sanitize-vr5400
1060 *vr5400:
1061 // end-sanitize-vr5400
1062 // start-sanitize-r5900
1063 *r5900:
1064 // end-sanitize-r5900
1065 *r3900:
1066 // start-sanitize-tx19
1067 *tx19:
1068 // end-sanitize-tx19
1069 {
1070   int s = MASKED64 (GPR[RS], 5, 0);
1071   GPR[RD] = ((signed64) GPR[RT]) >> s;
1072 }
1073
1074
1075 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1076 "dsrav r<RD>, r<RT>, <SA>"
1077 *mipsIII:
1078 *mipsIV:
1079 // start-sanitize-vr5400
1080 *vr5400:
1081 // end-sanitize-vr5400
1082 // start-sanitize-r5900
1083 *r5900:
1084 // end-sanitize-r5900
1085 *r3900:
1086 // start-sanitize-tx19
1087 *tx19:
1088 // end-sanitize-tx19
1089 {
1090   int s = SA;
1091   GPR[RD] = (unsigned64) GPR[RT] >> s;
1092 }
1093
1094
1095 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1096 "dsrl32 r<RD>, r<RT>, <SA>"
1097 *mipsIII:
1098 *mipsIV:
1099 // start-sanitize-vr5400
1100 *vr5400:
1101 // end-sanitize-vr5400
1102 // start-sanitize-r5900
1103 *r5900:
1104 // end-sanitize-r5900
1105 *r3900:
1106 // start-sanitize-tx19
1107 *tx19:
1108 // end-sanitize-tx19
1109 {
1110   int s = 32 + SA;
1111   GPR[RD] = (unsigned64) GPR[RT] >> s;
1112 }
1113
1114
1115 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1116 "dsrl32 r<RD>, r<RT>, r<RS>"
1117 *mipsIII:
1118 *mipsIV:
1119 // start-sanitize-vr5400
1120 *vr5400:
1121 // end-sanitize-vr5400
1122 // start-sanitize-r5900
1123 *r5900:
1124 // end-sanitize-r5900
1125 *r3900:
1126 // start-sanitize-tx19
1127 *tx19:
1128 // end-sanitize-tx19
1129 {
1130   int s = MASKED64 (GPR[RS], 5, 0);
1131   GPR[RD] = (unsigned64) GPR[RT] >> s;
1132 }
1133
1134
1135 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1136 "dsub r<RD>, r<RS>, r<RT>"
1137 *mipsIII:
1138 *mipsIV:
1139 // start-sanitize-vr5400
1140 *vr5400:
1141 // end-sanitize-vr5400
1142 // start-sanitize-r5900
1143 *r5900:
1144 // end-sanitize-r5900
1145 *r3900:
1146 // start-sanitize-tx19
1147 *tx19:
1148 // end-sanitize-tx19
1149 {
1150   ALU64_BEGIN (GPR[RS]);
1151   ALU64_SUB (GPR[RT]);
1152   ALU64_END (GPR[RD]);
1153 }
1154
1155
1156 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1157 "dsubu r<RD>, r<RS>, r<RT>"
1158 *mipsIII:
1159 *mipsIV:
1160 // start-sanitize-vr5400
1161 *vr5400:
1162 // end-sanitize-vr5400
1163 // start-sanitize-r5900
1164 *r5900:
1165 // end-sanitize-r5900
1166 *r3900:
1167 // start-sanitize-tx19
1168 *tx19:
1169 // end-sanitize-tx19
1170 {
1171   GPR[RD] = GPR[RS] - GPR[RT];
1172 }
1173
1174
1175 000010,26.INSTR_INDEX:NORMAL:32::J
1176 "j <INSTR_INDEX>"
1177 *mipsI:
1178 *mipsII:
1179 *mipsIII:
1180 *mipsIV:
1181 // start-sanitize-vr5400
1182 *vr5400:
1183 // end-sanitize-vr5400
1184 // start-sanitize-r5900
1185 *r5900:
1186 // end-sanitize-r5900
1187 *r3900:
1188 // start-sanitize-tx19
1189 *tx19:
1190 // end-sanitize-tx19
1191 {
1192   /* NOTE: The region used is that of the delay slot NIA and NOT the
1193      current instruction */
1194   address_word region = (NIA & MASK (63, 28));
1195   DELAY_SLOT (region | (INSTR_INDEX << 2));
1196 }
1197
1198
1199 000011,26.INSTR_INDEX:NORMAL:32::JAL
1200 "jal <INSTR_INDEX>"
1201 *mipsI:
1202 *mipsII:
1203 *mipsIII:
1204 *mipsIV:
1205 // start-sanitize-vr5400
1206 *vr5400:
1207 // end-sanitize-vr5400
1208 // start-sanitize-r5900
1209 *r5900:
1210 // end-sanitize-r5900
1211 *r3900:
1212 // start-sanitize-tx19
1213 *tx19:
1214 // end-sanitize-tx19
1215 {
1216   /* NOTE: The region used is that of the delay slot and NOT the
1217      current instruction */
1218   address_word region = (NIA & MASK (63, 28));
1219   GPR[31] = CIA + 8;
1220   DELAY_SLOT (region | (INSTR_INDEX << 2));
1221 }
1222
1223
1224 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1225 "jalr r<RS>":RD == 31
1226 "jalr r<RD>, r<RS>"
1227 *mipsI:
1228 *mipsII:
1229 *mipsIII:
1230 *mipsIV:
1231 // start-sanitize-vr5400
1232 *vr5400:
1233 // end-sanitize-vr5400
1234 // start-sanitize-r5900
1235 *r5900:
1236 // end-sanitize-r5900
1237 *r3900:
1238 // start-sanitize-tx19
1239 *tx19:
1240 // end-sanitize-tx19
1241 {
1242   address_word temp = GPR[RS];
1243   GPR[RD] = CIA + 8;
1244   DELAY_SLOT (temp);
1245 }
1246
1247
1248 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1249 "jr r<RS>"
1250 *mipsI:
1251 *mipsII:
1252 *mipsIII:
1253 *mipsIV:
1254 // start-sanitize-vr5400
1255 *vr5400:
1256 // end-sanitize-vr5400
1257 // start-sanitize-r5900
1258 *r5900:
1259 // end-sanitize-r5900
1260 *r3900:
1261 // start-sanitize-tx19
1262 *tx19:
1263 // end-sanitize-tx19
1264 {
1265   DELAY_SLOT (GPR[RS]);
1266 }
1267
1268
1269 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1270 "lb r<RT>, <OFFSET>(r<BASE>)"
1271 *mipsI:
1272 *mipsII:
1273 *mipsIII:
1274 *mipsIV:
1275 // start-sanitize-vr5400
1276 *vr5400:
1277 // end-sanitize-vr5400
1278 // start-sanitize-r5900
1279 *r5900:
1280 // end-sanitize-r5900
1281 *r3900:
1282 // start-sanitize-tx19
1283 *tx19:
1284 // end-sanitize-tx19
1285 {
1286   unsigned32 instruction = instruction_0;
1287   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1288   int destreg = ((instruction >> 16) & 0x0000001F);
1289   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1290   {
1291     address_word vaddr = ((uword64)op1 + offset);
1292     address_word paddr;
1293     int uncached;
1294     {
1295       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1296         {
1297           uword64 memval = 0;
1298           uword64 memval1 = 0;
1299           uword64 mask = 0x7;
1300           unsigned int shift = 0;
1301           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1302           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1303           unsigned int byte;
1304           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1305           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1306           byte = ((vaddr & mask) ^ (bigend << shift));
1307           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1308         }
1309     }
1310   }
1311 }
1312
1313
1314 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1315 "lbu r<RT>, <OFFSET>(r<BASE>)"
1316 *mipsI:
1317 *mipsII:
1318 *mipsIII:
1319 *mipsIV:
1320 // start-sanitize-vr5400
1321 *vr5400:
1322 // end-sanitize-vr5400
1323 // start-sanitize-r5900
1324 *r5900:
1325 // end-sanitize-r5900
1326 *r3900:
1327 // start-sanitize-tx19
1328 *tx19:
1329 // end-sanitize-tx19
1330 {
1331   unsigned32 instruction = instruction_0;
1332   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1333   int destreg = ((instruction >> 16) & 0x0000001F);
1334   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1335   {
1336     address_word vaddr = ((unsigned64)op1 + offset);
1337     address_word paddr;
1338     int uncached;
1339     {
1340       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1341         {
1342           unsigned64 memval = 0;
1343           unsigned64 memval1 = 0;
1344           unsigned64 mask = 0x7;
1345           unsigned int shift = 0;
1346           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1347           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1348           unsigned int byte;
1349           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1350           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1351           byte = ((vaddr & mask) ^ (bigend << shift));
1352           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1353         }
1354     }
1355   }
1356 }
1357
1358
1359 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1360 "ld r<RT>, <OFFSET>(r<BASE>)"
1361 *mipsIII:
1362 *mipsIV:
1363 // start-sanitize-vr5400
1364 *vr5400:
1365 // end-sanitize-vr5400
1366 // start-sanitize-r5900
1367 *r5900:
1368 // end-sanitize-r5900
1369 *r3900:
1370 // start-sanitize-tx19
1371 *tx19:
1372 // end-sanitize-tx19
1373 {
1374   unsigned32 instruction = instruction_0;
1375   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1376   int destreg = ((instruction >> 16) & 0x0000001F);
1377   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1378   {
1379     address_word vaddr = ((unsigned64)op1 + offset);
1380     address_word paddr;
1381     int uncached;
1382     if ((vaddr & 7) != 0)
1383       SignalExceptionAddressLoad();
1384     else
1385       {
1386         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1387           {
1388             unsigned64 memval = 0;
1389             unsigned64 memval1 = 0;
1390             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1391             GPR[destreg] = memval;
1392           }
1393       }
1394   }
1395 }
1396
1397
1398 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1399 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1400 *mipsII:
1401 *mipsIII:
1402 *mipsIV:
1403 // start-sanitize-vr5400
1404 *vr5400:
1405 // end-sanitize-vr5400
1406 // start-sanitize-r5900
1407 *r5900:
1408 // end-sanitize-r5900
1409 *r3900:
1410 // start-sanitize-tx19
1411 *tx19:
1412 // end-sanitize-tx19
1413 {
1414   unsigned32 instruction = instruction_0;
1415   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1416   int destreg = ((instruction >> 16) & 0x0000001F);
1417   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1418   {
1419     address_word vaddr = ((unsigned64)op1 + offset);
1420     address_word paddr;
1421     int uncached;
1422     if ((vaddr & 7) != 0)
1423       SignalExceptionAddressLoad();
1424     else
1425       {
1426         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1427           {
1428             unsigned64 memval = 0;
1429             unsigned64 memval1 = 0;
1430             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1431             COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1432           }
1433       }
1434   }
1435 }
1436
1437
1438 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1439 "ldl r<RT>, <OFFSET>(r<BASE>)"
1440 *mipsIII:
1441 *mipsIV:
1442 // start-sanitize-vr5400
1443 *vr5400:
1444 // end-sanitize-vr5400
1445 // start-sanitize-r5900
1446 *r5900:
1447 // end-sanitize-r5900
1448 *r3900:
1449 // start-sanitize-tx19
1450 *tx19:
1451 // end-sanitize-tx19
1452 {
1453   unsigned32 instruction = instruction_0;
1454   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1455   int destreg = ((instruction >> 16) & 0x0000001F);
1456   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1457   {
1458     address_word vaddr = ((unsigned64)op1 + offset);
1459     address_word paddr;
1460     int uncached;
1461     {
1462       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1463         {
1464           unsigned64 memval = 0;
1465           unsigned64 memval1 = 0;
1466           unsigned64 mask = 7;
1467           unsigned int reverse = (ReverseEndian ? mask : 0);
1468           unsigned int bigend = (BigEndianCPU ? mask : 0);
1469           int byte;
1470           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1471           byte = ((vaddr & mask) ^ bigend);
1472           if (!!ByteSwapMem)
1473             paddr &= ~mask;
1474           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1475           GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1476         }
1477     }
1478   }
1479 }
1480
1481
1482 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1483 "ldr r<RT>, <OFFSET>(r<BASE>)"
1484 *mipsIII:
1485 *mipsIV:
1486 // start-sanitize-vr5400
1487 *vr5400:
1488 // end-sanitize-vr5400
1489 // start-sanitize-r5900
1490 *r5900:
1491 // end-sanitize-r5900
1492 *r3900:
1493 // start-sanitize-tx19
1494 *tx19:
1495 // end-sanitize-tx19
1496 {
1497   unsigned32 instruction = instruction_0;
1498   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1499   int destreg = ((instruction >> 16) & 0x0000001F);
1500   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1501   {
1502     address_word vaddr = ((unsigned64)op1 + offset);
1503     address_word paddr;
1504     int uncached;
1505     {
1506       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1507         {
1508           unsigned64 memval = 0;
1509           unsigned64 memval1 = 0;
1510           unsigned64 mask = 7;
1511           unsigned int reverse = (ReverseEndian ? mask : 0);
1512           unsigned int bigend = (BigEndianCPU ? mask : 0);
1513           int byte;
1514           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1515           byte = ((vaddr & mask) ^ bigend);
1516           if (!ByteSwapMem)
1517             paddr &= ~mask;
1518           LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1519           {
1520             unsigned64 srcmask;
1521             if (byte == 0)
1522               srcmask = 0;
1523             else
1524               srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1525             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1526           }
1527         }
1528     }
1529   }
1530 }
1531
1532
1533 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1534 "lh r<RT>, <OFFSET>(r<BASE>)"
1535 *mipsI:
1536 *mipsII:
1537 *mipsIII:
1538 *mipsIV:
1539 // start-sanitize-vr5400
1540 *vr5400:
1541 // end-sanitize-vr5400
1542 // start-sanitize-r5900
1543 *r5900:
1544 // end-sanitize-r5900
1545 *r3900:
1546 // start-sanitize-tx19
1547 *tx19:
1548 // end-sanitize-tx19
1549 {
1550   unsigned32 instruction = instruction_0;
1551   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1552   int destreg = ((instruction >> 16) & 0x0000001F);
1553   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1554   {
1555     address_word vaddr = ((unsigned64)op1 + offset);
1556     address_word paddr;
1557     int uncached;
1558     if ((vaddr & 1) != 0)
1559       SignalExceptionAddressLoad();
1560     else
1561       {
1562         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1563           {
1564             unsigned64 memval = 0;
1565             unsigned64 memval1 = 0;
1566             unsigned64 mask = 0x7;
1567             unsigned int shift = 1;
1568             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1569             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1570             unsigned int byte;
1571             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1572             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1573             byte = ((vaddr & mask) ^ (bigend << shift));
1574             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1575           }
1576       }
1577   }
1578 }
1579
1580
1581 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1582 "lhu r<RT>, <OFFSET>(r<BASE>)"
1583 *mipsI:
1584 *mipsII:
1585 *mipsIII:
1586 *mipsIV:
1587 // start-sanitize-vr5400
1588 *vr5400:
1589 // end-sanitize-vr5400
1590 // start-sanitize-r5900
1591 *r5900:
1592 // end-sanitize-r5900
1593 *r3900:
1594 // start-sanitize-tx19
1595 *tx19:
1596 // end-sanitize-tx19
1597 {
1598   unsigned32 instruction = instruction_0;
1599   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1600   int destreg = ((instruction >> 16) & 0x0000001F);
1601   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1602   {
1603     address_word vaddr = ((unsigned64)op1 + offset);
1604     address_word paddr;
1605     int uncached;
1606     if ((vaddr & 1) != 0)
1607       SignalExceptionAddressLoad();
1608     else
1609       {
1610         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1611           {
1612             unsigned64 memval = 0;
1613             unsigned64 memval1 = 0;
1614             unsigned64 mask = 0x7;
1615             unsigned int shift = 1;
1616             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1617             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1618             unsigned int byte;
1619             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1620             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1621             byte = ((vaddr & mask) ^ (bigend << shift));
1622             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1623           }
1624       }
1625   }
1626 }
1627
1628
1629 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1630 "ll r<RT>, <OFFSET>(r<BASE>)"
1631 *mipsII:
1632 *mipsIII:
1633 *mipsIV:
1634 // start-sanitize-vr5400
1635 *vr5400:
1636 // end-sanitize-vr5400
1637 // start-sanitize-r5900
1638 *r5900:
1639 // end-sanitize-r5900
1640 *r3900:
1641 // start-sanitize-tx19
1642 *tx19:
1643 // end-sanitize-tx19
1644 {
1645   unsigned32 instruction = instruction_0;
1646   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1647   int destreg = ((instruction >> 16) & 0x0000001F);
1648   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1649   {
1650     address_word vaddr = ((unsigned64)op1 + offset);
1651     address_word paddr;
1652     int uncached;
1653     if ((vaddr & 3) != 0)
1654       SignalExceptionAddressLoad();
1655     else
1656       {
1657         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1658           {
1659             unsigned64 memval = 0;
1660             unsigned64 memval1 = 0;
1661             unsigned64 mask = 0x7;
1662             unsigned int shift = 2;
1663             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1664             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1665             unsigned int byte;
1666             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1667             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1668             byte = ((vaddr & mask) ^ (bigend << shift));
1669             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1670             LLBIT = 1;
1671           }
1672       }
1673   }
1674 }
1675
1676
1677 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1678 "lld r<RT>, <OFFSET>(r<BASE>)"
1679 *mipsIII:
1680 *mipsIV:
1681 // start-sanitize-vr5400
1682 *vr5400:
1683 // end-sanitize-vr5400
1684 // start-sanitize-r5900
1685 *r5900:
1686 // end-sanitize-r5900
1687 *r3900:
1688 // start-sanitize-tx19
1689 *tx19:
1690 // end-sanitize-tx19
1691 {
1692   unsigned32 instruction = instruction_0;
1693   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1694   int destreg = ((instruction >> 16) & 0x0000001F);
1695   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1696   {
1697     address_word vaddr = ((unsigned64)op1 + offset);
1698     address_word paddr;
1699     int uncached;
1700     if ((vaddr & 7) != 0)
1701       SignalExceptionAddressLoad();
1702     else
1703       {
1704         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1705           {
1706             unsigned64 memval = 0;
1707             unsigned64 memval1 = 0;
1708             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1709             GPR[destreg] = memval;
1710             LLBIT = 1;
1711           }
1712       }
1713   }
1714 }
1715
1716
1717 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1718 "lui r<RT>, <IMMEDIATE>"
1719 *mipsI:
1720 *mipsII:
1721 *mipsIII:
1722 *mipsIV:
1723 // start-sanitize-vr5400
1724 *vr5400:
1725 // end-sanitize-vr5400
1726 // start-sanitize-r5900
1727 *r5900:
1728 // end-sanitize-r5900
1729 *r3900:
1730 // start-sanitize-tx19
1731 *tx19:
1732 // end-sanitize-tx19
1733 {
1734   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1735 }
1736
1737
1738 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1739 "lw r<RT>, <OFFSET>(r<BASE>)"
1740 *mipsI:
1741 *mipsII:
1742 *mipsIII:
1743 *mipsIV:
1744 // start-sanitize-vr5400
1745 *vr5400:
1746 // end-sanitize-vr5400
1747 // start-sanitize-r5900
1748 *r5900:
1749 // end-sanitize-r5900
1750 *r3900:
1751 // start-sanitize-tx19
1752 *tx19:
1753 // end-sanitize-tx19
1754 {
1755   unsigned32 instruction = instruction_0;
1756   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1757   int destreg = ((instruction >> 16) & 0x0000001F);
1758   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1759   {
1760     address_word vaddr = ((unsigned64)op1 + offset);
1761     address_word paddr;
1762     int uncached;
1763     if ((vaddr & 3) != 0)
1764       SignalExceptionAddressLoad();
1765     else
1766       {
1767         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1768           {
1769             unsigned64 memval = 0;
1770             unsigned64 memval1 = 0;
1771             unsigned64 mask = 0x7;
1772             unsigned int shift = 2;
1773             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1774             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1775             unsigned int byte;
1776             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1777             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1778             byte = ((vaddr & mask) ^ (bigend << shift));
1779             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1780           }
1781       }
1782   }
1783 }
1784
1785
1786 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1787 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1788 *mipsI:
1789 *mipsII:
1790 *mipsIII:
1791 *mipsIV:
1792 // start-sanitize-vr5400
1793 *vr5400:
1794 // end-sanitize-vr5400
1795 // start-sanitize-r5900
1796 *r5900:
1797 // end-sanitize-r5900
1798 *r3900:
1799 // start-sanitize-tx19
1800 *tx19:
1801 // end-sanitize-tx19
1802 {
1803   unsigned32 instruction = instruction_0;
1804   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1805   int destreg = ((instruction >> 16) & 0x0000001F);
1806   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1807   {
1808     address_word vaddr = ((unsigned64)op1 + offset);
1809     address_word paddr;
1810     int uncached;
1811     if ((vaddr & 3) != 0)
1812       SignalExceptionAddressLoad();
1813     else
1814       {
1815         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1816           {
1817             unsigned64 memval = 0;
1818             unsigned64 memval1 = 0;
1819             unsigned64 mask = 0x7;
1820             unsigned int shift = 2;
1821             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1822             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1823             unsigned int byte;
1824             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1825             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1826             byte = ((vaddr & mask) ^ (bigend << shift));
1827             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
1828           }
1829       }
1830   }
1831 }
1832
1833
1834 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1835 "lwl r<RT>, <OFFSET>(r<BASE>)"
1836 *mipsI:
1837 *mipsII:
1838 *mipsIII:
1839 *mipsIV:
1840 // start-sanitize-vr5400
1841 *vr5400:
1842 // end-sanitize-vr5400
1843 // start-sanitize-r5900
1844 *r5900:
1845 // end-sanitize-r5900
1846 *r3900:
1847 // start-sanitize-tx19
1848 *tx19:
1849 // end-sanitize-tx19
1850 {
1851   unsigned32 instruction = instruction_0;
1852   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1853   int destreg = ((instruction >> 16) & 0x0000001F);
1854   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1855   {
1856     address_word vaddr = ((unsigned64)op1 + offset);
1857     address_word paddr;
1858     int uncached;
1859     {
1860       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1861         {
1862           unsigned64 memval = 0;
1863           unsigned64 memval1 = 0;
1864           unsigned64 mask = 3;
1865           unsigned int reverse = (ReverseEndian ? mask : 0);
1866           unsigned int bigend = (BigEndianCPU ? mask : 0);
1867           int byte;
1868           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1869           byte = ((vaddr & mask) ^ bigend);
1870           if (!!ByteSwapMem)
1871             paddr &= ~mask;
1872           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1873           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1874             memval >>= 32;
1875           }
1876           GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
1877           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1878         }
1879     }
1880   }
1881 }
1882
1883
1884 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1885 "lwr r<RT>, <OFFSET>(r<BASE>)"
1886 *mipsI:
1887 *mipsII:
1888 *mipsIII:
1889 *mipsIV:
1890 // start-sanitize-vr5400
1891 *vr5400:
1892 // end-sanitize-vr5400
1893 // start-sanitize-r5900
1894 *r5900:
1895 // end-sanitize-r5900
1896 *r3900:
1897 // start-sanitize-tx19
1898 *tx19:
1899 // end-sanitize-tx19
1900 {
1901   unsigned32 instruction = instruction_0;
1902   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1903   int destreg = ((instruction >> 16) & 0x0000001F);
1904   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1905   {
1906     address_word vaddr = ((unsigned64)op1 + offset);
1907     address_word paddr;
1908     int uncached;
1909     {
1910       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1911         {
1912           unsigned64 memval = 0;
1913           unsigned64 memval1 = 0;
1914           unsigned64 mask = 3;
1915           unsigned int reverse = (ReverseEndian ? mask : 0);
1916           unsigned int bigend = (BigEndianCPU ? mask : 0);
1917           int byte;
1918           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1919           byte = ((vaddr & mask) ^ bigend);
1920           if (!ByteSwapMem)
1921             paddr &= ~mask;
1922           LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
1923           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
1924             memval >>= 32;
1925           }
1926           {
1927             unsigned64 srcmask;
1928             if (byte == 0)
1929               srcmask = 0;
1930             else
1931               srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
1932             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1933           }
1934           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
1935         }
1936     }
1937   }
1938 }
1939
1940
1941 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1942 "lwu r<RT>, <OFFSET>(r<BASE>)"
1943 *mipsIII:
1944 *mipsIV:
1945 // start-sanitize-vr5400
1946 *vr5400:
1947 // end-sanitize-vr5400
1948 // start-sanitize-r5900
1949 *r5900:
1950 // end-sanitize-r5900
1951 *r3900:
1952 // start-sanitize-tx19
1953 *tx19:
1954 // end-sanitize-tx19
1955 {
1956   unsigned32 instruction = instruction_0;
1957   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1958   int destreg = ((instruction >> 16) & 0x0000001F);
1959   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1960   {
1961     address_word vaddr = ((unsigned64)op1 + offset);
1962     address_word paddr;
1963     int uncached;
1964     if ((vaddr & 3) != 0)
1965       SignalExceptionAddressLoad();
1966     else
1967       {
1968         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1969           {
1970             unsigned64 memval = 0;
1971             unsigned64 memval1 = 0;
1972             unsigned64 mask = 0x7;
1973             unsigned int shift = 2;
1974             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1975             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1976             unsigned int byte;
1977             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1978             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1979             byte = ((vaddr & mask) ^ (bigend << shift));
1980             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
1981           }
1982       }
1983   }
1984 }
1985
1986
1987 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1988 "mfhi r<RD>"
1989 *mipsI:
1990 *mipsII:
1991 *mipsIII:
1992 *mipsIV:
1993 // start-sanitize-vr5400
1994 *vr5400:
1995 // end-sanitize-vr5400
1996 // start-sanitize-r5900
1997 *r5900:
1998 // end-sanitize-r5900
1999 *r3900:
2000 // start-sanitize-tx19
2001 *tx19:
2002 // end-sanitize-tx19
2003 {
2004   GPR[RD] = HI;
2005   HIACCESS = 3;
2006 }
2007
2008
2009 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2010 "mflo r<RD>"
2011 *mipsI:
2012 *mipsII:
2013 *mipsIII:
2014 *mipsIV:
2015 // start-sanitize-vr5400
2016 *vr5400:
2017 // end-sanitize-vr5400
2018 // start-sanitize-r5900
2019 *r5900:
2020 // end-sanitize-r5900
2021 *r3900:
2022 // start-sanitize-tx19
2023 *tx19:
2024 // end-sanitize-tx19
2025 {
2026   GPR[RD] = LO;
2027   LOACCESS = 3; /* 3rd instruction will be safe */
2028 }
2029
2030
2031 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2032 "movn r<RD>, r<RS>, r<RT>"
2033 *mipsIV:
2034 // start-sanitize-vr5400
2035 *vr5400:
2036 // end-sanitize-vr5400
2037 // start-sanitize-r5900
2038 *r5900:
2039 // end-sanitize-r5900
2040 {
2041   if (GPR[RT] != 0)
2042     GPR[RD] = GPR[RS];
2043 }
2044
2045
2046 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2047 "movz r<RD>, r<RS>, r<RT>"
2048 *mipsIV:
2049 // start-sanitize-vr5400
2050 *vr5400:
2051 // end-sanitize-vr5400
2052 // start-sanitize-r5900
2053 *r5900:
2054 // end-sanitize-r5900
2055 {
2056   if (GPR[RT] == 0)
2057     GPR[RD] = GPR[RS];
2058 }
2059
2060
2061 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2062 "mthi r<RS>"
2063 *mipsI:
2064 *mipsII:
2065 *mipsIII:
2066 *mipsIV:
2067 // start-sanitize-vr5400
2068 *vr5400:
2069 // end-sanitize-vr5400
2070 // start-sanitize-r5900
2071 *r5900:
2072 // end-sanitize-r5900
2073 *r3900:
2074 // start-sanitize-tx19
2075 *tx19:
2076 // end-sanitize-tx19
2077 {
2078   if (HIACCESS != 0)
2079     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2080   HI = GPR[RS];
2081   HIACCESS = 3; /* 3rd instruction will be safe */
2082 }
2083
2084
2085 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2086 "mtlo r<RS>"
2087 *mipsI:
2088 *mipsII:
2089 *mipsIII:
2090 *mipsIV:
2091 // start-sanitize-vr5400
2092 *vr5400:
2093 // end-sanitize-vr5400
2094 // start-sanitize-r5900
2095 *r5900:
2096 // end-sanitize-r5900
2097 *r3900:
2098 // start-sanitize-tx19
2099 *tx19:
2100 // end-sanitize-tx19
2101 {
2102   if (LOACCESS != 0)
2103     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2104   LO = GPR[RS];
2105   LOACCESS = 3; /* 3rd instruction will be safe */
2106 }
2107
2108
2109 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2110 "mult r<RS>, r<RT>"
2111 *mipsI:
2112 *mipsII:
2113 *mipsIII:
2114 *mipsIV:
2115 // start-sanitize-vr5400
2116 *vr5400:
2117 // end-sanitize-vr5400
2118 // start-sanitize-r5900
2119 *r5900:
2120 // end-sanitize-r5900
2121 *r3900:
2122 // start-sanitize-tx19
2123 *tx19:
2124 // end-sanitize-tx19
2125 {
2126   signed64 prod;
2127   CHECKHILO ("Multiplication");
2128   prod = (((signed64)(signed32) GPR[RS])
2129           * ((signed64)(signed32) GPR[RT]));
2130   LO = EXTEND32 (VL4_8 (prod));
2131   HI = EXTEND32 (VH4_8 (prod));
2132 }
2133
2134
2135 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2136 "multu r<RS>, r<RT>"
2137 *mipsI:
2138 *mipsII:
2139 *mipsIII:
2140 *mipsIV:
2141 // start-sanitize-vr5400
2142 *vr5400:
2143 // end-sanitize-vr5400
2144 // start-sanitize-r5900
2145 *r5900:
2146 // end-sanitize-r5900
2147 *r3900:
2148 // start-sanitize-tx19
2149 *tx19:
2150 // end-sanitize-tx19
2151 {
2152   unsigned64 prod;
2153   CHECKHILO ("Multiplication");
2154   prod = (((unsigned64)(unsigned32) GPR[RS])
2155           * ((unsigned64)(unsigned32) GPR[RT]));
2156   LO = EXTEND32 (VL4_8 (prod));
2157   HI = EXTEND32 (VH4_8 (prod));
2158 }
2159
2160
2161 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2162 "nor r<RD>, r<RS>, r<RT>"
2163 *mipsI:
2164 *mipsII:
2165 *mipsIII:
2166 *mipsIV:
2167 // start-sanitize-vr5400
2168 *vr5400:
2169 // end-sanitize-vr5400
2170 // start-sanitize-r5900
2171 *r5900:
2172 // end-sanitize-r5900
2173 *r3900:
2174 // start-sanitize-tx19
2175 *tx19:
2176 // end-sanitize-tx19
2177 {
2178   GPR[RD] = ~ (GPR[RS] | GPR[RT]);
2179 }
2180
2181
2182 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2183 "or r<RD>, r<RS>, r<RT>"
2184 *mipsI:
2185 *mipsII:
2186 *mipsIII:
2187 *mipsIV:
2188 // start-sanitize-vr5400
2189 *vr5400:
2190 // end-sanitize-vr5400
2191 // start-sanitize-r5900
2192 *r5900:
2193 // end-sanitize-r5900
2194 *r3900:
2195 // start-sanitize-tx19
2196 *tx19:
2197 // end-sanitize-tx19
2198 {
2199   GPR[RD] = (GPR[RS] | GPR[RT]);
2200 }
2201
2202
2203 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2204 "ori r<RT>, r<RS>, <IMMEDIATE>"
2205 *mipsI:
2206 *mipsII:
2207 *mipsIII:
2208 *mipsIV:
2209 // start-sanitize-vr5400
2210 *vr5400:
2211 // end-sanitize-vr5400
2212 // start-sanitize-r5900
2213 *r5900:
2214 // end-sanitize-r5900
2215 *r3900:
2216 // start-sanitize-tx19
2217 *tx19:
2218 // end-sanitize-tx19
2219 {
2220   GPR[RT] = (GPR[RS] | IMMEDIATE);
2221 }
2222
2223
2224 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2225 *mipsIV:
2226 // start-sanitize-vr5400
2227 *vr5400:
2228 // end-sanitize-vr5400
2229 // start-sanitize-r5900
2230 *r5900:
2231 // end-sanitize-r5900
2232 {
2233   unsigned32 instruction = instruction_0;
2234   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2235   int hint = ((instruction >> 16) & 0x0000001F);
2236   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2237   {
2238     address_word vaddr = ((unsigned64)op1 + offset);
2239     address_word paddr;
2240     int uncached;
2241     {
2242       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2243         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2244     }
2245   }
2246 }
2247
2248 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2249 "sb r<RT>, <OFFSET>(r<BASE>)"
2250 *mipsI:
2251 *mipsII:
2252 *mipsIII:
2253 *mipsIV:
2254 // start-sanitize-vr5400
2255 *vr5400:
2256 // end-sanitize-vr5400
2257 // start-sanitize-r5900
2258 *r5900:
2259 // end-sanitize-r5900
2260 *r3900:
2261 // start-sanitize-tx19
2262 *tx19:
2263 // end-sanitize-tx19
2264 {
2265   unsigned32 instruction = instruction_0;
2266   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2267   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2268   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2269   {
2270     address_word vaddr = ((unsigned64)op1 + offset);
2271     address_word paddr;
2272     int uncached;
2273     {
2274       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2275         {
2276           unsigned64 memval = 0;
2277           unsigned64 memval1 = 0;
2278           unsigned64 mask = 0x7;
2279           unsigned int shift = 0;
2280           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2281           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2282           unsigned int byte;
2283           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2284           byte = ((vaddr & mask) ^ (bigend << shift));
2285           memval = ((unsigned64) op2 << (8 * byte));
2286           {
2287             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2288           }
2289         }
2290     }
2291   }
2292 }
2293
2294
2295 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2296 "sc r<RT>, <OFFSET>(r<BASE>)"
2297 *mipsII:
2298 *mipsIII:
2299 *mipsIV:
2300 // start-sanitize-vr5400
2301 *vr5400:
2302 // end-sanitize-vr5400
2303 // start-sanitize-r5900
2304 *r5900:
2305 // end-sanitize-r5900
2306 *r3900:
2307 // start-sanitize-tx19
2308 *tx19:
2309 // end-sanitize-tx19
2310 {
2311   unsigned32 instruction = instruction_0;
2312   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2313   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2314   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2315   {
2316     address_word vaddr = ((unsigned64)op1 + offset);
2317     address_word paddr;
2318     int uncached;
2319     if ((vaddr & 3) != 0)
2320       SignalExceptionAddressStore();
2321     else
2322       {
2323         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2324           {
2325             unsigned64 memval = 0;
2326             unsigned64 memval1 = 0;
2327             unsigned64 mask = 0x7;
2328             unsigned int byte;
2329             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2330             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2331             memval = ((unsigned64) op2 << (8 * byte));
2332             if (LLBIT)
2333               {
2334                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2335               }
2336             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2337           }
2338       }
2339   }
2340 }
2341
2342
2343 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2344 "scd r<RT>, <OFFSET>(r<BASE>)"
2345 *mipsIII:
2346 *mipsIV:
2347 // start-sanitize-vr5400
2348 *vr5400:
2349 // end-sanitize-vr5400
2350 // start-sanitize-r5900
2351 *r5900:
2352 // end-sanitize-r5900
2353 *r3900:
2354 // start-sanitize-tx19
2355 *tx19:
2356 // end-sanitize-tx19
2357 {
2358   unsigned32 instruction = instruction_0;
2359   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2360   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2361   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2362   {
2363     address_word vaddr = ((unsigned64)op1 + offset);
2364     address_word paddr;
2365     int uncached;
2366     if ((vaddr & 7) != 0)
2367       SignalExceptionAddressStore();
2368     else
2369       {
2370         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2371           {
2372             unsigned64 memval = 0;
2373             unsigned64 memval1 = 0;
2374             memval = op2;
2375             if (LLBIT)
2376               {
2377                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2378               }
2379             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2380           }
2381       }
2382   }
2383 }
2384
2385
2386 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2387 "sd r<RT>, <OFFSET>(r<BASE>)"
2388 *mipsIII:
2389 *mipsIV:
2390 // start-sanitize-vr5400
2391 *vr5400:
2392 // end-sanitize-vr5400
2393 // start-sanitize-r5900
2394 *r5900:
2395 // end-sanitize-r5900
2396 *r3900:
2397 // start-sanitize-tx19
2398 *tx19:
2399 // end-sanitize-tx19
2400 {
2401   unsigned32 instruction = instruction_0;
2402   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2403   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2404   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2405   {
2406     address_word vaddr = ((unsigned64)op1 + offset);
2407     address_word paddr;
2408     int uncached;
2409     if ((vaddr & 7) != 0)
2410       SignalExceptionAddressStore();
2411     else
2412       {
2413         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2414           {
2415             unsigned64 memval = 0;
2416             unsigned64 memval1 = 0;
2417             memval = op2;
2418             {
2419               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2420             }
2421           }
2422       }
2423   }
2424 }
2425
2426
2427 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2428 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2429 *mipsII:
2430 *mipsIII:
2431 *mipsIV:
2432 // start-sanitize-vr5400
2433 *vr5400:
2434 // end-sanitize-vr5400
2435 // start-sanitize-r5900
2436 *r5900:
2437 // end-sanitize-r5900
2438 *r3900:
2439 // start-sanitize-tx19
2440 *tx19:
2441 // end-sanitize-tx19
2442 {
2443   unsigned32 instruction = instruction_0;
2444   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2445   int destreg = ((instruction >> 16) & 0x0000001F);
2446   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2447   {
2448     address_word vaddr = ((unsigned64)op1 + offset);
2449     address_word paddr;
2450     int uncached;
2451     if ((vaddr & 7) != 0)
2452       SignalExceptionAddressStore();
2453     else
2454       {
2455         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2456           {
2457             unsigned64 memval = 0;
2458             unsigned64 memval1 = 0;
2459             memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2460             {
2461               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2462             }
2463           }
2464       }
2465   }
2466 }
2467
2468
2469 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2470 "sdl r<RT>, <OFFSET>(r<BASE>)"
2471 *mipsIII:
2472 *mipsIV:
2473 // start-sanitize-vr5400
2474 *vr5400:
2475 // end-sanitize-vr5400
2476 // start-sanitize-r5900
2477 *r5900:
2478 // end-sanitize-r5900
2479 *r3900:
2480 // start-sanitize-tx19
2481 *tx19:
2482 // end-sanitize-tx19
2483 {
2484   unsigned32 instruction = instruction_0;
2485   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2486   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2487   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2488   {
2489     address_word vaddr = ((unsigned64)op1 + offset);
2490     address_word paddr;
2491     int uncached;
2492     {
2493       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2494         {
2495           unsigned64 memval = 0;
2496           unsigned64 memval1 = 0;
2497           unsigned64 mask = 7;
2498           unsigned int reverse = (ReverseEndian ? mask : 0);
2499           unsigned int bigend = (BigEndianCPU ? mask : 0);
2500           int byte;
2501           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2502           byte = ((vaddr & mask) ^ bigend);
2503           if (!!ByteSwapMem)
2504             paddr &= ~mask;
2505           memval = (op2 >> (8 * (7 - byte)));
2506           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2507         }
2508     }
2509   }
2510 }
2511
2512
2513 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2514 "sdr r<RT>, <OFFSET>(r<BASE>)"
2515 *mipsIII:
2516 *mipsIV:
2517 // start-sanitize-vr5400
2518 *vr5400:
2519 // end-sanitize-vr5400
2520 // start-sanitize-r5900
2521 *r5900:
2522 // end-sanitize-r5900
2523 *r3900:
2524 // start-sanitize-tx19
2525 *tx19:
2526 // end-sanitize-tx19
2527 {
2528   unsigned32 instruction = instruction_0;
2529   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2530   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2531   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2532   {
2533     address_word vaddr = ((unsigned64)op1 + offset);
2534     address_word paddr;
2535     int uncached;
2536     {
2537       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2538         {
2539           unsigned64 memval = 0;
2540           unsigned64 memval1 = 0;
2541           unsigned64 mask = 7;
2542           unsigned int reverse = (ReverseEndian ? mask : 0);
2543           unsigned int bigend = (BigEndianCPU ? mask : 0);
2544           int byte;
2545           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2546           byte = ((vaddr & mask) ^ bigend);
2547           if (!ByteSwapMem)
2548             paddr &= ~mask;
2549           memval = ((unsigned64) op2 << (byte * 8));
2550           StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
2551         }
2552     }
2553   }
2554 }
2555
2556
2557 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2558 "sh r<RT>, <OFFSET>(r<BASE>)"
2559 *mipsI:
2560 *mipsII:
2561 *mipsIII:
2562 *mipsIV:
2563 // start-sanitize-vr5400
2564 *vr5400:
2565 // end-sanitize-vr5400
2566 // start-sanitize-r5900
2567 *r5900:
2568 // end-sanitize-r5900
2569 *r3900:
2570 // start-sanitize-tx19
2571 *tx19:
2572 // end-sanitize-tx19
2573 {
2574   unsigned32 instruction = instruction_0;
2575   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2576   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2577   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2578   {
2579     address_word vaddr = ((unsigned64)op1 + offset);
2580     address_word paddr;
2581     int uncached;
2582     if ((vaddr & 1) != 0)
2583       SignalExceptionAddressStore();
2584     else
2585       {
2586         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2587           {
2588             unsigned64 memval = 0;
2589             unsigned64 memval1 = 0;
2590             unsigned64 mask = 0x7;
2591             unsigned int shift = 1;
2592             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2593             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2594             unsigned int byte;
2595             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2596             byte = ((vaddr & mask) ^ (bigend << shift));
2597             memval = ((unsigned64) op2 << (8 * byte));
2598             {
2599               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2600             }
2601           }
2602       }
2603   }
2604 }
2605
2606
2607 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2608 "sll r<RD>, r<RT>, <SHIFT>"
2609 *mipsI:
2610 *mipsII:
2611 *mipsIII:
2612 *mipsIV:
2613 // start-sanitize-vr5400
2614 *vr5400:
2615 // end-sanitize-vr5400
2616 // start-sanitize-r5900
2617 *r5900:
2618 // end-sanitize-r5900
2619 *r3900:
2620 // start-sanitize-tx19
2621 *tx19:
2622 // end-sanitize-tx19
2623 {
2624   int s = SHIFT;
2625   unsigned32 temp = (GPR[RT] << s);
2626   GPR[RD] = EXTEND32 (temp);
2627 }
2628
2629
2630 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2631 "sllv r<RD>, r<RT>, r<RS>"
2632 *mipsI:
2633 *mipsII:
2634 *mipsIII:
2635 *mipsIV:
2636 // start-sanitize-vr5400
2637 *vr5400:
2638 // end-sanitize-vr5400
2639 // start-sanitize-r5900
2640 *r5900:
2641 // end-sanitize-r5900
2642 *r3900:
2643 // start-sanitize-tx19
2644 *tx19:
2645 // end-sanitize-tx19
2646 {
2647   int s = MASKED (GPR[RS], 4, 0);
2648   unsigned32 temp = (GPR[RT] << s);
2649   GPR[RD] = EXTEND32 (temp);
2650 }
2651
2652
2653 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2654 "slt r<RD>, r<RS>, r<RT>"
2655 *mipsI:
2656 *mipsII:
2657 *mipsIII:
2658 *mipsIV:
2659 // start-sanitize-vr5400
2660 *vr5400:
2661 // end-sanitize-vr5400
2662 // start-sanitize-r5900
2663 *r5900:
2664 // end-sanitize-r5900
2665 *r3900:
2666 // start-sanitize-tx19
2667 *tx19:
2668 // end-sanitize-tx19
2669 {
2670   GPR[RD] = (GPR[RS] < GPR[RT]);
2671 }
2672
2673
2674 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2675 "slti r<RT>, r<RS>, <IMMEDIATE>"
2676 *mipsI:
2677 *mipsII:
2678 *mipsIII:
2679 *mipsIV:
2680 // start-sanitize-vr5400
2681 *vr5400:
2682 // end-sanitize-vr5400
2683 // start-sanitize-r5900
2684 *r5900:
2685 // end-sanitize-r5900
2686 *r3900:
2687 // start-sanitize-tx19
2688 *tx19:
2689 // end-sanitize-tx19
2690 {
2691   GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE));
2692 }
2693
2694
2695 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2696 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2697 *mipsI:
2698 *mipsII:
2699 *mipsIII:
2700 *mipsIV:
2701 // start-sanitize-vr5400
2702 *vr5400:
2703 // end-sanitize-vr5400
2704 // start-sanitize-r5900
2705 *r5900:
2706 // end-sanitize-r5900
2707 *r3900:
2708 // start-sanitize-tx19
2709 *tx19:
2710 // end-sanitize-tx19
2711 {
2712   GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
2713 }
2714
2715 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2716 "sltu r<RD>, r<RS>, r<RT>"
2717 *mipsI:
2718 *mipsII:
2719 *mipsIII:
2720 *mipsIV:
2721 // start-sanitize-vr5400
2722 *vr5400:
2723 // end-sanitize-vr5400
2724 // start-sanitize-r5900
2725 *r5900:
2726 // end-sanitize-r5900
2727 *r3900:
2728 // start-sanitize-tx19
2729 *tx19:
2730 // end-sanitize-tx19
2731 {
2732   GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
2733 }
2734
2735
2736 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2737 "sra r<RD>, r<RT>, <SHIFT>"
2738 *mipsI:
2739 *mipsII:
2740 *mipsIII:
2741 *mipsIV:
2742 // start-sanitize-vr5400
2743 *vr5400:
2744 // end-sanitize-vr5400
2745 // start-sanitize-r5900
2746 *r5900:
2747 // end-sanitize-r5900
2748 *r3900:
2749 // start-sanitize-tx19
2750 *tx19:
2751 // end-sanitize-tx19
2752 {
2753   int s = SHIFT;
2754   signed32 temp = (signed32) GPR[RT] >> s;
2755   GPR[RD] = EXTEND32 (temp);
2756 }
2757
2758
2759 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2760 "srav r<RD>, r<RT>, r<RS>"
2761 *mipsI:
2762 *mipsII:
2763 *mipsIII:
2764 *mipsIV:
2765 // start-sanitize-vr5400
2766 *vr5400:
2767 // end-sanitize-vr5400
2768 // start-sanitize-r5900
2769 *r5900:
2770 // end-sanitize-r5900
2771 *r3900:
2772 // start-sanitize-tx19
2773 *tx19:
2774 // end-sanitize-tx19
2775 {
2776   int s = MASKED (GPR[RS], 4, 0);
2777   signed32 temp = (signed32) GPR[RT] >> s;
2778   GPR[RD] = EXTEND32 (temp);
2779 }
2780
2781
2782 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2783 "srl r<RD>, r<RT>, <SHIFT>"
2784 *mipsI:
2785 *mipsII:
2786 *mipsIII:
2787 *mipsIV:
2788 // start-sanitize-vr5400
2789 *vr5400:
2790 // end-sanitize-vr5400
2791 // start-sanitize-r5900
2792 *r5900:
2793 // end-sanitize-r5900
2794 *r3900:
2795 // start-sanitize-tx19
2796 *tx19:
2797 // end-sanitize-tx19
2798 {
2799   int s = SHIFT;
2800   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2801   GPR[RD] = EXTEND32 (temp);
2802 }
2803
2804
2805 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2806 "srlv r<RD>, r<RT>, r<RS>"
2807 *mipsI:
2808 *mipsII:
2809 *mipsIII:
2810 *mipsIV:
2811 // start-sanitize-vr5400
2812 *vr5400:
2813 // end-sanitize-vr5400
2814 // start-sanitize-r5900
2815 *r5900:
2816 // end-sanitize-r5900
2817 *r3900:
2818 // start-sanitize-tx19
2819 *tx19:
2820 // end-sanitize-tx19
2821 {
2822   int s = MASKED (GPR[RS], 4, 0);
2823   unsigned32 temp = (unsigned32) GPR[RT] >> s;
2824   GPR[RD] = EXTEND32 (temp);
2825 }
2826
2827
2828 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2829 "sub r<RD>, r<RS>, r<RT>"
2830 *mipsI:
2831 *mipsII:
2832 *mipsIII:
2833 *mipsIV:
2834 // start-sanitize-vr5400
2835 *vr5400:
2836 // end-sanitize-vr5400
2837 // start-sanitize-r5900
2838 *r5900:
2839 // end-sanitize-r5900
2840 *r3900:
2841 // start-sanitize-tx19
2842 *tx19:
2843 // end-sanitize-tx19
2844 {
2845   ALU32_BEGIN (GPR[RS]);
2846   ALU32_SUB (GPR[RT]);
2847   ALU32_END (GPR[RD]);
2848 }
2849
2850
2851 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2852 "subu r<RD>, r<RS>, r<RT>"
2853 *mipsI:
2854 *mipsII:
2855 *mipsIII:
2856 *mipsIV:
2857 // start-sanitize-vr5400
2858 *vr5400:
2859 // end-sanitize-vr5400
2860 // start-sanitize-r5900
2861 *r5900:
2862 // end-sanitize-r5900
2863 *r3900:
2864 // start-sanitize-tx19
2865 *tx19:
2866 // end-sanitize-tx19
2867 {
2868   GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
2869 }
2870
2871
2872 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2873 "sw r<RT>, <OFFSET>(r<BASE>)"
2874 *mipsI:
2875 *mipsII:
2876 *mipsIII:
2877 *mipsIV:
2878 // start-sanitize-vr5400
2879 *vr5400:
2880 // end-sanitize-vr5400
2881 // start-sanitize-r5900
2882 *r5900:
2883 // end-sanitize-r5900
2884 *r3900:
2885 // start-sanitize-tx19
2886 *tx19:
2887 // end-sanitize-tx19
2888 {
2889   unsigned32 instruction = instruction_0;
2890   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2891   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2892   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2893   {
2894     address_word vaddr = ((unsigned64)op1 + offset);
2895     address_word paddr;
2896     int uncached;
2897     if ((vaddr & 3) != 0)
2898       SignalExceptionAddressStore();
2899     else
2900       {
2901         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2902           {
2903             unsigned64 memval = 0;
2904             unsigned64 memval1 = 0;
2905             unsigned64 mask = 0x7;
2906             unsigned int byte;
2907             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2908             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2909             memval = ((unsigned64) op2 << (8 * byte));
2910             {
2911               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2912             }
2913           }
2914       }
2915   }
2916 }
2917
2918
2919 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2920 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2921 *mipsI:
2922 *mipsII:
2923 *mipsIII:
2924 *mipsIV:
2925 // start-sanitize-vr5400
2926 *vr5400:
2927 // end-sanitize-vr5400
2928 // start-sanitize-r5900
2929 *r5900:
2930 // end-sanitize-r5900
2931 *r3900:
2932 // start-sanitize-tx19
2933 *tx19:
2934 // end-sanitize-tx19
2935 {
2936   unsigned32 instruction = instruction_0;
2937   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2938   int destreg = ((instruction >> 16) & 0x0000001F);
2939   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2940   {
2941     address_word vaddr = ((unsigned64)op1 + offset);
2942     address_word paddr;
2943     int uncached;
2944     if ((vaddr & 3) != 0)
2945       SignalExceptionAddressStore();
2946     else
2947       {
2948         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2949           {
2950             unsigned64 memval = 0;
2951             unsigned64 memval1 = 0;
2952             unsigned64 mask = 0x7;
2953             unsigned int byte;
2954             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2955             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2956             memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
2957             {
2958               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2959             }
2960           }
2961       }
2962   }
2963 }
2964
2965
2966 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2967 "swl r<RT>, <OFFSET>(r<BASE>)"
2968 *mipsI:
2969 *mipsII:
2970 *mipsIII:
2971 *mipsIV:
2972 // start-sanitize-vr5400
2973 *vr5400:
2974 // end-sanitize-vr5400
2975 // start-sanitize-r5900
2976 *r5900:
2977 // end-sanitize-r5900
2978 *r3900:
2979 // start-sanitize-tx19
2980 *tx19:
2981 // end-sanitize-tx19
2982 {
2983   unsigned32 instruction = instruction_0;
2984   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2985   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2986   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2987   {
2988     address_word vaddr = ((unsigned64)op1 + offset);
2989     address_word paddr;
2990     int uncached;
2991     {
2992       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2993         {
2994           unsigned64 memval = 0;
2995           unsigned64 memval1 = 0;
2996           unsigned64 mask = 3;
2997           unsigned int reverse = (ReverseEndian ? mask : 0);
2998           unsigned int bigend = (BigEndianCPU ? mask : 0);
2999           int byte;
3000           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3001           byte = ((vaddr & mask) ^ bigend);
3002           if (!!ByteSwapMem)
3003             paddr &= ~mask;
3004           memval = (op2 >> (8 * (3 - byte)));
3005           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3006             memval <<= 32;
3007           }
3008           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
3009         }
3010     }
3011   }
3012 }
3013
3014
3015 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3016 "swr r<RT>, <OFFSET>(r<BASE>)"
3017 *mipsI:
3018 *mipsII:
3019 *mipsIII:
3020 *mipsIV:
3021 // start-sanitize-vr5400
3022 *vr5400:
3023 // end-sanitize-vr5400
3024 // start-sanitize-r5900
3025 *r5900:
3026 // end-sanitize-r5900
3027 *r3900:
3028 // start-sanitize-tx19
3029 *tx19:
3030 // end-sanitize-tx19
3031 {
3032   unsigned32 instruction = instruction_0;
3033   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3034   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3035   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3036   {
3037     address_word vaddr = ((unsigned64)op1 + offset);
3038     address_word paddr;
3039     int uncached;
3040     {
3041       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3042         {
3043           unsigned64 memval = 0;
3044           unsigned64 memval1 = 0;
3045           unsigned64 mask = 3;
3046           unsigned int reverse = (ReverseEndian ? mask : 0);
3047           unsigned int bigend = (BigEndianCPU ? mask : 0);
3048           int byte;
3049           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3050           byte = ((vaddr & mask) ^ bigend);
3051           if (!ByteSwapMem)
3052             paddr &= ~mask;
3053           memval = ((unsigned64) op2 << (byte * 8));
3054           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3055             memval <<= 32;
3056           }
3057           StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
3058         }
3059     }
3060   }
3061 }
3062
3063
3064 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3065 "sync":STYPE == 0
3066 "sync <STYPE>"
3067 *mipsII:
3068 *mipsIII:
3069 *mipsIV:
3070 // start-sanitize-vr5400
3071 *vr5400:
3072 // end-sanitize-vr5400
3073 // start-sanitize-r5900
3074 *r5900:
3075 // end-sanitize-r5900
3076 *r3900:
3077 // start-sanitize-tx19
3078 *tx19:
3079 // end-sanitize-tx19
3080 {
3081   SyncOperation (STYPE);
3082 }
3083
3084
3085 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3086 "syscall <CODE>"
3087 *mipsI:
3088 *mipsII:
3089 *mipsIII:
3090 *mipsIV:
3091 // start-sanitize-vr5400
3092 *vr5400:
3093 // end-sanitize-vr5400
3094 // start-sanitize-r5900
3095 *r5900:
3096 // end-sanitize-r5900
3097 *r3900:
3098 // start-sanitize-tx19
3099 *tx19:
3100 // end-sanitize-tx19
3101 {
3102   SignalException(SystemCall, instruction_0);
3103 }
3104
3105
3106 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3107 "teq r<RS>, r<RT>"
3108 *mipsII:
3109 *mipsIII:
3110 *mipsIV:
3111 // start-sanitize-vr5400
3112 *vr5400:
3113 // end-sanitize-vr5400
3114 // start-sanitize-r5900
3115 *r5900:
3116 // end-sanitize-r5900
3117 *r3900:
3118 // start-sanitize-tx19
3119 *tx19:
3120 // end-sanitize-tx19
3121 {
3122   if (GPR[RS] == GPR[RT])
3123     SignalException(Trap, instruction_0);
3124 }
3125
3126
3127 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3128 "teqi r<RS>, <IMMEDIATE>"
3129 *mipsII:
3130 *mipsIII:
3131 *mipsIV:
3132 // start-sanitize-vr5400
3133 *vr5400:
3134 // end-sanitize-vr5400
3135 // start-sanitize-r5900
3136 *r5900:
3137 // end-sanitize-r5900
3138 *r3900:
3139 // start-sanitize-tx19
3140 *tx19:
3141 // end-sanitize-tx19
3142 {
3143   if (GPR[RS] == EXTEND16 (IMMEDIATE))
3144     SignalException(Trap, instruction_0);
3145 }
3146
3147
3148 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3149 "tge r<RS>, r<RT>"
3150 *mipsII:
3151 *mipsIII:
3152 *mipsIV:
3153 // start-sanitize-vr5400
3154 *vr5400:
3155 // end-sanitize-vr5400
3156 // start-sanitize-r5900
3157 *r5900:
3158 // end-sanitize-r5900
3159 *r3900:
3160 // start-sanitize-tx19
3161 *tx19:
3162 // end-sanitize-tx19
3163 {
3164   if (GPR[RS] >= GPR[RT])
3165     SignalException(Trap, instruction_0);
3166 }
3167
3168
3169 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3170 "tgei r<RS>, <IMMEDIATE>"
3171 *mipsII:
3172 *mipsIII:
3173 *mipsIV:
3174 // start-sanitize-vr5400
3175 *vr5400:
3176 // end-sanitize-vr5400
3177 // start-sanitize-r5900
3178 *r5900:
3179 // end-sanitize-r5900
3180 *r3900:
3181 // start-sanitize-tx19
3182 *tx19:
3183 // end-sanitize-tx19
3184 {
3185   if (GPR[RS] >= EXTEND16 (IMMEDIATE))
3186     SignalException(Trap, instruction_0);
3187 }
3188
3189
3190 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3191 "tgeiu r<RS>, <IMMEDIATE>"
3192 *mipsII:
3193 *mipsIII:
3194 *mipsIV:
3195 // start-sanitize-vr5400
3196 *vr5400:
3197 // end-sanitize-vr5400
3198 // start-sanitize-r5900
3199 *r5900:
3200 // end-sanitize-r5900
3201 *r3900:
3202 // start-sanitize-tx19
3203 *tx19:
3204 // end-sanitize-tx19
3205 {
3206   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3207     SignalException(Trap, instruction_0);
3208 }
3209
3210
3211 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3212 "tgeu r<RS>, r<RT>"
3213 *mipsII:
3214 *mipsIII:
3215 *mipsIV:
3216 // start-sanitize-vr5400
3217 *vr5400:
3218 // end-sanitize-vr5400
3219 // start-sanitize-r5900
3220 *r5900:
3221 // end-sanitize-r5900
3222 *r3900:
3223 // start-sanitize-tx19
3224 *tx19:
3225 // end-sanitize-tx19
3226 {
3227   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3228     SignalException(Trap, instruction_0);
3229 }
3230
3231
3232 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3233 "tlt r<RS>, r<RT>"
3234 *mipsII:
3235 *mipsIII:
3236 *mipsIV:
3237 // start-sanitize-vr5400
3238 *vr5400:
3239 // end-sanitize-vr5400
3240 // start-sanitize-r5900
3241 *r5900:
3242 // end-sanitize-r5900
3243 *r3900:
3244 // start-sanitize-tx19
3245 *tx19:
3246 // end-sanitize-tx19
3247 {
3248   if (GPR[RS] < GPR[RT])
3249     SignalException(Trap, instruction_0);
3250 }
3251
3252
3253 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3254 "tlti r<RS>, <IMMEDIATE>"
3255 *mipsII:
3256 *mipsIII:
3257 *mipsIV:
3258 // start-sanitize-vr5400
3259 *vr5400:
3260 // end-sanitize-vr5400
3261 // start-sanitize-r5900
3262 *r5900:
3263 // end-sanitize-r5900
3264 *r3900:
3265 // start-sanitize-tx19
3266 *tx19:
3267 // end-sanitize-tx19
3268 {
3269   if (GPR[RS] < EXTEND16 (IMMEDIATE))
3270     SignalException(Trap, instruction_0);
3271 }
3272
3273
3274 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3275 "tltiu r<RS>, <IMMEDIATE>"
3276 *mipsII:
3277 *mipsIII:
3278 *mipsIV:
3279 // start-sanitize-vr5400
3280 *vr5400:
3281 // end-sanitize-vr5400
3282 // start-sanitize-r5900
3283 *r5900:
3284 // end-sanitize-r5900
3285 *r3900:
3286 // start-sanitize-tx19
3287 *tx19:
3288 // end-sanitize-tx19
3289 {
3290   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3291     SignalException(Trap, instruction_0);
3292 }
3293
3294
3295 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3296 "tltu r<RS>, r<RT>"
3297 *mipsII:
3298 *mipsIII:
3299 *mipsIV:
3300 // start-sanitize-vr5400
3301 *vr5400:
3302 // end-sanitize-vr5400
3303 // start-sanitize-r5900
3304 *r5900:
3305 // end-sanitize-r5900
3306 *r3900:
3307 // start-sanitize-tx19
3308 *tx19:
3309 // end-sanitize-tx19
3310 {
3311   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3312     SignalException(Trap, instruction_0);
3313 }
3314
3315
3316 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3317 "tne r<RS>, r<RT>"
3318 *mipsII:
3319 *mipsIII:
3320 *mipsIV:
3321 // start-sanitize-vr5400
3322 *vr5400:
3323 // end-sanitize-vr5400
3324 // start-sanitize-r5900
3325 *r5900:
3326 // end-sanitize-r5900
3327 *r3900:
3328 // start-sanitize-tx19
3329 *tx19:
3330 // end-sanitize-tx19
3331 {
3332   if (GPR[RS] != GPR[RT])
3333     SignalException(Trap, instruction_0);
3334 }
3335
3336
3337 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3338 "tne r<RS>, <IMMEDIATE>"
3339 *mipsII:
3340 *mipsIII:
3341 *mipsIV:
3342 // start-sanitize-vr5400
3343 *vr5400:
3344 // end-sanitize-vr5400
3345 // start-sanitize-r5900
3346 *r5900:
3347 // end-sanitize-r5900
3348 *r3900:
3349 // start-sanitize-tx19
3350 *tx19:
3351 // end-sanitize-tx19
3352 {
3353   if (GPR[RS] != EXTEND16 (IMMEDIATE))
3354     SignalException(Trap, instruction_0);
3355 }
3356
3357
3358 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3359 "xor r<RD>, r<RS>, r<RT>"
3360 *mipsI:
3361 *mipsII:
3362 *mipsIII:
3363 *mipsIV:
3364 // start-sanitize-vr5400
3365 *vr5400:
3366 // end-sanitize-vr5400
3367 // start-sanitize-r5900
3368 *r5900:
3369 // end-sanitize-r5900
3370 *r3900:
3371 // start-sanitize-tx19
3372 *tx19:
3373 // end-sanitize-tx19
3374 {
3375   GPR[RD] = GPR[RS] ^ GPR[RT];
3376 }
3377
3378
3379 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3380 "xori r<RT>, r<RS>, <IMMEDIATE>"
3381 *mipsI:
3382 *mipsII:
3383 *mipsIII:
3384 *mipsIV:
3385 // start-sanitize-vr5400
3386 *vr5400:
3387 // end-sanitize-vr5400
3388 // start-sanitize-r5900
3389 *r5900:
3390 // end-sanitize-r5900
3391 *r3900:
3392 // start-sanitize-tx19
3393 *tx19:
3394 // end-sanitize-tx19
3395 {
3396   GPR[RT] = GPR[RS] ^ IMMEDIATE;
3397 }
3398
3399 \f
3400 //
3401 // MIPS Architecture:
3402 //
3403 //        FPU Instruction Set (COP1 & COP1X)
3404 //
3405
3406
3407 :%s::::FMT:int fmt
3408 {
3409   switch (fmt)
3410     {
3411     case fmt_single: return "s";
3412     case fmt_double: return "d";
3413     case fmt_word: return "w";
3414     case fmt_long: return "l";
3415     default: return "?";
3416     }
3417 }
3418
3419 :%s::::TF:int tf
3420 {
3421   if (tf)
3422     return "t";
3423   else
3424     return "f";
3425 }
3426
3427 :%s::::ND:int nd
3428 {
3429   if (nd)
3430     return "l";
3431   else
3432     return "";
3433 }
3434
3435 :%s::::COND:int cond
3436 {
3437   switch (cond)
3438     {
3439     case 00: return "f";
3440     case 01: return "un";
3441     case 02: return "eq";
3442     case 03: return "ueq";
3443     case 04: return "olt";
3444     case 05: return "ult";
3445     case 06: return "ole";
3446     case 07: return "ule";
3447     case 010: return "sf";
3448     case 011: return "ngle";
3449     case 012: return "seq";
3450     case 013: return "ngl";
3451     case 014: return "lt";
3452     case 015: return "nge";
3453     case 016: return "le";
3454     case 017: return "ngt";
3455     default: return "?";
3456     }
3457 }
3458
3459
3460 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3461 "abs.%s<FMT> f<FD>, f<FS>"
3462 *mipsI:
3463 *mipsII:
3464 *mipsIII:
3465 *mipsIV:
3466 // start-sanitize-vr5400
3467 *vr5400:
3468 // end-sanitize-vr5400
3469 // start-sanitize-r5900
3470 *r5900:
3471 // end-sanitize-r5900
3472 *r3900:
3473 // start-sanitize-tx19
3474 *tx19:
3475 // end-sanitize-tx19
3476 {
3477   unsigned32 instruction = instruction_0;
3478   int destreg = ((instruction >> 6) & 0x0000001F);
3479   int fs = ((instruction >> 11) & 0x0000001F);
3480   int format = ((instruction >> 21) & 0x00000007);
3481   {
3482     if ((format != fmt_single) && (format != fmt_double))
3483       SignalException(ReservedInstruction,instruction);
3484     else
3485       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3486   }
3487 }
3488
3489
3490
3491
3492 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
3493 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3494 *mipsI:
3495 *mipsII:
3496 *mipsIII:
3497 *mipsIV:
3498 // start-sanitize-vr5400
3499 *vr5400:
3500 // end-sanitize-vr5400
3501 // start-sanitize-r5900
3502 *r5900:
3503 // end-sanitize-r5900
3504 *r3900:
3505 // start-sanitize-tx19
3506 *tx19:
3507 // end-sanitize-tx19
3508 {
3509   unsigned32 instruction = instruction_0;
3510   int destreg = ((instruction >> 6) & 0x0000001F);
3511   int fs = ((instruction >> 11) & 0x0000001F);
3512   int ft = ((instruction >> 16) & 0x0000001F);
3513   int format = ((instruction >> 21) & 0x00000007);
3514   {
3515     if ((format != fmt_single) && (format != fmt_double))
3516       SignalException(ReservedInstruction, instruction);
3517     else
3518       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3519   }
3520 }
3521
3522
3523 //
3524 // FIXME: This does not correctly resolve mipsI-mipsIV differences.
3525 //
3526 // BC1F
3527 // BC1FL
3528 // BC1T
3529 // BC1TL
3530 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3531 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3532 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3533 *mipsI:
3534 *mipsII:
3535 *mipsIII:
3536 *mipsIV:
3537 // start-sanitize-vr5400
3538 *vr5400:
3539 // end-sanitize-vr5400
3540 // start-sanitize-r5900
3541 *r5900:
3542 // end-sanitize-r5900
3543 *r3900:
3544 // start-sanitize-tx19
3545 *tx19:
3546 // end-sanitize-tx19
3547 {
3548   unsigned32 instruction = instruction_0;
3549   signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
3550   int boolean = ((instruction >> 16) & 0x00000001);
3551   int likely = ((instruction >> 17) & 0x00000001);
3552   int condition_code = ((instruction >> 18) & 0x00000007);
3553   {
3554     if (condition_code != 0)
3555       SignalException(ReservedInstruction,instruction);
3556     else {
3557       int condition = (PREVCOC1() == boolean);
3558       /* NOTE: The branch occurs AFTER the next instruction has been executed */
3559       if (condition) {
3560         DELAY_SLOT (PC + offset);
3561       }
3562       else if (likely) {
3563         NULLIFY_NEXT_INSTRUCTION ();
3564       }
3565     }
3566   }
3567 }
3568
3569
3570 //
3571 // FIXME: This does not correctly differentiate between mips*
3572 //
3573 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
3574 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3575 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3576 *mipsI:
3577 *mipsII:
3578 *mipsIII:
3579 *mipsIV:
3580 // start-sanitize-vr5400
3581 *vr5400:
3582 // end-sanitize-vr5400
3583 // start-sanitize-r5900
3584 *r5900:
3585 // end-sanitize-r5900
3586 *r3900:
3587 // start-sanitize-tx19
3588 *tx19:
3589 // end-sanitize-tx19
3590 {
3591   unsigned32 instruction = instruction_0;
3592   int cmpflags = ((instruction >> 0) & 0x0000000F);
3593   int condition_code = ((instruction >> 8) & 0x00000007);
3594   int fs = ((instruction >> 11) & 0x0000001F);
3595   int ft = ((instruction >> 16) & 0x0000001F);
3596   int format = ((instruction >> 21) & 0x00000007);
3597   if (condition_code != 0)
3598     {
3599       SignalException(ReservedInstruction,instruction);
3600     }
3601   else
3602     {
3603       if ((format != fmt_single) && (format != fmt_double))
3604         SignalException(ReservedInstruction,instruction);
3605       else {
3606         if (condition_code != 0)
3607           SignalException(ReservedInstruction,instruction);
3608         else
3609           {
3610             int ignore = 0;
3611             int less = 0;
3612             int equal = 0;
3613             int unordered = 1;
3614             unsigned64 ofs = ValueFPR(fs,format);
3615             unsigned64 oft = ValueFPR(ft,format);
3616             if (NaN(ofs,format) || NaN(oft,format)) {
3617               if (FCSR & FP_ENABLE(IO)) {
3618                 FCSR |= FP_CAUSE(IO);
3619                 SignalExceptionFPE();
3620                 ignore = 1;
3621               }
3622             } else {
3623               less = Less(ofs,oft,format);
3624               equal = Equal(ofs,oft,format);
3625               unordered = 0;
3626             }
3627             if (!ignore) {
3628               int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
3629               SETFCC(condition_code,condition);
3630             }
3631           }
3632       }
3633     }
3634 }
3635
3636
3637 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
3638 "ceil.l.%s<FMT> f<FD>, f<FS>"
3639 *mipsIII:
3640 *mipsIV:
3641 // start-sanitize-vr5400
3642 *vr5400:
3643 // end-sanitize-vr5400
3644 // start-sanitize-r5900
3645 *r5900:
3646 // end-sanitize-r5900
3647 *r3900:
3648 // start-sanitize-tx19
3649 *tx19:
3650 // end-sanitize-tx19
3651 {
3652   unsigned32 instruction = instruction_0;
3653   int destreg = ((instruction >> 6) & 0x0000001F);
3654   int fs = ((instruction >> 11) & 0x0000001F);
3655   int format = ((instruction >> 21) & 0x00000007);
3656   {
3657     if ((format != fmt_single) && (format != fmt_double))
3658       SignalException(ReservedInstruction,instruction);
3659     else
3660       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3661   }
3662 }
3663
3664
3665 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
3666 *mipsII:
3667 *mipsIII:
3668 *mipsIV:
3669 // start-sanitize-vr5400
3670 *vr5400:
3671 // end-sanitize-vr5400
3672 // start-sanitize-r5900
3673 *r5900:
3674 // end-sanitize-r5900
3675 *r3900:
3676 // start-sanitize-tx19
3677 *tx19:
3678 // end-sanitize-tx19
3679 {
3680   unsigned32 instruction = instruction_0;
3681   int destreg = ((instruction >> 6) & 0x0000001F);
3682   int fs = ((instruction >> 11) & 0x0000001F);
3683   int format = ((instruction >> 21) & 0x00000007);
3684   {
3685   if ((format != fmt_single) && (format != fmt_double))
3686    SignalException(ReservedInstruction,instruction);
3687   else
3688    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3689   }
3690 }
3691
3692
3693 // CFC1
3694 // CTC1
3695 01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1
3696 *mipsI:
3697 *mipsII:
3698 *mipsIII:
3699 *mipsIV:
3700 // start-sanitize-vr5400
3701 *vr5400:
3702 // end-sanitize-vr5400
3703 // start-sanitize-r5900
3704 *r5900:
3705 // end-sanitize-r5900
3706 *r3900:
3707 // start-sanitize-tx19
3708 *tx19:
3709 // end-sanitize-tx19
3710 {
3711   unsigned32 instruction = instruction_0;
3712   int fs = ((instruction >> 11) & 0x0000001F);
3713   int ft = ((instruction >> 16) & 0x0000001F);
3714   int to = ((instruction >> 23) & 0x00000001);
3715   {
3716     if (to) {
3717       if (fs == 0) {
3718         PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft]));
3719       } else if (fs == 31) {
3720         PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft]));
3721       } /* else NOP */
3722       PENDING_FILL(COCIDX,0); /* special case */
3723     } else { /* control from */
3724       if (fs == 0) {
3725         PENDING_FILL(ft,SIGNEXTEND(FCR0,32));
3726       } else if (fs == 31) {
3727         PENDING_FILL(ft,SIGNEXTEND(FCR31,32));
3728       } /* else NOP */
3729     }
3730   }
3731 }
3732
3733
3734 //
3735 // FIXME: Does not correctly differentiate between mips*
3736 //
3737 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
3738 "cvt.d.%s<FMT> f<FD>, f<FS>"
3739 *mipsI:
3740 *mipsII:
3741 *mipsIII:
3742 *mipsIV:
3743 // start-sanitize-vr5400
3744 *vr5400:
3745 // end-sanitize-vr5400
3746 // start-sanitize-r5900
3747 *r5900:
3748 // end-sanitize-r5900
3749 *r3900:
3750 // start-sanitize-tx19
3751 *tx19:
3752 // end-sanitize-tx19
3753 {
3754   unsigned32 instruction = instruction_0;
3755   int destreg = ((instruction >> 6) & 0x0000001F);
3756   int fs = ((instruction >> 11) & 0x0000001F);
3757   int format = ((instruction >> 21) & 0x00000007);
3758   {
3759     if ((format == fmt_double) | 0)
3760       SignalException(ReservedInstruction,instruction);
3761     else
3762       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3763   }
3764 }
3765
3766
3767 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
3768 "cvt.l.%s<FMT> f<FD>, f<FS>"
3769 *mipsIII:
3770 *mipsIV:
3771 // start-sanitize-vr5400
3772 *vr5400:
3773 // end-sanitize-vr5400
3774 // start-sanitize-r5900
3775 *r5900:
3776 // end-sanitize-r5900
3777 *r3900:
3778 // start-sanitize-tx19
3779 *tx19:
3780 // end-sanitize-tx19
3781 {
3782   unsigned32 instruction = instruction_0;
3783   int destreg = ((instruction >> 6) & 0x0000001F);
3784   int fs = ((instruction >> 11) & 0x0000001F);
3785   int format = ((instruction >> 21) & 0x00000007);
3786   {
3787     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3788       SignalException(ReservedInstruction,instruction);
3789     else
3790       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3791   }
3792 }
3793
3794
3795 //
3796 // FIXME: Does not correctly differentiate between mips*
3797 //
3798 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
3799 "cvt.s.%s<FMT> f<FD>, f<FS>"
3800 *mipsI:
3801 *mipsII:
3802 *mipsIII:
3803 *mipsIV:
3804 // start-sanitize-vr5400
3805 *vr5400:
3806 // end-sanitize-vr5400
3807 // start-sanitize-r5900
3808 *r5900:
3809 // end-sanitize-r5900
3810 *r3900:
3811 // start-sanitize-tx19
3812 *tx19:
3813 // end-sanitize-tx19
3814 {
3815   unsigned32 instruction = instruction_0;
3816   int destreg = ((instruction >> 6) & 0x0000001F);
3817   int fs = ((instruction >> 11) & 0x0000001F);
3818   int format = ((instruction >> 21) & 0x00000007);
3819   {
3820     if ((format == fmt_single) | 0)
3821       SignalException(ReservedInstruction,instruction);
3822     else
3823       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3824   }
3825 }
3826
3827
3828 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
3829 "cvt.w.%s<FMT> f<FD>, f<FS>"
3830 *mipsI:
3831 *mipsII:
3832 *mipsIII:
3833 *mipsIV:
3834 // start-sanitize-vr5400
3835 *vr5400:
3836 // end-sanitize-vr5400
3837 // start-sanitize-r5900
3838 *r5900:
3839 // end-sanitize-r5900
3840 *r3900:
3841 // start-sanitize-tx19
3842 *tx19:
3843 // end-sanitize-tx19
3844 {
3845   unsigned32 instruction = instruction_0;
3846   int destreg = ((instruction >> 6) & 0x0000001F);
3847   int fs = ((instruction >> 11) & 0x0000001F);
3848   int format = ((instruction >> 21) & 0x00000007);
3849   {
3850     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3851       SignalException(ReservedInstruction,instruction);
3852     else
3853       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3854   }
3855 }
3856
3857
3858 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
3859 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3860 *mipsI:
3861 *mipsII:
3862 *mipsIII:
3863 *mipsIV:
3864 // start-sanitize-vr5400
3865 *vr5400:
3866 // end-sanitize-vr5400
3867 // start-sanitize-r5900
3868 *r5900:
3869 // end-sanitize-r5900
3870 *r3900:
3871 // start-sanitize-tx19
3872 *tx19:
3873 // end-sanitize-tx19
3874 {
3875   unsigned32 instruction = instruction_0;
3876   int destreg = ((instruction >> 6) & 0x0000001F);
3877   int fs = ((instruction >> 11) & 0x0000001F);
3878   int ft = ((instruction >> 16) & 0x0000001F);
3879   int format = ((instruction >> 21) & 0x00000007);
3880   {
3881     if ((format != fmt_single) && (format != fmt_double))
3882       SignalException(ReservedInstruction,instruction);
3883     else
3884       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3885   }
3886 }
3887
3888
3889 // DMFC1
3890 // DMTC1
3891 01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1
3892 *mipsIII:
3893 *mipsIV:
3894 // start-sanitize-vr5400
3895 *vr5400:
3896 // end-sanitize-vr5400
3897 // start-sanitize-r5900
3898 *r5900:
3899 // end-sanitize-r5900
3900 *r3900:
3901 // start-sanitize-tx19
3902 *tx19:
3903 // end-sanitize-tx19
3904 {
3905   unsigned32 instruction = instruction_0;
3906   int fs = ((instruction >> 11) & 0x0000001F);
3907   int ft = ((instruction >> 16) & 0x0000001F);
3908   int to = ((instruction >> 23) & 0x00000001);
3909   {
3910     if (to) {
3911       if (SizeFGR() == 64) {
3912         PENDING_FILL((fs + FGRIDX),GPR[ft]);
3913       } else
3914         if ((fs & 0x1) == 0)
3915           {
3916             PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft]));
3917             PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft]));
3918           }
3919     } else {
3920       if (SizeFGR() == 64) {
3921         PENDING_FILL(ft,FGR[fs]);
3922       } else
3923         if ((fs & 0x1) == 0) {
3924           PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs]));
3925         } else {
3926           PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3927         }
3928     }
3929   }
3930 }
3931
3932
3933 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3934 "floor.l.%s<FMT> f<FD>, f<FS>"
3935 *mipsIII:
3936 *mipsIV:
3937 // start-sanitize-vr5400
3938 *vr5400:
3939 // end-sanitize-vr5400
3940 // start-sanitize-r5900
3941 *r5900:
3942 // end-sanitize-r5900
3943 *r3900:
3944 // start-sanitize-tx19
3945 *tx19:
3946 // end-sanitize-tx19
3947 {
3948   unsigned32 instruction = instruction_0;
3949   int destreg = ((instruction >> 6) & 0x0000001F);
3950   int fs = ((instruction >> 11) & 0x0000001F);
3951   int format = ((instruction >> 21) & 0x00000007);
3952   {
3953     if ((format != fmt_single) && (format != fmt_double))
3954       SignalException(ReservedInstruction,instruction);
3955     else
3956       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3957   }
3958 }
3959
3960
3961 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3962 "floor.w.%s<FMT> f<FD>, f<FS>"
3963 *mipsII:
3964 *mipsIII:
3965 *mipsIV:
3966 // start-sanitize-vr5400
3967 *vr5400:
3968 // end-sanitize-vr5400
3969 // start-sanitize-r5900
3970 *r5900:
3971 // end-sanitize-r5900
3972 *r3900:
3973 // start-sanitize-tx19
3974 *tx19:
3975 // end-sanitize-tx19
3976 {
3977   unsigned32 instruction = instruction_0;
3978   int destreg = ((instruction >> 6) & 0x0000001F);
3979   int fs = ((instruction >> 11) & 0x0000001F);
3980   int format = ((instruction >> 21) & 0x00000007);
3981   {
3982     if ((format != fmt_single) && (format != fmt_double))
3983       SignalException(ReservedInstruction,instruction);
3984     else
3985       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3986   }
3987 }
3988
3989
3990 // LDC1
3991 110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1
3992
3993
3994 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3995 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3996 *mipsIV:
3997 // start-sanitize-vr5400
3998 *vr5400:
3999 // end-sanitize-vr5400
4000 // start-sanitize-r5900
4001 *r5900:
4002 // end-sanitize-r5900
4003 {
4004   unsigned32 instruction = instruction_0;
4005   int destreg = ((instruction >> 6) & 0x0000001F);
4006   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4007   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4008   {
4009     address_word vaddr = ((unsigned64)op1 + op2);
4010     address_word paddr;
4011     int uncached;
4012     if ((vaddr & 7) != 0)
4013       SignalExceptionAddressLoad();
4014     else
4015       {
4016         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4017           {
4018             unsigned64 memval = 0;
4019             unsigned64 memval1 = 0;
4020             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4021             COP_LD(1,destreg,memval);;
4022           }
4023       }
4024   }
4025 }
4026
4027
4028 // LWC1
4029 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4030
4031
4032 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4033 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4034 *mipsIV:
4035 // start-sanitize-vr5400
4036 *vr5400:
4037 // end-sanitize-vr5400
4038 // start-sanitize-r5900
4039 *r5900:
4040 // end-sanitize-r5900
4041 {
4042   unsigned32 instruction = instruction_0;
4043   int destreg = ((instruction >> 6) & 0x0000001F);
4044   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4045   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4046   {
4047    address_word vaddr = ((unsigned64)op1 + op2);
4048    address_word paddr;
4049    int uncached;
4050    if ((vaddr & 3) != 0)
4051     SignalExceptionAddressLoad();
4052    else
4053    {
4054     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4055     {
4056      unsigned64 memval = 0;
4057      unsigned64 memval1 = 0;
4058      unsigned64 mask = 0x7;
4059      unsigned int shift = 2;
4060      unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4061      unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4062      unsigned int byte;
4063      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4064      LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4065      byte = ((vaddr & mask) ^ (bigend << shift));
4066      COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4067     }
4068    }
4069   }
4070 }
4071
4072
4073
4074 //
4075 // FIXME: Not correct for mips*
4076 //
4077 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
4078 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4079 *mipsIV:
4080 // start-sanitize-vr5400
4081 *vr5400:
4082 // end-sanitize-vr5400
4083 // start-sanitize-r5900
4084 *r5900:
4085 // end-sanitize-r5900
4086 {
4087   unsigned32 instruction = instruction_0;
4088   int destreg = ((instruction >> 6) & 0x0000001F);
4089   int fs = ((instruction >> 11) & 0x0000001F);
4090   int ft = ((instruction >> 16) & 0x0000001F);
4091   int fr = ((instruction >> 21) & 0x0000001F);
4092   {
4093     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4094   }
4095 }
4096
4097
4098 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
4099 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4100 *mipsIV:
4101 // start-sanitize-vr5400
4102 *vr5400:
4103 // end-sanitize-vr5400
4104 // start-sanitize-r5900
4105 *r5900:
4106 // end-sanitize-r5900
4107 {
4108   unsigned32 instruction = instruction_0;
4109   int destreg = ((instruction >> 6) & 0x0000001F);
4110   int fs = ((instruction >> 11) & 0x0000001F);
4111   int ft = ((instruction >> 16) & 0x0000001F);
4112   int fr = ((instruction >> 21) & 0x0000001F);
4113   {
4114     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4115   }
4116 }
4117
4118
4119 // MFC1
4120 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4121 "m<X>c1 r<RT>, f<FS>"
4122 *mipsI:
4123 *mipsII:
4124 *mipsIII:
4125 *mipsIV:
4126 // start-sanitize-vr5400
4127 *vr5400:
4128 // end-sanitize-vr5400
4129 // start-sanitize-r5900
4130 *r5900:
4131 // end-sanitize-r5900
4132 *r3900:
4133 // start-sanitize-tx19
4134 *tx19:
4135 // end-sanitize-tx19
4136 {
4137   unsigned32 instruction = instruction_0;
4138   int fs = ((instruction >> 11) & 0x0000001F);
4139   int ft = ((instruction >> 16) & 0x0000001F);
4140   int to = ((instruction >> 23) & 0x00000001);
4141   {
4142     if (to) {
4143       if (SizeFGR() == 64) {
4144         PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft])));
4145       } else {
4146         PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft]));
4147       }
4148     } else {
4149       PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32));
4150     }
4151   }
4152 }
4153
4154
4155 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4156 "mov.%s<FMT> f<FD>, f<FS>"
4157 *mipsI:
4158 *mipsII:
4159 *mipsIII:
4160 *mipsIV:
4161 // start-sanitize-vr5400
4162 *vr5400:
4163 // end-sanitize-vr5400
4164 // start-sanitize-r5900
4165 *r5900:
4166 // end-sanitize-r5900
4167 *r3900:
4168 // start-sanitize-tx19
4169 *tx19:
4170 // end-sanitize-tx19
4171 {
4172   unsigned32 instruction = instruction_0;
4173   int destreg = ((instruction >> 6) & 0x0000001F);
4174   int fs = ((instruction >> 11) & 0x0000001F);
4175   int format = ((instruction >> 21) & 0x00000007);
4176   {
4177     StoreFPR(destreg,format,ValueFPR(fs,format));
4178   }
4179 }
4180
4181
4182 // MOVF
4183 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4184 "mov%s<TF> r<RD>, r<RS>, <CC>"
4185 *mipsIV:
4186 // start-sanitize-vr5400
4187 *vr5400:
4188 // end-sanitize-vr5400
4189 // start-sanitize-r5900
4190 *r5900:
4191 // end-sanitize-r5900
4192 {
4193   if (GETFCC(CC) == TF)
4194     GPR[RD] = GPR[RS];
4195 }
4196
4197
4198 // MOVF.fmt
4199 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4200 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4201 *mipsIV:
4202 // start-sanitize-vr5400
4203 *vr5400:
4204 // end-sanitize-vr5400
4205 // start-sanitize-r5900
4206 *r5900:
4207 // end-sanitize-r5900
4208 {
4209   unsigned32 instruction = instruction_0;
4210   int format = ((instruction >> 21) & 0x00000007);
4211   {
4212    if (GETFCC(CC) == TF)
4213      StoreFPR (FD, format, ValueFPR (FS, format));
4214    else
4215      StoreFPR (FD, format, ValueFPR (FD, format));
4216   }
4217 }
4218
4219
4220 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4221 *mipsIV:
4222 // start-sanitize-vr5400
4223 *vr5400:
4224 // end-sanitize-vr5400
4225 // start-sanitize-r5900
4226 *r5900:
4227 // end-sanitize-r5900
4228 {
4229   unsigned32 instruction = instruction_0;
4230   int destreg = ((instruction >> 6) & 0x0000001F);
4231   int fs = ((instruction >> 11) & 0x0000001F);
4232   int format = ((instruction >> 21) & 0x00000007);
4233   {
4234     StoreFPR(destreg,format,ValueFPR(fs,format));
4235   }
4236 }
4237
4238
4239 // MOVT see MOVtf
4240
4241
4242 // MOVT.fmt see MOVtf.fmt
4243
4244
4245
4246 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4247 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4248 *mipsIV:
4249 // start-sanitize-vr5400
4250 *vr5400:
4251 // end-sanitize-vr5400
4252 // start-sanitize-r5900
4253 *r5900:
4254 // end-sanitize-r5900
4255 {
4256   unsigned32 instruction = instruction_0;
4257   int destreg = ((instruction >> 6) & 0x0000001F);
4258   int fs = ((instruction >> 11) & 0x0000001F);
4259   int format = ((instruction >> 21) & 0x00000007);
4260   {
4261    StoreFPR(destreg,format,ValueFPR(fs,format));
4262   }
4263 }
4264
4265
4266 // MSUB.fmt
4267 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4268 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4269 *mipsIV:
4270 // start-sanitize-vr5400
4271 *vr5400:
4272 // end-sanitize-vr5400
4273 // start-sanitize-r5900
4274 *r5900:
4275 // end-sanitize-r5900
4276 {
4277   unsigned32 instruction = instruction_0;
4278   int destreg = ((instruction >> 6) & 0x0000001F);
4279   int fs = ((instruction >> 11) & 0x0000001F);
4280   int ft = ((instruction >> 16) & 0x0000001F);
4281   int fr = ((instruction >> 21) & 0x0000001F);
4282   {
4283     StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4284   }
4285 }
4286
4287
4288 // MSUB.fmt
4289 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4290 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4291 *mipsIV:
4292 // start-sanitize-vr5400
4293 *vr5400:
4294 // end-sanitize-vr5400
4295 // start-sanitize-r5900
4296 *r5900:
4297 // end-sanitize-r5900
4298 {
4299   unsigned32 instruction = instruction_0;
4300   int destreg = ((instruction >> 6) & 0x0000001F);
4301   int fs = ((instruction >> 11) & 0x0000001F);
4302   int ft = ((instruction >> 16) & 0x0000001F);
4303   int fr = ((instruction >> 21) & 0x0000001F);
4304   {
4305    StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4306   }
4307 }
4308
4309
4310 // MTC1 see MxC1
4311
4312
4313 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4314 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4315 *mipsI:
4316 *mipsII:
4317 *mipsIII:
4318 *mipsIV:
4319 // start-sanitize-vr5400
4320 *vr5400:
4321 // end-sanitize-vr5400
4322 // start-sanitize-r5900
4323 *r5900:
4324 // end-sanitize-r5900
4325 *r3900:
4326 // start-sanitize-tx19
4327 *tx19:
4328 // end-sanitize-tx19
4329 {
4330   unsigned32 instruction = instruction_0;
4331   int destreg = ((instruction >> 6) & 0x0000001F);
4332   int fs = ((instruction >> 11) & 0x0000001F);
4333   int ft = ((instruction >> 16) & 0x0000001F);
4334   int format = ((instruction >> 21) & 0x00000007);
4335   {
4336     if ((format != fmt_single) && (format != fmt_double))
4337       SignalException(ReservedInstruction,instruction);
4338     else
4339       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4340   }
4341 }
4342
4343
4344 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4345 "neg.%s<FMT> f<FD>, f<FS>"
4346 *mipsI:
4347 *mipsII:
4348 *mipsIII:
4349 *mipsIV:
4350 // start-sanitize-vr5400
4351 *vr5400:
4352 // end-sanitize-vr5400
4353 // start-sanitize-r5900
4354 *r5900:
4355 // end-sanitize-r5900
4356 *r3900:
4357 // start-sanitize-tx19
4358 *tx19:
4359 // end-sanitize-tx19
4360 {
4361   unsigned32 instruction = instruction_0;
4362   int destreg = ((instruction >> 6) & 0x0000001F);
4363   int fs = ((instruction >> 11) & 0x0000001F);
4364   int format = ((instruction >> 21) & 0x00000007);
4365   {
4366     if ((format != fmt_single) && (format != fmt_double))
4367       SignalException(ReservedInstruction,instruction);
4368     else
4369       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4370   }
4371 }
4372
4373
4374 // NMADD.fmt
4375 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4376 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4377 *mipsIV:
4378 // start-sanitize-vr5400
4379 *vr5400:
4380 // end-sanitize-vr5400
4381 {
4382   unsigned32 instruction = instruction_0;
4383   int destreg = ((instruction >> 6) & 0x0000001F);
4384   int fs = ((instruction >> 11) & 0x0000001F);
4385   int ft = ((instruction >> 16) & 0x0000001F);
4386   int fr = ((instruction >> 21) & 0x0000001F);
4387   {
4388    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4389   }
4390 }
4391
4392
4393 // NMADD.fmt
4394 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4395 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4396 *mipsIV:
4397 // start-sanitize-vr5400
4398 *vr5400:
4399 // end-sanitize-vr5400
4400 {
4401   unsigned32 instruction = instruction_0;
4402   int destreg = ((instruction >> 6) & 0x0000001F);
4403   int fs = ((instruction >> 11) & 0x0000001F);
4404   int ft = ((instruction >> 16) & 0x0000001F);
4405   int fr = ((instruction >> 21) & 0x0000001F);
4406   {
4407    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4408   }
4409 }
4410
4411
4412 // NMSUB.fmt
4413 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4414 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4415 *mipsIV:
4416 // start-sanitize-vr5400
4417 *vr5400:
4418 // end-sanitize-vr5400
4419 {
4420   unsigned32 instruction = instruction_0;
4421   int destreg = ((instruction >> 6) & 0x0000001F);
4422   int fs = ((instruction >> 11) & 0x0000001F);
4423   int ft = ((instruction >> 16) & 0x0000001F);
4424   int fr = ((instruction >> 21) & 0x0000001F);
4425   {
4426    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4427   }
4428 }
4429
4430
4431 // NMSUB.fmt
4432 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4433 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4434 *mipsIV:
4435 // start-sanitize-vr5400
4436 *vr5400:
4437 // end-sanitize-vr5400
4438 {
4439   unsigned32 instruction = instruction_0;
4440   int destreg = ((instruction >> 6) & 0x0000001F);
4441   int fs = ((instruction >> 11) & 0x0000001F);
4442   int ft = ((instruction >> 16) & 0x0000001F);
4443   int fr = ((instruction >> 21) & 0x0000001F);
4444   {
4445     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4446   }
4447 }
4448
4449
4450 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4451 "prefx <HINT>, r<INDEX>(r<BASE>)"
4452 *mipsIV:
4453 // start-sanitize-vr5400
4454 *vr5400:
4455 // end-sanitize-vr5400
4456 {
4457   unsigned32 instruction = instruction_0;
4458   int fs = ((instruction >> 11) & 0x0000001F);
4459   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4460   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4461   {
4462     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4463     address_word paddr;
4464     int uncached;
4465     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4466       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4467   }
4468 }
4469
4470 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4471 *mipsIV:
4472 "recip.%s<FMT> f<FD>, f<FS>"
4473 // start-sanitize-vr5400
4474 *vr5400:
4475 // end-sanitize-vr5400
4476 {
4477   unsigned32 instruction = instruction_0;
4478   int destreg = ((instruction >> 6) & 0x0000001F);
4479   int fs = ((instruction >> 11) & 0x0000001F);
4480   int format = ((instruction >> 21) & 0x00000007);
4481   {
4482   if ((format != fmt_single) && (format != fmt_double))
4483    SignalException(ReservedInstruction,instruction);
4484   else
4485    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4486   }
4487 }
4488
4489
4490 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4491 "round.l.%s<FMT> f<FD>, f<FS>"
4492 *mipsIII:
4493 *mipsIV:
4494 // start-sanitize-vr5400
4495 *vr5400:
4496 // end-sanitize-vr5400
4497 // start-sanitize-r5900
4498 *r5900:
4499 // end-sanitize-r5900
4500 *r3900:
4501 // start-sanitize-tx19
4502 *tx19:
4503 // end-sanitize-tx19
4504 {
4505   unsigned32 instruction = instruction_0;
4506   int destreg = ((instruction >> 6) & 0x0000001F);
4507   int fs = ((instruction >> 11) & 0x0000001F);
4508   int format = ((instruction >> 21) & 0x00000007);
4509   {
4510     if ((format != fmt_single) && (format != fmt_double))
4511       SignalException(ReservedInstruction,instruction);
4512     else
4513       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4514   }
4515 }
4516
4517
4518 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
4519 "round.w.%s<FMT> f<FD>, f<FS>"
4520 *mipsII:
4521 *mipsIII:
4522 *mipsIV:
4523 // start-sanitize-vr5400
4524 *vr5400:
4525 // end-sanitize-vr5400
4526 // start-sanitize-r5900
4527 *r5900:
4528 // end-sanitize-r5900
4529 *r3900:
4530 // start-sanitize-tx19
4531 *tx19:
4532 // end-sanitize-tx19
4533 {
4534   unsigned32 instruction = instruction_0;
4535   int destreg = ((instruction >> 6) & 0x0000001F);
4536   int fs = ((instruction >> 11) & 0x0000001F);
4537   int format = ((instruction >> 21) & 0x00000007);
4538   {
4539   if ((format != fmt_single) && (format != fmt_double))
4540    SignalException(ReservedInstruction,instruction);
4541   else
4542    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4543   }
4544 }
4545
4546
4547 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
4548 *mipsIV:
4549 "rsqrt.%s<FMT> f<FD>, f<FS>"
4550 // start-sanitize-vr5400
4551 *vr5400:
4552 // end-sanitize-vr5400
4553 {
4554   unsigned32 instruction = instruction_0;
4555   int destreg = ((instruction >> 6) & 0x0000001F);
4556   int fs = ((instruction >> 11) & 0x0000001F);
4557   int format = ((instruction >> 21) & 0x00000007);
4558   {
4559   if ((format != fmt_single) && (format != fmt_double))
4560    SignalException(ReservedInstruction,instruction);
4561   else
4562    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4563   }
4564 }
4565
4566
4567 // SDC1
4568
4569
4570 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
4571 *mipsIV:
4572 // start-sanitize-vr5400
4573 *vr5400:
4574 // end-sanitize-vr5400
4575 // start-sanitize-r5900
4576 *r5900:
4577 // end-sanitize-r5900
4578 {
4579   unsigned32 instruction = instruction_0;
4580   int fs = ((instruction >> 11) & 0x0000001F);
4581   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4582   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4583   {
4584     address_word vaddr = ((unsigned64)op1 + op2);
4585     address_word paddr;
4586     int uncached;
4587     if ((vaddr & 7) != 0)
4588       SignalExceptionAddressStore();
4589     else
4590       {
4591         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4592           {
4593             unsigned64 memval = 0;
4594             unsigned64 memval1 = 0;
4595             memval = (unsigned64)COP_SD(1,fs);
4596             {
4597               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
4598             }
4599           }
4600       }
4601   }
4602 }
4603
4604
4605 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
4606 "sqrt.%s<FMT> f<FD>, f<FS>"
4607 *mipsII:
4608 *mipsIII:
4609 *mipsIV:
4610 // start-sanitize-vr5400
4611 *vr5400:
4612 // end-sanitize-vr5400
4613 // start-sanitize-r5900
4614 *r5900:
4615 // end-sanitize-r5900
4616 *r3900:
4617 // start-sanitize-tx19
4618 *tx19:
4619 // end-sanitize-tx19
4620 {
4621   unsigned32 instruction = instruction_0;
4622   int destreg = ((instruction >> 6) & 0x0000001F);
4623   int fs = ((instruction >> 11) & 0x0000001F);
4624   int format = ((instruction >> 21) & 0x00000007);
4625   {
4626     if ((format != fmt_single) && (format != fmt_double))
4627       SignalException(ReservedInstruction,instruction);
4628     else
4629       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4630   }
4631 }
4632
4633
4634 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
4635 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4636 *mipsI:
4637 *mipsII:
4638 *mipsIII:
4639 *mipsIV:
4640 // start-sanitize-vr5400
4641 *vr5400:
4642 // end-sanitize-vr5400
4643 // start-sanitize-r5900
4644 *r5900:
4645 // end-sanitize-r5900
4646 *r3900:
4647 // start-sanitize-tx19
4648 *tx19:
4649 // end-sanitize-tx19
4650 {
4651   unsigned32 instruction = instruction_0;
4652   int destreg = ((instruction >> 6) & 0x0000001F);
4653   int fs = ((instruction >> 11) & 0x0000001F);
4654   int ft = ((instruction >> 16) & 0x0000001F);
4655   int format = ((instruction >> 21) & 0x00000007);
4656   {
4657     if ((format != fmt_single) && (format != fmt_double))
4658       SignalException(ReservedInstruction,instruction);
4659     else
4660       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4661   }
4662 }
4663
4664
4665 // SWC1
4666
4667
4668 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
4669 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4670 *mipsIV:
4671 // start-sanitize-vr5400
4672 *vr5400:
4673 // end-sanitize-vr5400
4674 // start-sanitize-r5900
4675 *r5900:
4676 // end-sanitize-r5900
4677 {
4678   unsigned32 instruction = instruction_0;
4679   int fs = ((instruction >> 11) & 0x0000001F);
4680   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4681   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4682   {
4683    address_word vaddr = ((unsigned64)op1 + op2);
4684    address_word paddr;
4685    int uncached;
4686    if ((vaddr & 3) != 0)
4687     SignalExceptionAddressStore();
4688    else
4689    {
4690     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4691     {
4692      unsigned64 memval = 0;
4693      unsigned64 memval1 = 0;
4694      unsigned64 mask = 0x7;
4695      unsigned int byte;
4696      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4697      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4698      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4699       {
4700        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4701       }
4702     }
4703    }
4704   }
4705 }
4706
4707
4708 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
4709 "trunc.l.%s<FMT> f<FD>, f<FS>"
4710 *mipsIII:
4711 *mipsIV:
4712 // start-sanitize-vr5400
4713 *vr5400:
4714 // end-sanitize-vr5400
4715 // start-sanitize-r5900
4716 *r5900:
4717 // end-sanitize-r5900
4718 *r3900:
4719 // start-sanitize-tx19
4720 *tx19:
4721 // end-sanitize-tx19
4722 {
4723   unsigned32 instruction = instruction_0;
4724   int destreg = ((instruction >> 6) & 0x0000001F);
4725   int fs = ((instruction >> 11) & 0x0000001F);
4726   int format = ((instruction >> 21) & 0x00000007);
4727   {
4728   if ((format != fmt_single) && (format != fmt_double))
4729    SignalException(ReservedInstruction,instruction);
4730   else
4731    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4732   }
4733 }
4734
4735
4736 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
4737 "trunc.w.%s<FMT> f<FD>, f<FS>"
4738 *mipsII:
4739 *mipsIII:
4740 *mipsIV:
4741 // start-sanitize-vr5400
4742 *vr5400:
4743 // end-sanitize-vr5400
4744 // start-sanitize-r5900
4745 *r5900:
4746 // end-sanitize-r5900
4747 *r3900:
4748 // start-sanitize-tx19
4749 *tx19:
4750 // end-sanitize-tx19
4751 {
4752   unsigned32 instruction = instruction_0;
4753   int destreg = ((instruction >> 6) & 0x0000001F);
4754   int fs = ((instruction >> 11) & 0x0000001F);
4755   int format = ((instruction >> 21) & 0x00000007);
4756   {
4757   if ((format != fmt_single) && (format != fmt_double))
4758    SignalException(ReservedInstruction,instruction);
4759   else
4760    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4761   }
4762 }
4763
4764 \f
4765 //
4766 // MIPS Architecture:
4767 //
4768 //        System Control Instruction Set (COP0)
4769 //
4770
4771
4772 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4773 "bc0f <OFFSET>"
4774 *mipsI:
4775 *mipsII:
4776 *mipsIII:
4777 *mipsIV:
4778 // start-sanitize-vr5400
4779 *vr5400:
4780 // end-sanitize-vr5400
4781 // start-sanitize-r5900
4782 *r5900:
4783 // end-sanitize-r5900
4784
4785
4786 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4787 "bc0fl <OFFSET>"
4788 *mipsI:
4789 *mipsII:
4790 *mipsIII:
4791 *mipsIV:
4792 // start-sanitize-vr5400
4793 *vr5400:
4794 // end-sanitize-vr5400
4795 // start-sanitize-r5900
4796 *r5900:
4797 // end-sanitize-r5900
4798
4799
4800 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4801 "bc0t <OFFSET>"
4802 *mipsI:
4803 *mipsII:
4804 *mipsIII:
4805 *mipsIV:
4806 // start-sanitize-r5900
4807 *r5900:
4808 // end-sanitize-r5900
4809
4810
4811
4812 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4813 "bc0tl <OFFSET>"
4814 *mipsI:
4815 *mipsII:
4816 *mipsIII:
4817 *mipsIV:
4818 // start-sanitize-vr5400
4819 *vr5400:
4820 // end-sanitize-vr5400
4821 // start-sanitize-r5900
4822 *r5900:
4823 // end-sanitize-r5900
4824
4825
4826 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4827 *mipsIII:
4828 *mipsIV:
4829 // start-sanitize-vr5400
4830 *vr5400:
4831 // end-sanitize-vr5400
4832 // start-sanitize-r5900
4833 *r5900:
4834 // end-sanitize-r5900
4835 *r3900:
4836 // start-sanitize-tx19
4837 *tx19:
4838 // end-sanitize-tx19
4839 {
4840   unsigned32 instruction = instruction_0;
4841   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
4842   int hint = ((instruction >> 16) & 0x0000001F);
4843   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4844   {
4845     address_word vaddr = (op1 + offset);
4846     address_word paddr;
4847     int uncached;
4848     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4849       CacheOp(hint,vaddr,paddr,instruction);
4850   }
4851 }
4852
4853
4854 010000,10000,000000000000000,111001:COP0:32::DI
4855 "di"
4856 *mipsI:
4857 *mipsII:
4858 *mipsIII:
4859 *mipsIV:
4860 // start-sanitize-vr5400
4861 *vr5400:
4862 // end-sanitize-vr5400
4863 // start-sanitize-r5900
4864 *r5900:
4865 // end-sanitize-r5900
4866
4867
4868 010000,10000,000000000000000,111000:COP0:32::EI
4869 "ei"
4870 *mipsI:
4871 *mipsII:
4872 *mipsIII:
4873 *mipsIV:
4874 // start-sanitize-vr5400
4875 *vr5400:
4876 // end-sanitize-vr5400
4877 // start-sanitize-r5900
4878 *r5900:
4879 // end-sanitize-r5900
4880
4881
4882 010000,10000,000000000000000,011000:COP0:32::ERET
4883 "eret"
4884 *mipsIII:
4885 *mipsIV:
4886 // start-sanitize-vr5400
4887 *vr5400:
4888 // end-sanitize-vr5400
4889 // start-sanitize-r5900
4890 *r5900:
4891 // end-sanitize-r5900
4892
4893
4894 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4895 "mfc0 r<RT>, r<RD> # <REGX>"
4896 *mipsI:
4897 *mipsII:
4898 *mipsIII:
4899 *mipsIV:
4900 // start-sanitize-vr5400
4901 *vr5400:
4902 // end-sanitize-vr5400
4903 // start-sanitize-r5900
4904 *r5900:
4905 // end-sanitize-r5900
4906
4907
4908 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4909 "mtc0 r<RT>, r<RD> # <REGX>"
4910 *mipsI:
4911 *mipsII:
4912 *mipsIII:
4913 *mipsIV:
4914 // start-sanitize-vr5400
4915 *vr5400:
4916 // end-sanitize-vr5400
4917 // start-sanitize-r5900
4918 *r5900:
4919 // end-sanitize-r5900
4920
4921
4922 010000,10000,000000000000000,001000:COP0:32::TLBP
4923 "tlbp"
4924 *mipsI:
4925 *mipsII:
4926 *mipsIII:
4927 *mipsIV:
4928 // start-sanitize-vr5400
4929 *vr5400:
4930 // end-sanitize-vr5400
4931 // start-sanitize-r5900
4932 *r5900:
4933 // end-sanitize-r5900
4934
4935
4936 010000,10000,000000000000000,000001:COP0:32::TLBR
4937 "tlbr"
4938 *mipsI:
4939 *mipsII:
4940 *mipsIII:
4941 *mipsIV:
4942 // start-sanitize-vr5400
4943 *vr5400:
4944 // end-sanitize-vr5400
4945 // start-sanitize-r5900
4946 *r5900:
4947 // end-sanitize-r5900
4948
4949
4950 010000,10000,000000000000000,000010:COP0:32::TLBWI
4951 "tlbwi"
4952 *mipsI:
4953 *mipsII:
4954 *mipsIII:
4955 *mipsIV:
4956 // start-sanitize-vr5400
4957 *vr5400:
4958 // end-sanitize-vr5400
4959 // start-sanitize-r5900
4960 *r5900:
4961 // end-sanitize-r5900
4962
4963
4964 010000,10000,000000000000000,000110:COP0:32::TLBWR
4965 "tlbwr"
4966 *mipsI:
4967 *mipsII:
4968 *mipsIII:
4969 *mipsIV:
4970 // start-sanitize-vr5400
4971 *vr5400:
4972 // end-sanitize-vr5400
4973 // start-sanitize-r5900
4974 *r5900:
4975 // end-sanitize-r5900
4976
4977 \f
4978 :include:::m16.igen
4979 // start-sanitize-vr5400
4980 :include::vr5400:vr5400.igen
4981 // end-sanitize-vr5400
4982 // start-sanitize-r5900
4983 :include::r5900:r5900.igen
4984 // end-sanitize-r5900
4985 \f
4986 // start-sanitize-cygnus-never
4987
4988 // // FIXME FIXME FIXME What is this instruction?
4989 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
4990 // *mipsI:
4991 // *mipsII:
4992 // *mipsIII:
4993 // *mipsIV:
4994 // // start-sanitize-r5900
4995 // *r5900:
4996 // // end-sanitize-r5900
4997 // *r3900:
4998 // // start-sanitize-tx19
4999 // *tx19:
5000 // // end-sanitize-tx19
5001 // {
5002 //   unsigned32 instruction = instruction_0;
5003 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5004 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5005 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5006 //   {
5007 //     if (CoProcPresent(3))
5008 //       SignalException(CoProcessorUnusable);
5009 //     else
5010 //       SignalException(ReservedInstruction,instruction);
5011 //   }
5012 // }
5013
5014 // end-sanitize-cygnus-never
5015 // start-sanitize-cygnus-never
5016
5017 // // FIXME FIXME FIXME What is this?
5018 // 11100,******,00001:RR:16::SDBBP
5019 // *mips16:
5020 // {
5021 //   unsigned32 instruction = instruction_0;
5022 //   if (have_extendval)
5023 //     SignalException (ReservedInstruction, instruction);
5024 //   {
5025 //     SignalException(DebugBreakPoint,instruction);
5026 //   }
5027 // }
5028
5029 // end-sanitize-cygnus-never
5030 // start-sanitize-cygnus-never
5031
5032 // // FIXME FIXME FIXME What is this?
5033 // 000000,********************,001110:SPECIAL:32::SDBBP
5034 // *r3900:
5035 // {
5036 //   unsigned32 instruction = instruction_0;
5037 //   {
5038 //     SignalException(DebugBreakPoint,instruction);
5039 //   }
5040 // }
5041
5042 // end-sanitize-cygnus-never
5043 // start-sanitize-cygnus-never
5044
5045 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5046 // // isn't yet reconized by this simulator.
5047 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5048 // *vr4100:
5049 // {
5050 //   unsigned32 instruction = instruction_0;
5051 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5052 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5053 //   {
5054 //     CHECKHILO("Multiply-Add");
5055 //     {
5056 //       unsigned64 temp = (op1 * op2);
5057 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5058 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5059 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5060 //     }
5061 //   }
5062 // }
5063
5064 // end-sanitize-cygnus-never
5065 // start-sanitize-cygnus-never
5066
5067 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5068 // // isn't yet reconized by this simulator.
5069 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5070 // *vr4100:
5071 // {
5072 //   unsigned32 instruction = instruction_0;
5073 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5074 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5075 //   {
5076 //     CHECKHILO("Multiply-Add");
5077 //     {
5078 //       unsigned64 temp = (op1 * op2);
5079 //       LO = LO + temp;
5080 //     }
5081 //   }
5082 // }
5083
5084 // start-sanitize-cygnus-never