sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips64:mipsisa64:
  49
  50 //  Vendor ISAs:
  51 //
  52 //  Standard MIPS ISA instructions used for these models are listed here,
  53 //  as are functions needed by those standard instructions.  Instructions
  54 //  which are model-dependent and which are not in the standard MIPS ISAs
  55 //  (or which pre-date or use different encodings than the standard
  56 //  instructions) are (for the most part) in separate .igen files.
  57 :model:::vr4100:mips4100:               // vr.igen
  58 :model:::vr4120:mips4120:
  59 :model:::vr5000:mips5000:
  60 :model:::vr5400:mips5400:
  61 :model:::vr5500:mips5500:
  62 :model:::r3900:mips3900:                // tx.igen
  63
  64 //  MIPS Application Specific Extensions (ASEs)
  65 //
  66 //  Instructions for the ASEs are in separate .igen files.
  67 //  ASEs add instructions on to a base ISA.
  68 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  69 :model:::mips3d:mips3d:                 // mips3d.igen
  70 :model:::mdmx:mdmx:                     // mdmx.igen
  71
  72 //  Vendor Extensions
  73 //
  74 //  Instructions specific to these extensions are in separate .igen files.
  75 //  Extensions add instructions on to a base ISA.
  76 :model:::sb1:sb1:                       // sb1.igen
  77
  78
  79 // Pseudo instructions known by IGEN
  80 :internal::::illegal:
  81 {
  82   SignalException (ReservedInstruction, 0);
  83 }
  84
  85
  86 // Pseudo instructions known by interp.c
  87 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  88 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  89 "rsvd <OP>"
  90 {
  91   SignalException (ReservedInstruction, instruction_0);
  92 }
  93
  94
  95
  96 // Helper:
  97 //
  98 // Simulate a 32 bit delayslot instruction
  99 //
 100
 101 :function:::address_word:delayslot32:address_word target
 102 {
 103   instruction_word delay_insn;
 104   sim_events_slip (SD, 1);
 105   DSPC = CIA;
 106   CIA = CIA + 4; /* NOTE not mips16 */
 107   STATE |= simDELAYSLOT;
 108   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 109   ENGINE_ISSUE_PREFIX_HOOK();
 110   idecode_issue (CPU_, delay_insn, (CIA));
 111   STATE &= ~simDELAYSLOT;
 112   return target;
 113 }
 114
 115 :function:::address_word:nullify_next_insn32:
 116 {
 117   sim_events_slip (SD, 1);
 118   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 119   return CIA + 8;
 120 }
 121
 122
 123 // Helper:
 124 //
 125 // Calculate an effective address given a base and an offset.
 126 //
 127
 128 :function:::address_word:loadstore_ea:address_word base, address_word offset
 129 *mipsI:
 130 *mipsII:
 131 *mipsIII:
 132 *mipsIV:
 133 *mipsV:
 134 *mips32:
 135 *vr4100:
 136 *vr5000:
 137 *r3900:
 138 {
 139   return base + offset;
 140 }
 141
 142 :function:::address_word:loadstore_ea:address_word base, address_word offset
 143 *mips64:
 144 {
 145 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 146   /* If in user mode and UX is not set, use 32-bit compatibility effective
 147      address computations as defined in the MIPS64 Architecture for
 148      Programmers Volume III, Revision 0.95, section 4.9.  */
 149   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 150       == (ksu_user << status_KSU_shift))
 151     return (address_word)((signed32)base + (signed32)offset);
 152 #endif
 153   return base + offset;
 154 }
 155
 156
 157 // Helper:
 158 //
 159 // Check that a 32-bit register value is properly sign-extended.
 160 // (See NotWordValue in ISA spec.)
 161 //
 162
 163 :function:::int:not_word_value:unsigned_word value
 164 *mipsI:
 165 *mipsII:
 166 *mipsIII:
 167 *mipsIV:
 168 *mipsV:
 169 *vr4100:
 170 *vr5000:
 171 *r3900:
 172 {
 173   /* For historical simulator compatibility (until documentation is
 174      found that makes these operations unpredictable on some of these
 175      architectures), this check never returns true.  */
 176   return 0;
 177 }
 178
 179 :function:::int:not_word_value:unsigned_word value
 180 *mips32:
 181 {
 182   /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
 183   return 0;
 184 }
 185
 186 :function:::int:not_word_value:unsigned_word value
 187 *mips64:
 188 {
 189   return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
 190 }
 191
 192
 193 // Helper:
 194 //
 195 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 196 // theoretically portable code which invokes non-portable behaviour from
 197 // running with no indication of the portability issue.
 198 // (See definition of UNPREDICTABLE in ISA spec.)
 199 //
 200
 201 :function:::void:unpredictable:
 202 *mipsI:
 203 *mipsII:
 204 *mipsIII:
 205 *mipsIV:
 206 *mipsV:
 207 *vr4100:
 208 *vr5000:
 209 *r3900:
 210 {
 211 }
 212
 213 :function:::void:unpredictable:
 214 *mips32:
 215 *mips64:
 216 {
 217   unpredictable_action (CPU, CIA);
 218 }
 219
 220
 221 // Helper:
 222 //
 223 // Check that an access to a HI/LO register meets timing requirements
 224 //
 225 // The following requirements exist:
 226 //
 227 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 228 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 229 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 230 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 231 //
 232
 233 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 234 {
 235   if (history->mf.timestamp + 3 > time)
 236     {
 237       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 238                         itable[MY_INDEX].name,
 239                         new, (long) CIA,
 240                         (long) history->mf.cia);
 241       return 0;
 242     }
 243   return 1;
 244 }
 245
 246 :function:::int:check_mt_hilo:hilo_history *history
 247 *mipsI:
 248 *mipsII:
 249 *mipsIII:
 250 *mipsIV:
 251 *mipsV:
 252 *vr4100:
 253 *vr5000:
 254 {
 255   signed64 time = sim_events_time (SD);
 256   int ok = check_mf_cycles (SD_, history, time, "MT");
 257   history->mt.timestamp = time;
 258   history->mt.cia = CIA;
 259   return ok;
 260 }
 261
 262 :function:::int:check_mt_hilo:hilo_history *history
 263 *mips32:
 264 *mips64:
 265 *r3900:
 266 {
 267   signed64 time = sim_events_time (SD);
 268   history->mt.timestamp = time;
 269   history->mt.cia = CIA;
 270   return 1;
 271 }
 272
 273
 274 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 275 *mipsI:
 276 *mipsII:
 277 *mipsIII:
 278 *mipsIV:
 279 *mipsV:
 280 *mips32:
 281 *mips64:
 282 *vr4100:
 283 *vr5000:
 284 *r3900:
 285 {
 286   signed64 time = sim_events_time (SD);
 287   int ok = 1;
 288   if (peer != NULL
 289       && peer->mt.timestamp > history->op.timestamp
 290       && history->mt.timestamp < history->op.timestamp
 291       && ! (history->mf.timestamp > history->op.timestamp
 292             && history->mf.timestamp < peer->mt.timestamp)
 293       && ! (peer->mf.timestamp > history->op.timestamp
 294             && peer->mf.timestamp < peer->mt.timestamp))
 295     {
 296       /* The peer has been written to since the last OP yet we have
 297          not */
 298       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 299                         itable[MY_INDEX].name,
 300                         (long) CIA,
 301                         (long) history->op.cia,
 302                         (long) peer->mt.cia);
 303       ok = 0;
 304     }
 305   history->mf.timestamp = time;
 306   history->mf.cia = CIA;
 307   return ok;
 308 }
 309
 310
 311
 312 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 313 *mipsI:
 314 *mipsII:
 315 *mipsIII:
 316 *mipsIV:
 317 *mipsV:
 318 *vr4100:
 319 *vr5000:
 320 {
 321   signed64 time = sim_events_time (SD);
 322   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 323             && check_mf_cycles (SD_, lo, time, "OP"));
 324   hi->op.timestamp = time;
 325   lo->op.timestamp = time;
 326   hi->op.cia = CIA;
 327   lo->op.cia = CIA;
 328   return ok;
 329 }
 330
 331 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 332 // a mf{hi,lo}
 333 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 334 *mips32:
 335 *mips64:
 336 *r3900:
 337 {
 338   /* FIXME: could record the fact that a stall occured if we want */
 339   signed64 time = sim_events_time (SD);
 340   hi->op.timestamp = time;
 341   lo->op.timestamp = time;
 342   hi->op.cia = CIA;
 343   lo->op.cia = CIA;
 344   return 1;
 345 }
 346
 347
 348 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 349 *mipsI:
 350 *mipsII:
 351 *mipsIII:
 352 *mipsIV:
 353 *mipsV:
 354 *mips32:
 355 *mips64:
 356 *vr4100:
 357 *vr5000:
 358 *r3900:
 359 {
 360   signed64 time = sim_events_time (SD);
 361   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 362             && check_mf_cycles (SD_, lo, time, "OP"));
 363   hi->op.timestamp = time;
 364   lo->op.timestamp = time;
 365   hi->op.cia = CIA;
 366   lo->op.cia = CIA;
 367   return ok;
 368 }
 369
 370
 371 // Helper:
 372 //
 373 // Check that the 64-bit instruction can currently be used, and signal
 374 // a ReservedInstruction exception if not.
 375 //
 376
 377 :function:::void:check_u64:instruction_word insn
 378 *mipsIII:
 379 *mipsIV:
 380 *mipsV:
 381 *vr4100:
 382 *vr5000:
 383 {
 384   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 385 }
 386
 387 :function:::void:check_u64:instruction_word insn
 388 *mips64:
 389 {
 390 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 391   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 392     SignalException (ReservedInstruction, insn);
 393 #endif
 394 }
 395
 396
 397
 398 //
 399 // MIPS Architecture:
 400 //
 401 //        CPU Instruction Set (mipsI - mipsV, mips32, mips64)
 402 //
 403
 404
 405
 406 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 407 "add r<RD>, r<RS>, r<RT>"
 408 *mipsI:
 409 *mipsII:
 410 *mipsIII:
 411 *mipsIV:
 412 *mipsV:
 413 *mips32:
 414 *mips64:
 415 *vr4100:
 416 *vr5000:
 417 *r3900:
 418 {
 419   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 420     Unpredictable ();
 421   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 422   {
 423     ALU32_BEGIN (GPR[RS]);
 424     ALU32_ADD (GPR[RT]);
 425     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 426   }
 427   TRACE_ALU_RESULT (GPR[RD]);
 428 }
 429
 430
 431
 432 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 433 "addi r<RT>, r<RS>, <IMMEDIATE>"
 434 *mipsI:
 435 *mipsII:
 436 *mipsIII:
 437 *mipsIV:
 438 *mipsV:
 439 *mips32:
 440 *mips64:
 441 *vr4100:
 442 *vr5000:
 443 *r3900:
 444 {
 445   if (NotWordValue (GPR[RS]))
 446     Unpredictable ();
 447   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 448   {
 449     ALU32_BEGIN (GPR[RS]);
 450     ALU32_ADD (EXTEND16 (IMMEDIATE));
 451     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 452   }
 453   TRACE_ALU_RESULT (GPR[RT]);
 454 }
 455
 456
 457
 458 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 459 {
 460   if (NotWordValue (GPR[rs]))
 461     Unpredictable ();
 462   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 463   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 464   TRACE_ALU_RESULT (GPR[rt]);
 465 }
 466
 467 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 468 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 469 *mipsI:
 470 *mipsII:
 471 *mipsIII:
 472 *mipsIV:
 473 *mipsV:
 474 *mips32:
 475 *mips64:
 476 *vr4100:
 477 *vr5000:
 478 *r3900:
 479 {
 480   do_addiu (SD_, RS, RT, IMMEDIATE);
 481 }
 482
 483
 484
 485 :function:::void:do_addu:int rs, int rt, int rd
 486 {
 487   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 488     Unpredictable ();
 489   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 490   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 491   TRACE_ALU_RESULT (GPR[rd]);
 492 }
 493
 494 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 495 "addu r<RD>, r<RS>, r<RT>"
 496 *mipsI:
 497 *mipsII:
 498 *mipsIII:
 499 *mipsIV:
 500 *mipsV:
 501 *mips32:
 502 *mips64:
 503 *vr4100:
 504 *vr5000:
 505 *r3900:
 506 {
 507   do_addu (SD_, RS, RT, RD);
 508 }
 509
 510
 511
 512 :function:::void:do_and:int rs, int rt, int rd
 513 {
 514   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 515   GPR[rd] = GPR[rs] & GPR[rt];
 516   TRACE_ALU_RESULT (GPR[rd]);
 517 }
 518
 519 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 520 "and r<RD>, r<RS>, r<RT>"
 521 *mipsI:
 522 *mipsII:
 523 *mipsIII:
 524 *mipsIV:
 525 *mipsV:
 526 *mips32:
 527 *mips64:
 528 *vr4100:
 529 *vr5000:
 530 *r3900:
 531 {
 532   do_and (SD_, RS, RT, RD);
 533 }
 534
 535
 536
 537 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 538 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 539 *mipsI:
 540 *mipsII:
 541 *mipsIII:
 542 *mipsIV:
 543 *mipsV:
 544 *mips32:
 545 *mips64:
 546 *vr4100:
 547 *vr5000:
 548 *r3900:
 549 {
 550   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 551   GPR[RT] = GPR[RS] & IMMEDIATE;
 552   TRACE_ALU_RESULT (GPR[RT]);
 553 }
 554
 555
 556
 557 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 558 "beq r<RS>, r<RT>, <OFFSET>"
 559 *mipsI:
 560 *mipsII:
 561 *mipsIII:
 562 *mipsIV:
 563 *mipsV:
 564 *mips32:
 565 *mips64:
 566 *vr4100:
 567 *vr5000:
 568 *r3900:
 569 {
 570   address_word offset = EXTEND16 (OFFSET) << 2;
 571   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 572     {
 573       DELAY_SLOT (NIA + offset);
 574     }
 575 }
 576
 577
 578
 579 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 580 "beql r<RS>, r<RT>, <OFFSET>"
 581 *mipsII:
 582 *mipsIII:
 583 *mipsIV:
 584 *mipsV:
 585 *mips32:
 586 *mips64:
 587 *vr4100:
 588 *vr5000:
 589 *r3900:
 590 {
 591   address_word offset = EXTEND16 (OFFSET) << 2;
 592   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 593     {
 594       DELAY_SLOT (NIA + offset);
 595     }
 596   else
 597     NULLIFY_NEXT_INSTRUCTION ();
 598 }
 599
 600
 601
 602 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 603 "bgez r<RS>, <OFFSET>"
 604 *mipsI:
 605 *mipsII:
 606 *mipsIII:
 607 *mipsIV:
 608 *mipsV:
 609 *mips32:
 610 *mips64:
 611 *vr4100:
 612 *vr5000:
 613 *r3900:
 614 {
 615   address_word offset = EXTEND16 (OFFSET) << 2;
 616   if ((signed_word) GPR[RS] >= 0)
 617     {
 618       DELAY_SLOT (NIA + offset);
 619     }
 620 }
 621
 622
 623
 624 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 625 "bgezal r<RS>, <OFFSET>"
 626 *mipsI:
 627 *mipsII:
 628 *mipsIII:
 629 *mipsIV:
 630 *mipsV:
 631 *mips32:
 632 *mips64:
 633 *vr4100:
 634 *vr5000:
 635 *r3900:
 636 {
 637   address_word offset = EXTEND16 (OFFSET) << 2;
 638   if (RS == 31)
 639     Unpredictable ();
 640   RA = (CIA + 8);
 641   if ((signed_word) GPR[RS] >= 0)
 642     {
 643       DELAY_SLOT (NIA + offset);
 644     }
 645 }
 646
 647
 648
 649 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 650 "bgezall r<RS>, <OFFSET>"
 651 *mipsII:
 652 *mipsIII:
 653 *mipsIV:
 654 *mipsV:
 655 *mips32:
 656 *mips64:
 657 *vr4100:
 658 *vr5000:
 659 *r3900:
 660 {
 661   address_word offset = EXTEND16 (OFFSET) << 2;
 662   if (RS == 31)
 663     Unpredictable ();
 664   RA = (CIA + 8);
 665   /* NOTE: The branch occurs AFTER the next instruction has been
 666      executed */
 667   if ((signed_word) GPR[RS] >= 0)
 668     {
 669       DELAY_SLOT (NIA + offset);
 670     }
 671   else
 672     NULLIFY_NEXT_INSTRUCTION ();
 673 }
 674
 675
 676
 677 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 678 "bgezl r<RS>, <OFFSET>"
 679 *mipsII:
 680 *mipsIII:
 681 *mipsIV:
 682 *mipsV:
 683 *mips32:
 684 *mips64:
 685 *vr4100:
 686 *vr5000:
 687 *r3900:
 688 {
 689   address_word offset = EXTEND16 (OFFSET) << 2;
 690   if ((signed_word) GPR[RS] >= 0)
 691     {
 692       DELAY_SLOT (NIA + offset);
 693     }
 694   else
 695     NULLIFY_NEXT_INSTRUCTION ();
 696 }
 697
 698
 699
 700 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 701 "bgtz r<RS>, <OFFSET>"
 702 *mipsI:
 703 *mipsII:
 704 *mipsIII:
 705 *mipsIV:
 706 *mipsV:
 707 *mips32:
 708 *mips64:
 709 *vr4100:
 710 *vr5000:
 711 *r3900:
 712 {
 713   address_word offset = EXTEND16 (OFFSET) << 2;
 714   if ((signed_word) GPR[RS] > 0)
 715     {
 716       DELAY_SLOT (NIA + offset);
 717     }
 718 }
 719
 720
 721
 722 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 723 "bgtzl r<RS>, <OFFSET>"
 724 *mipsII:
 725 *mipsIII:
 726 *mipsIV:
 727 *mipsV:
 728 *mips32:
 729 *mips64:
 730 *vr4100:
 731 *vr5000:
 732 *r3900:
 733 {
 734   address_word offset = EXTEND16 (OFFSET) << 2;
 735   /* NOTE: The branch occurs AFTER the next instruction has been
 736      executed */
 737   if ((signed_word) GPR[RS] > 0)
 738     {
 739       DELAY_SLOT (NIA + offset);
 740     }
 741   else
 742     NULLIFY_NEXT_INSTRUCTION ();
 743 }
 744
 745
 746
 747 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 748 "blez r<RS>, <OFFSET>"
 749 *mipsI:
 750 *mipsII:
 751 *mipsIII:
 752 *mipsIV:
 753 *mipsV:
 754 *mips32:
 755 *mips64:
 756 *vr4100:
 757 *vr5000:
 758 *r3900:
 759 {
 760   address_word offset = EXTEND16 (OFFSET) << 2;
 761   /* NOTE: The branch occurs AFTER the next instruction has been
 762      executed */
 763   if ((signed_word) GPR[RS] <= 0)
 764     {
 765       DELAY_SLOT (NIA + offset);
 766     }
 767 }
 768
 769
 770
 771 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 772 "bgezl r<RS>, <OFFSET>"
 773 *mipsII:
 774 *mipsIII:
 775 *mipsIV:
 776 *mipsV:
 777 *mips32:
 778 *mips64:
 779 *vr4100:
 780 *vr5000:
 781 *r3900:
 782 {
 783   address_word offset = EXTEND16 (OFFSET) << 2;
 784   if ((signed_word) GPR[RS] <= 0)
 785     {
 786       DELAY_SLOT (NIA + offset);
 787     }
 788   else
 789     NULLIFY_NEXT_INSTRUCTION ();
 790 }
 791
 792
 793
 794 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 795 "bltz r<RS>, <OFFSET>"
 796 *mipsI:
 797 *mipsII:
 798 *mipsIII:
 799 *mipsIV:
 800 *mipsV:
 801 *mips32:
 802 *mips64:
 803 *vr4100:
 804 *vr5000:
 805 *r3900:
 806 {
 807   address_word offset = EXTEND16 (OFFSET) << 2;
 808   if ((signed_word) GPR[RS] < 0)
 809     {
 810       DELAY_SLOT (NIA + offset);
 811     }
 812 }
 813
 814
 815
 816 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 817 "bltzal r<RS>, <OFFSET>"
 818 *mipsI:
 819 *mipsII:
 820 *mipsIII:
 821 *mipsIV:
 822 *mipsV:
 823 *mips32:
 824 *mips64:
 825 *vr4100:
 826 *vr5000:
 827 *r3900:
 828 {
 829   address_word offset = EXTEND16 (OFFSET) << 2;
 830   if (RS == 31)
 831     Unpredictable ();
 832   RA = (CIA + 8);
 833   /* NOTE: The branch occurs AFTER the next instruction has been
 834      executed */
 835   if ((signed_word) GPR[RS] < 0)
 836     {
 837       DELAY_SLOT (NIA + offset);
 838     }
 839 }
 840
 841
 842
 843 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 844 "bltzall r<RS>, <OFFSET>"
 845 *mipsII:
 846 *mipsIII:
 847 *mipsIV:
 848 *mipsV:
 849 *mips32:
 850 *mips64:
 851 *vr4100:
 852 *vr5000:
 853 *r3900:
 854 {
 855   address_word offset = EXTEND16 (OFFSET) << 2;
 856   if (RS == 31)
 857     Unpredictable ();
 858   RA = (CIA + 8);
 859   if ((signed_word) GPR[RS] < 0)
 860     {
 861       DELAY_SLOT (NIA + offset);
 862     }
 863   else
 864     NULLIFY_NEXT_INSTRUCTION ();
 865 }
 866
 867
 868
 869 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 870 "bltzl r<RS>, <OFFSET>"
 871 *mipsII:
 872 *mipsIII:
 873 *mipsIV:
 874 *mipsV:
 875 *mips32:
 876 *mips64:
 877 *vr4100:
 878 *vr5000:
 879 *r3900:
 880 {
 881   address_word offset = EXTEND16 (OFFSET) << 2;
 882   /* NOTE: The branch occurs AFTER the next instruction has been
 883      executed */
 884   if ((signed_word) GPR[RS] < 0)
 885     {
 886       DELAY_SLOT (NIA + offset);
 887     }
 888   else
 889     NULLIFY_NEXT_INSTRUCTION ();
 890 }
 891
 892
 893
 894 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 895 "bne r<RS>, r<RT>, <OFFSET>"
 896 *mipsI:
 897 *mipsII:
 898 *mipsIII:
 899 *mipsIV:
 900 *mipsV:
 901 *mips32:
 902 *mips64:
 903 *vr4100:
 904 *vr5000:
 905 *r3900:
 906 {
 907   address_word offset = EXTEND16 (OFFSET) << 2;
 908   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 909     {
 910       DELAY_SLOT (NIA + offset);
 911     }
 912 }
 913
 914
 915
 916 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 917 "bnel r<RS>, r<RT>, <OFFSET>"
 918 *mipsII:
 919 *mipsIII:
 920 *mipsIV:
 921 *mipsV:
 922 *mips32:
 923 *mips64:
 924 *vr4100:
 925 *vr5000:
 926 *r3900:
 927 {
 928   address_word offset = EXTEND16 (OFFSET) << 2;
 929   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 930     {
 931       DELAY_SLOT (NIA + offset);
 932     }
 933   else
 934     NULLIFY_NEXT_INSTRUCTION ();
 935 }
 936
 937
 938
 939 000000,20.CODE,001101:SPECIAL:32::BREAK
 940 "break %#lx<CODE>"
 941 *mipsI:
 942 *mipsII:
 943 *mipsIII:
 944 *mipsIV:
 945 *mipsV:
 946 *mips32:
 947 *mips64:
 948 *vr4100:
 949 *vr5000:
 950 *r3900:
 951 {
 952   /* Check for some break instruction which are reserved for use by the simulator.  */
 953   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 954   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 955       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 956     {
 957       sim_engine_halt (SD, CPU, NULL, cia,
 958                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 959     }
 960   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 961            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 962     {
 963       if (STATE & simDELAYSLOT)
 964         PC = cia - 4; /* reference the branch instruction */
 965       else
 966         PC = cia;
 967       SignalException (BreakPoint, instruction_0);
 968     }
 969
 970   else
 971     {
 972       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 973          the exception. */
 974       SignalException (BreakPoint, instruction_0);
 975     }
 976 }
 977
 978
 979
 980 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
 981 "clo r<RD>, r<RS>"
 982 *mips32:
 983 *mips64:
 984 *vr5500:
 985 {
 986   unsigned32 temp = GPR[RS];
 987   unsigned32 i, mask;
 988   if (RT != RD)
 989     Unpredictable ();
 990   if (NotWordValue (GPR[RS]))
 991     Unpredictable ();
 992   TRACE_ALU_INPUT1 (GPR[RS]);
 993   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
 994     {
 995       if ((temp & mask) == 0)
 996         break;
 997       mask >>= 1;
 998     }
 999   GPR[RD] = EXTEND32 (i);
1000   TRACE_ALU_RESULT (GPR[RD]);
1001 }
1002
1003
1004
1005 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1006 "clz r<RD>, r<RS>"
1007 *mips32:
1008 *mips64:
1009 *vr5500:
1010 {
1011   unsigned32 temp = GPR[RS];
1012   unsigned32 i, mask;
1013   if (RT != RD)
1014     Unpredictable ();
1015   if (NotWordValue (GPR[RS]))
1016     Unpredictable ();
1017   TRACE_ALU_INPUT1 (GPR[RS]);
1018   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1019     {
1020       if ((temp & mask) != 0)
1021         break;
1022       mask >>= 1;
1023     }
1024   GPR[RD] = EXTEND32 (i);
1025   TRACE_ALU_RESULT (GPR[RD]);
1026 }
1027
1028
1029
1030 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1031 "dadd r<RD>, r<RS>, r<RT>"
1032 *mipsIII:
1033 *mipsIV:
1034 *mipsV:
1035 *mips64:
1036 *vr4100:
1037 *vr5000:
1038 {
1039   check_u64 (SD_, instruction_0);
1040   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1041   {
1042     ALU64_BEGIN (GPR[RS]);
1043     ALU64_ADD (GPR[RT]);
1044     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1045   }
1046   TRACE_ALU_RESULT (GPR[RD]);
1047 }
1048
1049
1050
1051 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1052 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1053 *mipsIII:
1054 *mipsIV:
1055 *mipsV:
1056 *mips64:
1057 *vr4100:
1058 *vr5000:
1059 {
1060   check_u64 (SD_, instruction_0);
1061   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1062   {
1063     ALU64_BEGIN (GPR[RS]);
1064     ALU64_ADD (EXTEND16 (IMMEDIATE));
1065     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1066   }
1067   TRACE_ALU_RESULT (GPR[RT]);
1068 }
1069
1070
1071
1072 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1073 {
1074   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1075   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1076   TRACE_ALU_RESULT (GPR[rt]);
1077 }
1078
1079 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1080 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1081 *mipsIII:
1082 *mipsIV:
1083 *mipsV:
1084 *mips64:
1085 *vr4100:
1086 *vr5000:
1087 {
1088   check_u64 (SD_, instruction_0);
1089   do_daddiu (SD_, RS, RT, IMMEDIATE);
1090 }
1091
1092
1093
1094 :function:::void:do_daddu:int rs, int rt, int rd
1095 {
1096   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1097   GPR[rd] = GPR[rs] + GPR[rt];
1098   TRACE_ALU_RESULT (GPR[rd]);
1099 }
1100
1101 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1102 "daddu r<RD>, r<RS>, r<RT>"
1103 *mipsIII:
1104 *mipsIV:
1105 *mipsV:
1106 *mips64:
1107 *vr4100:
1108 *vr5000:
1109 {
1110   check_u64 (SD_, instruction_0);
1111   do_daddu (SD_, RS, RT, RD);
1112 }
1113
1114
1115
1116 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1117 "dclo r<RD>, r<RS>"
1118 *mips64:
1119 *vr5500:
1120 {
1121   unsigned64 temp = GPR[RS];
1122   unsigned32 i;
1123   unsigned64 mask;
1124   check_u64 (SD_, instruction_0);
1125   if (RT != RD)
1126     Unpredictable ();
1127   TRACE_ALU_INPUT1 (GPR[RS]);
1128   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1129     {
1130       if ((temp & mask) == 0)
1131         break;
1132       mask >>= 1;
1133     }
1134   GPR[RD] = EXTEND32 (i);
1135   TRACE_ALU_RESULT (GPR[RD]);
1136 }
1137
1138
1139
1140 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1141 "dclz r<RD>, r<RS>"
1142 *mips64:
1143 *vr5500:
1144 {
1145   unsigned64 temp = GPR[RS];
1146   unsigned32 i;
1147   unsigned64 mask;
1148   check_u64 (SD_, instruction_0);
1149   if (RT != RD)
1150     Unpredictable ();
1151   TRACE_ALU_INPUT1 (GPR[RS]);
1152   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1153     {
1154       if ((temp & mask) != 0)
1155         break;
1156       mask >>= 1;
1157     }
1158   GPR[RD] = EXTEND32 (i);
1159   TRACE_ALU_RESULT (GPR[RD]);
1160 }
1161
1162
1163
1164 :function:::void:do_ddiv:int rs, int rt
1165 {
1166   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1167   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1168   {
1169     signed64 n = GPR[rs];
1170     signed64 d = GPR[rt];
1171     signed64 hi;
1172     signed64 lo;
1173     if (d == 0)
1174       {
1175         lo = SIGNED64 (0x8000000000000000);
1176         hi = 0;
1177       }
1178     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1179       {
1180         lo = SIGNED64 (0x8000000000000000);
1181         hi = 0;
1182       }
1183     else
1184       {
1185         lo = (n / d);
1186         hi = (n % d);
1187       }
1188     HI = hi;
1189     LO = lo;
1190   }
1191   TRACE_ALU_RESULT2 (HI, LO);
1192 }
1193
1194 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1195 "ddiv r<RS>, r<RT>"
1196 *mipsIII:
1197 *mipsIV:
1198 *mipsV:
1199 *mips64:
1200 *vr4100:
1201 *vr5000:
1202 {
1203   check_u64 (SD_, instruction_0);
1204   do_ddiv (SD_, RS, RT);
1205 }
1206
1207
1208
1209 :function:::void:do_ddivu:int rs, int rt
1210 {
1211   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1212   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1213   {
1214     unsigned64 n = GPR[rs];
1215     unsigned64 d = GPR[rt];
1216     unsigned64 hi;
1217     unsigned64 lo;
1218     if (d == 0)
1219       {
1220         lo = SIGNED64 (0x8000000000000000);
1221         hi = 0;
1222       }
1223     else
1224       {
1225         lo = (n / d);
1226         hi = (n % d);
1227       }
1228     HI = hi;
1229     LO = lo;
1230   }
1231   TRACE_ALU_RESULT2 (HI, LO);
1232 }
1233
1234 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1235 "ddivu r<RS>, r<RT>"
1236 *mipsIII:
1237 *mipsIV:
1238 *mipsV:
1239 *mips64:
1240 *vr4100:
1241 *vr5000:
1242 {
1243   check_u64 (SD_, instruction_0);
1244   do_ddivu (SD_, RS, RT);
1245 }
1246
1247
1248
1249 :function:::void:do_div:int rs, int rt
1250 {
1251   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1252   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1253   {
1254     signed32 n = GPR[rs];
1255     signed32 d = GPR[rt];
1256     if (d == 0)
1257       {
1258         LO = EXTEND32 (0x80000000);
1259         HI = EXTEND32 (0);
1260       }
1261     else if (n == SIGNED32 (0x80000000) && d == -1)
1262       {
1263         LO = EXTEND32 (0x80000000);
1264         HI = EXTEND32 (0);
1265       }
1266     else
1267       {
1268         LO = EXTEND32 (n / d);
1269         HI = EXTEND32 (n % d);
1270       }
1271   }
1272   TRACE_ALU_RESULT2 (HI, LO);
1273 }
1274
1275 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1276 "div r<RS>, r<RT>"
1277 *mipsI:
1278 *mipsII:
1279 *mipsIII:
1280 *mipsIV:
1281 *mipsV:
1282 *mips32:
1283 *mips64:
1284 *vr4100:
1285 *vr5000:
1286 *r3900:
1287 {
1288   do_div (SD_, RS, RT);
1289 }
1290
1291
1292
1293 :function:::void:do_divu:int rs, int rt
1294 {
1295   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1296   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1297   {
1298     unsigned32 n = GPR[rs];
1299     unsigned32 d = GPR[rt];
1300     if (d == 0)
1301       {
1302         LO = EXTEND32 (0x80000000);
1303         HI = EXTEND32 (0);
1304       }
1305     else
1306       {
1307         LO = EXTEND32 (n / d);
1308         HI = EXTEND32 (n % d);
1309       }
1310   }
1311   TRACE_ALU_RESULT2 (HI, LO);
1312 }
1313
1314 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1315 "divu r<RS>, r<RT>"
1316 *mipsI:
1317 *mipsII:
1318 *mipsIII:
1319 *mipsIV:
1320 *mipsV:
1321 *mips32:
1322 *mips64:
1323 *vr4100:
1324 *vr5000:
1325 *r3900:
1326 {
1327   do_divu (SD_, RS, RT);
1328 }
1329
1330
1331
1332 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1333 {
1334   unsigned64 lo;
1335   unsigned64 hi;
1336   unsigned64 m00;
1337   unsigned64 m01;
1338   unsigned64 m10;
1339   unsigned64 m11;
1340   unsigned64 mid;
1341   int sign;
1342   unsigned64 op1 = GPR[rs];
1343   unsigned64 op2 = GPR[rt];
1344   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1345   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1346   /* make signed multiply unsigned */
1347   sign = 0;
1348   if (signed_p)
1349     {
1350       if (op1 < 0)
1351         {
1352           op1 = - op1;
1353           ++sign;
1354         }
1355       if (op2 < 0)
1356         {
1357           op2 = - op2;
1358           ++sign;
1359         }
1360     }
1361   /* multiply out the 4 sub products */
1362   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1363   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1364   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1365   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1366   /* add the products */
1367   mid = ((unsigned64) VH4_8 (m00)
1368          + (unsigned64) VL4_8 (m10)
1369          + (unsigned64) VL4_8 (m01));
1370   lo = U8_4 (mid, m00);
1371   hi = (m11
1372         + (unsigned64) VH4_8 (mid)
1373         + (unsigned64) VH4_8 (m01)
1374         + (unsigned64) VH4_8 (m10));
1375   /* fix the sign */
1376   if (sign & 1)
1377     {
1378       lo = -lo;
1379       if (lo == 0)
1380         hi = -hi;
1381       else
1382         hi = -hi - 1;
1383     }
1384   /* save the result HI/LO (and a gpr) */
1385   LO = lo;
1386   HI = hi;
1387   if (rd != 0)
1388     GPR[rd] = lo;
1389   TRACE_ALU_RESULT2 (HI, LO);
1390 }
1391
1392 :function:::void:do_dmult:int rs, int rt, int rd
1393 {
1394   do_dmultx (SD_, rs, rt, rd, 1);
1395 }
1396
1397 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1398 "dmult r<RS>, r<RT>"
1399 *mipsIII:
1400 *mipsIV:
1401 *mipsV:
1402 *mips64:
1403 *vr4100:
1404 {
1405   check_u64 (SD_, instruction_0);
1406   do_dmult (SD_, RS, RT, 0);
1407 }
1408
1409 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1410 "dmult r<RS>, r<RT>":RD == 0
1411 "dmult r<RD>, r<RS>, r<RT>"
1412 *vr5000:
1413 {
1414   check_u64 (SD_, instruction_0);
1415   do_dmult (SD_, RS, RT, RD);
1416 }
1417
1418
1419
1420 :function:::void:do_dmultu:int rs, int rt, int rd
1421 {
1422   do_dmultx (SD_, rs, rt, rd, 0);
1423 }
1424
1425 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1426 "dmultu r<RS>, r<RT>"
1427 *mipsIII:
1428 *mipsIV:
1429 *mipsV:
1430 *mips64:
1431 *vr4100:
1432 {
1433   check_u64 (SD_, instruction_0);
1434   do_dmultu (SD_, RS, RT, 0);
1435 }
1436
1437 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1438 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1439 "dmultu r<RS>, r<RT>"
1440 *vr5000:
1441 {
1442   check_u64 (SD_, instruction_0);
1443   do_dmultu (SD_, RS, RT, RD);
1444 }
1445
1446 :function:::void:do_dsll:int rt, int rd, int shift
1447 {
1448   TRACE_ALU_INPUT2 (GPR[rt], shift);
1449   GPR[rd] = GPR[rt] << shift;
1450   TRACE_ALU_RESULT (GPR[rd]);
1451 }
1452
1453 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1454 "dsll r<RD>, r<RT>, <SHIFT>"
1455 *mipsIII:
1456 *mipsIV:
1457 *mipsV:
1458 *mips64:
1459 *vr4100:
1460 *vr5000:
1461 {
1462   check_u64 (SD_, instruction_0);
1463   do_dsll (SD_, RT, RD, SHIFT);
1464 }
1465
1466
1467 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1468 "dsll32 r<RD>, r<RT>, <SHIFT>"
1469 *mipsIII:
1470 *mipsIV:
1471 *mipsV:
1472 *mips64:
1473 *vr4100:
1474 *vr5000:
1475 {
1476   int s = 32 + SHIFT;
1477   check_u64 (SD_, instruction_0);
1478   TRACE_ALU_INPUT2 (GPR[RT], s);
1479   GPR[RD] = GPR[RT] << s;
1480   TRACE_ALU_RESULT (GPR[RD]);
1481 }
1482
1483 :function:::void:do_dsllv:int rs, int rt, int rd
1484 {
1485   int s = MASKED64 (GPR[rs], 5, 0);
1486   TRACE_ALU_INPUT2 (GPR[rt], s);
1487   GPR[rd] = GPR[rt] << s;
1488   TRACE_ALU_RESULT (GPR[rd]);
1489 }
1490
1491 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1492 "dsllv r<RD>, r<RT>, r<RS>"
1493 *mipsIII:
1494 *mipsIV:
1495 *mipsV:
1496 *mips64:
1497 *vr4100:
1498 *vr5000:
1499 {
1500   check_u64 (SD_, instruction_0);
1501   do_dsllv (SD_, RS, RT, RD);
1502 }
1503
1504 :function:::void:do_dsra:int rt, int rd, int shift
1505 {
1506   TRACE_ALU_INPUT2 (GPR[rt], shift);
1507   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1508   TRACE_ALU_RESULT (GPR[rd]);
1509 }
1510
1511
1512 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1513 "dsra r<RD>, r<RT>, <SHIFT>"
1514 *mipsIII:
1515 *mipsIV:
1516 *mipsV:
1517 *mips64:
1518 *vr4100:
1519 *vr5000:
1520 {
1521   check_u64 (SD_, instruction_0);
1522   do_dsra (SD_, RT, RD, SHIFT);
1523 }
1524
1525
1526 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1527 "dsra32 r<RD>, r<RT>, <SHIFT>"
1528 *mipsIII:
1529 *mipsIV:
1530 *mipsV:
1531 *mips64:
1532 *vr4100:
1533 *vr5000:
1534 {
1535   int s = 32 + SHIFT;
1536   check_u64 (SD_, instruction_0);
1537   TRACE_ALU_INPUT2 (GPR[RT], s);
1538   GPR[RD] = ((signed64) GPR[RT]) >> s;
1539   TRACE_ALU_RESULT (GPR[RD]);
1540 }
1541
1542
1543 :function:::void:do_dsrav:int rs, int rt, int rd
1544 {
1545   int s = MASKED64 (GPR[rs], 5, 0);
1546   TRACE_ALU_INPUT2 (GPR[rt], s);
1547   GPR[rd] = ((signed64) GPR[rt]) >> s;
1548   TRACE_ALU_RESULT (GPR[rd]);
1549 }
1550
1551 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1552 "dsrav r<RD>, r<RT>, r<RS>"
1553 *mipsIII:
1554 *mipsIV:
1555 *mipsV:
1556 *mips64:
1557 *vr4100:
1558 *vr5000:
1559 {
1560   check_u64 (SD_, instruction_0);
1561   do_dsrav (SD_, RS, RT, RD);
1562 }
1563
1564 :function:::void:do_dsrl:int rt, int rd, int shift
1565 {
1566   TRACE_ALU_INPUT2 (GPR[rt], shift);
1567   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1568   TRACE_ALU_RESULT (GPR[rd]);
1569 }
1570
1571
1572 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1573 "dsrl r<RD>, r<RT>, <SHIFT>"
1574 *mipsIII:
1575 *mipsIV:
1576 *mipsV:
1577 *mips64:
1578 *vr4100:
1579 *vr5000:
1580 {
1581   check_u64 (SD_, instruction_0);
1582   do_dsrl (SD_, RT, RD, SHIFT);
1583 }
1584
1585
1586 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1587 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1588 *mipsIII:
1589 *mipsIV:
1590 *mipsV:
1591 *mips64:
1592 *vr4100:
1593 *vr5000:
1594 {
1595   int s = 32 + SHIFT;
1596   check_u64 (SD_, instruction_0);
1597   TRACE_ALU_INPUT2 (GPR[RT], s);
1598   GPR[RD] = (unsigned64) GPR[RT] >> s;
1599   TRACE_ALU_RESULT (GPR[RD]);
1600 }
1601
1602
1603 :function:::void:do_dsrlv:int rs, int rt, int rd
1604 {
1605   int s = MASKED64 (GPR[rs], 5, 0);
1606   TRACE_ALU_INPUT2 (GPR[rt], s);
1607   GPR[rd] = (unsigned64) GPR[rt] >> s;
1608   TRACE_ALU_RESULT (GPR[rd]);
1609 }
1610
1611
1612
1613 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1614 "dsrlv r<RD>, r<RT>, r<RS>"
1615 *mipsIII:
1616 *mipsIV:
1617 *mipsV:
1618 *mips64:
1619 *vr4100:
1620 *vr5000:
1621 {
1622   check_u64 (SD_, instruction_0);
1623   do_dsrlv (SD_, RS, RT, RD);
1624 }
1625
1626
1627 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1628 "dsub r<RD>, r<RS>, r<RT>"
1629 *mipsIII:
1630 *mipsIV:
1631 *mipsV:
1632 *mips64:
1633 *vr4100:
1634 *vr5000:
1635 {
1636   check_u64 (SD_, instruction_0);
1637   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1638   {
1639     ALU64_BEGIN (GPR[RS]);
1640     ALU64_SUB (GPR[RT]);
1641     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1642   }
1643   TRACE_ALU_RESULT (GPR[RD]);
1644 }
1645
1646
1647 :function:::void:do_dsubu:int rs, int rt, int rd
1648 {
1649   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1650   GPR[rd] = GPR[rs] - GPR[rt];
1651   TRACE_ALU_RESULT (GPR[rd]);
1652 }
1653
1654 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1655 "dsubu r<RD>, r<RS>, r<RT>"
1656 *mipsIII:
1657 *mipsIV:
1658 *mipsV:
1659 *mips64:
1660 *vr4100:
1661 *vr5000:
1662 {
1663   check_u64 (SD_, instruction_0);
1664   do_dsubu (SD_, RS, RT, RD);
1665 }
1666
1667
1668 000010,26.INSTR_INDEX:NORMAL:32::J
1669 "j <INSTR_INDEX>"
1670 *mipsI:
1671 *mipsII:
1672 *mipsIII:
1673 *mipsIV:
1674 *mipsV:
1675 *mips32:
1676 *mips64:
1677 *vr4100:
1678 *vr5000:
1679 *r3900:
1680 {
1681   /* NOTE: The region used is that of the delay slot NIA and NOT the
1682      current instruction */
1683   address_word region = (NIA & MASK (63, 28));
1684   DELAY_SLOT (region | (INSTR_INDEX << 2));
1685 }
1686
1687
1688 000011,26.INSTR_INDEX:NORMAL:32::JAL
1689 "jal <INSTR_INDEX>"
1690 *mipsI:
1691 *mipsII:
1692 *mipsIII:
1693 *mipsIV:
1694 *mipsV:
1695 *mips32:
1696 *mips64:
1697 *vr4100:
1698 *vr5000:
1699 *r3900:
1700 {
1701   /* NOTE: The region used is that of the delay slot and NOT the
1702      current instruction */
1703   address_word region = (NIA & MASK (63, 28));
1704   GPR[31] = CIA + 8;
1705   DELAY_SLOT (region | (INSTR_INDEX << 2));
1706 }
1707
1708 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1709 "jalr r<RS>":RD == 31
1710 "jalr r<RD>, r<RS>"
1711 *mipsI:
1712 *mipsII:
1713 *mipsIII:
1714 *mipsIV:
1715 *mipsV:
1716 *mips32:
1717 *mips64:
1718 *vr4100:
1719 *vr5000:
1720 *r3900:
1721 {
1722   address_word temp = GPR[RS];
1723   GPR[RD] = CIA + 8;
1724   DELAY_SLOT (temp);
1725 }
1726
1727
1728 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1729 "jr r<RS>"
1730 *mipsI:
1731 *mipsII:
1732 *mipsIII:
1733 *mipsIV:
1734 *mipsV:
1735 *mips32:
1736 *mips64:
1737 *vr4100:
1738 *vr5000:
1739 *r3900:
1740 {
1741   DELAY_SLOT (GPR[RS]);
1742 }
1743
1744
1745 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1746 {
1747   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1748   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1749   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1750   unsigned int byte;
1751   address_word paddr;
1752   int uncached;
1753   unsigned64 memval;
1754   address_word vaddr;
1755
1756   vaddr = loadstore_ea (SD_, base, offset);
1757   if ((vaddr & access) != 0)
1758     {
1759       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1760     }
1761   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1762   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1763   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1764   byte = ((vaddr & mask) ^ bigendiancpu);
1765   return (memval >> (8 * byte));
1766 }
1767
1768 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1769 {
1770   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1771   address_word reverseendian = (ReverseEndian ? -1 : 0);
1772   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1773   unsigned int byte;
1774   unsigned int word;
1775   address_word paddr;
1776   int uncached;
1777   unsigned64 memval;
1778   address_word vaddr;
1779   int nr_lhs_bits;
1780   int nr_rhs_bits;
1781   unsigned_word lhs_mask;
1782   unsigned_word temp;
1783
1784   vaddr = loadstore_ea (SD_, base, offset);
1785   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1786   paddr = (paddr ^ (reverseendian & mask));
1787   if (BigEndianMem == 0)
1788     paddr = paddr & ~access;
1789
1790   /* compute where within the word/mem we are */
1791   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1792   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1793   nr_lhs_bits = 8 * byte + 8;
1794   nr_rhs_bits = 8 * access - 8 * byte;
1795   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1796
1797   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1798            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1799            (long) ((unsigned64) paddr >> 32), (long) paddr,
1800            word, byte, nr_lhs_bits, nr_rhs_bits); */
1801
1802   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1803   if (word == 0)
1804     {
1805       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1806       temp = (memval << nr_rhs_bits);
1807     }
1808   else
1809     {
1810       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1811       temp = (memval >> nr_lhs_bits);
1812     }
1813   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1814   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1815
1816   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1817            (long) ((unsigned64) memval >> 32), (long) memval,
1818            (long) ((unsigned64) temp >> 32), (long) temp,
1819            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1820            (long) (rt >> 32), (long) rt); */
1821   return rt;
1822 }
1823
1824 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1825 {
1826   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1827   address_word reverseendian = (ReverseEndian ? -1 : 0);
1828   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1829   unsigned int byte;
1830   address_word paddr;
1831   int uncached;
1832   unsigned64 memval;
1833   address_word vaddr;
1834
1835   vaddr = loadstore_ea (SD_, base, offset);
1836   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1837   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1838   paddr = (paddr ^ (reverseendian & mask));
1839   if (BigEndianMem != 0)
1840     paddr = paddr & ~access;
1841   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1842   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1843   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1844   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1845      (long) paddr, byte, (long) paddr, (long) memval); */
1846   {
1847     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1848     rt &= ~screen;
1849     rt |= (memval >> (8 * byte)) & screen;
1850   }
1851   return rt;
1852 }
1853
1854
1855 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1856 "lb r<RT>, <OFFSET>(r<BASE>)"
1857 *mipsI:
1858 *mipsII:
1859 *mipsIII:
1860 *mipsIV:
1861 *mipsV:
1862 *mips32:
1863 *mips64:
1864 *vr4100:
1865 *vr5000:
1866 *r3900:
1867 {
1868   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1869 }
1870
1871
1872 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1873 "lbu r<RT>, <OFFSET>(r<BASE>)"
1874 *mipsI:
1875 *mipsII:
1876 *mipsIII:
1877 *mipsIV:
1878 *mipsV:
1879 *mips32:
1880 *mips64:
1881 *vr4100:
1882 *vr5000:
1883 *r3900:
1884 {
1885   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1886 }
1887
1888
1889 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1890 "ld r<RT>, <OFFSET>(r<BASE>)"
1891 *mipsIII:
1892 *mipsIV:
1893 *mipsV:
1894 *mips64:
1895 *vr4100:
1896 *vr5000:
1897 {
1898   check_u64 (SD_, instruction_0);
1899   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1900 }
1901
1902
1903 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1904 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1905 *mipsII:
1906 *mipsIII:
1907 *mipsIV:
1908 *mipsV:
1909 *mips32:
1910 *mips64:
1911 *vr4100:
1912 *vr5000:
1913 *r3900:
1914 {
1915   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1916 }
1917
1918
1919
1920
1921 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1922 "ldl r<RT>, <OFFSET>(r<BASE>)"
1923 *mipsIII:
1924 *mipsIV:
1925 *mipsV:
1926 *mips64:
1927 *vr4100:
1928 *vr5000:
1929 {
1930   check_u64 (SD_, instruction_0);
1931   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1932 }
1933
1934
1935 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1936 "ldr r<RT>, <OFFSET>(r<BASE>)"
1937 *mipsIII:
1938 *mipsIV:
1939 *mipsV:
1940 *mips64:
1941 *vr4100:
1942 *vr5000:
1943 {
1944   check_u64 (SD_, instruction_0);
1945   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1946 }
1947
1948
1949 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1950 "lh r<RT>, <OFFSET>(r<BASE>)"
1951 *mipsI:
1952 *mipsII:
1953 *mipsIII:
1954 *mipsIV:
1955 *mipsV:
1956 *mips32:
1957 *mips64:
1958 *vr4100:
1959 *vr5000:
1960 *r3900:
1961 {
1962   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1963 }
1964
1965
1966 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1967 "lhu r<RT>, <OFFSET>(r<BASE>)"
1968 *mipsI:
1969 *mipsII:
1970 *mipsIII:
1971 *mipsIV:
1972 *mipsV:
1973 *mips32:
1974 *mips64:
1975 *vr4100:
1976 *vr5000:
1977 *r3900:
1978 {
1979   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1980 }
1981
1982
1983 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1984 "ll r<RT>, <OFFSET>(r<BASE>)"
1985 *mipsII:
1986 *mipsIII:
1987 *mipsIV:
1988 *mipsV:
1989 *mips32:
1990 *mips64:
1991 *vr4100:
1992 *vr5000:
1993 {
1994   address_word base = GPR[BASE];
1995   address_word offset = EXTEND16 (OFFSET);
1996   {
1997     address_word vaddr = loadstore_ea (SD_, base, offset);
1998     address_word paddr;
1999     int uncached;
2000     if ((vaddr & 3) != 0)
2001       {
2002         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2003       }
2004     else
2005       {
2006         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2007           {
2008             unsigned64 memval = 0;
2009             unsigned64 memval1 = 0;
2010             unsigned64 mask = 0x7;
2011             unsigned int shift = 2;
2012             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2013             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2014             unsigned int byte;
2015             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2016             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2017             byte = ((vaddr & mask) ^ (bigend << shift));
2018             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2019             LLBIT = 1;
2020           }
2021       }
2022   }
2023 }
2024
2025
2026 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2027 "lld r<RT>, <OFFSET>(r<BASE>)"
2028 *mipsIII:
2029 *mipsIV:
2030 *mipsV:
2031 *mips64:
2032 *vr4100:
2033 *vr5000:
2034 {
2035   address_word base = GPR[BASE];
2036   address_word offset = EXTEND16 (OFFSET);
2037   check_u64 (SD_, instruction_0);
2038   {
2039     address_word vaddr = loadstore_ea (SD_, base, offset);
2040     address_word paddr;
2041     int uncached;
2042     if ((vaddr & 7) != 0)
2043       {
2044         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2045       }
2046     else
2047       {
2048         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2049           {
2050             unsigned64 memval = 0;
2051             unsigned64 memval1 = 0;
2052             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2053             GPR[RT] = memval;
2054             LLBIT = 1;
2055           }
2056       }
2057   }
2058 }
2059
2060
2061 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2062 "lui r<RT>, %#lx<IMMEDIATE>"
2063 *mipsI:
2064 *mipsII:
2065 *mipsIII:
2066 *mipsIV:
2067 *mipsV:
2068 *mips32:
2069 *mips64:
2070 *vr4100:
2071 *vr5000:
2072 *r3900:
2073 {
2074   TRACE_ALU_INPUT1 (IMMEDIATE);
2075   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2076   TRACE_ALU_RESULT (GPR[RT]);
2077 }
2078
2079
2080 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2081 "lw r<RT>, <OFFSET>(r<BASE>)"
2082 *mipsI:
2083 *mipsII:
2084 *mipsIII:
2085 *mipsIV:
2086 *mipsV:
2087 *mips32:
2088 *mips64:
2089 *vr4100:
2090 *vr5000:
2091 *r3900:
2092 {
2093   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2094 }
2095
2096
2097 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2098 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2099 *mipsI:
2100 *mipsII:
2101 *mipsIII:
2102 *mipsIV:
2103 *mipsV:
2104 *mips32:
2105 *mips64:
2106 *vr4100:
2107 *vr5000:
2108 *r3900:
2109 {
2110   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2111 }
2112
2113
2114 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2115 "lwl r<RT>, <OFFSET>(r<BASE>)"
2116 *mipsI:
2117 *mipsII:
2118 *mipsIII:
2119 *mipsIV:
2120 *mipsV:
2121 *mips32:
2122 *mips64:
2123 *vr4100:
2124 *vr5000:
2125 *r3900:
2126 {
2127   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2128 }
2129
2130
2131 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2132 "lwr r<RT>, <OFFSET>(r<BASE>)"
2133 *mipsI:
2134 *mipsII:
2135 *mipsIII:
2136 *mipsIV:
2137 *mipsV:
2138 *mips32:
2139 *mips64:
2140 *vr4100:
2141 *vr5000:
2142 *r3900:
2143 {
2144   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2145 }
2146
2147
2148 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2149 "lwu r<RT>, <OFFSET>(r<BASE>)"
2150 *mipsIII:
2151 *mipsIV:
2152 *mipsV:
2153 *mips64:
2154 *vr4100:
2155 *vr5000:
2156 {
2157   check_u64 (SD_, instruction_0);
2158   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2159 }
2160
2161
2162
2163 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2164 "madd r<RS>, r<RT>"
2165 *mips32:
2166 *mips64:
2167 *vr5500:
2168 {
2169   signed64 temp;
2170   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2171   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2172     Unpredictable ();
2173   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2174   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2175           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2176   LO = EXTEND32 (temp);
2177   HI = EXTEND32 (VH4_8 (temp));
2178   TRACE_ALU_RESULT2 (HI, LO);
2179 }
2180
2181
2182
2183 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2184 "maddu r<RS>, r<RT>"
2185 *mips32:
2186 *mips64:
2187 *vr5500:
2188 {
2189   unsigned64 temp;
2190   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2191   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2192     Unpredictable ();
2193   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2194   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2195           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2196   LO = EXTEND32 (temp);
2197   HI = EXTEND32 (VH4_8 (temp));
2198   TRACE_ALU_RESULT2 (HI, LO);
2199 }
2200
2201
2202 :function:::void:do_mfhi:int rd
2203 {
2204   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2205   TRACE_ALU_INPUT1 (HI);
2206   GPR[rd] = HI;
2207   TRACE_ALU_RESULT (GPR[rd]);
2208 }
2209
2210 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2211 "mfhi r<RD>"
2212 *mipsI:
2213 *mipsII:
2214 *mipsIII:
2215 *mipsIV:
2216 *mipsV:
2217 *mips32:
2218 *mips64:
2219 *vr4100:
2220 *vr5000:
2221 *r3900:
2222 {
2223   do_mfhi (SD_, RD);
2224 }
2225
2226
2227
2228 :function:::void:do_mflo:int rd
2229 {
2230   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2231   TRACE_ALU_INPUT1 (LO);
2232   GPR[rd] = LO;
2233   TRACE_ALU_RESULT (GPR[rd]);
2234 }
2235
2236 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2237 "mflo r<RD>"
2238 *mipsI:
2239 *mipsII:
2240 *mipsIII:
2241 *mipsIV:
2242 *mipsV:
2243 *mips32:
2244 *mips64:
2245 *vr4100:
2246 *vr5000:
2247 *r3900:
2248 {
2249   do_mflo (SD_, RD);
2250 }
2251
2252
2253
2254 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2255 "movn r<RD>, r<RS>, r<RT>"
2256 *mipsIV:
2257 *mipsV:
2258 *mips32:
2259 *mips64:
2260 *vr5000:
2261 {
2262   if (GPR[RT] != 0)
2263     {
2264       GPR[RD] = GPR[RS];
2265       TRACE_ALU_RESULT (GPR[RD]);
2266     }
2267 }
2268
2269
2270
2271 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2272 "movz r<RD>, r<RS>, r<RT>"
2273 *mipsIV:
2274 *mipsV:
2275 *mips32:
2276 *mips64:
2277 *vr5000:
2278 {
2279   if (GPR[RT] == 0)
2280     {
2281       GPR[RD] = GPR[RS];
2282       TRACE_ALU_RESULT (GPR[RD]);
2283     }
2284 }
2285
2286
2287
2288 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2289 "msub r<RS>, r<RT>"
2290 *mips32:
2291 *mips64:
2292 *vr5500:
2293 {
2294   signed64 temp;
2295   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2296   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2297     Unpredictable ();
2298   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2299   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2300           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2301   LO = EXTEND32 (temp);
2302   HI = EXTEND32 (VH4_8 (temp));
2303   TRACE_ALU_RESULT2 (HI, LO);
2304 }
2305
2306
2307
2308 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2309 "msubu r<RS>, r<RT>"
2310 *mips32:
2311 *mips64:
2312 *vr5500:
2313 {
2314   unsigned64 temp;
2315   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2316   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2317     Unpredictable ();
2318   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2319   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2320           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2321   LO = EXTEND32 (temp);
2322   HI = EXTEND32 (VH4_8 (temp));
2323   TRACE_ALU_RESULT2 (HI, LO);
2324 }
2325
2326
2327
2328 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2329 "mthi r<RS>"
2330 *mipsI:
2331 *mipsII:
2332 *mipsIII:
2333 *mipsIV:
2334 *mipsV:
2335 *mips32:
2336 *mips64:
2337 *vr4100:
2338 *vr5000:
2339 *r3900:
2340 {
2341   check_mt_hilo (SD_, HIHISTORY);
2342   HI = GPR[RS];
2343 }
2344
2345
2346
2347 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2348 "mtlo r<RS>"
2349 *mipsI:
2350 *mipsII:
2351 *mipsIII:
2352 *mipsIV:
2353 *mipsV:
2354 *mips32:
2355 *mips64:
2356 *vr4100:
2357 *vr5000:
2358 *r3900:
2359 {
2360   check_mt_hilo (SD_, LOHISTORY);
2361   LO = GPR[RS];
2362 }
2363
2364
2365
2366 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2367 "mul r<RD>, r<RS>, r<RT>"
2368 *mips32:
2369 *mips64:
2370 *vr5500:
2371 {
2372   signed64 prod;
2373   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2374     Unpredictable ();
2375   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2376   prod = (((signed64)(signed32) GPR[RS])
2377           * ((signed64)(signed32) GPR[RT]));
2378   GPR[RD] = EXTEND32 (VL4_8 (prod));
2379   TRACE_ALU_RESULT (GPR[RD]);
2380 }
2381
2382
2383
2384 :function:::void:do_mult:int rs, int rt, int rd
2385 {
2386   signed64 prod;
2387   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2388   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2389     Unpredictable ();
2390   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2391   prod = (((signed64)(signed32) GPR[rs])
2392           * ((signed64)(signed32) GPR[rt]));
2393   LO = EXTEND32 (VL4_8 (prod));
2394   HI = EXTEND32 (VH4_8 (prod));
2395   if (rd != 0)
2396     GPR[rd] = LO;
2397   TRACE_ALU_RESULT2 (HI, LO);
2398 }
2399
2400 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2401 "mult r<RS>, r<RT>"
2402 *mipsI:
2403 *mipsII:
2404 *mipsIII:
2405 *mipsIV:
2406 *mipsV:
2407 *mips32:
2408 *mips64:
2409 *vr4100:
2410 {
2411   do_mult (SD_, RS, RT, 0);
2412 }
2413
2414
2415 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2416 "mult r<RS>, r<RT>":RD == 0
2417 "mult r<RD>, r<RS>, r<RT>"
2418 *vr5000:
2419 *r3900:
2420 {
2421   do_mult (SD_, RS, RT, RD);
2422 }
2423
2424
2425 :function:::void:do_multu:int rs, int rt, int rd
2426 {
2427   unsigned64 prod;
2428   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2429   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2430     Unpredictable ();
2431   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2432   prod = (((unsigned64)(unsigned32) GPR[rs])
2433           * ((unsigned64)(unsigned32) GPR[rt]));
2434   LO = EXTEND32 (VL4_8 (prod));
2435   HI = EXTEND32 (VH4_8 (prod));
2436   if (rd != 0)
2437     GPR[rd] = LO;
2438   TRACE_ALU_RESULT2 (HI, LO);
2439 }
2440
2441 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2442 "multu r<RS>, r<RT>"
2443 *mipsI:
2444 *mipsII:
2445 *mipsIII:
2446 *mipsIV:
2447 *mipsV:
2448 *mips32:
2449 *mips64:
2450 *vr4100:
2451 {
2452   do_multu (SD_, RS, RT, 0);
2453 }
2454
2455 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2456 "multu r<RS>, r<RT>":RD == 0
2457 "multu r<RD>, r<RS>, r<RT>"
2458 *vr5000:
2459 *r3900:
2460 {
2461   do_multu (SD_, RS, RT, RD);
2462 }
2463
2464
2465 :function:::void:do_nor:int rs, int rt, int rd
2466 {
2467   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2468   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2469   TRACE_ALU_RESULT (GPR[rd]);
2470 }
2471
2472 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2473 "nor r<RD>, r<RS>, r<RT>"
2474 *mipsI:
2475 *mipsII:
2476 *mipsIII:
2477 *mipsIV:
2478 *mipsV:
2479 *mips32:
2480 *mips64:
2481 *vr4100:
2482 *vr5000:
2483 *r3900:
2484 {
2485   do_nor (SD_, RS, RT, RD);
2486 }
2487
2488
2489 :function:::void:do_or:int rs, int rt, int rd
2490 {
2491   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2492   GPR[rd] = (GPR[rs] | GPR[rt]);
2493   TRACE_ALU_RESULT (GPR[rd]);
2494 }
2495
2496 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2497 "or r<RD>, r<RS>, r<RT>"
2498 *mipsI:
2499 *mipsII:
2500 *mipsIII:
2501 *mipsIV:
2502 *mipsV:
2503 *mips32:
2504 *mips64:
2505 *vr4100:
2506 *vr5000:
2507 *r3900:
2508 {
2509   do_or (SD_, RS, RT, RD);
2510 }
2511
2512
2513
2514 :function:::void:do_ori:int rs, int rt, unsigned immediate
2515 {
2516   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2517   GPR[rt] = (GPR[rs] | immediate);
2518   TRACE_ALU_RESULT (GPR[rt]);
2519 }
2520
2521 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2522 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2523 *mipsI:
2524 *mipsII:
2525 *mipsIII:
2526 *mipsIV:
2527 *mipsV:
2528 *mips32:
2529 *mips64:
2530 *vr4100:
2531 *vr5000:
2532 *r3900:
2533 {
2534   do_ori (SD_, RS, RT, IMMEDIATE);
2535 }
2536
2537
2538 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2539 "pref <HINT>, <OFFSET>(r<BASE>)"
2540 *mipsIV:
2541 *mipsV:
2542 *mips32:
2543 *mips64:
2544 *vr5000:
2545 {
2546   address_word base = GPR[BASE];
2547   address_word offset = EXTEND16 (OFFSET);
2548   {
2549     address_word vaddr = loadstore_ea (SD_, base, offset);
2550     address_word paddr;
2551     int uncached;
2552     {
2553       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2554         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2555     }
2556   }
2557 }
2558
2559
2560 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2561 {
2562   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2563   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2564   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2565   unsigned int byte;
2566   address_word paddr;
2567   int uncached;
2568   unsigned64 memval;
2569   address_word vaddr;
2570
2571   vaddr = loadstore_ea (SD_, base, offset);
2572   if ((vaddr & access) != 0)
2573     {
2574       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2575     }
2576   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2577   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2578   byte = ((vaddr & mask) ^ bigendiancpu);
2579   memval = (word << (8 * byte));
2580   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2581 }
2582
2583 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2584 {
2585   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2586   address_word reverseendian = (ReverseEndian ? -1 : 0);
2587   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2588   unsigned int byte;
2589   unsigned int word;
2590   address_word paddr;
2591   int uncached;
2592   unsigned64 memval;
2593   address_word vaddr;
2594   int nr_lhs_bits;
2595   int nr_rhs_bits;
2596
2597   vaddr = loadstore_ea (SD_, base, offset);
2598   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2599   paddr = (paddr ^ (reverseendian & mask));
2600   if (BigEndianMem == 0)
2601     paddr = paddr & ~access;
2602
2603   /* compute where within the word/mem we are */
2604   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2605   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2606   nr_lhs_bits = 8 * byte + 8;
2607   nr_rhs_bits = 8 * access - 8 * byte;
2608   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2609   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2610            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2611            (long) ((unsigned64) paddr >> 32), (long) paddr,
2612            word, byte, nr_lhs_bits, nr_rhs_bits); */
2613
2614   if (word == 0)
2615     {
2616       memval = (rt >> nr_rhs_bits);
2617     }
2618   else
2619     {
2620       memval = (rt << nr_lhs_bits);
2621     }
2622   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2623            (long) ((unsigned64) rt >> 32), (long) rt,
2624            (long) ((unsigned64) memval >> 32), (long) memval); */
2625   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2626 }
2627
2628 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2629 {
2630   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2631   address_word reverseendian = (ReverseEndian ? -1 : 0);
2632   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2633   unsigned int byte;
2634   address_word paddr;
2635   int uncached;
2636   unsigned64 memval;
2637   address_word vaddr;
2638
2639   vaddr = loadstore_ea (SD_, base, offset);
2640   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2641   paddr = (paddr ^ (reverseendian & mask));
2642   if (BigEndianMem != 0)
2643     paddr &= ~access;
2644   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2645   memval = (rt << (byte * 8));
2646   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2647 }
2648
2649
2650 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2651 "sb r<RT>, <OFFSET>(r<BASE>)"
2652 *mipsI:
2653 *mipsII:
2654 *mipsIII:
2655 *mipsIV:
2656 *mipsV:
2657 *mips32:
2658 *mips64:
2659 *vr4100:
2660 *vr5000:
2661 *r3900:
2662 {
2663   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2664 }
2665
2666
2667 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2668 "sc r<RT>, <OFFSET>(r<BASE>)"
2669 *mipsII:
2670 *mipsIII:
2671 *mipsIV:
2672 *mipsV:
2673 *mips32:
2674 *mips64:
2675 *vr4100:
2676 *vr5000:
2677 {
2678   unsigned32 instruction = instruction_0;
2679   address_word base = GPR[BASE];
2680   address_word offset = EXTEND16 (OFFSET);
2681   {
2682     address_word vaddr = loadstore_ea (SD_, base, offset);
2683     address_word paddr;
2684     int uncached;
2685     if ((vaddr & 3) != 0)
2686       {
2687         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2688       }
2689     else
2690       {
2691         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2692           {
2693             unsigned64 memval = 0;
2694             unsigned64 memval1 = 0;
2695             unsigned64 mask = 0x7;
2696             unsigned int byte;
2697             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2698             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2699             memval = ((unsigned64) GPR[RT] << (8 * byte));
2700             if (LLBIT)
2701               {
2702                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2703               }
2704             GPR[RT] = LLBIT;
2705           }
2706       }
2707   }
2708 }
2709
2710
2711 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2712 "scd r<RT>, <OFFSET>(r<BASE>)"
2713 *mipsIII:
2714 *mipsIV:
2715 *mipsV:
2716 *mips64:
2717 *vr4100:
2718 *vr5000:
2719 {
2720   address_word base = GPR[BASE];
2721   address_word offset = EXTEND16 (OFFSET);
2722   check_u64 (SD_, instruction_0);
2723   {
2724     address_word vaddr = loadstore_ea (SD_, base, offset);
2725     address_word paddr;
2726     int uncached;
2727     if ((vaddr & 7) != 0)
2728       {
2729         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2730       }
2731     else
2732       {
2733         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2734           {
2735             unsigned64 memval = 0;
2736             unsigned64 memval1 = 0;
2737             memval = GPR[RT];
2738             if (LLBIT)
2739               {
2740                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2741               }
2742             GPR[RT] = LLBIT;
2743           }
2744       }
2745   }
2746 }
2747
2748
2749 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2750 "sd r<RT>, <OFFSET>(r<BASE>)"
2751 *mipsIII:
2752 *mipsIV:
2753 *mipsV:
2754 *mips64:
2755 *vr4100:
2756 *vr5000:
2757 {
2758   check_u64 (SD_, instruction_0);
2759   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2760 }
2761
2762
2763 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2764 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2765 *mipsII:
2766 *mipsIII:
2767 *mipsIV:
2768 *mipsV:
2769 *mips32:
2770 *mips64:
2771 *vr4100:
2772 *vr5000:
2773 {
2774   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2775 }
2776
2777
2778 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2779 "sdl r<RT>, <OFFSET>(r<BASE>)"
2780 *mipsIII:
2781 *mipsIV:
2782 *mipsV:
2783 *mips64:
2784 *vr4100:
2785 *vr5000:
2786 {
2787   check_u64 (SD_, instruction_0);
2788   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2789 }
2790
2791
2792 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2793 "sdr r<RT>, <OFFSET>(r<BASE>)"
2794 *mipsIII:
2795 *mipsIV:
2796 *mipsV:
2797 *mips64:
2798 *vr4100:
2799 *vr5000:
2800 {
2801   check_u64 (SD_, instruction_0);
2802   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2803 }
2804
2805
2806 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2807 "sh r<RT>, <OFFSET>(r<BASE>)"
2808 *mipsI:
2809 *mipsII:
2810 *mipsIII:
2811 *mipsIV:
2812 *mipsV:
2813 *mips32:
2814 *mips64:
2815 *vr4100:
2816 *vr5000:
2817 *r3900:
2818 {
2819   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2820 }
2821
2822
2823 :function:::void:do_sll:int rt, int rd, int shift
2824 {
2825   unsigned32 temp = (GPR[rt] << shift);
2826   TRACE_ALU_INPUT2 (GPR[rt], shift);
2827   GPR[rd] = EXTEND32 (temp);
2828   TRACE_ALU_RESULT (GPR[rd]);
2829 }
2830
2831 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2832 "nop":RD == 0 && RT == 0 && SHIFT == 0
2833 "sll r<RD>, r<RT>, <SHIFT>"
2834 *mipsI:
2835 *mipsII:
2836 *mipsIII:
2837 *mipsIV:
2838 *mipsV:
2839 *vr4100:
2840 *vr5000:
2841 *r3900:
2842 {
2843   /* Skip shift for NOP, so that there won't be lots of extraneous
2844      trace output.  */
2845   if (RD != 0 || RT != 0 || SHIFT != 0)
2846     do_sll (SD_, RT, RD, SHIFT);
2847 }
2848
2849 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2850 "nop":RD == 0 && RT == 0 && SHIFT == 0
2851 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2852 "sll r<RD>, r<RT>, <SHIFT>"
2853 *mips32:
2854 *mips64:
2855 {
2856   /* Skip shift for NOP and SSNOP, so that there won't be lots of
2857      extraneous trace output.  */
2858   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2859     do_sll (SD_, RT, RD, SHIFT);
2860 }
2861
2862
2863 :function:::void:do_sllv:int rs, int rt, int rd
2864 {
2865   int s = MASKED (GPR[rs], 4, 0);
2866   unsigned32 temp = (GPR[rt] << s);
2867   TRACE_ALU_INPUT2 (GPR[rt], s);
2868   GPR[rd] = EXTEND32 (temp);
2869   TRACE_ALU_RESULT (GPR[rd]);
2870 }
2871
2872 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2873 "sllv r<RD>, r<RT>, r<RS>"
2874 *mipsI:
2875 *mipsII:
2876 *mipsIII:
2877 *mipsIV:
2878 *mipsV:
2879 *mips32:
2880 *mips64:
2881 *vr4100:
2882 *vr5000:
2883 *r3900:
2884 {
2885   do_sllv (SD_, RS, RT, RD);
2886 }
2887
2888
2889 :function:::void:do_slt:int rs, int rt, int rd
2890 {
2891   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2892   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2893   TRACE_ALU_RESULT (GPR[rd]);
2894 }
2895
2896 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2897 "slt r<RD>, r<RS>, r<RT>"
2898 *mipsI:
2899 *mipsII:
2900 *mipsIII:
2901 *mipsIV:
2902 *mipsV:
2903 *mips32:
2904 *mips64:
2905 *vr4100:
2906 *vr5000:
2907 *r3900:
2908 {
2909   do_slt (SD_, RS, RT, RD);
2910 }
2911
2912
2913 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2914 {
2915   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2916   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2917   TRACE_ALU_RESULT (GPR[rt]);
2918 }
2919
2920 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2921 "slti r<RT>, r<RS>, <IMMEDIATE>"
2922 *mipsI:
2923 *mipsII:
2924 *mipsIII:
2925 *mipsIV:
2926 *mipsV:
2927 *mips32:
2928 *mips64:
2929 *vr4100:
2930 *vr5000:
2931 *r3900:
2932 {
2933   do_slti (SD_, RS, RT, IMMEDIATE);
2934 }
2935
2936
2937 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2938 {
2939   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2940   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2941   TRACE_ALU_RESULT (GPR[rt]);
2942 }
2943
2944 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2945 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2946 *mipsI:
2947 *mipsII:
2948 *mipsIII:
2949 *mipsIV:
2950 *mipsV:
2951 *mips32:
2952 *mips64:
2953 *vr4100:
2954 *vr5000:
2955 *r3900:
2956 {
2957   do_sltiu (SD_, RS, RT, IMMEDIATE);
2958 }
2959
2960
2961
2962 :function:::void:do_sltu:int rs, int rt, int rd
2963 {
2964   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2965   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2966   TRACE_ALU_RESULT (GPR[rd]);
2967 }
2968
2969 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2970 "sltu r<RD>, r<RS>, r<RT>"
2971 *mipsI:
2972 *mipsII:
2973 *mipsIII:
2974 *mipsIV:
2975 *mipsV:
2976 *mips32:
2977 *mips64:
2978 *vr4100:
2979 *vr5000:
2980 *r3900:
2981 {
2982   do_sltu (SD_, RS, RT, RD);
2983 }
2984
2985
2986 :function:::void:do_sra:int rt, int rd, int shift
2987 {
2988   signed32 temp = (signed32) GPR[rt] >> shift;
2989   if (NotWordValue (GPR[rt]))
2990     Unpredictable ();
2991   TRACE_ALU_INPUT2 (GPR[rt], shift);
2992   GPR[rd] = EXTEND32 (temp);
2993   TRACE_ALU_RESULT (GPR[rd]);
2994 }
2995
2996 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2997 "sra r<RD>, r<RT>, <SHIFT>"
2998 *mipsI:
2999 *mipsII:
3000 *mipsIII:
3001 *mipsIV:
3002 *mipsV:
3003 *mips32:
3004 *mips64:
3005 *vr4100:
3006 *vr5000:
3007 *r3900:
3008 {
3009   do_sra (SD_, RT, RD, SHIFT);
3010 }
3011
3012
3013
3014 :function:::void:do_srav:int rs, int rt, int rd
3015 {
3016   int s = MASKED (GPR[rs], 4, 0);
3017   signed32 temp = (signed32) GPR[rt] >> s;
3018   if (NotWordValue (GPR[rt]))
3019     Unpredictable ();
3020   TRACE_ALU_INPUT2 (GPR[rt], s);
3021   GPR[rd] = EXTEND32 (temp);
3022   TRACE_ALU_RESULT (GPR[rd]);
3023 }
3024
3025 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3026 "srav r<RD>, r<RT>, r<RS>"
3027 *mipsI:
3028 *mipsII:
3029 *mipsIII:
3030 *mipsIV:
3031 *mipsV:
3032 *mips32:
3033 *mips64:
3034 *vr4100:
3035 *vr5000:
3036 *r3900:
3037 {
3038   do_srav (SD_, RS, RT, RD);
3039 }
3040
3041
3042
3043 :function:::void:do_srl:int rt, int rd, int shift
3044 {
3045   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3046   if (NotWordValue (GPR[rt]))
3047     Unpredictable ();
3048   TRACE_ALU_INPUT2 (GPR[rt], shift);
3049   GPR[rd] = EXTEND32 (temp);
3050   TRACE_ALU_RESULT (GPR[rd]);
3051 }
3052
3053 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3054 "srl r<RD>, r<RT>, <SHIFT>"
3055 *mipsI:
3056 *mipsII:
3057 *mipsIII:
3058 *mipsIV:
3059 *mipsV:
3060 *mips32:
3061 *mips64:
3062 *vr4100:
3063 *vr5000:
3064 *r3900:
3065 {
3066   do_srl (SD_, RT, RD, SHIFT);
3067 }
3068
3069
3070 :function:::void:do_srlv:int rs, int rt, int rd
3071 {
3072   int s = MASKED (GPR[rs], 4, 0);
3073   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3074   if (NotWordValue (GPR[rt]))
3075     Unpredictable ();
3076   TRACE_ALU_INPUT2 (GPR[rt], s);
3077   GPR[rd] = EXTEND32 (temp);
3078   TRACE_ALU_RESULT (GPR[rd]);
3079 }
3080
3081 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3082 "srlv r<RD>, r<RT>, r<RS>"
3083 *mipsI:
3084 *mipsII:
3085 *mipsIII:
3086 *mipsIV:
3087 *mipsV:
3088 *mips32:
3089 *mips64:
3090 *vr4100:
3091 *vr5000:
3092 *r3900:
3093 {
3094   do_srlv (SD_, RS, RT, RD);
3095 }
3096
3097
3098 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3099 "sub r<RD>, r<RS>, r<RT>"
3100 *mipsI:
3101 *mipsII:
3102 *mipsIII:
3103 *mipsIV:
3104 *mipsV:
3105 *mips32:
3106 *mips64:
3107 *vr4100:
3108 *vr5000:
3109 *r3900:
3110 {
3111   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3112     Unpredictable ();
3113   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3114   {
3115     ALU32_BEGIN (GPR[RS]);
3116     ALU32_SUB (GPR[RT]);
3117     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3118   }
3119   TRACE_ALU_RESULT (GPR[RD]);
3120 }
3121
3122
3123 :function:::void:do_subu:int rs, int rt, int rd
3124 {
3125   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3126     Unpredictable ();
3127   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3128   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3129   TRACE_ALU_RESULT (GPR[rd]);
3130 }
3131
3132 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3133 "subu r<RD>, r<RS>, r<RT>"
3134 *mipsI:
3135 *mipsII:
3136 *mipsIII:
3137 *mipsIV:
3138 *mipsV:
3139 *mips32:
3140 *mips64:
3141 *vr4100:
3142 *vr5000:
3143 *r3900:
3144 {
3145   do_subu (SD_, RS, RT, RD);
3146 }
3147
3148
3149 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3150 "sw r<RT>, <OFFSET>(r<BASE>)"
3151 *mipsI:
3152 *mipsII:
3153 *mipsIII:
3154 *mipsIV:
3155 *mipsV:
3156 *mips32:
3157 *mips64:
3158 *vr4100:
3159 *r3900:
3160 *vr5000:
3161 {
3162   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3163 }
3164
3165
3166 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3167 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3168 *mipsI:
3169 *mipsII:
3170 *mipsIII:
3171 *mipsIV:
3172 *mipsV:
3173 *mips32:
3174 *mips64:
3175 *vr4100:
3176 *vr5000:
3177 *r3900:
3178 {
3179   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3180 }
3181
3182
3183 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3184 "swl r<RT>, <OFFSET>(r<BASE>)"
3185 *mipsI:
3186 *mipsII:
3187 *mipsIII:
3188 *mipsIV:
3189 *mipsV:
3190 *mips32:
3191 *mips64:
3192 *vr4100:
3193 *vr5000:
3194 *r3900:
3195 {
3196   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3197 }
3198
3199
3200 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3201 "swr r<RT>, <OFFSET>(r<BASE>)"
3202 *mipsI:
3203 *mipsII:
3204 *mipsIII:
3205 *mipsIV:
3206 *mipsV:
3207 *mips32:
3208 *mips64:
3209 *vr4100:
3210 *vr5000:
3211 *r3900:
3212 {
3213   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3214 }
3215
3216
3217 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3218 "sync":STYPE == 0
3219 "sync <STYPE>"
3220 *mipsII:
3221 *mipsIII:
3222 *mipsIV:
3223 *mipsV:
3224 *mips32:
3225 *mips64:
3226 *vr4100:
3227 *vr5000:
3228 *r3900:
3229 {
3230   SyncOperation (STYPE);
3231 }
3232
3233
3234 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3235 "syscall %#lx<CODE>"
3236 *mipsI:
3237 *mipsII:
3238 *mipsIII:
3239 *mipsIV:
3240 *mipsV:
3241 *mips32:
3242 *mips64:
3243 *vr4100:
3244 *vr5000:
3245 *r3900:
3246 {
3247   SignalException (SystemCall, instruction_0);
3248 }
3249
3250
3251 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3252 "teq r<RS>, r<RT>"
3253 *mipsII:
3254 *mipsIII:
3255 *mipsIV:
3256 *mipsV:
3257 *mips32:
3258 *mips64:
3259 *vr4100:
3260 *vr5000:
3261 {
3262   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3263     SignalException (Trap, instruction_0);
3264 }
3265
3266
3267 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3268 "teqi r<RS>, <IMMEDIATE>"
3269 *mipsII:
3270 *mipsIII:
3271 *mipsIV:
3272 *mipsV:
3273 *mips32:
3274 *mips64:
3275 *vr4100:
3276 *vr5000:
3277 {
3278   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3279     SignalException (Trap, instruction_0);
3280 }
3281
3282
3283 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3284 "tge r<RS>, r<RT>"
3285 *mipsII:
3286 *mipsIII:
3287 *mipsIV:
3288 *mipsV:
3289 *mips32:
3290 *mips64:
3291 *vr4100:
3292 *vr5000:
3293 {
3294   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3295     SignalException (Trap, instruction_0);
3296 }
3297
3298
3299 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3300 "tgei r<RS>, <IMMEDIATE>"
3301 *mipsII:
3302 *mipsIII:
3303 *mipsIV:
3304 *mipsV:
3305 *mips32:
3306 *mips64:
3307 *vr4100:
3308 *vr5000:
3309 {
3310   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3311     SignalException (Trap, instruction_0);
3312 }
3313
3314
3315 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3316 "tgeiu r<RS>, <IMMEDIATE>"
3317 *mipsII:
3318 *mipsIII:
3319 *mipsIV:
3320 *mipsV:
3321 *mips32:
3322 *mips64:
3323 *vr4100:
3324 *vr5000:
3325 {
3326   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3327     SignalException (Trap, instruction_0);
3328 }
3329
3330
3331 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3332 "tgeu r<RS>, r<RT>"
3333 *mipsII:
3334 *mipsIII:
3335 *mipsIV:
3336 *mipsV:
3337 *mips32:
3338 *mips64:
3339 *vr4100:
3340 *vr5000:
3341 {
3342   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3343     SignalException (Trap, instruction_0);
3344 }
3345
3346
3347 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3348 "tlt r<RS>, r<RT>"
3349 *mipsII:
3350 *mipsIII:
3351 *mipsIV:
3352 *mipsV:
3353 *mips32:
3354 *mips64:
3355 *vr4100:
3356 *vr5000:
3357 {
3358   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3359     SignalException (Trap, instruction_0);
3360 }
3361
3362
3363 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3364 "tlti r<RS>, <IMMEDIATE>"
3365 *mipsII:
3366 *mipsIII:
3367 *mipsIV:
3368 *mipsV:
3369 *mips32:
3370 *mips64:
3371 *vr4100:
3372 *vr5000:
3373 {
3374   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3375     SignalException (Trap, instruction_0);
3376 }
3377
3378
3379 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3380 "tltiu r<RS>, <IMMEDIATE>"
3381 *mipsII:
3382 *mipsIII:
3383 *mipsIV:
3384 *mipsV:
3385 *mips32:
3386 *mips64:
3387 *vr4100:
3388 *vr5000:
3389 {
3390   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3391     SignalException (Trap, instruction_0);
3392 }
3393
3394
3395 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3396 "tltu r<RS>, r<RT>"
3397 *mipsII:
3398 *mipsIII:
3399 *mipsIV:
3400 *mipsV:
3401 *mips32:
3402 *mips64:
3403 *vr4100:
3404 *vr5000:
3405 {
3406   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3407     SignalException (Trap, instruction_0);
3408 }
3409
3410
3411 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3412 "tne r<RS>, r<RT>"
3413 *mipsII:
3414 *mipsIII:
3415 *mipsIV:
3416 *mipsV:
3417 *mips32:
3418 *mips64:
3419 *vr4100:
3420 *vr5000:
3421 {
3422   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3423     SignalException (Trap, instruction_0);
3424 }
3425
3426
3427 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3428 "tnei r<RS>, <IMMEDIATE>"
3429 *mipsII:
3430 *mipsIII:
3431 *mipsIV:
3432 *mipsV:
3433 *mips32:
3434 *mips64:
3435 *vr4100:
3436 *vr5000:
3437 {
3438   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3439     SignalException (Trap, instruction_0);
3440 }
3441
3442
3443 :function:::void:do_xor:int rs, int rt, int rd
3444 {
3445   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3446   GPR[rd] = GPR[rs] ^ GPR[rt];
3447   TRACE_ALU_RESULT (GPR[rd]);
3448 }
3449
3450 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3451 "xor r<RD>, r<RS>, r<RT>"
3452 *mipsI:
3453 *mipsII:
3454 *mipsIII:
3455 *mipsIV:
3456 *mipsV:
3457 *mips32:
3458 *mips64:
3459 *vr4100:
3460 *vr5000:
3461 *r3900:
3462 {
3463   do_xor (SD_, RS, RT, RD);
3464 }
3465
3466
3467 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3468 {
3469   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3470   GPR[rt] = GPR[rs] ^ immediate;
3471   TRACE_ALU_RESULT (GPR[rt]);
3472 }
3473
3474 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3475 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3476 *mipsI:
3477 *mipsII:
3478 *mipsIII:
3479 *mipsIV:
3480 *mipsV:
3481 *mips32:
3482 *mips64:
3483 *vr4100:
3484 *vr5000:
3485 *r3900:
3486 {
3487   do_xori (SD_, RS, RT, IMMEDIATE);
3488 }
3489
3490 \f
3491 //
3492 // MIPS Architecture:
3493 //
3494 //        FPU Instruction Set (COP1 & COP1X)
3495 //
3496
3497
3498 :%s::::FMT:int fmt
3499 {
3500   switch (fmt)
3501     {
3502     case fmt_single: return "s";
3503     case fmt_double: return "d";
3504     case fmt_word: return "w";
3505     case fmt_long: return "l";
3506     case fmt_ps: return "ps";
3507     default: return "?";
3508     }
3509 }
3510
3511 :%s::::TF:int tf
3512 {
3513   if (tf)
3514     return "t";
3515   else
3516     return "f";
3517 }
3518
3519 :%s::::ND:int nd
3520 {
3521   if (nd)
3522     return "l";
3523   else
3524     return "";
3525 }
3526
3527 :%s::::COND:int cond
3528 {
3529   switch (cond)
3530     {
3531     case 00: return "f";
3532     case 01: return "un";
3533     case 02: return "eq";
3534     case 03: return "ueq";
3535     case 04: return "olt";
3536     case 05: return "ult";
3537     case 06: return "ole";
3538     case 07: return "ule";
3539     case 010: return "sf";
3540     case 011: return "ngle";
3541     case 012: return "seq";
3542     case 013: return "ngl";
3543     case 014: return "lt";
3544     case 015: return "nge";
3545     case 016: return "le";
3546     case 017: return "ngt";
3547     default: return "?";
3548     }
3549 }
3550
3551
3552 // Helpers:
3553 //
3554 // Check that the given FPU format is usable, and signal a
3555 // ReservedInstruction exception if not.
3556 //
3557
3558 // check_fmt checks that the format is single or double.
3559 :function:::void:check_fmt:int fmt, instruction_word insn
3560 *mipsI:
3561 *mipsII:
3562 *mipsIII:
3563 *mipsIV:
3564 *mipsV:
3565 *mips32:
3566 *mips64:
3567 *vr4100:
3568 *vr5000:
3569 *r3900:
3570 {
3571   if ((fmt != fmt_single) && (fmt != fmt_double))
3572     SignalException (ReservedInstruction, insn);
3573 }
3574
3575 // check_fmt_p checks that the format is single, double, or paired single.
3576 :function:::void:check_fmt_p:int fmt, instruction_word insn
3577 *mipsI:
3578 *mipsII:
3579 *mipsIII:
3580 *mipsIV:
3581 *mips32:
3582 *vr4100:
3583 *vr5000:
3584 *r3900:
3585 {
3586   /* None of these ISAs support Paired Single, so just fall back to
3587      the single/double check.  */
3588   check_fmt (SD_, fmt, insn);
3589 }
3590
3591 :function:::void:check_fmt_p:int fmt, instruction_word insn
3592 *mipsV:
3593 *mips64:
3594 {
3595   if ((fmt != fmt_single) && (fmt != fmt_double)
3596       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3597     SignalException (ReservedInstruction, insn);
3598 }
3599
3600
3601 // Helper:
3602 //
3603 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3604 // exception if not.
3605 //
3606
3607 :function:::void:check_fpu:
3608 *mipsI:
3609 *mipsII:
3610 *mipsIII:
3611 *mipsIV:
3612 *mipsV:
3613 *mips32:
3614 *mips64:
3615 *vr4100:
3616 *vr5000:
3617 *r3900:
3618 {
3619   if (! COP_Usable (1))
3620     SignalExceptionCoProcessorUnusable (1);
3621 }
3622
3623
3624 // Helper:
3625 //
3626 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
3627 // or MIPS32.  do_load cannot be used instead because it returns an
3628 // unsigned_word, which is limited to the size of the machine's registers.
3629 //
3630
3631 :function:::unsigned64:do_load_double:address_word base, address_word offset
3632 *mipsII:
3633 *mips32:
3634 {
3635   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3636   address_word vaddr;
3637   address_word paddr;
3638   int uncached;
3639   unsigned64 memval;
3640   unsigned64 v;
3641
3642   vaddr = loadstore_ea (SD_, base, offset);
3643   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3644     {
3645       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
3646                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
3647                        sim_core_unaligned_signal);
3648     }
3649   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
3650                       isREAL);
3651   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
3652               isDATA, isREAL);
3653   v = (unsigned64)memval;
3654   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
3655               isDATA, isREAL);
3656   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
3657 }
3658
3659
3660 // Helper:
3661 //
3662 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
3663 // or MIPS32.  do_load cannot be used instead because it returns an
3664 // unsigned_word, which is limited to the size of the machine's registers.
3665 //
3666
3667 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
3668 *mipsII:
3669 *mips32:
3670 {
3671   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3672   address_word vaddr;
3673   address_word paddr;
3674   int uncached;
3675   unsigned64 memval;
3676
3677   vaddr = loadstore_ea (SD_, base, offset);
3678   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3679     {
3680       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
3681                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
3682                        sim_core_unaligned_signal);
3683     }
3684   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
3685                       isREAL);
3686   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
3687   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
3688                isREAL);
3689   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
3690   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
3691                isREAL);
3692 }
3693
3694
3695 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3696 "abs.%s<FMT> f<FD>, f<FS>"
3697 *mipsI:
3698 *mipsII:
3699 *mipsIII:
3700 *mipsIV:
3701 *mipsV:
3702 *mips32:
3703 *mips64:
3704 *vr4100:
3705 *vr5000:
3706 *r3900:
3707 {
3708   int fmt = FMT;
3709   check_fpu (SD_);
3710   check_fmt_p (SD_, fmt, instruction_0);
3711   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
3712 }
3713
3714
3715
3716 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3717 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3718 *mipsI:
3719 *mipsII:
3720 *mipsIII:
3721 *mipsIV:
3722 *mipsV:
3723 *mips32:
3724 *mips64:
3725 *vr4100:
3726 *vr5000:
3727 *r3900:
3728 {
3729   int fmt = FMT;
3730   check_fpu (SD_);
3731   check_fmt_p (SD_, fmt, instruction_0);
3732   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
3733 }
3734
3735
3736 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
3737 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
3738 *mipsV:
3739 *mips64:
3740 {
3741   unsigned64 fs;
3742   unsigned64 ft;
3743   unsigned64 fd;
3744   check_fpu (SD_);
3745   check_u64 (SD_, instruction_0);
3746   fs = ValueFPR (FS, fmt_ps);
3747   if ((GPR[RS] & 0x3) != 0)
3748     Unpredictable ();
3749   if ((GPR[RS] & 0x4) == 0)
3750     fd = fs;
3751   else
3752     {
3753       ft = ValueFPR (FT, fmt_ps);
3754       if (BigEndianCPU)
3755         fd = PackPS (PSLower (fs), PSUpper (ft));
3756       else
3757         fd = PackPS (PSLower (ft), PSUpper (fs));
3758     }
3759   StoreFPR (FD, fmt_ps, fd);
3760 }
3761
3762
3763 // BC1F
3764 // BC1FL
3765 // BC1T
3766 // BC1TL
3767
3768 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3769 "bc1%s<TF>%s<ND> <OFFSET>"
3770 *mipsI:
3771 *mipsII:
3772 *mipsIII:
3773 {
3774   check_fpu (SD_);
3775   TRACE_BRANCH_INPUT (PREVCOC1());
3776   if (PREVCOC1() == TF)
3777     {
3778       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3779       TRACE_BRANCH_RESULT (dest);
3780       DELAY_SLOT (dest);
3781     }
3782   else if (ND)
3783     {
3784       TRACE_BRANCH_RESULT (0);
3785       NULLIFY_NEXT_INSTRUCTION ();
3786     }
3787   else
3788     {
3789       TRACE_BRANCH_RESULT (NIA);
3790     }
3791 }
3792
3793 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3794 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3795 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3796 *mipsIV:
3797 *mipsV:
3798 *mips32:
3799 *mips64:
3800 #*vr4100:
3801 *vr5000:
3802 *r3900:
3803 {
3804   check_fpu (SD_);
3805   if (GETFCC(CC) == TF)
3806     {
3807       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3808       DELAY_SLOT (dest);
3809     }
3810   else if (ND)
3811     {
3812       NULLIFY_NEXT_INSTRUCTION ();
3813     }
3814 }
3815
3816
3817 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3818 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3819 *mipsI:
3820 *mipsII:
3821 *mipsIII:
3822 {
3823   int fmt = FMT;
3824   check_fpu (SD_);
3825   check_fmt_p (SD_, fmt, instruction_0);
3826   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
3827   TRACE_ALU_RESULT (ValueFCR (31));
3828 }
3829
3830 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3831 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3832 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3833 *mipsIV:
3834 *mipsV:
3835 *mips32:
3836 *mips64:
3837 *vr4100:
3838 *vr5000:
3839 *r3900:
3840 {
3841   int fmt = FMT;
3842   check_fpu (SD_);
3843   check_fmt_p (SD_, fmt, instruction_0);
3844   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
3845   TRACE_ALU_RESULT (ValueFCR (31));
3846 }
3847
3848
3849 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3850 "ceil.l.%s<FMT> f<FD>, f<FS>"
3851 *mipsIII:
3852 *mipsIV:
3853 *mipsV:
3854 *mips64:
3855 *vr4100:
3856 *vr5000:
3857 *r3900:
3858 {
3859   int fmt = FMT;
3860   check_fpu (SD_);
3861   check_fmt (SD_, fmt, instruction_0);
3862   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3863             fmt_long));
3864 }
3865
3866
3867 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3868 "ceil.w.%s<FMT> f<FD>, f<FS>"
3869 *mipsII:
3870 *mipsIII:
3871 *mipsIV:
3872 *mipsV:
3873 *mips32:
3874 *mips64:
3875 *vr4100:
3876 *vr5000:
3877 *r3900:
3878 {
3879   int fmt = FMT;
3880   check_fpu (SD_);
3881   check_fmt (SD_, fmt, instruction_0);
3882   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3883             fmt_word));
3884 }
3885
3886
3887 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
3888 "cfc1 r<RT>, f<FS>"
3889 *mipsI:
3890 *mipsII:
3891 *mipsIII:
3892 {
3893   check_fpu (SD_);
3894   if (FS == 0)
3895     PENDING_FILL (RT, EXTEND32 (FCR0));
3896   else if (FS == 31)
3897     PENDING_FILL (RT, EXTEND32 (FCR31));
3898   /* else NOP */
3899 }
3900
3901 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
3902 "cfc1 r<RT>, f<FS>"
3903 *mipsIV:
3904 *vr4100:
3905 *vr5000:
3906 *r3900:
3907 {
3908   check_fpu (SD_);
3909   if (FS == 0 || FS == 31)
3910     {
3911       unsigned_word  fcr = ValueFCR (FS);
3912       TRACE_ALU_INPUT1 (fcr);
3913       GPR[RT] = fcr;
3914     }
3915   /* else NOP */
3916   TRACE_ALU_RESULT (GPR[RT]);
3917 }
3918
3919 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
3920 "cfc1 r<RT>, f<FS>"
3921 *mipsV:
3922 *mips32:
3923 *mips64:
3924 {
3925   check_fpu (SD_);
3926   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
3927     {
3928       unsigned_word  fcr = ValueFCR (FS);
3929       TRACE_ALU_INPUT1 (fcr);
3930       GPR[RT] = fcr;
3931     }
3932   /* else NOP */
3933   TRACE_ALU_RESULT (GPR[RT]);
3934 }
3935
3936 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
3937 "ctc1 r<RT>, f<FS>"
3938 *mipsI:
3939 *mipsII:
3940 *mipsIII:
3941 {
3942   check_fpu (SD_);
3943   if (FS == 31)
3944     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
3945   /* else NOP */
3946 }
3947
3948 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
3949 "ctc1 r<RT>, f<FS>"
3950 *mipsIV:
3951 *vr4100:
3952 *vr5000:
3953 *r3900:
3954 {
3955   check_fpu (SD_);
3956   TRACE_ALU_INPUT1 (GPR[RT]);
3957   if (FS == 31)
3958     StoreFCR (FS, GPR[RT]);
3959   /* else NOP */
3960 }
3961
3962 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
3963 "ctc1 r<RT>, f<FS>"
3964 *mipsV:
3965 *mips32:
3966 *mips64:
3967 {
3968   check_fpu (SD_);
3969   TRACE_ALU_INPUT1 (GPR[RT]);
3970   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
3971       StoreFCR (FS, GPR[RT]);
3972   /* else NOP */
3973 }
3974
3975
3976 //
3977 // FIXME: Does not correctly differentiate between mips*
3978 //
3979 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3980 "cvt.d.%s<FMT> f<FD>, f<FS>"
3981 *mipsI:
3982 *mipsII:
3983 *mipsIII:
3984 *mipsIV:
3985 *mipsV:
3986 *mips32:
3987 *mips64:
3988 *vr4100:
3989 *vr5000:
3990 *r3900:
3991 {
3992   int fmt = FMT;
3993   check_fpu (SD_);
3994   if ((fmt == fmt_double) | 0)
3995     SignalException (ReservedInstruction, instruction_0);
3996   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
3997             fmt_double));
3998 }
3999
4000
4001 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4002 "cvt.l.%s<FMT> f<FD>, f<FS>"
4003 *mipsIII:
4004 *mipsIV:
4005 *mipsV:
4006 *mips64:
4007 *vr4100:
4008 *vr5000:
4009 *r3900:
4010 {
4011   int fmt = FMT;
4012   check_fpu (SD_);
4013   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4014     SignalException (ReservedInstruction, instruction_0);
4015   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4016             fmt_long));
4017 }
4018
4019
4020 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4021 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4022 *mipsV:
4023 *mips64:
4024 {
4025   check_fpu (SD_);
4026   check_u64 (SD_, instruction_0);
4027   StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4028                                 ValueFPR (FT, fmt_single)));
4029 }
4030
4031
4032 //
4033 // FIXME: Does not correctly differentiate between mips*
4034 //
4035 010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4036 "cvt.s.%s<FMT> f<FD>, f<FS>"
4037 *mipsI:
4038 *mipsII:
4039 *mipsIII:
4040 *mipsIV:
4041 *mipsV:
4042 *mips32:
4043 *mips64:
4044 *vr4100:
4045 *vr5000:
4046 *r3900:
4047 {
4048   int fmt = FMT;
4049   check_fpu (SD_);
4050   if ((fmt == fmt_single) | 0)
4051     SignalException (ReservedInstruction, instruction_0);
4052   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4053             fmt_single));
4054 }
4055
4056
4057 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4058 "cvt.s.pl f<FD>, f<FS>"
4059 *mipsV:
4060 *mips64:
4061 {
4062   check_fpu (SD_);
4063   check_u64 (SD_, instruction_0);
4064   StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4065 }
4066
4067
4068 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4069 "cvt.s.pu f<FD>, f<FS>"
4070 *mipsV:
4071 *mips64:
4072 {
4073   check_fpu (SD_);
4074   check_u64 (SD_, instruction_0);
4075   StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4076 }
4077
4078
4079 010001,10,3.FMT!6,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4080 "cvt.w.%s<FMT> f<FD>, f<FS>"
4081 *mipsI:
4082 *mipsII:
4083 *mipsIII:
4084 *mipsIV:
4085 *mipsV:
4086 *mips32:
4087 *mips64:
4088 *vr4100:
4089 *vr5000:
4090 *r3900:
4091 {
4092   int fmt = FMT;
4093   check_fpu (SD_);
4094   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4095     SignalException (ReservedInstruction, instruction_0);
4096   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4097             fmt_word));
4098 }
4099
4100
4101 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4102 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4103 *mipsI:
4104 *mipsII:
4105 *mipsIII:
4106 *mipsIV:
4107 *mipsV:
4108 *mips32:
4109 *mips64:
4110 *vr4100:
4111 *vr5000:
4112 *r3900:
4113 {
4114   int fmt = FMT;
4115   check_fpu (SD_);
4116   check_fmt (SD_, fmt, instruction_0);
4117   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4118 }
4119
4120
4121 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4122 "dmfc1 r<RT>, f<FS>"
4123 *mipsIII:
4124 {
4125   unsigned64 v;
4126   check_fpu (SD_);
4127   check_u64 (SD_, instruction_0);
4128   if (SizeFGR () == 64)
4129     v = FGR[FS];
4130   else if ((FS & 0x1) == 0)
4131     v = SET64HI (FGR[FS+1]) | FGR[FS];
4132   else
4133     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4134   PENDING_FILL (RT, v);
4135   TRACE_ALU_RESULT (v);
4136 }
4137
4138 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4139 "dmfc1 r<RT>, f<FS>"
4140 *mipsIV:
4141 *mipsV:
4142 *mips64:
4143 *vr4100:
4144 *vr5000:
4145 *r3900:
4146 {
4147   check_fpu (SD_);
4148   check_u64 (SD_, instruction_0);
4149   if (SizeFGR () == 64)
4150     GPR[RT] = FGR[FS];
4151   else if ((FS & 0x1) == 0)
4152     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4153   else
4154     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4155   TRACE_ALU_RESULT (GPR[RT]);
4156 }
4157
4158
4159 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4160 "dmtc1 r<RT>, f<FS>"
4161 *mipsIII:
4162 {
4163   unsigned64 v;
4164   check_fpu (SD_);
4165   check_u64 (SD_, instruction_0);
4166   if (SizeFGR () == 64)
4167     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4168   else if ((FS & 0x1) == 0)
4169     {
4170       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4171       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4172     }
4173   else
4174     Unpredictable ();
4175   TRACE_FP_RESULT (GPR[RT]);
4176 }
4177
4178 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4179 "dmtc1 r<RT>, f<FS>"
4180 *mipsIV:
4181 *mipsV:
4182 *mips64:
4183 *vr4100:
4184 *vr5000:
4185 *r3900:
4186 {
4187   check_fpu (SD_);
4188   check_u64 (SD_, instruction_0);
4189   if (SizeFGR () == 64)
4190     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4191   else if ((FS & 0x1) == 0)
4192     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4193   else
4194     Unpredictable ();
4195 }
4196
4197
4198 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4199 "floor.l.%s<FMT> f<FD>, f<FS>"
4200 *mipsIII:
4201 *mipsIV:
4202 *mipsV:
4203 *mips64:
4204 *vr4100:
4205 *vr5000:
4206 *r3900:
4207 {
4208   int fmt = FMT;
4209   check_fpu (SD_);
4210   check_fmt (SD_, fmt, instruction_0);
4211   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4212             fmt_long));
4213 }
4214
4215
4216 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4217 "floor.w.%s<FMT> f<FD>, f<FS>"
4218 *mipsII:
4219 *mipsIII:
4220 *mipsIV:
4221 *mipsV:
4222 *mips32:
4223 *mips64:
4224 *vr4100:
4225 *vr5000:
4226 *r3900:
4227 {
4228   int fmt = FMT;
4229   check_fpu (SD_);
4230   check_fmt (SD_, fmt, instruction_0);
4231   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4232             fmt_word));
4233 }
4234
4235
4236 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4237 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4238 *mipsII:
4239 *mips32:
4240 {
4241   check_fpu (SD_);
4242   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4243 }
4244
4245
4246 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4247 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4248 *mipsIII:
4249 *mipsIV:
4250 *mipsV:
4251 *mips64:
4252 *vr4100:
4253 *vr5000:
4254 *r3900:
4255 {
4256   check_fpu (SD_);
4257   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4258 }
4259
4260
4261 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4262 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4263 *mipsIV:
4264 *mipsV:
4265 *mips64:
4266 *vr5000:
4267 {
4268   check_fpu (SD_);
4269   check_u64 (SD_, instruction_0);
4270   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4271 }
4272
4273
4274
4275 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4276 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4277 *mipsI:
4278 *mipsII:
4279 *mipsIII:
4280 *mipsIV:
4281 *mipsV:
4282 *mips32:
4283 *mips64:
4284 *vr4100:
4285 *vr5000:
4286 *r3900:
4287 {
4288   check_fpu (SD_);
4289   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4290 }
4291
4292
4293 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4294 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4295 *mipsIV:
4296 *mipsV:
4297 *mips64:
4298 *vr5000:
4299 {
4300   check_fpu (SD_);
4301   check_u64 (SD_, instruction_0);
4302   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4303 }
4304
4305
4306
4307 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
4308 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4309 *mipsIV:
4310 *mipsV:
4311 *mips64:
4312 *vr5000:
4313 {
4314   int fmt = FMT;
4315   check_fpu (SD_);
4316   check_u64 (SD_, instruction_0);
4317   check_fmt_p (SD_, fmt, instruction_0);
4318   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4319                                   ValueFPR (FR, fmt), fmt));
4320 }
4321
4322
4323 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4324 "mfc1 r<RT>, f<FS>"
4325 *mipsI:
4326 *mipsII:
4327 *mipsIII:
4328 {
4329   unsigned64 v;
4330   check_fpu (SD_);
4331   v = EXTEND32 (FGR[FS]);
4332   PENDING_FILL (RT, v);
4333   TRACE_ALU_RESULT (v);
4334 }
4335
4336 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4337 "mfc1 r<RT>, f<FS>"
4338 *mipsIV:
4339 *mipsV:
4340 *mips32:
4341 *mips64:
4342 *vr4100:
4343 *vr5000:
4344 *r3900:
4345 {
4346   check_fpu (SD_);
4347   GPR[RT] = EXTEND32 (FGR[FS]);
4348   TRACE_ALU_RESULT (GPR[RT]);
4349 }
4350
4351
4352 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4353 "mov.%s<FMT> f<FD>, f<FS>"
4354 *mipsI:
4355 *mipsII:
4356 *mipsIII:
4357 *mipsIV:
4358 *mipsV:
4359 *mips32:
4360 *mips64:
4361 *vr4100:
4362 *vr5000:
4363 *r3900:
4364 {
4365   int fmt = FMT;
4366   check_fpu (SD_);
4367   check_fmt_p (SD_, fmt, instruction_0);
4368   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4369 }
4370
4371
4372 // MOVF
4373 // MOVT
4374 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4375 "mov%s<TF> r<RD>, r<RS>, <CC>"
4376 *mipsIV:
4377 *mipsV:
4378 *mips32:
4379 *mips64:
4380 *vr5000:
4381 {
4382   check_fpu (SD_);
4383   if (GETFCC(CC) == TF)
4384     GPR[RD] = GPR[RS];
4385 }
4386
4387
4388 // MOVF.fmt
4389 // MOVT.fmt
4390 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4391 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4392 *mipsIV:
4393 *mipsV:
4394 *mips32:
4395 *mips64:
4396 *vr5000:
4397 {
4398   int fmt = FMT;
4399   check_fpu (SD_);
4400   if (fmt != fmt_ps)
4401     {
4402       if (GETFCC(CC) == TF)
4403         StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4404       else
4405         StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
4406     }
4407   else
4408     {
4409       unsigned64 fd;
4410       fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4411                                       fmt_ps)),
4412                    PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4413                                       fmt_ps)));
4414       StoreFPR (FD, fmt_ps, fd);
4415     }
4416 }
4417
4418
4419 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4420 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4421 *mipsIV:
4422 *mipsV:
4423 *mips32:
4424 *mips64:
4425 *vr5000:
4426 {
4427   check_fpu (SD_);
4428   if (GPR[RT] != 0)
4429     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4430   else
4431     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4432 }
4433
4434
4435 // MOVT see MOVtf
4436
4437
4438 // MOVT.fmt see MOVtf.fmt
4439
4440
4441
4442 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4443 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4444 *mipsIV:
4445 *mipsV:
4446 *mips32:
4447 *mips64:
4448 *vr5000:
4449 {
4450   check_fpu (SD_);
4451   if (GPR[RT] == 0)
4452     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4453   else
4454     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4455 }
4456
4457
4458 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
4459 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4460 *mipsIV:
4461 *mipsV:
4462 *mips64:
4463 *vr5000:
4464 {
4465   int fmt = FMT;
4466   check_fpu (SD_);
4467   check_u64 (SD_, instruction_0);
4468   check_fmt_p (SD_, fmt, instruction_0);
4469   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4470                                   ValueFPR (FR, fmt), fmt));
4471 }
4472
4473
4474 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4475 "mtc1 r<RT>, f<FS>"
4476 *mipsI:
4477 *mipsII:
4478 *mipsIII:
4479 {
4480   check_fpu (SD_);
4481   if (SizeFGR () == 64)
4482     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4483   else
4484     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4485   TRACE_FP_RESULT (GPR[RT]);
4486 }
4487
4488 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4489 "mtc1 r<RT>, f<FS>"
4490 *mipsIV:
4491 *mipsV:
4492 *mips32:
4493 *mips64:
4494 *vr4100:
4495 *vr5000:
4496 *r3900:
4497 {
4498   check_fpu (SD_);
4499   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4500 }
4501
4502
4503 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4504 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4505 *mipsI:
4506 *mipsII:
4507 *mipsIII:
4508 *mipsIV:
4509 *mipsV:
4510 *mips32:
4511 *mips64:
4512 *vr4100:
4513 *vr5000:
4514 *r3900:
4515 {
4516   int fmt = FMT;
4517   check_fpu (SD_);
4518   check_fmt_p (SD_, fmt, instruction_0);
4519   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4520 }
4521
4522
4523 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4524 "neg.%s<FMT> f<FD>, f<FS>"
4525 *mipsI:
4526 *mipsII:
4527 *mipsIII:
4528 *mipsIV:
4529 *mipsV:
4530 *mips32:
4531 *mips64:
4532 *vr4100:
4533 *vr5000:
4534 *r3900:
4535 {
4536   int fmt = FMT;
4537   check_fpu (SD_);
4538   check_fmt_p (SD_, fmt, instruction_0);
4539   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4540 }
4541
4542
4543 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
4544 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4545 *mipsIV:
4546 *mipsV:
4547 *mips64:
4548 *vr5000:
4549 {
4550   int fmt = FMT;
4551   check_fpu (SD_);
4552   check_u64 (SD_, instruction_0);
4553   check_fmt_p (SD_, fmt, instruction_0);
4554   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4555                                      ValueFPR (FR, fmt), fmt));
4556 }
4557
4558
4559 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
4560 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4561 *mipsIV:
4562 *mipsV:
4563 *mips64:
4564 *vr5000:
4565 {
4566   int fmt = FMT;
4567   check_fpu (SD_);
4568   check_u64 (SD_, instruction_0);
4569   check_fmt_p (SD_, fmt, instruction_0);
4570   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4571                                      ValueFPR (FR, fmt), fmt));
4572 }
4573
4574
4575 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
4576 "pll.ps f<FD>, f<FS>, f<FT>"
4577 *mipsV:
4578 *mips64:
4579 {
4580   check_fpu (SD_);
4581   check_u64 (SD_, instruction_0);
4582   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4583                                 PSLower (ValueFPR (FT, fmt_ps))));
4584 }
4585
4586
4587 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
4588 "plu.ps f<FD>, f<FS>, f<FT>"
4589 *mipsV:
4590 *mips64:
4591 {
4592   check_fpu (SD_);
4593   check_u64 (SD_, instruction_0);
4594   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4595                                 PSUpper (ValueFPR (FT, fmt_ps))));
4596 }
4597
4598
4599 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4600 "prefx <HINT>, r<INDEX>(r<BASE>)"
4601 *mipsIV:
4602 *mipsV:
4603 *mips64:
4604 *vr5000:
4605 {
4606   address_word base = GPR[BASE];
4607   address_word index = GPR[INDEX];
4608   {
4609     address_word vaddr = loadstore_ea (SD_, base, index);
4610     address_word paddr;
4611     int uncached;
4612     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4613       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4614   }
4615 }
4616
4617
4618 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
4619 "pul.ps f<FD>, f<FS>, f<FT>"
4620 *mipsV:
4621 *mips64:
4622 {
4623   check_fpu (SD_);
4624   check_u64 (SD_, instruction_0);
4625   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4626                                 PSLower (ValueFPR (FT, fmt_ps))));
4627 }
4628
4629
4630 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
4631 "puu.ps f<FD>, f<FS>, f<FT>"
4632 *mipsV:
4633 *mips64:
4634 {
4635   check_fpu (SD_);
4636   check_u64 (SD_, instruction_0);
4637   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4638                                 PSUpper (ValueFPR (FT, fmt_ps))));
4639 }
4640
4641
4642 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4643 "recip.%s<FMT> f<FD>, f<FS>"
4644 *mipsIV:
4645 *mipsV:
4646 *mips64:
4647 *vr5000:
4648 {
4649   int fmt = FMT;
4650   check_fpu (SD_);
4651   check_fmt (SD_, fmt, instruction_0);
4652   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
4653 }
4654
4655
4656 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4657 "round.l.%s<FMT> f<FD>, f<FS>"
4658 *mipsIII:
4659 *mipsIV:
4660 *mipsV:
4661 *mips64:
4662 *vr4100:
4663 *vr5000:
4664 *r3900:
4665 {
4666   int fmt = FMT;
4667   check_fpu (SD_);
4668   check_fmt (SD_, fmt, instruction_0);
4669   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4670             fmt_long));
4671 }
4672
4673
4674 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4675 "round.w.%s<FMT> f<FD>, f<FS>"
4676 *mipsII:
4677 *mipsIII:
4678 *mipsIV:
4679 *mipsV:
4680 *mips32:
4681 *mips64:
4682 *vr4100:
4683 *vr5000:
4684 *r3900:
4685 {
4686   int fmt = FMT;
4687   check_fpu (SD_);
4688   check_fmt (SD_, fmt, instruction_0);
4689   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4690             fmt_word));
4691 }
4692
4693
4694 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4695 "rsqrt.%s<FMT> f<FD>, f<FS>"
4696 *mipsIV:
4697 *mipsV:
4698 *mips64:
4699 *vr5000:
4700 {
4701   int fmt = FMT;
4702   check_fpu (SD_);
4703   check_fmt (SD_, fmt, instruction_0);
4704   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
4705 }
4706
4707
4708 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
4709 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4710 *mipsII:
4711 *mips32:
4712 {
4713   check_fpu (SD_);
4714   do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4715 }
4716
4717
4718 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
4719 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4720 *mipsIII:
4721 *mipsIV:
4722 *mipsV:
4723 *mips64:
4724 *vr4100:
4725 *vr5000:
4726 *r3900:
4727 {
4728   check_fpu (SD_);
4729   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4730 }
4731
4732
4733 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4734 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4735 *mipsIV:
4736 *mipsV:
4737 *mips64:
4738 *vr5000:
4739 {
4740   check_fpu (SD_);
4741   check_u64 (SD_, instruction_0);
4742   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4743 }
4744
4745
4746 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4747 "sqrt.%s<FMT> f<FD>, f<FS>"
4748 *mipsII:
4749 *mipsIII:
4750 *mipsIV:
4751 *mipsV:
4752 *mips32:
4753 *mips64:
4754 *vr4100:
4755 *vr5000:
4756 *r3900:
4757 {
4758   int fmt = FMT;
4759   check_fpu (SD_);
4760   check_fmt (SD_, fmt, instruction_0);
4761   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
4762 }
4763
4764
4765 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4766 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4767 *mipsI:
4768 *mipsII:
4769 *mipsIII:
4770 *mipsIV:
4771 *mipsV:
4772 *mips32:
4773 *mips64:
4774 *vr4100:
4775 *vr5000:
4776 *r3900:
4777 {
4778   int fmt = FMT;
4779   check_fpu (SD_);
4780   check_fmt_p (SD_, fmt, instruction_0);
4781   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4782 }
4783
4784
4785
4786 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4787 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4788 *mipsI:
4789 *mipsII:
4790 *mipsIII:
4791 *mipsIV:
4792 *mipsV:
4793 *mips32:
4794 *mips64:
4795 *vr4100:
4796 *vr5000:
4797 *r3900:
4798 {
4799   address_word base = GPR[BASE];
4800   address_word offset = EXTEND16 (OFFSET);
4801   check_fpu (SD_);
4802   {
4803     address_word vaddr = loadstore_ea (SD_, base, offset);
4804     address_word paddr;
4805     int uncached;
4806     if ((vaddr & 3) != 0)
4807       {
4808         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4809       }
4810     else
4811       {
4812         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4813           {
4814             uword64 memval = 0;
4815             uword64 memval1 = 0;
4816             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4817             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4818             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4819             unsigned int byte;
4820             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4821             byte = ((vaddr & mask) ^ bigendiancpu);
4822             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4823             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4824           }
4825       }
4826   }
4827 }
4828
4829
4830 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4831 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4832 *mipsIV:
4833 *mipsV:
4834 *mips64:
4835 *vr5000:
4836 {
4837
4838   address_word base = GPR[BASE];
4839   address_word index = GPR[INDEX];
4840   check_fpu (SD_);
4841   check_u64 (SD_, instruction_0);
4842   {
4843    address_word vaddr = loadstore_ea (SD_, base, index);
4844    address_word paddr;
4845    int uncached;
4846    if ((vaddr & 3) != 0)
4847      {
4848        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4849      }
4850    else
4851    {
4852     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4853     {
4854      unsigned64 memval = 0;
4855      unsigned64 memval1 = 0;
4856      unsigned64 mask = 0x7;
4857      unsigned int byte;
4858      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4859      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4860      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4861       {
4862        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4863       }
4864     }
4865    }
4866   }
4867 }
4868
4869
4870 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4871 "trunc.l.%s<FMT> f<FD>, f<FS>"
4872 *mipsIII:
4873 *mipsIV:
4874 *mipsV:
4875 *mips64:
4876 *vr4100:
4877 *vr5000:
4878 *r3900:
4879 {
4880   int fmt = FMT;
4881   check_fpu (SD_);
4882   check_fmt (SD_, fmt, instruction_0);
4883   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4884             fmt_long));
4885 }
4886
4887
4888 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4889 "trunc.w.%s<FMT> f<FD>, f<FS>"
4890 *mipsII:
4891 *mipsIII:
4892 *mipsIV:
4893 *mipsV:
4894 *mips32:
4895 *mips64:
4896 *vr4100:
4897 *vr5000:
4898 *r3900:
4899 {
4900   int fmt = FMT;
4901   check_fpu (SD_);
4902   check_fmt (SD_, fmt, instruction_0);
4903   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4904             fmt_word));
4905 }
4906
4907 \f
4908 //
4909 // MIPS Architecture:
4910 //
4911 //        System Control Instruction Set (COP0)
4912 //
4913
4914
4915 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4916 "bc0f <OFFSET>"
4917 *mipsI:
4918 *mipsII:
4919 *mipsIII:
4920 *mipsIV:
4921 *mipsV:
4922 *mips32:
4923 *mips64:
4924 *vr4100:
4925 *vr5000:
4926
4927 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4928 "bc0f <OFFSET>"
4929 // stub needed for eCos as tx39 hardware bug workaround
4930 *r3900:
4931 {
4932   /* do nothing */
4933 }
4934
4935
4936 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4937 "bc0fl <OFFSET>"
4938 *mipsI:
4939 *mipsII:
4940 *mipsIII:
4941 *mipsIV:
4942 *mipsV:
4943 *mips32:
4944 *mips64:
4945 *vr4100:
4946 *vr5000:
4947
4948
4949 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4950 "bc0t <OFFSET>"
4951 *mipsI:
4952 *mipsII:
4953 *mipsIII:
4954 *mipsIV:
4955 *mipsV:
4956 *mips32:
4957 *mips64:
4958 *vr4100:
4959
4960
4961 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4962 "bc0tl <OFFSET>"
4963 *mipsI:
4964 *mipsII:
4965 *mipsIII:
4966 *mipsIV:
4967 *mipsV:
4968 *mips32:
4969 *mips64:
4970 *vr4100:
4971 *vr5000:
4972
4973
4974 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4975 "cache <OP>, <OFFSET>(r<BASE>)"
4976 *mipsIII:
4977 *mipsIV:
4978 *mipsV:
4979 *mips32:
4980 *mips64:
4981 *vr4100:
4982 *vr5000:
4983 *r3900:
4984 {
4985   address_word base = GPR[BASE];
4986   address_word offset = EXTEND16 (OFFSET);
4987   {
4988     address_word vaddr = loadstore_ea (SD_, base, offset);
4989     address_word paddr;
4990     int uncached;
4991     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4992       CacheOp(OP,vaddr,paddr,instruction_0);
4993   }
4994 }
4995
4996
4997 010000,1,0000000000000000000,111001:COP0:32::DI
4998 "di"
4999 *mipsI:
5000 *mipsII:
5001 *mipsIII:
5002 *mipsIV:
5003 *mipsV:
5004 *vr4100:
5005 *vr5000:
5006
5007
5008 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5009 "dmfc0 r<RT>, r<RD>"
5010 *mipsIII:
5011 *mipsIV:
5012 *mipsV:
5013 *mips64:
5014 {
5015   check_u64 (SD_, instruction_0);
5016   DecodeCoproc (instruction_0);
5017 }
5018
5019
5020 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5021 "dmtc0 r<RT>, r<RD>"
5022 *mipsIII:
5023 *mipsIV:
5024 *mipsV:
5025 *mips64:
5026 {
5027   check_u64 (SD_, instruction_0);
5028   DecodeCoproc (instruction_0);
5029 }
5030
5031
5032 010000,1,0000000000000000000,111000:COP0:32::EI
5033 "ei"
5034 *mipsI:
5035 *mipsII:
5036 *mipsIII:
5037 *mipsIV:
5038 *mipsV:
5039 *mips64:
5040 *vr4100:
5041 *vr5000:
5042
5043
5044 010000,1,0000000000000000000,011000:COP0:32::ERET
5045 "eret"
5046 *mipsIII:
5047 *mipsIV:
5048 *mipsV:
5049 *mips32:
5050 *mips64:
5051 *vr4100:
5052 *vr5000:
5053 {
5054   if (SR & status_ERL)
5055     {
5056       /* Oops, not yet available */
5057       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5058       NIA = EPC;
5059       SR &= ~status_ERL;
5060     }
5061   else
5062     {
5063       NIA = EPC;
5064       SR &= ~status_EXL;
5065     }
5066 }
5067
5068
5069 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5070 "mfc0 r<RT>, r<RD> # <REGX>"
5071 *mipsI:
5072 *mipsII:
5073 *mipsIII:
5074 *mipsIV:
5075 *mipsV:
5076 *mips32:
5077 *mips64:
5078 *vr4100:
5079 *vr5000:
5080 *r3900:
5081 {
5082   TRACE_ALU_INPUT0 ();
5083   DecodeCoproc (instruction_0);
5084   TRACE_ALU_RESULT (GPR[RT]);
5085 }
5086
5087 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5088 "mtc0 r<RT>, r<RD> # <REGX>"
5089 *mipsI:
5090 *mipsII:
5091 *mipsIII:
5092 *mipsIV:
5093 *mipsV:
5094 *mips32:
5095 *mips64:
5096 *vr4100:
5097 *vr5000:
5098 *r3900:
5099 {
5100   DecodeCoproc (instruction_0);
5101 }
5102
5103
5104 010000,1,0000000000000000000,010000:COP0:32::RFE
5105 "rfe"
5106 *mipsI:
5107 *mipsII:
5108 *mipsIII:
5109 *mipsIV:
5110 *mipsV:
5111 *vr4100:
5112 *vr5000:
5113 *r3900:
5114 {
5115   DecodeCoproc (instruction_0);
5116 }
5117
5118
5119 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5120 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5121 *mipsI:
5122 *mipsII:
5123 *mipsIII:
5124 *mipsIV:
5125 *mipsV:
5126 *mips32:
5127 *mips64:
5128 *vr4100:
5129 *r3900:
5130 {
5131   DecodeCoproc (instruction_0);
5132 }
5133
5134
5135
5136 010000,1,0000000000000000000,001000:COP0:32::TLBP
5137 "tlbp"
5138 *mipsI:
5139 *mipsII:
5140 *mipsIII:
5141 *mipsIV:
5142 *mipsV:
5143 *mips32:
5144 *mips64:
5145 *vr4100:
5146 *vr5000:
5147
5148
5149 010000,1,0000000000000000000,000001:COP0:32::TLBR
5150 "tlbr"
5151 *mipsI:
5152 *mipsII:
5153 *mipsIII:
5154 *mipsIV:
5155 *mipsV:
5156 *mips32:
5157 *mips64:
5158 *vr4100:
5159 *vr5000:
5160
5161
5162 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5163 "tlbwi"
5164 *mipsI:
5165 *mipsII:
5166 *mipsIII:
5167 *mipsIV:
5168 *mipsV:
5169 *mips32:
5170 *mips64:
5171 *vr4100:
5172 *vr5000:
5173
5174
5175 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5176 "tlbwr"
5177 *mipsI:
5178 *mipsII:
5179 *mipsIII:
5180 *mipsIV:
5181 *mipsV:
5182 *mips32:
5183 *mips64:
5184 *vr4100:
5185 *vr5000:
5186
5187 \f
5188 :include:::m16.igen
5189 :include:::mdmx.igen
5190 :include:::mips3d.igen
5191 :include:::sb1.igen
5192 :include:::tx.igen
5193 :include:::vr.igen
5194 \f