3 // In mips.igen, the semantics for many of the instructions were created
4 // using code generated by gencode. Those semantic segments could be
8 // <insn-word> { "+" <insn-word> }
15 // { <insn-mnemonic> }
20 // IGEN config - mips16
21 // :option:16::insn-bit-size:16
22 // :option:16::hi-bit-nr:15
23 :option:16::insn-specifying-widths:true
24 :option:16::gen-delayed-branch:false
26 // IGEN config - mips32/64..
27 // :option:32::insn-bit-size:32
28 // :option:32::hi-bit-nr:31
29 :option:32::insn-specifying-widths:true
30 :option:32::gen-delayed-branch:false
33 // Generate separate simulators for each target
34 // :option:::multi-sim:true
37 // Models known by this simulator
38 :model:::mipsI:mips3000:
39 :model:::mipsII:mips6000:
40 :model:::mipsIII:mips4000:
41 :model:::mipsIV:mips8000:
42 :model:::mips16:mips16:
43 // start-sanitize-r5900
44 :model:::r5900:mips5900:
46 :model:::r3900:mips3900:
47 // start-sanitize-tx19
50 :model:::vr4100:mips4100:
51 // start-sanitize-vr4xxx
52 :model:::vr4121:mips4121:
53 // end-sanitize-vr4xxx
54 // start-sanitize-vr4320
55 :model:::vr4320:mips4320:
56 // end-sanitize-vr4320
57 // start-sanitize-cygnus
58 :model:::vr5400:mips5400:
60 // end-sanitize-cygnus
61 :model:::vr5000:mips5000:
65 // Pseudo instructions known by IGEN
68 SignalException (ReservedInstruction, 0);
72 // Pseudo instructions known by interp.c
73 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
74 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
77 SignalException (ReservedInstruction, instruction_0);
84 // Simulate a 32 bit delayslot instruction
87 :function:::address_word:delayslot32:address_word target
89 instruction_word delay_insn;
90 sim_events_slip (SD, 1);
92 CIA = CIA + 4; /* NOTE not mips16 */
93 STATE |= simDELAYSLOT;
94 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
95 idecode_issue (CPU_, delay_insn, (CIA));
96 STATE &= ~simDELAYSLOT;
100 :function:::address_word:nullify_next_insn32:
102 sim_events_slip (SD, 1);
103 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
107 // start-sanitize-branchbug4011
108 :function:::void:check_4011_branch_bug:
110 if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
111 sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
112 itable[MY_INDEX].name,
114 (long) BRANCHBUG4011_LAST_CIA);
117 :function:::void:mark_4011_branch_bug:address_word target
119 if (BRANCHBUG4011_OPTION)
121 BRANCHBUG4011_OPTION = 2;
122 BRANCHBUG4011_LAST_TARGET = target;
123 BRANCHBUG4011_LAST_CIA = CIA;
127 // end-sanitize-branchbug4011
130 // Check that an access to a HI/LO register meets timing requirements
132 // The following requirements exist:
134 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
135 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
136 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
137 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
140 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
142 if (history->mf.timestamp + 3 > time)
144 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
145 itable[MY_INDEX].name,
147 (long) history->mf.cia);
153 :function:::int:check_mt_hilo:hilo_history *history
154 *mipsI,mipsII,mipsIII,mipsIV:
157 // start-sanitize-vr4xxx
159 // end-sanitize-vr4xxx
160 // start-sanitize-vr4320
162 // end-sanitize-vr4320
163 // start-sanitize-cygnus
165 // end-sanitize-cygnus
167 signed64 time = sim_events_time (SD);
168 int ok = check_mf_cycles (SD_, history, time, "MT");
169 history->mt.timestamp = time;
170 history->mt.cia = CIA;
174 :function:::int:check_mt_hilo:hilo_history *history
176 // start-sanitize-tx19
179 // start-sanitize-r5900
181 // end-sanitize-r5900
183 signed64 time = sim_events_time (SD);
184 history->mt.timestamp = time;
185 history->mt.cia = CIA;
190 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
191 *mipsI,mipsII,mipsIII,mipsIV:
194 // start-sanitize-vr4xxx
196 // end-sanitize-vr4xxx
197 // start-sanitize-vr4320
199 // end-sanitize-vr4320
200 // start-sanitize-cygnus
202 // end-sanitize-cygnus
204 // start-sanitize-tx19
208 signed64 time = sim_events_time (SD);
211 && peer->mt.timestamp > history->op.timestamp
212 && history->mt.timestamp < history->op.timestamp
213 && ! (history->mf.timestamp > history->op.timestamp
214 && history->mf.timestamp < peer->mt.timestamp)
215 && ! (peer->mf.timestamp > history->op.timestamp
216 && peer->mf.timestamp < peer->mt.timestamp))
218 /* The peer has been written to since the last OP yet we have
220 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
221 itable[MY_INDEX].name,
223 (long) history->op.cia,
224 (long) peer->mt.cia);
227 history->mf.timestamp = time;
228 history->mf.cia = CIA;
232 // start-sanitize-r5900
233 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
234 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
235 // end-sanitize-r5900
236 // start-sanitize-r5900
238 // end-sanitize-r5900
239 // start-sanitize-r5900
241 /* FIXME: could record the fact that a stall occured if we want */
242 signed64 time = sim_events_time (SD);
243 history->mf.timestamp = time;
244 history->mf.cia = CIA;
247 // end-sanitize-r5900
250 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
251 *mipsI,mipsII,mipsIII,mipsIV:
254 // start-sanitize-vr4xxx
256 // end-sanitize-vr4xxx
257 // start-sanitize-vr4320
259 // end-sanitize-vr4320
260 // start-sanitize-cygnus
262 // end-sanitize-cygnus
264 signed64 time = sim_events_time (SD);
265 int ok = (check_mf_cycles (SD_, hi, time, "OP")
266 && check_mf_cycles (SD_, lo, time, "OP"));
267 hi->op.timestamp = time;
268 lo->op.timestamp = time;
274 // The r3900 mult and multu insns _can_ be exectuted immediatly after
276 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
278 // start-sanitize-tx19
281 // start-sanitize-r5900
283 // end-sanitize-r5900
285 /* FIXME: could record the fact that a stall occured if we want */
286 signed64 time = sim_events_time (SD);
287 hi->op.timestamp = time;
288 lo->op.timestamp = time;
295 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
296 *mipsI,mipsII,mipsIII,mipsIV:
299 // start-sanitize-vr4xxx
301 // end-sanitize-vr4xxx
302 // start-sanitize-vr4320
304 // end-sanitize-vr4320
305 // start-sanitize-cygnus
307 // end-sanitize-cygnus
309 // start-sanitize-tx19
313 signed64 time = sim_events_time (SD);
314 int ok = (check_mf_cycles (SD_, hi, time, "OP")
315 && check_mf_cycles (SD_, lo, time, "OP"));
316 hi->op.timestamp = time;
317 lo->op.timestamp = time;
324 // start-sanitize-r5900
325 // The r5900 div et.al insns _can_ be exectuted immediatly after
327 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
328 // end-sanitize-r5900
329 // start-sanitize-r5900
331 // end-sanitize-r5900
332 // start-sanitize-r5900
334 /* FIXME: could record the fact that a stall occured if we want */
335 signed64 time = sim_events_time (SD);
336 hi->op.timestamp = time;
337 lo->op.timestamp = time;
342 // end-sanitize-r5900
347 // Mips Architecture:
349 // CPU Instruction Set (mipsI - mipsIV)
354 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
355 "add r<RD>, r<RS>, r<RT>"
356 *mipsI,mipsII,mipsIII,mipsIV:
359 // start-sanitize-vr4xxx
361 // end-sanitize-vr4xxx
362 // start-sanitize-vr4320
364 // end-sanitize-vr4320
365 // start-sanitize-cygnus
367 // end-sanitize-cygnus
368 // start-sanitize-r5900
370 // end-sanitize-r5900
372 // start-sanitize-tx19
376 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
378 ALU32_BEGIN (GPR[RS]);
382 TRACE_ALU_RESULT (GPR[RD]);
387 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
388 "addi r<RT>, r<RS>, IMMEDIATE"
389 *mipsI,mipsII,mipsIII,mipsIV:
392 // start-sanitize-vr4xxx
394 // end-sanitize-vr4xxx
395 // start-sanitize-vr4320
397 // end-sanitize-vr4320
398 // start-sanitize-cygnus
400 // end-sanitize-cygnus
401 // start-sanitize-r5900
403 // end-sanitize-r5900
405 // start-sanitize-tx19
409 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
411 ALU32_BEGIN (GPR[RS]);
412 ALU32_ADD (EXTEND16 (IMMEDIATE));
415 TRACE_ALU_RESULT (GPR[RT]);
420 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
422 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
423 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
424 TRACE_ALU_RESULT (GPR[rt]);
427 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
428 "addiu r<RT>, r<RS>, <IMMEDIATE>"
429 *mipsI,mipsII,mipsIII,mipsIV:
432 // start-sanitize-vr4xxx
434 // end-sanitize-vr4xxx
435 // start-sanitize-vr4320
437 // end-sanitize-vr4320
438 // start-sanitize-cygnus
440 // end-sanitize-cygnus
441 // start-sanitize-r5900
443 // end-sanitize-r5900
445 // start-sanitize-tx19
449 do_addiu (SD_, RS, RT, IMMEDIATE);
454 :function:::void:do_addu:int rs, int rt, int rd
456 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
457 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
458 TRACE_ALU_RESULT (GPR[rd]);
461 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
462 "addu r<RD>, r<RS>, r<RT>"
463 *mipsI,mipsII,mipsIII,mipsIV:
466 // start-sanitize-vr4xxx
468 // end-sanitize-vr4xxx
469 // start-sanitize-vr4320
471 // end-sanitize-vr4320
472 // start-sanitize-cygnus
474 // end-sanitize-cygnus
475 // start-sanitize-r5900
477 // end-sanitize-r5900
479 // start-sanitize-tx19
483 do_addu (SD_, RS, RT, RD);
488 :function:::void:do_and:int rs, int rt, int rd
490 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
491 GPR[rd] = GPR[rs] & GPR[rt];
492 TRACE_ALU_RESULT (GPR[rd]);
495 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
496 "and r<RD>, r<RS>, r<RT>"
497 *mipsI,mipsII,mipsIII,mipsIV:
500 // start-sanitize-vr4xxx
502 // end-sanitize-vr4xxx
503 // start-sanitize-vr4320
505 // end-sanitize-vr4320
506 // start-sanitize-cygnus
508 // end-sanitize-cygnus
509 // start-sanitize-r5900
511 // end-sanitize-r5900
513 // start-sanitize-tx19
517 do_and (SD_, RS, RT, RD);
522 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
523 "and r<RT>, r<RS>, <IMMEDIATE>"
524 *mipsI,mipsII,mipsIII,mipsIV:
527 // start-sanitize-vr4xxx
529 // end-sanitize-vr4xxx
530 // start-sanitize-vr4320
532 // end-sanitize-vr4320
533 // start-sanitize-cygnus
535 // end-sanitize-cygnus
536 // start-sanitize-r5900
538 // end-sanitize-r5900
540 // start-sanitize-tx19
544 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
545 GPR[RT] = GPR[RS] & IMMEDIATE;
546 TRACE_ALU_RESULT (GPR[RT]);
551 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
552 "beq r<RS>, r<RT>, <OFFSET>"
553 *mipsI,mipsII,mipsIII,mipsIV:
556 // start-sanitize-vr4xxx
558 // end-sanitize-vr4xxx
559 // start-sanitize-vr4320
561 // end-sanitize-vr4320
562 // start-sanitize-cygnus
564 // end-sanitize-cygnus
565 // start-sanitize-r5900
567 // end-sanitize-r5900
569 // start-sanitize-tx19
573 address_word offset = EXTEND16 (OFFSET) << 2;
575 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
577 mark_branch_bug (NIA+offset);
578 DELAY_SLOT (NIA + offset);
584 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
585 "beql r<RS>, r<RT>, <OFFSET>"
591 // start-sanitize-vr4xxx
593 // end-sanitize-vr4xxx
594 // start-sanitize-vr4320
596 // end-sanitize-vr4320
597 // start-sanitize-cygnus
599 // end-sanitize-cygnus
600 // start-sanitize-r5900
602 // end-sanitize-r5900
604 // start-sanitize-tx19
608 address_word offset = EXTEND16 (OFFSET) << 2;
610 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
612 mark_branch_bug (NIA+offset);
613 DELAY_SLOT (NIA + offset);
616 NULLIFY_NEXT_INSTRUCTION ();
621 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
622 "bgez r<RS>, <OFFSET>"
623 *mipsI,mipsII,mipsIII,mipsIV:
626 // start-sanitize-vr4xxx
628 // end-sanitize-vr4xxx
629 // start-sanitize-vr4320
631 // end-sanitize-vr4320
632 // start-sanitize-cygnus
634 // end-sanitize-cygnus
635 // start-sanitize-r5900
637 // end-sanitize-r5900
639 // start-sanitize-tx19
643 address_word offset = EXTEND16 (OFFSET) << 2;
645 if ((signed_word) GPR[RS] >= 0)
647 mark_branch_bug (NIA+offset);
648 DELAY_SLOT (NIA + offset);
654 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
655 "bgezal r<RS>, <OFFSET>"
656 *mipsI,mipsII,mipsIII,mipsIV:
659 // start-sanitize-vr4xxx
661 // end-sanitize-vr4xxx
662 // start-sanitize-vr4320
664 // end-sanitize-vr4320
665 // start-sanitize-cygnus
667 // end-sanitize-cygnus
668 // start-sanitize-r5900
670 // end-sanitize-r5900
672 // start-sanitize-tx19
676 address_word offset = EXTEND16 (OFFSET) << 2;
679 if ((signed_word) GPR[RS] >= 0)
681 mark_branch_bug (NIA+offset);
682 DELAY_SLOT (NIA + offset);
688 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
689 "bgezall r<RS>, <OFFSET>"
695 // start-sanitize-vr4xxx
697 // end-sanitize-vr4xxx
698 // start-sanitize-vr4320
700 // end-sanitize-vr4320
701 // start-sanitize-cygnus
703 // end-sanitize-cygnus
704 // start-sanitize-r5900
706 // end-sanitize-r5900
708 // start-sanitize-tx19
712 address_word offset = EXTEND16 (OFFSET) << 2;
715 /* NOTE: The branch occurs AFTER the next instruction has been
717 if ((signed_word) GPR[RS] >= 0)
719 mark_branch_bug (NIA+offset);
720 DELAY_SLOT (NIA + offset);
723 NULLIFY_NEXT_INSTRUCTION ();
728 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
729 "bgezl r<RS>, <OFFSET>"
735 // start-sanitize-vr4xxx
737 // end-sanitize-vr4xxx
738 // start-sanitize-vr4320
740 // end-sanitize-vr4320
741 // start-sanitize-cygnus
743 // end-sanitize-cygnus
744 // start-sanitize-r5900
746 // end-sanitize-r5900
748 // start-sanitize-tx19
752 address_word offset = EXTEND16 (OFFSET) << 2;
754 if ((signed_word) GPR[RS] >= 0)
756 mark_branch_bug (NIA+offset);
757 DELAY_SLOT (NIA + offset);
760 NULLIFY_NEXT_INSTRUCTION ();
765 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
766 "bgtz r<RS>, <OFFSET>"
767 *mipsI,mipsII,mipsIII,mipsIV:
770 // start-sanitize-vr4xxx
772 // end-sanitize-vr4xxx
773 // start-sanitize-vr4320
775 // end-sanitize-vr4320
776 // start-sanitize-cygnus
778 // end-sanitize-cygnus
779 // start-sanitize-r5900
781 // end-sanitize-r5900
783 // start-sanitize-tx19
787 address_word offset = EXTEND16 (OFFSET) << 2;
789 if ((signed_word) GPR[RS] > 0)
791 mark_branch_bug (NIA+offset);
792 DELAY_SLOT (NIA + offset);
798 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
799 "bgtzl r<RS>, <OFFSET>"
805 // start-sanitize-vr4xxx
807 // end-sanitize-vr4xxx
808 // start-sanitize-vr4320
810 // end-sanitize-vr4320
811 // start-sanitize-cygnus
813 // end-sanitize-cygnus
814 // start-sanitize-r5900
816 // end-sanitize-r5900
818 // start-sanitize-tx19
822 address_word offset = EXTEND16 (OFFSET) << 2;
824 /* NOTE: The branch occurs AFTER the next instruction has been
826 if ((signed_word) GPR[RS] > 0)
828 mark_branch_bug (NIA+offset);
829 DELAY_SLOT (NIA + offset);
832 NULLIFY_NEXT_INSTRUCTION ();
837 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
838 "blez r<RS>, <OFFSET>"
839 *mipsI,mipsII,mipsIII,mipsIV:
842 // start-sanitize-vr4xxx
844 // end-sanitize-vr4xxx
845 // start-sanitize-vr4320
847 // end-sanitize-vr4320
848 // start-sanitize-cygnus
850 // end-sanitize-cygnus
851 // start-sanitize-r5900
853 // end-sanitize-r5900
855 // start-sanitize-tx19
859 address_word offset = EXTEND16 (OFFSET) << 2;
861 /* NOTE: The branch occurs AFTER the next instruction has been
863 if ((signed_word) GPR[RS] <= 0)
865 mark_branch_bug (NIA+offset);
866 DELAY_SLOT (NIA + offset);
872 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
873 "bgezl r<RS>, <OFFSET>"
879 // start-sanitize-vr4xxx
881 // end-sanitize-vr4xxx
882 // start-sanitize-vr4320
884 // end-sanitize-vr4320
885 // start-sanitize-cygnus
887 // end-sanitize-cygnus
888 // start-sanitize-r5900
890 // end-sanitize-r5900
892 // start-sanitize-tx19
896 address_word offset = EXTEND16 (OFFSET) << 2;
898 if ((signed_word) GPR[RS] <= 0)
900 mark_branch_bug (NIA+offset);
901 DELAY_SLOT (NIA + offset);
904 NULLIFY_NEXT_INSTRUCTION ();
909 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
910 "bltz r<RS>, <OFFSET>"
911 *mipsI,mipsII,mipsIII,mipsIV:
914 // start-sanitize-vr4xxx
916 // end-sanitize-vr4xxx
917 // start-sanitize-vr4320
919 // end-sanitize-vr4320
920 // start-sanitize-cygnus
922 // end-sanitize-cygnus
923 // start-sanitize-r5900
925 // end-sanitize-r5900
927 // start-sanitize-tx19
931 address_word offset = EXTEND16 (OFFSET) << 2;
933 if ((signed_word) GPR[RS] < 0)
935 mark_branch_bug (NIA+offset);
936 DELAY_SLOT (NIA + offset);
942 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
943 "bltzal r<RS>, <OFFSET>"
944 *mipsI,mipsII,mipsIII,mipsIV:
947 // start-sanitize-vr4xxx
949 // end-sanitize-vr4xxx
950 // start-sanitize-vr4320
952 // end-sanitize-vr4320
953 // start-sanitize-cygnus
955 // end-sanitize-cygnus
956 // start-sanitize-r5900
958 // end-sanitize-r5900
960 // start-sanitize-tx19
964 address_word offset = EXTEND16 (OFFSET) << 2;
967 /* NOTE: The branch occurs AFTER the next instruction has been
969 if ((signed_word) GPR[RS] < 0)
971 mark_branch_bug (NIA+offset);
972 DELAY_SLOT (NIA + offset);
978 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
979 "bltzall r<RS>, <OFFSET>"
985 // start-sanitize-vr4xxx
987 // end-sanitize-vr4xxx
988 // start-sanitize-vr4320
990 // end-sanitize-vr4320
991 // start-sanitize-cygnus
993 // end-sanitize-cygnus
994 // start-sanitize-r5900
996 // end-sanitize-r5900
998 // start-sanitize-tx19
1000 // end-sanitize-tx19
1002 address_word offset = EXTEND16 (OFFSET) << 2;
1003 check_branch_bug ();
1005 if ((signed_word) GPR[RS] < 0)
1007 mark_branch_bug (NIA+offset);
1008 DELAY_SLOT (NIA + offset);
1011 NULLIFY_NEXT_INSTRUCTION ();
1016 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1017 "bltzl r<RS>, <OFFSET>"
1023 // start-sanitize-vr4xxx
1025 // end-sanitize-vr4xxx
1026 // start-sanitize-vr4320
1028 // end-sanitize-vr4320
1029 // start-sanitize-cygnus
1031 // end-sanitize-cygnus
1032 // start-sanitize-r5900
1034 // end-sanitize-r5900
1036 // start-sanitize-tx19
1038 // end-sanitize-tx19
1040 address_word offset = EXTEND16 (OFFSET) << 2;
1041 check_branch_bug ();
1042 /* NOTE: The branch occurs AFTER the next instruction has been
1044 if ((signed_word) GPR[RS] < 0)
1046 mark_branch_bug (NIA+offset);
1047 DELAY_SLOT (NIA + offset);
1050 NULLIFY_NEXT_INSTRUCTION ();
1055 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1056 "bne r<RS>, r<RT>, <OFFSET>"
1057 *mipsI,mipsII,mipsIII,mipsIV:
1060 // start-sanitize-vr4xxx
1062 // end-sanitize-vr4xxx
1063 // start-sanitize-vr4320
1065 // end-sanitize-vr4320
1066 // start-sanitize-cygnus
1068 // end-sanitize-cygnus
1069 // start-sanitize-r5900
1071 // end-sanitize-r5900
1073 // start-sanitize-tx19
1075 // end-sanitize-tx19
1077 address_word offset = EXTEND16 (OFFSET) << 2;
1078 check_branch_bug ();
1079 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1081 mark_branch_bug (NIA+offset);
1082 DELAY_SLOT (NIA + offset);
1088 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1089 "bnel r<RS>, r<RT>, <OFFSET>"
1095 // start-sanitize-vr4xxx
1097 // end-sanitize-vr4xxx
1098 // start-sanitize-vr4320
1100 // end-sanitize-vr4320
1101 // start-sanitize-cygnus
1103 // end-sanitize-cygnus
1104 // start-sanitize-r5900
1106 // end-sanitize-r5900
1108 // start-sanitize-tx19
1110 // end-sanitize-tx19
1112 address_word offset = EXTEND16 (OFFSET) << 2;
1113 check_branch_bug ();
1114 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1116 mark_branch_bug (NIA+offset);
1117 DELAY_SLOT (NIA + offset);
1120 NULLIFY_NEXT_INSTRUCTION ();
1125 000000,20.CODE,001101:SPECIAL:32::BREAK
1127 *mipsI,mipsII,mipsIII,mipsIV:
1130 // start-sanitize-vr4xxx
1132 // end-sanitize-vr4xxx
1133 // start-sanitize-vr4320
1135 // end-sanitize-vr4320
1136 // start-sanitize-cygnus
1138 // end-sanitize-cygnus
1139 // start-sanitize-r5900
1141 // end-sanitize-r5900
1143 // start-sanitize-tx19
1145 // end-sanitize-tx19
1147 /* Check for some break instruction which are reserved for use by the simulator. */
1148 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1149 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1150 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1152 sim_engine_halt (SD, CPU, NULL, cia,
1153 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1155 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1156 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1158 if (STATE & simDELAYSLOT)
1159 PC = cia - 4; /* reference the branch instruction */
1162 sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1164 // start-sanitize-sky
1166 else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
1168 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
1170 else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
1172 sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
1174 else if (break_code == (PRINTF_INSTRUCTION & HALT_INSTRUCTION_MASK))
1176 sim_monitor(SD, CPU, cia, 316); /* Magic number for idt printf routine. */
1178 else if (break_code == (LOAD_INSTRUCTION & HALT_INSTRUCTION_MASK))
1180 /* This is a multi-phase load instruction. Load next configured
1181 executable and return its starting PC in A0 ($4). */
1183 if (STATE_MLOAD_INDEX (SD) == STATE_MLOAD_COUNT (SD))
1185 sim_io_eprintf (SD, "Cannot load program %d. Not enough load-next options.\n",
1186 STATE_MLOAD_COUNT (SD));
1191 char* next = STATE_MLOAD_NAME (SD) [STATE_MLOAD_INDEX (SD)];
1194 STATE_MLOAD_INDEX (SD) ++;
1196 /* call sim_load_file, preserving most previous state */
1197 rc = sim_load (SD, next, NULL, 0);
1200 sim_io_eprintf (SD, "Error during multi-phase load #%d.\n",
1201 STATE_MLOAD_INDEX (SD));
1205 A0 = STATE_START_ADDR (SD);
1213 /* If we get this far, we're not an instruction reserved by the sim. Raise
1215 SignalException(BreakPoint, instruction_0);
1224 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1225 "dadd r<RD>, r<RS>, r<RT>"
1230 // start-sanitize-vr4xxx
1232 // end-sanitize-vr4xxx
1233 // start-sanitize-vr4320
1235 // end-sanitize-vr4320
1236 // start-sanitize-cygnus
1238 // end-sanitize-cygnus
1239 // start-sanitize-r5900
1241 // end-sanitize-r5900
1242 // start-sanitize-tx19
1244 // end-sanitize-tx19
1246 /* this check's for overflow */
1247 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1249 ALU64_BEGIN (GPR[RS]);
1250 ALU64_ADD (GPR[RT]);
1251 ALU64_END (GPR[RD]);
1253 TRACE_ALU_RESULT (GPR[RD]);
1258 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1259 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1264 // start-sanitize-vr4xxx
1266 // end-sanitize-vr4xxx
1267 // start-sanitize-vr4320
1269 // end-sanitize-vr4320
1270 // start-sanitize-cygnus
1272 // end-sanitize-cygnus
1273 // start-sanitize-r5900
1275 // end-sanitize-r5900
1276 // start-sanitize-tx19
1278 // end-sanitize-tx19
1280 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1282 ALU64_BEGIN (GPR[RS]);
1283 ALU64_ADD (EXTEND16 (IMMEDIATE));
1284 ALU64_END (GPR[RT]);
1286 TRACE_ALU_RESULT (GPR[RT]);
1291 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1293 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1294 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1295 TRACE_ALU_RESULT (GPR[rt]);
1298 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1299 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1304 // start-sanitize-vr4xxx
1306 // end-sanitize-vr4xxx
1307 // start-sanitize-vr4320
1309 // end-sanitize-vr4320
1310 // start-sanitize-cygnus
1312 // end-sanitize-cygnus
1313 // start-sanitize-r5900
1315 // end-sanitize-r5900
1316 // start-sanitize-tx19
1318 // end-sanitize-tx19
1320 do_daddiu (SD_, RS, RT, IMMEDIATE);
1325 :function:::void:do_daddu:int rs, int rt, int rd
1327 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1328 GPR[rd] = GPR[rs] + GPR[rt];
1329 TRACE_ALU_RESULT (GPR[rd]);
1332 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1333 "daddu r<RD>, r<RS>, r<RT>"
1338 // start-sanitize-vr4xxx
1340 // end-sanitize-vr4xxx
1341 // start-sanitize-vr4320
1343 // end-sanitize-vr4320
1344 // start-sanitize-cygnus
1346 // end-sanitize-cygnus
1347 // start-sanitize-r5900
1349 // end-sanitize-r5900
1350 // start-sanitize-tx19
1352 // end-sanitize-tx19
1354 do_daddu (SD_, RS, RT, RD);
1359 :function:::void:do_ddiv:int rs, int rt
1361 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1362 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1364 signed64 n = GPR[rs];
1365 signed64 d = GPR[rt];
1370 lo = SIGNED64 (0x8000000000000000);
1373 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1375 lo = SIGNED64 (0x8000000000000000);
1386 TRACE_ALU_RESULT2 (HI, LO);
1389 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1395 // start-sanitize-vr4xxx
1397 // end-sanitize-vr4xxx
1398 // start-sanitize-vr4320
1400 // end-sanitize-vr4320
1401 // start-sanitize-cygnus
1403 // end-sanitize-cygnus
1404 // start-sanitize-r5900
1406 // end-sanitize-r5900
1407 // start-sanitize-tx19
1409 // end-sanitize-tx19
1411 do_ddiv (SD_, RS, RT);
1416 :function:::void:do_ddivu:int rs, int rt
1418 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1419 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1421 unsigned64 n = GPR[rs];
1422 unsigned64 d = GPR[rt];
1427 lo = SIGNED64 (0x8000000000000000);
1438 TRACE_ALU_RESULT2 (HI, LO);
1441 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1442 "ddivu r<RS>, r<RT>"
1447 // start-sanitize-vr4xxx
1449 // end-sanitize-vr4xxx
1450 // start-sanitize-vr4320
1452 // end-sanitize-vr4320
1453 // start-sanitize-cygnus
1455 // end-sanitize-cygnus
1456 // start-sanitize-tx19
1458 // end-sanitize-tx19
1460 do_ddivu (SD_, RS, RT);
1465 :function:::void:do_div:int rs, int rt
1467 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1468 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1470 signed32 n = GPR[rs];
1471 signed32 d = GPR[rt];
1474 LO = EXTEND32 (0x80000000);
1477 else if (n == SIGNED32 (0x80000000) && d == -1)
1479 LO = EXTEND32 (0x80000000);
1484 LO = EXTEND32 (n / d);
1485 HI = EXTEND32 (n % d);
1488 TRACE_ALU_RESULT2 (HI, LO);
1491 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1493 *mipsI,mipsII,mipsIII,mipsIV:
1496 // start-sanitize-vr4xxx
1498 // end-sanitize-vr4xxx
1499 // start-sanitize-vr4320
1501 // end-sanitize-vr4320
1502 // start-sanitize-cygnus
1504 // end-sanitize-cygnus
1505 // start-sanitize-r5900
1507 // end-sanitize-r5900
1509 // start-sanitize-tx19
1511 // end-sanitize-tx19
1513 do_div (SD_, RS, RT);
1518 :function:::void:do_divu:int rs, int rt
1520 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1521 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1523 unsigned32 n = GPR[rs];
1524 unsigned32 d = GPR[rt];
1527 LO = EXTEND32 (0x80000000);
1532 LO = EXTEND32 (n / d);
1533 HI = EXTEND32 (n % d);
1536 TRACE_ALU_RESULT2 (HI, LO);
1539 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1541 *mipsI,mipsII,mipsIII,mipsIV:
1544 // start-sanitize-vr4xxx
1546 // end-sanitize-vr4xxx
1547 // start-sanitize-vr4320
1549 // end-sanitize-vr4320
1550 // start-sanitize-cygnus
1552 // end-sanitize-cygnus
1553 // start-sanitize-r5900
1555 // end-sanitize-r5900
1557 // start-sanitize-tx19
1559 // end-sanitize-tx19
1561 do_divu (SD_, RS, RT);
1566 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1576 unsigned64 op1 = GPR[rs];
1577 unsigned64 op2 = GPR[rt];
1578 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1579 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1580 /* make signed multiply unsigned */
1595 /* multuply out the 4 sub products */
1596 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1597 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1598 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1599 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1600 /* add the products */
1601 mid = ((unsigned64) VH4_8 (m00)
1602 + (unsigned64) VL4_8 (m10)
1603 + (unsigned64) VL4_8 (m01));
1604 lo = U8_4 (mid, m00);
1606 + (unsigned64) VH4_8 (mid)
1607 + (unsigned64) VH4_8 (m01)
1608 + (unsigned64) VH4_8 (m10));
1618 /* save the result HI/LO (and a gpr) */
1623 TRACE_ALU_RESULT2 (HI, LO);
1626 :function:::void:do_dmult:int rs, int rt, int rd
1628 do_dmultx (SD_, rs, rt, rd, 1);
1631 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1632 "dmult r<RS>, r<RT>"
1635 // start-sanitize-vr4xxx
1637 // end-sanitize-vr4xxx
1638 // start-sanitize-tx19
1640 // end-sanitize-tx19
1641 // start-sanitize-vr4320
1643 // end-sanitize-vr4320
1645 do_dmult (SD_, RS, RT, 0);
1648 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1649 "dmult r<RS>, r<RT>":RD == 0
1650 "dmult r<RD>, r<RS>, r<RT>"
1652 // start-sanitize-cygnus
1654 // end-sanitize-cygnus
1656 do_dmult (SD_, RS, RT, RD);
1661 :function:::void:do_dmultu:int rs, int rt, int rd
1663 do_dmultx (SD_, rs, rt, rd, 0);
1666 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1667 "dmultu r<RS>, r<RT>"
1670 // start-sanitize-vr4xxx
1672 // end-sanitize-vr4xxx
1673 // start-sanitize-tx19
1675 // end-sanitize-tx19
1676 // start-sanitize-vr4320
1678 // end-sanitize-vr4320
1680 do_dmultu (SD_, RS, RT, 0);
1683 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1684 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1685 "dmultu r<RS>, r<RT>"
1687 // start-sanitize-cygnus
1689 // end-sanitize-cygnus
1691 do_dmultu (SD_, RS, RT, RD);
1694 :function:::void:do_dsll:int rt, int rd, int shift
1696 GPR[rd] = GPR[rt] << shift;
1699 :function:::void:do_dsllv:int rs, int rt, int rd
1701 int s = MASKED64 (GPR[rs], 5, 0);
1702 GPR[rd] = GPR[rt] << s;
1706 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1707 "dsll r<RD>, r<RT>, <SHIFT>"
1712 // start-sanitize-vr4xxx
1714 // end-sanitize-vr4xxx
1715 // start-sanitize-vr4320
1717 // end-sanitize-vr4320
1718 // start-sanitize-cygnus
1720 // end-sanitize-cygnus
1721 // start-sanitize-r5900
1723 // end-sanitize-r5900
1724 // start-sanitize-tx19
1726 // end-sanitize-tx19
1728 do_dsll (SD_, RT, RD, SHIFT);
1732 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1733 "dsll32 r<RD>, r<RT>, <SHIFT>"
1738 // start-sanitize-vr4xxx
1740 // end-sanitize-vr4xxx
1741 // start-sanitize-vr4320
1743 // end-sanitize-vr4320
1744 // start-sanitize-cygnus
1746 // end-sanitize-cygnus
1747 // start-sanitize-r5900
1749 // end-sanitize-r5900
1750 // start-sanitize-tx19
1752 // end-sanitize-tx19
1755 GPR[RD] = GPR[RT] << s;
1758 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1759 "dsllv r<RD>, r<RT>, r<RS>"
1764 // start-sanitize-vr4xxx
1766 // end-sanitize-vr4xxx
1767 // start-sanitize-vr4320
1769 // end-sanitize-vr4320
1770 // start-sanitize-cygnus
1772 // end-sanitize-cygnus
1773 // start-sanitize-r5900
1775 // end-sanitize-r5900
1776 // start-sanitize-tx19
1778 // end-sanitize-tx19
1780 do_dsllv (SD_, RS, RT, RD);
1783 :function:::void:do_dsra:int rt, int rd, int shift
1785 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1789 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1790 "dsra r<RD>, r<RT>, <SHIFT>"
1795 // start-sanitize-vr4xxx
1797 // end-sanitize-vr4xxx
1798 // start-sanitize-vr4320
1800 // end-sanitize-vr4320
1801 // start-sanitize-cygnus
1803 // end-sanitize-cygnus
1804 // start-sanitize-r5900
1806 // end-sanitize-r5900
1807 // start-sanitize-tx19
1809 // end-sanitize-tx19
1811 do_dsra (SD_, RT, RD, SHIFT);
1815 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1816 "dsra32 r<RT>, r<RD>, <SHIFT>"
1821 // start-sanitize-vr4xxx
1823 // end-sanitize-vr4xxx
1824 // start-sanitize-vr4320
1826 // end-sanitize-vr4320
1827 // start-sanitize-cygnus
1829 // end-sanitize-cygnus
1830 // start-sanitize-r5900
1832 // end-sanitize-r5900
1833 // start-sanitize-tx19
1835 // end-sanitize-tx19
1838 GPR[RD] = ((signed64) GPR[RT]) >> s;
1842 :function:::void:do_dsrav:int rs, int rt, int rd
1844 int s = MASKED64 (GPR[rs], 5, 0);
1845 TRACE_ALU_INPUT2 (GPR[rt], s);
1846 GPR[rd] = ((signed64) GPR[rt]) >> s;
1847 TRACE_ALU_RESULT (GPR[rd]);
1850 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1851 "dsra32 r<RT>, r<RD>, r<RS>"
1856 // start-sanitize-vr4xxx
1858 // end-sanitize-vr4xxx
1859 // start-sanitize-vr4320
1861 // end-sanitize-vr4320
1862 // start-sanitize-cygnus
1864 // end-sanitize-cygnus
1865 // start-sanitize-r5900
1867 // end-sanitize-r5900
1868 // start-sanitize-tx19
1870 // end-sanitize-tx19
1872 do_dsrav (SD_, RS, RT, RD);
1875 :function:::void:do_dsrl:int rt, int rd, int shift
1877 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1881 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1882 "dsrl r<RD>, r<RT>, <SHIFT>"
1887 // start-sanitize-vr4xxx
1889 // end-sanitize-vr4xxx
1890 // start-sanitize-vr4320
1892 // end-sanitize-vr4320
1893 // start-sanitize-cygnus
1895 // end-sanitize-cygnus
1896 // start-sanitize-r5900
1898 // end-sanitize-r5900
1899 // start-sanitize-tx19
1901 // end-sanitize-tx19
1903 do_dsrl (SD_, RT, RD, SHIFT);
1907 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1908 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1913 // start-sanitize-vr4xxx
1915 // end-sanitize-vr4xxx
1916 // start-sanitize-vr4320
1918 // end-sanitize-vr4320
1919 // start-sanitize-cygnus
1921 // end-sanitize-cygnus
1922 // start-sanitize-r5900
1924 // end-sanitize-r5900
1925 // start-sanitize-tx19
1927 // end-sanitize-tx19
1930 GPR[RD] = (unsigned64) GPR[RT] >> s;
1934 :function:::void:do_dsrlv:int rs, int rt, int rd
1936 int s = MASKED64 (GPR[rs], 5, 0);
1937 GPR[rd] = (unsigned64) GPR[rt] >> s;
1942 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1943 "dsrl32 r<RD>, r<RT>, r<RS>"
1948 // start-sanitize-vr4xxx
1950 // end-sanitize-vr4xxx
1951 // start-sanitize-vr4320
1953 // end-sanitize-vr4320
1954 // start-sanitize-cygnus
1956 // end-sanitize-cygnus
1957 // start-sanitize-r5900
1959 // end-sanitize-r5900
1960 // start-sanitize-tx19
1962 // end-sanitize-tx19
1964 do_dsrlv (SD_, RS, RT, RD);
1968 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1969 "dsub r<RD>, r<RS>, r<RT>"
1974 // start-sanitize-vr4xxx
1976 // end-sanitize-vr4xxx
1977 // start-sanitize-vr4320
1979 // end-sanitize-vr4320
1980 // start-sanitize-cygnus
1982 // end-sanitize-cygnus
1983 // start-sanitize-r5900
1985 // end-sanitize-r5900
1986 // start-sanitize-tx19
1988 // end-sanitize-tx19
1990 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1992 ALU64_BEGIN (GPR[RS]);
1993 ALU64_SUB (GPR[RT]);
1994 ALU64_END (GPR[RD]);
1996 TRACE_ALU_RESULT (GPR[RD]);
2000 :function:::void:do_dsubu:int rs, int rt, int rd
2002 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2003 GPR[rd] = GPR[rs] - GPR[rt];
2004 TRACE_ALU_RESULT (GPR[rd]);
2007 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
2008 "dsubu r<RD>, r<RS>, r<RT>"
2013 // start-sanitize-vr4xxx
2015 // end-sanitize-vr4xxx
2016 // start-sanitize-vr4320
2018 // end-sanitize-vr4320
2019 // start-sanitize-cygnus
2021 // end-sanitize-cygnus
2022 // start-sanitize-r5900
2024 // end-sanitize-r5900
2025 // start-sanitize-tx19
2027 // end-sanitize-tx19
2029 do_dsubu (SD_, RS, RT, RD);
2033 000010,26.INSTR_INDEX:NORMAL:32::J
2035 *mipsI,mipsII,mipsIII,mipsIV:
2038 // start-sanitize-vr4xxx
2040 // end-sanitize-vr4xxx
2041 // start-sanitize-vr4320
2043 // end-sanitize-vr4320
2044 // start-sanitize-cygnus
2046 // end-sanitize-cygnus
2047 // start-sanitize-r5900
2049 // end-sanitize-r5900
2051 // start-sanitize-tx19
2053 // end-sanitize-tx19
2055 /* NOTE: The region used is that of the delay slot NIA and NOT the
2056 current instruction */
2057 address_word region = (NIA & MASK (63, 28));
2058 DELAY_SLOT (region | (INSTR_INDEX << 2));
2062 000011,26.INSTR_INDEX:NORMAL:32::JAL
2064 *mipsI,mipsII,mipsIII,mipsIV:
2067 // start-sanitize-vr4xxx
2069 // end-sanitize-vr4xxx
2070 // start-sanitize-vr4320
2072 // end-sanitize-vr4320
2073 // start-sanitize-cygnus
2075 // end-sanitize-cygnus
2076 // start-sanitize-r5900
2078 // end-sanitize-r5900
2080 // start-sanitize-tx19
2082 // end-sanitize-tx19
2084 /* NOTE: The region used is that of the delay slot and NOT the
2085 current instruction */
2086 address_word region = (NIA & MASK (63, 28));
2088 DELAY_SLOT (region | (INSTR_INDEX << 2));
2091 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
2092 "jalr r<RS>":RD == 31
2094 *mipsI,mipsII,mipsIII,mipsIV:
2097 // start-sanitize-vr4xxx
2099 // end-sanitize-vr4xxx
2100 // start-sanitize-vr4320
2102 // end-sanitize-vr4320
2103 // start-sanitize-cygnus
2105 // end-sanitize-cygnus
2106 // start-sanitize-r5900
2108 // end-sanitize-r5900
2110 // start-sanitize-tx19
2112 // end-sanitize-tx19
2114 address_word temp = GPR[RS];
2120 000000,5.RS,000000000000000001000:SPECIAL:32::JR
2122 *mipsI,mipsII,mipsIII,mipsIV:
2125 // start-sanitize-vr4xxx
2127 // end-sanitize-vr4xxx
2128 // start-sanitize-vr4320
2130 // end-sanitize-vr4320
2131 // start-sanitize-cygnus
2133 // end-sanitize-cygnus
2134 // start-sanitize-r5900
2136 // end-sanitize-r5900
2138 // start-sanitize-tx19
2140 // end-sanitize-tx19
2142 DELAY_SLOT (GPR[RS]);
2146 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
2148 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2149 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2150 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2157 vaddr = base + offset;
2158 if ((vaddr & access) != 0)
2160 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
2162 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2163 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2164 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
2165 byte = ((vaddr & mask) ^ bigendiancpu);
2166 return (memval >> (8 * byte));
2170 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2171 "lb r<RT>, <OFFSET>(r<BASE>)"
2172 *mipsI,mipsII,mipsIII,mipsIV:
2175 // start-sanitize-vr4xxx
2177 // end-sanitize-vr4xxx
2178 // start-sanitize-vr4320
2180 // end-sanitize-vr4320
2181 // start-sanitize-cygnus
2183 // end-sanitize-cygnus
2184 // start-sanitize-r5900
2186 // end-sanitize-r5900
2188 // start-sanitize-tx19
2190 // end-sanitize-tx19
2192 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2196 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2197 "lbu r<RT>, <OFFSET>(r<BASE>)"
2198 *mipsI,mipsII,mipsIII,mipsIV:
2201 // start-sanitize-vr4xxx
2203 // end-sanitize-vr4xxx
2204 // start-sanitize-vr4320
2206 // end-sanitize-vr4320
2207 // start-sanitize-cygnus
2209 // end-sanitize-cygnus
2210 // start-sanitize-r5900
2212 // end-sanitize-r5900
2214 // start-sanitize-tx19
2216 // end-sanitize-tx19
2218 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2222 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2223 "ld r<RT>, <OFFSET>(r<BASE>)"
2228 // start-sanitize-vr4xxx
2230 // end-sanitize-vr4xxx
2231 // start-sanitize-vr4320
2233 // end-sanitize-vr4320
2234 // start-sanitize-cygnus
2236 // end-sanitize-cygnus
2237 // start-sanitize-r5900
2239 // end-sanitize-r5900
2240 // start-sanitize-tx19
2242 // end-sanitize-tx19
2244 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2248 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2249 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2255 // start-sanitize-vr4xxx
2257 // end-sanitize-vr4xxx
2258 // start-sanitize-vr4320
2260 // end-sanitize-vr4320
2261 // start-sanitize-cygnus
2263 // end-sanitize-cygnus
2265 // start-sanitize-tx19
2267 // end-sanitize-tx19
2269 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2275 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2276 "ldl r<RT>, <OFFSET>(r<BASE>)"
2281 // start-sanitize-vr4xxx
2283 // end-sanitize-vr4xxx
2284 // start-sanitize-vr4320
2286 // end-sanitize-vr4320
2287 // start-sanitize-cygnus
2289 // end-sanitize-cygnus
2290 // start-sanitize-r5900
2292 // end-sanitize-r5900
2293 // start-sanitize-tx19
2295 // end-sanitize-tx19
2297 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2301 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2302 "ldr r<RT>, <OFFSET>(r<BASE>)"
2307 // start-sanitize-vr4xxx
2309 // end-sanitize-vr4xxx
2310 // start-sanitize-vr4320
2312 // end-sanitize-vr4320
2313 // start-sanitize-cygnus
2315 // end-sanitize-cygnus
2316 // start-sanitize-r5900
2318 // end-sanitize-r5900
2319 // start-sanitize-tx19
2321 // end-sanitize-tx19
2323 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2327 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2328 "lh r<RT>, <OFFSET>(r<BASE>)"
2329 *mipsI,mipsII,mipsIII,mipsIV:
2332 // start-sanitize-vr4xxx
2334 // end-sanitize-vr4xxx
2335 // start-sanitize-vr4320
2337 // end-sanitize-vr4320
2338 // start-sanitize-cygnus
2340 // end-sanitize-cygnus
2341 // start-sanitize-r5900
2343 // end-sanitize-r5900
2345 // start-sanitize-tx19
2347 // end-sanitize-tx19
2349 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2353 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2354 "lhu r<RT>, <OFFSET>(r<BASE>)"
2355 *mipsI,mipsII,mipsIII,mipsIV:
2358 // start-sanitize-vr4xxx
2360 // end-sanitize-vr4xxx
2361 // start-sanitize-vr4320
2363 // end-sanitize-vr4320
2364 // start-sanitize-cygnus
2366 // end-sanitize-cygnus
2367 // start-sanitize-r5900
2369 // end-sanitize-r5900
2371 // start-sanitize-tx19
2373 // end-sanitize-tx19
2375 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2379 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2380 "ll r<RT>, <OFFSET>(r<BASE>)"
2386 // start-sanitize-vr4xxx
2388 // end-sanitize-vr4xxx
2389 // start-sanitize-vr4320
2391 // end-sanitize-vr4320
2392 // start-sanitize-cygnus
2394 // end-sanitize-cygnus
2395 // start-sanitize-r5900
2397 // end-sanitize-r5900
2398 // start-sanitize-tx19
2400 // end-sanitize-tx19
2402 unsigned32 instruction = instruction_0;
2403 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2404 int destreg = ((instruction >> 16) & 0x0000001F);
2405 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2407 address_word vaddr = ((unsigned64)op1 + offset);
2410 if ((vaddr & 3) != 0)
2412 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2416 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2418 unsigned64 memval = 0;
2419 unsigned64 memval1 = 0;
2420 unsigned64 mask = 0x7;
2421 unsigned int shift = 2;
2422 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2423 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2425 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2426 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2427 byte = ((vaddr & mask) ^ (bigend << shift));
2428 GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2436 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2437 "lld r<RT>, <OFFSET>(r<BASE>)"
2442 // start-sanitize-vr4xxx
2444 // end-sanitize-vr4xxx
2445 // start-sanitize-vr4320
2447 // end-sanitize-vr4320
2448 // start-sanitize-cygnus
2450 // end-sanitize-cygnus
2451 // start-sanitize-r5900
2453 // end-sanitize-r5900
2454 // start-sanitize-tx19
2456 // end-sanitize-tx19
2458 unsigned32 instruction = instruction_0;
2459 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2460 int destreg = ((instruction >> 16) & 0x0000001F);
2461 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2463 address_word vaddr = ((unsigned64)op1 + offset);
2466 if ((vaddr & 7) != 0)
2468 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2472 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2474 unsigned64 memval = 0;
2475 unsigned64 memval1 = 0;
2476 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2477 GPR[destreg] = memval;
2485 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2486 "lui r<RT>, <IMMEDIATE>"
2487 *mipsI,mipsII,mipsIII,mipsIV:
2490 // start-sanitize-vr4xxx
2492 // end-sanitize-vr4xxx
2493 // start-sanitize-vr4320
2495 // end-sanitize-vr4320
2496 // start-sanitize-cygnus
2498 // end-sanitize-cygnus
2499 // start-sanitize-r5900
2501 // end-sanitize-r5900
2503 // start-sanitize-tx19
2505 // end-sanitize-tx19
2507 TRACE_ALU_INPUT1 (IMMEDIATE);
2508 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2509 TRACE_ALU_RESULT (GPR[RT]);
2513 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2514 "lw r<RT>, <OFFSET>(r<BASE>)"
2515 *mipsI,mipsII,mipsIII,mipsIV:
2518 // start-sanitize-vr4xxx
2520 // end-sanitize-vr4xxx
2521 // start-sanitize-vr4320
2523 // end-sanitize-vr4320
2524 // start-sanitize-cygnus
2526 // end-sanitize-cygnus
2527 // start-sanitize-r5900
2529 // end-sanitize-r5900
2531 // start-sanitize-tx19
2533 // end-sanitize-tx19
2535 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2539 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2540 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2541 *mipsI,mipsII,mipsIII,mipsIV:
2544 // start-sanitize-vr4xxx
2546 // end-sanitize-vr4xxx
2547 // start-sanitize-vr4320
2549 // end-sanitize-vr4320
2550 // start-sanitize-cygnus
2552 // end-sanitize-cygnus
2553 // start-sanitize-r5900
2555 // end-sanitize-r5900
2557 // start-sanitize-tx19
2559 // end-sanitize-tx19
2561 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2565 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2567 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2568 address_word reverseendian = (ReverseEndian ? -1 : 0);
2569 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2578 unsigned_word lhs_mask;
2581 vaddr = base + offset;
2582 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2583 paddr = (paddr ^ (reverseendian & mask));
2584 if (BigEndianMem == 0)
2585 paddr = paddr & ~access;
2587 /* compute where within the word/mem we are */
2588 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2589 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2590 nr_lhs_bits = 8 * byte + 8;
2591 nr_rhs_bits = 8 * access - 8 * byte;
2592 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2594 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2595 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2596 (long) ((unsigned64) paddr >> 32), (long) paddr,
2597 word, byte, nr_lhs_bits, nr_rhs_bits); */
2599 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2602 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2603 temp = (memval << nr_rhs_bits);
2607 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2608 temp = (memval >> nr_lhs_bits);
2610 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2611 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2613 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2614 (long) ((unsigned64) memval >> 32), (long) memval,
2615 (long) ((unsigned64) temp >> 32), (long) temp,
2616 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2617 (long) (rt >> 32), (long) rt); */
2622 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2623 "lwl r<RT>, <OFFSET>(r<BASE>)"
2624 *mipsI,mipsII,mipsIII,mipsIV:
2627 // start-sanitize-vr4xxx
2629 // end-sanitize-vr4xxx
2630 // start-sanitize-vr4320
2632 // end-sanitize-vr4320
2633 // start-sanitize-cygnus
2635 // end-sanitize-cygnus
2636 // start-sanitize-r5900
2638 // end-sanitize-r5900
2640 // start-sanitize-tx19
2642 // end-sanitize-tx19
2644 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2648 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2650 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2651 address_word reverseendian = (ReverseEndian ? -1 : 0);
2652 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2659 vaddr = base + offset;
2660 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2661 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2662 paddr = (paddr ^ (reverseendian & mask));
2663 if (BigEndianMem != 0)
2664 paddr = paddr & ~access;
2665 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2666 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2667 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2668 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2669 (long) paddr, byte, (long) paddr, (long) memval); */
2671 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2673 rt |= (memval >> (8 * byte)) & screen;
2679 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2680 "lwr r<RT>, <OFFSET>(r<BASE>)"
2681 *mipsI,mipsII,mipsIII,mipsIV:
2684 // start-sanitize-vr4xxx
2686 // end-sanitize-vr4xxx
2687 // start-sanitize-vr4320
2689 // end-sanitize-vr4320
2690 // start-sanitize-cygnus
2692 // end-sanitize-cygnus
2693 // start-sanitize-r5900
2695 // end-sanitize-r5900
2697 // start-sanitize-tx19
2699 // end-sanitize-tx19
2701 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2705 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2706 "lwu r<RT>, <OFFSET>(r<BASE>)"
2711 // start-sanitize-vr4xxx
2713 // end-sanitize-vr4xxx
2714 // start-sanitize-vr4320
2716 // end-sanitize-vr4320
2717 // start-sanitize-cygnus
2719 // end-sanitize-cygnus
2720 // start-sanitize-r5900
2722 // end-sanitize-r5900
2723 // start-sanitize-tx19
2725 // end-sanitize-tx19
2727 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2731 :function:::void:do_mfhi:int rd
2733 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2734 TRACE_ALU_INPUT1 (HI);
2736 TRACE_ALU_RESULT (GPR[rd]);
2739 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2741 *mipsI,mipsII,mipsIII,mipsIV:
2744 // start-sanitize-vr4xxx
2746 // end-sanitize-vr4xxx
2747 // start-sanitize-vr4320
2749 // end-sanitize-vr4320
2750 // start-sanitize-cygnus
2752 // end-sanitize-cygnus
2753 // start-sanitize-r5900
2755 // end-sanitize-r5900
2757 // start-sanitize-tx19
2759 // end-sanitize-tx19
2766 :function:::void:do_mflo:int rd
2768 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2769 TRACE_ALU_INPUT1 (LO);
2771 TRACE_ALU_RESULT (GPR[rd]);
2774 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2776 *mipsI,mipsII,mipsIII,mipsIV:
2779 // start-sanitize-vr4xxx
2781 // end-sanitize-vr4xxx
2782 // start-sanitize-vr4320
2784 // end-sanitize-vr4320
2785 // start-sanitize-cygnus
2787 // end-sanitize-cygnus
2788 // start-sanitize-r5900
2790 // end-sanitize-r5900
2792 // start-sanitize-tx19
2794 // end-sanitize-tx19
2801 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2802 "movn r<RD>, r<RS>, r<RT>"
2805 // start-sanitize-vr4xxx
2807 // end-sanitize-vr4xxx
2808 // start-sanitize-vr4320
2810 // end-sanitize-vr4320
2811 // start-sanitize-cygnus
2813 // end-sanitize-cygnus
2814 // start-sanitize-r5900
2816 // end-sanitize-r5900
2824 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2825 "movz r<RD>, r<RS>, r<RT>"
2828 // start-sanitize-vr4320
2830 // end-sanitize-vr4320
2831 // start-sanitize-cygnus
2833 // end-sanitize-cygnus
2834 // start-sanitize-r5900
2836 // end-sanitize-r5900
2844 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2846 *mipsI,mipsII,mipsIII,mipsIV:
2849 // start-sanitize-vr4xxx
2851 // end-sanitize-vr4xxx
2852 // start-sanitize-vr4320
2854 // end-sanitize-vr4320
2855 // start-sanitize-cygnus
2857 // end-sanitize-cygnus
2858 // start-sanitize-r5900
2860 // end-sanitize-r5900
2862 // start-sanitize-tx19
2864 // end-sanitize-tx19
2866 check_mt_hilo (SD_, HIHISTORY);
2872 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2874 *mipsI,mipsII,mipsIII,mipsIV:
2877 // start-sanitize-vr4xxx
2879 // end-sanitize-vr4xxx
2880 // start-sanitize-vr4320
2882 // end-sanitize-vr4320
2883 // start-sanitize-cygnus
2885 // end-sanitize-cygnus
2886 // start-sanitize-r5900
2888 // end-sanitize-r5900
2890 // start-sanitize-tx19
2892 // end-sanitize-tx19
2894 check_mt_hilo (SD_, LOHISTORY);
2900 :function:::void:do_mult:int rs, int rt, int rd
2903 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2904 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2905 prod = (((signed64)(signed32) GPR[rs])
2906 * ((signed64)(signed32) GPR[rt]));
2907 LO = EXTEND32 (VL4_8 (prod));
2908 HI = EXTEND32 (VH4_8 (prod));
2911 TRACE_ALU_RESULT2 (HI, LO);
2914 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2916 *mipsI,mipsII,mipsIII,mipsIV:
2918 // start-sanitize-vr4xxx
2920 // end-sanitize-vr4xxx
2921 // start-sanitize-vr4320
2923 // end-sanitize-vr4320
2925 do_mult (SD_, RS, RT, 0);
2929 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2930 "mult r<RD>, r<RS>, r<RT>"
2932 // start-sanitize-cygnus
2934 // end-sanitize-cygnus
2935 // start-sanitize-r5900
2937 // end-sanitize-r5900
2939 // start-sanitize-tx19
2941 // end-sanitize-tx19
2943 do_mult (SD_, RS, RT, RD);
2947 :function:::void:do_multu:int rs, int rt, int rd
2950 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2951 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2952 prod = (((unsigned64)(unsigned32) GPR[rs])
2953 * ((unsigned64)(unsigned32) GPR[rt]));
2954 LO = EXTEND32 (VL4_8 (prod));
2955 HI = EXTEND32 (VH4_8 (prod));
2958 TRACE_ALU_RESULT2 (HI, LO);
2961 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2962 "multu r<RS>, r<RT>"
2963 *mipsI,mipsII,mipsIII,mipsIV:
2965 // start-sanitize-vr4xxx
2967 // end-sanitize-vr4xxx
2968 // start-sanitize-vr4320
2970 // end-sanitize-vr4320
2972 do_multu (SD_, RS, RT, 0);
2975 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2976 "multu r<RD>, r<RS>, r<RT>"
2978 // start-sanitize-cygnus
2980 // end-sanitize-cygnus
2981 // start-sanitize-r5900
2983 // end-sanitize-r5900
2985 // start-sanitize-tx19
2987 // end-sanitize-tx19
2989 do_multu (SD_, RS, RT, 0);
2993 :function:::void:do_nor:int rs, int rt, int rd
2995 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2996 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2997 TRACE_ALU_RESULT (GPR[rd]);
3000 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
3001 "nor r<RD>, r<RS>, r<RT>"
3002 *mipsI,mipsII,mipsIII,mipsIV:
3005 // start-sanitize-vr4xxx
3007 // end-sanitize-vr4xxx
3008 // start-sanitize-vr4320
3010 // end-sanitize-vr4320
3011 // start-sanitize-cygnus
3013 // end-sanitize-cygnus
3014 // start-sanitize-r5900
3016 // end-sanitize-r5900
3018 // start-sanitize-tx19
3020 // end-sanitize-tx19
3022 do_nor (SD_, RS, RT, RD);
3026 :function:::void:do_or:int rs, int rt, int rd
3028 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3029 GPR[rd] = (GPR[rs] | GPR[rt]);
3030 TRACE_ALU_RESULT (GPR[rd]);
3033 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
3034 "or r<RD>, r<RS>, r<RT>"
3035 *mipsI,mipsII,mipsIII,mipsIV:
3038 // start-sanitize-vr4xxx
3040 // end-sanitize-vr4xxx
3041 // start-sanitize-vr4320
3043 // end-sanitize-vr4320
3044 // start-sanitize-cygnus
3046 // end-sanitize-cygnus
3047 // start-sanitize-r5900
3049 // end-sanitize-r5900
3051 // start-sanitize-tx19
3053 // end-sanitize-tx19
3055 do_or (SD_, RS, RT, RD);
3060 :function:::void:do_ori:int rs, int rt, unsigned immediate
3062 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3063 GPR[rt] = (GPR[rs] | immediate);
3064 TRACE_ALU_RESULT (GPR[rt]);
3067 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
3068 "ori r<RT>, r<RS>, <IMMEDIATE>"
3069 *mipsI,mipsII,mipsIII,mipsIV:
3072 // start-sanitize-vr4xxx
3074 // end-sanitize-vr4xxx
3075 // start-sanitize-vr4320
3077 // end-sanitize-vr4320
3078 // start-sanitize-cygnus
3080 // end-sanitize-cygnus
3081 // start-sanitize-r5900
3083 // end-sanitize-r5900
3085 // start-sanitize-tx19
3087 // end-sanitize-tx19
3089 do_ori (SD_, RS, RT, IMMEDIATE);
3093 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
3096 // start-sanitize-vr4320
3098 // end-sanitize-vr4320
3099 // start-sanitize-cygnus
3101 // end-sanitize-cygnus
3102 // start-sanitize-r5900
3104 // end-sanitize-r5900
3106 unsigned32 instruction = instruction_0;
3107 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3108 int hint = ((instruction >> 16) & 0x0000001F);
3109 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3111 address_word vaddr = ((unsigned64)op1 + offset);
3115 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3116 Prefetch(uncached,paddr,vaddr,isDATA,hint);
3121 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
3123 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3124 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3125 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3132 vaddr = base + offset;
3133 if ((vaddr & access) != 0)
3135 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
3137 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3138 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3139 byte = ((vaddr & mask) ^ bigendiancpu);
3140 memval = (word << (8 * byte));
3141 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
3145 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
3146 "sb r<RT>, <OFFSET>(r<BASE>)"
3147 *mipsI,mipsII,mipsIII,mipsIV:
3150 // start-sanitize-vr4xxx
3152 // end-sanitize-vr4xxx
3153 // start-sanitize-vr4320
3155 // end-sanitize-vr4320
3156 // start-sanitize-cygnus
3158 // end-sanitize-cygnus
3159 // start-sanitize-r5900
3161 // end-sanitize-r5900
3163 // start-sanitize-tx19
3165 // end-sanitize-tx19
3167 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3171 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
3172 "sc r<RT>, <OFFSET>(r<BASE>)"
3178 // start-sanitize-vr4xxx
3180 // end-sanitize-vr4xxx
3181 // start-sanitize-vr4320
3183 // end-sanitize-vr4320
3184 // start-sanitize-cygnus
3186 // end-sanitize-cygnus
3187 // start-sanitize-r5900
3189 // end-sanitize-r5900
3190 // start-sanitize-tx19
3192 // end-sanitize-tx19
3194 unsigned32 instruction = instruction_0;
3195 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3196 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3197 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3199 address_word vaddr = ((unsigned64)op1 + offset);
3202 if ((vaddr & 3) != 0)
3204 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3208 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3210 unsigned64 memval = 0;
3211 unsigned64 memval1 = 0;
3212 unsigned64 mask = 0x7;
3214 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3215 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3216 memval = ((unsigned64) op2 << (8 * byte));
3219 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3221 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
3228 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3229 "scd r<RT>, <OFFSET>(r<BASE>)"
3234 // start-sanitize-vr4xxx
3236 // end-sanitize-vr4xxx
3237 // start-sanitize-vr4320
3239 // end-sanitize-vr4320
3240 // start-sanitize-cygnus
3242 // end-sanitize-cygnus
3243 // start-sanitize-r5900
3245 // end-sanitize-r5900
3246 // start-sanitize-tx19
3248 // end-sanitize-tx19
3250 unsigned32 instruction = instruction_0;
3251 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3252 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3253 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3255 address_word vaddr = ((unsigned64)op1 + offset);
3258 if ((vaddr & 7) != 0)
3260 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3264 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3266 unsigned64 memval = 0;
3267 unsigned64 memval1 = 0;
3271 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3273 GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
3280 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3281 "sd r<RT>, <OFFSET>(r<BASE>)"
3286 // start-sanitize-vr4xxx
3288 // end-sanitize-vr4xxx
3289 // start-sanitize-vr4320
3291 // end-sanitize-vr4320
3292 // start-sanitize-cygnus
3294 // end-sanitize-cygnus
3295 // start-sanitize-r5900
3297 // end-sanitize-r5900
3298 // start-sanitize-tx19
3300 // end-sanitize-tx19
3302 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3306 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3307 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3313 // start-sanitize-vr4xxx
3315 // end-sanitize-vr4xxx
3316 // start-sanitize-vr4320
3318 // end-sanitize-vr4320
3319 // start-sanitize-cygnus
3321 // end-sanitize-cygnus
3322 // start-sanitize-tx19
3324 // end-sanitize-tx19
3326 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3330 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3331 "sdl r<RT>, <OFFSET>(r<BASE>)"
3336 // start-sanitize-vr4xxx
3338 // end-sanitize-vr4xxx
3339 // start-sanitize-vr4320
3341 // end-sanitize-vr4320
3342 // start-sanitize-cygnus
3344 // end-sanitize-cygnus
3345 // start-sanitize-r5900
3347 // end-sanitize-r5900
3348 // start-sanitize-tx19
3350 // end-sanitize-tx19
3352 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3356 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3357 "sdr r<RT>, <OFFSET>(r<BASE>)"
3362 // start-sanitize-vr4xxx
3364 // end-sanitize-vr4xxx
3365 // start-sanitize-vr4320
3367 // end-sanitize-vr4320
3368 // start-sanitize-cygnus
3370 // end-sanitize-cygnus
3371 // start-sanitize-r5900
3373 // end-sanitize-r5900
3374 // start-sanitize-tx19
3376 // end-sanitize-tx19
3378 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3382 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3383 "sh r<RT>, <OFFSET>(r<BASE>)"
3384 *mipsI,mipsII,mipsIII,mipsIV:
3387 // start-sanitize-vr4xxx
3389 // end-sanitize-vr4xxx
3390 // start-sanitize-vr4320
3392 // end-sanitize-vr4320
3393 // start-sanitize-cygnus
3395 // end-sanitize-cygnus
3396 // start-sanitize-r5900
3398 // end-sanitize-r5900
3400 // start-sanitize-tx19
3402 // end-sanitize-tx19
3404 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3408 :function:::void:do_sll:int rt, int rd, int shift
3410 unsigned32 temp = (GPR[rt] << shift);
3411 TRACE_ALU_INPUT2 (GPR[rt], shift);
3412 GPR[rd] = EXTEND32 (temp);
3413 TRACE_ALU_RESULT (GPR[rd]);
3416 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
3417 "sll r<RD>, r<RT>, <SHIFT>"
3418 *mipsI,mipsII,mipsIII,mipsIV:
3421 // start-sanitize-vr4xxx
3423 // end-sanitize-vr4xxx
3424 // start-sanitize-vr4320
3426 // end-sanitize-vr4320
3427 // start-sanitize-cygnus
3429 // end-sanitize-cygnus
3430 // start-sanitize-r5900
3432 // end-sanitize-r5900
3434 // start-sanitize-tx19
3436 // end-sanitize-tx19
3438 do_sll (SD_, RT, RD, SHIFT);
3442 :function:::void:do_sllv:int rs, int rt, int rd
3444 int s = MASKED (GPR[rs], 4, 0);
3445 unsigned32 temp = (GPR[rt] << s);
3446 TRACE_ALU_INPUT2 (GPR[rt], s);
3447 GPR[rd] = EXTEND32 (temp);
3448 TRACE_ALU_RESULT (GPR[rd]);
3451 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
3452 "sllv r<RD>, r<RT>, r<RS>"
3453 *mipsI,mipsII,mipsIII,mipsIV:
3456 // start-sanitize-vr4xxx
3458 // end-sanitize-vr4xxx
3459 // start-sanitize-vr4320
3461 // end-sanitize-vr4320
3462 // start-sanitize-cygnus
3464 // end-sanitize-cygnus
3465 // start-sanitize-r5900
3467 // end-sanitize-r5900
3469 // start-sanitize-tx19
3471 // end-sanitize-tx19
3473 do_sllv (SD_, RS, RT, RD);
3477 :function:::void:do_slt:int rs, int rt, int rd
3479 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3480 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3481 TRACE_ALU_RESULT (GPR[rd]);
3484 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3485 "slt r<RD>, r<RS>, r<RT>"
3486 *mipsI,mipsII,mipsIII,mipsIV:
3489 // start-sanitize-vr4xxx
3491 // end-sanitize-vr4xxx
3492 // start-sanitize-vr4320
3494 // end-sanitize-vr4320
3495 // start-sanitize-cygnus
3497 // end-sanitize-cygnus
3498 // start-sanitize-r5900
3500 // end-sanitize-r5900
3502 // start-sanitize-tx19
3504 // end-sanitize-tx19
3506 do_slt (SD_, RS, RT, RD);
3510 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3512 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3513 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3514 TRACE_ALU_RESULT (GPR[rt]);
3517 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3518 "slti r<RT>, r<RS>, <IMMEDIATE>"
3519 *mipsI,mipsII,mipsIII,mipsIV:
3522 // start-sanitize-vr4xxx
3524 // end-sanitize-vr4xxx
3525 // start-sanitize-vr4320
3527 // end-sanitize-vr4320
3528 // start-sanitize-cygnus
3530 // end-sanitize-cygnus
3531 // start-sanitize-r5900
3533 // end-sanitize-r5900
3535 // start-sanitize-tx19
3537 // end-sanitize-tx19
3539 do_slti (SD_, RS, RT, IMMEDIATE);
3543 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3545 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3546 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3547 TRACE_ALU_RESULT (GPR[rt]);
3550 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3551 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3552 *mipsI,mipsII,mipsIII,mipsIV:
3555 // start-sanitize-vr4xxx
3557 // end-sanitize-vr4xxx
3558 // start-sanitize-vr4320
3560 // end-sanitize-vr4320
3561 // start-sanitize-cygnus
3563 // end-sanitize-cygnus
3564 // start-sanitize-r5900
3566 // end-sanitize-r5900
3568 // start-sanitize-tx19
3570 // end-sanitize-tx19
3572 do_sltiu (SD_, RS, RT, IMMEDIATE);
3577 :function:::void:do_sltu:int rs, int rt, int rd
3579 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3580 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3581 TRACE_ALU_RESULT (GPR[rd]);
3584 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3585 "sltu r<RD>, r<RS>, r<RT>"
3586 *mipsI,mipsII,mipsIII,mipsIV:
3589 // start-sanitize-vr4xxx
3591 // end-sanitize-vr4xxx
3592 // start-sanitize-vr4320
3594 // end-sanitize-vr4320
3595 // start-sanitize-cygnus
3597 // end-sanitize-cygnus
3598 // start-sanitize-r5900
3600 // end-sanitize-r5900
3602 // start-sanitize-tx19
3604 // end-sanitize-tx19
3606 do_sltu (SD_, RS, RT, RD);
3610 :function:::void:do_sra:int rt, int rd, int shift
3612 signed32 temp = (signed32) GPR[rt] >> shift;
3613 TRACE_ALU_INPUT2 (GPR[rt], shift);
3614 GPR[rd] = EXTEND32 (temp);
3615 TRACE_ALU_RESULT (GPR[rd]);
3618 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3619 "sra r<RD>, r<RT>, <SHIFT>"
3620 *mipsI,mipsII,mipsIII,mipsIV:
3623 // start-sanitize-vr4xxx
3625 // end-sanitize-vr4xxx
3626 // start-sanitize-vr4320
3628 // end-sanitize-vr4320
3629 // start-sanitize-cygnus
3631 // end-sanitize-cygnus
3632 // start-sanitize-r5900
3634 // end-sanitize-r5900
3636 // start-sanitize-tx19
3638 // end-sanitize-tx19
3640 do_sra (SD_, RT, RD, SHIFT);
3645 :function:::void:do_srav:int rs, int rt, int rd
3647 int s = MASKED (GPR[rs], 4, 0);
3648 signed32 temp = (signed32) GPR[rt] >> s;
3649 TRACE_ALU_INPUT2 (GPR[rt], s);
3650 GPR[rd] = EXTEND32 (temp);
3651 TRACE_ALU_RESULT (GPR[rd]);
3654 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3655 "srav r<RD>, r<RT>, r<RS>"
3656 *mipsI,mipsII,mipsIII,mipsIV:
3659 // start-sanitize-vr4xxx
3661 // end-sanitize-vr4xxx
3662 // start-sanitize-vr4320
3664 // end-sanitize-vr4320
3665 // start-sanitize-cygnus
3667 // end-sanitize-cygnus
3668 // start-sanitize-r5900
3670 // end-sanitize-r5900
3672 // start-sanitize-tx19
3674 // end-sanitize-tx19
3676 do_srav (SD_, RS, RT, RD);
3681 :function:::void:do_srl:int rt, int rd, int shift
3683 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3684 TRACE_ALU_INPUT2 (GPR[rt], shift);
3685 GPR[rd] = EXTEND32 (temp);
3686 TRACE_ALU_RESULT (GPR[rd]);
3689 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3690 "srl r<RD>, r<RT>, <SHIFT>"
3691 *mipsI,mipsII,mipsIII,mipsIV:
3694 // start-sanitize-vr4xxx
3696 // end-sanitize-vr4xxx
3697 // start-sanitize-vr4320
3699 // end-sanitize-vr4320
3700 // start-sanitize-cygnus
3702 // end-sanitize-cygnus
3703 // start-sanitize-r5900
3705 // end-sanitize-r5900
3707 // start-sanitize-tx19
3709 // end-sanitize-tx19
3711 do_srl (SD_, RT, RD, SHIFT);
3715 :function:::void:do_srlv:int rs, int rt, int rd
3717 int s = MASKED (GPR[rs], 4, 0);
3718 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3719 TRACE_ALU_INPUT2 (GPR[rt], s);
3720 GPR[rd] = EXTEND32 (temp);
3721 TRACE_ALU_RESULT (GPR[rd]);
3724 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3725 "srlv r<RD>, r<RT>, r<RS>"
3726 *mipsI,mipsII,mipsIII,mipsIV:
3729 // start-sanitize-vr4xxx
3731 // end-sanitize-vr4xxx
3732 // start-sanitize-vr4320
3734 // end-sanitize-vr4320
3735 // start-sanitize-cygnus
3737 // end-sanitize-cygnus
3738 // start-sanitize-r5900
3740 // end-sanitize-r5900
3742 // start-sanitize-tx19
3744 // end-sanitize-tx19
3746 do_srlv (SD_, RS, RT, RD);
3750 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3751 "sub r<RD>, r<RS>, r<RT>"
3752 *mipsI,mipsII,mipsIII,mipsIV:
3755 // start-sanitize-vr4xxx
3757 // end-sanitize-vr4xxx
3758 // start-sanitize-vr4320
3760 // end-sanitize-vr4320
3761 // start-sanitize-cygnus
3763 // end-sanitize-cygnus
3764 // start-sanitize-r5900
3766 // end-sanitize-r5900
3768 // start-sanitize-tx19
3770 // end-sanitize-tx19
3772 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3774 ALU32_BEGIN (GPR[RS]);
3775 ALU32_SUB (GPR[RT]);
3776 ALU32_END (GPR[RD]);
3778 TRACE_ALU_RESULT (GPR[RD]);
3782 :function:::void:do_subu:int rs, int rt, int rd
3784 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3785 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3786 TRACE_ALU_RESULT (GPR[rd]);
3789 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3790 "subu r<RD>, r<RS>, r<RT>"
3791 *mipsI,mipsII,mipsIII,mipsIV:
3794 // start-sanitize-vr4xxx
3796 // end-sanitize-vr4xxx
3797 // start-sanitize-vr4320
3799 // end-sanitize-vr4320
3800 // start-sanitize-cygnus
3802 // end-sanitize-cygnus
3803 // start-sanitize-r5900
3805 // end-sanitize-r5900
3807 // start-sanitize-tx19
3809 // end-sanitize-tx19
3811 do_subu (SD_, RS, RT, RD);
3815 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3816 "sw r<RT>, <OFFSET>(r<BASE>)"
3817 *mipsI,mipsII,mipsIII,mipsIV:
3819 // start-sanitize-vr4xxx
3821 // end-sanitize-vr4xxx
3822 // start-sanitize-tx19
3824 // end-sanitize-tx19
3826 // start-sanitize-vr4320
3828 // end-sanitize-vr4320
3830 // start-sanitize-cygnus
3832 // end-sanitize-cygnus
3833 // start-sanitize-r5900
3835 // end-sanitize-r5900
3837 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3841 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3842 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3843 *mipsI,mipsII,mipsIII,mipsIV:
3846 // start-sanitize-vr4xxx
3848 // end-sanitize-vr4xxx
3849 // start-sanitize-vr4320
3851 // end-sanitize-vr4320
3852 // start-sanitize-cygnus
3854 // end-sanitize-cygnus
3856 // start-sanitize-tx19
3858 // end-sanitize-tx19
3860 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3865 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3867 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3868 address_word reverseendian = (ReverseEndian ? -1 : 0);
3869 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3879 vaddr = base + offset;
3880 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3881 paddr = (paddr ^ (reverseendian & mask));
3882 if (BigEndianMem == 0)
3883 paddr = paddr & ~access;
3885 /* compute where within the word/mem we are */
3886 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3887 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3888 nr_lhs_bits = 8 * byte + 8;
3889 nr_rhs_bits = 8 * access - 8 * byte;
3890 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3891 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3892 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3893 (long) ((unsigned64) paddr >> 32), (long) paddr,
3894 word, byte, nr_lhs_bits, nr_rhs_bits); */
3898 memval = (rt >> nr_rhs_bits);
3902 memval = (rt << nr_lhs_bits);
3904 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3905 (long) ((unsigned64) rt >> 32), (long) rt,
3906 (long) ((unsigned64) memval >> 32), (long) memval); */
3907 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3911 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3912 "swl r<RT>, <OFFSET>(r<BASE>)"
3913 *mipsI,mipsII,mipsIII,mipsIV:
3916 // start-sanitize-vr4xxx
3918 // end-sanitize-vr4xxx
3919 // start-sanitize-vr4320
3921 // end-sanitize-vr4320
3922 // start-sanitize-cygnus
3924 // end-sanitize-cygnus
3925 // start-sanitize-r5900
3927 // end-sanitize-r5900
3929 // start-sanitize-tx19
3931 // end-sanitize-tx19
3933 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3937 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3939 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3940 address_word reverseendian = (ReverseEndian ? -1 : 0);
3941 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3948 vaddr = base + offset;
3949 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3950 paddr = (paddr ^ (reverseendian & mask));
3951 if (BigEndianMem != 0)
3953 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3954 memval = (rt << (byte * 8));
3955 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3958 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3959 "swr r<RT>, <OFFSET>(r<BASE>)"
3960 *mipsI,mipsII,mipsIII,mipsIV:
3963 // start-sanitize-vr4xxx
3965 // end-sanitize-vr4xxx
3966 // start-sanitize-vr4320
3968 // end-sanitize-vr4320
3969 // start-sanitize-cygnus
3971 // end-sanitize-cygnus
3972 // start-sanitize-r5900
3974 // end-sanitize-r5900
3976 // start-sanitize-tx19
3978 // end-sanitize-tx19
3980 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3984 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3992 // start-sanitize-vr4xxx
3994 // end-sanitize-vr4xxx
3995 // start-sanitize-vr4320
3997 // end-sanitize-vr4320
3998 // start-sanitize-cygnus
4000 // end-sanitize-cygnus
4001 // start-sanitize-r5900
4003 // end-sanitize-r5900
4005 // start-sanitize-tx19
4007 // end-sanitize-tx19
4009 SyncOperation (STYPE);
4013 000000,20.CODE,001100:SPECIAL:32::SYSCALL
4015 *mipsI,mipsII,mipsIII,mipsIV:
4018 // start-sanitize-vr4xxx
4020 // end-sanitize-vr4xxx
4021 // start-sanitize-vr4320
4023 // end-sanitize-vr4320
4024 // start-sanitize-cygnus
4026 // end-sanitize-cygnus
4027 // start-sanitize-r5900
4029 // end-sanitize-r5900
4031 // start-sanitize-tx19
4033 // end-sanitize-tx19
4035 SignalException(SystemCall, instruction_0);
4039 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
4046 // start-sanitize-vr4xxx
4048 // end-sanitize-vr4xxx
4049 // start-sanitize-vr4320
4051 // end-sanitize-vr4320
4052 // start-sanitize-cygnus
4054 // end-sanitize-cygnus
4055 // start-sanitize-r5900
4057 // end-sanitize-r5900
4058 // start-sanitize-tx19
4060 // end-sanitize-tx19
4062 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
4063 SignalException(Trap, instruction_0);
4067 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
4068 "teqi r<RS>, <IMMEDIATE>"
4074 // start-sanitize-vr4xxx
4076 // end-sanitize-vr4xxx
4077 // start-sanitize-vr4320
4079 // end-sanitize-vr4320
4080 // start-sanitize-cygnus
4082 // end-sanitize-cygnus
4083 // start-sanitize-r5900
4085 // end-sanitize-r5900
4086 // start-sanitize-tx19
4088 // end-sanitize-tx19
4090 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
4091 SignalException(Trap, instruction_0);
4095 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
4102 // start-sanitize-vr4xxx
4104 // end-sanitize-vr4xxx
4105 // start-sanitize-vr4320
4107 // end-sanitize-vr4320
4108 // start-sanitize-cygnus
4110 // end-sanitize-cygnus
4111 // start-sanitize-r5900
4113 // end-sanitize-r5900
4114 // start-sanitize-tx19
4116 // end-sanitize-tx19
4118 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
4119 SignalException(Trap, instruction_0);
4123 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
4124 "tgei r<RS>, <IMMEDIATE>"
4130 // start-sanitize-vr4xxx
4132 // end-sanitize-vr4xxx
4133 // start-sanitize-vr4320
4135 // end-sanitize-vr4320
4136 // start-sanitize-cygnus
4138 // end-sanitize-cygnus
4139 // start-sanitize-r5900
4141 // end-sanitize-r5900
4142 // start-sanitize-tx19
4144 // end-sanitize-tx19
4146 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
4147 SignalException(Trap, instruction_0);
4151 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
4152 "tgeiu r<RS>, <IMMEDIATE>"
4158 // start-sanitize-vr4xxx
4160 // end-sanitize-vr4xxx
4161 // start-sanitize-vr4320
4163 // end-sanitize-vr4320
4164 // start-sanitize-cygnus
4166 // end-sanitize-cygnus
4167 // start-sanitize-r5900
4169 // end-sanitize-r5900
4170 // start-sanitize-tx19
4172 // end-sanitize-tx19
4174 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
4175 SignalException(Trap, instruction_0);
4179 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
4186 // start-sanitize-vr4xxx
4188 // end-sanitize-vr4xxx
4189 // start-sanitize-vr4320
4191 // end-sanitize-vr4320
4192 // start-sanitize-cygnus
4194 // end-sanitize-cygnus
4195 // start-sanitize-r5900
4197 // end-sanitize-r5900
4198 // start-sanitize-tx19
4200 // end-sanitize-tx19
4202 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
4203 SignalException(Trap, instruction_0);
4207 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
4214 // start-sanitize-vr4xxx
4216 // end-sanitize-vr4xxx
4217 // start-sanitize-vr4320
4219 // end-sanitize-vr4320
4220 // start-sanitize-cygnus
4222 // end-sanitize-cygnus
4223 // start-sanitize-r5900
4225 // end-sanitize-r5900
4226 // start-sanitize-tx19
4228 // end-sanitize-tx19
4230 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
4231 SignalException(Trap, instruction_0);
4235 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
4236 "tlti r<RS>, <IMMEDIATE>"
4242 // start-sanitize-vr4xxx
4244 // end-sanitize-vr4xxx
4245 // start-sanitize-vr4320
4247 // end-sanitize-vr4320
4248 // start-sanitize-cygnus
4250 // end-sanitize-cygnus
4251 // start-sanitize-r5900
4253 // end-sanitize-r5900
4254 // start-sanitize-tx19
4256 // end-sanitize-tx19
4258 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
4259 SignalException(Trap, instruction_0);
4263 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
4264 "tltiu r<RS>, <IMMEDIATE>"
4270 // start-sanitize-vr4xxx
4272 // end-sanitize-vr4xxx
4273 // start-sanitize-vr4320
4275 // end-sanitize-vr4320
4276 // start-sanitize-cygnus
4278 // end-sanitize-cygnus
4279 // start-sanitize-r5900
4281 // end-sanitize-r5900
4282 // start-sanitize-tx19
4284 // end-sanitize-tx19
4286 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
4287 SignalException(Trap, instruction_0);
4291 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
4298 // start-sanitize-vr4xxx
4300 // end-sanitize-vr4xxx
4301 // start-sanitize-vr4320
4303 // end-sanitize-vr4320
4304 // start-sanitize-cygnus
4306 // end-sanitize-cygnus
4307 // start-sanitize-r5900
4309 // end-sanitize-r5900
4310 // start-sanitize-tx19
4312 // end-sanitize-tx19
4314 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
4315 SignalException(Trap, instruction_0);
4319 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
4326 // start-sanitize-vr4xxx
4328 // end-sanitize-vr4xxx
4329 // start-sanitize-vr4320
4331 // end-sanitize-vr4320
4332 // start-sanitize-cygnus
4334 // end-sanitize-cygnus
4335 // start-sanitize-r5900
4337 // end-sanitize-r5900
4338 // start-sanitize-tx19
4340 // end-sanitize-tx19
4342 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
4343 SignalException(Trap, instruction_0);
4347 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
4348 "tne r<RS>, <IMMEDIATE>"
4354 // start-sanitize-vr4xxx
4356 // end-sanitize-vr4xxx
4357 // start-sanitize-vr4320
4359 // end-sanitize-vr4320
4360 // start-sanitize-cygnus
4362 // end-sanitize-cygnus
4363 // start-sanitize-r5900
4365 // end-sanitize-r5900
4366 // start-sanitize-tx19
4368 // end-sanitize-tx19
4370 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
4371 SignalException(Trap, instruction_0);
4375 :function:::void:do_xor:int rs, int rt, int rd
4377 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4378 GPR[rd] = GPR[rs] ^ GPR[rt];
4379 TRACE_ALU_RESULT (GPR[rd]);
4382 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
4383 "xor r<RD>, r<RS>, r<RT>"
4384 *mipsI,mipsII,mipsIII,mipsIV:
4387 // start-sanitize-vr4xxx
4389 // end-sanitize-vr4xxx
4390 // start-sanitize-vr4320
4392 // end-sanitize-vr4320
4393 // start-sanitize-cygnus
4395 // end-sanitize-cygnus
4396 // start-sanitize-r5900
4398 // end-sanitize-r5900
4400 // start-sanitize-tx19
4402 // end-sanitize-tx19
4404 do_xor (SD_, RS, RT, RD);
4408 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
4410 TRACE_ALU_INPUT2 (GPR[rs], immediate);
4411 GPR[rt] = GPR[rs] ^ immediate;
4412 TRACE_ALU_RESULT (GPR[rt]);
4415 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
4416 "xori r<RT>, r<RS>, <IMMEDIATE>"
4417 *mipsI,mipsII,mipsIII,mipsIV:
4420 // start-sanitize-vr4xxx
4422 // end-sanitize-vr4xxx
4423 // start-sanitize-vr4320
4425 // end-sanitize-vr4320
4426 // start-sanitize-cygnus
4428 // end-sanitize-cygnus
4429 // start-sanitize-r5900
4431 // end-sanitize-r5900
4433 // start-sanitize-tx19
4435 // end-sanitize-tx19
4437 do_xori (SD_, RS, RT, IMMEDIATE);
4442 // MIPS Architecture:
4444 // FPU Instruction Set (COP1 & COP1X)
4452 case fmt_single: return "s";
4453 case fmt_double: return "d";
4454 case fmt_word: return "w";
4455 case fmt_long: return "l";
4456 default: return "?";
4466 default: return "?";
4486 :%s::::COND:int cond
4490 case 00: return "f";
4491 case 01: return "un";
4492 case 02: return "eq";
4493 case 03: return "ueq";
4494 case 04: return "olt";
4495 case 05: return "ult";
4496 case 06: return "ole";
4497 case 07: return "ule";
4498 case 010: return "sf";
4499 case 011: return "ngle";
4500 case 012: return "seq";
4501 case 013: return "ngl";
4502 case 014: return "lt";
4503 case 015: return "nge";
4504 case 016: return "le";
4505 case 017: return "ngt";
4506 default: return "?";
4511 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4512 "abs.%s<FMT> f<FD>, f<FS>"
4513 *mipsI,mipsII,mipsIII,mipsIV:
4516 // start-sanitize-vr4xxx
4518 // end-sanitize-vr4xxx
4519 // start-sanitize-vr4320
4521 // end-sanitize-vr4320
4522 // start-sanitize-cygnus
4524 // end-sanitize-cygnus
4526 // start-sanitize-tx19
4528 // end-sanitize-tx19
4530 unsigned32 instruction = instruction_0;
4531 int destreg = ((instruction >> 6) & 0x0000001F);
4532 int fs = ((instruction >> 11) & 0x0000001F);
4533 int format = ((instruction >> 21) & 0x00000007);
4535 if ((format != fmt_single) && (format != fmt_double))
4536 SignalException(ReservedInstruction,instruction);
4538 StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
4544 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4545 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4546 *mipsI,mipsII,mipsIII,mipsIV:
4549 // start-sanitize-vr4xxx
4551 // end-sanitize-vr4xxx
4552 // start-sanitize-vr4320
4554 // end-sanitize-vr4320
4555 // start-sanitize-cygnus
4557 // end-sanitize-cygnus
4559 // start-sanitize-tx19
4561 // end-sanitize-tx19
4563 unsigned32 instruction = instruction_0;
4564 int destreg = ((instruction >> 6) & 0x0000001F);
4565 int fs = ((instruction >> 11) & 0x0000001F);
4566 int ft = ((instruction >> 16) & 0x0000001F);
4567 int format = ((instruction >> 21) & 0x00000007);
4569 if ((format != fmt_single) && (format != fmt_double))
4570 SignalException(ReservedInstruction, instruction);
4572 StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
4583 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4584 "bc1%s<TF>%s<ND> <OFFSET>"
4585 *mipsI,mipsII,mipsIII:
4586 // start-sanitize-r5900
4588 // end-sanitize-r5900
4590 check_branch_bug ();
4591 TRACE_BRANCH_INPUT (PREVCOC1());
4592 if (PREVCOC1() == TF)
4594 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4595 TRACE_BRANCH_RESULT (dest);
4596 mark_branch_bug (dest);
4601 TRACE_BRANCH_RESULT (0);
4602 NULLIFY_NEXT_INSTRUCTION ();
4606 TRACE_BRANCH_RESULT (NIA);
4610 // start-sanitize-vr4xxx
4611 // FIXME: vr4100,vr4320, and 4121 all should be in the
4612 // previous insn, but the renameing thing wasn't working
4613 // so I cheated -gavin
4614 // end-sanitize-vr4xxx
4615 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4616 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4617 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4621 // start-sanitize-vr4320
4623 // end-sanitize-vr4320
4624 // start-sanitize-vr4xxx
4626 // end-sanitize-vr4xxx
4627 // start-sanitize-cygnus
4629 // end-sanitize-cygnus
4631 // start-sanitize-tx19
4633 // end-sanitize-tx19
4635 check_branch_bug ();
4636 if (GETFCC(CC) == TF)
4638 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4639 mark_branch_bug (dest);
4644 NULLIFY_NEXT_INSTRUCTION ();
4657 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4659 if ((fmt != fmt_single) && (fmt != fmt_double))
4660 SignalException (ReservedInstruction, insn);
4667 unsigned64 ofs = ValueFPR (fs, fmt);
4668 unsigned64 oft = ValueFPR (ft, fmt);
4669 if (NaN (ofs, fmt) || NaN (oft, fmt))
4671 if (FCSR & FP_ENABLE (IO))
4673 FCSR |= FP_CAUSE (IO);
4674 SignalExceptionFPE ();
4682 less = Less (ofs, oft, fmt);
4683 equal = Equal (ofs, oft, fmt);
4686 condition = (((cond & (1 << 2)) && less)
4687 || ((cond & (1 << 1)) && equal)
4688 || ((cond & (1 << 0)) && unordered));
4689 SETFCC (cc, condition);
4693 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
4694 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4695 *mipsI,mipsII,mipsIII:
4697 do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4700 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
4701 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4702 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4706 // start-sanitize-vr4xxx
4708 // end-sanitize-vr4xxx
4709 // start-sanitize-vr4320
4711 // end-sanitize-vr4320
4712 // start-sanitize-cygnus
4714 // end-sanitize-cygnus
4716 // start-sanitize-tx19
4718 // end-sanitize-tx19
4720 do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4724 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4725 "ceil.l.%s<FMT> f<FD>, f<FS>"
4730 // start-sanitize-vr4xxx
4732 // end-sanitize-vr4xxx
4733 // start-sanitize-vr4320
4735 // end-sanitize-vr4320
4736 // start-sanitize-cygnus
4738 // end-sanitize-cygnus
4739 // start-sanitize-r5900
4741 // end-sanitize-r5900
4743 // start-sanitize-tx19
4745 // end-sanitize-tx19
4747 unsigned32 instruction = instruction_0;
4748 int destreg = ((instruction >> 6) & 0x0000001F);
4749 int fs = ((instruction >> 11) & 0x0000001F);
4750 int format = ((instruction >> 21) & 0x00000007);
4752 if ((format != fmt_single) && (format != fmt_double))
4753 SignalException(ReservedInstruction,instruction);
4755 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4760 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4766 // start-sanitize-vr4xxx
4768 // end-sanitize-vr4xxx
4769 // start-sanitize-vr4320
4771 // end-sanitize-vr4320
4772 // start-sanitize-cygnus
4774 // end-sanitize-cygnus
4775 // start-sanitize-r5900
4777 // end-sanitize-r5900
4779 // start-sanitize-tx19
4781 // end-sanitize-tx19
4783 unsigned32 instruction = instruction_0;
4784 int destreg = ((instruction >> 6) & 0x0000001F);
4785 int fs = ((instruction >> 11) & 0x0000001F);
4786 int format = ((instruction >> 21) & 0x00000007);
4788 if ((format != fmt_single) && (format != fmt_double))
4789 SignalException(ReservedInstruction,instruction);
4791 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4798 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
4799 "c%s<X>c1 r<RT>, f<FS>"
4807 PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4809 PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4811 PENDING_FILL(COCIDX,0); /* special case */
4814 { /* control from */
4816 PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4818 PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4822 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
4823 "c%s<X>c1 r<RT>, f<FS>"
4827 // start-sanitize-vr4xxx
4829 // end-sanitize-vr4xxx
4830 // start-sanitize-vr4320
4832 // end-sanitize-vr4320
4833 // start-sanitize-cygnus
4835 // end-sanitize-cygnus
4837 // start-sanitize-tx19
4839 // end-sanitize-tx19
4844 TRACE_ALU_INPUT1 (GPR[RT]);
4847 FCR0 = VL4_8(GPR[RT]);
4848 TRACE_ALU_RESULT (FCR0);
4852 FCR31 = VL4_8(GPR[RT]);
4853 SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4854 TRACE_ALU_RESULT (FCR31);
4858 TRACE_ALU_RESULT0 ();
4863 { /* control from */
4866 TRACE_ALU_INPUT1 (FCR0);
4867 GPR[RT] = SIGNEXTEND (FCR0, 32);
4871 TRACE_ALU_INPUT1 (FCR31);
4872 GPR[RT] = SIGNEXTEND (FCR31, 32);
4874 TRACE_ALU_RESULT (GPR[RT]);
4881 // FIXME: Does not correctly differentiate between mips*
4883 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4884 "cvt.d.%s<FMT> f<FD>, f<FS>"
4885 *mipsI,mipsII,mipsIII,mipsIV:
4888 // start-sanitize-vr4xxx
4890 // end-sanitize-vr4xxx
4891 // start-sanitize-vr4320
4893 // end-sanitize-vr4320
4894 // start-sanitize-cygnus
4896 // end-sanitize-cygnus
4898 // start-sanitize-tx19
4900 // end-sanitize-tx19
4902 unsigned32 instruction = instruction_0;
4903 int destreg = ((instruction >> 6) & 0x0000001F);
4904 int fs = ((instruction >> 11) & 0x0000001F);
4905 int format = ((instruction >> 21) & 0x00000007);
4907 if ((format == fmt_double) | 0)
4908 SignalException(ReservedInstruction,instruction);
4910 StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4915 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4916 "cvt.l.%s<FMT> f<FD>, f<FS>"
4921 // start-sanitize-vr4xxx
4923 // end-sanitize-vr4xxx
4924 // start-sanitize-vr4320
4926 // end-sanitize-vr4320
4927 // start-sanitize-cygnus
4929 // end-sanitize-cygnus
4931 // start-sanitize-tx19
4933 // end-sanitize-tx19
4935 unsigned32 instruction = instruction_0;
4936 int destreg = ((instruction >> 6) & 0x0000001F);
4937 int fs = ((instruction >> 11) & 0x0000001F);
4938 int format = ((instruction >> 21) & 0x00000007);
4940 if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4941 SignalException(ReservedInstruction,instruction);
4943 StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4949 // FIXME: Does not correctly differentiate between mips*
4951 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4952 "cvt.s.%s<FMT> f<FD>, f<FS>"
4953 *mipsI,mipsII,mipsIII,mipsIV:
4956 // start-sanitize-vr4xxx
4958 // end-sanitize-vr4xxx
4959 // start-sanitize-vr4320
4961 // end-sanitize-vr4320
4962 // start-sanitize-cygnus
4964 // end-sanitize-cygnus
4966 // start-sanitize-tx19
4968 // end-sanitize-tx19
4970 unsigned32 instruction = instruction_0;
4971 int destreg = ((instruction >> 6) & 0x0000001F);
4972 int fs = ((instruction >> 11) & 0x0000001F);
4973 int format = ((instruction >> 21) & 0x00000007);
4975 if ((format == fmt_single) | 0)
4976 SignalException(ReservedInstruction,instruction);
4978 StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4983 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4984 "cvt.w.%s<FMT> f<FD>, f<FS>"
4985 *mipsI,mipsII,mipsIII,mipsIV:
4988 // start-sanitize-vr4xxx
4990 // end-sanitize-vr4xxx
4991 // start-sanitize-vr4320
4993 // end-sanitize-vr4320
4994 // start-sanitize-cygnus
4996 // end-sanitize-cygnus
4998 // start-sanitize-tx19
5000 // end-sanitize-tx19
5002 unsigned32 instruction = instruction_0;
5003 int destreg = ((instruction >> 6) & 0x0000001F);
5004 int fs = ((instruction >> 11) & 0x0000001F);
5005 int format = ((instruction >> 21) & 0x00000007);
5007 if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
5008 SignalException(ReservedInstruction,instruction);
5010 StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
5015 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
5016 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
5017 *mipsI,mipsII,mipsIII,mipsIV:
5020 // start-sanitize-vr4xxx
5022 // end-sanitize-vr4xxx
5023 // start-sanitize-vr4320
5025 // end-sanitize-vr4320
5026 // start-sanitize-cygnus
5028 // end-sanitize-cygnus
5030 // start-sanitize-tx19
5032 // end-sanitize-tx19
5034 unsigned32 instruction = instruction_0;
5035 int destreg = ((instruction >> 6) & 0x0000001F);
5036 int fs = ((instruction >> 11) & 0x0000001F);
5037 int ft = ((instruction >> 16) & 0x0000001F);
5038 int format = ((instruction >> 21) & 0x00000007);
5040 if ((format != fmt_single) && (format != fmt_double))
5041 SignalException(ReservedInstruction,instruction);
5043 StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
5050 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
5051 "dm%s<X>c1 r<RT>, f<FS>"
5056 if (SizeFGR() == 64)
5057 PENDING_FILL((FS + FGRIDX),GPR[RT]);
5058 else if ((FS & 0x1) == 0)
5060 PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
5061 PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
5066 if (SizeFGR() == 64)
5067 PENDING_FILL(RT,FGR[FS]);
5068 else if ((FS & 0x1) == 0)
5069 PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
5071 PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
5074 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
5075 "dm%s<X>c1 r<RT>, f<FS>"
5079 // start-sanitize-vr4xxx
5081 // end-sanitize-vr4xxx
5082 // start-sanitize-vr4320
5084 // end-sanitize-vr4320
5085 // start-sanitize-cygnus
5087 // end-sanitize-cygnus
5088 // start-sanitize-r5900
5090 // end-sanitize-r5900
5092 // start-sanitize-tx19
5094 // end-sanitize-tx19
5098 if (SizeFGR() == 64)
5099 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
5100 else if ((FS & 0x1) == 0)
5101 StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
5105 if (SizeFGR() == 64)
5107 else if ((FS & 0x1) == 0)
5108 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
5110 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
5115 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
5116 "floor.l.%s<FMT> f<FD>, f<FS>"
5121 // start-sanitize-vr4xxx
5123 // end-sanitize-vr4xxx
5124 // start-sanitize-vr4320
5126 // end-sanitize-vr4320
5127 // start-sanitize-cygnus
5129 // end-sanitize-cygnus
5130 // start-sanitize-r5900
5132 // end-sanitize-r5900
5134 // start-sanitize-tx19
5136 // end-sanitize-tx19
5138 unsigned32 instruction = instruction_0;
5139 int destreg = ((instruction >> 6) & 0x0000001F);
5140 int fs = ((instruction >> 11) & 0x0000001F);
5141 int format = ((instruction >> 21) & 0x00000007);
5143 if ((format != fmt_single) && (format != fmt_double))
5144 SignalException(ReservedInstruction,instruction);
5146 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
5151 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
5152 "floor.w.%s<FMT> f<FD>, f<FS>"
5158 // start-sanitize-vr4xxx
5160 // end-sanitize-vr4xxx
5161 // start-sanitize-vr4320
5163 // end-sanitize-vr4320
5164 // start-sanitize-cygnus
5166 // end-sanitize-cygnus
5167 // start-sanitize-r5900
5169 // end-sanitize-r5900
5171 // start-sanitize-tx19
5173 // end-sanitize-tx19
5175 unsigned32 instruction = instruction_0;
5176 int destreg = ((instruction >> 6) & 0x0000001F);
5177 int fs = ((instruction >> 11) & 0x0000001F);
5178 int format = ((instruction >> 21) & 0x00000007);
5180 if ((format != fmt_single) && (format != fmt_double))
5181 SignalException(ReservedInstruction,instruction);
5183 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
5188 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
5189 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
5195 // start-sanitize-vr4xxx
5197 // end-sanitize-vr4xxx
5198 // start-sanitize-vr4320
5200 // end-sanitize-vr4320
5201 // start-sanitize-cygnus
5203 // end-sanitize-cygnus
5205 // start-sanitize-tx19
5207 // end-sanitize-tx19
5209 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
5213 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
5214 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5217 // start-sanitize-vr4320
5219 // end-sanitize-vr4320
5220 // start-sanitize-cygnus
5222 // end-sanitize-cygnus
5224 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
5229 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
5230 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
5231 *mipsI,mipsII,mipsIII,mipsIV:
5234 // start-sanitize-vr4xxx
5236 // end-sanitize-vr4xxx
5237 // start-sanitize-vr4320
5239 // end-sanitize-vr4320
5240 // start-sanitize-cygnus
5242 // end-sanitize-cygnus
5243 // start-sanitize-r5900
5245 // end-sanitize-r5900
5247 // start-sanitize-tx19
5249 // end-sanitize-tx19
5251 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
5255 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
5256 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
5259 // start-sanitize-vr4320
5261 // end-sanitize-vr4320
5262 // start-sanitize-cygnus
5264 // end-sanitize-cygnus
5266 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
5272 // FIXME: Not correct for mips*
5274 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
5275 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
5278 // start-sanitize-vr4320
5280 // end-sanitize-vr4320
5281 // start-sanitize-cygnus
5283 // end-sanitize-cygnus
5285 unsigned32 instruction = instruction_0;
5286 int destreg = ((instruction >> 6) & 0x0000001F);
5287 int fs = ((instruction >> 11) & 0x0000001F);
5288 int ft = ((instruction >> 16) & 0x0000001F);
5289 int fr = ((instruction >> 21) & 0x0000001F);
5291 StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
5296 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
5297 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
5300 // start-sanitize-vr4320
5302 // end-sanitize-vr4320
5303 // start-sanitize-cygnus
5305 // end-sanitize-cygnus
5307 unsigned32 instruction = instruction_0;
5308 int destreg = ((instruction >> 6) & 0x0000001F);
5309 int fs = ((instruction >> 11) & 0x0000001F);
5310 int ft = ((instruction >> 16) & 0x0000001F);
5311 int fr = ((instruction >> 21) & 0x0000001F);
5313 StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
5320 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
5321 "m%s<X>c1 r<RT>, f<FS>"
5328 if (SizeFGR() == 64)
5329 PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
5331 PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
5334 PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
5336 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
5337 "m%s<X>c1 r<RT>, f<FS>"
5341 // start-sanitize-vr4xxx
5343 // end-sanitize-vr4xxx
5344 // start-sanitize-vr4320
5346 // end-sanitize-vr4320
5347 // start-sanitize-cygnus
5349 // end-sanitize-cygnus
5351 // start-sanitize-tx19
5353 // end-sanitize-tx19
5358 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
5360 GPR[RT] = SIGNEXTEND(FGR[FS],32);
5364 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
5365 "mov.%s<FMT> f<FD>, f<FS>"
5366 *mipsI,mipsII,mipsIII,mipsIV:
5369 // start-sanitize-vr4xxx
5371 // end-sanitize-vr4xxx
5372 // start-sanitize-vr4320
5374 // end-sanitize-vr4320
5375 // start-sanitize-cygnus
5377 // end-sanitize-cygnus
5379 // start-sanitize-tx19
5381 // end-sanitize-tx19
5383 unsigned32 instruction = instruction_0;
5384 int destreg = ((instruction >> 6) & 0x0000001F);
5385 int fs = ((instruction >> 11) & 0x0000001F);
5386 int format = ((instruction >> 21) & 0x00000007);
5388 StoreFPR(destreg,format,ValueFPR(fs,format));
5394 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
5395 "mov%s<TF> r<RD>, r<RS>, <CC>"
5398 // start-sanitize-vr4320
5400 // end-sanitize-vr4320
5401 // start-sanitize-cygnus
5403 // end-sanitize-cygnus
5404 // start-sanitize-r5900
5406 // end-sanitize-r5900
5408 if (GETFCC(CC) == TF)
5414 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
5415 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
5418 // start-sanitize-vr4320
5420 // end-sanitize-vr4320
5421 // start-sanitize-cygnus
5423 // end-sanitize-cygnus
5424 // start-sanitize-r5900
5426 // end-sanitize-r5900
5428 unsigned32 instruction = instruction_0;
5429 int format = ((instruction >> 21) & 0x00000007);
5431 if (GETFCC(CC) == TF)
5432 StoreFPR (FD, format, ValueFPR (FS, format));
5434 StoreFPR (FD, format, ValueFPR (FD, format));
5439 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
5442 // start-sanitize-vr4320
5444 // end-sanitize-vr4320
5445 // start-sanitize-cygnus
5447 // end-sanitize-cygnus
5448 // start-sanitize-r5900
5450 // end-sanitize-r5900
5452 unsigned32 instruction = instruction_0;
5453 int destreg = ((instruction >> 6) & 0x0000001F);
5454 int fs = ((instruction >> 11) & 0x0000001F);
5455 int format = ((instruction >> 21) & 0x00000007);
5457 StoreFPR(destreg,format,ValueFPR(fs,format));
5465 // MOVT.fmt see MOVtf.fmt
5469 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
5470 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5473 // start-sanitize-vr4320
5475 // end-sanitize-vr4320
5476 // start-sanitize-cygnus
5478 // end-sanitize-cygnus
5479 // start-sanitize-r5900
5481 // end-sanitize-r5900
5483 unsigned32 instruction = instruction_0;
5484 int destreg = ((instruction >> 6) & 0x0000001F);
5485 int fs = ((instruction >> 11) & 0x0000001F);
5486 int format = ((instruction >> 21) & 0x00000007);
5488 StoreFPR(destreg,format,ValueFPR(fs,format));
5494 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
5495 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
5498 // start-sanitize-vr4320
5500 // end-sanitize-vr4320
5501 // start-sanitize-cygnus
5503 // end-sanitize-cygnus
5504 // start-sanitize-r5900
5506 // end-sanitize-r5900
5508 unsigned32 instruction = instruction_0;
5509 int destreg = ((instruction >> 6) & 0x0000001F);
5510 int fs = ((instruction >> 11) & 0x0000001F);
5511 int ft = ((instruction >> 16) & 0x0000001F);
5512 int fr = ((instruction >> 21) & 0x0000001F);
5514 StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
5520 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
5521 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
5524 // start-sanitize-vr4320
5526 // end-sanitize-vr4320
5527 // start-sanitize-cygnus
5529 // end-sanitize-cygnus
5530 // start-sanitize-r5900
5532 // end-sanitize-r5900
5534 unsigned32 instruction = instruction_0;
5535 int destreg = ((instruction >> 6) & 0x0000001F);
5536 int fs = ((instruction >> 11) & 0x0000001F);
5537 int ft = ((instruction >> 16) & 0x0000001F);
5538 int fr = ((instruction >> 21) & 0x0000001F);
5540 StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
5548 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
5549 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
5550 *mipsI,mipsII,mipsIII,mipsIV:
5553 // start-sanitize-vr4xxx
5555 // end-sanitize-vr4xxx
5556 // start-sanitize-vr4320
5558 // end-sanitize-vr4320
5559 // start-sanitize-cygnus
5561 // end-sanitize-cygnus
5563 // start-sanitize-tx19
5565 // end-sanitize-tx19
5567 unsigned32 instruction = instruction_0;
5568 int destreg = ((instruction >> 6) & 0x0000001F);
5569 int fs = ((instruction >> 11) & 0x0000001F);
5570 int ft = ((instruction >> 16) & 0x0000001F);
5571 int format = ((instruction >> 21) & 0x00000007);
5573 if ((format != fmt_single) && (format != fmt_double))
5574 SignalException(ReservedInstruction,instruction);
5576 StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
5581 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
5582 "neg.%s<FMT> f<FD>, f<FS>"
5583 *mipsI,mipsII,mipsIII,mipsIV:
5586 // start-sanitize-vr4xxx
5588 // end-sanitize-vr4xxx
5589 // start-sanitize-vr4320
5591 // end-sanitize-vr4320
5592 // start-sanitize-cygnus
5594 // end-sanitize-cygnus
5596 // start-sanitize-tx19
5598 // end-sanitize-tx19
5600 unsigned32 instruction = instruction_0;
5601 int destreg = ((instruction >> 6) & 0x0000001F);
5602 int fs = ((instruction >> 11) & 0x0000001F);
5603 int format = ((instruction >> 21) & 0x00000007);
5605 if ((format != fmt_single) && (format != fmt_double))
5606 SignalException(ReservedInstruction,instruction);
5608 StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
5614 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
5615 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
5618 // start-sanitize-vr4320
5620 // end-sanitize-vr4320
5621 // start-sanitize-cygnus
5623 // end-sanitize-cygnus
5625 unsigned32 instruction = instruction_0;
5626 int destreg = ((instruction >> 6) & 0x0000001F);
5627 int fs = ((instruction >> 11) & 0x0000001F);
5628 int ft = ((instruction >> 16) & 0x0000001F);
5629 int fr = ((instruction >> 21) & 0x0000001F);
5631 StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5637 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
5638 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
5641 // start-sanitize-vr4320
5643 // end-sanitize-vr4320
5644 // start-sanitize-cygnus
5646 // end-sanitize-cygnus
5648 unsigned32 instruction = instruction_0;
5649 int destreg = ((instruction >> 6) & 0x0000001F);
5650 int fs = ((instruction >> 11) & 0x0000001F);
5651 int ft = ((instruction >> 16) & 0x0000001F);
5652 int fr = ((instruction >> 21) & 0x0000001F);
5654 StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5660 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5661 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5664 // start-sanitize-vr4320
5666 // end-sanitize-vr4320
5667 // start-sanitize-cygnus
5669 // end-sanitize-cygnus
5671 unsigned32 instruction = instruction_0;
5672 int destreg = ((instruction >> 6) & 0x0000001F);
5673 int fs = ((instruction >> 11) & 0x0000001F);
5674 int ft = ((instruction >> 16) & 0x0000001F);
5675 int fr = ((instruction >> 21) & 0x0000001F);
5677 StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5683 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5684 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5687 // start-sanitize-vr4320
5689 // end-sanitize-vr4320
5690 // start-sanitize-cygnus
5692 // end-sanitize-cygnus
5694 unsigned32 instruction = instruction_0;
5695 int destreg = ((instruction >> 6) & 0x0000001F);
5696 int fs = ((instruction >> 11) & 0x0000001F);
5697 int ft = ((instruction >> 16) & 0x0000001F);
5698 int fr = ((instruction >> 21) & 0x0000001F);
5700 StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5705 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5706 "prefx <HINT>, r<INDEX>(r<BASE>)"
5709 // start-sanitize-vr4320
5711 // end-sanitize-vr4320
5712 // start-sanitize-cygnus
5714 // end-sanitize-cygnus
5716 unsigned32 instruction = instruction_0;
5717 int fs = ((instruction >> 11) & 0x0000001F);
5718 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5719 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5721 address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5724 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5725 Prefetch(uncached,paddr,vaddr,isDATA,fs);
5729 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5731 "recip.%s<FMT> f<FD>, f<FS>"
5733 // start-sanitize-vr4320
5735 // end-sanitize-vr4320
5736 // start-sanitize-cygnus
5738 // end-sanitize-cygnus
5740 unsigned32 instruction = instruction_0;
5741 int destreg = ((instruction >> 6) & 0x0000001F);
5742 int fs = ((instruction >> 11) & 0x0000001F);
5743 int format = ((instruction >> 21) & 0x00000007);
5745 if ((format != fmt_single) && (format != fmt_double))
5746 SignalException(ReservedInstruction,instruction);
5748 StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5753 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5754 "round.l.%s<FMT> f<FD>, f<FS>"
5759 // start-sanitize-vr4xxx
5761 // end-sanitize-vr4xxx
5762 // start-sanitize-vr4320
5764 // end-sanitize-vr4320
5765 // start-sanitize-cygnus
5767 // end-sanitize-cygnus
5768 // start-sanitize-r5900
5770 // end-sanitize-r5900
5772 // start-sanitize-tx19
5774 // end-sanitize-tx19
5776 unsigned32 instruction = instruction_0;
5777 int destreg = ((instruction >> 6) & 0x0000001F);
5778 int fs = ((instruction >> 11) & 0x0000001F);
5779 int format = ((instruction >> 21) & 0x00000007);
5781 if ((format != fmt_single) && (format != fmt_double))
5782 SignalException(ReservedInstruction,instruction);
5784 StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5789 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5790 "round.w.%s<FMT> f<FD>, f<FS>"
5796 // start-sanitize-vr4xxx
5798 // end-sanitize-vr4xxx
5799 // start-sanitize-vr4320
5801 // end-sanitize-vr4320
5802 // start-sanitize-cygnus
5804 // end-sanitize-cygnus
5805 // start-sanitize-r5900
5807 // end-sanitize-r5900
5809 // start-sanitize-tx19
5811 // end-sanitize-tx19
5813 unsigned32 instruction = instruction_0;
5814 int destreg = ((instruction >> 6) & 0x0000001F);
5815 int fs = ((instruction >> 11) & 0x0000001F);
5816 int format = ((instruction >> 21) & 0x00000007);
5818 if ((format != fmt_single) && (format != fmt_double))
5819 SignalException(ReservedInstruction,instruction);
5821 StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5826 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5828 "rsqrt.%s<FMT> f<FD>, f<FS>"
5830 // start-sanitize-vr4320
5832 // end-sanitize-vr4320
5833 // start-sanitize-cygnus
5835 // end-sanitize-cygnus
5837 unsigned32 instruction = instruction_0;
5838 int destreg = ((instruction >> 6) & 0x0000001F);
5839 int fs = ((instruction >> 11) & 0x0000001F);
5840 int format = ((instruction >> 21) & 0x00000007);
5842 if ((format != fmt_single) && (format != fmt_double))
5843 SignalException(ReservedInstruction,instruction);
5845 StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5850 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5851 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5857 // start-sanitize-vr4xxx
5859 // end-sanitize-vr4xxx
5860 // start-sanitize-vr4320
5862 // end-sanitize-vr4320
5863 // start-sanitize-cygnus
5865 // end-sanitize-cygnus
5867 // start-sanitize-tx19
5869 // end-sanitize-tx19
5871 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5875 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5876 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5879 // start-sanitize-vr4320
5881 // end-sanitize-vr4320
5882 // start-sanitize-cygnus
5884 // end-sanitize-cygnus
5886 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5890 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5891 "sqrt.%s<FMT> f<FD>, f<FS>"
5897 // start-sanitize-vr4xxx
5899 // end-sanitize-vr4xxx
5900 // start-sanitize-vr4320
5902 // end-sanitize-vr4320
5903 // start-sanitize-cygnus
5905 // end-sanitize-cygnus
5907 // start-sanitize-tx19
5909 // end-sanitize-tx19
5911 unsigned32 instruction = instruction_0;
5912 int destreg = ((instruction >> 6) & 0x0000001F);
5913 int fs = ((instruction >> 11) & 0x0000001F);
5914 int format = ((instruction >> 21) & 0x00000007);
5916 if ((format != fmt_single) && (format != fmt_double))
5917 SignalException(ReservedInstruction,instruction);
5919 StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5924 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5925 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5926 *mipsI,mipsII,mipsIII,mipsIV:
5929 // start-sanitize-vr4xxx
5931 // end-sanitize-vr4xxx
5932 // start-sanitize-vr4320
5934 // end-sanitize-vr4320
5935 // start-sanitize-cygnus
5937 // end-sanitize-cygnus
5939 // start-sanitize-tx19
5941 // end-sanitize-tx19
5943 unsigned32 instruction = instruction_0;
5944 int destreg = ((instruction >> 6) & 0x0000001F);
5945 int fs = ((instruction >> 11) & 0x0000001F);
5946 int ft = ((instruction >> 16) & 0x0000001F);
5947 int format = ((instruction >> 21) & 0x00000007);
5949 if ((format != fmt_single) && (format != fmt_double))
5950 SignalException(ReservedInstruction,instruction);
5952 StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5958 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5959 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5960 *mipsI,mipsII,mipsIII,mipsIV:
5963 // start-sanitize-vr4xxx
5965 // end-sanitize-vr4xxx
5966 // start-sanitize-vr4320
5968 // end-sanitize-vr4320
5969 // start-sanitize-cygnus
5971 // end-sanitize-cygnus
5972 // start-sanitize-r5900
5974 // end-sanitize-r5900
5976 // start-sanitize-tx19
5978 // end-sanitize-tx19
5980 unsigned32 instruction = instruction_0;
5981 signed_word offset = EXTEND16 (OFFSET);
5982 int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5983 signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5985 address_word vaddr = ((uword64)op1 + offset);
5988 if ((vaddr & 3) != 0)
5990 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5994 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5997 uword64 memval1 = 0;
5998 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5999 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
6000 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
6002 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
6003 byte = ((vaddr & mask) ^ bigendiancpu);
6004 memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
6005 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
6012 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
6013 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
6016 // start-sanitize-vr4320
6018 // end-sanitize-vr4320
6019 // start-sanitize-cygnus
6021 // end-sanitize-cygnus
6023 unsigned32 instruction = instruction_0;
6024 int fs = ((instruction >> 11) & 0x0000001F);
6025 signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
6026 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
6028 address_word vaddr = ((unsigned64)op1 + op2);
6031 if ((vaddr & 3) != 0)
6033 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
6037 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
6039 unsigned64 memval = 0;
6040 unsigned64 memval1 = 0;
6041 unsigned64 mask = 0x7;
6043 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
6044 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
6045 memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
6047 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
6055 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
6056 "trunc.l.%s<FMT> f<FD>, f<FS>"
6061 // start-sanitize-vr4xxx
6063 // end-sanitize-vr4xxx
6064 // start-sanitize-vr4320
6066 // end-sanitize-vr4320
6067 // start-sanitize-cygnus
6069 // end-sanitize-cygnus
6070 // start-sanitize-r5900
6072 // end-sanitize-r5900
6074 // start-sanitize-tx19
6076 // end-sanitize-tx19
6078 unsigned32 instruction = instruction_0;
6079 int destreg = ((instruction >> 6) & 0x0000001F);
6080 int fs = ((instruction >> 11) & 0x0000001F);
6081 int format = ((instruction >> 21) & 0x00000007);
6083 if ((format != fmt_single) && (format != fmt_double))
6084 SignalException(ReservedInstruction,instruction);
6086 StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
6091 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
6092 "trunc.w.%s<FMT> f<FD>, f<FS>"
6098 // start-sanitize-vr4xxx
6100 // end-sanitize-vr4xxx
6101 // start-sanitize-vr4320
6103 // end-sanitize-vr4320
6104 // start-sanitize-cygnus
6106 // end-sanitize-cygnus
6107 // start-sanitize-r5900
6109 // end-sanitize-r5900
6111 // start-sanitize-tx19
6113 // end-sanitize-tx19
6115 unsigned32 instruction = instruction_0;
6116 int destreg = ((instruction >> 6) & 0x0000001F);
6117 int fs = ((instruction >> 11) & 0x0000001F);
6118 int format = ((instruction >> 21) & 0x00000007);
6120 if ((format != fmt_single) && (format != fmt_double))
6121 SignalException(ReservedInstruction,instruction);
6123 StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
6129 // MIPS Architecture:
6131 // System Control Instruction Set (COP0)
6135 010000,01000,00000,16.OFFSET:COP0:32::BC0F
6137 *mipsI,mipsII,mipsIII,mipsIV:
6140 // start-sanitize-vr4xxx
6142 // end-sanitize-vr4xxx
6143 // start-sanitize-vr4320
6145 // end-sanitize-vr4320
6146 // start-sanitize-cygnus
6148 // end-sanitize-cygnus
6151 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
6153 *mipsI,mipsII,mipsIII,mipsIV:
6156 // start-sanitize-vr4xxx
6158 // end-sanitize-vr4xxx
6159 // start-sanitize-vr4320
6161 // end-sanitize-vr4320
6162 // start-sanitize-cygnus
6164 // end-sanitize-cygnus
6167 010000,01000,00001,16.OFFSET:COP0:32::BC0T
6169 *mipsI,mipsII,mipsIII,mipsIV:
6171 // start-sanitize-vr4xxx
6173 // end-sanitize-vr4xxx
6176 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
6178 *mipsI,mipsII,mipsIII,mipsIV:
6181 // start-sanitize-vr4xxx
6183 // end-sanitize-vr4xxx
6184 // start-sanitize-vr4320
6186 // end-sanitize-vr4320
6187 // start-sanitize-cygnus
6189 // end-sanitize-cygnus
6192 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
6197 // start-sanitize-vr4xxx
6199 // end-sanitize-vr4xxx
6200 // start-sanitize-vr4320
6202 // end-sanitize-vr4320
6203 // start-sanitize-cygnus
6205 // end-sanitize-cygnus
6207 // start-sanitize-tx19
6209 // end-sanitize-tx19
6211 unsigned32 instruction = instruction_0;
6212 signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
6213 int hint = ((instruction >> 16) & 0x0000001F);
6214 signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
6216 address_word vaddr = (op1 + offset);
6219 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
6220 CacheOp(hint,vaddr,paddr,instruction);
6225 010000,10000,000000000000000,111001:COP0:32::DI
6227 *mipsI,mipsII,mipsIII,mipsIV:
6230 // start-sanitize-vr4xxx
6232 // end-sanitize-vr4xxx
6233 // start-sanitize-vr4320
6235 // end-sanitize-vr4320
6236 // start-sanitize-cygnus
6238 // end-sanitize-cygnus
6241 010000,10000,000000000000000,111000:COP0:32::EI
6243 *mipsI,mipsII,mipsIII,mipsIV:
6246 // start-sanitize-vr4xxx
6248 // end-sanitize-vr4xxx
6249 // start-sanitize-vr4320
6251 // end-sanitize-vr4320
6252 // start-sanitize-cygnus
6254 // end-sanitize-cygnus
6257 010000,10000,000000000000000,011000:COP0:32::ERET
6263 // start-sanitize-vr4xxx
6265 // end-sanitize-vr4xxx
6266 // start-sanitize-vr4320
6268 // end-sanitize-vr4320
6269 // start-sanitize-cygnus
6271 // end-sanitize-cygnus
6272 // start-sanitize-r5900
6274 // end-sanitize-r5900
6276 if (SR & status_ERL)
6278 /* Oops, not yet available */
6279 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
6291 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
6292 "mfc0 r<RT>, r<RD> # <REGX>"
6293 *mipsI,mipsII,mipsIII,mipsIV:
6297 // start-sanitize-vr4xxx
6299 // end-sanitize-vr4xxx
6300 // start-sanitize-vr4320
6302 // end-sanitize-vr4320
6303 // start-sanitize-cygnus
6305 // end-sanitize-cygnus
6306 // start-sanitize-r5900
6308 // end-sanitize-r5900
6310 TRACE_ALU_INPUT0 ();
6311 DecodeCoproc (instruction_0);
6312 TRACE_ALU_RESULT (GPR[RT]);
6315 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
6316 "mtc0 r<RT>, r<RD> # <REGX>"
6317 *mipsI,mipsII,mipsIII,mipsIV:
6318 // start-sanitize-tx19
6320 // end-sanitize-tx19
6323 // start-sanitize-vr4xxx
6325 // end-sanitize-vr4xxx
6326 // start-sanitize-vr4320
6328 // end-sanitize-vr4320
6330 // start-sanitize-cygnus
6332 // end-sanitize-cygnus
6333 // start-sanitize-r5900
6335 // end-sanitize-r5900
6337 DecodeCoproc (instruction_0);
6341 010000,10000,000000000000000,010000:COP0:32::RFE
6343 *mipsI,mipsII,mipsIII,mipsIV:
6344 // start-sanitize-tx19
6346 // end-sanitize-tx19
6349 // start-sanitize-vr4xxx
6351 // end-sanitize-vr4xxx
6352 // start-sanitize-vr4320
6354 // end-sanitize-vr4320
6356 // start-sanitize-cygnus
6358 // end-sanitize-cygnus
6359 // start-sanitize-r5900
6361 // end-sanitize-r5900
6363 DecodeCoproc (instruction_0);
6367 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
6368 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
6369 *mipsI,mipsII,mipsIII,mipsIV:
6371 // start-sanitize-vr4xxx
6373 // end-sanitize-vr4xxx
6374 // start-sanitize-r5900
6376 // end-sanitize-r5900
6378 // start-sanitize-tx19
6380 // end-sanitize-tx19
6382 DecodeCoproc (instruction_0);
6387 010000,10000,000000000000000,001000:COP0:32::TLBP
6389 *mipsI,mipsII,mipsIII,mipsIV:
6392 // start-sanitize-vr4xxx
6394 // end-sanitize-vr4xxx
6395 // start-sanitize-vr4320
6397 // end-sanitize-vr4320
6398 // start-sanitize-cygnus
6400 // end-sanitize-cygnus
6403 010000,10000,000000000000000,000001:COP0:32::TLBR
6405 *mipsI,mipsII,mipsIII,mipsIV:
6408 // start-sanitize-vr4xxx
6410 // end-sanitize-vr4xxx
6411 // start-sanitize-vr4320
6413 // end-sanitize-vr4320
6414 // start-sanitize-cygnus
6416 // end-sanitize-cygnus
6419 010000,10000,000000000000000,000010:COP0:32::TLBWI
6421 *mipsI,mipsII,mipsIII,mipsIV:
6424 // start-sanitize-vr4xxx
6426 // end-sanitize-vr4xxx
6427 // start-sanitize-vr4320
6429 // end-sanitize-vr4320
6430 // start-sanitize-cygnus
6432 // end-sanitize-cygnus
6435 010000,10000,000000000000000,000110:COP0:32::TLBWR
6437 *mipsI,mipsII,mipsIII,mipsIV:
6440 // start-sanitize-vr4xxx
6442 // end-sanitize-vr4xxx
6443 // start-sanitize-vr4320
6445 // end-sanitize-vr4320
6446 // start-sanitize-cygnus
6448 // end-sanitize-cygnus
6452 // start-sanitize-cygnus
6453 :include:64,f::mdmx.igen
6454 // end-sanitize-cygnus
6455 // start-sanitize-r5900
6456 :include::r5900:r5900.igen
6457 // end-sanitize-r5900
6461 // start-sanitize-cygnus-never
6463 // // FIXME FIXME FIXME What is this instruction?
6464 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
6469 // // start-sanitize-r5900
6471 // // end-sanitize-r5900
6473 // // start-sanitize-tx19
6475 // // end-sanitize-tx19
6477 // unsigned32 instruction = instruction_0;
6478 // signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
6479 // signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
6480 // signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
6482 // if (CoProcPresent(3))
6483 // SignalException(CoProcessorUnusable);
6485 // SignalException(ReservedInstruction,instruction);
6489 // end-sanitize-cygnus-never
6490 // start-sanitize-cygnus-never
6492 // // FIXME FIXME FIXME What is this?
6493 // 11100,******,00001:RR:16::SDBBP
6496 // unsigned32 instruction = instruction_0;
6497 // if (have_extendval)
6498 // SignalException (ReservedInstruction, instruction);
6500 // SignalException(DebugBreakPoint,instruction);
6504 // end-sanitize-cygnus-never
6505 // start-sanitize-cygnus-never
6507 // // FIXME FIXME FIXME What is this?
6508 // 000000,********************,001110:SPECIAL:32::SDBBP
6511 // unsigned32 instruction = instruction_0;
6513 // SignalException(DebugBreakPoint,instruction);
6517 // end-sanitize-cygnus-never