4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator are defined below.
35 // When placing models in the instruction descriptions, please place
36 // them one per line, in the order given here.
40 // Instructions and related functions for these models are included in
42 :model:::mipsI:mips3000:
43 :model:::mipsII:mips6000:
44 :model:::mipsIII:mips4000:
45 :model:::mipsIV:mips8000:
46 :model:::mipsV:mipsisaV:
47 :model:::mips32:mipsisa32:
48 :model:::mips32r2:mipsisa32r2:
49 :model:::mips64:mipsisa64:
50 :model:::mips64r2:mipsisa64r2:
54 // Standard MIPS ISA instructions used for these models are listed here,
55 // as are functions needed by those standard instructions. Instructions
56 // which are model-dependent and which are not in the standard MIPS ISAs
57 // (or which pre-date or use different encodings than the standard
58 // instructions) are (for the most part) in separate .igen files.
59 :model:::vr4100:mips4100: // vr.igen
60 :model:::vr4120:mips4120:
61 :model:::vr5000:mips5000:
62 :model:::vr5400:mips5400:
63 :model:::vr5500:mips5500:
64 :model:::r3900:mips3900: // tx.igen
66 // MIPS Application Specific Extensions (ASEs)
68 // Instructions for the ASEs are in separate .igen files.
69 // ASEs add instructions on to a base ISA.
70 :model:::mips16:mips16: // m16.igen (and m16.dc)
71 :model:::mips16e:mips16e: // m16e.igen
72 :model:::mips3d:mips3d: // mips3d.igen
73 :model:::mdmx:mdmx: // mdmx.igen
74 :model:::dsp:dsp: // dsp.igen
75 :model:::smartmips:smartmips: // smartmips.igen
79 // Instructions specific to these extensions are in separate .igen files.
80 // Extensions add instructions on to a base ISA.
81 :model:::sb1:sb1: // sb1.igen
84 // Pseudo instructions known by IGEN
87 SignalException (ReservedInstruction, 0);
91 // Pseudo instructions known by interp.c
92 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
93 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
96 SignalException (ReservedInstruction, instruction_0);
103 // Simulate a 32 bit delayslot instruction
106 :function:::address_word:delayslot32:address_word target
108 instruction_word delay_insn;
109 sim_events_slip (SD, 1);
111 CIA = CIA + 4; /* NOTE not mips16 */
112 STATE |= simDELAYSLOT;
113 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
114 ENGINE_ISSUE_PREFIX_HOOK();
115 idecode_issue (CPU_, delay_insn, (CIA));
116 STATE &= ~simDELAYSLOT;
120 :function:::address_word:nullify_next_insn32:
122 sim_events_slip (SD, 1);
123 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
130 // Calculate an effective address given a base and an offset.
133 :function:::address_word:loadstore_ea:address_word base, address_word offset
145 return base + offset;
148 :function:::address_word:loadstore_ea:address_word base, address_word offset
152 #if 0 /* XXX FIXME: enable this only after some additional testing. */
153 /* If in user mode and UX is not set, use 32-bit compatibility effective
154 address computations as defined in the MIPS64 Architecture for
155 Programmers Volume III, Revision 0.95, section 4.9. */
156 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
157 == (ksu_user << status_KSU_shift))
158 return (address_word)((signed32)base + (signed32)offset);
160 return base + offset;
166 // Check that a 32-bit register value is properly sign-extended.
167 // (See NotWordValue in ISA spec.)
170 :function:::int:not_word_value:unsigned_word value
184 #if WITH_TARGET_WORD_BITSIZE == 64
185 return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
193 // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
194 // theoretically portable code which invokes non-portable behaviour from
195 // running with no indication of the portability issue.
196 // (See definition of UNPREDICTABLE in ISA spec.)
199 :function:::void:unpredictable:
211 :function:::void:unpredictable:
217 unpredictable_action (CPU, CIA);
223 // Check that an access to a HI/LO register meets timing requirements
227 // OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
228 // makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
230 // The following restrictions exist for MIPS I - MIPS III:
232 // MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
233 // in between makes MF UNPREDICTABLE. (2)
235 // MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
236 // in between makes MF UNPREDICTABLE. (3)
238 // On the r3900, restriction (2) is not present, and restriction (3) is not
239 // present for multiplication.
241 // Unfortunately, there seems to be some confusion about whether the last
242 // two restrictions should apply to "MIPS IV" as well. One edition of
243 // the MIPS IV ISA says they do, but references in later ISA documents
244 // suggest they don't.
246 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
247 // these restrictions, while others, like the VR5500, don't. To accomodate
248 // such differences, the MIPS IV and MIPS V version of these helper functions
249 // use auxillary routines to determine whether the restriction applies.
253 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
254 // to check for restrictions (2) and (3) above.
256 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
258 if (history->mf.timestamp + 3 > time)
260 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
261 itable[MY_INDEX].name,
263 (long) history->mf.cia);
272 // Check for restriction (2) above (for ISAs/processors that have it),
273 // and record timestamps for restriction (1) above.
275 :function:::int:check_mt_hilo:hilo_history *history
282 signed64 time = sim_events_time (SD);
283 int ok = check_mf_cycles (SD_, history, time, "MT");
284 history->mt.timestamp = time;
285 history->mt.cia = CIA;
289 :function:::int:check_mt_hilo:hilo_history *history
293 signed64 time = sim_events_time (SD);
294 int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
295 || check_mf_cycles (SD_, history, time, "MT"));
296 history->mt.timestamp = time;
297 history->mt.cia = CIA;
301 :function:::int:check_mt_hilo:hilo_history *history
308 signed64 time = sim_events_time (SD);
309 history->mt.timestamp = time;
310 history->mt.cia = CIA;
317 // Check for restriction (1) above, and record timestamps for
318 // restriction (2) and (3) above.
320 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
334 signed64 time = sim_events_time (SD);
337 && peer->mt.timestamp > history->op.timestamp
338 && history->mt.timestamp < history->op.timestamp
339 && ! (history->mf.timestamp > history->op.timestamp
340 && history->mf.timestamp < peer->mt.timestamp)
341 && ! (peer->mf.timestamp > history->op.timestamp
342 && peer->mf.timestamp < peer->mt.timestamp))
344 /* The peer has been written to since the last OP yet we have
346 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
347 itable[MY_INDEX].name,
349 (long) history->op.cia,
350 (long) peer->mt.cia);
353 history->mf.timestamp = time;
354 history->mf.cia = CIA;
362 // Check for restriction (3) above (for ISAs/processors that have it)
363 // for MULT ops, and record timestamps for restriction (1) above.
365 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
372 signed64 time = sim_events_time (SD);
373 int ok = (check_mf_cycles (SD_, hi, time, "OP")
374 && check_mf_cycles (SD_, lo, time, "OP"));
375 hi->op.timestamp = time;
376 lo->op.timestamp = time;
382 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
386 signed64 time = sim_events_time (SD);
387 int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
388 || (check_mf_cycles (SD_, hi, time, "OP")
389 && check_mf_cycles (SD_, lo, time, "OP")));
390 hi->op.timestamp = time;
391 lo->op.timestamp = time;
397 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
404 /* FIXME: could record the fact that a stall occured if we want */
405 signed64 time = sim_events_time (SD);
406 hi->op.timestamp = time;
407 lo->op.timestamp = time;
416 // Check for restriction (3) above (for ISAs/processors that have it)
417 // for DIV ops, and record timestamps for restriction (1) above.
419 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
427 signed64 time = sim_events_time (SD);
428 int ok = (check_mf_cycles (SD_, hi, time, "OP")
429 && check_mf_cycles (SD_, lo, time, "OP"));
430 hi->op.timestamp = time;
431 lo->op.timestamp = time;
437 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
441 signed64 time = sim_events_time (SD);
442 int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
443 || (check_mf_cycles (SD_, hi, time, "OP")
444 && check_mf_cycles (SD_, lo, time, "OP")));
445 hi->op.timestamp = time;
446 lo->op.timestamp = time;
452 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
458 signed64 time = sim_events_time (SD);
459 hi->op.timestamp = time;
460 lo->op.timestamp = time;
469 // Check that the 64-bit instruction can currently be used, and signal
470 // a ReservedInstruction exception if not.
473 :function:::void:check_u64:instruction_word insn
482 // The check should be similar to mips64 for any with PX/UX bit equivalents.
485 :function:::void:check_u64:instruction_word insn
490 #if 0 /* XXX FIXME: enable this only after some additional testing. */
491 if (UserMode && (SR & (status_UX|status_PX)) == 0)
492 SignalException (ReservedInstruction, insn);
499 // MIPS Architecture:
501 // CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
506 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
507 "add r<RD>, r<RS>, r<RT>"
521 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
523 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
525 ALU32_BEGIN (GPR[RS]);
527 ALU32_END (GPR[RD]); /* This checks for overflow. */
529 TRACE_ALU_RESULT (GPR[RD]);
534 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
535 "addi r<RT>, r<RS>, <IMMEDIATE>"
549 if (NotWordValue (GPR[RS]))
551 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
553 ALU32_BEGIN (GPR[RS]);
554 ALU32_ADD (EXTEND16 (IMMEDIATE));
555 ALU32_END (GPR[RT]); /* This checks for overflow. */
557 TRACE_ALU_RESULT (GPR[RT]);
562 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
564 if (NotWordValue (GPR[rs]))
566 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
567 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
568 TRACE_ALU_RESULT (GPR[rt]);
571 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
572 "addiu r<RT>, r<RS>, <IMMEDIATE>"
586 do_addiu (SD_, RS, RT, IMMEDIATE);
591 :function:::void:do_addu:int rs, int rt, int rd
593 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
595 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
596 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
597 TRACE_ALU_RESULT (GPR[rd]);
600 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
601 "addu r<RD>, r<RS>, r<RT>"
615 do_addu (SD_, RS, RT, RD);
620 :function:::void:do_and:int rs, int rt, int rd
622 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
623 GPR[rd] = GPR[rs] & GPR[rt];
624 TRACE_ALU_RESULT (GPR[rd]);
627 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
628 "and r<RD>, r<RS>, r<RT>"
642 do_and (SD_, RS, RT, RD);
647 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
648 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
662 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
663 GPR[RT] = GPR[RS] & IMMEDIATE;
664 TRACE_ALU_RESULT (GPR[RT]);
669 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
670 "beq r<RS>, r<RT>, <OFFSET>"
684 address_word offset = EXTEND16 (OFFSET) << 2;
685 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
687 DELAY_SLOT (NIA + offset);
693 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
694 "beql r<RS>, r<RT>, <OFFSET>"
707 address_word offset = EXTEND16 (OFFSET) << 2;
708 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
710 DELAY_SLOT (NIA + offset);
713 NULLIFY_NEXT_INSTRUCTION ();
718 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
719 "bgez r<RS>, <OFFSET>"
733 address_word offset = EXTEND16 (OFFSET) << 2;
734 if ((signed_word) GPR[RS] >= 0)
736 DELAY_SLOT (NIA + offset);
742 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
743 "bgezal r<RS>, <OFFSET>"
757 address_word offset = EXTEND16 (OFFSET) << 2;
761 if ((signed_word) GPR[RS] >= 0)
763 DELAY_SLOT (NIA + offset);
769 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
770 "bgezall r<RS>, <OFFSET>"
783 address_word offset = EXTEND16 (OFFSET) << 2;
787 /* NOTE: The branch occurs AFTER the next instruction has been
789 if ((signed_word) GPR[RS] >= 0)
791 DELAY_SLOT (NIA + offset);
794 NULLIFY_NEXT_INSTRUCTION ();
799 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
800 "bgezl r<RS>, <OFFSET>"
813 address_word offset = EXTEND16 (OFFSET) << 2;
814 if ((signed_word) GPR[RS] >= 0)
816 DELAY_SLOT (NIA + offset);
819 NULLIFY_NEXT_INSTRUCTION ();
824 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
825 "bgtz r<RS>, <OFFSET>"
839 address_word offset = EXTEND16 (OFFSET) << 2;
840 if ((signed_word) GPR[RS] > 0)
842 DELAY_SLOT (NIA + offset);
848 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
849 "bgtzl r<RS>, <OFFSET>"
862 address_word offset = EXTEND16 (OFFSET) << 2;
863 /* NOTE: The branch occurs AFTER the next instruction has been
865 if ((signed_word) GPR[RS] > 0)
867 DELAY_SLOT (NIA + offset);
870 NULLIFY_NEXT_INSTRUCTION ();
875 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
876 "blez r<RS>, <OFFSET>"
890 address_word offset = EXTEND16 (OFFSET) << 2;
891 /* NOTE: The branch occurs AFTER the next instruction has been
893 if ((signed_word) GPR[RS] <= 0)
895 DELAY_SLOT (NIA + offset);
901 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
902 "bgezl r<RS>, <OFFSET>"
915 address_word offset = EXTEND16 (OFFSET) << 2;
916 if ((signed_word) GPR[RS] <= 0)
918 DELAY_SLOT (NIA + offset);
921 NULLIFY_NEXT_INSTRUCTION ();
926 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
927 "bltz r<RS>, <OFFSET>"
941 address_word offset = EXTEND16 (OFFSET) << 2;
942 if ((signed_word) GPR[RS] < 0)
944 DELAY_SLOT (NIA + offset);
950 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
951 "bltzal r<RS>, <OFFSET>"
965 address_word offset = EXTEND16 (OFFSET) << 2;
969 /* NOTE: The branch occurs AFTER the next instruction has been
971 if ((signed_word) GPR[RS] < 0)
973 DELAY_SLOT (NIA + offset);
979 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
980 "bltzall r<RS>, <OFFSET>"
993 address_word offset = EXTEND16 (OFFSET) << 2;
997 if ((signed_word) GPR[RS] < 0)
999 DELAY_SLOT (NIA + offset);
1002 NULLIFY_NEXT_INSTRUCTION ();
1007 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1008 "bltzl r<RS>, <OFFSET>"
1021 address_word offset = EXTEND16 (OFFSET) << 2;
1022 /* NOTE: The branch occurs AFTER the next instruction has been
1024 if ((signed_word) GPR[RS] < 0)
1026 DELAY_SLOT (NIA + offset);
1029 NULLIFY_NEXT_INSTRUCTION ();
1034 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1035 "bne r<RS>, r<RT>, <OFFSET>"
1049 address_word offset = EXTEND16 (OFFSET) << 2;
1050 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1052 DELAY_SLOT (NIA + offset);
1058 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1059 "bnel r<RS>, r<RT>, <OFFSET>"
1072 address_word offset = EXTEND16 (OFFSET) << 2;
1073 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1075 DELAY_SLOT (NIA + offset);
1078 NULLIFY_NEXT_INSTRUCTION ();
1083 000000,20.CODE,001101:SPECIAL:32::BREAK
1098 /* Check for some break instruction which are reserved for use by the simulator. */
1099 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1100 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1101 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1103 sim_engine_halt (SD, CPU, NULL, cia,
1104 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1106 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
1107 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1109 if (STATE & simDELAYSLOT)
1110 PC = cia - 4; /* reference the branch instruction */
1113 SignalException (BreakPoint, instruction_0);
1118 /* If we get this far, we're not an instruction reserved by the sim. Raise
1120 SignalException (BreakPoint, instruction_0);
1126 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1134 unsigned32 temp = GPR[RS];
1138 if (NotWordValue (GPR[RS]))
1140 TRACE_ALU_INPUT1 (GPR[RS]);
1141 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1143 if ((temp & mask) == 0)
1147 GPR[RD] = EXTEND32 (i);
1148 TRACE_ALU_RESULT (GPR[RD]);
1153 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1161 unsigned32 temp = GPR[RS];
1165 if (NotWordValue (GPR[RS]))
1167 TRACE_ALU_INPUT1 (GPR[RS]);
1168 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1170 if ((temp & mask) != 0)
1174 GPR[RD] = EXTEND32 (i);
1175 TRACE_ALU_RESULT (GPR[RD]);
1180 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1181 "dadd r<RD>, r<RS>, r<RT>"
1190 check_u64 (SD_, instruction_0);
1191 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1193 ALU64_BEGIN (GPR[RS]);
1194 ALU64_ADD (GPR[RT]);
1195 ALU64_END (GPR[RD]); /* This checks for overflow. */
1197 TRACE_ALU_RESULT (GPR[RD]);
1202 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1203 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1212 check_u64 (SD_, instruction_0);
1213 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1215 ALU64_BEGIN (GPR[RS]);
1216 ALU64_ADD (EXTEND16 (IMMEDIATE));
1217 ALU64_END (GPR[RT]); /* This checks for overflow. */
1219 TRACE_ALU_RESULT (GPR[RT]);
1224 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1226 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1227 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1228 TRACE_ALU_RESULT (GPR[rt]);
1231 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1232 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1241 check_u64 (SD_, instruction_0);
1242 do_daddiu (SD_, RS, RT, IMMEDIATE);
1247 :function:::void:do_daddu:int rs, int rt, int rd
1249 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1250 GPR[rd] = GPR[rs] + GPR[rt];
1251 TRACE_ALU_RESULT (GPR[rd]);
1254 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1255 "daddu r<RD>, r<RS>, r<RT>"
1264 check_u64 (SD_, instruction_0);
1265 do_daddu (SD_, RS, RT, RD);
1270 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1276 unsigned64 temp = GPR[RS];
1279 check_u64 (SD_, instruction_0);
1282 TRACE_ALU_INPUT1 (GPR[RS]);
1283 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1285 if ((temp & mask) == 0)
1289 GPR[RD] = EXTEND32 (i);
1290 TRACE_ALU_RESULT (GPR[RD]);
1295 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1301 unsigned64 temp = GPR[RS];
1304 check_u64 (SD_, instruction_0);
1307 TRACE_ALU_INPUT1 (GPR[RS]);
1308 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1310 if ((temp & mask) != 0)
1314 GPR[RD] = EXTEND32 (i);
1315 TRACE_ALU_RESULT (GPR[RD]);
1320 :function:::void:do_ddiv:int rs, int rt
1322 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1323 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1325 signed64 n = GPR[rs];
1326 signed64 d = GPR[rt];
1331 lo = SIGNED64 (0x8000000000000000);
1334 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1336 lo = SIGNED64 (0x8000000000000000);
1347 TRACE_ALU_RESULT2 (HI, LO);
1350 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1360 check_u64 (SD_, instruction_0);
1361 do_ddiv (SD_, RS, RT);
1366 :function:::void:do_ddivu:int rs, int rt
1368 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1369 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1371 unsigned64 n = GPR[rs];
1372 unsigned64 d = GPR[rt];
1377 lo = SIGNED64 (0x8000000000000000);
1388 TRACE_ALU_RESULT2 (HI, LO);
1391 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1392 "ddivu r<RS>, r<RT>"
1401 check_u64 (SD_, instruction_0);
1402 do_ddivu (SD_, RS, RT);
1405 :function:::void:do_div:int rs, int rt
1407 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1408 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1410 signed32 n = GPR[rs];
1411 signed32 d = GPR[rt];
1414 LO = EXTEND32 (0x80000000);
1417 else if (n == SIGNED32 (0x80000000) && d == -1)
1419 LO = EXTEND32 (0x80000000);
1424 LO = EXTEND32 (n / d);
1425 HI = EXTEND32 (n % d);
1428 TRACE_ALU_RESULT2 (HI, LO);
1431 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1446 do_div (SD_, RS, RT);
1451 :function:::void:do_divu:int rs, int rt
1453 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1454 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1456 unsigned32 n = GPR[rs];
1457 unsigned32 d = GPR[rt];
1460 LO = EXTEND32 (0x80000000);
1465 LO = EXTEND32 (n / d);
1466 HI = EXTEND32 (n % d);
1469 TRACE_ALU_RESULT2 (HI, LO);
1472 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1487 do_divu (SD_, RS, RT);
1491 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1501 unsigned64 op1 = GPR[rs];
1502 unsigned64 op2 = GPR[rt];
1503 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1504 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1505 /* make signed multiply unsigned */
1509 if ((signed64) op1 < 0)
1514 if ((signed64) op2 < 0)
1520 /* multiply out the 4 sub products */
1521 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1522 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1523 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1524 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1525 /* add the products */
1526 mid = ((unsigned64) VH4_8 (m00)
1527 + (unsigned64) VL4_8 (m10)
1528 + (unsigned64) VL4_8 (m01));
1529 lo = U8_4 (mid, m00);
1531 + (unsigned64) VH4_8 (mid)
1532 + (unsigned64) VH4_8 (m01)
1533 + (unsigned64) VH4_8 (m10));
1543 /* save the result HI/LO (and a gpr) */
1548 TRACE_ALU_RESULT2 (HI, LO);
1551 :function:::void:do_dmult:int rs, int rt, int rd
1553 do_dmultx (SD_, rs, rt, rd, 1);
1556 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1557 "dmult r<RS>, r<RT>"
1565 check_u64 (SD_, instruction_0);
1566 do_dmult (SD_, RS, RT, 0);
1569 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1570 "dmult r<RS>, r<RT>":RD == 0
1571 "dmult r<RD>, r<RS>, r<RT>"
1574 check_u64 (SD_, instruction_0);
1575 do_dmult (SD_, RS, RT, RD);
1580 :function:::void:do_dmultu:int rs, int rt, int rd
1582 do_dmultx (SD_, rs, rt, rd, 0);
1585 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1586 "dmultu r<RS>, r<RT>"
1594 check_u64 (SD_, instruction_0);
1595 do_dmultu (SD_, RS, RT, 0);
1598 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1599 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1600 "dmultu r<RS>, r<RT>"
1603 check_u64 (SD_, instruction_0);
1604 do_dmultu (SD_, RS, RT, RD);
1608 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1613 TRACE_ALU_INPUT2 (x, y);
1614 result = ROTR64 (x, y);
1615 TRACE_ALU_RESULT (result);
1619 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1620 "dror r<RD>, r<RT>, <SHIFT>"
1625 check_u64 (SD_, instruction_0);
1626 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1629 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1630 "dror32 r<RD>, r<RT>, <SHIFT>"
1635 check_u64 (SD_, instruction_0);
1636 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1639 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1640 "drorv r<RD>, r<RT>, r<RS>"
1645 check_u64 (SD_, instruction_0);
1646 GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1650 :function:::void:do_dsll:int rt, int rd, int shift
1652 TRACE_ALU_INPUT2 (GPR[rt], shift);
1653 GPR[rd] = GPR[rt] << shift;
1654 TRACE_ALU_RESULT (GPR[rd]);
1657 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1658 "dsll r<RD>, r<RT>, <SHIFT>"
1667 check_u64 (SD_, instruction_0);
1668 do_dsll (SD_, RT, RD, SHIFT);
1672 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1673 "dsll32 r<RD>, r<RT>, <SHIFT>"
1683 check_u64 (SD_, instruction_0);
1684 TRACE_ALU_INPUT2 (GPR[RT], s);
1685 GPR[RD] = GPR[RT] << s;
1686 TRACE_ALU_RESULT (GPR[RD]);
1689 :function:::void:do_dsllv:int rs, int rt, int rd
1691 int s = MASKED64 (GPR[rs], 5, 0);
1692 TRACE_ALU_INPUT2 (GPR[rt], s);
1693 GPR[rd] = GPR[rt] << s;
1694 TRACE_ALU_RESULT (GPR[rd]);
1697 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1698 "dsllv r<RD>, r<RT>, r<RS>"
1707 check_u64 (SD_, instruction_0);
1708 do_dsllv (SD_, RS, RT, RD);
1711 :function:::void:do_dsra:int rt, int rd, int shift
1713 TRACE_ALU_INPUT2 (GPR[rt], shift);
1714 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1715 TRACE_ALU_RESULT (GPR[rd]);
1719 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1720 "dsra r<RD>, r<RT>, <SHIFT>"
1729 check_u64 (SD_, instruction_0);
1730 do_dsra (SD_, RT, RD, SHIFT);
1734 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1735 "dsra32 r<RD>, r<RT>, <SHIFT>"
1745 check_u64 (SD_, instruction_0);
1746 TRACE_ALU_INPUT2 (GPR[RT], s);
1747 GPR[RD] = ((signed64) GPR[RT]) >> s;
1748 TRACE_ALU_RESULT (GPR[RD]);
1752 :function:::void:do_dsrav:int rs, int rt, int rd
1754 int s = MASKED64 (GPR[rs], 5, 0);
1755 TRACE_ALU_INPUT2 (GPR[rt], s);
1756 GPR[rd] = ((signed64) GPR[rt]) >> s;
1757 TRACE_ALU_RESULT (GPR[rd]);
1760 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1761 "dsrav r<RD>, r<RT>, r<RS>"
1770 check_u64 (SD_, instruction_0);
1771 do_dsrav (SD_, RS, RT, RD);
1774 :function:::void:do_dsrl:int rt, int rd, int shift
1776 TRACE_ALU_INPUT2 (GPR[rt], shift);
1777 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1778 TRACE_ALU_RESULT (GPR[rd]);
1782 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1783 "dsrl r<RD>, r<RT>, <SHIFT>"
1792 check_u64 (SD_, instruction_0);
1793 do_dsrl (SD_, RT, RD, SHIFT);
1797 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1798 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1808 check_u64 (SD_, instruction_0);
1809 TRACE_ALU_INPUT2 (GPR[RT], s);
1810 GPR[RD] = (unsigned64) GPR[RT] >> s;
1811 TRACE_ALU_RESULT (GPR[RD]);
1815 :function:::void:do_dsrlv:int rs, int rt, int rd
1817 int s = MASKED64 (GPR[rs], 5, 0);
1818 TRACE_ALU_INPUT2 (GPR[rt], s);
1819 GPR[rd] = (unsigned64) GPR[rt] >> s;
1820 TRACE_ALU_RESULT (GPR[rd]);
1825 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1826 "dsrlv r<RD>, r<RT>, r<RS>"
1835 check_u64 (SD_, instruction_0);
1836 do_dsrlv (SD_, RS, RT, RD);
1840 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1841 "dsub r<RD>, r<RS>, r<RT>"
1850 check_u64 (SD_, instruction_0);
1851 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1853 ALU64_BEGIN (GPR[RS]);
1854 ALU64_SUB (GPR[RT]);
1855 ALU64_END (GPR[RD]); /* This checks for overflow. */
1857 TRACE_ALU_RESULT (GPR[RD]);
1861 :function:::void:do_dsubu:int rs, int rt, int rd
1863 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1864 GPR[rd] = GPR[rs] - GPR[rt];
1865 TRACE_ALU_RESULT (GPR[rd]);
1868 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1869 "dsubu r<RD>, r<RS>, r<RT>"
1878 check_u64 (SD_, instruction_0);
1879 do_dsubu (SD_, RS, RT, RD);
1883 000010,26.INSTR_INDEX:NORMAL:32::J
1898 /* NOTE: The region used is that of the delay slot NIA and NOT the
1899 current instruction */
1900 address_word region = (NIA & MASK (63, 28));
1901 DELAY_SLOT (region | (INSTR_INDEX << 2));
1905 000011,26.INSTR_INDEX:NORMAL:32::JAL
1920 /* NOTE: The region used is that of the delay slot and NOT the
1921 current instruction */
1922 address_word region = (NIA & MASK (63, 28));
1924 DELAY_SLOT (region | (INSTR_INDEX << 2));
1927 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1928 "jalr r<RS>":RD == 31
1943 address_word temp = GPR[RS];
1949 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1964 DELAY_SLOT (GPR[RS]);
1968 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1970 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1971 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1972 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1979 vaddr = loadstore_ea (SD_, base, offset);
1980 if ((vaddr & access) != 0)
1982 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1984 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1985 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1986 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1987 byte = ((vaddr & mask) ^ bigendiancpu);
1988 return (memval >> (8 * byte));
1991 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1993 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1994 address_word reverseendian = (ReverseEndian ? -1 : 0);
1995 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2004 unsigned_word lhs_mask;
2007 vaddr = loadstore_ea (SD_, base, offset);
2008 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2009 paddr = (paddr ^ (reverseendian & mask));
2010 if (BigEndianMem == 0)
2011 paddr = paddr & ~access;
2013 /* compute where within the word/mem we are */
2014 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2015 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2016 nr_lhs_bits = 8 * byte + 8;
2017 nr_rhs_bits = 8 * access - 8 * byte;
2018 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2020 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2021 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2022 (long) ((unsigned64) paddr >> 32), (long) paddr,
2023 word, byte, nr_lhs_bits, nr_rhs_bits); */
2025 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2028 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2029 temp = (memval << nr_rhs_bits);
2033 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2034 temp = (memval >> nr_lhs_bits);
2036 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2037 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2039 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2040 (long) ((unsigned64) memval >> 32), (long) memval,
2041 (long) ((unsigned64) temp >> 32), (long) temp,
2042 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2043 (long) (rt >> 32), (long) rt); */
2047 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2049 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2050 address_word reverseendian = (ReverseEndian ? -1 : 0);
2051 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2058 vaddr = loadstore_ea (SD_, base, offset);
2059 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2060 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2061 paddr = (paddr ^ (reverseendian & mask));
2062 if (BigEndianMem != 0)
2063 paddr = paddr & ~access;
2064 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2065 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
2066 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2067 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2068 (long) paddr, byte, (long) paddr, (long) memval); */
2070 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2072 rt |= (memval >> (8 * byte)) & screen;
2078 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2079 "lb r<RT>, <OFFSET>(r<BASE>)"
2093 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2097 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2098 "lbu r<RT>, <OFFSET>(r<BASE>)"
2112 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2116 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2117 "ld r<RT>, <OFFSET>(r<BASE>)"
2126 check_u64 (SD_, instruction_0);
2127 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2131 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2132 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2145 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2151 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2152 "ldl r<RT>, <OFFSET>(r<BASE>)"
2161 check_u64 (SD_, instruction_0);
2162 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2166 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2167 "ldr r<RT>, <OFFSET>(r<BASE>)"
2176 check_u64 (SD_, instruction_0);
2177 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2181 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2182 "lh r<RT>, <OFFSET>(r<BASE>)"
2196 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2200 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2201 "lhu r<RT>, <OFFSET>(r<BASE>)"
2215 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2219 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2220 "ll r<RT>, <OFFSET>(r<BASE>)"
2232 address_word base = GPR[BASE];
2233 address_word offset = EXTEND16 (OFFSET);
2235 address_word vaddr = loadstore_ea (SD_, base, offset);
2238 if ((vaddr & 3) != 0)
2240 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2244 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2246 unsigned64 memval = 0;
2247 unsigned64 memval1 = 0;
2248 unsigned64 mask = 0x7;
2249 unsigned int shift = 2;
2250 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2251 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2253 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2254 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2255 byte = ((vaddr & mask) ^ (bigend << shift));
2256 GPR[RT] = EXTEND32 (memval >> (8 * byte));
2264 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2265 "lld r<RT>, <OFFSET>(r<BASE>)"
2274 address_word base = GPR[BASE];
2275 address_word offset = EXTEND16 (OFFSET);
2276 check_u64 (SD_, instruction_0);
2278 address_word vaddr = loadstore_ea (SD_, base, offset);
2281 if ((vaddr & 7) != 0)
2283 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2287 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2289 unsigned64 memval = 0;
2290 unsigned64 memval1 = 0;
2291 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2300 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2301 "lui r<RT>, %#lx<IMMEDIATE>"
2315 TRACE_ALU_INPUT1 (IMMEDIATE);
2316 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2317 TRACE_ALU_RESULT (GPR[RT]);
2321 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2322 "lw r<RT>, <OFFSET>(r<BASE>)"
2336 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2340 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2341 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2355 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2359 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2360 "lwl r<RT>, <OFFSET>(r<BASE>)"
2374 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2378 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2379 "lwr r<RT>, <OFFSET>(r<BASE>)"
2393 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2397 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2398 "lwu r<RT>, <OFFSET>(r<BASE>)"
2407 check_u64 (SD_, instruction_0);
2408 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2413 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2422 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2423 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2425 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2426 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2427 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2428 LO = EXTEND32 (temp);
2429 HI = EXTEND32 (VH4_8 (temp));
2430 TRACE_ALU_RESULT2 (HI, LO);
2435 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2436 "maddu r<RS>, r<RT>"
2444 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2445 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2447 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2448 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2449 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2450 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
2451 LO = EXTEND32 (temp);
2452 HI = EXTEND32 (VH4_8 (temp));
2453 TRACE_ALU_RESULT2 (HI, LO);
2457 :function:::void:do_mfhi:int rd
2459 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2460 TRACE_ALU_INPUT1 (HI);
2462 TRACE_ALU_RESULT (GPR[rd]);
2465 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2481 :function:::void:do_mflo:int rd
2483 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2484 TRACE_ALU_INPUT1 (LO);
2486 TRACE_ALU_RESULT (GPR[rd]);
2489 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2505 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2506 "movn r<RD>, r<RS>, r<RT>"
2518 TRACE_ALU_RESULT (GPR[RD]);
2524 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2525 "movz r<RD>, r<RS>, r<RT>"
2537 TRACE_ALU_RESULT (GPR[RD]);
2543 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2552 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2553 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2555 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2556 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2557 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2558 LO = EXTEND32 (temp);
2559 HI = EXTEND32 (VH4_8 (temp));
2560 TRACE_ALU_RESULT2 (HI, LO);
2565 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2566 "msubu r<RS>, r<RT>"
2574 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2575 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2577 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2578 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2579 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2580 LO = EXTEND32 (temp);
2581 HI = EXTEND32 (VH4_8 (temp));
2582 TRACE_ALU_RESULT2 (HI, LO);
2587 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2598 check_mt_hilo (SD_, HIHISTORY);
2604 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2615 check_mt_hilo (SD_, LOHISTORY);
2621 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2622 "mul r<RD>, r<RS>, r<RT>"
2630 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2632 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2633 prod = (((signed64)(signed32) GPR[RS])
2634 * ((signed64)(signed32) GPR[RT]));
2635 GPR[RD] = EXTEND32 (VL4_8 (prod));
2636 TRACE_ALU_RESULT (GPR[RD]);
2641 :function:::void:do_mult:int rs, int rt, int rd
2644 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2645 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2647 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2648 prod = (((signed64)(signed32) GPR[rs])
2649 * ((signed64)(signed32) GPR[rt]));
2650 LO = EXTEND32 (VL4_8 (prod));
2651 HI = EXTEND32 (VH4_8 (prod));
2652 ACX = 0; /* SmartMIPS */
2655 TRACE_ALU_RESULT2 (HI, LO);
2658 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2671 do_mult (SD_, RS, RT, 0);
2675 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2676 "mult r<RS>, r<RT>":RD == 0
2677 "mult r<RD>, r<RS>, r<RT>"
2681 do_mult (SD_, RS, RT, RD);
2685 :function:::void:do_multu:int rs, int rt, int rd
2688 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2689 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2691 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2692 prod = (((unsigned64)(unsigned32) GPR[rs])
2693 * ((unsigned64)(unsigned32) GPR[rt]));
2694 LO = EXTEND32 (VL4_8 (prod));
2695 HI = EXTEND32 (VH4_8 (prod));
2698 TRACE_ALU_RESULT2 (HI, LO);
2701 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2702 "multu r<RS>, r<RT>"
2714 do_multu (SD_, RS, RT, 0);
2717 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2718 "multu r<RS>, r<RT>":RD == 0
2719 "multu r<RD>, r<RS>, r<RT>"
2723 do_multu (SD_, RS, RT, RD);
2727 :function:::void:do_nor:int rs, int rt, int rd
2729 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2730 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2731 TRACE_ALU_RESULT (GPR[rd]);
2734 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2735 "nor r<RD>, r<RS>, r<RT>"
2749 do_nor (SD_, RS, RT, RD);
2753 :function:::void:do_or:int rs, int rt, int rd
2755 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2756 GPR[rd] = (GPR[rs] | GPR[rt]);
2757 TRACE_ALU_RESULT (GPR[rd]);
2760 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2761 "or r<RD>, r<RS>, r<RT>"
2775 do_or (SD_, RS, RT, RD);
2780 :function:::void:do_ori:int rs, int rt, unsigned immediate
2782 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2783 GPR[rt] = (GPR[rs] | immediate);
2784 TRACE_ALU_RESULT (GPR[rt]);
2787 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2788 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2802 do_ori (SD_, RS, RT, IMMEDIATE);
2806 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2807 "pref <HINT>, <OFFSET>(r<BASE>)"
2816 address_word base = GPR[BASE];
2817 address_word offset = EXTEND16 (OFFSET);
2819 address_word vaddr = loadstore_ea (SD_, base, offset);
2823 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2824 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2830 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
2835 TRACE_ALU_INPUT2 (x, y);
2836 result = EXTEND32 (ROTR32 (x, y));
2837 TRACE_ALU_RESULT (result);
2841 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
2842 "ror r<RD>, r<RT>, <SHIFT>"
2849 GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
2852 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
2853 "rorv r<RD>, r<RT>, r<RS>"
2860 GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
2864 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2866 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2867 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2868 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2875 vaddr = loadstore_ea (SD_, base, offset);
2876 if ((vaddr & access) != 0)
2878 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2880 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2881 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2882 byte = ((vaddr & mask) ^ bigendiancpu);
2883 memval = (word << (8 * byte));
2884 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2887 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2889 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2890 address_word reverseendian = (ReverseEndian ? -1 : 0);
2891 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2901 vaddr = loadstore_ea (SD_, base, offset);
2902 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2903 paddr = (paddr ^ (reverseendian & mask));
2904 if (BigEndianMem == 0)
2905 paddr = paddr & ~access;
2907 /* compute where within the word/mem we are */
2908 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2909 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2910 nr_lhs_bits = 8 * byte + 8;
2911 nr_rhs_bits = 8 * access - 8 * byte;
2912 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2913 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2914 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2915 (long) ((unsigned64) paddr >> 32), (long) paddr,
2916 word, byte, nr_lhs_bits, nr_rhs_bits); */
2920 memval = (rt >> nr_rhs_bits);
2924 memval = (rt << nr_lhs_bits);
2926 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2927 (long) ((unsigned64) rt >> 32), (long) rt,
2928 (long) ((unsigned64) memval >> 32), (long) memval); */
2929 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2932 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2934 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2935 address_word reverseendian = (ReverseEndian ? -1 : 0);
2936 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2943 vaddr = loadstore_ea (SD_, base, offset);
2944 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2945 paddr = (paddr ^ (reverseendian & mask));
2946 if (BigEndianMem != 0)
2948 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2949 memval = (rt << (byte * 8));
2950 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2954 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2955 "sb r<RT>, <OFFSET>(r<BASE>)"
2969 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2973 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2974 "sc r<RT>, <OFFSET>(r<BASE>)"
2986 unsigned32 instruction = instruction_0;
2987 address_word base = GPR[BASE];
2988 address_word offset = EXTEND16 (OFFSET);
2990 address_word vaddr = loadstore_ea (SD_, base, offset);
2993 if ((vaddr & 3) != 0)
2995 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2999 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3001 unsigned64 memval = 0;
3002 unsigned64 memval1 = 0;
3003 unsigned64 mask = 0x7;
3005 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3006 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3007 memval = ((unsigned64) GPR[RT] << (8 * byte));
3010 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3019 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3020 "scd r<RT>, <OFFSET>(r<BASE>)"
3029 address_word base = GPR[BASE];
3030 address_word offset = EXTEND16 (OFFSET);
3031 check_u64 (SD_, instruction_0);
3033 address_word vaddr = loadstore_ea (SD_, base, offset);
3036 if ((vaddr & 7) != 0)
3038 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3042 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3044 unsigned64 memval = 0;
3045 unsigned64 memval1 = 0;
3049 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3058 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3059 "sd r<RT>, <OFFSET>(r<BASE>)"
3068 check_u64 (SD_, instruction_0);
3069 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3073 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3074 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3086 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3090 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3091 "sdl r<RT>, <OFFSET>(r<BASE>)"
3100 check_u64 (SD_, instruction_0);
3101 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3105 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3106 "sdr r<RT>, <OFFSET>(r<BASE>)"
3115 check_u64 (SD_, instruction_0);
3116 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3121 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3122 "sh r<RT>, <OFFSET>(r<BASE>)"
3136 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3140 :function:::void:do_sll:int rt, int rd, int shift
3142 unsigned32 temp = (GPR[rt] << shift);
3143 TRACE_ALU_INPUT2 (GPR[rt], shift);
3144 GPR[rd] = EXTEND32 (temp);
3145 TRACE_ALU_RESULT (GPR[rd]);
3148 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
3149 "nop":RD == 0 && RT == 0 && SHIFT == 0
3150 "sll r<RD>, r<RT>, <SHIFT>"
3160 /* Skip shift for NOP, so that there won't be lots of extraneous
3162 if (RD != 0 || RT != 0 || SHIFT != 0)
3163 do_sll (SD_, RT, RD, SHIFT);
3166 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3167 "nop":RD == 0 && RT == 0 && SHIFT == 0
3168 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
3169 "sll r<RD>, r<RT>, <SHIFT>"
3175 /* Skip shift for NOP and SSNOP, so that there won't be lots of
3176 extraneous trace output. */
3177 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3178 do_sll (SD_, RT, RD, SHIFT);
3182 :function:::void:do_sllv:int rs, int rt, int rd
3184 int s = MASKED (GPR[rs], 4, 0);
3185 unsigned32 temp = (GPR[rt] << s);
3186 TRACE_ALU_INPUT2 (GPR[rt], s);
3187 GPR[rd] = EXTEND32 (temp);
3188 TRACE_ALU_RESULT (GPR[rd]);
3191 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
3192 "sllv r<RD>, r<RT>, r<RS>"
3206 do_sllv (SD_, RS, RT, RD);
3210 :function:::void:do_slt:int rs, int rt, int rd
3212 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3213 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3214 TRACE_ALU_RESULT (GPR[rd]);
3217 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
3218 "slt r<RD>, r<RS>, r<RT>"
3232 do_slt (SD_, RS, RT, RD);
3236 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3238 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3239 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3240 TRACE_ALU_RESULT (GPR[rt]);
3243 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3244 "slti r<RT>, r<RS>, <IMMEDIATE>"
3258 do_slti (SD_, RS, RT, IMMEDIATE);
3262 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3264 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3265 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3266 TRACE_ALU_RESULT (GPR[rt]);
3269 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3270 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3284 do_sltiu (SD_, RS, RT, IMMEDIATE);
3289 :function:::void:do_sltu:int rs, int rt, int rd
3291 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3292 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3293 TRACE_ALU_RESULT (GPR[rd]);
3296 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3297 "sltu r<RD>, r<RS>, r<RT>"
3311 do_sltu (SD_, RS, RT, RD);
3315 :function:::void:do_sra:int rt, int rd, int shift
3317 signed32 temp = (signed32) GPR[rt] >> shift;
3318 if (NotWordValue (GPR[rt]))
3320 TRACE_ALU_INPUT2 (GPR[rt], shift);
3321 GPR[rd] = EXTEND32 (temp);
3322 TRACE_ALU_RESULT (GPR[rd]);
3325 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3326 "sra r<RD>, r<RT>, <SHIFT>"
3340 do_sra (SD_, RT, RD, SHIFT);
3345 :function:::void:do_srav:int rs, int rt, int rd
3347 int s = MASKED (GPR[rs], 4, 0);
3348 signed32 temp = (signed32) GPR[rt] >> s;
3349 if (NotWordValue (GPR[rt]))
3351 TRACE_ALU_INPUT2 (GPR[rt], s);
3352 GPR[rd] = EXTEND32 (temp);
3353 TRACE_ALU_RESULT (GPR[rd]);
3356 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3357 "srav r<RD>, r<RT>, r<RS>"
3371 do_srav (SD_, RS, RT, RD);
3376 :function:::void:do_srl:int rt, int rd, int shift
3378 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3379 if (NotWordValue (GPR[rt]))
3381 TRACE_ALU_INPUT2 (GPR[rt], shift);
3382 GPR[rd] = EXTEND32 (temp);
3383 TRACE_ALU_RESULT (GPR[rd]);
3386 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3387 "srl r<RD>, r<RT>, <SHIFT>"
3401 do_srl (SD_, RT, RD, SHIFT);
3405 :function:::void:do_srlv:int rs, int rt, int rd
3407 int s = MASKED (GPR[rs], 4, 0);
3408 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3409 if (NotWordValue (GPR[rt]))
3411 TRACE_ALU_INPUT2 (GPR[rt], s);
3412 GPR[rd] = EXTEND32 (temp);
3413 TRACE_ALU_RESULT (GPR[rd]);
3416 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3417 "srlv r<RD>, r<RT>, r<RS>"
3431 do_srlv (SD_, RS, RT, RD);
3435 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3436 "sub r<RD>, r<RS>, r<RT>"
3450 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3452 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3454 ALU32_BEGIN (GPR[RS]);
3455 ALU32_SUB (GPR[RT]);
3456 ALU32_END (GPR[RD]); /* This checks for overflow. */
3458 TRACE_ALU_RESULT (GPR[RD]);
3462 :function:::void:do_subu:int rs, int rt, int rd
3464 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3466 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3467 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3468 TRACE_ALU_RESULT (GPR[rd]);
3471 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3472 "subu r<RD>, r<RS>, r<RT>"
3486 do_subu (SD_, RS, RT, RD);
3490 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3491 "sw r<RT>, <OFFSET>(r<BASE>)"
3505 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3509 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3510 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3524 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3528 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3529 "swl r<RT>, <OFFSET>(r<BASE>)"
3543 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3547 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3548 "swr r<RT>, <OFFSET>(r<BASE>)"
3562 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3566 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3581 SyncOperation (STYPE);
3585 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3586 "syscall %#lx<CODE>"
3600 SignalException (SystemCall, instruction_0);
3604 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3617 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3618 SignalException (Trap, instruction_0);
3622 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3623 "teqi r<RS>, <IMMEDIATE>"
3635 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3636 SignalException (Trap, instruction_0);
3640 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3653 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3654 SignalException (Trap, instruction_0);
3658 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3659 "tgei r<RS>, <IMMEDIATE>"
3671 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3672 SignalException (Trap, instruction_0);
3676 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3677 "tgeiu r<RS>, <IMMEDIATE>"
3689 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3690 SignalException (Trap, instruction_0);
3694 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3707 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3708 SignalException (Trap, instruction_0);
3712 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3725 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3726 SignalException (Trap, instruction_0);
3730 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3731 "tlti r<RS>, <IMMEDIATE>"
3743 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3744 SignalException (Trap, instruction_0);
3748 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3749 "tltiu r<RS>, <IMMEDIATE>"
3761 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3762 SignalException (Trap, instruction_0);
3766 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3779 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3780 SignalException (Trap, instruction_0);
3784 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3797 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3798 SignalException (Trap, instruction_0);
3802 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3803 "tnei r<RS>, <IMMEDIATE>"
3815 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3816 SignalException (Trap, instruction_0);
3820 :function:::void:do_xor:int rs, int rt, int rd
3822 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3823 GPR[rd] = GPR[rs] ^ GPR[rt];
3824 TRACE_ALU_RESULT (GPR[rd]);
3827 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3828 "xor r<RD>, r<RS>, r<RT>"
3842 do_xor (SD_, RS, RT, RD);
3846 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3848 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3849 GPR[rt] = GPR[rs] ^ immediate;
3850 TRACE_ALU_RESULT (GPR[rt]);
3853 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3854 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3868 do_xori (SD_, RS, RT, IMMEDIATE);
3873 // MIPS Architecture:
3875 // FPU Instruction Set (COP1 & COP1X)
3883 case fmt_single: return "s";
3884 case fmt_double: return "d";
3885 case fmt_word: return "w";
3886 case fmt_long: return "l";
3887 case fmt_ps: return "ps";
3888 default: return "?";
3908 :%s::::COND:int cond
3912 case 00: return "f";
3913 case 01: return "un";
3914 case 02: return "eq";
3915 case 03: return "ueq";
3916 case 04: return "olt";
3917 case 05: return "ult";
3918 case 06: return "ole";
3919 case 07: return "ule";
3920 case 010: return "sf";
3921 case 011: return "ngle";
3922 case 012: return "seq";
3923 case 013: return "ngl";
3924 case 014: return "lt";
3925 case 015: return "nge";
3926 case 016: return "le";
3927 case 017: return "ngt";
3928 default: return "?";
3935 // Check that the given FPU format is usable, and signal a
3936 // ReservedInstruction exception if not.
3939 // check_fmt_p checks that the format is single, double, or paired single.
3940 :function:::void:check_fmt_p:int fmt, instruction_word insn
3951 /* None of these ISAs support Paired Single, so just fall back to
3952 the single/double check. */
3953 if ((fmt != fmt_single) && (fmt != fmt_double))
3954 SignalException (ReservedInstruction, insn);
3957 :function:::void:check_fmt_p:int fmt, instruction_word insn
3962 if ((fmt != fmt_single) && (fmt != fmt_double)
3963 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3964 SignalException (ReservedInstruction, insn);
3970 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3971 // exception if not.
3974 :function:::void:check_fpu:
3988 if (! COP_Usable (1))
3989 SignalExceptionCoProcessorUnusable (1);
3995 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
3996 // or MIPS32. do_load cannot be used instead because it returns an
3997 // unsigned_word, which is limited to the size of the machine's registers.
4000 :function:::unsigned64:do_load_double:address_word base, address_word offset
4005 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4012 vaddr = loadstore_ea (SD_, base, offset);
4013 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4015 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4016 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4017 sim_core_unaligned_signal);
4019 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4021 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4023 v = (unsigned64)memval;
4024 LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4026 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4032 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4033 // or MIPS32. do_load cannot be used instead because it returns an
4034 // unsigned_word, which is limited to the size of the machine's registers.
4037 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4042 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4048 vaddr = loadstore_ea (SD_, base, offset);
4049 if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4051 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4052 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4053 sim_core_unaligned_signal);
4055 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4057 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4058 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4060 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4061 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4066 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4067 "abs.%s<FMT> f<FD>, f<FS>"
4083 check_fmt_p (SD_, fmt, instruction_0);
4084 StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
4089 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4090 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4106 check_fmt_p (SD_, fmt, instruction_0);
4107 StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4111 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
4112 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4121 check_u64 (SD_, instruction_0);
4122 fs = ValueFPR (FS, fmt_ps);
4123 if ((GPR[RS] & 0x3) != 0)
4125 if ((GPR[RS] & 0x4) == 0)
4129 ft = ValueFPR (FT, fmt_ps);
4131 fd = PackPS (PSLower (fs), PSUpper (ft));
4133 fd = PackPS (PSLower (ft), PSUpper (fs));
4135 StoreFPR (FD, fmt_ps, fd);
4144 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4145 "bc1%s<TF>%s<ND> <OFFSET>"
4151 TRACE_BRANCH_INPUT (PREVCOC1());
4152 if (PREVCOC1() == TF)
4154 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4155 TRACE_BRANCH_RESULT (dest);
4160 TRACE_BRANCH_RESULT (0);
4161 NULLIFY_NEXT_INSTRUCTION ();
4165 TRACE_BRANCH_RESULT (NIA);
4169 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4170 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4171 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4183 if (GETFCC(CC) == TF)
4185 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4190 NULLIFY_NEXT_INSTRUCTION ();
4195 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
4196 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4203 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4204 TRACE_ALU_RESULT (ValueFCR (31));
4207 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
4208 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4209 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4222 check_fmt_p (SD_, fmt, instruction_0);
4223 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4224 TRACE_ALU_RESULT (ValueFCR (31));
4228 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
4229 "ceil.l.%s<FMT> f<FD>, f<FS>"
4241 StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4246 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
4247 "ceil.w.%s<FMT> f<FD>, f<FS>"
4262 StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4267 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4275 PENDING_FILL (RT, EXTEND32 (FCR0));
4277 PENDING_FILL (RT, EXTEND32 (FCR31));
4281 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4289 if (FS == 0 || FS == 31)
4291 unsigned_word fcr = ValueFCR (FS);
4292 TRACE_ALU_INPUT1 (fcr);
4296 TRACE_ALU_RESULT (GPR[RT]);
4299 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4308 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4310 unsigned_word fcr = ValueFCR (FS);
4311 TRACE_ALU_INPUT1 (fcr);
4315 TRACE_ALU_RESULT (GPR[RT]);
4318 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4326 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4330 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4338 TRACE_ALU_INPUT1 (GPR[RT]);
4340 StoreFCR (FS, GPR[RT]);
4344 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4353 TRACE_ALU_INPUT1 (GPR[RT]);
4354 if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4355 StoreFCR (FS, GPR[RT]);
4361 // FIXME: Does not correctly differentiate between mips*
4363 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4364 "cvt.d.%s<FMT> f<FD>, f<FS>"
4380 if ((fmt == fmt_double) | 0)
4381 SignalException (ReservedInstruction, instruction_0);
4382 StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4387 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4388 "cvt.l.%s<FMT> f<FD>, f<FS>"
4400 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4401 SignalException (ReservedInstruction, instruction_0);
4402 StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4407 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4408 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4414 check_u64 (SD_, instruction_0);
4415 StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4416 ValueFPR (FT, fmt_single)));
4421 // FIXME: Does not correctly differentiate between mips*
4423 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4424 "cvt.s.%s<FMT> f<FD>, f<FS>"
4440 if ((fmt == fmt_single) | 0)
4441 SignalException (ReservedInstruction, instruction_0);
4442 StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4447 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4448 "cvt.s.pl f<FD>, f<FS>"
4454 check_u64 (SD_, instruction_0);
4455 StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4459 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4460 "cvt.s.pu f<FD>, f<FS>"
4466 check_u64 (SD_, instruction_0);
4467 StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4471 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4472 "cvt.w.%s<FMT> f<FD>, f<FS>"
4488 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4489 SignalException (ReservedInstruction, instruction_0);
4490 StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4495 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4496 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4512 StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4516 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4517 "dmfc1 r<RT>, f<FS>"
4522 check_u64 (SD_, instruction_0);
4523 if (SizeFGR () == 64)
4525 else if ((FS & 0x1) == 0)
4526 v = SET64HI (FGR[FS+1]) | FGR[FS];
4528 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4529 PENDING_FILL (RT, v);
4530 TRACE_ALU_RESULT (v);
4533 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4534 "dmfc1 r<RT>, f<FS>"
4544 check_u64 (SD_, instruction_0);
4545 if (SizeFGR () == 64)
4547 else if ((FS & 0x1) == 0)
4548 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4550 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4551 TRACE_ALU_RESULT (GPR[RT]);
4555 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4556 "dmtc1 r<RT>, f<FS>"
4561 check_u64 (SD_, instruction_0);
4562 if (SizeFGR () == 64)
4563 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4564 else if ((FS & 0x1) == 0)
4566 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4567 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4571 TRACE_FP_RESULT (GPR[RT]);
4574 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4575 "dmtc1 r<RT>, f<FS>"
4585 check_u64 (SD_, instruction_0);
4586 if (SizeFGR () == 64)
4587 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4588 else if ((FS & 0x1) == 0)
4589 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4595 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4596 "floor.l.%s<FMT> f<FD>, f<FS>"
4608 StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4613 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4614 "floor.w.%s<FMT> f<FD>, f<FS>"
4629 StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4634 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4635 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4641 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4645 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4646 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4657 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4661 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4662 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4670 check_u64 (SD_, instruction_0);
4671 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4675 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4676 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4681 address_word base = GPR[BASE];
4682 address_word index = GPR[INDEX];
4683 address_word vaddr = base + index;
4685 check_u64 (SD_, instruction_0);
4686 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
4687 if ((vaddr & 0x7) != 0)
4688 index -= (vaddr & 0x7);
4689 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4693 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4694 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4709 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4713 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4714 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4722 check_u64 (SD_, instruction_0);
4723 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4728 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
4729 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4738 check_u64 (SD_, instruction_0);
4739 check_fmt_p (SD_, fmt, instruction_0);
4740 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4741 ValueFPR (FR, fmt), fmt));
4745 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4753 v = EXTEND32 (FGR[FS]);
4754 PENDING_FILL (RT, v);
4755 TRACE_ALU_RESULT (v);
4758 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4771 GPR[RT] = EXTEND32 (FGR[FS]);
4772 TRACE_ALU_RESULT (GPR[RT]);
4776 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4777 "mov.%s<FMT> f<FD>, f<FS>"
4793 check_fmt_p (SD_, fmt, instruction_0);
4794 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4800 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4801 "mov%s<TF> r<RD>, r<RS>, <CC>"
4811 if (GETFCC(CC) == TF)
4818 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4819 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4832 if (GETFCC(CC) == TF)
4833 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4835 StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
4840 fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4842 PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4844 StoreFPR (FD, fmt_ps, fd);
4849 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4850 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4861 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4863 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4870 // MOVT.fmt see MOVtf.fmt
4874 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4875 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4886 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4888 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4892 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
4893 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4902 check_u64 (SD_, instruction_0);
4903 check_fmt_p (SD_, fmt, instruction_0);
4904 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4905 ValueFPR (FR, fmt), fmt));
4909 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4916 if (SizeFGR () == 64)
4917 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4919 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4920 TRACE_FP_RESULT (GPR[RT]);
4923 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4936 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4940 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4941 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4957 check_fmt_p (SD_, fmt, instruction_0);
4958 StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4962 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4963 "neg.%s<FMT> f<FD>, f<FS>"
4979 check_fmt_p (SD_, fmt, instruction_0);
4980 StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4984 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
4985 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4994 check_u64 (SD_, instruction_0);
4995 check_fmt_p (SD_, fmt, instruction_0);
4996 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4997 ValueFPR (FR, fmt), fmt));
5001 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
5002 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5011 check_u64 (SD_, instruction_0);
5012 check_fmt_p (SD_, fmt, instruction_0);
5013 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5014 ValueFPR (FR, fmt), fmt));
5018 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
5019 "pll.ps f<FD>, f<FS>, f<FT>"
5025 check_u64 (SD_, instruction_0);
5026 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5027 PSLower (ValueFPR (FT, fmt_ps))));
5031 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
5032 "plu.ps f<FD>, f<FS>, f<FT>"
5038 check_u64 (SD_, instruction_0);
5039 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5040 PSUpper (ValueFPR (FT, fmt_ps))));
5044 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
5045 "prefx <HINT>, r<INDEX>(r<BASE>)"
5052 address_word base = GPR[BASE];
5053 address_word index = GPR[INDEX];
5055 address_word vaddr = loadstore_ea (SD_, base, index);
5058 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5059 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
5064 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
5065 "pul.ps f<FD>, f<FS>, f<FT>"
5071 check_u64 (SD_, instruction_0);
5072 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5073 PSLower (ValueFPR (FT, fmt_ps))));
5077 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
5078 "puu.ps f<FD>, f<FS>, f<FT>"
5084 check_u64 (SD_, instruction_0);
5085 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5086 PSUpper (ValueFPR (FT, fmt_ps))));
5090 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
5091 "recip.%s<FMT> f<FD>, f<FS>"
5100 StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
5104 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
5105 "round.l.%s<FMT> f<FD>, f<FS>"
5117 StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5122 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
5123 "round.w.%s<FMT> f<FD>, f<FS>"
5138 StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5143 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
5144 "rsqrt.%s<FMT> f<FD>, f<FS>"
5153 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
5157 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
5158 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5164 do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5168 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5169 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5180 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5184 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
5185 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5193 check_u64 (SD_, instruction_0);
5194 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5198 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5199 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5205 address_word base = GPR[BASE];
5206 address_word index = GPR[INDEX];
5207 address_word vaddr = base + index;
5209 check_u64 (SD_, instruction_0);
5210 /* Arrange for the bottom 3 bits of (base + index) to be 0. */
5211 if ((vaddr & 0x7) != 0)
5212 index -= (vaddr & 0x7);
5213 do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5217 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
5218 "sqrt.%s<FMT> f<FD>, f<FS>"
5233 StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
5237 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
5238 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5254 check_fmt_p (SD_, fmt, instruction_0);
5255 StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5260 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
5261 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5275 address_word base = GPR[BASE];
5276 address_word offset = EXTEND16 (OFFSET);
5279 address_word vaddr = loadstore_ea (SD_, base, offset);
5282 if ((vaddr & 3) != 0)
5284 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5288 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5291 uword64 memval1 = 0;
5292 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5293 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5294 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5296 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5297 byte = ((vaddr & mask) ^ bigendiancpu);
5298 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
5299 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5306 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
5307 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5315 address_word base = GPR[BASE];
5316 address_word index = GPR[INDEX];
5318 check_u64 (SD_, instruction_0);
5320 address_word vaddr = loadstore_ea (SD_, base, index);
5323 if ((vaddr & 3) != 0)
5325 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5329 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5331 unsigned64 memval = 0;
5332 unsigned64 memval1 = 0;
5333 unsigned64 mask = 0x7;
5335 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5336 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5337 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
5339 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5347 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
5348 "trunc.l.%s<FMT> f<FD>, f<FS>"
5360 StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5365 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
5366 "trunc.w.%s<FMT> f<FD>, f<FS>"
5381 StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5387 // MIPS Architecture:
5389 // System Control Instruction Set (COP0)
5393 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5407 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5409 // stub needed for eCos as tx39 hardware bug workaround
5416 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5431 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5445 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5460 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5461 "cache <OP>, <OFFSET>(r<BASE>)"
5473 address_word base = GPR[BASE];
5474 address_word offset = EXTEND16 (OFFSET);
5476 address_word vaddr = loadstore_ea (SD_, base, offset);
5479 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5480 CacheOp(OP,vaddr,paddr,instruction_0);
5485 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5486 "dmfc0 r<RT>, r<RD>"
5493 check_u64 (SD_, instruction_0);
5494 DecodeCoproc (instruction_0);
5498 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5499 "dmtc0 r<RT>, r<RD>"
5506 check_u64 (SD_, instruction_0);
5507 DecodeCoproc (instruction_0);
5511 010000,1,0000000000000000000,011000:COP0:32::ERET
5523 if (SR & status_ERL)
5525 /* Oops, not yet available */
5526 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5538 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5539 "mfc0 r<RT>, r<RD> # <REGX>"
5553 TRACE_ALU_INPUT0 ();
5554 DecodeCoproc (instruction_0);
5555 TRACE_ALU_RESULT (GPR[RT]);
5558 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5559 "mtc0 r<RT>, r<RD> # <REGX>"
5573 DecodeCoproc (instruction_0);
5577 010000,1,0000000000000000000,010000:COP0:32::RFE
5588 DecodeCoproc (instruction_0);
5592 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5593 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5606 DecodeCoproc (instruction_0);
5611 010000,1,0000000000000000000,001000:COP0:32::TLBP
5626 010000,1,0000000000000000000,000001:COP0:32::TLBR
5641 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5656 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5671 :include:::mips3264r2.igen
5673 :include:::m16e.igen
5674 :include:::mdmx.igen
5675 :include:::mips3d.igen
5680 :include:::smartmips.igen