sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 // start-sanitize-vr4320
  47 :model:::vr4320:mips4320:
  48 // end-sanitize-vr4320
  49 // start-sanitize-vr5400
  50 :model:::vr5400:mips5400:
  51 :model:::mdmx:mdmx:
  52 // end-sanitize-vr5400
  53 :model:::vr5000:mips5000:
  54
  55
  56
  57 // Pseudo instructions known by IGEN
  58 :internal::::illegal:
  59 {
  60   SignalException (ReservedInstruction, 0);
  61 }
  62
  63
  64 // Pseudo instructions known by interp.c
  65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  67 "rsvd <OP>"
  68 {
  69   SignalException (ReservedInstruction, instruction_0);
  70 }
  71
  72
  73
  74 // Helper:
  75 //
  76 // Simulate a 32 bit delayslot instruction
  77 //
  78
  79 :function:::address_word:delayslot32:address_word target
  80 {
  81   instruction_word delay_insn;
  82   sim_events_slip (SD, 1);
  83   DSPC = CIA;
  84   CIA = CIA + 4; /* NOTE not mips16 */
  85   STATE |= simDELAYSLOT;
  86   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  87   idecode_issue (CPU_, delay_insn, (CIA));
  88   STATE &= ~simDELAYSLOT;
  89   return target;
  90 }
  91
  92 :function:::address_word:nullify_next_insn32:
  93 {
  94   sim_events_slip (SD, 1);
  95   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  96   return CIA + 8;
  97 }
  98
  99
 100
 101 // Helper:
 102 //
 103 // Check that an access to a HI/LO register meets timing requirements
 104 //
 105 // The following requirements exist:
 106 //
 107 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 108 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 109 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 110 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 111 //
 112
 113 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 114 {
 115   if (history->mf.timestamp + 3 > time)
 116     {
 117       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 118                         itable[MY_INDEX].name,
 119                         new, (long) CIA,
 120                         (long) history->mf.cia);
 121       return 0;
 122     }
 123   return 1;
 124 }
 125
 126 :function:::int:check_mt_hilo:hilo_history *history
 127 *mipsI,mipsII,mipsIII,mipsIV:
 128 *vr5000:
 129 // start-sanitize-vr4320
 130 *vr4320:
 131 // end-sanitize-vr4320
 132 // start-sanitize-vr5400
 133 *vr5400:
 134 // end-sanitize-vr5400
 135 {
 136   signed64 time = sim_events_time (SD);
 137   int ok = check_mf_cycles (SD_, history, time, "MT");
 138   history->mt.timestamp = time;
 139   history->mt.cia = CIA;
 140   return ok;
 141 }
 142
 143 :function:::int:check_mt_hilo:hilo_history *history
 144 *r3900:
 145 // start-sanitize-tx19
 146 *tx19:
 147 // end-sanitize-tx19
 148 // start-sanitize-r5900
 149 *r5900:
 150 // end-sanitize-r5900
 151 {
 152   signed64 time = sim_events_time (SD);
 153   history->mt.timestamp = time;
 154   history->mt.cia = CIA;
 155   return 1;
 156 }
 157
 158
 159 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 160 *mipsI,mipsII,mipsIII,mipsIV:
 161 *vr5000:
 162 // start-sanitize-vr4320
 163 *vr4320:
 164 // end-sanitize-vr4320
 165 // start-sanitize-vr5400
 166 *vr5400:
 167 // end-sanitize-vr5400
 168 *r3900:
 169 // start-sanitize-tx19
 170 *tx19:
 171 // end-sanitize-tx19
 172 {
 173   signed64 time = sim_events_time (SD);
 174   int ok = 1;
 175   if (peer != NULL
 176       && peer->mt.timestamp > history->op.timestamp
 177       && history->mf.timestamp < history->op.timestamp)
 178     {
 179       /* The peer has been written to since the last OP yet we have
 180          not */
 181       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 182                         itable[MY_INDEX].name,
 183                         (long) CIA,
 184                         (long) history->op.cia,
 185                         (long) peer->mt.cia);
 186       ok = 0;
 187     }
 188   history->mf.timestamp = time;
 189   history->mf.cia = CIA;
 190   return ok;
 191 }
 192
 193 // start-sanitize-r5900
 194 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
 195 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 196 // end-sanitize-r5900
 197 // start-sanitize-r5900
 198 *r5900:
 199 // end-sanitize-r5900
 200 // start-sanitize-r5900
 201 {
 202   /* FIXME: could record the fact that a stall occured if we want */
 203   signed64 time = sim_events_time (SD);
 204   history->mf.timestamp = time;
 205   history->mf.cia = CIA;
 206   return 1;
 207 }
 208 // end-sanitize-r5900
 209
 210
 211 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 212 *mipsI,mipsII,mipsIII,mipsIV:
 213 *vr5000:
 214 // start-sanitize-vr4320
 215 *vr4320:
 216 // end-sanitize-vr4320
 217 // start-sanitize-vr5400
 218 *vr5400:
 219 // end-sanitize-vr5400
 220 {
 221   signed64 time = sim_events_time (SD);
 222   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 223             && check_mf_cycles (SD_, lo, time, "OP"));
 224   hi->op.timestamp = time;
 225   lo->op.timestamp = time;
 226   hi->op.cia = CIA;
 227   lo->op.cia = CIA;
 228   return ok;
 229 }
 230
 231 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 232 // a mf{hi,lo}
 233 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 234 *r3900:
 235 // start-sanitize-tx19
 236 *tx19:
 237 // end-sanitize-tx19
 238 // start-sanitize-r5900
 239 *r5900:
 240 // end-sanitize-r5900
 241 {
 242   /* FIXME: could record the fact that a stall occured if we want */
 243   signed64 time = sim_events_time (SD);
 244   hi->op.timestamp = time;
 245   lo->op.timestamp = time;
 246   hi->op.cia = CIA;
 247   lo->op.cia = CIA;
 248   return 1;
 249 }
 250
 251
 252 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 253 *mipsI,mipsII,mipsIII,mipsIV:
 254 *vr5000:
 255 // start-sanitize-vr4320
 256 *vr4320:
 257 // end-sanitize-vr4320
 258 // start-sanitize-vr5400
 259 *vr5400:
 260 // end-sanitize-vr5400
 261 *r3900:
 262 // start-sanitize-tx19
 263 *tx19:
 264 // end-sanitize-tx19
 265 {
 266   signed64 time = sim_events_time (SD);
 267   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 268             && check_mf_cycles (SD_, lo, time, "OP"));
 269   hi->op.timestamp = time;
 270   lo->op.timestamp = time;
 271   hi->op.cia = CIA;
 272   lo->op.cia = CIA;
 273   return ok;
 274 }
 275
 276
 277 // start-sanitize-r5900
 278 // The r5900 div et.al insns _can_ be exectuted immediatly after
 279 // a mf{hi,lo}
 280 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 281 // end-sanitize-r5900
 282 // start-sanitize-r5900
 283 *r5900:
 284 // end-sanitize-r5900
 285 // start-sanitize-r5900
 286 {
 287   /* FIXME: could record the fact that a stall occured if we want */
 288   signed64 time = sim_events_time (SD);
 289   hi->op.timestamp = time;
 290   lo->op.timestamp = time;
 291   hi->op.cia = CIA;
 292   lo->op.cia = CIA;
 293   return 1;
 294 }
 295 // end-sanitize-r5900
 296
 297
 298
 299 //
 300 // Mips Architecture:
 301 //
 302 //        CPU Instruction Set (mipsI - mipsIV)
 303 //
 304
 305
 306
 307 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 308 "add r<RD>, r<RS>, r<RT>"
 309 *mipsI,mipsII,mipsIII,mipsIV:
 310 *vr5000:
 311 // start-sanitize-vr4320
 312 *vr4320:
 313 // end-sanitize-vr4320
 314 // start-sanitize-vr5400
 315 *vr5400:
 316 // end-sanitize-vr5400
 317 // start-sanitize-r5900
 318 *r5900:
 319 // end-sanitize-r5900
 320 *r3900:
 321 // start-sanitize-tx19
 322 *tx19:
 323 // end-sanitize-tx19
 324 {
 325   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 326   {
 327     ALU32_BEGIN (GPR[RS]);
 328     ALU32_ADD (GPR[RT]);
 329     ALU32_END (GPR[RD]);
 330   }
 331   TRACE_ALU_RESULT (GPR[RD]);
 332 }
 333
 334
 335
 336 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 337 "addi r<RT>, r<RS>, IMMEDIATE"
 338 *mipsI,mipsII,mipsIII,mipsIV:
 339 *vr5000:
 340 // start-sanitize-vr4320
 341 *vr4320:
 342 // end-sanitize-vr4320
 343 // start-sanitize-vr5400
 344 *vr5400:
 345 // end-sanitize-vr5400
 346 // start-sanitize-r5900
 347 *r5900:
 348 // end-sanitize-r5900
 349 *r3900:
 350 // start-sanitize-tx19
 351 *tx19:
 352 // end-sanitize-tx19
 353 {
 354   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 355   {
 356     ALU32_BEGIN (GPR[RS]);
 357     ALU32_ADD (EXTEND16 (IMMEDIATE));
 358     ALU32_END (GPR[RT]);
 359   }
 360   TRACE_ALU_RESULT (GPR[RT]);
 361 }
 362
 363
 364
 365 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 366 {
 367   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 368   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 369   TRACE_ALU_RESULT (GPR[rt]);
 370 }
 371
 372 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 373 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 374 *mipsI,mipsII,mipsIII,mipsIV:
 375 *vr5000:
 376 // start-sanitize-vr4320
 377 *vr4320:
 378 // end-sanitize-vr4320
 379 // start-sanitize-vr5400
 380 *vr5400:
 381 // end-sanitize-vr5400
 382 // start-sanitize-r5900
 383 *r5900:
 384 // end-sanitize-r5900
 385 *r3900:
 386 // start-sanitize-tx19
 387 *tx19:
 388 // end-sanitize-tx19
 389 {
 390   do_addiu (SD_, RS, RT, IMMEDIATE);
 391 }
 392
 393
 394
 395 :function:::void:do_addu:int rs, int rt, int rd
 396 {
 397   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 398   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 399   TRACE_ALU_RESULT (GPR[rd]);
 400 }
 401
 402 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 403 "addu r<RD>, r<RS>, r<RT>"
 404 *mipsI,mipsII,mipsIII,mipsIV:
 405 *vr5000:
 406 // start-sanitize-vr4320
 407 *vr4320:
 408 // end-sanitize-vr4320
 409 // start-sanitize-vr5400
 410 *vr5400:
 411 // end-sanitize-vr5400
 412 // start-sanitize-r5900
 413 *r5900:
 414 // end-sanitize-r5900
 415 *r3900:
 416 // start-sanitize-tx19
 417 *tx19:
 418 // end-sanitize-tx19
 419 {
 420   do_addu (SD_, RS, RT, RD);
 421 }
 422
 423
 424
 425 :function:::void:do_and:int rs, int rt, int rd
 426 {
 427   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 428   GPR[rd] = GPR[rs] & GPR[rt];
 429   TRACE_ALU_RESULT (GPR[rd]);
 430 }
 431
 432 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 433 "and r<RD>, r<RS>, r<RT>"
 434 *mipsI,mipsII,mipsIII,mipsIV:
 435 *vr5000:
 436 // start-sanitize-vr4320
 437 *vr4320:
 438 // end-sanitize-vr4320
 439 // start-sanitize-vr5400
 440 *vr5400:
 441 // end-sanitize-vr5400
 442 // start-sanitize-r5900
 443 *r5900:
 444 // end-sanitize-r5900
 445 *r3900:
 446 // start-sanitize-tx19
 447 *tx19:
 448 // end-sanitize-tx19
 449 {
 450   do_and (SD_, RS, RT, RD);
 451 }
 452
 453
 454
 455 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 456 "and r<RT>, r<RS>, <IMMEDIATE>"
 457 *mipsI,mipsII,mipsIII,mipsIV:
 458 *vr5000:
 459 // start-sanitize-vr4320
 460 *vr4320:
 461 // end-sanitize-vr4320
 462 // start-sanitize-vr5400
 463 *vr5400:
 464 // end-sanitize-vr5400
 465 // start-sanitize-r5900
 466 *r5900:
 467 // end-sanitize-r5900
 468 *r3900:
 469 // start-sanitize-tx19
 470 *tx19:
 471 // end-sanitize-tx19
 472 {
 473   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 474   GPR[RT] = GPR[RS] & IMMEDIATE;
 475   TRACE_ALU_RESULT (GPR[RT]);
 476 }
 477
 478
 479
 480 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 481 "beq r<RS>, r<RT>, <OFFSET>"
 482 *mipsI,mipsII,mipsIII,mipsIV:
 483 *vr5000:
 484 // start-sanitize-vr4320
 485 *vr4320:
 486 // end-sanitize-vr4320
 487 // start-sanitize-vr5400
 488 *vr5400:
 489 // end-sanitize-vr5400
 490 // start-sanitize-r5900
 491 *r5900:
 492 // end-sanitize-r5900
 493 *r3900:
 494 // start-sanitize-tx19
 495 *tx19:
 496 // end-sanitize-tx19
 497 {
 498   address_word offset = EXTEND16 (OFFSET) << 2;
 499   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 500     DELAY_SLOT (NIA + offset);
 501 }
 502
 503
 504
 505 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 506 "beql r<RS>, r<RT>, <OFFSET>"
 507 *mipsII:
 508 *mipsIII:
 509 *mipsIV:
 510 *vr5000:
 511 // start-sanitize-vr4320
 512 *vr4320:
 513 // end-sanitize-vr4320
 514 // start-sanitize-vr5400
 515 *vr5400:
 516 // end-sanitize-vr5400
 517 // start-sanitize-r5900
 518 *r5900:
 519 // end-sanitize-r5900
 520 *r3900:
 521 // start-sanitize-tx19
 522 *tx19:
 523 // end-sanitize-tx19
 524 {
 525   address_word offset = EXTEND16 (OFFSET) << 2;
 526   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 527     DELAY_SLOT (NIA + offset);
 528   else
 529     NULLIFY_NEXT_INSTRUCTION ();
 530 }
 531
 532
 533
 534 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 535 "bgez r<RS>, <OFFSET>"
 536 *mipsI,mipsII,mipsIII,mipsIV:
 537 *vr5000:
 538 // start-sanitize-vr4320
 539 *vr4320:
 540 // end-sanitize-vr4320
 541 // start-sanitize-vr5400
 542 *vr5400:
 543 // end-sanitize-vr5400
 544 // start-sanitize-r5900
 545 *r5900:
 546 // end-sanitize-r5900
 547 *r3900:
 548 // start-sanitize-tx19
 549 *tx19:
 550 // end-sanitize-tx19
 551 {
 552   address_word offset = EXTEND16 (OFFSET) << 2;
 553   if ((signed_word) GPR[RS] >= 0)
 554     DELAY_SLOT (NIA + offset);
 555 }
 556
 557
 558
 559 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 560 "bgezal r<RS>, <OFFSET>"
 561 *mipsI,mipsII,mipsIII,mipsIV:
 562 *vr5000:
 563 // start-sanitize-vr4320
 564 *vr4320:
 565 // end-sanitize-vr4320
 566 // start-sanitize-vr5400
 567 *vr5400:
 568 // end-sanitize-vr5400
 569 // start-sanitize-r5900
 570 *r5900:
 571 // end-sanitize-r5900
 572 *r3900:
 573 // start-sanitize-tx19
 574 *tx19:
 575 // end-sanitize-tx19
 576 {
 577   address_word offset = EXTEND16 (OFFSET) << 2;
 578   RA = (CIA + 8);
 579   if ((signed_word) GPR[RS] >= 0)
 580     DELAY_SLOT (NIA + offset);
 581 }
 582
 583
 584
 585 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 586 "bgezall r<RS>, <OFFSET>"
 587 *mipsII:
 588 *mipsIII:
 589 *mipsIV:
 590 *vr5000:
 591 // start-sanitize-vr4320
 592 *vr4320:
 593 // end-sanitize-vr4320
 594 // start-sanitize-vr5400
 595 *vr5400:
 596 // end-sanitize-vr5400
 597 // start-sanitize-r5900
 598 *r5900:
 599 // end-sanitize-r5900
 600 *r3900:
 601 // start-sanitize-tx19
 602 *tx19:
 603 // end-sanitize-tx19
 604 {
 605   address_word offset = EXTEND16 (OFFSET) << 2;
 606   RA = (CIA + 8);
 607   /* NOTE: The branch occurs AFTER the next instruction has been
 608      executed */
 609   if ((signed_word) GPR[RS] >= 0)
 610     DELAY_SLOT (NIA + offset);
 611   else
 612     NULLIFY_NEXT_INSTRUCTION ();
 613 }
 614
 615
 616
 617 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 618 "bgezl r<RS>, <OFFSET>"
 619 *mipsII:
 620 *mipsIII:
 621 *mipsIV:
 622 *vr5000:
 623 // start-sanitize-vr4320
 624 *vr4320:
 625 // end-sanitize-vr4320
 626 // start-sanitize-vr5400
 627 *vr5400:
 628 // end-sanitize-vr5400
 629 // start-sanitize-r5900
 630 *r5900:
 631 // end-sanitize-r5900
 632 *r3900:
 633 // start-sanitize-tx19
 634 *tx19:
 635 // end-sanitize-tx19
 636 {
 637   address_word offset = EXTEND16 (OFFSET) << 2;
 638   if ((signed_word) GPR[RS] >= 0)
 639     DELAY_SLOT (NIA + offset);
 640   else
 641     NULLIFY_NEXT_INSTRUCTION ();
 642 }
 643
 644
 645
 646 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 647 "bgtz r<RS>, <OFFSET>"
 648 *mipsI,mipsII,mipsIII,mipsIV:
 649 *vr5000:
 650 // start-sanitize-vr4320
 651 *vr4320:
 652 // end-sanitize-vr4320
 653 // start-sanitize-vr5400
 654 *vr5400:
 655 // end-sanitize-vr5400
 656 // start-sanitize-r5900
 657 *r5900:
 658 // end-sanitize-r5900
 659 *r3900:
 660 // start-sanitize-tx19
 661 *tx19:
 662 // end-sanitize-tx19
 663 {
 664   address_word offset = EXTEND16 (OFFSET) << 2;
 665   if ((signed_word) GPR[RS] > 0)
 666     DELAY_SLOT (NIA + offset);
 667 }
 668
 669
 670
 671 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 672 "bgtzl r<RS>, <OFFSET>"
 673 *mipsII:
 674 *mipsIII:
 675 *mipsIV:
 676 *vr5000:
 677 // start-sanitize-vr4320
 678 *vr4320:
 679 // end-sanitize-vr4320
 680 // start-sanitize-vr5400
 681 *vr5400:
 682 // end-sanitize-vr5400
 683 // start-sanitize-r5900
 684 *r5900:
 685 // end-sanitize-r5900
 686 *r3900:
 687 // start-sanitize-tx19
 688 *tx19:
 689 // end-sanitize-tx19
 690 {
 691   address_word offset = EXTEND16 (OFFSET) << 2;
 692   /* NOTE: The branch occurs AFTER the next instruction has been
 693      executed */
 694   if ((signed_word) GPR[RS] > 0)
 695     DELAY_SLOT (NIA + offset);
 696   else
 697     NULLIFY_NEXT_INSTRUCTION ();
 698 }
 699
 700
 701
 702 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 703 "blez r<RS>, <OFFSET>"
 704 *mipsI,mipsII,mipsIII,mipsIV:
 705 *vr5000:
 706 // start-sanitize-vr4320
 707 *vr4320:
 708 // end-sanitize-vr4320
 709 // start-sanitize-vr5400
 710 *vr5400:
 711 // end-sanitize-vr5400
 712 // start-sanitize-r5900
 713 *r5900:
 714 // end-sanitize-r5900
 715 *r3900:
 716 // start-sanitize-tx19
 717 *tx19:
 718 // end-sanitize-tx19
 719 {
 720   address_word offset = EXTEND16 (OFFSET) << 2;
 721   /* NOTE: The branch occurs AFTER the next instruction has been
 722      executed */
 723   if ((signed_word) GPR[RS] <= 0)
 724     DELAY_SLOT (NIA + offset);
 725 }
 726
 727
 728
 729 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 730 "bgezl r<RS>, <OFFSET>"
 731 *mipsII:
 732 *mipsIII:
 733 *mipsIV:
 734 *vr5000:
 735 // start-sanitize-vr4320
 736 *vr4320:
 737 // end-sanitize-vr4320
 738 // start-sanitize-vr5400
 739 *vr5400:
 740 // end-sanitize-vr5400
 741 // start-sanitize-r5900
 742 *r5900:
 743 // end-sanitize-r5900
 744 *r3900:
 745 // start-sanitize-tx19
 746 *tx19:
 747 // end-sanitize-tx19
 748 {
 749   address_word offset = EXTEND16 (OFFSET) << 2;
 750   if ((signed_word) GPR[RS] <= 0)
 751     DELAY_SLOT (NIA + offset);
 752   else
 753     NULLIFY_NEXT_INSTRUCTION ();
 754 }
 755
 756
 757
 758 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 759 "bltz r<RS>, <OFFSET>"
 760 *mipsI,mipsII,mipsIII,mipsIV:
 761 *vr5000:
 762 // start-sanitize-vr4320
 763 *vr4320:
 764 // end-sanitize-vr4320
 765 // start-sanitize-vr5400
 766 *vr5400:
 767 // end-sanitize-vr5400
 768 // start-sanitize-r5900
 769 *r5900:
 770 // end-sanitize-r5900
 771 *r3900:
 772 // start-sanitize-tx19
 773 *tx19:
 774 // end-sanitize-tx19
 775 {
 776   address_word offset = EXTEND16 (OFFSET) << 2;
 777   if ((signed_word) GPR[RS] < 0)
 778     DELAY_SLOT (NIA + offset);
 779 }
 780
 781
 782
 783 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 784 "bltzal r<RS>, <OFFSET>"
 785 *mipsI,mipsII,mipsIII,mipsIV:
 786 *vr5000:
 787 // start-sanitize-vr4320
 788 *vr4320:
 789 // end-sanitize-vr4320
 790 // start-sanitize-vr5400
 791 *vr5400:
 792 // end-sanitize-vr5400
 793 // start-sanitize-r5900
 794 *r5900:
 795 // end-sanitize-r5900
 796 *r3900:
 797 // start-sanitize-tx19
 798 *tx19:
 799 // end-sanitize-tx19
 800 {
 801   address_word offset = EXTEND16 (OFFSET) << 2;
 802   RA = (CIA + 8);
 803   /* NOTE: The branch occurs AFTER the next instruction has been
 804      executed */
 805   if ((signed_word) GPR[RS] < 0)
 806     DELAY_SLOT (NIA + offset);
 807 }
 808
 809
 810
 811 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 812 "bltzall r<RS>, <OFFSET>"
 813 *mipsII:
 814 *mipsIII:
 815 *mipsIV:
 816 *vr5000:
 817 // start-sanitize-vr4320
 818 *vr4320:
 819 // end-sanitize-vr4320
 820 // start-sanitize-vr5400
 821 *vr5400:
 822 // end-sanitize-vr5400
 823 // start-sanitize-r5900
 824 *r5900:
 825 // end-sanitize-r5900
 826 *r3900:
 827 // start-sanitize-tx19
 828 *tx19:
 829 // end-sanitize-tx19
 830 {
 831   address_word offset = EXTEND16 (OFFSET) << 2;
 832   RA = (CIA + 8);
 833   if ((signed_word) GPR[RS] < 0)
 834     DELAY_SLOT (NIA + offset);
 835   else
 836     NULLIFY_NEXT_INSTRUCTION ();
 837 }
 838
 839
 840
 841 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 842 "bltzl r<RS>, <OFFSET>"
 843 *mipsII:
 844 *mipsIII:
 845 *mipsIV:
 846 *vr5000:
 847 // start-sanitize-vr4320
 848 *vr4320:
 849 // end-sanitize-vr4320
 850 // start-sanitize-vr5400
 851 *vr5400:
 852 // end-sanitize-vr5400
 853 // start-sanitize-r5900
 854 *r5900:
 855 // end-sanitize-r5900
 856 *r3900:
 857 // start-sanitize-tx19
 858 *tx19:
 859 // end-sanitize-tx19
 860 {
 861   address_word offset = EXTEND16 (OFFSET) << 2;
 862   /* NOTE: The branch occurs AFTER the next instruction has been
 863      executed */
 864   if ((signed_word) GPR[RS] < 0)
 865     DELAY_SLOT (NIA + offset);
 866   else
 867     NULLIFY_NEXT_INSTRUCTION ();
 868 }
 869
 870
 871
 872 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 873 "bne r<RS>, r<RT>, <OFFSET>"
 874 *mipsI,mipsII,mipsIII,mipsIV:
 875 *vr5000:
 876 // start-sanitize-vr4320
 877 *vr4320:
 878 // end-sanitize-vr4320
 879 // start-sanitize-vr5400
 880 *vr5400:
 881 // end-sanitize-vr5400
 882 // start-sanitize-r5900
 883 *r5900:
 884 // end-sanitize-r5900
 885 *r3900:
 886 // start-sanitize-tx19
 887 *tx19:
 888 // end-sanitize-tx19
 889 {
 890   address_word offset = EXTEND16 (OFFSET) << 2;
 891   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 892     DELAY_SLOT (NIA + offset);
 893 }
 894
 895
 896
 897 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 898 "bnel r<RS>, r<RT>, <OFFSET>"
 899 *mipsII:
 900 *mipsIII:
 901 *mipsIV:
 902 *vr5000:
 903 // start-sanitize-vr4320
 904 *vr4320:
 905 // end-sanitize-vr4320
 906 // start-sanitize-vr5400
 907 *vr5400:
 908 // end-sanitize-vr5400
 909 // start-sanitize-r5900
 910 *r5900:
 911 // end-sanitize-r5900
 912 *r3900:
 913 // start-sanitize-tx19
 914 *tx19:
 915 // end-sanitize-tx19
 916 {
 917   address_word offset = EXTEND16 (OFFSET) << 2;
 918   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 919     DELAY_SLOT (NIA + offset);
 920   else
 921     NULLIFY_NEXT_INSTRUCTION ();
 922 }
 923
 924
 925
 926 000000,20.CODE,001101:SPECIAL:32::BREAK
 927 "break"
 928 *mipsI,mipsII,mipsIII,mipsIV:
 929 *vr5000:
 930 // start-sanitize-vr4320
 931 *vr4320:
 932 // end-sanitize-vr4320
 933 // start-sanitize-vr5400
 934 *vr5400:
 935 // end-sanitize-vr5400
 936 // start-sanitize-r5900
 937 *r5900:
 938 // end-sanitize-r5900
 939 *r3900:
 940 // start-sanitize-tx19
 941 *tx19:
 942 // end-sanitize-tx19
 943 {
 944   SignalException(BreakPoint, instruction_0);
 945 }
 946
 947
 948
 949 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 950 "cop<ZZ> <COP_FUN>"
 951 *mipsI,mipsII,mipsIII,mipsIV:
 952 // start-sanitize-r5900
 953 *r5900:
 954 // end-sanitize-r5900
 955 *r3900:
 956 // start-sanitize-tx19
 957 *tx19:
 958 // end-sanitize-tx19
 959 {
 960   DecodeCoproc (instruction_0);
 961 }
 962
 963
 964
 965 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 966 "dadd r<RD>, r<RS>, r<RT>"
 967 *mipsIII:
 968 *mipsIV:
 969 *vr5000:
 970 // start-sanitize-vr4320
 971 *vr4320:
 972 // end-sanitize-vr4320
 973 // start-sanitize-vr5400
 974 *vr5400:
 975 // end-sanitize-vr5400
 976 // start-sanitize-r5900
 977 *r5900:
 978 // end-sanitize-r5900
 979 // start-sanitize-tx19
 980 *tx19:
 981 // end-sanitize-tx19
 982 {
 983   /* this check's for overflow */
 984   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 985   {
 986     ALU64_BEGIN (GPR[RS]);
 987     ALU64_ADD (GPR[RT]);
 988     ALU64_END (GPR[RD]);
 989   }
 990   TRACE_ALU_RESULT (GPR[RD]);
 991 }
 992
 993
 994
 995 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 996 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 997 *mipsIII:
 998 *mipsIV:
 999 *vr5000:
1000 // start-sanitize-vr4320
1001 *vr4320:
1002 // end-sanitize-vr4320
1003 // start-sanitize-vr5400
1004 *vr5400:
1005 // end-sanitize-vr5400
1006 // start-sanitize-r5900
1007 *r5900:
1008 // end-sanitize-r5900
1009 // start-sanitize-tx19
1010 *tx19:
1011 // end-sanitize-tx19
1012 {
1013   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1014   {
1015     ALU64_BEGIN (GPR[RS]);
1016     ALU64_ADD (EXTEND16 (IMMEDIATE));
1017     ALU64_END (GPR[RT]);
1018   }
1019   TRACE_ALU_RESULT (GPR[RT]);
1020 }
1021
1022
1023
1024 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1025 {
1026   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1027   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1028   TRACE_ALU_RESULT (GPR[rt]);
1029 }
1030
1031 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1032 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1033 *mipsIII:
1034 *mipsIV:
1035 *vr5000:
1036 // start-sanitize-vr4320
1037 *vr4320:
1038 // end-sanitize-vr4320
1039 // start-sanitize-vr5400
1040 *vr5400:
1041 // end-sanitize-vr5400
1042 // start-sanitize-r5900
1043 *r5900:
1044 // end-sanitize-r5900
1045 // start-sanitize-tx19
1046 *tx19:
1047 // end-sanitize-tx19
1048 {
1049   do_daddiu (SD_, RS, RT, IMMEDIATE);
1050 }
1051
1052
1053
1054 :function:::void:do_daddu:int rs, int rt, int rd
1055 {
1056   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1057   GPR[rd] = GPR[rs] + GPR[rt];
1058   TRACE_ALU_RESULT (GPR[rd]);
1059 }
1060
1061 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1062 "daddu r<RD>, r<RS>, r<RT>"
1063 *mipsIII:
1064 *mipsIV:
1065 *vr5000:
1066 // start-sanitize-vr4320
1067 *vr4320:
1068 // end-sanitize-vr4320
1069 // start-sanitize-vr5400
1070 *vr5400:
1071 // end-sanitize-vr5400
1072 // start-sanitize-r5900
1073 *r5900:
1074 // end-sanitize-r5900
1075 // start-sanitize-tx19
1076 *tx19:
1077 // end-sanitize-tx19
1078 {
1079   do_daddu (SD_, RS, RT, RD);
1080 }
1081
1082
1083
1084 :function:64::void:do_ddiv:int rs, int rt
1085 {
1086   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1087   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1088   {
1089     signed64 n = GPR[rs];
1090     signed64 d = GPR[rt];
1091     if (d == 0)
1092       {
1093         LO = SIGNED64 (0x8000000000000000);
1094         HI = 0;
1095       }
1096     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1097       {
1098         LO = SIGNED64 (0x8000000000000000);
1099         HI = 0;
1100       }
1101     else
1102       {
1103         LO = (n / d);
1104         HI = (n % d);
1105       }
1106   }
1107   TRACE_ALU_RESULT2 (HI, LO);
1108 }
1109
1110 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1111 "ddiv r<RS>, r<RT>"
1112 *mipsIII:
1113 *mipsIV:
1114 *vr5000:
1115 // start-sanitize-vr4320
1116 *vr4320:
1117 // end-sanitize-vr4320
1118 // start-sanitize-vr5400
1119 *vr5400:
1120 // end-sanitize-vr5400
1121 // start-sanitize-r5900
1122 *r5900:
1123 // end-sanitize-r5900
1124 // start-sanitize-tx19
1125 *tx19:
1126 // end-sanitize-tx19
1127 {
1128   do_ddiv (SD_, RS, RT);
1129 }
1130
1131
1132
1133 :function:64::void:do_ddivu:int rs, int rt
1134 {
1135   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1136   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1137   {
1138     unsigned64 n = GPR[rs];
1139     unsigned64 d = GPR[rt];
1140     if (d == 0)
1141       {
1142         LO = SIGNED64 (0x8000000000000000);
1143         HI = 0;
1144       }
1145     else
1146       {
1147         LO = (n / d);
1148         HI = (n % d);
1149       }
1150   }
1151   TRACE_ALU_RESULT2 (HI, LO);
1152 }
1153
1154 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1155 "ddivu r<RS>, r<RT>"
1156 *mipsIII:
1157 *mipsIV:
1158 *vr5000:
1159 // start-sanitize-vr4320
1160 *vr4320:
1161 // end-sanitize-vr4320
1162 // start-sanitize-vr5400
1163 *vr5400:
1164 // end-sanitize-vr5400
1165 // start-sanitize-tx19
1166 *tx19:
1167 // end-sanitize-tx19
1168 {
1169   do_ddivu (SD_, RS, RT);
1170 }
1171
1172
1173
1174 :function:::void:do_div:int rs, int rt
1175 {
1176   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1177   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1178   {
1179     signed32 n = GPR[rs];
1180     signed32 d = GPR[rt];
1181     if (d == 0)
1182       {
1183         LO = EXTEND32 (0x80000000);
1184         HI = EXTEND32 (0);
1185       }
1186     else if (n == SIGNED32 (0x80000000) && d == -1)
1187       {
1188         LO = EXTEND32 (0x80000000);
1189         HI = EXTEND32 (0);
1190       }
1191     else
1192       {
1193         LO = EXTEND32 (n / d);
1194         HI = EXTEND32 (n % d);
1195       }
1196   }
1197   TRACE_ALU_RESULT2 (HI, LO);
1198 }
1199
1200 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1201 "div r<RS>, r<RT>"
1202 *mipsI,mipsII,mipsIII,mipsIV:
1203 *vr5000:
1204 // start-sanitize-vr4320
1205 *vr4320:
1206 // end-sanitize-vr4320
1207 // start-sanitize-vr5400
1208 *vr5400:
1209 // end-sanitize-vr5400
1210 // start-sanitize-r5900
1211 *r5900:
1212 // end-sanitize-r5900
1213 *r3900:
1214 // start-sanitize-tx19
1215 *tx19:
1216 // end-sanitize-tx19
1217 {
1218   do_div (SD_, RS, RT);
1219 }
1220
1221
1222
1223 :function:::void:do_divu:int rs, int rt
1224 {
1225   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1226   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1227   {
1228     unsigned32 n = GPR[rs];
1229     unsigned32 d = GPR[rt];
1230     if (d == 0)
1231       {
1232         LO = EXTEND32 (0x80000000);
1233         HI = EXTEND32 (0);
1234       }
1235    else
1236      {
1237        LO = EXTEND32 (n / d);
1238        HI = EXTEND32 (n % d);
1239      }
1240   }
1241   TRACE_ALU_RESULT2 (HI, LO);
1242 }
1243
1244 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1245 "divu r<RS>, r<RT>"
1246 *mipsI,mipsII,mipsIII,mipsIV:
1247 *vr5000:
1248 // start-sanitize-vr4320
1249 *vr4320:
1250 // end-sanitize-vr4320
1251 // start-sanitize-vr5400
1252 *vr5400:
1253 // end-sanitize-vr5400
1254 // start-sanitize-r5900
1255 *r5900:
1256 // end-sanitize-r5900
1257 *r3900:
1258 // start-sanitize-tx19
1259 *tx19:
1260 // end-sanitize-tx19
1261 {
1262   do_divu (SD_, RS, RT);
1263 }
1264
1265
1266
1267 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1268 {
1269   unsigned64 lo;
1270   unsigned64 hi;
1271   unsigned64 m00;
1272   unsigned64 m01;
1273   unsigned64 m10;
1274   unsigned64 m11;
1275   unsigned64 mid;
1276   int sign;
1277   unsigned64 op1 = GPR[rs];
1278   unsigned64 op2 = GPR[rt];
1279   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1280   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1281   /* make signed multiply unsigned */
1282   sign = 0;
1283   if (signed_p)
1284     {
1285       if (op1 < 0)
1286         {
1287           op1 = - op1;
1288           ++sign;
1289         }
1290       if (op2 < 0)
1291         {
1292           op2 = - op2;
1293           ++sign;
1294         }
1295     }
1296   /* multuply out the 4 sub products */
1297   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1298   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1299   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1300   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1301   /* add the products */
1302   mid = ((unsigned64) VH4_8 (m00)
1303          + (unsigned64) VL4_8 (m10)
1304          + (unsigned64) VL4_8 (m01));
1305   lo = U8_4 (mid, m00);
1306   hi = (m11
1307         + (unsigned64) VH4_8 (mid)
1308         + (unsigned64) VH4_8 (m01)
1309         + (unsigned64) VH4_8 (m10));
1310   /* fix the sign */
1311   if (sign & 1)
1312     {
1313       lo = -lo;
1314       if (lo == 0)
1315         hi = -hi;
1316       else
1317         hi = -hi - 1;
1318     }
1319   /* save the result HI/LO (and a gpr) */
1320   LO = lo;
1321   HI = hi;
1322   if (rd != 0)
1323     GPR[rd] = lo;
1324   TRACE_ALU_RESULT2 (HI, LO);
1325 }
1326
1327 :function:::void:do_dmult:int rs, int rt, int rd
1328 {
1329   do_dmultx (SD_, rs, rt, rd, 1);
1330 }
1331
1332 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1333 "dmult r<RS>, r<RT>"
1334 *mipsIII,mipsIV:
1335 // start-sanitize-tx19
1336 *tx19:
1337 // end-sanitize-tx19
1338 // start-sanitize-vr4320
1339 *vr4320:
1340 // end-sanitize-vr4320
1341 {
1342   do_dmult (SD_, RS, RT, 0);
1343 }
1344
1345 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1346 "dmult r<RS>, r<RT>":RD == 0
1347 "dmult r<RD>, r<RS>, r<RT>"
1348 *vr5000:
1349 // start-sanitize-vr5400
1350 *vr5400:
1351 // end-sanitize-vr5400
1352 {
1353   do_dmult (SD_, RS, RT, RD);
1354 }
1355
1356
1357
1358 :function:::void:do_dmultu:int rs, int rt, int rd
1359 {
1360   do_dmultx (SD_, rs, rt, rd, 0);
1361 }
1362
1363 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1364 "dmultu r<RS>, r<RT>"
1365 *mipsIII,mipsIV:
1366 // start-sanitize-tx19
1367 *tx19:
1368 // end-sanitize-tx19
1369 // start-sanitize-vr4320
1370 *vr4320:
1371 // end-sanitize-vr4320
1372 {
1373   do_dmultu (SD_, RS, RT, 0);
1374 }
1375
1376 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1377 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1378 "dmultu r<RS>, r<RT>"
1379 *vr5000:
1380 // start-sanitize-vr5400
1381 *vr5400:
1382 // end-sanitize-vr5400
1383 {
1384   do_dmultu (SD_, RS, RT, RD);
1385 }
1386
1387
1388
1389 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1390 "dsll r<RD>, r<RT>, <SHIFT>"
1391 *mipsIII:
1392 *mipsIV:
1393 *vr5000:
1394 // start-sanitize-vr4320
1395 *vr4320:
1396 // end-sanitize-vr4320
1397 // start-sanitize-vr5400
1398 *vr5400:
1399 // end-sanitize-vr5400
1400 // start-sanitize-r5900
1401 *r5900:
1402 // end-sanitize-r5900
1403 // start-sanitize-tx19
1404 *tx19:
1405 // end-sanitize-tx19
1406 {
1407   int s = SHIFT;
1408   GPR[RD] = GPR[RT] << s;
1409 }
1410
1411
1412 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1413 "dsll32 r<RD>, r<RT>, <SHIFT>"
1414 *mipsIII:
1415 *mipsIV:
1416 *vr5000:
1417 // start-sanitize-vr4320
1418 *vr4320:
1419 // end-sanitize-vr4320
1420 // start-sanitize-vr5400
1421 *vr5400:
1422 // end-sanitize-vr5400
1423 // start-sanitize-r5900
1424 *r5900:
1425 // end-sanitize-r5900
1426 // start-sanitize-tx19
1427 *tx19:
1428 // end-sanitize-tx19
1429 {
1430   int s = 32 + SHIFT;
1431   GPR[RD] = GPR[RT] << s;
1432 }
1433
1434
1435
1436 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1437 "dsllv r<RD>, r<RT>, r<RS>"
1438 *mipsIII:
1439 *mipsIV:
1440 *vr5000:
1441 // start-sanitize-vr4320
1442 *vr4320:
1443 // end-sanitize-vr4320
1444 // start-sanitize-vr5400
1445 *vr5400:
1446 // end-sanitize-vr5400
1447 // start-sanitize-r5900
1448 *r5900:
1449 // end-sanitize-r5900
1450 // start-sanitize-tx19
1451 *tx19:
1452 // end-sanitize-tx19
1453 {
1454   int s = MASKED64 (GPR[RS], 5, 0);
1455   GPR[RD] = GPR[RT] << s;
1456 }
1457
1458
1459
1460 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1461 "dsra r<RD>, r<RT>, <SHIFT>"
1462 *mipsIII:
1463 *mipsIV:
1464 *vr5000:
1465 // start-sanitize-vr4320
1466 *vr4320:
1467 // end-sanitize-vr4320
1468 // start-sanitize-vr5400
1469 *vr5400:
1470 // end-sanitize-vr5400
1471 // start-sanitize-r5900
1472 *r5900:
1473 // end-sanitize-r5900
1474 // start-sanitize-tx19
1475 *tx19:
1476 // end-sanitize-tx19
1477 {
1478   int s = SHIFT;
1479   GPR[RD] = ((signed64) GPR[RT]) >> s;
1480 }
1481
1482
1483 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1484 "dsra32 r<RT>, r<RD>, <SHIFT>"
1485 *mipsIII:
1486 *mipsIV:
1487 *vr5000:
1488 // start-sanitize-vr4320
1489 *vr4320:
1490 // end-sanitize-vr4320
1491 // start-sanitize-vr5400
1492 *vr5400:
1493 // end-sanitize-vr5400
1494 // start-sanitize-r5900
1495 *r5900:
1496 // end-sanitize-r5900
1497 // start-sanitize-tx19
1498 *tx19:
1499 // end-sanitize-tx19
1500 {
1501   int s = 32 + SHIFT;
1502   GPR[RD] = ((signed64) GPR[RT]) >> s;
1503 }
1504
1505
1506 :function:::void:do_dsrav:int rs, int rt, int rd
1507 {
1508   int s = MASKED64 (GPR[rs], 5, 0);
1509   TRACE_ALU_INPUT2 (GPR[rt], s);
1510   GPR[rd] = ((signed64) GPR[rt]) >> s;
1511   TRACE_ALU_RESULT (GPR[rd]);
1512 }
1513
1514 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1515 "dsra32 r<RT>, r<RD>, r<RS>"
1516 *mipsIII:
1517 *mipsIV:
1518 *vr5000:
1519 // start-sanitize-vr4320
1520 *vr4320:
1521 // end-sanitize-vr4320
1522 // start-sanitize-vr5400
1523 *vr5400:
1524 // end-sanitize-vr5400
1525 // start-sanitize-r5900
1526 *r5900:
1527 // end-sanitize-r5900
1528 // start-sanitize-tx19
1529 *tx19:
1530 // end-sanitize-tx19
1531 {
1532   do_dsrav (SD_, RS, RT, RD);
1533 }
1534
1535
1536 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1537 "dsrl r<RD>, r<RT>, <SHIFT>"
1538 *mipsIII:
1539 *mipsIV:
1540 *vr5000:
1541 // start-sanitize-vr4320
1542 *vr4320:
1543 // end-sanitize-vr4320
1544 // start-sanitize-vr5400
1545 *vr5400:
1546 // end-sanitize-vr5400
1547 // start-sanitize-r5900
1548 *r5900:
1549 // end-sanitize-r5900
1550 // start-sanitize-tx19
1551 *tx19:
1552 // end-sanitize-tx19
1553 {
1554   int s = SHIFT;
1555   GPR[RD] = (unsigned64) GPR[RT] >> s;
1556 }
1557
1558
1559 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1560 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1561 *mipsIII:
1562 *mipsIV:
1563 *vr5000:
1564 // start-sanitize-vr4320
1565 *vr4320:
1566 // end-sanitize-vr4320
1567 // start-sanitize-vr5400
1568 *vr5400:
1569 // end-sanitize-vr5400
1570 // start-sanitize-r5900
1571 *r5900:
1572 // end-sanitize-r5900
1573 // start-sanitize-tx19
1574 *tx19:
1575 // end-sanitize-tx19
1576 {
1577   int s = 32 + SHIFT;
1578   GPR[RD] = (unsigned64) GPR[RT] >> s;
1579 }
1580
1581
1582 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1583 "dsrl32 r<RD>, r<RT>, r<RS>"
1584 *mipsIII:
1585 *mipsIV:
1586 *vr5000:
1587 // start-sanitize-vr4320
1588 *vr4320:
1589 // end-sanitize-vr4320
1590 // start-sanitize-vr5400
1591 *vr5400:
1592 // end-sanitize-vr5400
1593 // start-sanitize-r5900
1594 *r5900:
1595 // end-sanitize-r5900
1596 // start-sanitize-tx19
1597 *tx19:
1598 // end-sanitize-tx19
1599 {
1600   int s = MASKED64 (GPR[RS], 5, 0);
1601   GPR[RD] = (unsigned64) GPR[RT] >> s;
1602 }
1603
1604
1605 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1606 "dsub r<RD>, r<RS>, r<RT>"
1607 *mipsIII:
1608 *mipsIV:
1609 *vr5000:
1610 // start-sanitize-vr4320
1611 *vr4320:
1612 // end-sanitize-vr4320
1613 // start-sanitize-vr5400
1614 *vr5400:
1615 // end-sanitize-vr5400
1616 // start-sanitize-r5900
1617 *r5900:
1618 // end-sanitize-r5900
1619 // start-sanitize-tx19
1620 *tx19:
1621 // end-sanitize-tx19
1622 {
1623   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1624   {
1625     ALU64_BEGIN (GPR[RS]);
1626     ALU64_SUB (GPR[RT]);
1627     ALU64_END (GPR[RD]);
1628   }
1629   TRACE_ALU_RESULT (GPR[RD]);
1630 }
1631
1632
1633 :function:::void:do_dsubu:int rs, int rt, int rd
1634 {
1635   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1636   GPR[rd] = GPR[rs] - GPR[rt];
1637   TRACE_ALU_RESULT (GPR[rd]);
1638 }
1639
1640 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1641 "dsubu r<RD>, r<RS>, r<RT>"
1642 *mipsIII:
1643 *mipsIV:
1644 *vr5000:
1645 // start-sanitize-vr4320
1646 *vr4320:
1647 // end-sanitize-vr4320
1648 // start-sanitize-vr5400
1649 *vr5400:
1650 // end-sanitize-vr5400
1651 // start-sanitize-r5900
1652 *r5900:
1653 // end-sanitize-r5900
1654 // start-sanitize-tx19
1655 *tx19:
1656 // end-sanitize-tx19
1657 {
1658   do_dsubu (SD_, RS, RT, RD);
1659 }
1660
1661
1662 000010,26.INSTR_INDEX:NORMAL:32::J
1663 "j <INSTR_INDEX>"
1664 *mipsI,mipsII,mipsIII,mipsIV:
1665 *vr5000:
1666 // start-sanitize-vr4320
1667 *vr4320:
1668 // end-sanitize-vr4320
1669 // start-sanitize-vr5400
1670 *vr5400:
1671 // end-sanitize-vr5400
1672 // start-sanitize-r5900
1673 *r5900:
1674 // end-sanitize-r5900
1675 *r3900:
1676 // start-sanitize-tx19
1677 *tx19:
1678 // end-sanitize-tx19
1679 {
1680   /* NOTE: The region used is that of the delay slot NIA and NOT the
1681      current instruction */
1682   address_word region = (NIA & MASK (63, 28));
1683   DELAY_SLOT (region | (INSTR_INDEX << 2));
1684 }
1685
1686
1687 000011,26.INSTR_INDEX:NORMAL:32::JAL
1688 "jal <INSTR_INDEX>"
1689 *mipsI,mipsII,mipsIII,mipsIV:
1690 *vr5000:
1691 // start-sanitize-vr4320
1692 *vr4320:
1693 // end-sanitize-vr4320
1694 // start-sanitize-vr5400
1695 *vr5400:
1696 // end-sanitize-vr5400
1697 // start-sanitize-r5900
1698 *r5900:
1699 // end-sanitize-r5900
1700 *r3900:
1701 // start-sanitize-tx19
1702 *tx19:
1703 // end-sanitize-tx19
1704 {
1705   /* NOTE: The region used is that of the delay slot and NOT the
1706      current instruction */
1707   address_word region = (NIA & MASK (63, 28));
1708   GPR[31] = CIA + 8;
1709   DELAY_SLOT (region | (INSTR_INDEX << 2));
1710 }
1711
1712
1713 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1714 "jalr r<RS>":RD == 31
1715 "jalr r<RD>, r<RS>"
1716 *mipsI,mipsII,mipsIII,mipsIV:
1717 *vr5000:
1718 // start-sanitize-vr4320
1719 *vr4320:
1720 // end-sanitize-vr4320
1721 // start-sanitize-vr5400
1722 *vr5400:
1723 // end-sanitize-vr5400
1724 // start-sanitize-r5900
1725 *r5900:
1726 // end-sanitize-r5900
1727 *r3900:
1728 // start-sanitize-tx19
1729 *tx19:
1730 // end-sanitize-tx19
1731 {
1732   address_word temp = GPR[RS];
1733   GPR[RD] = CIA + 8;
1734   DELAY_SLOT (temp);
1735 }
1736
1737
1738 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1739 "jr r<RS>"
1740 *mipsI,mipsII,mipsIII,mipsIV:
1741 *vr5000:
1742 // start-sanitize-vr4320
1743 *vr4320:
1744 // end-sanitize-vr4320
1745 // start-sanitize-vr5400
1746 *vr5400:
1747 // end-sanitize-vr5400
1748 // start-sanitize-r5900
1749 *r5900:
1750 // end-sanitize-r5900
1751 *r3900:
1752 // start-sanitize-tx19
1753 *tx19:
1754 // end-sanitize-tx19
1755 {
1756   DELAY_SLOT (GPR[RS]);
1757 }
1758
1759
1760 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1761 {
1762   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1763   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1764   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1765   unsigned int byte;
1766   address_word paddr;
1767   int uncached;
1768   unsigned64 memval;
1769   address_word vaddr;
1770
1771   vaddr = base + offset;
1772   if ((vaddr & access) != 0)
1773     SignalExceptionAddressLoad ();
1774   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1775   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1776   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1777   byte = ((vaddr & mask) ^ bigendiancpu);
1778   return (memval >> (8 * byte));
1779 }
1780
1781
1782 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1783 "lb r<RT>, <OFFSET>(r<BASE>)"
1784 *mipsI,mipsII,mipsIII,mipsIV:
1785 *vr5000:
1786 // start-sanitize-vr4320
1787 *vr4320:
1788 // end-sanitize-vr4320
1789 // start-sanitize-vr5400
1790 *vr5400:
1791 // end-sanitize-vr5400
1792 // start-sanitize-r5900
1793 *r5900:
1794 // end-sanitize-r5900
1795 *r3900:
1796 // start-sanitize-tx19
1797 *tx19:
1798 // end-sanitize-tx19
1799 {
1800   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1801 }
1802
1803
1804 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1805 "lbu r<RT>, <OFFSET>(r<BASE>)"
1806 *mipsI,mipsII,mipsIII,mipsIV:
1807 *vr5000:
1808 // start-sanitize-vr4320
1809 *vr4320:
1810 // end-sanitize-vr4320
1811 // start-sanitize-vr5400
1812 *vr5400:
1813 // end-sanitize-vr5400
1814 // start-sanitize-r5900
1815 *r5900:
1816 // end-sanitize-r5900
1817 *r3900:
1818 // start-sanitize-tx19
1819 *tx19:
1820 // end-sanitize-tx19
1821 {
1822   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1823 }
1824
1825
1826 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1827 "ld r<RT>, <OFFSET>(r<BASE>)"
1828 *mipsIII:
1829 *mipsIV:
1830 *vr5000:
1831 // start-sanitize-vr4320
1832 *vr4320:
1833 // end-sanitize-vr4320
1834 // start-sanitize-vr5400
1835 *vr5400:
1836 // end-sanitize-vr5400
1837 // start-sanitize-r5900
1838 *r5900:
1839 // end-sanitize-r5900
1840 // start-sanitize-tx19
1841 *tx19:
1842 // end-sanitize-tx19
1843 {
1844   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1845 }
1846
1847
1848 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1849 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1850 *mipsII:
1851 *mipsIII:
1852 *mipsIV:
1853 *vr5000:
1854 // start-sanitize-vr4320
1855 *vr4320:
1856 // end-sanitize-vr4320
1857 // start-sanitize-vr5400
1858 *vr5400:
1859 // end-sanitize-vr5400
1860 *r3900:
1861 // start-sanitize-tx19
1862 *tx19:
1863 // end-sanitize-tx19
1864 {
1865   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1866 }
1867
1868
1869
1870
1871 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1872 "ldl r<RT>, <OFFSET>(r<BASE>)"
1873 *mipsIII:
1874 *mipsIV:
1875 *vr5000:
1876 // start-sanitize-vr4320
1877 *vr4320:
1878 // end-sanitize-vr4320
1879 // start-sanitize-vr5400
1880 *vr5400:
1881 // end-sanitize-vr5400
1882 // start-sanitize-r5900
1883 *r5900:
1884 // end-sanitize-r5900
1885 // start-sanitize-tx19
1886 *tx19:
1887 // end-sanitize-tx19
1888 {
1889   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1890 }
1891
1892
1893 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1894 "ldr r<RT>, <OFFSET>(r<BASE>)"
1895 *mipsIII:
1896 *mipsIV:
1897 *vr5000:
1898 // start-sanitize-vr4320
1899 *vr4320:
1900 // end-sanitize-vr4320
1901 // start-sanitize-vr5400
1902 *vr5400:
1903 // end-sanitize-vr5400
1904 // start-sanitize-r5900
1905 *r5900:
1906 // end-sanitize-r5900
1907 // start-sanitize-tx19
1908 *tx19:
1909 // end-sanitize-tx19
1910 {
1911   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1912 }
1913
1914
1915 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1916 "lh r<RT>, <OFFSET>(r<BASE>)"
1917 *mipsI,mipsII,mipsIII,mipsIV:
1918 *vr5000:
1919 // start-sanitize-vr4320
1920 *vr4320:
1921 // end-sanitize-vr4320
1922 // start-sanitize-vr5400
1923 *vr5400:
1924 // end-sanitize-vr5400
1925 // start-sanitize-r5900
1926 *r5900:
1927 // end-sanitize-r5900
1928 *r3900:
1929 // start-sanitize-tx19
1930 *tx19:
1931 // end-sanitize-tx19
1932 {
1933   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1934 }
1935
1936
1937 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1938 "lhu r<RT>, <OFFSET>(r<BASE>)"
1939 *mipsI,mipsII,mipsIII,mipsIV:
1940 *vr5000:
1941 // start-sanitize-vr4320
1942 *vr4320:
1943 // end-sanitize-vr4320
1944 // start-sanitize-vr5400
1945 *vr5400:
1946 // end-sanitize-vr5400
1947 // start-sanitize-r5900
1948 *r5900:
1949 // end-sanitize-r5900
1950 *r3900:
1951 // start-sanitize-tx19
1952 *tx19:
1953 // end-sanitize-tx19
1954 {
1955   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1956 }
1957
1958
1959 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1960 "ll r<RT>, <OFFSET>(r<BASE>)"
1961 *mipsII:
1962 *mipsIII:
1963 *mipsIV:
1964 *vr5000:
1965 // start-sanitize-vr4320
1966 *vr4320:
1967 // end-sanitize-vr4320
1968 // start-sanitize-vr5400
1969 *vr5400:
1970 // end-sanitize-vr5400
1971 // start-sanitize-r5900
1972 *r5900:
1973 // end-sanitize-r5900
1974 // start-sanitize-tx19
1975 *tx19:
1976 // end-sanitize-tx19
1977 {
1978   unsigned32 instruction = instruction_0;
1979   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1980   int destreg = ((instruction >> 16) & 0x0000001F);
1981   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1982   {
1983     address_word vaddr = ((unsigned64)op1 + offset);
1984     address_word paddr;
1985     int uncached;
1986     if ((vaddr & 3) != 0)
1987       SignalExceptionAddressLoad();
1988     else
1989       {
1990         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1991           {
1992             unsigned64 memval = 0;
1993             unsigned64 memval1 = 0;
1994             unsigned64 mask = 0x7;
1995             unsigned int shift = 2;
1996             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1997             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1998             unsigned int byte;
1999             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2000             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2001             byte = ((vaddr & mask) ^ (bigend << shift));
2002             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2003             LLBIT = 1;
2004           }
2005       }
2006   }
2007 }
2008
2009
2010 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2011 "lld r<RT>, <OFFSET>(r<BASE>)"
2012 *mipsIII:
2013 *mipsIV:
2014 *vr5000:
2015 // start-sanitize-vr4320
2016 *vr4320:
2017 // end-sanitize-vr4320
2018 // start-sanitize-vr5400
2019 *vr5400:
2020 // end-sanitize-vr5400
2021 // start-sanitize-r5900
2022 *r5900:
2023 // end-sanitize-r5900
2024 // start-sanitize-tx19
2025 *tx19:
2026 // end-sanitize-tx19
2027 {
2028   unsigned32 instruction = instruction_0;
2029   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2030   int destreg = ((instruction >> 16) & 0x0000001F);
2031   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2032   {
2033     address_word vaddr = ((unsigned64)op1 + offset);
2034     address_word paddr;
2035     int uncached;
2036     if ((vaddr & 7) != 0)
2037       SignalExceptionAddressLoad();
2038     else
2039       {
2040         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2041           {
2042             unsigned64 memval = 0;
2043             unsigned64 memval1 = 0;
2044             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2045             GPR[destreg] = memval;
2046             LLBIT = 1;
2047           }
2048       }
2049   }
2050 }
2051
2052
2053 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2054 "lui r<RT>, <IMMEDIATE>"
2055 *mipsI,mipsII,mipsIII,mipsIV:
2056 *vr5000:
2057 // start-sanitize-vr4320
2058 *vr4320:
2059 // end-sanitize-vr4320
2060 // start-sanitize-vr5400
2061 *vr5400:
2062 // end-sanitize-vr5400
2063 // start-sanitize-r5900
2064 *r5900:
2065 // end-sanitize-r5900
2066 *r3900:
2067 // start-sanitize-tx19
2068 *tx19:
2069 // end-sanitize-tx19
2070 {
2071   TRACE_ALU_INPUT1 (IMMEDIATE);
2072   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2073   TRACE_ALU_RESULT (GPR[RT]);
2074 }
2075
2076
2077 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2078 "lw r<RT>, <OFFSET>(r<BASE>)"
2079 *mipsI,mipsII,mipsIII,mipsIV:
2080 *vr5000:
2081 // start-sanitize-vr4320
2082 *vr4320:
2083 // end-sanitize-vr4320
2084 // start-sanitize-vr5400
2085 *vr5400:
2086 // end-sanitize-vr5400
2087 // start-sanitize-r5900
2088 *r5900:
2089 // end-sanitize-r5900
2090 *r3900:
2091 // start-sanitize-tx19
2092 *tx19:
2093 // end-sanitize-tx19
2094 {
2095   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2096 }
2097
2098
2099 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2100 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2101 *mipsI,mipsII,mipsIII,mipsIV:
2102 *vr5000:
2103 // start-sanitize-vr4320
2104 *vr4320:
2105 // end-sanitize-vr4320
2106 // start-sanitize-vr5400
2107 *vr5400:
2108 // end-sanitize-vr5400
2109 // start-sanitize-r5900
2110 *r5900:
2111 // end-sanitize-r5900
2112 *r3900:
2113 // start-sanitize-tx19
2114 *tx19:
2115 // end-sanitize-tx19
2116 {
2117   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2118 }
2119
2120
2121 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2122 {
2123   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2124   address_word reverseendian = (ReverseEndian ? -1 : 0);
2125   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2126   unsigned int byte;
2127   unsigned int word;
2128   address_word paddr;
2129   int uncached;
2130   unsigned64 memval;
2131   address_word vaddr;
2132   int nr_lhs_bits;
2133   int nr_rhs_bits;
2134   unsigned_word lhs_mask;
2135   unsigned_word temp;
2136
2137   vaddr = base + offset;
2138   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2139   paddr = (paddr ^ (reverseendian & mask));
2140   if (BigEndianMem == 0)
2141     paddr = paddr & ~access;
2142
2143   /* compute where within the word/mem we are */
2144   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2145   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2146   nr_lhs_bits = 8 * byte + 8;
2147   nr_rhs_bits = 8 * access - 8 * byte;
2148   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2149
2150   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2151            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2152            (long) ((unsigned64) paddr >> 32), (long) paddr,
2153            word, byte, nr_lhs_bits, nr_rhs_bits); */
2154
2155   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2156   if (word == 0)
2157     {
2158       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2159       temp = (memval << nr_rhs_bits);
2160     }
2161   else
2162     {
2163       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2164       temp = (memval >> nr_lhs_bits);
2165     }
2166   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2167   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2168
2169   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2170            (long) ((unsigned64) memval >> 32), (long) memval,
2171            (long) ((unsigned64) temp >> 32), (long) temp,
2172            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2173            (long) (rt >> 32), (long) rt); */
2174   return rt;
2175 }
2176
2177
2178 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2179 "lwl r<RT>, <OFFSET>(r<BASE>)"
2180 *mipsI,mipsII,mipsIII,mipsIV:
2181 *vr5000:
2182 // start-sanitize-vr4320
2183 *vr4320:
2184 // end-sanitize-vr4320
2185 // start-sanitize-vr5400
2186 *vr5400:
2187 // end-sanitize-vr5400
2188 // start-sanitize-r5900
2189 *r5900:
2190 // end-sanitize-r5900
2191 *r3900:
2192 // start-sanitize-tx19
2193 *tx19:
2194 // end-sanitize-tx19
2195 {
2196   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2197 }
2198
2199
2200 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2201 {
2202   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2203   address_word reverseendian = (ReverseEndian ? -1 : 0);
2204   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2205   unsigned int byte;
2206   address_word paddr;
2207   int uncached;
2208   unsigned64 memval;
2209   address_word vaddr;
2210
2211   vaddr = base + offset;
2212   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2213   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2214   paddr = (paddr ^ (reverseendian & mask));
2215   if (BigEndianMem != 0)
2216     paddr = paddr & ~access;
2217   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2218   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2219   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2220   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2221      (long) paddr, byte, (long) paddr, (long) memval); */
2222   {
2223     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2224     rt &= ~screen;
2225     rt |= (memval >> (8 * byte)) & screen;
2226   }
2227   return rt;
2228 }
2229
2230
2231 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2232 "lwr r<RT>, <OFFSET>(r<BASE>)"
2233 *mipsI,mipsII,mipsIII,mipsIV:
2234 *vr5000:
2235 // start-sanitize-vr4320
2236 *vr4320:
2237 // end-sanitize-vr4320
2238 // start-sanitize-vr5400
2239 *vr5400:
2240 // end-sanitize-vr5400
2241 // start-sanitize-r5900
2242 *r5900:
2243 // end-sanitize-r5900
2244 *r3900:
2245 // start-sanitize-tx19
2246 *tx19:
2247 // end-sanitize-tx19
2248 {
2249   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2250 }
2251
2252
2253 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2254 "lwu r<RT>, <OFFSET>(r<BASE>)"
2255 *mipsIII:
2256 *mipsIV:
2257 *vr5000:
2258 // start-sanitize-vr4320
2259 *vr4320:
2260 // end-sanitize-vr4320
2261 // start-sanitize-vr5400
2262 *vr5400:
2263 // end-sanitize-vr5400
2264 // start-sanitize-r5900
2265 *r5900:
2266 // end-sanitize-r5900
2267 // start-sanitize-tx19
2268 *tx19:
2269 // end-sanitize-tx19
2270 {
2271   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2272 }
2273
2274
2275 :function:::void:do_mfhi:int rd
2276 {
2277   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2278   TRACE_ALU_INPUT1 (HI);
2279   GPR[rd] = HI;
2280   TRACE_ALU_RESULT (GPR[rd]);
2281 }
2282
2283 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2284 "mfhi r<RD>"
2285 *mipsI,mipsII,mipsIII,mipsIV:
2286 *vr5000:
2287 // start-sanitize-vr4320
2288 *vr4320:
2289 // end-sanitize-vr4320
2290 // start-sanitize-vr5400
2291 *vr5400:
2292 // end-sanitize-vr5400
2293 // start-sanitize-r5900
2294 *r5900:
2295 // end-sanitize-r5900
2296 *r3900:
2297 // start-sanitize-tx19
2298 *tx19:
2299 // end-sanitize-tx19
2300 {
2301   do_mfhi (SD_, RD);
2302 }
2303
2304
2305
2306 :function:::void:do_mflo:int rd
2307 {
2308   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2309   TRACE_ALU_INPUT1 (LO);
2310   GPR[rd] = LO;
2311   TRACE_ALU_RESULT (GPR[rd]);
2312 }
2313
2314 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2315 "mflo r<RD>"
2316 *mipsI,mipsII,mipsIII,mipsIV:
2317 *vr5000:
2318 // start-sanitize-vr4320
2319 *vr4320:
2320 // end-sanitize-vr4320
2321 // start-sanitize-vr5400
2322 *vr5400:
2323 // end-sanitize-vr5400
2324 // start-sanitize-r5900
2325 *r5900:
2326 // end-sanitize-r5900
2327 *r3900:
2328 // start-sanitize-tx19
2329 *tx19:
2330 // end-sanitize-tx19
2331 {
2332   do_mflo (SD_, RD);
2333 }
2334
2335
2336
2337 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2338 "movn r<RD>, r<RS>, r<RT>"
2339 *mipsIV:
2340 *vr5000:
2341 // start-sanitize-vr4320
2342 *vr4320:
2343 // end-sanitize-vr4320
2344 // start-sanitize-vr5400
2345 *vr5400:
2346 // end-sanitize-vr5400
2347 // start-sanitize-r5900
2348 *r5900:
2349 // end-sanitize-r5900
2350 {
2351   if (GPR[RT] != 0)
2352     GPR[RD] = GPR[RS];
2353 }
2354
2355
2356
2357 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2358 "movz r<RD>, r<RS>, r<RT>"
2359 *mipsIV:
2360 *vr5000:
2361 // start-sanitize-vr4320
2362 *vr4320:
2363 // end-sanitize-vr4320
2364 // start-sanitize-vr5400
2365 *vr5400:
2366 // end-sanitize-vr5400
2367 // start-sanitize-r5900
2368 *r5900:
2369 // end-sanitize-r5900
2370 {
2371   if (GPR[RT] == 0)
2372     GPR[RD] = GPR[RS];
2373 }
2374
2375
2376
2377 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2378 "mthi r<RS>"
2379 *mipsI,mipsII,mipsIII,mipsIV:
2380 *vr5000:
2381 // start-sanitize-vr4320
2382 *vr4320:
2383 // end-sanitize-vr4320
2384 // start-sanitize-vr5400
2385 *vr5400:
2386 // end-sanitize-vr5400
2387 // start-sanitize-r5900
2388 *r5900:
2389 // end-sanitize-r5900
2390 *r3900:
2391 // start-sanitize-tx19
2392 *tx19:
2393 // end-sanitize-tx19
2394 {
2395   check_mt_hilo (SD_, HIHISTORY);
2396   HI = GPR[RS];
2397 }
2398
2399
2400
2401 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2402 "mtlo r<RS>"
2403 *mipsI,mipsII,mipsIII,mipsIV:
2404 *vr5000:
2405 // start-sanitize-vr4320
2406 *vr4320:
2407 // end-sanitize-vr4320
2408 // start-sanitize-vr5400
2409 *vr5400:
2410 // end-sanitize-vr5400
2411 // start-sanitize-r5900
2412 *r5900:
2413 // end-sanitize-r5900
2414 *r3900:
2415 // start-sanitize-tx19
2416 *tx19:
2417 // end-sanitize-tx19
2418 {
2419   check_mt_hilo (SD_, LOHISTORY);
2420   LO = GPR[RS];
2421 }
2422
2423
2424
2425 :function:::void:do_mult:int rs, int rt, int rd
2426 {
2427   signed64 prod;
2428   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2429   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2430   prod = (((signed64)(signed32) GPR[rs])
2431           * ((signed64)(signed32) GPR[rt]));
2432   LO = EXTEND32 (VL4_8 (prod));
2433   HI = EXTEND32 (VH4_8 (prod));
2434   if (rd != 0)
2435     GPR[rd] = LO;
2436   TRACE_ALU_RESULT2 (HI, LO);
2437 }
2438
2439 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2440 "mult r<RS>, r<RT>"
2441 *mipsI,mipsII,mipsIII,mipsIV:
2442 // start-sanitize-vr4320
2443 *vr4320:
2444 // end-sanitize-vr4320
2445 {
2446   do_mult (SD_, RS, RT, 0);
2447 }
2448
2449
2450 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2451 "mult r<RD>, r<RS>, r<RT>"
2452 *vr5000:
2453 // start-sanitize-vr5400
2454 *vr5400:
2455 // end-sanitize-vr5400
2456 // start-sanitize-r5900
2457 *r5900:
2458 // end-sanitize-r5900
2459 *r3900:
2460 // start-sanitize-tx19
2461 *tx19:
2462 // end-sanitize-tx19
2463 {
2464   do_mult (SD_, RS, RT, RD);
2465 }
2466
2467
2468 :function:::void:do_multu:int rs, int rt, int rd
2469 {
2470   unsigned64 prod;
2471   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2472   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2473   prod = (((unsigned64)(unsigned32) GPR[rs])
2474           * ((unsigned64)(unsigned32) GPR[rt]));
2475   LO = EXTEND32 (VL4_8 (prod));
2476   HI = EXTEND32 (VH4_8 (prod));
2477   if (rd != 0)
2478     GPR[rd] = LO;
2479   TRACE_ALU_RESULT2 (HI, LO);
2480 }
2481
2482 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2483 "multu r<RS>, r<RT>"
2484 *mipsI,mipsII,mipsIII,mipsIV:
2485 // start-sanitize-vr4320
2486 *vr4320:
2487 // end-sanitize-vr4320
2488 {
2489   do_multu (SD_, RS, RT, 0);
2490 }
2491
2492 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2493 "multu r<RD>, r<RS>, r<RT>"
2494 *vr5000:
2495 // start-sanitize-vr5400
2496 *vr5400:
2497 // end-sanitize-vr5400
2498 // start-sanitize-r5900
2499 *r5900:
2500 // end-sanitize-r5900
2501 *r3900:
2502 // start-sanitize-tx19
2503 *tx19:
2504 // end-sanitize-tx19
2505 {
2506   do_multu (SD_, RS, RT, 0);
2507 }
2508
2509
2510 :function:::void:do_nor:int rs, int rt, int rd
2511 {
2512   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2513   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2514   TRACE_ALU_RESULT (GPR[rd]);
2515 }
2516
2517 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2518 "nor r<RD>, r<RS>, r<RT>"
2519 *mipsI,mipsII,mipsIII,mipsIV:
2520 *vr5000:
2521 // start-sanitize-vr4320
2522 *vr4320:
2523 // end-sanitize-vr4320
2524 // start-sanitize-vr5400
2525 *vr5400:
2526 // end-sanitize-vr5400
2527 // start-sanitize-r5900
2528 *r5900:
2529 // end-sanitize-r5900
2530 *r3900:
2531 // start-sanitize-tx19
2532 *tx19:
2533 // end-sanitize-tx19
2534 {
2535   do_nor (SD_, RS, RT, RD);
2536 }
2537
2538
2539 :function:::void:do_or:int rs, int rt, int rd
2540 {
2541   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2542   GPR[rd] = (GPR[rs] | GPR[rt]);
2543   TRACE_ALU_RESULT (GPR[rd]);
2544 }
2545
2546 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2547 "or r<RD>, r<RS>, r<RT>"
2548 *mipsI,mipsII,mipsIII,mipsIV:
2549 *vr5000:
2550 // start-sanitize-vr4320
2551 *vr4320:
2552 // end-sanitize-vr4320
2553 // start-sanitize-vr5400
2554 *vr5400:
2555 // end-sanitize-vr5400
2556 // start-sanitize-r5900
2557 *r5900:
2558 // end-sanitize-r5900
2559 *r3900:
2560 // start-sanitize-tx19
2561 *tx19:
2562 // end-sanitize-tx19
2563 {
2564   do_or (SD_, RS, RT, RD);
2565 }
2566
2567
2568
2569 :function:::void:do_ori:int rs, int rt, unsigned immediate
2570 {
2571   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2572   GPR[rt] = (GPR[rs] | immediate);
2573   TRACE_ALU_RESULT (GPR[rt]);
2574 }
2575
2576 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2577 "ori r<RT>, r<RS>, <IMMEDIATE>"
2578 *mipsI,mipsII,mipsIII,mipsIV:
2579 *vr5000:
2580 // start-sanitize-vr4320
2581 *vr4320:
2582 // end-sanitize-vr4320
2583 // start-sanitize-vr5400
2584 *vr5400:
2585 // end-sanitize-vr5400
2586 // start-sanitize-r5900
2587 *r5900:
2588 // end-sanitize-r5900
2589 *r3900:
2590 // start-sanitize-tx19
2591 *tx19:
2592 // end-sanitize-tx19
2593 {
2594   do_ori (SD_, RS, RT, IMMEDIATE);
2595 }
2596
2597
2598 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2599 *mipsIV:
2600 *vr5000:
2601 // start-sanitize-vr4320
2602 *vr4320:
2603 // end-sanitize-vr4320
2604 // start-sanitize-vr5400
2605 *vr5400:
2606 // end-sanitize-vr5400
2607 // start-sanitize-r5900
2608 *r5900:
2609 // end-sanitize-r5900
2610 {
2611   unsigned32 instruction = instruction_0;
2612   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2613   int hint = ((instruction >> 16) & 0x0000001F);
2614   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2615   {
2616     address_word vaddr = ((unsigned64)op1 + offset);
2617     address_word paddr;
2618     int uncached;
2619     {
2620       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2621         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2622     }
2623   }
2624 }
2625
2626 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2627 {
2628   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2629   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2630   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2631   unsigned int byte;
2632   address_word paddr;
2633   int uncached;
2634   unsigned64 memval;
2635   address_word vaddr;
2636
2637   vaddr = base + offset;
2638   if ((vaddr & access) != 0)
2639     SignalExceptionAddressStore ();
2640   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2641   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2642   byte = ((vaddr & mask) ^ bigendiancpu);
2643   memval = (word << (8 * byte));
2644   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2645 }
2646
2647
2648 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2649 "sb r<RT>, <OFFSET>(r<BASE>)"
2650 *mipsI,mipsII,mipsIII,mipsIV:
2651 *vr5000:
2652 // start-sanitize-vr4320
2653 *vr4320:
2654 // end-sanitize-vr4320
2655 // start-sanitize-vr5400
2656 *vr5400:
2657 // end-sanitize-vr5400
2658 // start-sanitize-r5900
2659 *r5900:
2660 // end-sanitize-r5900
2661 *r3900:
2662 // start-sanitize-tx19
2663 *tx19:
2664 // end-sanitize-tx19
2665 {
2666   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2667 }
2668
2669
2670 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2671 "sc r<RT>, <OFFSET>(r<BASE>)"
2672 *mipsII:
2673 *mipsIII:
2674 *mipsIV:
2675 *vr5000:
2676 // start-sanitize-vr4320
2677 *vr4320:
2678 // end-sanitize-vr4320
2679 // start-sanitize-vr5400
2680 *vr5400:
2681 // end-sanitize-vr5400
2682 // start-sanitize-r5900
2683 *r5900:
2684 // end-sanitize-r5900
2685 // start-sanitize-tx19
2686 *tx19:
2687 // end-sanitize-tx19
2688 {
2689   unsigned32 instruction = instruction_0;
2690   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2691   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2692   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2693   {
2694     address_word vaddr = ((unsigned64)op1 + offset);
2695     address_word paddr;
2696     int uncached;
2697     if ((vaddr & 3) != 0)
2698       SignalExceptionAddressStore();
2699     else
2700       {
2701         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2702           {
2703             unsigned64 memval = 0;
2704             unsigned64 memval1 = 0;
2705             unsigned64 mask = 0x7;
2706             unsigned int byte;
2707             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2708             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2709             memval = ((unsigned64) op2 << (8 * byte));
2710             if (LLBIT)
2711               {
2712                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2713               }
2714             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2715           }
2716       }
2717   }
2718 }
2719
2720
2721 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2722 "scd r<RT>, <OFFSET>(r<BASE>)"
2723 *mipsIII:
2724 *mipsIV:
2725 *vr5000:
2726 // start-sanitize-vr4320
2727 *vr4320:
2728 // end-sanitize-vr4320
2729 // start-sanitize-vr5400
2730 *vr5400:
2731 // end-sanitize-vr5400
2732 // start-sanitize-r5900
2733 *r5900:
2734 // end-sanitize-r5900
2735 // start-sanitize-tx19
2736 *tx19:
2737 // end-sanitize-tx19
2738 {
2739   unsigned32 instruction = instruction_0;
2740   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2741   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2742   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2743   {
2744     address_word vaddr = ((unsigned64)op1 + offset);
2745     address_word paddr;
2746     int uncached;
2747     if ((vaddr & 7) != 0)
2748       SignalExceptionAddressStore();
2749     else
2750       {
2751         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2752           {
2753             unsigned64 memval = 0;
2754             unsigned64 memval1 = 0;
2755             memval = op2;
2756             if (LLBIT)
2757               {
2758                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2759               }
2760             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2761           }
2762       }
2763   }
2764 }
2765
2766
2767 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2768 "sd r<RT>, <OFFSET>(r<BASE>)"
2769 *mipsIII:
2770 *mipsIV:
2771 *vr5000:
2772 // start-sanitize-vr4320
2773 *vr4320:
2774 // end-sanitize-vr4320
2775 // start-sanitize-vr5400
2776 *vr5400:
2777 // end-sanitize-vr5400
2778 // start-sanitize-r5900
2779 *r5900:
2780 // end-sanitize-r5900
2781 // start-sanitize-tx19
2782 *tx19:
2783 // end-sanitize-tx19
2784 {
2785   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2786 }
2787
2788
2789 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2790 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2791 *mipsII:
2792 *mipsIII:
2793 *mipsIV:
2794 *vr5000:
2795 // start-sanitize-vr4320
2796 *vr4320:
2797 // end-sanitize-vr4320
2798 // start-sanitize-vr5400
2799 *vr5400:
2800 // end-sanitize-vr5400
2801 // start-sanitize-r5900
2802 *r5900:
2803 // end-sanitize-r5900
2804 // start-sanitize-tx19
2805 *tx19:
2806 // end-sanitize-tx19
2807 {
2808   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2809 }
2810
2811
2812 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2813 "sdl r<RT>, <OFFSET>(r<BASE>)"
2814 *mipsIII:
2815 *mipsIV:
2816 *vr5000:
2817 // start-sanitize-vr4320
2818 *vr4320:
2819 // end-sanitize-vr4320
2820 // start-sanitize-vr5400
2821 *vr5400:
2822 // end-sanitize-vr5400
2823 // start-sanitize-r5900
2824 *r5900:
2825 // end-sanitize-r5900
2826 // start-sanitize-tx19
2827 *tx19:
2828 // end-sanitize-tx19
2829 {
2830   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2831 }
2832
2833
2834 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2835 "sdr r<RT>, <OFFSET>(r<BASE>)"
2836 *mipsIII:
2837 *mipsIV:
2838 *vr5000:
2839 // start-sanitize-vr4320
2840 *vr4320:
2841 // end-sanitize-vr4320
2842 // start-sanitize-vr5400
2843 *vr5400:
2844 // end-sanitize-vr5400
2845 // start-sanitize-r5900
2846 *r5900:
2847 // end-sanitize-r5900
2848 // start-sanitize-tx19
2849 *tx19:
2850 // end-sanitize-tx19
2851 {
2852   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2853 }
2854
2855
2856 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2857 "sh r<RT>, <OFFSET>(r<BASE>)"
2858 *mipsI,mipsII,mipsIII,mipsIV:
2859 *vr5000:
2860 // start-sanitize-vr4320
2861 *vr4320:
2862 // end-sanitize-vr4320
2863 // start-sanitize-vr5400
2864 *vr5400:
2865 // end-sanitize-vr5400
2866 // start-sanitize-r5900
2867 *r5900:
2868 // end-sanitize-r5900
2869 *r3900:
2870 // start-sanitize-tx19
2871 *tx19:
2872 // end-sanitize-tx19
2873 {
2874   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2875 }
2876
2877
2878 :function:::void:do_sll:int rt, int rd, int shift
2879 {
2880   unsigned32 temp = (GPR[rt] << shift);
2881   TRACE_ALU_INPUT2 (GPR[rt], shift);
2882   GPR[rd] = EXTEND32 (temp);
2883   TRACE_ALU_RESULT (GPR[rd]);
2884 }
2885
2886 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2887 "sll r<RD>, r<RT>, <SHIFT>"
2888 *mipsI,mipsII,mipsIII,mipsIV:
2889 *vr5000:
2890 // start-sanitize-vr4320
2891 *vr4320:
2892 // end-sanitize-vr4320
2893 // start-sanitize-vr5400
2894 *vr5400:
2895 // end-sanitize-vr5400
2896 // start-sanitize-r5900
2897 *r5900:
2898 // end-sanitize-r5900
2899 *r3900:
2900 // start-sanitize-tx19
2901 *tx19:
2902 // end-sanitize-tx19
2903 {
2904   do_sll (SD_, RT, RD, SHIFT);
2905 }
2906
2907
2908 :function:::void:do_sllv:int rs, int rt, int rd
2909 {
2910   int s = MASKED (GPR[rs], 4, 0);
2911   unsigned32 temp = (GPR[rt] << s);
2912   TRACE_ALU_INPUT2 (GPR[rt], s);
2913   GPR[rd] = EXTEND32 (temp);
2914   TRACE_ALU_RESULT (GPR[rd]);
2915 }
2916
2917 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2918 "sllv r<RD>, r<RT>, r<RS>"
2919 *mipsI,mipsII,mipsIII,mipsIV:
2920 *vr5000:
2921 // start-sanitize-vr4320
2922 *vr4320:
2923 // end-sanitize-vr4320
2924 // start-sanitize-vr5400
2925 *vr5400:
2926 // end-sanitize-vr5400
2927 // start-sanitize-r5900
2928 *r5900:
2929 // end-sanitize-r5900
2930 *r3900:
2931 // start-sanitize-tx19
2932 *tx19:
2933 // end-sanitize-tx19
2934 {
2935   do_sllv (SD_, RS, RT, RD);
2936 }
2937
2938
2939 :function:::void:do_slt:int rs, int rt, int rd
2940 {
2941   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2942   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2943   TRACE_ALU_RESULT (GPR[rd]);
2944 }
2945
2946 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2947 "slt r<RD>, r<RS>, r<RT>"
2948 *mipsI,mipsII,mipsIII,mipsIV:
2949 *vr5000:
2950 // start-sanitize-vr4320
2951 *vr4320:
2952 // end-sanitize-vr4320
2953 // start-sanitize-vr5400
2954 *vr5400:
2955 // end-sanitize-vr5400
2956 // start-sanitize-r5900
2957 *r5900:
2958 // end-sanitize-r5900
2959 *r3900:
2960 // start-sanitize-tx19
2961 *tx19:
2962 // end-sanitize-tx19
2963 {
2964   do_slt (SD_, RS, RT, RD);
2965 }
2966
2967
2968 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2969 {
2970   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2971   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2972   TRACE_ALU_RESULT (GPR[rt]);
2973 }
2974
2975 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2976 "slti r<RT>, r<RS>, <IMMEDIATE>"
2977 *mipsI,mipsII,mipsIII,mipsIV:
2978 *vr5000:
2979 // start-sanitize-vr4320
2980 *vr4320:
2981 // end-sanitize-vr4320
2982 // start-sanitize-vr5400
2983 *vr5400:
2984 // end-sanitize-vr5400
2985 // start-sanitize-r5900
2986 *r5900:
2987 // end-sanitize-r5900
2988 *r3900:
2989 // start-sanitize-tx19
2990 *tx19:
2991 // end-sanitize-tx19
2992 {
2993   do_slti (SD_, RS, RT, IMMEDIATE);
2994 }
2995
2996
2997 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2998 {
2999   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3000   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3001   TRACE_ALU_RESULT (GPR[rt]);
3002 }
3003
3004 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3005 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3006 *mipsI,mipsII,mipsIII,mipsIV:
3007 *vr5000:
3008 // start-sanitize-vr4320
3009 *vr4320:
3010 // end-sanitize-vr4320
3011 // start-sanitize-vr5400
3012 *vr5400:
3013 // end-sanitize-vr5400
3014 // start-sanitize-r5900
3015 *r5900:
3016 // end-sanitize-r5900
3017 *r3900:
3018 // start-sanitize-tx19
3019 *tx19:
3020 // end-sanitize-tx19
3021 {
3022   do_sltiu (SD_, RS, RT, IMMEDIATE);
3023 }
3024
3025
3026
3027 :function:::void:do_sltu:int rs, int rt, int rd
3028 {
3029   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3030   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3031   TRACE_ALU_RESULT (GPR[rd]);
3032 }
3033
3034 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3035 "sltu r<RD>, r<RS>, r<RT>"
3036 *mipsI,mipsII,mipsIII,mipsIV:
3037 *vr5000:
3038 // start-sanitize-vr4320
3039 *vr4320:
3040 // end-sanitize-vr4320
3041 // start-sanitize-vr5400
3042 *vr5400:
3043 // end-sanitize-vr5400
3044 // start-sanitize-r5900
3045 *r5900:
3046 // end-sanitize-r5900
3047 *r3900:
3048 // start-sanitize-tx19
3049 *tx19:
3050 // end-sanitize-tx19
3051 {
3052   do_sltu (SD_, RS, RT, RD);
3053 }
3054
3055
3056 :function:::void:do_sra:int rt, int rd, int shift
3057 {
3058   signed32 temp = (signed32) GPR[rt] >> shift;
3059   TRACE_ALU_INPUT2 (GPR[rt], shift);
3060   GPR[rd] = EXTEND32 (temp);
3061   TRACE_ALU_RESULT (GPR[rd]);
3062 }
3063
3064 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3065 "sra r<RD>, r<RT>, <SHIFT>"
3066 *mipsI,mipsII,mipsIII,mipsIV:
3067 *vr5000:
3068 // start-sanitize-vr4320
3069 *vr4320:
3070 // end-sanitize-vr4320
3071 // start-sanitize-vr5400
3072 *vr5400:
3073 // end-sanitize-vr5400
3074 // start-sanitize-r5900
3075 *r5900:
3076 // end-sanitize-r5900
3077 *r3900:
3078 // start-sanitize-tx19
3079 *tx19:
3080 // end-sanitize-tx19
3081 {
3082   do_sra (SD_, RT, RD, SHIFT);
3083 }
3084
3085
3086
3087 :function:::void:do_srav:int rs, int rt, int rd
3088 {
3089   int s = MASKED (GPR[rs], 4, 0);
3090   signed32 temp = (signed32) GPR[rt] >> s;
3091   TRACE_ALU_INPUT2 (GPR[rt], s);
3092   GPR[rd] = EXTEND32 (temp);
3093   TRACE_ALU_RESULT (GPR[rd]);
3094 }
3095
3096 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3097 "srav r<RD>, r<RT>, r<RS>"
3098 *mipsI,mipsII,mipsIII,mipsIV:
3099 *vr5000:
3100 // start-sanitize-vr4320
3101 *vr4320:
3102 // end-sanitize-vr4320
3103 // start-sanitize-vr5400
3104 *vr5400:
3105 // end-sanitize-vr5400
3106 // start-sanitize-r5900
3107 *r5900:
3108 // end-sanitize-r5900
3109 *r3900:
3110 // start-sanitize-tx19
3111 *tx19:
3112 // end-sanitize-tx19
3113 {
3114   do_srav (SD_, RS, RT, RD);
3115 }
3116
3117
3118
3119 :function:::void:do_srl:int rt, int rd, int shift
3120 {
3121   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3122   TRACE_ALU_INPUT2 (GPR[rt], shift);
3123   GPR[rd] = EXTEND32 (temp);
3124   TRACE_ALU_RESULT (GPR[rd]);
3125 }
3126
3127 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3128 "srl r<RD>, r<RT>, <SHIFT>"
3129 *mipsI,mipsII,mipsIII,mipsIV:
3130 *vr5000:
3131 // start-sanitize-vr4320
3132 *vr4320:
3133 // end-sanitize-vr4320
3134 // start-sanitize-vr5400
3135 *vr5400:
3136 // end-sanitize-vr5400
3137 // start-sanitize-r5900
3138 *r5900:
3139 // end-sanitize-r5900
3140 *r3900:
3141 // start-sanitize-tx19
3142 *tx19:
3143 // end-sanitize-tx19
3144 {
3145   do_srl (SD_, RT, RD, SHIFT);
3146 }
3147
3148
3149 :function:::void:do_srlv:int rs, int rt, int rd
3150 {
3151   int s = MASKED (GPR[rs], 4, 0);
3152   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3153   TRACE_ALU_INPUT2 (GPR[rt], s);
3154   GPR[rd] = EXTEND32 (temp);
3155   TRACE_ALU_RESULT (GPR[rd]);
3156 }
3157
3158 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3159 "srlv r<RD>, r<RT>, r<RS>"
3160 *mipsI,mipsII,mipsIII,mipsIV:
3161 *vr5000:
3162 // start-sanitize-vr4320
3163 *vr4320:
3164 // end-sanitize-vr4320
3165 // start-sanitize-vr5400
3166 *vr5400:
3167 // end-sanitize-vr5400
3168 // start-sanitize-r5900
3169 *r5900:
3170 // end-sanitize-r5900
3171 *r3900:
3172 // start-sanitize-tx19
3173 *tx19:
3174 // end-sanitize-tx19
3175 {
3176   do_srlv (SD_, RS, RT, RD);
3177 }
3178
3179
3180 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3181 "sub r<RD>, r<RS>, r<RT>"
3182 *mipsI,mipsII,mipsIII,mipsIV:
3183 *vr5000:
3184 // start-sanitize-vr4320
3185 *vr4320:
3186 // end-sanitize-vr4320
3187 // start-sanitize-vr5400
3188 *vr5400:
3189 // end-sanitize-vr5400
3190 // start-sanitize-r5900
3191 *r5900:
3192 // end-sanitize-r5900
3193 *r3900:
3194 // start-sanitize-tx19
3195 *tx19:
3196 // end-sanitize-tx19
3197 {
3198   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3199   {
3200     ALU32_BEGIN (GPR[RS]);
3201     ALU32_SUB (GPR[RT]);
3202     ALU32_END (GPR[RD]);
3203   }
3204   TRACE_ALU_RESULT (GPR[RD]);
3205 }
3206
3207
3208 :function:::void:do_subu:int rs, int rt, int rd
3209 {
3210   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3211   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3212   TRACE_ALU_RESULT (GPR[rd]);
3213 }
3214
3215 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3216 "subu r<RD>, r<RS>, r<RT>"
3217 *mipsI,mipsII,mipsIII,mipsIV:
3218 *vr5000:
3219 // start-sanitize-vr4320
3220 *vr4320:
3221 // end-sanitize-vr4320
3222 // start-sanitize-vr5400
3223 *vr5400:
3224 // end-sanitize-vr5400
3225 // start-sanitize-r5900
3226 *r5900:
3227 // end-sanitize-r5900
3228 *r3900:
3229 // start-sanitize-tx19
3230 *tx19:
3231 // end-sanitize-tx19
3232 {
3233   do_subu (SD_, RS, RT, RD);
3234 }
3235
3236
3237 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3238 "sw r<RT>, <OFFSET>(r<BASE>)"
3239 *mipsI,mipsII,mipsIII,mipsIV:
3240 // start-sanitize-tx19
3241 *tx19:
3242 // end-sanitize-tx19
3243 *r3900:
3244 // start-sanitize-vr4320
3245 *vr4320:
3246 // end-sanitize-vr4320
3247 *vr5000:
3248 // start-sanitize-vr5400
3249 *vr5400:
3250 // end-sanitize-vr5400
3251 // start-sanitize-r5900
3252 *r5900:
3253 // end-sanitize-r5900
3254 {
3255   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3256 }
3257
3258
3259 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3260 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3261 *mipsI,mipsII,mipsIII,mipsIV:
3262 *vr5000:
3263 // start-sanitize-vr4320
3264 *vr4320:
3265 // end-sanitize-vr4320
3266 // start-sanitize-vr5400
3267 *vr5400:
3268 // end-sanitize-vr5400
3269 *r3900:
3270 // start-sanitize-tx19
3271 *tx19:
3272 // end-sanitize-tx19
3273 {
3274   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3275 }
3276
3277
3278
3279 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3280 {
3281   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3282   address_word reverseendian = (ReverseEndian ? -1 : 0);
3283   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3284   unsigned int byte;
3285   unsigned int word;
3286   address_word paddr;
3287   int uncached;
3288   unsigned64 memval;
3289   address_word vaddr;
3290   int nr_lhs_bits;
3291   int nr_rhs_bits;
3292
3293   vaddr = base + offset;
3294   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3295   paddr = (paddr ^ (reverseendian & mask));
3296   if (BigEndianMem == 0)
3297     paddr = paddr & ~access;
3298
3299   /* compute where within the word/mem we are */
3300   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3301   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3302   nr_lhs_bits = 8 * byte + 8;
3303   nr_rhs_bits = 8 * access - 8 * byte;
3304   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3305   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3306            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3307            (long) ((unsigned64) paddr >> 32), (long) paddr,
3308            word, byte, nr_lhs_bits, nr_rhs_bits); */
3309
3310   if (word == 0)
3311     {
3312       memval = (rt >> nr_rhs_bits);
3313     }
3314   else
3315     {
3316       memval = (rt << nr_lhs_bits);
3317     }
3318   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3319            (long) ((unsigned64) rt >> 32), (long) rt,
3320            (long) ((unsigned64) memval >> 32), (long) memval); */
3321   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3322 }
3323
3324
3325 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3326 "swl r<RT>, <OFFSET>(r<BASE>)"
3327 *mipsI,mipsII,mipsIII,mipsIV:
3328 *vr5000:
3329 // start-sanitize-vr4320
3330 *vr4320:
3331 // end-sanitize-vr4320
3332 // start-sanitize-vr5400
3333 *vr5400:
3334 // end-sanitize-vr5400
3335 // start-sanitize-r5900
3336 *r5900:
3337 // end-sanitize-r5900
3338 *r3900:
3339 // start-sanitize-tx19
3340 *tx19:
3341 // end-sanitize-tx19
3342 {
3343   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3344 }
3345
3346
3347 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3348 {
3349   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3350   address_word reverseendian = (ReverseEndian ? -1 : 0);
3351   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3352   unsigned int byte;
3353   address_word paddr;
3354   int uncached;
3355   unsigned64 memval;
3356   address_word vaddr;
3357
3358   vaddr = base + offset;
3359   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3360   paddr = (paddr ^ (reverseendian & mask));
3361   if (BigEndianMem != 0)
3362     paddr &= ~access;
3363   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3364   memval = (rt << (byte * 8));
3365   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3366 }
3367
3368 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3369 "swr r<RT>, <OFFSET>(r<BASE>)"
3370 *mipsI,mipsII,mipsIII,mipsIV:
3371 *vr5000:
3372 // start-sanitize-vr4320
3373 *vr4320:
3374 // end-sanitize-vr4320
3375 // start-sanitize-vr5400
3376 *vr5400:
3377 // end-sanitize-vr5400
3378 // start-sanitize-r5900
3379 *r5900:
3380 // end-sanitize-r5900
3381 *r3900:
3382 // start-sanitize-tx19
3383 *tx19:
3384 // end-sanitize-tx19
3385 {
3386   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3387 }
3388
3389
3390 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3391 "sync":STYPE == 0
3392 "sync <STYPE>"
3393 *mipsII:
3394 *mipsIII:
3395 *mipsIV:
3396 *vr5000:
3397 // start-sanitize-vr4320
3398 *vr4320:
3399 // end-sanitize-vr4320
3400 // start-sanitize-vr5400
3401 *vr5400:
3402 // end-sanitize-vr5400
3403 // start-sanitize-r5900
3404 *r5900:
3405 // end-sanitize-r5900
3406 *r3900:
3407 // start-sanitize-tx19
3408 *tx19:
3409 // end-sanitize-tx19
3410 {
3411   SyncOperation (STYPE);
3412 }
3413
3414
3415 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3416 "syscall <CODE>"
3417 *mipsI,mipsII,mipsIII,mipsIV:
3418 *vr5000:
3419 // start-sanitize-vr4320
3420 *vr4320:
3421 // end-sanitize-vr4320
3422 // start-sanitize-vr5400
3423 *vr5400:
3424 // end-sanitize-vr5400
3425 // start-sanitize-r5900
3426 *r5900:
3427 // end-sanitize-r5900
3428 *r3900:
3429 // start-sanitize-tx19
3430 *tx19:
3431 // end-sanitize-tx19
3432 {
3433   SignalException(SystemCall, instruction_0);
3434 }
3435
3436
3437 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3438 "teq r<RS>, r<RT>"
3439 *mipsII:
3440 *mipsIII:
3441 *mipsIV:
3442 *vr5000:
3443 // start-sanitize-vr4320
3444 *vr4320:
3445 // end-sanitize-vr4320
3446 // start-sanitize-vr5400
3447 *vr5400:
3448 // end-sanitize-vr5400
3449 // start-sanitize-r5900
3450 *r5900:
3451 // end-sanitize-r5900
3452 // start-sanitize-tx19
3453 *tx19:
3454 // end-sanitize-tx19
3455 {
3456   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3457     SignalException(Trap, instruction_0);
3458 }
3459
3460
3461 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3462 "teqi r<RS>, <IMMEDIATE>"
3463 *mipsII:
3464 *mipsIII:
3465 *mipsIV:
3466 *vr5000:
3467 // start-sanitize-vr4320
3468 *vr4320:
3469 // end-sanitize-vr4320
3470 // start-sanitize-vr5400
3471 *vr5400:
3472 // end-sanitize-vr5400
3473 // start-sanitize-r5900
3474 *r5900:
3475 // end-sanitize-r5900
3476 // start-sanitize-tx19
3477 *tx19:
3478 // end-sanitize-tx19
3479 {
3480   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3481     SignalException(Trap, instruction_0);
3482 }
3483
3484
3485 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3486 "tge r<RS>, r<RT>"
3487 *mipsII:
3488 *mipsIII:
3489 *mipsIV:
3490 *vr5000:
3491 // start-sanitize-vr4320
3492 *vr4320:
3493 // end-sanitize-vr4320
3494 // start-sanitize-vr5400
3495 *vr5400:
3496 // end-sanitize-vr5400
3497 // start-sanitize-r5900
3498 *r5900:
3499 // end-sanitize-r5900
3500 // start-sanitize-tx19
3501 *tx19:
3502 // end-sanitize-tx19
3503 {
3504   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3505     SignalException(Trap, instruction_0);
3506 }
3507
3508
3509 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3510 "tgei r<RS>, <IMMEDIATE>"
3511 *mipsII:
3512 *mipsIII:
3513 *mipsIV:
3514 *vr5000:
3515 // start-sanitize-vr4320
3516 *vr4320:
3517 // end-sanitize-vr4320
3518 // start-sanitize-vr5400
3519 *vr5400:
3520 // end-sanitize-vr5400
3521 // start-sanitize-r5900
3522 *r5900:
3523 // end-sanitize-r5900
3524 // start-sanitize-tx19
3525 *tx19:
3526 // end-sanitize-tx19
3527 {
3528   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3529     SignalException(Trap, instruction_0);
3530 }
3531
3532
3533 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3534 "tgeiu r<RS>, <IMMEDIATE>"
3535 *mipsII:
3536 *mipsIII:
3537 *mipsIV:
3538 *vr5000:
3539 // start-sanitize-vr4320
3540 *vr4320:
3541 // end-sanitize-vr4320
3542 // start-sanitize-vr5400
3543 *vr5400:
3544 // end-sanitize-vr5400
3545 // start-sanitize-r5900
3546 *r5900:
3547 // end-sanitize-r5900
3548 // start-sanitize-tx19
3549 *tx19:
3550 // end-sanitize-tx19
3551 {
3552   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3553     SignalException(Trap, instruction_0);
3554 }
3555
3556
3557 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3558 "tgeu r<RS>, r<RT>"
3559 *mipsII:
3560 *mipsIII:
3561 *mipsIV:
3562 *vr5000:
3563 // start-sanitize-vr4320
3564 *vr4320:
3565 // end-sanitize-vr4320
3566 // start-sanitize-vr5400
3567 *vr5400:
3568 // end-sanitize-vr5400
3569 // start-sanitize-r5900
3570 *r5900:
3571 // end-sanitize-r5900
3572 // start-sanitize-tx19
3573 *tx19:
3574 // end-sanitize-tx19
3575 {
3576   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3577     SignalException(Trap, instruction_0);
3578 }
3579
3580
3581 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3582 "tlt r<RS>, r<RT>"
3583 *mipsII:
3584 *mipsIII:
3585 *mipsIV:
3586 *vr5000:
3587 // start-sanitize-vr4320
3588 *vr4320:
3589 // end-sanitize-vr4320
3590 // start-sanitize-vr5400
3591 *vr5400:
3592 // end-sanitize-vr5400
3593 // start-sanitize-r5900
3594 *r5900:
3595 // end-sanitize-r5900
3596 // start-sanitize-tx19
3597 *tx19:
3598 // end-sanitize-tx19
3599 {
3600   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3601     SignalException(Trap, instruction_0);
3602 }
3603
3604
3605 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3606 "tlti r<RS>, <IMMEDIATE>"
3607 *mipsII:
3608 *mipsIII:
3609 *mipsIV:
3610 *vr5000:
3611 // start-sanitize-vr4320
3612 *vr4320:
3613 // end-sanitize-vr4320
3614 // start-sanitize-vr5400
3615 *vr5400:
3616 // end-sanitize-vr5400
3617 // start-sanitize-r5900
3618 *r5900:
3619 // end-sanitize-r5900
3620 // start-sanitize-tx19
3621 *tx19:
3622 // end-sanitize-tx19
3623 {
3624   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3625     SignalException(Trap, instruction_0);
3626 }
3627
3628
3629 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3630 "tltiu r<RS>, <IMMEDIATE>"
3631 *mipsII:
3632 *mipsIII:
3633 *mipsIV:
3634 *vr5000:
3635 // start-sanitize-vr4320
3636 *vr4320:
3637 // end-sanitize-vr4320
3638 // start-sanitize-vr5400
3639 *vr5400:
3640 // end-sanitize-vr5400
3641 // start-sanitize-r5900
3642 *r5900:
3643 // end-sanitize-r5900
3644 // start-sanitize-tx19
3645 *tx19:
3646 // end-sanitize-tx19
3647 {
3648   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3649     SignalException(Trap, instruction_0);
3650 }
3651
3652
3653 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3654 "tltu r<RS>, r<RT>"
3655 *mipsII:
3656 *mipsIII:
3657 *mipsIV:
3658 *vr5000:
3659 // start-sanitize-vr4320
3660 *vr4320:
3661 // end-sanitize-vr4320
3662 // start-sanitize-vr5400
3663 *vr5400:
3664 // end-sanitize-vr5400
3665 // start-sanitize-r5900
3666 *r5900:
3667 // end-sanitize-r5900
3668 // start-sanitize-tx19
3669 *tx19:
3670 // end-sanitize-tx19
3671 {
3672   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3673     SignalException(Trap, instruction_0);
3674 }
3675
3676
3677 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3678 "tne r<RS>, r<RT>"
3679 *mipsII:
3680 *mipsIII:
3681 *mipsIV:
3682 *vr5000:
3683 // start-sanitize-vr4320
3684 *vr4320:
3685 // end-sanitize-vr4320
3686 // start-sanitize-vr5400
3687 *vr5400:
3688 // end-sanitize-vr5400
3689 // start-sanitize-r5900
3690 *r5900:
3691 // end-sanitize-r5900
3692 // start-sanitize-tx19
3693 *tx19:
3694 // end-sanitize-tx19
3695 {
3696   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3697     SignalException(Trap, instruction_0);
3698 }
3699
3700
3701 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3702 "tne r<RS>, <IMMEDIATE>"
3703 *mipsII:
3704 *mipsIII:
3705 *mipsIV:
3706 *vr5000:
3707 // start-sanitize-vr4320
3708 *vr4320:
3709 // end-sanitize-vr4320
3710 // start-sanitize-vr5400
3711 *vr5400:
3712 // end-sanitize-vr5400
3713 // start-sanitize-r5900
3714 *r5900:
3715 // end-sanitize-r5900
3716 // start-sanitize-tx19
3717 *tx19:
3718 // end-sanitize-tx19
3719 {
3720   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3721     SignalException(Trap, instruction_0);
3722 }
3723
3724
3725 :function:::void:do_xor:int rs, int rt, int rd
3726 {
3727   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3728   GPR[rd] = GPR[rs] ^ GPR[rt];
3729   TRACE_ALU_RESULT (GPR[rd]);
3730 }
3731
3732 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3733 "xor r<RD>, r<RS>, r<RT>"
3734 *mipsI,mipsII,mipsIII,mipsIV:
3735 *vr5000:
3736 // start-sanitize-vr4320
3737 *vr4320:
3738 // end-sanitize-vr4320
3739 // start-sanitize-vr5400
3740 *vr5400:
3741 // end-sanitize-vr5400
3742 // start-sanitize-r5900
3743 *r5900:
3744 // end-sanitize-r5900
3745 *r3900:
3746 // start-sanitize-tx19
3747 *tx19:
3748 // end-sanitize-tx19
3749 {
3750   do_xor (SD_, RS, RT, RD);
3751 }
3752
3753
3754 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3755 {
3756   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3757   GPR[rt] = GPR[rs] ^ immediate;
3758   TRACE_ALU_RESULT (GPR[rt]);
3759 }
3760
3761 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3762 "xori r<RT>, r<RS>, <IMMEDIATE>"
3763 *mipsI,mipsII,mipsIII,mipsIV:
3764 *vr5000:
3765 // start-sanitize-vr4320
3766 *vr4320:
3767 // end-sanitize-vr4320
3768 // start-sanitize-vr5400
3769 *vr5400:
3770 // end-sanitize-vr5400
3771 // start-sanitize-r5900
3772 *r5900:
3773 // end-sanitize-r5900
3774 *r3900:
3775 // start-sanitize-tx19
3776 *tx19:
3777 // end-sanitize-tx19
3778 {
3779   do_xori (SD_, RS, RT, IMMEDIATE);
3780 }
3781
3782 \f
3783 //
3784 // MIPS Architecture:
3785 //
3786 //        FPU Instruction Set (COP1 & COP1X)
3787 //
3788
3789
3790 :%s::::FMT:int fmt
3791 {
3792   switch (fmt)
3793     {
3794     case fmt_single: return "s";
3795     case fmt_double: return "d";
3796     case fmt_word: return "w";
3797     case fmt_long: return "l";
3798     default: return "?";
3799     }
3800 }
3801
3802 :%s::::X:int x
3803 {
3804   switch (x)
3805     {
3806     case 0: return "f";
3807     case 1: return "t";
3808     default: return "?";
3809     }
3810 }
3811
3812 :%s::::TF:int tf
3813 {
3814   if (tf)
3815     return "t";
3816   else
3817     return "f";
3818 }
3819
3820 :%s::::ND:int nd
3821 {
3822   if (nd)
3823     return "l";
3824   else
3825     return "";
3826 }
3827
3828 :%s::::COND:int cond
3829 {
3830   switch (cond)
3831     {
3832     case 00: return "f";
3833     case 01: return "un";
3834     case 02: return "eq";
3835     case 03: return "ueq";
3836     case 04: return "olt";
3837     case 05: return "ult";
3838     case 06: return "ole";
3839     case 07: return "ule";
3840     case 010: return "sf";
3841     case 011: return "ngle";
3842     case 012: return "seq";
3843     case 013: return "ngl";
3844     case 014: return "lt";
3845     case 015: return "nge";
3846     case 016: return "le";
3847     case 017: return "ngt";
3848     default: return "?";
3849     }
3850 }
3851
3852
3853 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3854 "abs.%s<FMT> f<FD>, f<FS>"
3855 *mipsI,mipsII,mipsIII,mipsIV:
3856 *vr5000:
3857 // start-sanitize-vr4320
3858 *vr4320:
3859 // end-sanitize-vr4320
3860 // start-sanitize-vr5400
3861 *vr5400:
3862 // end-sanitize-vr5400
3863 *r3900:
3864 // start-sanitize-tx19
3865 *tx19:
3866 // end-sanitize-tx19
3867 {
3868   unsigned32 instruction = instruction_0;
3869   int destreg = ((instruction >> 6) & 0x0000001F);
3870   int fs = ((instruction >> 11) & 0x0000001F);
3871   int format = ((instruction >> 21) & 0x00000007);
3872   {
3873     if ((format != fmt_single) && (format != fmt_double))
3874       SignalException(ReservedInstruction,instruction);
3875     else
3876       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3877   }
3878 }
3879
3880
3881
3882 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3883 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3884 *mipsI,mipsII,mipsIII,mipsIV:
3885 *vr5000:
3886 // start-sanitize-vr4320
3887 *vr4320:
3888 // end-sanitize-vr4320
3889 // start-sanitize-vr5400
3890 *vr5400:
3891 // end-sanitize-vr5400
3892 *r3900:
3893 // start-sanitize-tx19
3894 *tx19:
3895 // end-sanitize-tx19
3896 {
3897   unsigned32 instruction = instruction_0;
3898   int destreg = ((instruction >> 6) & 0x0000001F);
3899   int fs = ((instruction >> 11) & 0x0000001F);
3900   int ft = ((instruction >> 16) & 0x0000001F);
3901   int format = ((instruction >> 21) & 0x00000007);
3902   {
3903     if ((format != fmt_single) && (format != fmt_double))
3904       SignalException(ReservedInstruction, instruction);
3905     else
3906       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3907   }
3908 }
3909
3910
3911
3912 // BC1F
3913 // BC1FL
3914 // BC1T
3915 // BC1TL
3916
3917 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3918 "bc1%s<TF>%s<ND> <OFFSET>"
3919 *mipsI,mipsII,mipsIII:
3920 // start-sanitize-r5900
3921 *r5900:
3922 // end-sanitize-r5900
3923 {
3924   TRACE_BRANCH_INPUT (PREVCOC1());
3925   if (PREVCOC1() == TF)
3926     {
3927       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3928       TRACE_BRANCH_RESULT (dest);
3929       DELAY_SLOT (dest);
3930     }
3931   else if (ND)
3932     {
3933       TRACE_BRANCH_RESULT (0);
3934       NULLIFY_NEXT_INSTRUCTION ();
3935     }
3936   else
3937     {
3938       TRACE_BRANCH_RESULT (NIA);
3939     }
3940 }
3941
3942 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3943 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3944 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3945 *mipsIV:
3946 *vr5000:
3947 // start-sanitize-vr4320
3948 *vr4320:
3949 // end-sanitize-vr4320
3950 // start-sanitize-vr5400
3951 *vr5400:
3952 // end-sanitize-vr5400
3953 *r3900:
3954 // start-sanitize-tx19
3955 *tx19:
3956 // end-sanitize-tx19
3957 {
3958   if (GETFCC(CC) == TF)
3959     {
3960       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3961     }
3962   else if (ND)
3963     {
3964       NULLIFY_NEXT_INSTRUCTION ();
3965     }
3966 }
3967
3968
3969
3970 // C.EQ.S
3971 // C.EQ.D
3972 // ...
3973
3974 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3975 {
3976   if ((fmt != fmt_single) && (fmt != fmt_double))
3977     SignalException (ReservedInstruction, insn);
3978   else
3979     {
3980       int less;
3981       int equal;
3982       int unordered;
3983       int condition;
3984       unsigned64 ofs = ValueFPR (fs, fmt);
3985       unsigned64 oft = ValueFPR (ft, fmt);
3986       if (NaN (ofs, fmt) || NaN (oft, fmt))
3987         {
3988           if (FCSR & FP_ENABLE (IO))
3989             {
3990               FCSR |= FP_CAUSE (IO);
3991               SignalExceptionFPE ();
3992             }
3993           less = 0;
3994           equal = 0;
3995           unordered = 1;
3996         }
3997       else
3998         {
3999           less = Less (ofs, oft, fmt);
4000           equal = Equal (ofs, oft, fmt);
4001           unordered = 0;
4002         }
4003       condition = (((cond & (1 << 2)) && less)
4004                    || ((cond & (1 << 1)) && equal)
4005                    || ((cond & (1 << 0)) && unordered));
4006       SETFCC (cc, condition);
4007     }
4008 }
4009
4010 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4011 *mipsI,mipsII,mipsIII:
4012 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
4013 {
4014   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4015 }
4016
4017 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4018 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4019 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4020 *mipsIV:
4021 *vr5000:
4022 // start-sanitize-vr4320
4023 *vr4320:
4024 // end-sanitize-vr4320
4025 // start-sanitize-vr5400
4026 *vr5400:
4027 // end-sanitize-vr5400
4028 *r3900:
4029 // start-sanitize-tx19
4030 *tx19:
4031 // end-sanitize-tx19
4032 {
4033   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4034 }
4035
4036
4037 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4038 "ceil.l.%s<FMT> f<FD>, f<FS>"
4039 *mipsIII:
4040 *mipsIV:
4041 *vr5000:
4042 // start-sanitize-vr4320
4043 *vr4320:
4044 // end-sanitize-vr4320
4045 // start-sanitize-vr5400
4046 *vr5400:
4047 // end-sanitize-vr5400
4048 // start-sanitize-r5900
4049 *r5900:
4050 // end-sanitize-r5900
4051 *r3900:
4052 // start-sanitize-tx19
4053 *tx19:
4054 // end-sanitize-tx19
4055 {
4056   unsigned32 instruction = instruction_0;
4057   int destreg = ((instruction >> 6) & 0x0000001F);
4058   int fs = ((instruction >> 11) & 0x0000001F);
4059   int format = ((instruction >> 21) & 0x00000007);
4060   {
4061     if ((format != fmt_single) && (format != fmt_double))
4062       SignalException(ReservedInstruction,instruction);
4063     else
4064       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4065   }
4066 }
4067
4068
4069 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4070 *mipsII:
4071 *mipsIII:
4072 *mipsIV:
4073 *vr5000:
4074 // start-sanitize-vr4320
4075 *vr4320:
4076 // end-sanitize-vr4320
4077 // start-sanitize-vr5400
4078 *vr5400:
4079 // end-sanitize-vr5400
4080 // start-sanitize-r5900
4081 *r5900:
4082 // end-sanitize-r5900
4083 *r3900:
4084 // start-sanitize-tx19
4085 *tx19:
4086 // end-sanitize-tx19
4087 {
4088   unsigned32 instruction = instruction_0;
4089   int destreg = ((instruction >> 6) & 0x0000001F);
4090   int fs = ((instruction >> 11) & 0x0000001F);
4091   int format = ((instruction >> 21) & 0x00000007);
4092   {
4093   if ((format != fmt_single) && (format != fmt_double))
4094    SignalException(ReservedInstruction,instruction);
4095   else
4096    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4097   }
4098 }
4099
4100
4101 // CFC1
4102 // CTC1
4103 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4104 "c%s<X>c1 r<RT>, f<FS>"
4105 *mipsI:
4106 *mipsII:
4107 *mipsIII:
4108 {
4109   if (X)
4110     {
4111       if (FS == 0)
4112         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4113       else if (FS == 31)
4114         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4115       /* else NOP */
4116       PENDING_FILL(COCIDX,0); /* special case */
4117     }
4118   else
4119     { /* control from */
4120       if (FS == 0)
4121         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4122       else if (FS == 31)
4123         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4124       /* else NOP */
4125     }
4126 }
4127 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4128 "c%s<X>c1 r<RT>, f<FS>"
4129 *mipsIV:
4130 *vr5000:
4131 // start-sanitize-vr4320
4132 *vr4320:
4133 // end-sanitize-vr4320
4134 // start-sanitize-vr5400
4135 *vr5400:
4136 // end-sanitize-vr5400
4137 *r3900:
4138 // start-sanitize-tx19
4139 *tx19:
4140 // end-sanitize-tx19
4141 {
4142   if (X)
4143     {
4144       /* control to */
4145       TRACE_ALU_INPUT1 (GPR[RT]);
4146       if (FS == 0)
4147         {
4148           FCR0 = VL4_8(GPR[RT]);
4149           TRACE_ALU_RESULT (FCR0);
4150         }
4151       else if (FS == 31)
4152         {
4153           FCR31 = VL4_8(GPR[RT]);
4154           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4155           TRACE_ALU_RESULT (FCR31);
4156         }
4157       else
4158         {
4159           TRACE_ALU_RESULT0 ();
4160         }
4161       /* else NOP */
4162     }
4163   else
4164     { /* control from */
4165       if (FS == 0)
4166         {
4167           TRACE_ALU_INPUT1 (FCR0);
4168           GPR[RT] = SIGNEXTEND (FCR0, 32);
4169         }
4170       else if (FS == 31)
4171         {
4172           TRACE_ALU_INPUT1 (FCR31);
4173           GPR[RT] = SIGNEXTEND (FCR31, 32);
4174         }
4175       TRACE_ALU_RESULT (GPR[RT]);
4176       /* else NOP */
4177     }
4178 }
4179
4180
4181 //
4182 // FIXME: Does not correctly differentiate between mips*
4183 //
4184 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4185 "cvt.d.%s<FMT> f<FD>, f<FS>"
4186 *mipsI,mipsII,mipsIII,mipsIV:
4187 *vr5000:
4188 // start-sanitize-vr4320
4189 *vr4320:
4190 // end-sanitize-vr4320
4191 // start-sanitize-vr5400
4192 *vr5400:
4193 // end-sanitize-vr5400
4194 *r3900:
4195 // start-sanitize-tx19
4196 *tx19:
4197 // end-sanitize-tx19
4198 {
4199   unsigned32 instruction = instruction_0;
4200   int destreg = ((instruction >> 6) & 0x0000001F);
4201   int fs = ((instruction >> 11) & 0x0000001F);
4202   int format = ((instruction >> 21) & 0x00000007);
4203   {
4204     if ((format == fmt_double) | 0)
4205       SignalException(ReservedInstruction,instruction);
4206     else
4207       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4208   }
4209 }
4210
4211
4212 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4213 "cvt.l.%s<FMT> f<FD>, f<FS>"
4214 *mipsIII:
4215 *mipsIV:
4216 *vr5000:
4217 // start-sanitize-vr4320
4218 *vr4320:
4219 // end-sanitize-vr4320
4220 // start-sanitize-vr5400
4221 *vr5400:
4222 // end-sanitize-vr5400
4223 *r3900:
4224 // start-sanitize-tx19
4225 *tx19:
4226 // end-sanitize-tx19
4227 {
4228   unsigned32 instruction = instruction_0;
4229   int destreg = ((instruction >> 6) & 0x0000001F);
4230   int fs = ((instruction >> 11) & 0x0000001F);
4231   int format = ((instruction >> 21) & 0x00000007);
4232   {
4233     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4234       SignalException(ReservedInstruction,instruction);
4235     else
4236       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4237   }
4238 }
4239
4240
4241 //
4242 // FIXME: Does not correctly differentiate between mips*
4243 //
4244 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4245 "cvt.s.%s<FMT> f<FD>, f<FS>"
4246 *mipsI,mipsII,mipsIII,mipsIV:
4247 *vr5000:
4248 // start-sanitize-vr4320
4249 *vr4320:
4250 // end-sanitize-vr4320
4251 // start-sanitize-vr5400
4252 *vr5400:
4253 // end-sanitize-vr5400
4254 *r3900:
4255 // start-sanitize-tx19
4256 *tx19:
4257 // end-sanitize-tx19
4258 {
4259   unsigned32 instruction = instruction_0;
4260   int destreg = ((instruction >> 6) & 0x0000001F);
4261   int fs = ((instruction >> 11) & 0x0000001F);
4262   int format = ((instruction >> 21) & 0x00000007);
4263   {
4264     if ((format == fmt_single) | 0)
4265       SignalException(ReservedInstruction,instruction);
4266     else
4267       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4268   }
4269 }
4270
4271
4272 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4273 "cvt.w.%s<FMT> f<FD>, f<FS>"
4274 *mipsI,mipsII,mipsIII,mipsIV:
4275 *vr5000:
4276 // start-sanitize-vr4320
4277 *vr4320:
4278 // end-sanitize-vr4320
4279 // start-sanitize-vr5400
4280 *vr5400:
4281 // end-sanitize-vr5400
4282 *r3900:
4283 // start-sanitize-tx19
4284 *tx19:
4285 // end-sanitize-tx19
4286 {
4287   unsigned32 instruction = instruction_0;
4288   int destreg = ((instruction >> 6) & 0x0000001F);
4289   int fs = ((instruction >> 11) & 0x0000001F);
4290   int format = ((instruction >> 21) & 0x00000007);
4291   {
4292     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4293       SignalException(ReservedInstruction,instruction);
4294     else
4295       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4296   }
4297 }
4298
4299
4300 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4301 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4302 *mipsI,mipsII,mipsIII,mipsIV:
4303 *vr5000:
4304 // start-sanitize-vr4320
4305 *vr4320:
4306 // end-sanitize-vr4320
4307 // start-sanitize-vr5400
4308 *vr5400:
4309 // end-sanitize-vr5400
4310 *r3900:
4311 // start-sanitize-tx19
4312 *tx19:
4313 // end-sanitize-tx19
4314 {
4315   unsigned32 instruction = instruction_0;
4316   int destreg = ((instruction >> 6) & 0x0000001F);
4317   int fs = ((instruction >> 11) & 0x0000001F);
4318   int ft = ((instruction >> 16) & 0x0000001F);
4319   int format = ((instruction >> 21) & 0x00000007);
4320   {
4321     if ((format != fmt_single) && (format != fmt_double))
4322       SignalException(ReservedInstruction,instruction);
4323     else
4324       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4325   }
4326 }
4327
4328
4329 // DMFC1
4330 // DMTC1
4331 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4332 "dm%s<X>c1 r<RT>, f<FS>"
4333 *mipsIII:
4334 {
4335   if (X)
4336     {
4337       if (SizeFGR() == 64)
4338         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4339       else if ((FS & 0x1) == 0)
4340         {
4341           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4342           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4343         }
4344     }
4345   else
4346     {
4347       if (SizeFGR() == 64)
4348         PENDING_FILL(RT,FGR[FS]);
4349       else if ((FS & 0x1) == 0)
4350         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4351       else
4352         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4353     }
4354 }
4355 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4356 "dm%s<X>c1 r<RT>, f<FS>"
4357 *mipsIV:
4358 *vr5000:
4359 // start-sanitize-vr4320
4360 *vr4320:
4361 // end-sanitize-vr4320
4362 // start-sanitize-vr5400
4363 *vr5400:
4364 // end-sanitize-vr5400
4365 // start-sanitize-r5900
4366 *r5900:
4367 // end-sanitize-r5900
4368 *r3900:
4369 // start-sanitize-tx19
4370 *tx19:
4371 // end-sanitize-tx19
4372 {
4373   if (X)
4374     {
4375       if (SizeFGR() == 64)
4376         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4377       else if ((FS & 0x1) == 0)
4378         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4379     }
4380   else
4381     {
4382       if (SizeFGR() == 64)
4383         GPR[RT] = FGR[FS];
4384       else if ((FS & 0x1) == 0)
4385         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4386       else
4387         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4388     }
4389 }
4390
4391
4392 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4393 "floor.l.%s<FMT> f<FD>, f<FS>"
4394 *mipsIII:
4395 *mipsIV:
4396 *vr5000:
4397 // start-sanitize-vr4320
4398 *vr4320:
4399 // end-sanitize-vr4320
4400 // start-sanitize-vr5400
4401 *vr5400:
4402 // end-sanitize-vr5400
4403 // start-sanitize-r5900
4404 *r5900:
4405 // end-sanitize-r5900
4406 *r3900:
4407 // start-sanitize-tx19
4408 *tx19:
4409 // end-sanitize-tx19
4410 {
4411   unsigned32 instruction = instruction_0;
4412   int destreg = ((instruction >> 6) & 0x0000001F);
4413   int fs = ((instruction >> 11) & 0x0000001F);
4414   int format = ((instruction >> 21) & 0x00000007);
4415   {
4416     if ((format != fmt_single) && (format != fmt_double))
4417       SignalException(ReservedInstruction,instruction);
4418     else
4419       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4420   }
4421 }
4422
4423
4424 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4425 "floor.w.%s<FMT> f<FD>, f<FS>"
4426 *mipsII:
4427 *mipsIII:
4428 *mipsIV:
4429 *vr5000:
4430 // start-sanitize-vr4320
4431 *vr4320:
4432 // end-sanitize-vr4320
4433 // start-sanitize-vr5400
4434 *vr5400:
4435 // end-sanitize-vr5400
4436 // start-sanitize-r5900
4437 *r5900:
4438 // end-sanitize-r5900
4439 *r3900:
4440 // start-sanitize-tx19
4441 *tx19:
4442 // end-sanitize-tx19
4443 {
4444   unsigned32 instruction = instruction_0;
4445   int destreg = ((instruction >> 6) & 0x0000001F);
4446   int fs = ((instruction >> 11) & 0x0000001F);
4447   int format = ((instruction >> 21) & 0x00000007);
4448   {
4449     if ((format != fmt_single) && (format != fmt_double))
4450       SignalException(ReservedInstruction,instruction);
4451     else
4452       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4453   }
4454 }
4455
4456
4457 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4458 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4459 *mipsII:
4460 *mipsIII:
4461 *mipsIV:
4462 *vr5000:
4463 // start-sanitize-vr4320
4464 *vr4320:
4465 // end-sanitize-vr4320
4466 // start-sanitize-vr5400
4467 *vr5400:
4468 // end-sanitize-vr5400
4469 *r3900:
4470 // start-sanitize-tx19
4471 *tx19:
4472 // end-sanitize-tx19
4473 {
4474   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4475 }
4476
4477
4478 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4479 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4480 *mipsIV:
4481 *vr5000:
4482 // start-sanitize-vr4320
4483 *vr4320:
4484 // end-sanitize-vr4320
4485 // start-sanitize-vr5400
4486 *vr5400:
4487 // end-sanitize-vr5400
4488 {
4489   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4490 }
4491
4492
4493
4494 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4495 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4496 *mipsI,mipsII,mipsIII,mipsIV:
4497 *vr5000:
4498 // start-sanitize-vr4320
4499 *vr4320:
4500 // end-sanitize-vr4320
4501 // start-sanitize-vr5400
4502 *vr5400:
4503 // end-sanitize-vr5400
4504 // start-sanitize-r5900
4505 *r5900:
4506 // end-sanitize-r5900
4507 *r3900:
4508 // start-sanitize-tx19
4509 *tx19:
4510 // end-sanitize-tx19
4511 {
4512   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4513 }
4514
4515
4516 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4517 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4518 *mipsIV:
4519 *vr5000:
4520 // start-sanitize-vr4320
4521 *vr4320:
4522 // end-sanitize-vr4320
4523 // start-sanitize-vr5400
4524 *vr5400:
4525 // end-sanitize-vr5400
4526 {
4527   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4528 }
4529
4530
4531
4532 //
4533 // FIXME: Not correct for mips*
4534 //
4535 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4536 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4537 *mipsIV:
4538 *vr5000:
4539 // start-sanitize-vr4320
4540 *vr4320:
4541 // end-sanitize-vr4320
4542 // start-sanitize-vr5400
4543 *vr5400:
4544 // end-sanitize-vr5400
4545 {
4546   unsigned32 instruction = instruction_0;
4547   int destreg = ((instruction >> 6) & 0x0000001F);
4548   int fs = ((instruction >> 11) & 0x0000001F);
4549   int ft = ((instruction >> 16) & 0x0000001F);
4550   int fr = ((instruction >> 21) & 0x0000001F);
4551   {
4552     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4553   }
4554 }
4555
4556
4557 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4558 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4559 *mipsIV:
4560 *vr5000:
4561 // start-sanitize-vr4320
4562 *vr4320:
4563 // end-sanitize-vr4320
4564 // start-sanitize-vr5400
4565 *vr5400:
4566 // end-sanitize-vr5400
4567 {
4568   unsigned32 instruction = instruction_0;
4569   int destreg = ((instruction >> 6) & 0x0000001F);
4570   int fs = ((instruction >> 11) & 0x0000001F);
4571   int ft = ((instruction >> 16) & 0x0000001F);
4572   int fr = ((instruction >> 21) & 0x0000001F);
4573   {
4574     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4575   }
4576 }
4577
4578
4579 // MFC1
4580 // MTC1
4581 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4582 "m%s<X>c1 r<RT>, f<FS>"
4583 *mipsI:
4584 *mipsII:
4585 *mipsIII:
4586 {
4587   if (X)
4588     { /*MTC1*/
4589       if (SizeFGR() == 64)
4590         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4591       else
4592         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4593     }
4594   else /*MFC1*/
4595     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4596 }
4597 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4598 "m%s<X>c1 r<RT>, f<FS>"
4599 *mipsIV:
4600 *vr5000:
4601 // start-sanitize-vr4320
4602 *vr4320:
4603 // end-sanitize-vr4320
4604 // start-sanitize-vr5400
4605 *vr5400:
4606 // end-sanitize-vr5400
4607 *r3900:
4608 // start-sanitize-tx19
4609 *tx19:
4610 // end-sanitize-tx19
4611 {
4612   if (X)
4613     /*MTC1*/
4614     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4615   else /*MFC1*/
4616     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4617 }
4618
4619
4620 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4621 "mov.%s<FMT> f<FD>, f<FS>"
4622 *mipsI,mipsII,mipsIII,mipsIV:
4623 *vr5000:
4624 // start-sanitize-vr4320
4625 *vr4320:
4626 // end-sanitize-vr4320
4627 // start-sanitize-vr5400
4628 *vr5400:
4629 // end-sanitize-vr5400
4630 *r3900:
4631 // start-sanitize-tx19
4632 *tx19:
4633 // end-sanitize-tx19
4634 {
4635   unsigned32 instruction = instruction_0;
4636   int destreg = ((instruction >> 6) & 0x0000001F);
4637   int fs = ((instruction >> 11) & 0x0000001F);
4638   int format = ((instruction >> 21) & 0x00000007);
4639   {
4640     StoreFPR(destreg,format,ValueFPR(fs,format));
4641   }
4642 }
4643
4644
4645 // MOVF
4646 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4647 "mov%s<TF> r<RD>, r<RS>, <CC>"
4648 *mipsIV:
4649 *vr5000:
4650 // start-sanitize-vr4320
4651 *vr4320:
4652 // end-sanitize-vr4320
4653 // start-sanitize-vr5400
4654 *vr5400:
4655 // end-sanitize-vr5400
4656 // start-sanitize-r5900
4657 *r5900:
4658 // end-sanitize-r5900
4659 {
4660   if (GETFCC(CC) == TF)
4661     GPR[RD] = GPR[RS];
4662 }
4663
4664
4665 // MOVF.fmt
4666 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4667 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4668 *mipsIV:
4669 *vr5000:
4670 // start-sanitize-vr4320
4671 *vr4320:
4672 // end-sanitize-vr4320
4673 // start-sanitize-vr5400
4674 *vr5400:
4675 // end-sanitize-vr5400
4676 // start-sanitize-r5900
4677 *r5900:
4678 // end-sanitize-r5900
4679 {
4680   unsigned32 instruction = instruction_0;
4681   int format = ((instruction >> 21) & 0x00000007);
4682   {
4683    if (GETFCC(CC) == TF)
4684      StoreFPR (FD, format, ValueFPR (FS, format));
4685    else
4686      StoreFPR (FD, format, ValueFPR (FD, format));
4687   }
4688 }
4689
4690
4691 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4692 *mipsIV:
4693 *vr5000:
4694 // start-sanitize-vr4320
4695 *vr4320:
4696 // end-sanitize-vr4320
4697 // start-sanitize-vr5400
4698 *vr5400:
4699 // end-sanitize-vr5400
4700 // start-sanitize-r5900
4701 *r5900:
4702 // end-sanitize-r5900
4703 {
4704   unsigned32 instruction = instruction_0;
4705   int destreg = ((instruction >> 6) & 0x0000001F);
4706   int fs = ((instruction >> 11) & 0x0000001F);
4707   int format = ((instruction >> 21) & 0x00000007);
4708   {
4709     StoreFPR(destreg,format,ValueFPR(fs,format));
4710   }
4711 }
4712
4713
4714 // MOVT see MOVtf
4715
4716
4717 // MOVT.fmt see MOVtf.fmt
4718
4719
4720
4721 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4722 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4723 *mipsIV:
4724 *vr5000:
4725 // start-sanitize-vr4320
4726 *vr4320:
4727 // end-sanitize-vr4320
4728 // start-sanitize-vr5400
4729 *vr5400:
4730 // end-sanitize-vr5400
4731 // start-sanitize-r5900
4732 *r5900:
4733 // end-sanitize-r5900
4734 {
4735   unsigned32 instruction = instruction_0;
4736   int destreg = ((instruction >> 6) & 0x0000001F);
4737   int fs = ((instruction >> 11) & 0x0000001F);
4738   int format = ((instruction >> 21) & 0x00000007);
4739   {
4740    StoreFPR(destreg,format,ValueFPR(fs,format));
4741   }
4742 }
4743
4744
4745 // MSUB.fmt
4746 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4747 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4748 *mipsIV:
4749 *vr5000:
4750 // start-sanitize-vr4320
4751 *vr4320:
4752 // end-sanitize-vr4320
4753 // start-sanitize-vr5400
4754 *vr5400:
4755 // end-sanitize-vr5400
4756 // start-sanitize-r5900
4757 *r5900:
4758 // end-sanitize-r5900
4759 {
4760   unsigned32 instruction = instruction_0;
4761   int destreg = ((instruction >> 6) & 0x0000001F);
4762   int fs = ((instruction >> 11) & 0x0000001F);
4763   int ft = ((instruction >> 16) & 0x0000001F);
4764   int fr = ((instruction >> 21) & 0x0000001F);
4765   {
4766     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4767   }
4768 }
4769
4770
4771 // MSUB.fmt
4772 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4773 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4774 *mipsIV:
4775 *vr5000:
4776 // start-sanitize-vr4320
4777 *vr4320:
4778 // end-sanitize-vr4320
4779 // start-sanitize-vr5400
4780 *vr5400:
4781 // end-sanitize-vr5400
4782 // start-sanitize-r5900
4783 *r5900:
4784 // end-sanitize-r5900
4785 {
4786   unsigned32 instruction = instruction_0;
4787   int destreg = ((instruction >> 6) & 0x0000001F);
4788   int fs = ((instruction >> 11) & 0x0000001F);
4789   int ft = ((instruction >> 16) & 0x0000001F);
4790   int fr = ((instruction >> 21) & 0x0000001F);
4791   {
4792    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4793   }
4794 }
4795
4796
4797 // MTC1 see MxC1
4798
4799
4800 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4801 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4802 *mipsI,mipsII,mipsIII,mipsIV:
4803 *vr5000:
4804 // start-sanitize-vr4320
4805 *vr4320:
4806 // end-sanitize-vr4320
4807 // start-sanitize-vr5400
4808 *vr5400:
4809 // end-sanitize-vr5400
4810 *r3900:
4811 // start-sanitize-tx19
4812 *tx19:
4813 // end-sanitize-tx19
4814 {
4815   unsigned32 instruction = instruction_0;
4816   int destreg = ((instruction >> 6) & 0x0000001F);
4817   int fs = ((instruction >> 11) & 0x0000001F);
4818   int ft = ((instruction >> 16) & 0x0000001F);
4819   int format = ((instruction >> 21) & 0x00000007);
4820   {
4821     if ((format != fmt_single) && (format != fmt_double))
4822       SignalException(ReservedInstruction,instruction);
4823     else
4824       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4825   }
4826 }
4827
4828
4829 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4830 "neg.%s<FMT> f<FD>, f<FS>"
4831 *mipsI,mipsII,mipsIII,mipsIV:
4832 *vr5000:
4833 // start-sanitize-vr4320
4834 *vr4320:
4835 // end-sanitize-vr4320
4836 // start-sanitize-vr5400
4837 *vr5400:
4838 // end-sanitize-vr5400
4839 *r3900:
4840 // start-sanitize-tx19
4841 *tx19:
4842 // end-sanitize-tx19
4843 {
4844   unsigned32 instruction = instruction_0;
4845   int destreg = ((instruction >> 6) & 0x0000001F);
4846   int fs = ((instruction >> 11) & 0x0000001F);
4847   int format = ((instruction >> 21) & 0x00000007);
4848   {
4849     if ((format != fmt_single) && (format != fmt_double))
4850       SignalException(ReservedInstruction,instruction);
4851     else
4852       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4853   }
4854 }
4855
4856
4857 // NMADD.fmt
4858 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4859 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4860 *mipsIV:
4861 *vr5000:
4862 // start-sanitize-vr4320
4863 *vr4320:
4864 // end-sanitize-vr4320
4865 // start-sanitize-vr5400
4866 *vr5400:
4867 // end-sanitize-vr5400
4868 {
4869   unsigned32 instruction = instruction_0;
4870   int destreg = ((instruction >> 6) & 0x0000001F);
4871   int fs = ((instruction >> 11) & 0x0000001F);
4872   int ft = ((instruction >> 16) & 0x0000001F);
4873   int fr = ((instruction >> 21) & 0x0000001F);
4874   {
4875    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4876   }
4877 }
4878
4879
4880 // NMADD.fmt
4881 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4882 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4883 *mipsIV:
4884 *vr5000:
4885 // start-sanitize-vr4320
4886 *vr4320:
4887 // end-sanitize-vr4320
4888 // start-sanitize-vr5400
4889 *vr5400:
4890 // end-sanitize-vr5400
4891 {
4892   unsigned32 instruction = instruction_0;
4893   int destreg = ((instruction >> 6) & 0x0000001F);
4894   int fs = ((instruction >> 11) & 0x0000001F);
4895   int ft = ((instruction >> 16) & 0x0000001F);
4896   int fr = ((instruction >> 21) & 0x0000001F);
4897   {
4898    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4899   }
4900 }
4901
4902
4903 // NMSUB.fmt
4904 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4905 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4906 *mipsIV:
4907 *vr5000:
4908 // start-sanitize-vr4320
4909 *vr4320:
4910 // end-sanitize-vr4320
4911 // start-sanitize-vr5400
4912 *vr5400:
4913 // end-sanitize-vr5400
4914 {
4915   unsigned32 instruction = instruction_0;
4916   int destreg = ((instruction >> 6) & 0x0000001F);
4917   int fs = ((instruction >> 11) & 0x0000001F);
4918   int ft = ((instruction >> 16) & 0x0000001F);
4919   int fr = ((instruction >> 21) & 0x0000001F);
4920   {
4921    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4922   }
4923 }
4924
4925
4926 // NMSUB.fmt
4927 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4928 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4929 *mipsIV:
4930 *vr5000:
4931 // start-sanitize-vr4320
4932 *vr4320:
4933 // end-sanitize-vr4320
4934 // start-sanitize-vr5400
4935 *vr5400:
4936 // end-sanitize-vr5400
4937 {
4938   unsigned32 instruction = instruction_0;
4939   int destreg = ((instruction >> 6) & 0x0000001F);
4940   int fs = ((instruction >> 11) & 0x0000001F);
4941   int ft = ((instruction >> 16) & 0x0000001F);
4942   int fr = ((instruction >> 21) & 0x0000001F);
4943   {
4944     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4945   }
4946 }
4947
4948
4949 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4950 "prefx <HINT>, r<INDEX>(r<BASE>)"
4951 *mipsIV:
4952 *vr5000:
4953 // start-sanitize-vr4320
4954 *vr4320:
4955 // end-sanitize-vr4320
4956 // start-sanitize-vr5400
4957 *vr5400:
4958 // end-sanitize-vr5400
4959 {
4960   unsigned32 instruction = instruction_0;
4961   int fs = ((instruction >> 11) & 0x0000001F);
4962   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4963   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4964   {
4965     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4966     address_word paddr;
4967     int uncached;
4968     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4969       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4970   }
4971 }
4972
4973 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4974 *mipsIV:
4975 "recip.%s<FMT> f<FD>, f<FS>"
4976 *vr5000:
4977 // start-sanitize-vr4320
4978 *vr4320:
4979 // end-sanitize-vr4320
4980 // start-sanitize-vr5400
4981 *vr5400:
4982 // end-sanitize-vr5400
4983 {
4984   unsigned32 instruction = instruction_0;
4985   int destreg = ((instruction >> 6) & 0x0000001F);
4986   int fs = ((instruction >> 11) & 0x0000001F);
4987   int format = ((instruction >> 21) & 0x00000007);
4988   {
4989   if ((format != fmt_single) && (format != fmt_double))
4990    SignalException(ReservedInstruction,instruction);
4991   else
4992    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4993   }
4994 }
4995
4996
4997 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
4998 "round.l.%s<FMT> f<FD>, f<FS>"
4999 *mipsIII:
5000 *mipsIV:
5001 *vr5000:
5002 // start-sanitize-vr4320
5003 *vr4320:
5004 // end-sanitize-vr4320
5005 // start-sanitize-vr5400
5006 *vr5400:
5007 // end-sanitize-vr5400
5008 // start-sanitize-r5900
5009 *r5900:
5010 // end-sanitize-r5900
5011 *r3900:
5012 // start-sanitize-tx19
5013 *tx19:
5014 // end-sanitize-tx19
5015 {
5016   unsigned32 instruction = instruction_0;
5017   int destreg = ((instruction >> 6) & 0x0000001F);
5018   int fs = ((instruction >> 11) & 0x0000001F);
5019   int format = ((instruction >> 21) & 0x00000007);
5020   {
5021     if ((format != fmt_single) && (format != fmt_double))
5022       SignalException(ReservedInstruction,instruction);
5023     else
5024       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5025   }
5026 }
5027
5028
5029 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5030 "round.w.%s<FMT> f<FD>, f<FS>"
5031 *mipsII:
5032 *mipsIII:
5033 *mipsIV:
5034 *vr5000:
5035 // start-sanitize-vr4320
5036 *vr4320:
5037 // end-sanitize-vr4320
5038 // start-sanitize-vr5400
5039 *vr5400:
5040 // end-sanitize-vr5400
5041 // start-sanitize-r5900
5042 *r5900:
5043 // end-sanitize-r5900
5044 *r3900:
5045 // start-sanitize-tx19
5046 *tx19:
5047 // end-sanitize-tx19
5048 {
5049   unsigned32 instruction = instruction_0;
5050   int destreg = ((instruction >> 6) & 0x0000001F);
5051   int fs = ((instruction >> 11) & 0x0000001F);
5052   int format = ((instruction >> 21) & 0x00000007);
5053   {
5054   if ((format != fmt_single) && (format != fmt_double))
5055    SignalException(ReservedInstruction,instruction);
5056   else
5057    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5058   }
5059 }
5060
5061
5062 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5063 *mipsIV:
5064 "rsqrt.%s<FMT> f<FD>, f<FS>"
5065 *vr5000:
5066 // start-sanitize-vr4320
5067 *vr4320:
5068 // end-sanitize-vr4320
5069 // start-sanitize-vr5400
5070 *vr5400:
5071 // end-sanitize-vr5400
5072 {
5073   unsigned32 instruction = instruction_0;
5074   int destreg = ((instruction >> 6) & 0x0000001F);
5075   int fs = ((instruction >> 11) & 0x0000001F);
5076   int format = ((instruction >> 21) & 0x00000007);
5077   {
5078   if ((format != fmt_single) && (format != fmt_double))
5079    SignalException(ReservedInstruction,instruction);
5080   else
5081    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5082   }
5083 }
5084
5085
5086 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5087 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5088 *mipsII:
5089 *mipsIII:
5090 *mipsIV:
5091 *vr5000:
5092 // start-sanitize-vr4320
5093 *vr4320:
5094 // end-sanitize-vr4320
5095 // start-sanitize-vr5400
5096 *vr5400:
5097 // end-sanitize-vr5400
5098 *r3900:
5099 // start-sanitize-tx19
5100 *tx19:
5101 // end-sanitize-tx19
5102 {
5103   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5104 }
5105
5106
5107 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5108 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5109 *mipsIV:
5110 *vr5000:
5111 // start-sanitize-vr4320
5112 *vr4320:
5113 // end-sanitize-vr4320
5114 // start-sanitize-vr5400
5115 *vr5400:
5116 // end-sanitize-vr5400
5117 {
5118   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5119 }
5120
5121
5122 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5123 "sqrt.%s<FMT> f<FD>, f<FS>"
5124 *mipsII:
5125 *mipsIII:
5126 *mipsIV:
5127 *vr5000:
5128 // start-sanitize-vr4320
5129 *vr4320:
5130 // end-sanitize-vr4320
5131 // start-sanitize-vr5400
5132 *vr5400:
5133 // end-sanitize-vr5400
5134 *r3900:
5135 // start-sanitize-tx19
5136 *tx19:
5137 // end-sanitize-tx19
5138 {
5139   unsigned32 instruction = instruction_0;
5140   int destreg = ((instruction >> 6) & 0x0000001F);
5141   int fs = ((instruction >> 11) & 0x0000001F);
5142   int format = ((instruction >> 21) & 0x00000007);
5143   {
5144     if ((format != fmt_single) && (format != fmt_double))
5145       SignalException(ReservedInstruction,instruction);
5146     else
5147       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5148   }
5149 }
5150
5151
5152 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5153 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5154 *mipsI,mipsII,mipsIII,mipsIV:
5155 *vr5000:
5156 // start-sanitize-vr4320
5157 *vr4320:
5158 // end-sanitize-vr4320
5159 // start-sanitize-vr5400
5160 *vr5400:
5161 // end-sanitize-vr5400
5162 *r3900:
5163 // start-sanitize-tx19
5164 *tx19:
5165 // end-sanitize-tx19
5166 {
5167   unsigned32 instruction = instruction_0;
5168   int destreg = ((instruction >> 6) & 0x0000001F);
5169   int fs = ((instruction >> 11) & 0x0000001F);
5170   int ft = ((instruction >> 16) & 0x0000001F);
5171   int format = ((instruction >> 21) & 0x00000007);
5172   {
5173     if ((format != fmt_single) && (format != fmt_double))
5174       SignalException(ReservedInstruction,instruction);
5175     else
5176       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5177   }
5178 }
5179
5180
5181
5182 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5183 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5184 *mipsI,mipsII,mipsIII,mipsIV:
5185 *vr5000:
5186 // start-sanitize-vr4320
5187 *vr4320:
5188 // end-sanitize-vr4320
5189 // start-sanitize-vr5400
5190 *vr5400:
5191 // end-sanitize-vr5400
5192 // start-sanitize-r5900
5193 *r5900:
5194 // end-sanitize-r5900
5195 *r3900:
5196 // start-sanitize-tx19
5197 *tx19:
5198 // end-sanitize-tx19
5199 {
5200   unsigned32 instruction = instruction_0;
5201   signed_word offset = EXTEND16 (OFFSET);
5202   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5203   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5204   {
5205     address_word vaddr = ((uword64)op1 + offset);
5206     address_word paddr;
5207     int uncached;
5208     if ((vaddr & 3) != 0)
5209       SignalExceptionAddressStore();
5210     else
5211       {
5212         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5213           {
5214             uword64 memval = 0;
5215             uword64 memval1 = 0;
5216             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5217             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5218             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5219             unsigned int byte;
5220             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5221             byte = ((vaddr & mask) ^ bigendiancpu);
5222             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5223             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5224           }
5225       }
5226   }
5227 }
5228
5229
5230 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5231 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5232 *mipsIV:
5233 *vr5000:
5234 // start-sanitize-vr4320
5235 *vr4320:
5236 // end-sanitize-vr4320
5237 // start-sanitize-vr5400
5238 *vr5400:
5239 // end-sanitize-vr5400
5240 {
5241   unsigned32 instruction = instruction_0;
5242   int fs = ((instruction >> 11) & 0x0000001F);
5243   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5244   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5245   {
5246    address_word vaddr = ((unsigned64)op1 + op2);
5247    address_word paddr;
5248    int uncached;
5249    if ((vaddr & 3) != 0)
5250     SignalExceptionAddressStore();
5251    else
5252    {
5253     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5254     {
5255      unsigned64 memval = 0;
5256      unsigned64 memval1 = 0;
5257      unsigned64 mask = 0x7;
5258      unsigned int byte;
5259      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5260      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5261      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5262       {
5263        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5264       }
5265     }
5266    }
5267   }
5268 }
5269
5270
5271 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5272 "trunc.l.%s<FMT> f<FD>, f<FS>"
5273 *mipsIII:
5274 *mipsIV:
5275 *vr5000:
5276 // start-sanitize-vr4320
5277 *vr4320:
5278 // end-sanitize-vr4320
5279 // start-sanitize-vr5400
5280 *vr5400:
5281 // end-sanitize-vr5400
5282 // start-sanitize-r5900
5283 *r5900:
5284 // end-sanitize-r5900
5285 *r3900:
5286 // start-sanitize-tx19
5287 *tx19:
5288 // end-sanitize-tx19
5289 {
5290   unsigned32 instruction = instruction_0;
5291   int destreg = ((instruction >> 6) & 0x0000001F);
5292   int fs = ((instruction >> 11) & 0x0000001F);
5293   int format = ((instruction >> 21) & 0x00000007);
5294   {
5295   if ((format != fmt_single) && (format != fmt_double))
5296    SignalException(ReservedInstruction,instruction);
5297   else
5298    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5299   }
5300 }
5301
5302
5303 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5304 "trunc.w.%s<FMT> f<FD>, f<FS>"
5305 *mipsII:
5306 *mipsIII:
5307 *mipsIV:
5308 *vr5000:
5309 // start-sanitize-vr4320
5310 *vr4320:
5311 // end-sanitize-vr4320
5312 // start-sanitize-vr5400
5313 *vr5400:
5314 // end-sanitize-vr5400
5315 // start-sanitize-r5900
5316 *r5900:
5317 // end-sanitize-r5900
5318 *r3900:
5319 // start-sanitize-tx19
5320 *tx19:
5321 // end-sanitize-tx19
5322 {
5323   unsigned32 instruction = instruction_0;
5324   int destreg = ((instruction >> 6) & 0x0000001F);
5325   int fs = ((instruction >> 11) & 0x0000001F);
5326   int format = ((instruction >> 21) & 0x00000007);
5327   {
5328   if ((format != fmt_single) && (format != fmt_double))
5329    SignalException(ReservedInstruction,instruction);
5330   else
5331    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5332   }
5333 }
5334
5335 \f
5336 //
5337 // MIPS Architecture:
5338 //
5339 //        System Control Instruction Set (COP0)
5340 //
5341
5342
5343 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5344 "bc0f <OFFSET>"
5345 *mipsI,mipsII,mipsIII,mipsIV:
5346 *vr5000:
5347 // start-sanitize-vr4320
5348 *vr4320:
5349 // end-sanitize-vr4320
5350 // start-sanitize-vr5400
5351 *vr5400:
5352 // end-sanitize-vr5400
5353 // start-sanitize-r5900
5354 *r5900:
5355 // end-sanitize-r5900
5356
5357
5358 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5359 "bc0fl <OFFSET>"
5360 *mipsI,mipsII,mipsIII,mipsIV:
5361 *vr5000:
5362 // start-sanitize-vr4320
5363 *vr4320:
5364 // end-sanitize-vr4320
5365 // start-sanitize-vr5400
5366 *vr5400:
5367 // end-sanitize-vr5400
5368 // start-sanitize-r5900
5369 *r5900:
5370 // end-sanitize-r5900
5371
5372
5373 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5374 "bc0t <OFFSET>"
5375 *mipsI,mipsII,mipsIII,mipsIV:
5376 // start-sanitize-r5900
5377 *r5900:
5378 // end-sanitize-r5900
5379
5380
5381
5382 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5383 "bc0tl <OFFSET>"
5384 *mipsI,mipsII,mipsIII,mipsIV:
5385 *vr5000:
5386 // start-sanitize-vr4320
5387 *vr4320:
5388 // end-sanitize-vr4320
5389 // start-sanitize-vr5400
5390 *vr5400:
5391 // end-sanitize-vr5400
5392 // start-sanitize-r5900
5393 *r5900:
5394 // end-sanitize-r5900
5395
5396
5397 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5398 *mipsIII:
5399 *mipsIV:
5400 *vr5000:
5401 // start-sanitize-vr4320
5402 *vr4320:
5403 // end-sanitize-vr4320
5404 // start-sanitize-vr5400
5405 *vr5400:
5406 // end-sanitize-vr5400
5407 // start-sanitize-r5900
5408 *r5900:
5409 // end-sanitize-r5900
5410 *r3900:
5411 // start-sanitize-tx19
5412 *tx19:
5413 // end-sanitize-tx19
5414 {
5415   unsigned32 instruction = instruction_0;
5416   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5417   int hint = ((instruction >> 16) & 0x0000001F);
5418   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5419   {
5420     address_word vaddr = (op1 + offset);
5421     address_word paddr;
5422     int uncached;
5423     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5424       CacheOp(hint,vaddr,paddr,instruction);
5425   }
5426 }
5427
5428
5429 010000,10000,000000000000000,111001:COP0:32::DI
5430 "di"
5431 *mipsI,mipsII,mipsIII,mipsIV:
5432 *vr5000:
5433 // start-sanitize-vr4320
5434 *vr4320:
5435 // end-sanitize-vr4320
5436 // start-sanitize-vr5400
5437 *vr5400:
5438 // end-sanitize-vr5400
5439 // start-sanitize-r5900
5440 *r5900:
5441 // end-sanitize-r5900
5442
5443
5444 010000,10000,000000000000000,111000:COP0:32::EI
5445 "ei"
5446 *mipsI,mipsII,mipsIII,mipsIV:
5447 *vr5000:
5448 // start-sanitize-vr4320
5449 *vr4320:
5450 // end-sanitize-vr4320
5451 // start-sanitize-vr5400
5452 *vr5400:
5453 // end-sanitize-vr5400
5454 // start-sanitize-r5900
5455 *r5900:
5456 // end-sanitize-r5900
5457
5458
5459 010000,10000,000000000000000,011000:COP0:32::ERET
5460 "eret"
5461 *mipsIII:
5462 *mipsIV:
5463 *vr5000:
5464 // start-sanitize-vr4320
5465 *vr4320:
5466 // end-sanitize-vr4320
5467 // start-sanitize-vr5400
5468 *vr5400:
5469 // end-sanitize-vr5400
5470 // start-sanitize-r5900
5471 *r5900:
5472 // end-sanitize-r5900
5473 {
5474   if (SR & status_ERL)
5475     {
5476       /* Oops, not yet available */
5477       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5478       NIA = EPC;
5479       SR &= ~status_ERL;
5480     }
5481   else
5482     {
5483       NIA = EPC;
5484       SR &= ~status_EXL;
5485     }
5486 }
5487
5488
5489 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5490 "mfc0 r<RT>, r<RD> # <REGX>"
5491 *mipsI,mipsII,mipsIII,mipsIV:
5492 *r3900:
5493 *vr5000:
5494 // start-sanitize-vr4320
5495 *vr4320:
5496 // end-sanitize-vr4320
5497 // start-sanitize-vr5400
5498 *vr5400:
5499 // end-sanitize-vr5400
5500 // start-sanitize-r5900
5501 *r5900:
5502 // end-sanitize-r5900
5503 {
5504   TRACE_ALU_INPUT0 ();
5505   DecodeCoproc (instruction_0);
5506   TRACE_ALU_RESULT (GPR[RT]);
5507 }
5508
5509 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5510 "mtc0 r<RT>, r<RD> # <REGX>"
5511 *mipsI,mipsII,mipsIII,mipsIV:
5512 // start-sanitize-tx19
5513 *tx19:
5514 // end-sanitize-tx19
5515 *r3900:
5516 // start-sanitize-vr4320
5517 *vr4320:
5518 // end-sanitize-vr4320
5519 *vr5000:
5520 // start-sanitize-vr5400
5521 *vr5400:
5522 // end-sanitize-vr5400
5523 // start-sanitize-r5900
5524 *r5900:
5525 // end-sanitize-r5900
5526 {
5527   DecodeCoproc (instruction_0);
5528 }
5529
5530
5531 010000,10000,000000000000000,010000:COP0:32::RFE
5532 "rfe"
5533 *mipsI,mipsII,mipsIII,mipsIV:
5534 // start-sanitize-tx19
5535 *tx19:
5536 // end-sanitize-tx19
5537 *r3900:
5538 // start-sanitize-vr4320
5539 *vr4320:
5540 // end-sanitize-vr4320
5541 *vr5000:
5542 // start-sanitize-vr5400
5543 *vr5400:
5544 // end-sanitize-vr5400
5545 // start-sanitize-r5900
5546 *r5900:
5547 // end-sanitize-r5900
5548 {
5549   DecodeCoproc (instruction_0);
5550 }
5551
5552
5553 010000,10000,000000000000000,001000:COP0:32::TLBP
5554 "tlbp"
5555 *mipsI,mipsII,mipsIII,mipsIV:
5556 *vr5000:
5557 // start-sanitize-vr4320
5558 *vr4320:
5559 // end-sanitize-vr4320
5560 // start-sanitize-vr5400
5561 *vr5400:
5562 // end-sanitize-vr5400
5563 // start-sanitize-r5900
5564 *r5900:
5565 // end-sanitize-r5900
5566
5567
5568 010000,10000,000000000000000,000001:COP0:32::TLBR
5569 "tlbr"
5570 *mipsI,mipsII,mipsIII,mipsIV:
5571 *vr5000:
5572 // start-sanitize-vr4320
5573 *vr4320:
5574 // end-sanitize-vr4320
5575 // start-sanitize-vr5400
5576 *vr5400:
5577 // end-sanitize-vr5400
5578 // start-sanitize-r5900
5579 *r5900:
5580 // end-sanitize-r5900
5581
5582
5583 010000,10000,000000000000000,000010:COP0:32::TLBWI
5584 "tlbwi"
5585 *mipsI,mipsII,mipsIII,mipsIV:
5586 *vr5000:
5587 // start-sanitize-vr4320
5588 *vr4320:
5589 // end-sanitize-vr4320
5590 // start-sanitize-vr5400
5591 *vr5400:
5592 // end-sanitize-vr5400
5593 // start-sanitize-r5900
5594 *r5900:
5595 // end-sanitize-r5900
5596
5597
5598 010000,10000,000000000000000,000110:COP0:32::TLBWR
5599 "tlbwr"
5600 *mipsI,mipsII,mipsIII,mipsIV:
5601 *vr5000:
5602 // start-sanitize-vr4320
5603 *vr4320:
5604 // end-sanitize-vr4320
5605 // start-sanitize-vr5400
5606 *vr5400:
5607 // end-sanitize-vr5400
5608 // start-sanitize-r5900
5609 *r5900:
5610 // end-sanitize-r5900
5611
5612 \f
5613 :include:::m16.igen
5614 // start-sanitize-vr4320
5615 :include::vr4320:vr4320.igen
5616 // end-sanitize-vr4320
5617 // start-sanitize-vr5400
5618 :include::vr5400:vr5400.igen
5619 :include:64,f::mdmx.igen
5620 // end-sanitize-vr5400
5621 // start-sanitize-r5900
5622 :include::r5900:r5900.igen
5623 // end-sanitize-r5900
5624 :include:::tx.igen
5625 \f
5626 // start-sanitize-cygnus-never
5627
5628 // // FIXME FIXME FIXME What is this instruction?
5629 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5630 // *mipsI:
5631 // *mipsII:
5632 // *mipsIII:
5633 // *mipsIV:
5634 // // start-sanitize-r5900
5635 // *r5900:
5636 // // end-sanitize-r5900
5637 // *r3900:
5638 // // start-sanitize-tx19
5639 // *tx19:
5640 // // end-sanitize-tx19
5641 // {
5642 //   unsigned32 instruction = instruction_0;
5643 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5644 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5645 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5646 //   {
5647 //     if (CoProcPresent(3))
5648 //       SignalException(CoProcessorUnusable);
5649 //     else
5650 //       SignalException(ReservedInstruction,instruction);
5651 //   }
5652 // }
5653
5654 // end-sanitize-cygnus-never
5655 // start-sanitize-cygnus-never
5656
5657 // // FIXME FIXME FIXME What is this?
5658 // 11100,******,00001:RR:16::SDBBP
5659 // *mips16:
5660 // {
5661 //   unsigned32 instruction = instruction_0;
5662 //   if (have_extendval)
5663 //     SignalException (ReservedInstruction, instruction);
5664 //   {
5665 //     SignalException(DebugBreakPoint,instruction);
5666 //   }
5667 // }
5668
5669 // end-sanitize-cygnus-never
5670 // start-sanitize-cygnus-never
5671
5672 // // FIXME FIXME FIXME What is this?
5673 // 000000,********************,001110:SPECIAL:32::SDBBP
5674 // *r3900:
5675 // {
5676 //   unsigned32 instruction = instruction_0;
5677 //   {
5678 //     SignalException(DebugBreakPoint,instruction);
5679 //   }
5680 // }
5681
5682 // end-sanitize-cygnus-never
5683 // start-sanitize-cygnus-never
5684
5685 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5686 // // isn't yet reconized by this simulator.
5687 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5688 // *vr4100:
5689 // {
5690 //   unsigned32 instruction = instruction_0;
5691 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5692 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5693 //   {
5694 //     CHECKHILO("Multiply-Add");
5695 //     {
5696 //       unsigned64 temp = (op1 * op2);
5697 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5698 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5699 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5700 //     }
5701 //   }
5702 // }
5703
5704 // end-sanitize-cygnus-never
5705 // start-sanitize-cygnus-never
5706
5707 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5708 // // isn't yet reconized by this simulator.
5709 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5710 // *vr4100:
5711 // {
5712 //   unsigned32 instruction = instruction_0;
5713 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5714 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5715 //   {
5716 //     CHECKHILO("Multiply-Add");
5717 //     {
5718 //       unsigned64 temp = (op1 * op2);
5719 //       LO = LO + temp;
5720 //     }
5721 //   }
5722 // }
5723
5724 // end-sanitize-cygnus-never