4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator are defined below.
35 // When placing models in the instruction descriptions, please place
36 // them one per line, in the order given here.
40 // Instructions and related functions for these models are included in
42 :model:::mipsI:mips3000:
43 :model:::mipsII:mips6000:
44 :model:::mipsIII:mips4000:
45 :model:::mipsIV:mips8000:
46 :model:::mipsV:mipsisaV:
47 :model:::mips32:mipsisa32:
48 :model:::mips64:mipsisa64:
52 // Standard MIPS ISA instructions used for these models are listed here,
53 // as are functions needed by those standard instructions. Instructions
54 // which are model-dependent and which are not in the standard MIPS ISAs
55 // (or which pre-date or use different encodings than the standard
56 // instructions) are (for the most part) in separate .igen files.
57 :model:::vr4100:mips4100: // vr.igen
58 :model:::vr5000:mips5000:
59 :model:::r3900:mips3900: // tx.igen
61 // MIPS Application Specific Extensions (ASEs)
63 // Instructions for the ASEs are in separate .igen files.
64 // ASEs add instructions on to a base ISA.
65 :model:::mips16:mips16: // m16.igen (and m16.dc)
66 :model:::mdmx:mdmx: // mdmx.igen
70 // Instructions specific to these extensions are in separate .igen files.
71 // Extensions add instructions on to a base ISA.
72 :model:::sb1:sb1: // sb1.igen
75 // Pseudo instructions known by IGEN
78 SignalException (ReservedInstruction, 0);
82 // Pseudo instructions known by interp.c
83 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
84 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
87 SignalException (ReservedInstruction, instruction_0);
94 // Simulate a 32 bit delayslot instruction
97 :function:::address_word:delayslot32:address_word target
99 instruction_word delay_insn;
100 sim_events_slip (SD, 1);
102 CIA = CIA + 4; /* NOTE not mips16 */
103 STATE |= simDELAYSLOT;
104 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
105 ENGINE_ISSUE_PREFIX_HOOK();
106 idecode_issue (CPU_, delay_insn, (CIA));
107 STATE &= ~simDELAYSLOT;
111 :function:::address_word:nullify_next_insn32:
113 sim_events_slip (SD, 1);
114 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
121 // Calculate an effective address given a base and an offset.
124 :function:::address_word:loadstore_ea:address_word base, address_word offset
135 return base + offset;
138 :function:::address_word:loadstore_ea:address_word base, address_word offset
141 #if 0 /* XXX FIXME: enable this only after some additional testing. */
142 /* If in user mode and UX is not set, use 32-bit compatibility effective
143 address computations as defined in the MIPS64 Architecture for
144 Programmers Volume III, Revision 0.95, section 4.9. */
145 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
146 == (ksu_user << status_KSU_shift))
147 return (address_word)((signed32)base + (signed32)offset);
149 return base + offset;
155 // Check that a 32-bit register value is properly sign-extended.
156 // (See NotWordValue in ISA spec.)
159 :function:::int:not_word_value:unsigned_word value
169 /* For historical simulator compatibility (until documentation is
170 found that makes these operations unpredictable on some of these
171 architectures), this check never returns true. */
175 :function:::int:not_word_value:unsigned_word value
178 /* On MIPS32, since registers are 32-bits, there's no check to be done. */
182 :function:::int:not_word_value:unsigned_word value
185 return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
191 // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
192 // theoretically portable code which invokes non-portable behaviour from
193 // running with no indication of the portability issue.
194 // (See definition of UNPREDICTABLE in ISA spec.)
197 :function:::void:unpredictable:
209 :function:::void:unpredictable:
213 unpredictable_action (CPU, CIA);
219 // Check that an access to a HI/LO register meets timing requirements
221 // The following requirements exist:
223 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
224 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
225 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
226 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
229 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
231 if (history->mf.timestamp + 3 > time)
233 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
234 itable[MY_INDEX].name,
236 (long) history->mf.cia);
242 :function:::int:check_mt_hilo:hilo_history *history
251 signed64 time = sim_events_time (SD);
252 int ok = check_mf_cycles (SD_, history, time, "MT");
253 history->mt.timestamp = time;
254 history->mt.cia = CIA;
258 :function:::int:check_mt_hilo:hilo_history *history
263 signed64 time = sim_events_time (SD);
264 history->mt.timestamp = time;
265 history->mt.cia = CIA;
270 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
282 signed64 time = sim_events_time (SD);
285 && peer->mt.timestamp > history->op.timestamp
286 && history->mt.timestamp < history->op.timestamp
287 && ! (history->mf.timestamp > history->op.timestamp
288 && history->mf.timestamp < peer->mt.timestamp)
289 && ! (peer->mf.timestamp > history->op.timestamp
290 && peer->mf.timestamp < peer->mt.timestamp))
292 /* The peer has been written to since the last OP yet we have
294 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
295 itable[MY_INDEX].name,
297 (long) history->op.cia,
298 (long) peer->mt.cia);
301 history->mf.timestamp = time;
302 history->mf.cia = CIA;
308 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
317 signed64 time = sim_events_time (SD);
318 int ok = (check_mf_cycles (SD_, hi, time, "OP")
319 && check_mf_cycles (SD_, lo, time, "OP"));
320 hi->op.timestamp = time;
321 lo->op.timestamp = time;
327 // The r3900 mult and multu insns _can_ be exectuted immediatly after
329 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
334 /* FIXME: could record the fact that a stall occured if we want */
335 signed64 time = sim_events_time (SD);
336 hi->op.timestamp = time;
337 lo->op.timestamp = time;
344 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
356 signed64 time = sim_events_time (SD);
357 int ok = (check_mf_cycles (SD_, hi, time, "OP")
358 && check_mf_cycles (SD_, lo, time, "OP"));
359 hi->op.timestamp = time;
360 lo->op.timestamp = time;
369 // Check that the 64-bit instruction can currently be used, and signal
370 // a ReservedInstruction exception if not.
373 :function:::void:check_u64:instruction_word insn
380 // The check should be similar to mips64 for any with PX/UX bit equivalents.
383 :function:::void:check_u64:instruction_word insn
386 #if 0 /* XXX FIXME: enable this only after some additional testing. */
387 if (UserMode && (SR & (status_UX|status_PX)) == 0)
388 SignalException (ReservedInstruction, insn);
395 // MIPS Architecture:
397 // CPU Instruction Set (mipsI - mipsV, mips32, mips64)
402 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
403 "add r<RD>, r<RS>, r<RT>"
415 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
417 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
419 ALU32_BEGIN (GPR[RS]);
421 ALU32_END (GPR[RD]); /* This checks for overflow. */
423 TRACE_ALU_RESULT (GPR[RD]);
428 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
429 "addi r<RT>, r<RS>, <IMMEDIATE>"
441 if (NotWordValue (GPR[RS]))
443 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
445 ALU32_BEGIN (GPR[RS]);
446 ALU32_ADD (EXTEND16 (IMMEDIATE));
447 ALU32_END (GPR[RT]); /* This checks for overflow. */
449 TRACE_ALU_RESULT (GPR[RT]);
454 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
456 if (NotWordValue (GPR[rs]))
458 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
459 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
460 TRACE_ALU_RESULT (GPR[rt]);
463 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
464 "addiu r<RT>, r<RS>, <IMMEDIATE>"
476 do_addiu (SD_, RS, RT, IMMEDIATE);
481 :function:::void:do_addu:int rs, int rt, int rd
483 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
485 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
486 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
487 TRACE_ALU_RESULT (GPR[rd]);
490 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
491 "addu r<RD>, r<RS>, r<RT>"
503 do_addu (SD_, RS, RT, RD);
508 :function:::void:do_and:int rs, int rt, int rd
510 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
511 GPR[rd] = GPR[rs] & GPR[rt];
512 TRACE_ALU_RESULT (GPR[rd]);
515 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
516 "and r<RD>, r<RS>, r<RT>"
528 do_and (SD_, RS, RT, RD);
533 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
534 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
546 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
547 GPR[RT] = GPR[RS] & IMMEDIATE;
548 TRACE_ALU_RESULT (GPR[RT]);
553 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
554 "beq r<RS>, r<RT>, <OFFSET>"
566 address_word offset = EXTEND16 (OFFSET) << 2;
568 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
570 mark_branch_bug (NIA+offset);
571 DELAY_SLOT (NIA + offset);
577 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
578 "beql r<RS>, r<RT>, <OFFSET>"
589 address_word offset = EXTEND16 (OFFSET) << 2;
591 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
593 mark_branch_bug (NIA+offset);
594 DELAY_SLOT (NIA + offset);
597 NULLIFY_NEXT_INSTRUCTION ();
602 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
603 "bgez r<RS>, <OFFSET>"
615 address_word offset = EXTEND16 (OFFSET) << 2;
617 if ((signed_word) GPR[RS] >= 0)
619 mark_branch_bug (NIA+offset);
620 DELAY_SLOT (NIA + offset);
626 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
627 "bgezal r<RS>, <OFFSET>"
639 address_word offset = EXTEND16 (OFFSET) << 2;
644 if ((signed_word) GPR[RS] >= 0)
646 mark_branch_bug (NIA+offset);
647 DELAY_SLOT (NIA + offset);
653 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
654 "bgezall r<RS>, <OFFSET>"
665 address_word offset = EXTEND16 (OFFSET) << 2;
670 /* NOTE: The branch occurs AFTER the next instruction has been
672 if ((signed_word) GPR[RS] >= 0)
674 mark_branch_bug (NIA+offset);
675 DELAY_SLOT (NIA + offset);
678 NULLIFY_NEXT_INSTRUCTION ();
683 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
684 "bgezl r<RS>, <OFFSET>"
695 address_word offset = EXTEND16 (OFFSET) << 2;
697 if ((signed_word) GPR[RS] >= 0)
699 mark_branch_bug (NIA+offset);
700 DELAY_SLOT (NIA + offset);
703 NULLIFY_NEXT_INSTRUCTION ();
708 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
709 "bgtz r<RS>, <OFFSET>"
721 address_word offset = EXTEND16 (OFFSET) << 2;
723 if ((signed_word) GPR[RS] > 0)
725 mark_branch_bug (NIA+offset);
726 DELAY_SLOT (NIA + offset);
732 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
733 "bgtzl r<RS>, <OFFSET>"
744 address_word offset = EXTEND16 (OFFSET) << 2;
746 /* NOTE: The branch occurs AFTER the next instruction has been
748 if ((signed_word) GPR[RS] > 0)
750 mark_branch_bug (NIA+offset);
751 DELAY_SLOT (NIA + offset);
754 NULLIFY_NEXT_INSTRUCTION ();
759 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
760 "blez r<RS>, <OFFSET>"
772 address_word offset = EXTEND16 (OFFSET) << 2;
774 /* NOTE: The branch occurs AFTER the next instruction has been
776 if ((signed_word) GPR[RS] <= 0)
778 mark_branch_bug (NIA+offset);
779 DELAY_SLOT (NIA + offset);
785 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
786 "bgezl r<RS>, <OFFSET>"
797 address_word offset = EXTEND16 (OFFSET) << 2;
799 if ((signed_word) GPR[RS] <= 0)
801 mark_branch_bug (NIA+offset);
802 DELAY_SLOT (NIA + offset);
805 NULLIFY_NEXT_INSTRUCTION ();
810 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
811 "bltz r<RS>, <OFFSET>"
823 address_word offset = EXTEND16 (OFFSET) << 2;
825 if ((signed_word) GPR[RS] < 0)
827 mark_branch_bug (NIA+offset);
828 DELAY_SLOT (NIA + offset);
834 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
835 "bltzal r<RS>, <OFFSET>"
847 address_word offset = EXTEND16 (OFFSET) << 2;
852 /* NOTE: The branch occurs AFTER the next instruction has been
854 if ((signed_word) GPR[RS] < 0)
856 mark_branch_bug (NIA+offset);
857 DELAY_SLOT (NIA + offset);
863 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
864 "bltzall r<RS>, <OFFSET>"
875 address_word offset = EXTEND16 (OFFSET) << 2;
880 if ((signed_word) GPR[RS] < 0)
882 mark_branch_bug (NIA+offset);
883 DELAY_SLOT (NIA + offset);
886 NULLIFY_NEXT_INSTRUCTION ();
891 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
892 "bltzl r<RS>, <OFFSET>"
903 address_word offset = EXTEND16 (OFFSET) << 2;
905 /* NOTE: The branch occurs AFTER the next instruction has been
907 if ((signed_word) GPR[RS] < 0)
909 mark_branch_bug (NIA+offset);
910 DELAY_SLOT (NIA + offset);
913 NULLIFY_NEXT_INSTRUCTION ();
918 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
919 "bne r<RS>, r<RT>, <OFFSET>"
931 address_word offset = EXTEND16 (OFFSET) << 2;
933 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
935 mark_branch_bug (NIA+offset);
936 DELAY_SLOT (NIA + offset);
942 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
943 "bnel r<RS>, r<RT>, <OFFSET>"
954 address_word offset = EXTEND16 (OFFSET) << 2;
956 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
958 mark_branch_bug (NIA+offset);
959 DELAY_SLOT (NIA + offset);
962 NULLIFY_NEXT_INSTRUCTION ();
967 000000,20.CODE,001101:SPECIAL:32::BREAK
980 /* Check for some break instruction which are reserved for use by the simulator. */
981 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
982 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
983 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
985 sim_engine_halt (SD, CPU, NULL, cia,
986 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
988 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
989 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
991 if (STATE & simDELAYSLOT)
992 PC = cia - 4; /* reference the branch instruction */
995 SignalException (BreakPoint, instruction_0);
1000 /* If we get this far, we're not an instruction reserved by the sim. Raise
1002 SignalException (BreakPoint, instruction_0);
1008 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1013 unsigned32 temp = GPR[RS];
1017 if (NotWordValue (GPR[RS]))
1019 TRACE_ALU_INPUT1 (GPR[RS]);
1020 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1022 if ((temp & mask) == 0)
1026 GPR[RD] = EXTEND32 (i);
1027 TRACE_ALU_RESULT (GPR[RD]);
1032 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1037 unsigned32 temp = GPR[RS];
1041 if (NotWordValue (GPR[RS]))
1043 TRACE_ALU_INPUT1 (GPR[RS]);
1044 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1046 if ((temp & mask) != 0)
1050 GPR[RD] = EXTEND32 (i);
1051 TRACE_ALU_RESULT (GPR[RD]);
1056 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1057 "dadd r<RD>, r<RS>, r<RT>"
1065 check_u64 (SD_, instruction_0);
1066 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1068 ALU64_BEGIN (GPR[RS]);
1069 ALU64_ADD (GPR[RT]);
1070 ALU64_END (GPR[RD]); /* This checks for overflow. */
1072 TRACE_ALU_RESULT (GPR[RD]);
1077 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1078 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1086 check_u64 (SD_, instruction_0);
1087 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1089 ALU64_BEGIN (GPR[RS]);
1090 ALU64_ADD (EXTEND16 (IMMEDIATE));
1091 ALU64_END (GPR[RT]); /* This checks for overflow. */
1093 TRACE_ALU_RESULT (GPR[RT]);
1098 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1100 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1101 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1102 TRACE_ALU_RESULT (GPR[rt]);
1105 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1106 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1114 check_u64 (SD_, instruction_0);
1115 do_daddiu (SD_, RS, RT, IMMEDIATE);
1120 :function:::void:do_daddu:int rs, int rt, int rd
1122 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1123 GPR[rd] = GPR[rs] + GPR[rt];
1124 TRACE_ALU_RESULT (GPR[rd]);
1127 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1128 "daddu r<RD>, r<RS>, r<RT>"
1136 check_u64 (SD_, instruction_0);
1137 do_daddu (SD_, RS, RT, RD);
1142 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1146 unsigned64 temp = GPR[RS];
1149 check_u64 (SD_, instruction_0);
1152 TRACE_ALU_INPUT1 (GPR[RS]);
1153 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1155 if ((temp & mask) == 0)
1159 GPR[RD] = EXTEND32 (i);
1160 TRACE_ALU_RESULT (GPR[RD]);
1165 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1169 unsigned64 temp = GPR[RS];
1172 check_u64 (SD_, instruction_0);
1175 TRACE_ALU_INPUT1 (GPR[RS]);
1176 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1178 if ((temp & mask) != 0)
1182 GPR[RD] = EXTEND32 (i);
1183 TRACE_ALU_RESULT (GPR[RD]);
1188 :function:::void:do_ddiv:int rs, int rt
1190 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1191 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1193 signed64 n = GPR[rs];
1194 signed64 d = GPR[rt];
1199 lo = SIGNED64 (0x8000000000000000);
1202 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1204 lo = SIGNED64 (0x8000000000000000);
1215 TRACE_ALU_RESULT2 (HI, LO);
1218 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1227 check_u64 (SD_, instruction_0);
1228 do_ddiv (SD_, RS, RT);
1233 :function:::void:do_ddivu:int rs, int rt
1235 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1236 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1238 unsigned64 n = GPR[rs];
1239 unsigned64 d = GPR[rt];
1244 lo = SIGNED64 (0x8000000000000000);
1255 TRACE_ALU_RESULT2 (HI, LO);
1258 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1259 "ddivu r<RS>, r<RT>"
1267 check_u64 (SD_, instruction_0);
1268 do_ddivu (SD_, RS, RT);
1273 :function:::void:do_div:int rs, int rt
1275 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1276 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1278 signed32 n = GPR[rs];
1279 signed32 d = GPR[rt];
1282 LO = EXTEND32 (0x80000000);
1285 else if (n == SIGNED32 (0x80000000) && d == -1)
1287 LO = EXTEND32 (0x80000000);
1292 LO = EXTEND32 (n / d);
1293 HI = EXTEND32 (n % d);
1296 TRACE_ALU_RESULT2 (HI, LO);
1299 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1312 do_div (SD_, RS, RT);
1317 :function:::void:do_divu:int rs, int rt
1319 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1320 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1322 unsigned32 n = GPR[rs];
1323 unsigned32 d = GPR[rt];
1326 LO = EXTEND32 (0x80000000);
1331 LO = EXTEND32 (n / d);
1332 HI = EXTEND32 (n % d);
1335 TRACE_ALU_RESULT2 (HI, LO);
1338 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1351 do_divu (SD_, RS, RT);
1356 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1366 unsigned64 op1 = GPR[rs];
1367 unsigned64 op2 = GPR[rt];
1368 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1369 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1370 /* make signed multiply unsigned */
1385 /* multiply out the 4 sub products */
1386 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1387 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1388 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1389 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1390 /* add the products */
1391 mid = ((unsigned64) VH4_8 (m00)
1392 + (unsigned64) VL4_8 (m10)
1393 + (unsigned64) VL4_8 (m01));
1394 lo = U8_4 (mid, m00);
1396 + (unsigned64) VH4_8 (mid)
1397 + (unsigned64) VH4_8 (m01)
1398 + (unsigned64) VH4_8 (m10));
1408 /* save the result HI/LO (and a gpr) */
1413 TRACE_ALU_RESULT2 (HI, LO);
1416 :function:::void:do_dmult:int rs, int rt, int rd
1418 do_dmultx (SD_, rs, rt, rd, 1);
1421 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1422 "dmult r<RS>, r<RT>"
1429 check_u64 (SD_, instruction_0);
1430 do_dmult (SD_, RS, RT, 0);
1433 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1434 "dmult r<RS>, r<RT>":RD == 0
1435 "dmult r<RD>, r<RS>, r<RT>"
1438 check_u64 (SD_, instruction_0);
1439 do_dmult (SD_, RS, RT, RD);
1444 :function:::void:do_dmultu:int rs, int rt, int rd
1446 do_dmultx (SD_, rs, rt, rd, 0);
1449 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1450 "dmultu r<RS>, r<RT>"
1457 check_u64 (SD_, instruction_0);
1458 do_dmultu (SD_, RS, RT, 0);
1461 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1462 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1463 "dmultu r<RS>, r<RT>"
1466 check_u64 (SD_, instruction_0);
1467 do_dmultu (SD_, RS, RT, RD);
1470 :function:::void:do_dsll:int rt, int rd, int shift
1472 TRACE_ALU_INPUT2 (GPR[rt], shift);
1473 GPR[rd] = GPR[rt] << shift;
1474 TRACE_ALU_RESULT (GPR[rd]);
1477 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1478 "dsll r<RD>, r<RT>, <SHIFT>"
1486 check_u64 (SD_, instruction_0);
1487 do_dsll (SD_, RT, RD, SHIFT);
1491 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1492 "dsll32 r<RD>, r<RT>, <SHIFT>"
1501 check_u64 (SD_, instruction_0);
1502 TRACE_ALU_INPUT2 (GPR[RT], s);
1503 GPR[RD] = GPR[RT] << s;
1504 TRACE_ALU_RESULT (GPR[RD]);
1507 :function:::void:do_dsllv:int rs, int rt, int rd
1509 int s = MASKED64 (GPR[rs], 5, 0);
1510 TRACE_ALU_INPUT2 (GPR[rt], s);
1511 GPR[rd] = GPR[rt] << s;
1512 TRACE_ALU_RESULT (GPR[rd]);
1515 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1516 "dsllv r<RD>, r<RT>, r<RS>"
1524 check_u64 (SD_, instruction_0);
1525 do_dsllv (SD_, RS, RT, RD);
1528 :function:::void:do_dsra:int rt, int rd, int shift
1530 TRACE_ALU_INPUT2 (GPR[rt], shift);
1531 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1532 TRACE_ALU_RESULT (GPR[rd]);
1536 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1537 "dsra r<RD>, r<RT>, <SHIFT>"
1545 check_u64 (SD_, instruction_0);
1546 do_dsra (SD_, RT, RD, SHIFT);
1550 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1551 "dsra32 r<RD>, r<RT>, <SHIFT>"
1560 check_u64 (SD_, instruction_0);
1561 TRACE_ALU_INPUT2 (GPR[RT], s);
1562 GPR[RD] = ((signed64) GPR[RT]) >> s;
1563 TRACE_ALU_RESULT (GPR[RD]);
1567 :function:::void:do_dsrav:int rs, int rt, int rd
1569 int s = MASKED64 (GPR[rs], 5, 0);
1570 TRACE_ALU_INPUT2 (GPR[rt], s);
1571 GPR[rd] = ((signed64) GPR[rt]) >> s;
1572 TRACE_ALU_RESULT (GPR[rd]);
1575 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1576 "dsrav r<RD>, r<RT>, r<RS>"
1584 check_u64 (SD_, instruction_0);
1585 do_dsrav (SD_, RS, RT, RD);
1588 :function:::void:do_dsrl:int rt, int rd, int shift
1590 TRACE_ALU_INPUT2 (GPR[rt], shift);
1591 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1592 TRACE_ALU_RESULT (GPR[rd]);
1596 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1597 "dsrl r<RD>, r<RT>, <SHIFT>"
1605 check_u64 (SD_, instruction_0);
1606 do_dsrl (SD_, RT, RD, SHIFT);
1610 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1611 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1620 check_u64 (SD_, instruction_0);
1621 TRACE_ALU_INPUT2 (GPR[RT], s);
1622 GPR[RD] = (unsigned64) GPR[RT] >> s;
1623 TRACE_ALU_RESULT (GPR[RD]);
1627 :function:::void:do_dsrlv:int rs, int rt, int rd
1629 int s = MASKED64 (GPR[rs], 5, 0);
1630 TRACE_ALU_INPUT2 (GPR[rt], s);
1631 GPR[rd] = (unsigned64) GPR[rt] >> s;
1632 TRACE_ALU_RESULT (GPR[rd]);
1637 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1638 "dsrlv r<RD>, r<RT>, r<RS>"
1646 check_u64 (SD_, instruction_0);
1647 do_dsrlv (SD_, RS, RT, RD);
1651 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1652 "dsub r<RD>, r<RS>, r<RT>"
1660 check_u64 (SD_, instruction_0);
1661 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1663 ALU64_BEGIN (GPR[RS]);
1664 ALU64_SUB (GPR[RT]);
1665 ALU64_END (GPR[RD]); /* This checks for overflow. */
1667 TRACE_ALU_RESULT (GPR[RD]);
1671 :function:::void:do_dsubu:int rs, int rt, int rd
1673 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1674 GPR[rd] = GPR[rs] - GPR[rt];
1675 TRACE_ALU_RESULT (GPR[rd]);
1678 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1679 "dsubu r<RD>, r<RS>, r<RT>"
1687 check_u64 (SD_, instruction_0);
1688 do_dsubu (SD_, RS, RT, RD);
1692 000010,26.INSTR_INDEX:NORMAL:32::J
1705 /* NOTE: The region used is that of the delay slot NIA and NOT the
1706 current instruction */
1707 address_word region = (NIA & MASK (63, 28));
1708 DELAY_SLOT (region | (INSTR_INDEX << 2));
1712 000011,26.INSTR_INDEX:NORMAL:32::JAL
1725 /* NOTE: The region used is that of the delay slot and NOT the
1726 current instruction */
1727 address_word region = (NIA & MASK (63, 28));
1729 DELAY_SLOT (region | (INSTR_INDEX << 2));
1732 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1733 "jalr r<RS>":RD == 31
1746 address_word temp = GPR[RS];
1752 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1765 DELAY_SLOT (GPR[RS]);
1769 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1771 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1772 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1773 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1780 vaddr = loadstore_ea (SD_, base, offset);
1781 if ((vaddr & access) != 0)
1783 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1785 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1786 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1787 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1788 byte = ((vaddr & mask) ^ bigendiancpu);
1789 return (memval >> (8 * byte));
1792 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1794 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1795 address_word reverseendian = (ReverseEndian ? -1 : 0);
1796 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1805 unsigned_word lhs_mask;
1808 vaddr = loadstore_ea (SD_, base, offset);
1809 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1810 paddr = (paddr ^ (reverseendian & mask));
1811 if (BigEndianMem == 0)
1812 paddr = paddr & ~access;
1814 /* compute where within the word/mem we are */
1815 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1816 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1817 nr_lhs_bits = 8 * byte + 8;
1818 nr_rhs_bits = 8 * access - 8 * byte;
1819 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1821 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1822 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1823 (long) ((unsigned64) paddr >> 32), (long) paddr,
1824 word, byte, nr_lhs_bits, nr_rhs_bits); */
1826 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1829 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1830 temp = (memval << nr_rhs_bits);
1834 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1835 temp = (memval >> nr_lhs_bits);
1837 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1838 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1840 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1841 (long) ((unsigned64) memval >> 32), (long) memval,
1842 (long) ((unsigned64) temp >> 32), (long) temp,
1843 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1844 (long) (rt >> 32), (long) rt); */
1848 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1850 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1851 address_word reverseendian = (ReverseEndian ? -1 : 0);
1852 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1859 vaddr = loadstore_ea (SD_, base, offset);
1860 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1861 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1862 paddr = (paddr ^ (reverseendian & mask));
1863 if (BigEndianMem != 0)
1864 paddr = paddr & ~access;
1865 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1866 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1867 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1868 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1869 (long) paddr, byte, (long) paddr, (long) memval); */
1871 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1873 rt |= (memval >> (8 * byte)) & screen;
1879 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1880 "lb r<RT>, <OFFSET>(r<BASE>)"
1892 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1896 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1897 "lbu r<RT>, <OFFSET>(r<BASE>)"
1909 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1913 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1914 "ld r<RT>, <OFFSET>(r<BASE>)"
1922 check_u64 (SD_, instruction_0);
1923 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1927 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1928 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1939 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1945 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1946 "ldl r<RT>, <OFFSET>(r<BASE>)"
1954 check_u64 (SD_, instruction_0);
1955 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1959 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1960 "ldr r<RT>, <OFFSET>(r<BASE>)"
1968 check_u64 (SD_, instruction_0);
1969 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1973 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1974 "lh r<RT>, <OFFSET>(r<BASE>)"
1986 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1990 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1991 "lhu r<RT>, <OFFSET>(r<BASE>)"
2003 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2007 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2008 "ll r<RT>, <OFFSET>(r<BASE>)"
2018 address_word base = GPR[BASE];
2019 address_word offset = EXTEND16 (OFFSET);
2021 address_word vaddr = loadstore_ea (SD_, base, offset);
2024 if ((vaddr & 3) != 0)
2026 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2030 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2032 unsigned64 memval = 0;
2033 unsigned64 memval1 = 0;
2034 unsigned64 mask = 0x7;
2035 unsigned int shift = 2;
2036 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2037 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2039 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2040 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2041 byte = ((vaddr & mask) ^ (bigend << shift));
2042 GPR[RT] = EXTEND32 (memval >> (8 * byte));
2050 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2051 "lld r<RT>, <OFFSET>(r<BASE>)"
2059 address_word base = GPR[BASE];
2060 address_word offset = EXTEND16 (OFFSET);
2061 check_u64 (SD_, instruction_0);
2063 address_word vaddr = loadstore_ea (SD_, base, offset);
2066 if ((vaddr & 7) != 0)
2068 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2072 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2074 unsigned64 memval = 0;
2075 unsigned64 memval1 = 0;
2076 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2085 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2086 "lui r<RT>, %#lx<IMMEDIATE>"
2098 TRACE_ALU_INPUT1 (IMMEDIATE);
2099 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2100 TRACE_ALU_RESULT (GPR[RT]);
2104 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2105 "lw r<RT>, <OFFSET>(r<BASE>)"
2117 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2121 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2122 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2134 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2138 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2139 "lwl r<RT>, <OFFSET>(r<BASE>)"
2151 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2155 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2156 "lwr r<RT>, <OFFSET>(r<BASE>)"
2168 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2172 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2173 "lwu r<RT>, <OFFSET>(r<BASE>)"
2181 check_u64 (SD_, instruction_0);
2182 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2187 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2193 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2194 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2196 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2197 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2198 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2199 LO = EXTEND32 (temp);
2200 HI = EXTEND32 (VH4_8 (temp));
2201 TRACE_ALU_RESULT2 (HI, LO);
2206 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2207 "maddu r<RS>, r<RT>"
2212 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2213 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2215 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2216 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2217 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2218 LO = EXTEND32 (temp);
2219 HI = EXTEND32 (VH4_8 (temp));
2220 TRACE_ALU_RESULT2 (HI, LO);
2224 :function:::void:do_mfhi:int rd
2226 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2227 TRACE_ALU_INPUT1 (HI);
2229 TRACE_ALU_RESULT (GPR[rd]);
2232 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2250 :function:::void:do_mflo:int rd
2252 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2253 TRACE_ALU_INPUT1 (LO);
2255 TRACE_ALU_RESULT (GPR[rd]);
2258 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2276 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2277 "movn r<RD>, r<RS>, r<RT>"
2287 TRACE_ALU_RESULT (GPR[RD]);
2293 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2294 "movz r<RD>, r<RS>, r<RT>"
2304 TRACE_ALU_RESULT (GPR[RD]);
2310 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2316 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2317 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2319 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2320 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2321 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2322 LO = EXTEND32 (temp);
2323 HI = EXTEND32 (VH4_8 (temp));
2324 TRACE_ALU_RESULT2 (HI, LO);
2329 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2330 "msubu r<RS>, r<RT>"
2335 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2336 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2338 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2339 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2340 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2341 LO = EXTEND32 (temp);
2342 HI = EXTEND32 (VH4_8 (temp));
2343 TRACE_ALU_RESULT2 (HI, LO);
2348 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2361 check_mt_hilo (SD_, HIHISTORY);
2367 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2380 check_mt_hilo (SD_, LOHISTORY);
2386 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2387 "mul r<RD>, r<RS>, r<RT>"
2392 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2394 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2395 prod = (((signed64)(signed32) GPR[RS])
2396 * ((signed64)(signed32) GPR[RT]));
2397 GPR[RD] = EXTEND32 (VL4_8 (prod));
2398 TRACE_ALU_RESULT (GPR[RD]);
2403 :function:::void:do_mult:int rs, int rt, int rd
2406 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2407 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2409 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2410 prod = (((signed64)(signed32) GPR[rs])
2411 * ((signed64)(signed32) GPR[rt]));
2412 LO = EXTEND32 (VL4_8 (prod));
2413 HI = EXTEND32 (VH4_8 (prod));
2416 TRACE_ALU_RESULT2 (HI, LO);
2419 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2430 do_mult (SD_, RS, RT, 0);
2434 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2435 "mult r<RS>, r<RT>":RD == 0
2436 "mult r<RD>, r<RS>, r<RT>"
2440 do_mult (SD_, RS, RT, RD);
2444 :function:::void:do_multu:int rs, int rt, int rd
2447 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2448 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2450 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2451 prod = (((unsigned64)(unsigned32) GPR[rs])
2452 * ((unsigned64)(unsigned32) GPR[rt]));
2453 LO = EXTEND32 (VL4_8 (prod));
2454 HI = EXTEND32 (VH4_8 (prod));
2457 TRACE_ALU_RESULT2 (HI, LO);
2460 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2461 "multu r<RS>, r<RT>"
2471 do_multu (SD_, RS, RT, 0);
2474 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2475 "multu r<RS>, r<RT>":RD == 0
2476 "multu r<RD>, r<RS>, r<RT>"
2480 do_multu (SD_, RS, RT, RD);
2484 :function:::void:do_nor:int rs, int rt, int rd
2486 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2487 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2488 TRACE_ALU_RESULT (GPR[rd]);
2491 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2492 "nor r<RD>, r<RS>, r<RT>"
2504 do_nor (SD_, RS, RT, RD);
2508 :function:::void:do_or:int rs, int rt, int rd
2510 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2511 GPR[rd] = (GPR[rs] | GPR[rt]);
2512 TRACE_ALU_RESULT (GPR[rd]);
2515 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2516 "or r<RD>, r<RS>, r<RT>"
2528 do_or (SD_, RS, RT, RD);
2533 :function:::void:do_ori:int rs, int rt, unsigned immediate
2535 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2536 GPR[rt] = (GPR[rs] | immediate);
2537 TRACE_ALU_RESULT (GPR[rt]);
2540 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2541 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2553 do_ori (SD_, RS, RT, IMMEDIATE);
2557 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2558 "pref <HINT>, <OFFSET>(r<BASE>)"
2565 address_word base = GPR[BASE];
2566 address_word offset = EXTEND16 (OFFSET);
2568 address_word vaddr = loadstore_ea (SD_, base, offset);
2572 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2573 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2579 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2581 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2582 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2583 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2590 vaddr = loadstore_ea (SD_, base, offset);
2591 if ((vaddr & access) != 0)
2593 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2595 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2596 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2597 byte = ((vaddr & mask) ^ bigendiancpu);
2598 memval = (word << (8 * byte));
2599 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2602 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2604 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2605 address_word reverseendian = (ReverseEndian ? -1 : 0);
2606 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2616 vaddr = loadstore_ea (SD_, base, offset);
2617 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2618 paddr = (paddr ^ (reverseendian & mask));
2619 if (BigEndianMem == 0)
2620 paddr = paddr & ~access;
2622 /* compute where within the word/mem we are */
2623 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2624 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2625 nr_lhs_bits = 8 * byte + 8;
2626 nr_rhs_bits = 8 * access - 8 * byte;
2627 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2628 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2629 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2630 (long) ((unsigned64) paddr >> 32), (long) paddr,
2631 word, byte, nr_lhs_bits, nr_rhs_bits); */
2635 memval = (rt >> nr_rhs_bits);
2639 memval = (rt << nr_lhs_bits);
2641 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2642 (long) ((unsigned64) rt >> 32), (long) rt,
2643 (long) ((unsigned64) memval >> 32), (long) memval); */
2644 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2647 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2649 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2650 address_word reverseendian = (ReverseEndian ? -1 : 0);
2651 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2658 vaddr = loadstore_ea (SD_, base, offset);
2659 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2660 paddr = (paddr ^ (reverseendian & mask));
2661 if (BigEndianMem != 0)
2663 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2664 memval = (rt << (byte * 8));
2665 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2669 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2670 "sb r<RT>, <OFFSET>(r<BASE>)"
2682 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2686 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2687 "sc r<RT>, <OFFSET>(r<BASE>)"
2697 unsigned32 instruction = instruction_0;
2698 address_word base = GPR[BASE];
2699 address_word offset = EXTEND16 (OFFSET);
2701 address_word vaddr = loadstore_ea (SD_, base, offset);
2704 if ((vaddr & 3) != 0)
2706 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2710 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2712 unsigned64 memval = 0;
2713 unsigned64 memval1 = 0;
2714 unsigned64 mask = 0x7;
2716 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2717 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2718 memval = ((unsigned64) GPR[RT] << (8 * byte));
2721 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2730 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2731 "scd r<RT>, <OFFSET>(r<BASE>)"
2739 address_word base = GPR[BASE];
2740 address_word offset = EXTEND16 (OFFSET);
2741 check_u64 (SD_, instruction_0);
2743 address_word vaddr = loadstore_ea (SD_, base, offset);
2746 if ((vaddr & 7) != 0)
2748 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2752 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2754 unsigned64 memval = 0;
2755 unsigned64 memval1 = 0;
2759 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2768 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2769 "sd r<RT>, <OFFSET>(r<BASE>)"
2777 check_u64 (SD_, instruction_0);
2778 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2782 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2783 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2793 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2797 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2798 "sdl r<RT>, <OFFSET>(r<BASE>)"
2806 check_u64 (SD_, instruction_0);
2807 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2811 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2812 "sdr r<RT>, <OFFSET>(r<BASE>)"
2820 check_u64 (SD_, instruction_0);
2821 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2825 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2826 "sh r<RT>, <OFFSET>(r<BASE>)"
2838 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2842 :function:::void:do_sll:int rt, int rd, int shift
2844 unsigned32 temp = (GPR[rt] << shift);
2845 TRACE_ALU_INPUT2 (GPR[rt], shift);
2846 GPR[rd] = EXTEND32 (temp);
2847 TRACE_ALU_RESULT (GPR[rd]);
2850 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2851 "nop":RD == 0 && RT == 0 && SHIFT == 0
2852 "sll r<RD>, r<RT>, <SHIFT>"
2862 /* Skip shift for NOP, so that there won't be lots of extraneous
2864 if (RD != 0 || RT != 0 || SHIFT != 0)
2865 do_sll (SD_, RT, RD, SHIFT);
2868 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2869 "nop":RD == 0 && RT == 0 && SHIFT == 0
2870 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2871 "sll r<RD>, r<RT>, <SHIFT>"
2875 /* Skip shift for NOP and SSNOP, so that there won't be lots of
2876 extraneous trace output. */
2877 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2878 do_sll (SD_, RT, RD, SHIFT);
2882 :function:::void:do_sllv:int rs, int rt, int rd
2884 int s = MASKED (GPR[rs], 4, 0);
2885 unsigned32 temp = (GPR[rt] << s);
2886 TRACE_ALU_INPUT2 (GPR[rt], s);
2887 GPR[rd] = EXTEND32 (temp);
2888 TRACE_ALU_RESULT (GPR[rd]);
2891 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2892 "sllv r<RD>, r<RT>, r<RS>"
2904 do_sllv (SD_, RS, RT, RD);
2908 :function:::void:do_slt:int rs, int rt, int rd
2910 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2911 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2912 TRACE_ALU_RESULT (GPR[rd]);
2915 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2916 "slt r<RD>, r<RS>, r<RT>"
2928 do_slt (SD_, RS, RT, RD);
2932 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2934 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2935 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2936 TRACE_ALU_RESULT (GPR[rt]);
2939 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2940 "slti r<RT>, r<RS>, <IMMEDIATE>"
2952 do_slti (SD_, RS, RT, IMMEDIATE);
2956 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2958 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2959 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2960 TRACE_ALU_RESULT (GPR[rt]);
2963 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2964 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2976 do_sltiu (SD_, RS, RT, IMMEDIATE);
2981 :function:::void:do_sltu:int rs, int rt, int rd
2983 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2984 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2985 TRACE_ALU_RESULT (GPR[rd]);
2988 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2989 "sltu r<RD>, r<RS>, r<RT>"
3001 do_sltu (SD_, RS, RT, RD);
3005 :function:::void:do_sra:int rt, int rd, int shift
3007 signed32 temp = (signed32) GPR[rt] >> shift;
3008 if (NotWordValue (GPR[rt]))
3010 TRACE_ALU_INPUT2 (GPR[rt], shift);
3011 GPR[rd] = EXTEND32 (temp);
3012 TRACE_ALU_RESULT (GPR[rd]);
3015 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3016 "sra r<RD>, r<RT>, <SHIFT>"
3028 do_sra (SD_, RT, RD, SHIFT);
3033 :function:::void:do_srav:int rs, int rt, int rd
3035 int s = MASKED (GPR[rs], 4, 0);
3036 signed32 temp = (signed32) GPR[rt] >> s;
3037 if (NotWordValue (GPR[rt]))
3039 TRACE_ALU_INPUT2 (GPR[rt], s);
3040 GPR[rd] = EXTEND32 (temp);
3041 TRACE_ALU_RESULT (GPR[rd]);
3044 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3045 "srav r<RD>, r<RT>, r<RS>"
3057 do_srav (SD_, RS, RT, RD);
3062 :function:::void:do_srl:int rt, int rd, int shift
3064 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3065 if (NotWordValue (GPR[rt]))
3067 TRACE_ALU_INPUT2 (GPR[rt], shift);
3068 GPR[rd] = EXTEND32 (temp);
3069 TRACE_ALU_RESULT (GPR[rd]);
3072 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3073 "srl r<RD>, r<RT>, <SHIFT>"
3085 do_srl (SD_, RT, RD, SHIFT);
3089 :function:::void:do_srlv:int rs, int rt, int rd
3091 int s = MASKED (GPR[rs], 4, 0);
3092 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3093 if (NotWordValue (GPR[rt]))
3095 TRACE_ALU_INPUT2 (GPR[rt], s);
3096 GPR[rd] = EXTEND32 (temp);
3097 TRACE_ALU_RESULT (GPR[rd]);
3100 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3101 "srlv r<RD>, r<RT>, r<RS>"
3113 do_srlv (SD_, RS, RT, RD);
3117 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3118 "sub r<RD>, r<RS>, r<RT>"
3130 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3132 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3134 ALU32_BEGIN (GPR[RS]);
3135 ALU32_SUB (GPR[RT]);
3136 ALU32_END (GPR[RD]); /* This checks for overflow. */
3138 TRACE_ALU_RESULT (GPR[RD]);
3142 :function:::void:do_subu:int rs, int rt, int rd
3144 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3146 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3147 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3148 TRACE_ALU_RESULT (GPR[rd]);
3151 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3152 "subu r<RD>, r<RS>, r<RT>"
3164 do_subu (SD_, RS, RT, RD);
3168 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3169 "sw r<RT>, <OFFSET>(r<BASE>)"
3181 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3185 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3186 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3198 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3202 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3203 "swl r<RT>, <OFFSET>(r<BASE>)"
3215 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3219 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3220 "swr r<RT>, <OFFSET>(r<BASE>)"
3232 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3236 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3249 SyncOperation (STYPE);
3253 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3254 "syscall %#lx<CODE>"
3266 SignalException (SystemCall, instruction_0);
3270 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3281 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3282 SignalException (Trap, instruction_0);
3286 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3287 "teqi r<RS>, <IMMEDIATE>"
3297 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3298 SignalException (Trap, instruction_0);
3302 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3313 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3314 SignalException (Trap, instruction_0);
3318 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3319 "tgei r<RS>, <IMMEDIATE>"
3329 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3330 SignalException (Trap, instruction_0);
3334 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3335 "tgeiu r<RS>, <IMMEDIATE>"
3345 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3346 SignalException (Trap, instruction_0);
3350 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3361 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3362 SignalException (Trap, instruction_0);
3366 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3377 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3378 SignalException (Trap, instruction_0);
3382 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3383 "tlti r<RS>, <IMMEDIATE>"
3393 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3394 SignalException (Trap, instruction_0);
3398 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3399 "tltiu r<RS>, <IMMEDIATE>"
3409 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3410 SignalException (Trap, instruction_0);
3414 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3425 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3426 SignalException (Trap, instruction_0);
3430 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3441 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3442 SignalException (Trap, instruction_0);
3446 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3447 "tnei r<RS>, <IMMEDIATE>"
3457 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3458 SignalException (Trap, instruction_0);
3462 :function:::void:do_xor:int rs, int rt, int rd
3464 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3465 GPR[rd] = GPR[rs] ^ GPR[rt];
3466 TRACE_ALU_RESULT (GPR[rd]);
3469 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3470 "xor r<RD>, r<RS>, r<RT>"
3482 do_xor (SD_, RS, RT, RD);
3486 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3488 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3489 GPR[rt] = GPR[rs] ^ immediate;
3490 TRACE_ALU_RESULT (GPR[rt]);
3493 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3494 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3506 do_xori (SD_, RS, RT, IMMEDIATE);
3511 // MIPS Architecture:
3513 // FPU Instruction Set (COP1 & COP1X)
3521 case fmt_single: return "s";
3522 case fmt_double: return "d";
3523 case fmt_word: return "w";
3524 case fmt_long: return "l";
3525 case fmt_ps: return "ps";
3526 default: return "?";
3546 :%s::::COND:int cond
3550 case 00: return "f";
3551 case 01: return "un";
3552 case 02: return "eq";
3553 case 03: return "ueq";
3554 case 04: return "olt";
3555 case 05: return "ult";
3556 case 06: return "ole";
3557 case 07: return "ule";
3558 case 010: return "sf";
3559 case 011: return "ngle";
3560 case 012: return "seq";
3561 case 013: return "ngl";
3562 case 014: return "lt";
3563 case 015: return "nge";
3564 case 016: return "le";
3565 case 017: return "ngt";
3566 default: return "?";
3573 // Check that the given FPU format is usable, and signal a
3574 // ReservedInstruction exception if not.
3577 // check_fmt checks that the format is single or double.
3578 :function:::void:check_fmt:int fmt, instruction_word insn
3590 if ((fmt != fmt_single) && (fmt != fmt_double))
3591 SignalException (ReservedInstruction, insn);
3594 // check_fmt_p checks that the format is single, double, or paired single.
3595 :function:::void:check_fmt_p:int fmt, instruction_word insn
3605 /* None of these ISAs support Paired Single, so just fall back to
3606 the single/double check. */
3607 check_fmt (SD_, fmt, insn);
3610 :function:::void:check_fmt_p:int fmt, instruction_word insn
3614 if ((fmt != fmt_single) && (fmt != fmt_double)
3615 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3616 SignalException (ReservedInstruction, insn);
3622 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3623 // exception if not.
3626 :function:::void:check_fpu:
3638 if (! COP_Usable (1))
3639 SignalExceptionCoProcessorUnusable (1);
3643 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3644 "abs.%s<FMT> f<FD>, f<FS>"
3658 check_fmt_p (SD_, fmt, instruction_0);
3659 StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
3664 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3665 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3679 check_fmt_p (SD_, fmt, instruction_0);
3680 StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
3684 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
3685 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
3693 check_u64 (SD_, instruction_0);
3694 fs = ValueFPR (FS, fmt_ps);
3695 if ((GPR[RS] & 0x3) != 0)
3697 if ((GPR[RS] & 0x4) == 0)
3701 ft = ValueFPR (FT, fmt_ps);
3703 fd = PackPS (PSLower (fs), PSUpper (ft));
3705 fd = PackPS (PSLower (ft), PSUpper (fs));
3707 StoreFPR (FD, fmt_ps, fd);
3716 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3717 "bc1%s<TF>%s<ND> <OFFSET>"
3723 check_branch_bug ();
3724 TRACE_BRANCH_INPUT (PREVCOC1());
3725 if (PREVCOC1() == TF)
3727 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3728 TRACE_BRANCH_RESULT (dest);
3729 mark_branch_bug (dest);
3734 TRACE_BRANCH_RESULT (0);
3735 NULLIFY_NEXT_INSTRUCTION ();
3739 TRACE_BRANCH_RESULT (NIA);
3743 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3744 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3745 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3755 check_branch_bug ();
3756 if (GETFCC(CC) == TF)
3758 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3759 mark_branch_bug (dest);
3764 NULLIFY_NEXT_INSTRUCTION ();
3769 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3770 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3777 check_fmt_p (SD_, fmt, instruction_0);
3778 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
3779 TRACE_ALU_RESULT (ValueFCR (31));
3782 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3783 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3784 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3795 check_fmt_p (SD_, fmt, instruction_0);
3796 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
3797 TRACE_ALU_RESULT (ValueFCR (31));
3801 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3802 "ceil.l.%s<FMT> f<FD>, f<FS>"
3813 check_fmt (SD_, fmt, instruction_0);
3814 StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3819 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3820 "ceil.w.%s<FMT> f<FD>, f<FS>"
3833 check_fmt (SD_, fmt, instruction_0);
3834 StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3839 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
3847 PENDING_FILL (RT, EXTEND32 (FCR0));
3849 PENDING_FILL (RT, EXTEND32 (FCR31));
3853 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
3861 if (FS == 0 || FS == 31)
3863 unsigned_word fcr = ValueFCR (FS);
3864 TRACE_ALU_INPUT1 (fcr);
3868 TRACE_ALU_RESULT (GPR[RT]);
3871 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
3878 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
3880 unsigned_word fcr = ValueFCR (FS);
3881 TRACE_ALU_INPUT1 (fcr);
3885 TRACE_ALU_RESULT (GPR[RT]);
3888 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
3896 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
3900 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
3908 TRACE_ALU_INPUT1 (GPR[RT]);
3910 StoreFCR (FS, GPR[RT]);
3914 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
3921 TRACE_ALU_INPUT1 (GPR[RT]);
3922 if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
3923 StoreFCR (FS, GPR[RT]);
3929 // FIXME: Does not correctly differentiate between mips*
3931 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3932 "cvt.d.%s<FMT> f<FD>, f<FS>"
3946 if ((fmt == fmt_double) | 0)
3947 SignalException (ReservedInstruction, instruction_0);
3948 StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
3953 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3954 "cvt.l.%s<FMT> f<FD>, f<FS>"
3965 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3966 SignalException (ReservedInstruction, instruction_0);
3967 StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
3972 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
3973 "cvt.ps.s f<FD>, f<FS>, f<FT>"
3978 check_u64 (SD_, instruction_0);
3979 StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
3980 ValueFPR (FT, fmt_single)));
3985 // FIXME: Does not correctly differentiate between mips*
3987 010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3988 "cvt.s.%s<FMT> f<FD>, f<FS>"
4002 if ((fmt == fmt_single) | 0)
4003 SignalException (ReservedInstruction, instruction_0);
4004 StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4009 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4010 "cvt.s.pl f<FD>, f<FS>"
4015 check_u64 (SD_, instruction_0);
4016 StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4020 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4021 "cvt.s.pu f<FD>, f<FS>"
4026 check_u64 (SD_, instruction_0);
4027 StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4031 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4032 "cvt.w.%s<FMT> f<FD>, f<FS>"
4046 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4047 SignalException (ReservedInstruction, instruction_0);
4048 StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4053 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4054 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4068 check_fmt (SD_, fmt, instruction_0);
4069 StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4073 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4074 "dmfc1 r<RT>, f<FS>"
4079 check_u64 (SD_, instruction_0);
4080 if (SizeFGR () == 64)
4082 else if ((FS & 0x1) == 0)
4083 v = SET64HI (FGR[FS+1]) | FGR[FS];
4085 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4086 PENDING_FILL (RT, v);
4087 TRACE_ALU_RESULT (v);
4090 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4091 "dmfc1 r<RT>, f<FS>"
4100 check_u64 (SD_, instruction_0);
4101 if (SizeFGR () == 64)
4103 else if ((FS & 0x1) == 0)
4104 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4106 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4107 TRACE_ALU_RESULT (GPR[RT]);
4111 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4112 "dmtc1 r<RT>, f<FS>"
4117 check_u64 (SD_, instruction_0);
4118 if (SizeFGR () == 64)
4119 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4120 else if ((FS & 0x1) == 0)
4122 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4123 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4127 TRACE_FP_RESULT (GPR[RT]);
4130 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4131 "dmtc1 r<RT>, f<FS>"
4140 check_u64 (SD_, instruction_0);
4141 if (SizeFGR () == 64)
4142 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4143 else if ((FS & 0x1) == 0)
4144 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4150 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4151 "floor.l.%s<FMT> f<FD>, f<FS>"
4162 check_fmt (SD_, fmt, instruction_0);
4163 StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4168 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4169 "floor.w.%s<FMT> f<FD>, f<FS>"
4182 check_fmt (SD_, fmt, instruction_0);
4183 StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4188 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
4189 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4201 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4205 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4206 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4213 check_u64 (SD_, instruction_0);
4214 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4219 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4220 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4233 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4237 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4238 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4245 check_u64 (SD_, instruction_0);
4246 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4251 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
4252 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4260 check_u64 (SD_, instruction_0);
4261 check_fmt_p (SD_, fmt, instruction_0);
4262 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4263 ValueFPR (FR, fmt), fmt));
4267 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4275 v = EXTEND32 (FGR[FS]);
4276 PENDING_FILL (RT, v);
4277 TRACE_ALU_RESULT (v);
4280 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4291 GPR[RT] = EXTEND32 (FGR[FS]);
4292 TRACE_ALU_RESULT (GPR[RT]);
4296 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4297 "mov.%s<FMT> f<FD>, f<FS>"
4311 check_fmt_p (SD_, fmt, instruction_0);
4312 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4318 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4319 "mov%s<TF> r<RD>, r<RS>, <CC>"
4327 if (GETFCC(CC) == TF)
4334 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4335 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4346 if (GETFCC(CC) == TF)
4347 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4349 StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
4354 fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4356 PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4358 StoreFPR (FD, fmt_ps, fd);
4363 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4364 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4373 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4375 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4382 // MOVT.fmt see MOVtf.fmt
4386 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4387 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4396 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4398 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4402 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
4403 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4411 check_u64 (SD_, instruction_0);
4412 check_fmt_p (SD_, fmt, instruction_0);
4413 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4414 ValueFPR (FR, fmt), fmt));
4418 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4425 if (SizeFGR () == 64)
4426 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4428 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4429 TRACE_FP_RESULT (GPR[RT]);
4432 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4443 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4447 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4448 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4462 check_fmt_p (SD_, fmt, instruction_0);
4463 StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4467 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4468 "neg.%s<FMT> f<FD>, f<FS>"
4482 check_fmt_p (SD_, fmt, instruction_0);
4483 StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4487 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
4488 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4496 check_u64 (SD_, instruction_0);
4497 check_fmt_p (SD_, fmt, instruction_0);
4498 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4499 ValueFPR (FR, fmt), fmt));
4503 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
4504 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4512 check_u64 (SD_, instruction_0);
4513 check_fmt_p (SD_, fmt, instruction_0);
4514 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4515 ValueFPR (FR, fmt), fmt));
4519 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
4520 "pll.ps f<FD>, f<FS>, f<FT>"
4525 check_u64 (SD_, instruction_0);
4526 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4527 PSLower (ValueFPR (FT, fmt_ps))));
4531 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
4532 "plu.ps f<FD>, f<FS>, f<FT>"
4537 check_u64 (SD_, instruction_0);
4538 StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4539 PSUpper (ValueFPR (FT, fmt_ps))));
4543 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4544 "prefx <HINT>, r<INDEX>(r<BASE>)"
4550 address_word base = GPR[BASE];
4551 address_word index = GPR[INDEX];
4553 address_word vaddr = loadstore_ea (SD_, base, index);
4556 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4557 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4562 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
4563 "pul.ps f<FD>, f<FS>, f<FT>"
4568 check_u64 (SD_, instruction_0);
4569 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4570 PSLower (ValueFPR (FT, fmt_ps))));
4574 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
4575 "puu.ps f<FD>, f<FS>, f<FT>"
4580 check_u64 (SD_, instruction_0);
4581 StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4582 PSUpper (ValueFPR (FT, fmt_ps))));
4586 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4587 "recip.%s<FMT> f<FD>, f<FS>"
4595 check_fmt (SD_, fmt, instruction_0);
4596 StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
4600 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4601 "round.l.%s<FMT> f<FD>, f<FS>"
4612 check_fmt (SD_, fmt, instruction_0);
4613 StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4618 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4619 "round.w.%s<FMT> f<FD>, f<FS>"
4632 check_fmt (SD_, fmt, instruction_0);
4633 StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4638 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4639 "rsqrt.%s<FMT> f<FD>, f<FS>"
4647 check_fmt (SD_, fmt, instruction_0);
4648 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
4652 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
4653 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4665 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4669 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4670 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4677 check_u64 (SD_, instruction_0);
4678 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4682 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4683 "sqrt.%s<FMT> f<FD>, f<FS>"
4696 check_fmt (SD_, fmt, instruction_0);
4697 StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
4701 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4702 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4716 check_fmt_p (SD_, fmt, instruction_0);
4717 StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4722 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4723 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4735 address_word base = GPR[BASE];
4736 address_word offset = EXTEND16 (OFFSET);
4739 address_word vaddr = loadstore_ea (SD_, base, offset);
4742 if ((vaddr & 3) != 0)
4744 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4748 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4751 uword64 memval1 = 0;
4752 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4753 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4754 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4756 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4757 byte = ((vaddr & mask) ^ bigendiancpu);
4758 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4759 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4766 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4767 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4774 address_word base = GPR[BASE];
4775 address_word index = GPR[INDEX];
4777 check_u64 (SD_, instruction_0);
4779 address_word vaddr = loadstore_ea (SD_, base, index);
4782 if ((vaddr & 3) != 0)
4784 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4788 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4790 unsigned64 memval = 0;
4791 unsigned64 memval1 = 0;
4792 unsigned64 mask = 0x7;
4794 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4795 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4796 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4798 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4806 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4807 "trunc.l.%s<FMT> f<FD>, f<FS>"
4818 check_fmt (SD_, fmt, instruction_0);
4819 StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4824 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4825 "trunc.w.%s<FMT> f<FD>, f<FS>"
4838 check_fmt (SD_, fmt, instruction_0);
4839 StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4845 // MIPS Architecture:
4847 // System Control Instruction Set (COP0)
4851 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4863 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4865 // stub needed for eCos as tx39 hardware bug workaround
4872 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4885 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4897 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4910 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4911 "cache <OP>, <OFFSET>(r<BASE>)"
4921 address_word base = GPR[BASE];
4922 address_word offset = EXTEND16 (OFFSET);
4924 address_word vaddr = loadstore_ea (SD_, base, offset);
4927 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4928 CacheOp(OP,vaddr,paddr,instruction_0);
4933 010000,1,0000000000000000000,111001:COP0:32::DI
4944 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4945 "dmfc0 r<RT>, r<RD>"
4951 check_u64 (SD_, instruction_0);
4952 DecodeCoproc (instruction_0);
4956 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4957 "dmtc0 r<RT>, r<RD>"
4963 check_u64 (SD_, instruction_0);
4964 DecodeCoproc (instruction_0);
4968 010000,1,0000000000000000000,111000:COP0:32::EI
4980 010000,1,0000000000000000000,011000:COP0:32::ERET
4990 if (SR & status_ERL)
4992 /* Oops, not yet available */
4993 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5005 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5006 "mfc0 r<RT>, r<RD> # <REGX>"
5018 TRACE_ALU_INPUT0 ();
5019 DecodeCoproc (instruction_0);
5020 TRACE_ALU_RESULT (GPR[RT]);
5023 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5024 "mtc0 r<RT>, r<RD> # <REGX>"
5036 DecodeCoproc (instruction_0);
5040 010000,1,0000000000000000000,010000:COP0:32::RFE
5051 DecodeCoproc (instruction_0);
5055 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5056 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5067 DecodeCoproc (instruction_0);
5072 010000,1,0000000000000000000,001000:COP0:32::TLBP
5085 010000,1,0000000000000000000,000001:COP0:32::TLBR
5098 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5111 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5125 :include:::mdmx.igen