sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 // In mips.igen, the semantics for many of the instructions were created
   4 // using code generated by gencode.  Those semantic segments could be
   5 // greatly simplified.
   6 //
   7 //    <insn> ::=
   8 //        <insn-word> { "+" <insn-word> }
   9 //        ":" <format-name>
  10 //        ":" <filter-flags>
  11 //        ":" <options>
  12 //        ":" <name>
  13 //        <nl>
  14 //        { <insn-model> }
  15 //        { <insn-mnemonic> }
  16 //        <code-block>
  17 //
  18
  19
  20 // IGEN config - mips16
  21 // :option:16::insn-bit-size:16
  22 // :option:16::hi-bit-nr:15
  23 :option:16::insn-specifying-widths:true
  24 :option:16::gen-delayed-branch:false
  25
  26 // IGEN config - mips32/64..
  27 // :option:32::insn-bit-size:32
  28 // :option:32::hi-bit-nr:31
  29 :option:32::insn-specifying-widths:true
  30 :option:32::gen-delayed-branch:false
  31
  32
  33 // Generate separate simulators for each target
  34 // :option:::multi-sim:true
  35
  36
  37 // Models known by this simulator are defined below.
  38 //
  39 // When placing models in the instruction descriptions, please place
  40 // them one per line, in the order given here.
  41
  42 //  MIPS ISAs:
  43 //
  44 //  Instructions and related functions for these models are included in
  45 //  this file.
  46 :model:::mipsI:mips3000:
  47 :model:::mipsII:mips6000:
  48 :model:::mipsIII:mips4000:
  49 :model:::mipsIV:mips8000:
  50 :model:::mipsV:mipsisaV:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr5000:mips5000:
  61 :model:::r3900:mips3900:                // tx.igen
  62
  63 //  MIPS Application Specific Extensions (ASEs)
  64 //
  65 //  Instructions for the ASEs are in separate .igen files.
  66 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  67
  68
  69 // Pseudo instructions known by IGEN
  70 :internal::::illegal:
  71 {
  72   SignalException (ReservedInstruction, 0);
  73 }
  74
  75
  76 // Pseudo instructions known by interp.c
  77 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  78 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  79 "rsvd <OP>"
  80 {
  81   SignalException (ReservedInstruction, instruction_0);
  82 }
  83
  84
  85
  86 // Helper:
  87 //
  88 // Simulate a 32 bit delayslot instruction
  89 //
  90
  91 :function:::address_word:delayslot32:address_word target
  92 {
  93   instruction_word delay_insn;
  94   sim_events_slip (SD, 1);
  95   DSPC = CIA;
  96   CIA = CIA + 4; /* NOTE not mips16 */
  97   STATE |= simDELAYSLOT;
  98   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  99   ENGINE_ISSUE_PREFIX_HOOK();
 100   idecode_issue (CPU_, delay_insn, (CIA));
 101   STATE &= ~simDELAYSLOT;
 102   return target;
 103 }
 104
 105 :function:::address_word:nullify_next_insn32:
 106 {
 107   sim_events_slip (SD, 1);
 108   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 109   return CIA + 8;
 110 }
 111
 112 // Helper:
 113 //
 114 // Check that an access to a HI/LO register meets timing requirements
 115 //
 116 // The following requirements exist:
 117 //
 118 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 119 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 120 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 121 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 122 //
 123
 124 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 125 {
 126   if (history->mf.timestamp + 3 > time)
 127     {
 128       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 129                         itable[MY_INDEX].name,
 130                         new, (long) CIA,
 131                         (long) history->mf.cia);
 132       return 0;
 133     }
 134   return 1;
 135 }
 136
 137 :function:::int:check_mt_hilo:hilo_history *history
 138 *mipsI:
 139 *mipsII:
 140 *mipsIII:
 141 *mipsIV:
 142 *mipsV:
 143 *vr4100:
 144 *vr5000:
 145 {
 146   signed64 time = sim_events_time (SD);
 147   int ok = check_mf_cycles (SD_, history, time, "MT");
 148   history->mt.timestamp = time;
 149   history->mt.cia = CIA;
 150   return ok;
 151 }
 152
 153 :function:::int:check_mt_hilo:hilo_history *history
 154 *r3900:
 155 {
 156   signed64 time = sim_events_time (SD);
 157   history->mt.timestamp = time;
 158   history->mt.cia = CIA;
 159   return 1;
 160 }
 161
 162
 163 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 164 *mipsI:
 165 *mipsII:
 166 *mipsIII:
 167 *mipsIV:
 168 *mipsV:
 169 *vr4100:
 170 *vr5000:
 171 *r3900:
 172 {
 173   signed64 time = sim_events_time (SD);
 174   int ok = 1;
 175   if (peer != NULL
 176       && peer->mt.timestamp > history->op.timestamp
 177       && history->mt.timestamp < history->op.timestamp
 178       && ! (history->mf.timestamp > history->op.timestamp
 179             && history->mf.timestamp < peer->mt.timestamp)
 180       && ! (peer->mf.timestamp > history->op.timestamp
 181             && peer->mf.timestamp < peer->mt.timestamp))
 182     {
 183       /* The peer has been written to since the last OP yet we have
 184          not */
 185       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 186                         itable[MY_INDEX].name,
 187                         (long) CIA,
 188                         (long) history->op.cia,
 189                         (long) peer->mt.cia);
 190       ok = 0;
 191     }
 192   history->mf.timestamp = time;
 193   history->mf.cia = CIA;
 194   return ok;
 195 }
 196
 197
 198
 199 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 200 *mipsI:
 201 *mipsII:
 202 *mipsIII:
 203 *mipsIV:
 204 *mipsV:
 205 *vr4100:
 206 *vr5000:
 207 {
 208   signed64 time = sim_events_time (SD);
 209   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 210             && check_mf_cycles (SD_, lo, time, "OP"));
 211   hi->op.timestamp = time;
 212   lo->op.timestamp = time;
 213   hi->op.cia = CIA;
 214   lo->op.cia = CIA;
 215   return ok;
 216 }
 217
 218 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 219 // a mf{hi,lo}
 220 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 221 *r3900:
 222 {
 223   /* FIXME: could record the fact that a stall occured if we want */
 224   signed64 time = sim_events_time (SD);
 225   hi->op.timestamp = time;
 226   lo->op.timestamp = time;
 227   hi->op.cia = CIA;
 228   lo->op.cia = CIA;
 229   return 1;
 230 }
 231
 232
 233 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 234 *mipsI:
 235 *mipsII:
 236 *mipsIII:
 237 *mipsIV:
 238 *mipsV:
 239 *vr4100:
 240 *vr5000:
 241 *r3900:
 242 {
 243   signed64 time = sim_events_time (SD);
 244   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 245             && check_mf_cycles (SD_, lo, time, "OP"));
 246   hi->op.timestamp = time;
 247   lo->op.timestamp = time;
 248   hi->op.cia = CIA;
 249   lo->op.cia = CIA;
 250   return ok;
 251 }
 252
 253
 254 // Helper:
 255 //
 256 // Check that the 64-bit instruction can currently be used, and signal
 257 // an ReservedInstruction exception if not.
 258 //
 259
 260 :function:::void:check_u64:instruction_word insn
 261 *mipsIII:
 262 *mipsIV:
 263 *mipsV:
 264 *vr4100:
 265 *vr5000:
 266 {
 267   // On mips64, if UserMode check SR:PX & SR:UX bits.
 268   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 269 }
 270
 271
 272
 273 //
 274 // MIPS Architecture:
 275 //
 276 //        CPU Instruction Set (mipsI - mipsV)
 277 //
 278
 279
 280
 281 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 282 "add r<RD>, r<RS>, r<RT>"
 283 *mipsI:
 284 *mipsII:
 285 *mipsIII:
 286 *mipsIV:
 287 *mipsV:
 288 *vr4100:
 289 *vr5000:
 290 *r3900:
 291 {
 292   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 293   {
 294     ALU32_BEGIN (GPR[RS]);
 295     ALU32_ADD (GPR[RT]);
 296     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 297   }
 298   TRACE_ALU_RESULT (GPR[RD]);
 299 }
 300
 301
 302
 303 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 304 "addi r<RT>, r<RS>, <IMMEDIATE>"
 305 *mipsI:
 306 *mipsII:
 307 *mipsIII:
 308 *mipsIV:
 309 *mipsV:
 310 *vr4100:
 311 *vr5000:
 312 *r3900:
 313 {
 314   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 315   {
 316     ALU32_BEGIN (GPR[RS]);
 317     ALU32_ADD (EXTEND16 (IMMEDIATE));
 318     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 319   }
 320   TRACE_ALU_RESULT (GPR[RT]);
 321 }
 322
 323
 324
 325 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 326 {
 327   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 328   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 329   TRACE_ALU_RESULT (GPR[rt]);
 330 }
 331
 332 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 333 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 334 *mipsI:
 335 *mipsII:
 336 *mipsIII:
 337 *mipsIV:
 338 *mipsV:
 339 *vr4100:
 340 *vr5000:
 341 *r3900:
 342 {
 343   do_addiu (SD_, RS, RT, IMMEDIATE);
 344 }
 345
 346
 347
 348 :function:::void:do_addu:int rs, int rt, int rd
 349 {
 350   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 351   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 352   TRACE_ALU_RESULT (GPR[rd]);
 353 }
 354
 355 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 356 "addu r<RD>, r<RS>, r<RT>"
 357 *mipsI:
 358 *mipsII:
 359 *mipsIII:
 360 *mipsIV:
 361 *mipsV:
 362 *vr4100:
 363 *vr5000:
 364 *r3900:
 365 {
 366   do_addu (SD_, RS, RT, RD);
 367 }
 368
 369
 370
 371 :function:::void:do_and:int rs, int rt, int rd
 372 {
 373   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 374   GPR[rd] = GPR[rs] & GPR[rt];
 375   TRACE_ALU_RESULT (GPR[rd]);
 376 }
 377
 378 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 379 "and r<RD>, r<RS>, r<RT>"
 380 *mipsI:
 381 *mipsII:
 382 *mipsIII:
 383 *mipsIV:
 384 *mipsV:
 385 *vr4100:
 386 *vr5000:
 387 *r3900:
 388 {
 389   do_and (SD_, RS, RT, RD);
 390 }
 391
 392
 393
 394 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 395 "and r<RT>, r<RS>, <IMMEDIATE>"
 396 *mipsI:
 397 *mipsII:
 398 *mipsIII:
 399 *mipsIV:
 400 *mipsV:
 401 *vr4100:
 402 *vr5000:
 403 *r3900:
 404 {
 405   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 406   GPR[RT] = GPR[RS] & IMMEDIATE;
 407   TRACE_ALU_RESULT (GPR[RT]);
 408 }
 409
 410
 411
 412 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 413 "beq r<RS>, r<RT>, <OFFSET>"
 414 *mipsI:
 415 *mipsII:
 416 *mipsIII:
 417 *mipsIV:
 418 *mipsV:
 419 *vr4100:
 420 *vr5000:
 421 *r3900:
 422 {
 423   address_word offset = EXTEND16 (OFFSET) << 2;
 424   check_branch_bug ();
 425   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 426     {
 427       mark_branch_bug (NIA+offset);
 428       DELAY_SLOT (NIA + offset);
 429     }
 430 }
 431
 432
 433
 434 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 435 "beql r<RS>, r<RT>, <OFFSET>"
 436 *mipsII:
 437 *mipsIII:
 438 *mipsIV:
 439 *mipsV:
 440 *vr4100:
 441 *vr5000:
 442 *r3900:
 443 {
 444   address_word offset = EXTEND16 (OFFSET) << 2;
 445   check_branch_bug ();
 446   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 447     {
 448       mark_branch_bug (NIA+offset);
 449       DELAY_SLOT (NIA + offset);
 450     }
 451   else
 452     NULLIFY_NEXT_INSTRUCTION ();
 453 }
 454
 455
 456
 457 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 458 "bgez r<RS>, <OFFSET>"
 459 *mipsI:
 460 *mipsII:
 461 *mipsIII:
 462 *mipsIV:
 463 *mipsV:
 464 *vr4100:
 465 *vr5000:
 466 *r3900:
 467 {
 468   address_word offset = EXTEND16 (OFFSET) << 2;
 469   check_branch_bug ();
 470   if ((signed_word) GPR[RS] >= 0)
 471     {
 472       mark_branch_bug (NIA+offset);
 473       DELAY_SLOT (NIA + offset);
 474     }
 475 }
 476
 477
 478
 479 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 480 "bgezal r<RS>, <OFFSET>"
 481 *mipsI:
 482 *mipsII:
 483 *mipsIII:
 484 *mipsIV:
 485 *mipsV:
 486 *vr4100:
 487 *vr5000:
 488 *r3900:
 489 {
 490   address_word offset = EXTEND16 (OFFSET) << 2;
 491   check_branch_bug ();
 492   RA = (CIA + 8);
 493   if ((signed_word) GPR[RS] >= 0)
 494     {
 495       mark_branch_bug (NIA+offset);
 496       DELAY_SLOT (NIA + offset);
 497     }
 498 }
 499
 500
 501
 502 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 503 "bgezall r<RS>, <OFFSET>"
 504 *mipsII:
 505 *mipsIII:
 506 *mipsIV:
 507 *mipsV:
 508 *vr4100:
 509 *vr5000:
 510 *r3900:
 511 {
 512   address_word offset = EXTEND16 (OFFSET) << 2;
 513   check_branch_bug ();
 514   RA = (CIA + 8);
 515   /* NOTE: The branch occurs AFTER the next instruction has been
 516      executed */
 517   if ((signed_word) GPR[RS] >= 0)
 518     {
 519       mark_branch_bug (NIA+offset);
 520       DELAY_SLOT (NIA + offset);
 521     }
 522   else
 523     NULLIFY_NEXT_INSTRUCTION ();
 524 }
 525
 526
 527
 528 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 529 "bgezl r<RS>, <OFFSET>"
 530 *mipsII:
 531 *mipsIII:
 532 *mipsIV:
 533 *mipsV:
 534 *vr4100:
 535 *vr5000:
 536 *r3900:
 537 {
 538   address_word offset = EXTEND16 (OFFSET) << 2;
 539   check_branch_bug ();
 540   if ((signed_word) GPR[RS] >= 0)
 541     {
 542       mark_branch_bug (NIA+offset);
 543       DELAY_SLOT (NIA + offset);
 544     }
 545   else
 546     NULLIFY_NEXT_INSTRUCTION ();
 547 }
 548
 549
 550
 551 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 552 "bgtz r<RS>, <OFFSET>"
 553 *mipsI:
 554 *mipsII:
 555 *mipsIII:
 556 *mipsIV:
 557 *mipsV:
 558 *vr4100:
 559 *vr5000:
 560 *r3900:
 561 {
 562   address_word offset = EXTEND16 (OFFSET) << 2;
 563   check_branch_bug ();
 564   if ((signed_word) GPR[RS] > 0)
 565     {
 566       mark_branch_bug (NIA+offset);
 567       DELAY_SLOT (NIA + offset);
 568     }
 569 }
 570
 571
 572
 573 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 574 "bgtzl r<RS>, <OFFSET>"
 575 *mipsII:
 576 *mipsIII:
 577 *mipsIV:
 578 *mipsV:
 579 *vr4100:
 580 *vr5000:
 581 *r3900:
 582 {
 583   address_word offset = EXTEND16 (OFFSET) << 2;
 584   check_branch_bug ();
 585   /* NOTE: The branch occurs AFTER the next instruction has been
 586      executed */
 587   if ((signed_word) GPR[RS] > 0)
 588     {
 589       mark_branch_bug (NIA+offset);
 590       DELAY_SLOT (NIA + offset);
 591     }
 592   else
 593     NULLIFY_NEXT_INSTRUCTION ();
 594 }
 595
 596
 597
 598 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 599 "blez r<RS>, <OFFSET>"
 600 *mipsI:
 601 *mipsII:
 602 *mipsIII:
 603 *mipsIV:
 604 *mipsV:
 605 *vr4100:
 606 *vr5000:
 607 *r3900:
 608 {
 609   address_word offset = EXTEND16 (OFFSET) << 2;
 610   check_branch_bug ();
 611   /* NOTE: The branch occurs AFTER the next instruction has been
 612      executed */
 613   if ((signed_word) GPR[RS] <= 0)
 614     {
 615       mark_branch_bug (NIA+offset);
 616       DELAY_SLOT (NIA + offset);
 617     }
 618 }
 619
 620
 621
 622 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 623 "bgezl r<RS>, <OFFSET>"
 624 *mipsII:
 625 *mipsIII:
 626 *mipsIV:
 627 *mipsV:
 628 *vr4100:
 629 *vr5000:
 630 *r3900:
 631 {
 632   address_word offset = EXTEND16 (OFFSET) << 2;
 633   check_branch_bug ();
 634   if ((signed_word) GPR[RS] <= 0)
 635     {
 636       mark_branch_bug (NIA+offset);
 637       DELAY_SLOT (NIA + offset);
 638     }
 639   else
 640     NULLIFY_NEXT_INSTRUCTION ();
 641 }
 642
 643
 644
 645 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 646 "bltz r<RS>, <OFFSET>"
 647 *mipsI:
 648 *mipsII:
 649 *mipsIII:
 650 *mipsIV:
 651 *mipsV:
 652 *vr4100:
 653 *vr5000:
 654 *r3900:
 655 {
 656   address_word offset = EXTEND16 (OFFSET) << 2;
 657   check_branch_bug ();
 658   if ((signed_word) GPR[RS] < 0)
 659     {
 660       mark_branch_bug (NIA+offset);
 661       DELAY_SLOT (NIA + offset);
 662     }
 663 }
 664
 665
 666
 667 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 668 "bltzal r<RS>, <OFFSET>"
 669 *mipsI:
 670 *mipsII:
 671 *mipsIII:
 672 *mipsIV:
 673 *mipsV:
 674 *vr4100:
 675 *vr5000:
 676 *r3900:
 677 {
 678   address_word offset = EXTEND16 (OFFSET) << 2;
 679   check_branch_bug ();
 680   RA = (CIA + 8);
 681   /* NOTE: The branch occurs AFTER the next instruction has been
 682      executed */
 683   if ((signed_word) GPR[RS] < 0)
 684     {
 685       mark_branch_bug (NIA+offset);
 686       DELAY_SLOT (NIA + offset);
 687     }
 688 }
 689
 690
 691
 692 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 693 "bltzall r<RS>, <OFFSET>"
 694 *mipsII:
 695 *mipsIII:
 696 *mipsIV:
 697 *mipsV:
 698 *vr4100:
 699 *vr5000:
 700 *r3900:
 701 {
 702   address_word offset = EXTEND16 (OFFSET) << 2;
 703   check_branch_bug ();
 704   RA = (CIA + 8);
 705   if ((signed_word) GPR[RS] < 0)
 706     {
 707       mark_branch_bug (NIA+offset);
 708       DELAY_SLOT (NIA + offset);
 709     }
 710   else
 711     NULLIFY_NEXT_INSTRUCTION ();
 712 }
 713
 714
 715
 716 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 717 "bltzl r<RS>, <OFFSET>"
 718 *mipsII:
 719 *mipsIII:
 720 *mipsIV:
 721 *mipsV:
 722 *vr4100:
 723 *vr5000:
 724 *r3900:
 725 {
 726   address_word offset = EXTEND16 (OFFSET) << 2;
 727   check_branch_bug ();
 728   /* NOTE: The branch occurs AFTER the next instruction has been
 729      executed */
 730   if ((signed_word) GPR[RS] < 0)
 731     {
 732       mark_branch_bug (NIA+offset);
 733       DELAY_SLOT (NIA + offset);
 734     }
 735   else
 736     NULLIFY_NEXT_INSTRUCTION ();
 737 }
 738
 739
 740
 741 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 742 "bne r<RS>, r<RT>, <OFFSET>"
 743 *mipsI:
 744 *mipsII:
 745 *mipsIII:
 746 *mipsIV:
 747 *mipsV:
 748 *vr4100:
 749 *vr5000:
 750 *r3900:
 751 {
 752   address_word offset = EXTEND16 (OFFSET) << 2;
 753   check_branch_bug ();
 754   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 755     {
 756       mark_branch_bug (NIA+offset);
 757       DELAY_SLOT (NIA + offset);
 758     }
 759 }
 760
 761
 762
 763 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 764 "bnel r<RS>, r<RT>, <OFFSET>"
 765 *mipsII:
 766 *mipsIII:
 767 *mipsIV:
 768 *mipsV:
 769 *vr4100:
 770 *vr5000:
 771 *r3900:
 772 {
 773   address_word offset = EXTEND16 (OFFSET) << 2;
 774   check_branch_bug ();
 775   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 776     {
 777       mark_branch_bug (NIA+offset);
 778       DELAY_SLOT (NIA + offset);
 779     }
 780   else
 781     NULLIFY_NEXT_INSTRUCTION ();
 782 }
 783
 784
 785
 786 000000,20.CODE,001101:SPECIAL:32::BREAK
 787 "break <CODE>"
 788 *mipsI:
 789 *mipsII:
 790 *mipsIII:
 791 *mipsIV:
 792 *mipsV:
 793 *vr4100:
 794 *vr5000:
 795 *r3900:
 796 {
 797   /* Check for some break instruction which are reserved for use by the simulator.  */
 798   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 799   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 800       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 801     {
 802       sim_engine_halt (SD, CPU, NULL, cia,
 803                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 804     }
 805   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 806            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 807     {
 808       if (STATE & simDELAYSLOT)
 809         PC = cia - 4; /* reference the branch instruction */
 810       else
 811         PC = cia;
 812       SignalException(BreakPoint, instruction_0);
 813     }
 814
 815   else
 816     {
 817       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 818          the exception. */
 819       SignalException(BreakPoint, instruction_0);
 820     }
 821 }
 822
 823
 824
 825 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 826 "dadd r<RD>, r<RS>, r<RT>"
 827 *mipsIII:
 828 *mipsIV:
 829 *mipsV:
 830 *vr4100:
 831 *vr5000:
 832 {
 833   check_u64 (SD_, instruction_0);
 834   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 835   {
 836     ALU64_BEGIN (GPR[RS]);
 837     ALU64_ADD (GPR[RT]);
 838     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
 839   }
 840   TRACE_ALU_RESULT (GPR[RD]);
 841 }
 842
 843
 844
 845 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 846 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 847 *mipsIII:
 848 *mipsIV:
 849 *mipsV:
 850 *vr4100:
 851 *vr5000:
 852 {
 853   check_u64 (SD_, instruction_0);
 854   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 855   {
 856     ALU64_BEGIN (GPR[RS]);
 857     ALU64_ADD (EXTEND16 (IMMEDIATE));
 858     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
 859   }
 860   TRACE_ALU_RESULT (GPR[RT]);
 861 }
 862
 863
 864
 865 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
 866 {
 867   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 868   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
 869   TRACE_ALU_RESULT (GPR[rt]);
 870 }
 871
 872 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 873 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
 874 *mipsIII:
 875 *mipsIV:
 876 *mipsV:
 877 *vr4100:
 878 *vr5000:
 879 {
 880   check_u64 (SD_, instruction_0);
 881   do_daddiu (SD_, RS, RT, IMMEDIATE);
 882 }
 883
 884
 885
 886 :function:::void:do_daddu:int rs, int rt, int rd
 887 {
 888   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 889   GPR[rd] = GPR[rs] + GPR[rt];
 890   TRACE_ALU_RESULT (GPR[rd]);
 891 }
 892
 893 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 894 "daddu r<RD>, r<RS>, r<RT>"
 895 *mipsIII:
 896 *mipsIV:
 897 *mipsV:
 898 *vr4100:
 899 *vr5000:
 900 {
 901   check_u64 (SD_, instruction_0);
 902   do_daddu (SD_, RS, RT, RD);
 903 }
 904
 905
 906
 907 :function:::void:do_ddiv:int rs, int rt
 908 {
 909   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 910   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 911   {
 912     signed64 n = GPR[rs];
 913     signed64 d = GPR[rt];
 914     signed64 hi;
 915     signed64 lo;
 916     if (d == 0)
 917       {
 918         lo = SIGNED64 (0x8000000000000000);
 919         hi = 0;
 920       }
 921     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 922       {
 923         lo = SIGNED64 (0x8000000000000000);
 924         hi = 0;
 925       }
 926     else
 927       {
 928         lo = (n / d);
 929         hi = (n % d);
 930       }
 931     HI = hi;
 932     LO = lo;
 933   }
 934   TRACE_ALU_RESULT2 (HI, LO);
 935 }
 936
 937 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
 938 "ddiv r<RS>, r<RT>"
 939 *mipsIII:
 940 *mipsIV:
 941 *mipsV:
 942 *vr4100:
 943 *vr5000:
 944 {
 945   check_u64 (SD_, instruction_0);
 946   do_ddiv (SD_, RS, RT);
 947 }
 948
 949
 950
 951 :function:::void:do_ddivu:int rs, int rt
 952 {
 953   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 954   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 955   {
 956     unsigned64 n = GPR[rs];
 957     unsigned64 d = GPR[rt];
 958     unsigned64 hi;
 959     unsigned64 lo;
 960     if (d == 0)
 961       {
 962         lo = SIGNED64 (0x8000000000000000);
 963         hi = 0;
 964       }
 965     else
 966       {
 967         lo = (n / d);
 968         hi = (n % d);
 969       }
 970     HI = hi;
 971     LO = lo;
 972   }
 973   TRACE_ALU_RESULT2 (HI, LO);
 974 }
 975
 976 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 977 "ddivu r<RS>, r<RT>"
 978 *mipsIII:
 979 *mipsIV:
 980 *mipsV:
 981 *vr4100:
 982 *vr5000:
 983 {
 984   check_u64 (SD_, instruction_0);
 985   do_ddivu (SD_, RS, RT);
 986 }
 987
 988
 989
 990 :function:::void:do_div:int rs, int rt
 991 {
 992   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 993   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 994   {
 995     signed32 n = GPR[rs];
 996     signed32 d = GPR[rt];
 997     if (d == 0)
 998       {
 999         LO = EXTEND32 (0x80000000);
1000         HI = EXTEND32 (0);
1001       }
1002     else if (n == SIGNED32 (0x80000000) && d == -1)
1003       {
1004         LO = EXTEND32 (0x80000000);
1005         HI = EXTEND32 (0);
1006       }
1007     else
1008       {
1009         LO = EXTEND32 (n / d);
1010         HI = EXTEND32 (n % d);
1011       }
1012   }
1013   TRACE_ALU_RESULT2 (HI, LO);
1014 }
1015
1016 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1017 "div r<RS>, r<RT>"
1018 *mipsI:
1019 *mipsII:
1020 *mipsIII:
1021 *mipsIV:
1022 *mipsV:
1023 *vr4100:
1024 *vr5000:
1025 *r3900:
1026 {
1027   do_div (SD_, RS, RT);
1028 }
1029
1030
1031
1032 :function:::void:do_divu:int rs, int rt
1033 {
1034   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1035   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1036   {
1037     unsigned32 n = GPR[rs];
1038     unsigned32 d = GPR[rt];
1039     if (d == 0)
1040       {
1041         LO = EXTEND32 (0x80000000);
1042         HI = EXTEND32 (0);
1043       }
1044     else
1045       {
1046         LO = EXTEND32 (n / d);
1047         HI = EXTEND32 (n % d);
1048       }
1049   }
1050   TRACE_ALU_RESULT2 (HI, LO);
1051 }
1052
1053 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1054 "divu r<RS>, r<RT>"
1055 *mipsI:
1056 *mipsII:
1057 *mipsIII:
1058 *mipsIV:
1059 *mipsV:
1060 *vr4100:
1061 *vr5000:
1062 *r3900:
1063 {
1064   do_divu (SD_, RS, RT);
1065 }
1066
1067
1068
1069 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1070 {
1071   unsigned64 lo;
1072   unsigned64 hi;
1073   unsigned64 m00;
1074   unsigned64 m01;
1075   unsigned64 m10;
1076   unsigned64 m11;
1077   unsigned64 mid;
1078   int sign;
1079   unsigned64 op1 = GPR[rs];
1080   unsigned64 op2 = GPR[rt];
1081   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1082   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1083   /* make signed multiply unsigned */
1084   sign = 0;
1085   if (signed_p)
1086     {
1087       if (op1 < 0)
1088         {
1089           op1 = - op1;
1090           ++sign;
1091         }
1092       if (op2 < 0)
1093         {
1094           op2 = - op2;
1095           ++sign;
1096         }
1097     }
1098   /* multiply out the 4 sub products */
1099   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1100   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1101   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1102   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1103   /* add the products */
1104   mid = ((unsigned64) VH4_8 (m00)
1105          + (unsigned64) VL4_8 (m10)
1106          + (unsigned64) VL4_8 (m01));
1107   lo = U8_4 (mid, m00);
1108   hi = (m11
1109         + (unsigned64) VH4_8 (mid)
1110         + (unsigned64) VH4_8 (m01)
1111         + (unsigned64) VH4_8 (m10));
1112   /* fix the sign */
1113   if (sign & 1)
1114     {
1115       lo = -lo;
1116       if (lo == 0)
1117         hi = -hi;
1118       else
1119         hi = -hi - 1;
1120     }
1121   /* save the result HI/LO (and a gpr) */
1122   LO = lo;
1123   HI = hi;
1124   if (rd != 0)
1125     GPR[rd] = lo;
1126   TRACE_ALU_RESULT2 (HI, LO);
1127 }
1128
1129 :function:::void:do_dmult:int rs, int rt, int rd
1130 {
1131   do_dmultx (SD_, rs, rt, rd, 1);
1132 }
1133
1134 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1135 "dmult r<RS>, r<RT>"
1136 *mipsIII:
1137 *mipsIV:
1138 *mipsV:
1139 *vr4100:
1140 {
1141   check_u64 (SD_, instruction_0);
1142   do_dmult (SD_, RS, RT, 0);
1143 }
1144
1145 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1146 "dmult r<RS>, r<RT>":RD == 0
1147 "dmult r<RD>, r<RS>, r<RT>"
1148 *vr5000:
1149 {
1150   check_u64 (SD_, instruction_0);
1151   do_dmult (SD_, RS, RT, RD);
1152 }
1153
1154
1155
1156 :function:::void:do_dmultu:int rs, int rt, int rd
1157 {
1158   do_dmultx (SD_, rs, rt, rd, 0);
1159 }
1160
1161 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1162 "dmultu r<RS>, r<RT>"
1163 *mipsIII:
1164 *mipsIV:
1165 *mipsV:
1166 *vr4100:
1167 {
1168   check_u64 (SD_, instruction_0);
1169   do_dmultu (SD_, RS, RT, 0);
1170 }
1171
1172 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1173 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1174 "dmultu r<RS>, r<RT>"
1175 *vr5000:
1176 {
1177   check_u64 (SD_, instruction_0);
1178   do_dmultu (SD_, RS, RT, RD);
1179 }
1180
1181 :function:::void:do_dsll:int rt, int rd, int shift
1182 {
1183   TRACE_ALU_INPUT2 (GPR[rt], shift);
1184   GPR[rd] = GPR[rt] << shift;
1185   TRACE_ALU_RESULT (GPR[rd]);
1186 }
1187
1188 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1189 "dsll r<RD>, r<RT>, <SHIFT>"
1190 *mipsIII:
1191 *mipsIV:
1192 *mipsV:
1193 *vr4100:
1194 *vr5000:
1195 {
1196   check_u64 (SD_, instruction_0);
1197   do_dsll (SD_, RT, RD, SHIFT);
1198 }
1199
1200
1201 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1202 "dsll32 r<RD>, r<RT>, <SHIFT>"
1203 *mipsIII:
1204 *mipsIV:
1205 *mipsV:
1206 *vr4100:
1207 *vr5000:
1208 {
1209   int s = 32 + SHIFT;
1210   check_u64 (SD_, instruction_0);
1211   TRACE_ALU_INPUT2 (GPR[RT], s);
1212   GPR[RD] = GPR[RT] << s;
1213   TRACE_ALU_RESULT (GPR[RD]);
1214 }
1215
1216 :function:::void:do_dsllv:int rs, int rt, int rd
1217 {
1218   int s = MASKED64 (GPR[rs], 5, 0);
1219   TRACE_ALU_INPUT2 (GPR[rt], s);
1220   GPR[rd] = GPR[rt] << s;
1221   TRACE_ALU_RESULT (GPR[rd]);
1222 }
1223
1224 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1225 "dsllv r<RD>, r<RT>, r<RS>"
1226 *mipsIII:
1227 *mipsIV:
1228 *mipsV:
1229 *vr4100:
1230 *vr5000:
1231 {
1232   check_u64 (SD_, instruction_0);
1233   do_dsllv (SD_, RS, RT, RD);
1234 }
1235
1236 :function:::void:do_dsra:int rt, int rd, int shift
1237 {
1238   TRACE_ALU_INPUT2 (GPR[rt], shift);
1239   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1240   TRACE_ALU_RESULT (GPR[rd]);
1241 }
1242
1243
1244 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1245 "dsra r<RD>, r<RT>, <SHIFT>"
1246 *mipsIII:
1247 *mipsIV:
1248 *mipsV:
1249 *vr4100:
1250 *vr5000:
1251 {
1252   check_u64 (SD_, instruction_0);
1253   do_dsra (SD_, RT, RD, SHIFT);
1254 }
1255
1256
1257 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1258 "dsra32 r<RD>, r<RT>, <SHIFT>"
1259 *mipsIII:
1260 *mipsIV:
1261 *mipsV:
1262 *vr4100:
1263 *vr5000:
1264 {
1265   int s = 32 + SHIFT;
1266   check_u64 (SD_, instruction_0);
1267   TRACE_ALU_INPUT2 (GPR[RT], s);
1268   GPR[RD] = ((signed64) GPR[RT]) >> s;
1269   TRACE_ALU_RESULT (GPR[RD]);
1270 }
1271
1272
1273 :function:::void:do_dsrav:int rs, int rt, int rd
1274 {
1275   int s = MASKED64 (GPR[rs], 5, 0);
1276   TRACE_ALU_INPUT2 (GPR[rt], s);
1277   GPR[rd] = ((signed64) GPR[rt]) >> s;
1278   TRACE_ALU_RESULT (GPR[rd]);
1279 }
1280
1281 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1282 "dsrav r<RD>, r<RT>, r<RS>"
1283 *mipsIII:
1284 *mipsIV:
1285 *mipsV:
1286 *vr4100:
1287 *vr5000:
1288 {
1289   check_u64 (SD_, instruction_0);
1290   do_dsrav (SD_, RS, RT, RD);
1291 }
1292
1293 :function:::void:do_dsrl:int rt, int rd, int shift
1294 {
1295   TRACE_ALU_INPUT2 (GPR[rt], shift);
1296   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1297   TRACE_ALU_RESULT (GPR[rd]);
1298 }
1299
1300
1301 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1302 "dsrl r<RD>, r<RT>, <SHIFT>"
1303 *mipsIII:
1304 *mipsIV:
1305 *mipsV:
1306 *vr4100:
1307 *vr5000:
1308 {
1309   check_u64 (SD_, instruction_0);
1310   do_dsrl (SD_, RT, RD, SHIFT);
1311 }
1312
1313
1314 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1315 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1316 *mipsIII:
1317 *mipsIV:
1318 *mipsV:
1319 *vr4100:
1320 *vr5000:
1321 {
1322   int s = 32 + SHIFT;
1323   check_u64 (SD_, instruction_0);
1324   TRACE_ALU_INPUT2 (GPR[RT], s);
1325   GPR[RD] = (unsigned64) GPR[RT] >> s;
1326   TRACE_ALU_RESULT (GPR[RD]);
1327 }
1328
1329
1330 :function:::void:do_dsrlv:int rs, int rt, int rd
1331 {
1332   int s = MASKED64 (GPR[rs], 5, 0);
1333   TRACE_ALU_INPUT2 (GPR[rt], s);
1334   GPR[rd] = (unsigned64) GPR[rt] >> s;
1335   TRACE_ALU_RESULT (GPR[rd]);
1336 }
1337
1338
1339
1340 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1341 "dsrlv r<RD>, r<RT>, r<RS>"
1342 *mipsIII:
1343 *mipsIV:
1344 *mipsV:
1345 *vr4100:
1346 *vr5000:
1347 {
1348   check_u64 (SD_, instruction_0);
1349   do_dsrlv (SD_, RS, RT, RD);
1350 }
1351
1352
1353 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1354 "dsub r<RD>, r<RS>, r<RT>"
1355 *mipsIII:
1356 *mipsIV:
1357 *mipsV:
1358 *vr4100:
1359 *vr5000:
1360 {
1361   check_u64 (SD_, instruction_0);
1362   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1363   {
1364     ALU64_BEGIN (GPR[RS]);
1365     ALU64_SUB (GPR[RT]);
1366     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1367   }
1368   TRACE_ALU_RESULT (GPR[RD]);
1369 }
1370
1371
1372 :function:::void:do_dsubu:int rs, int rt, int rd
1373 {
1374   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1375   GPR[rd] = GPR[rs] - GPR[rt];
1376   TRACE_ALU_RESULT (GPR[rd]);
1377 }
1378
1379 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1380 "dsubu r<RD>, r<RS>, r<RT>"
1381 *mipsIII:
1382 *mipsIV:
1383 *mipsV:
1384 *vr4100:
1385 *vr5000:
1386 {
1387   check_u64 (SD_, instruction_0);
1388   do_dsubu (SD_, RS, RT, RD);
1389 }
1390
1391
1392 000010,26.INSTR_INDEX:NORMAL:32::J
1393 "j <INSTR_INDEX>"
1394 *mipsI:
1395 *mipsII:
1396 *mipsIII:
1397 *mipsIV:
1398 *mipsV:
1399 *vr4100:
1400 *vr5000:
1401 *r3900:
1402 {
1403   /* NOTE: The region used is that of the delay slot NIA and NOT the
1404      current instruction */
1405   address_word region = (NIA & MASK (63, 28));
1406   DELAY_SLOT (region | (INSTR_INDEX << 2));
1407 }
1408
1409
1410 000011,26.INSTR_INDEX:NORMAL:32::JAL
1411 "jal <INSTR_INDEX>"
1412 *mipsI:
1413 *mipsII:
1414 *mipsIII:
1415 *mipsIV:
1416 *mipsV:
1417 *vr4100:
1418 *vr5000:
1419 *r3900:
1420 {
1421   /* NOTE: The region used is that of the delay slot and NOT the
1422      current instruction */
1423   address_word region = (NIA & MASK (63, 28));
1424   GPR[31] = CIA + 8;
1425   DELAY_SLOT (region | (INSTR_INDEX << 2));
1426 }
1427
1428 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1429 "jalr r<RS>":RD == 31
1430 "jalr r<RD>, r<RS>"
1431 *mipsI:
1432 *mipsII:
1433 *mipsIII:
1434 *mipsIV:
1435 *mipsV:
1436 *vr4100:
1437 *vr5000:
1438 *r3900:
1439 {
1440   address_word temp = GPR[RS];
1441   GPR[RD] = CIA + 8;
1442   DELAY_SLOT (temp);
1443 }
1444
1445
1446 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1447 "jr r<RS>"
1448 *mipsI:
1449 *mipsII:
1450 *mipsIII:
1451 *mipsIV:
1452 *mipsV:
1453 *vr4100:
1454 *vr5000:
1455 *r3900:
1456 {
1457   DELAY_SLOT (GPR[RS]);
1458 }
1459
1460
1461 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1462 {
1463   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1464   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1465   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1466   unsigned int byte;
1467   address_word paddr;
1468   int uncached;
1469   unsigned64 memval;
1470   address_word vaddr;
1471
1472   vaddr = base + offset;
1473   if ((vaddr & access) != 0)
1474     {
1475       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1476     }
1477   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1478   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1479   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1480   byte = ((vaddr & mask) ^ bigendiancpu);
1481   return (memval >> (8 * byte));
1482 }
1483
1484 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1485 {
1486   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1487   address_word reverseendian = (ReverseEndian ? -1 : 0);
1488   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1489   unsigned int byte;
1490   unsigned int word;
1491   address_word paddr;
1492   int uncached;
1493   unsigned64 memval;
1494   address_word vaddr;
1495   int nr_lhs_bits;
1496   int nr_rhs_bits;
1497   unsigned_word lhs_mask;
1498   unsigned_word temp;
1499
1500   vaddr = base + offset;
1501   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1502   paddr = (paddr ^ (reverseendian & mask));
1503   if (BigEndianMem == 0)
1504     paddr = paddr & ~access;
1505
1506   /* compute where within the word/mem we are */
1507   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1508   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1509   nr_lhs_bits = 8 * byte + 8;
1510   nr_rhs_bits = 8 * access - 8 * byte;
1511   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1512
1513   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1514            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1515            (long) ((unsigned64) paddr >> 32), (long) paddr,
1516            word, byte, nr_lhs_bits, nr_rhs_bits); */
1517
1518   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1519   if (word == 0)
1520     {
1521       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1522       temp = (memval << nr_rhs_bits);
1523     }
1524   else
1525     {
1526       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1527       temp = (memval >> nr_lhs_bits);
1528     }
1529   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1530   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1531
1532   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1533            (long) ((unsigned64) memval >> 32), (long) memval,
1534            (long) ((unsigned64) temp >> 32), (long) temp,
1535            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1536            (long) (rt >> 32), (long) rt); */
1537   return rt;
1538 }
1539
1540 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1541 {
1542   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1543   address_word reverseendian = (ReverseEndian ? -1 : 0);
1544   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1545   unsigned int byte;
1546   address_word paddr;
1547   int uncached;
1548   unsigned64 memval;
1549   address_word vaddr;
1550
1551   vaddr = base + offset;
1552   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1553   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1554   paddr = (paddr ^ (reverseendian & mask));
1555   if (BigEndianMem != 0)
1556     paddr = paddr & ~access;
1557   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1558   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1559   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1560   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1561      (long) paddr, byte, (long) paddr, (long) memval); */
1562   {
1563     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1564     rt &= ~screen;
1565     rt |= (memval >> (8 * byte)) & screen;
1566   }
1567   return rt;
1568 }
1569
1570
1571 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1572 "lb r<RT>, <OFFSET>(r<BASE>)"
1573 *mipsI:
1574 *mipsII:
1575 *mipsIII:
1576 *mipsIV:
1577 *mipsV:
1578 *vr4100:
1579 *vr5000:
1580 *r3900:
1581 {
1582   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1583 }
1584
1585
1586 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1587 "lbu r<RT>, <OFFSET>(r<BASE>)"
1588 *mipsI:
1589 *mipsII:
1590 *mipsIII:
1591 *mipsIV:
1592 *mipsV:
1593 *vr4100:
1594 *vr5000:
1595 *r3900:
1596 {
1597   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1598 }
1599
1600
1601 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1602 "ld r<RT>, <OFFSET>(r<BASE>)"
1603 *mipsIII:
1604 *mipsIV:
1605 *mipsV:
1606 *vr4100:
1607 *vr5000:
1608 {
1609   check_u64 (SD_, instruction_0);
1610   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1611 }
1612
1613
1614 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1615 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1616 *mipsII:
1617 *mipsIII:
1618 *mipsIV:
1619 *mipsV:
1620 *vr4100:
1621 *vr5000:
1622 *r3900:
1623 {
1624   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1625 }
1626
1627
1628
1629
1630 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1631 "ldl r<RT>, <OFFSET>(r<BASE>)"
1632 *mipsIII:
1633 *mipsIV:
1634 *mipsV:
1635 *vr4100:
1636 *vr5000:
1637 {
1638   check_u64 (SD_, instruction_0);
1639   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1640 }
1641
1642
1643 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1644 "ldr r<RT>, <OFFSET>(r<BASE>)"
1645 *mipsIII:
1646 *mipsIV:
1647 *mipsV:
1648 *vr4100:
1649 *vr5000:
1650 {
1651   check_u64 (SD_, instruction_0);
1652   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1653 }
1654
1655
1656 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1657 "lh r<RT>, <OFFSET>(r<BASE>)"
1658 *mipsI:
1659 *mipsII:
1660 *mipsIII:
1661 *mipsIV:
1662 *mipsV:
1663 *vr4100:
1664 *vr5000:
1665 *r3900:
1666 {
1667   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1668 }
1669
1670
1671 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1672 "lhu r<RT>, <OFFSET>(r<BASE>)"
1673 *mipsI:
1674 *mipsII:
1675 *mipsIII:
1676 *mipsIV:
1677 *mipsV:
1678 *vr4100:
1679 *vr5000:
1680 *r3900:
1681 {
1682   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1683 }
1684
1685
1686 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1687 "ll r<RT>, <OFFSET>(r<BASE>)"
1688 *mipsII:
1689 *mipsIII:
1690 *mipsIV:
1691 *mipsV:
1692 *vr4100:
1693 *vr5000:
1694 {
1695   unsigned32 instruction = instruction_0;
1696   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1697   int destreg = ((instruction >> 16) & 0x0000001F);
1698   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1699   {
1700     address_word vaddr = ((unsigned64)op1 + offset);
1701     address_word paddr;
1702     int uncached;
1703     if ((vaddr & 3) != 0)
1704       {
1705         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1706       }
1707     else
1708       {
1709         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1710           {
1711             unsigned64 memval = 0;
1712             unsigned64 memval1 = 0;
1713             unsigned64 mask = 0x7;
1714             unsigned int shift = 2;
1715             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1716             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1717             unsigned int byte;
1718             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1719             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1720             byte = ((vaddr & mask) ^ (bigend << shift));
1721             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1722             LLBIT = 1;
1723           }
1724       }
1725   }
1726 }
1727
1728
1729 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1730 "lld r<RT>, <OFFSET>(r<BASE>)"
1731 *mipsIII:
1732 *mipsIV:
1733 *mipsV:
1734 *vr4100:
1735 *vr5000:
1736 {
1737   unsigned32 instruction = instruction_0;
1738   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1739   int destreg = ((instruction >> 16) & 0x0000001F);
1740   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1741   check_u64 (SD_, instruction_0);
1742   {
1743     address_word vaddr = ((unsigned64)op1 + offset);
1744     address_word paddr;
1745     int uncached;
1746     if ((vaddr & 7) != 0)
1747       {
1748         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1749       }
1750     else
1751       {
1752         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1753           {
1754             unsigned64 memval = 0;
1755             unsigned64 memval1 = 0;
1756             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1757             GPR[destreg] = memval;
1758             LLBIT = 1;
1759           }
1760       }
1761   }
1762 }
1763
1764
1765 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1766 "lui r<RT>, <IMMEDIATE>"
1767 *mipsI:
1768 *mipsII:
1769 *mipsIII:
1770 *mipsIV:
1771 *mipsV:
1772 *vr4100:
1773 *vr5000:
1774 *r3900:
1775 {
1776   TRACE_ALU_INPUT1 (IMMEDIATE);
1777   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1778   TRACE_ALU_RESULT (GPR[RT]);
1779 }
1780
1781
1782 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1783 "lw r<RT>, <OFFSET>(r<BASE>)"
1784 *mipsI:
1785 *mipsII:
1786 *mipsIII:
1787 *mipsIV:
1788 *mipsV:
1789 *vr4100:
1790 *vr5000:
1791 *r3900:
1792 {
1793   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1794 }
1795
1796
1797 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1798 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1799 *mipsI:
1800 *mipsII:
1801 *mipsIII:
1802 *mipsIV:
1803 *mipsV:
1804 *vr4100:
1805 *vr5000:
1806 *r3900:
1807 {
1808   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1809 }
1810
1811
1812 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1813 "lwl r<RT>, <OFFSET>(r<BASE>)"
1814 *mipsI:
1815 *mipsII:
1816 *mipsIII:
1817 *mipsIV:
1818 *mipsV:
1819 *vr4100:
1820 *vr5000:
1821 *r3900:
1822 {
1823   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1824 }
1825
1826
1827 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1828 "lwr r<RT>, <OFFSET>(r<BASE>)"
1829 *mipsI:
1830 *mipsII:
1831 *mipsIII:
1832 *mipsIV:
1833 *mipsV:
1834 *vr4100:
1835 *vr5000:
1836 *r3900:
1837 {
1838   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1839 }
1840
1841
1842 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
1843 "lwu r<RT>, <OFFSET>(r<BASE>)"
1844 *mipsIII:
1845 *mipsIV:
1846 *mipsV:
1847 *vr4100:
1848 *vr5000:
1849 {
1850   check_u64 (SD_, instruction_0);
1851   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1852 }
1853
1854
1855 :function:::void:do_mfhi:int rd
1856 {
1857   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1858   TRACE_ALU_INPUT1 (HI);
1859   GPR[rd] = HI;
1860   TRACE_ALU_RESULT (GPR[rd]);
1861 }
1862
1863 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1864 "mfhi r<RD>"
1865 *mipsI:
1866 *mipsII:
1867 *mipsIII:
1868 *mipsIV:
1869 *mipsV:
1870 *vr4100:
1871 *vr5000:
1872 *r3900:
1873 {
1874   do_mfhi (SD_, RD);
1875 }
1876
1877
1878
1879 :function:::void:do_mflo:int rd
1880 {
1881   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1882   TRACE_ALU_INPUT1 (LO);
1883   GPR[rd] = LO;
1884   TRACE_ALU_RESULT (GPR[rd]);
1885 }
1886
1887 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1888 "mflo r<RD>"
1889 *mipsI:
1890 *mipsII:
1891 *mipsIII:
1892 *mipsIV:
1893 *mipsV:
1894 *vr4100:
1895 *vr5000:
1896 *r3900:
1897 {
1898   do_mflo (SD_, RD);
1899 }
1900
1901
1902
1903 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
1904 "movn r<RD>, r<RS>, r<RT>"
1905 *mipsIV:
1906 *mipsV:
1907 *vr5000:
1908 {
1909   if (GPR[RT] != 0)
1910     GPR[RD] = GPR[RS];
1911 }
1912
1913
1914
1915 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
1916 "movz r<RD>, r<RS>, r<RT>"
1917 *mipsIV:
1918 *mipsV:
1919 *vr5000:
1920 {
1921   if (GPR[RT] == 0)
1922     GPR[RD] = GPR[RS];
1923 }
1924
1925
1926
1927 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1928 "mthi r<RS>"
1929 *mipsI:
1930 *mipsII:
1931 *mipsIII:
1932 *mipsIV:
1933 *mipsV:
1934 *vr4100:
1935 *vr5000:
1936 *r3900:
1937 {
1938   check_mt_hilo (SD_, HIHISTORY);
1939   HI = GPR[RS];
1940 }
1941
1942
1943
1944 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
1945 "mtlo r<RS>"
1946 *mipsI:
1947 *mipsII:
1948 *mipsIII:
1949 *mipsIV:
1950 *mipsV:
1951 *vr4100:
1952 *vr5000:
1953 *r3900:
1954 {
1955   check_mt_hilo (SD_, LOHISTORY);
1956   LO = GPR[RS];
1957 }
1958
1959
1960
1961 :function:::void:do_mult:int rs, int rt, int rd
1962 {
1963   signed64 prod;
1964   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1965   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1966   prod = (((signed64)(signed32) GPR[rs])
1967           * ((signed64)(signed32) GPR[rt]));
1968   LO = EXTEND32 (VL4_8 (prod));
1969   HI = EXTEND32 (VH4_8 (prod));
1970   if (rd != 0)
1971     GPR[rd] = LO;
1972   TRACE_ALU_RESULT2 (HI, LO);
1973 }
1974
1975 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
1976 "mult r<RS>, r<RT>"
1977 *mipsI:
1978 *mipsII:
1979 *mipsIII:
1980 *mipsIV:
1981 *mipsV:
1982 *vr4100:
1983 {
1984   do_mult (SD_, RS, RT, 0);
1985 }
1986
1987
1988 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
1989 "mult r<RS>, r<RT>":RD == 0
1990 "mult r<RD>, r<RS>, r<RT>"
1991 *vr5000:
1992 *r3900:
1993 {
1994   do_mult (SD_, RS, RT, RD);
1995 }
1996
1997
1998 :function:::void:do_multu:int rs, int rt, int rd
1999 {
2000   unsigned64 prod;
2001   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2002   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2003   prod = (((unsigned64)(unsigned32) GPR[rs])
2004           * ((unsigned64)(unsigned32) GPR[rt]));
2005   LO = EXTEND32 (VL4_8 (prod));
2006   HI = EXTEND32 (VH4_8 (prod));
2007   if (rd != 0)
2008     GPR[rd] = LO;
2009   TRACE_ALU_RESULT2 (HI, LO);
2010 }
2011
2012 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2013 "multu r<RS>, r<RT>"
2014 *mipsI:
2015 *mipsII:
2016 *mipsIII:
2017 *mipsIV:
2018 *mipsV:
2019 *vr4100:
2020 {
2021   do_multu (SD_, RS, RT, 0);
2022 }
2023
2024 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2025 "multu r<RS>, r<RT>":RD == 0
2026 "multu r<RD>, r<RS>, r<RT>"
2027 *vr5000:
2028 *r3900:
2029 {
2030   do_multu (SD_, RS, RT, RD);
2031 }
2032
2033
2034 :function:::void:do_nor:int rs, int rt, int rd
2035 {
2036   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2037   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2038   TRACE_ALU_RESULT (GPR[rd]);
2039 }
2040
2041 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2042 "nor r<RD>, r<RS>, r<RT>"
2043 *mipsI:
2044 *mipsII:
2045 *mipsIII:
2046 *mipsIV:
2047 *mipsV:
2048 *vr4100:
2049 *vr5000:
2050 *r3900:
2051 {
2052   do_nor (SD_, RS, RT, RD);
2053 }
2054
2055
2056 :function:::void:do_or:int rs, int rt, int rd
2057 {
2058   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2059   GPR[rd] = (GPR[rs] | GPR[rt]);
2060   TRACE_ALU_RESULT (GPR[rd]);
2061 }
2062
2063 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2064 "or r<RD>, r<RS>, r<RT>"
2065 *mipsI:
2066 *mipsII:
2067 *mipsIII:
2068 *mipsIV:
2069 *mipsV:
2070 *vr4100:
2071 *vr5000:
2072 *r3900:
2073 {
2074   do_or (SD_, RS, RT, RD);
2075 }
2076
2077
2078
2079 :function:::void:do_ori:int rs, int rt, unsigned immediate
2080 {
2081   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2082   GPR[rt] = (GPR[rs] | immediate);
2083   TRACE_ALU_RESULT (GPR[rt]);
2084 }
2085
2086 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2087 "ori r<RT>, r<RS>, <IMMEDIATE>"
2088 *mipsI:
2089 *mipsII:
2090 *mipsIII:
2091 *mipsIV:
2092 *mipsV:
2093 *vr4100:
2094 *vr5000:
2095 *r3900:
2096 {
2097   do_ori (SD_, RS, RT, IMMEDIATE);
2098 }
2099
2100
2101 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2102 "pref <HINT>, <OFFSET>(r<BASE>)"
2103 *mipsIV:
2104 *mipsV:
2105 *vr5000:
2106 {
2107   unsigned32 instruction = instruction_0;
2108   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2109   int hint = ((instruction >> 16) & 0x0000001F);
2110   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2111   {
2112     address_word vaddr = ((unsigned64)op1 + offset);
2113     address_word paddr;
2114     int uncached;
2115     {
2116       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2117         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2118     }
2119   }
2120 }
2121
2122
2123 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2124 {
2125   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2126   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2127   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2128   unsigned int byte;
2129   address_word paddr;
2130   int uncached;
2131   unsigned64 memval;
2132   address_word vaddr;
2133
2134   vaddr = base + offset;
2135   if ((vaddr & access) != 0)
2136     {
2137       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2138     }
2139   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2140   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2141   byte = ((vaddr & mask) ^ bigendiancpu);
2142   memval = (word << (8 * byte));
2143   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2144 }
2145
2146 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2147 {
2148   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2149   address_word reverseendian = (ReverseEndian ? -1 : 0);
2150   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2151   unsigned int byte;
2152   unsigned int word;
2153   address_word paddr;
2154   int uncached;
2155   unsigned64 memval;
2156   address_word vaddr;
2157   int nr_lhs_bits;
2158   int nr_rhs_bits;
2159
2160   vaddr = base + offset;
2161   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2162   paddr = (paddr ^ (reverseendian & mask));
2163   if (BigEndianMem == 0)
2164     paddr = paddr & ~access;
2165
2166   /* compute where within the word/mem we are */
2167   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2168   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2169   nr_lhs_bits = 8 * byte + 8;
2170   nr_rhs_bits = 8 * access - 8 * byte;
2171   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2172   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2173            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2174            (long) ((unsigned64) paddr >> 32), (long) paddr,
2175            word, byte, nr_lhs_bits, nr_rhs_bits); */
2176
2177   if (word == 0)
2178     {
2179       memval = (rt >> nr_rhs_bits);
2180     }
2181   else
2182     {
2183       memval = (rt << nr_lhs_bits);
2184     }
2185   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2186            (long) ((unsigned64) rt >> 32), (long) rt,
2187            (long) ((unsigned64) memval >> 32), (long) memval); */
2188   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2189 }
2190
2191 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2192 {
2193   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2194   address_word reverseendian = (ReverseEndian ? -1 : 0);
2195   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2196   unsigned int byte;
2197   address_word paddr;
2198   int uncached;
2199   unsigned64 memval;
2200   address_word vaddr;
2201
2202   vaddr = base + offset;
2203   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2204   paddr = (paddr ^ (reverseendian & mask));
2205   if (BigEndianMem != 0)
2206     paddr &= ~access;
2207   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2208   memval = (rt << (byte * 8));
2209   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2210 }
2211
2212
2213 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2214 "sb r<RT>, <OFFSET>(r<BASE>)"
2215 *mipsI:
2216 *mipsII:
2217 *mipsIII:
2218 *mipsIV:
2219 *mipsV:
2220 *vr4100:
2221 *vr5000:
2222 *r3900:
2223 {
2224   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2225 }
2226
2227
2228 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2229 "sc r<RT>, <OFFSET>(r<BASE>)"
2230 *mipsII:
2231 *mipsIII:
2232 *mipsIV:
2233 *mipsV:
2234 *vr4100:
2235 *vr5000:
2236 {
2237   unsigned32 instruction = instruction_0;
2238   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2239   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2240   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2241   {
2242     address_word vaddr = ((unsigned64)op1 + offset);
2243     address_word paddr;
2244     int uncached;
2245     if ((vaddr & 3) != 0)
2246       {
2247         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2248       }
2249     else
2250       {
2251         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2252           {
2253             unsigned64 memval = 0;
2254             unsigned64 memval1 = 0;
2255             unsigned64 mask = 0x7;
2256             unsigned int byte;
2257             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2258             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2259             memval = ((unsigned64) op2 << (8 * byte));
2260             if (LLBIT)
2261               {
2262                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2263               }
2264             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2265           }
2266       }
2267   }
2268 }
2269
2270
2271 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2272 "scd r<RT>, <OFFSET>(r<BASE>)"
2273 *mipsIII:
2274 *mipsIV:
2275 *mipsV:
2276 *vr4100:
2277 *vr5000:
2278 {
2279   unsigned32 instruction = instruction_0;
2280   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2281   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2282   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2283   check_u64 (SD_, instruction_0);
2284   {
2285     address_word vaddr = ((unsigned64)op1 + offset);
2286     address_word paddr;
2287     int uncached;
2288     if ((vaddr & 7) != 0)
2289       {
2290         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2291       }
2292     else
2293       {
2294         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2295           {
2296             unsigned64 memval = 0;
2297             unsigned64 memval1 = 0;
2298             memval = op2;
2299             if (LLBIT)
2300               {
2301                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2302               }
2303             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2304           }
2305       }
2306   }
2307 }
2308
2309
2310 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2311 "sd r<RT>, <OFFSET>(r<BASE>)"
2312 *mipsIII:
2313 *mipsIV:
2314 *mipsV:
2315 *vr4100:
2316 *vr5000:
2317 {
2318   check_u64 (SD_, instruction_0);
2319   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2320 }
2321
2322
2323 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2324 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2325 *mipsII:
2326 *mipsIII:
2327 *mipsIV:
2328 *mipsV:
2329 *vr4100:
2330 *vr5000:
2331 {
2332   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2333 }
2334
2335
2336 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2337 "sdl r<RT>, <OFFSET>(r<BASE>)"
2338 *mipsIII:
2339 *mipsIV:
2340 *mipsV:
2341 *vr4100:
2342 *vr5000:
2343 {
2344   check_u64 (SD_, instruction_0);
2345   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2346 }
2347
2348
2349 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2350 "sdr r<RT>, <OFFSET>(r<BASE>)"
2351 *mipsIII:
2352 *mipsIV:
2353 *mipsV:
2354 *vr4100:
2355 *vr5000:
2356 {
2357   check_u64 (SD_, instruction_0);
2358   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2359 }
2360
2361
2362 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2363 "sh r<RT>, <OFFSET>(r<BASE>)"
2364 *mipsI:
2365 *mipsII:
2366 *mipsIII:
2367 *mipsIV:
2368 *mipsV:
2369 *vr4100:
2370 *vr5000:
2371 *r3900:
2372 {
2373   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2374 }
2375
2376
2377 :function:::void:do_sll:int rt, int rd, int shift
2378 {
2379   unsigned32 temp = (GPR[rt] << shift);
2380   TRACE_ALU_INPUT2 (GPR[rt], shift);
2381   GPR[rd] = EXTEND32 (temp);
2382   TRACE_ALU_RESULT (GPR[rd]);
2383 }
2384
2385 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2386 "nop":RD == 0 && RT == 0 && SHIFT == 0
2387 "sll r<RD>, r<RT>, <SHIFT>"
2388 *mipsI:
2389 *mipsII:
2390 *mipsIII:
2391 *mipsIV:
2392 *mipsV:
2393 *vr4100:
2394 *vr5000:
2395 *r3900:
2396 {
2397   /* Skip shift for NOP, so that there won't be lots of extraneous
2398      trace output.  */
2399   if (RD != 0 || RT != 0 || SHIFT != 0)
2400     do_sll (SD_, RT, RD, SHIFT);
2401 }
2402
2403
2404 :function:::void:do_sllv:int rs, int rt, int rd
2405 {
2406   int s = MASKED (GPR[rs], 4, 0);
2407   unsigned32 temp = (GPR[rt] << s);
2408   TRACE_ALU_INPUT2 (GPR[rt], s);
2409   GPR[rd] = EXTEND32 (temp);
2410   TRACE_ALU_RESULT (GPR[rd]);
2411 }
2412
2413 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2414 "sllv r<RD>, r<RT>, r<RS>"
2415 *mipsI:
2416 *mipsII:
2417 *mipsIII:
2418 *mipsIV:
2419 *mipsV:
2420 *vr4100:
2421 *vr5000:
2422 *r3900:
2423 {
2424   do_sllv (SD_, RS, RT, RD);
2425 }
2426
2427
2428 :function:::void:do_slt:int rs, int rt, int rd
2429 {
2430   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2431   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2432   TRACE_ALU_RESULT (GPR[rd]);
2433 }
2434
2435 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2436 "slt r<RD>, r<RS>, r<RT>"
2437 *mipsI:
2438 *mipsII:
2439 *mipsIII:
2440 *mipsIV:
2441 *mipsV:
2442 *vr4100:
2443 *vr5000:
2444 *r3900:
2445 {
2446   do_slt (SD_, RS, RT, RD);
2447 }
2448
2449
2450 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2451 {
2452   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2453   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2454   TRACE_ALU_RESULT (GPR[rt]);
2455 }
2456
2457 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2458 "slti r<RT>, r<RS>, <IMMEDIATE>"
2459 *mipsI:
2460 *mipsII:
2461 *mipsIII:
2462 *mipsIV:
2463 *mipsV:
2464 *vr4100:
2465 *vr5000:
2466 *r3900:
2467 {
2468   do_slti (SD_, RS, RT, IMMEDIATE);
2469 }
2470
2471
2472 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2473 {
2474   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2475   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2476   TRACE_ALU_RESULT (GPR[rt]);
2477 }
2478
2479 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2480 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2481 *mipsI:
2482 *mipsII:
2483 *mipsIII:
2484 *mipsIV:
2485 *mipsV:
2486 *vr4100:
2487 *vr5000:
2488 *r3900:
2489 {
2490   do_sltiu (SD_, RS, RT, IMMEDIATE);
2491 }
2492
2493
2494
2495 :function:::void:do_sltu:int rs, int rt, int rd
2496 {
2497   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2498   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2499   TRACE_ALU_RESULT (GPR[rd]);
2500 }
2501
2502 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2503 "sltu r<RD>, r<RS>, r<RT>"
2504 *mipsI:
2505 *mipsII:
2506 *mipsIII:
2507 *mipsIV:
2508 *mipsV:
2509 *vr4100:
2510 *vr5000:
2511 *r3900:
2512 {
2513   do_sltu (SD_, RS, RT, RD);
2514 }
2515
2516
2517 :function:::void:do_sra:int rt, int rd, int shift
2518 {
2519   signed32 temp = (signed32) GPR[rt] >> shift;
2520   TRACE_ALU_INPUT2 (GPR[rt], shift);
2521   GPR[rd] = EXTEND32 (temp);
2522   TRACE_ALU_RESULT (GPR[rd]);
2523 }
2524
2525 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2526 "sra r<RD>, r<RT>, <SHIFT>"
2527 *mipsI:
2528 *mipsII:
2529 *mipsIII:
2530 *mipsIV:
2531 *mipsV:
2532 *vr4100:
2533 *vr5000:
2534 *r3900:
2535 {
2536   do_sra (SD_, RT, RD, SHIFT);
2537 }
2538
2539
2540
2541 :function:::void:do_srav:int rs, int rt, int rd
2542 {
2543   int s = MASKED (GPR[rs], 4, 0);
2544   signed32 temp = (signed32) GPR[rt] >> s;
2545   TRACE_ALU_INPUT2 (GPR[rt], s);
2546   GPR[rd] = EXTEND32 (temp);
2547   TRACE_ALU_RESULT (GPR[rd]);
2548 }
2549
2550 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
2551 "srav r<RD>, r<RT>, r<RS>"
2552 *mipsI:
2553 *mipsII:
2554 *mipsIII:
2555 *mipsIV:
2556 *mipsV:
2557 *vr4100:
2558 *vr5000:
2559 *r3900:
2560 {
2561   do_srav (SD_, RS, RT, RD);
2562 }
2563
2564
2565
2566 :function:::void:do_srl:int rt, int rd, int shift
2567 {
2568   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2569   TRACE_ALU_INPUT2 (GPR[rt], shift);
2570   GPR[rd] = EXTEND32 (temp);
2571   TRACE_ALU_RESULT (GPR[rd]);
2572 }
2573
2574 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2575 "srl r<RD>, r<RT>, <SHIFT>"
2576 *mipsI:
2577 *mipsII:
2578 *mipsIII:
2579 *mipsIV:
2580 *mipsV:
2581 *vr4100:
2582 *vr5000:
2583 *r3900:
2584 {
2585   do_srl (SD_, RT, RD, SHIFT);
2586 }
2587
2588
2589 :function:::void:do_srlv:int rs, int rt, int rd
2590 {
2591   int s = MASKED (GPR[rs], 4, 0);
2592   unsigned32 temp = (unsigned32) GPR[rt] >> s;
2593   TRACE_ALU_INPUT2 (GPR[rt], s);
2594   GPR[rd] = EXTEND32 (temp);
2595   TRACE_ALU_RESULT (GPR[rd]);
2596 }
2597
2598 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
2599 "srlv r<RD>, r<RT>, r<RS>"
2600 *mipsI:
2601 *mipsII:
2602 *mipsIII:
2603 *mipsIV:
2604 *mipsV:
2605 *vr4100:
2606 *vr5000:
2607 *r3900:
2608 {
2609   do_srlv (SD_, RS, RT, RD);
2610 }
2611
2612
2613 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
2614 "sub r<RD>, r<RS>, r<RT>"
2615 *mipsI:
2616 *mipsII:
2617 *mipsIII:
2618 *mipsIV:
2619 *mipsV:
2620 *vr4100:
2621 *vr5000:
2622 *r3900:
2623 {
2624   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2625   {
2626     ALU32_BEGIN (GPR[RS]);
2627     ALU32_SUB (GPR[RT]);
2628     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
2629   }
2630   TRACE_ALU_RESULT (GPR[RD]);
2631 }
2632
2633
2634 :function:::void:do_subu:int rs, int rt, int rd
2635 {
2636   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2637   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2638   TRACE_ALU_RESULT (GPR[rd]);
2639 }
2640
2641 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
2642 "subu r<RD>, r<RS>, r<RT>"
2643 *mipsI:
2644 *mipsII:
2645 *mipsIII:
2646 *mipsIV:
2647 *mipsV:
2648 *vr4100:
2649 *vr5000:
2650 *r3900:
2651 {
2652   do_subu (SD_, RS, RT, RD);
2653 }
2654
2655
2656 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2657 "sw r<RT>, <OFFSET>(r<BASE>)"
2658 *mipsI:
2659 *mipsII:
2660 *mipsIII:
2661 *mipsIV:
2662 *mipsV:
2663 *vr4100:
2664 *r3900:
2665 *vr5000:
2666 {
2667   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2668 }
2669
2670
2671 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2672 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2673 *mipsI:
2674 *mipsII:
2675 *mipsIII:
2676 *mipsIV:
2677 *mipsV:
2678 *vr4100:
2679 *vr5000:
2680 *r3900:
2681 {
2682   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2683 }
2684
2685
2686 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2687 "swl r<RT>, <OFFSET>(r<BASE>)"
2688 *mipsI:
2689 *mipsII:
2690 *mipsIII:
2691 *mipsIV:
2692 *mipsV:
2693 *vr4100:
2694 *vr5000:
2695 *r3900:
2696 {
2697   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2698 }
2699
2700
2701 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2702 "swr r<RT>, <OFFSET>(r<BASE>)"
2703 *mipsI:
2704 *mipsII:
2705 *mipsIII:
2706 *mipsIV:
2707 *mipsV:
2708 *vr4100:
2709 *vr5000:
2710 *r3900:
2711 {
2712   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2713 }
2714
2715
2716 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2717 "sync":STYPE == 0
2718 "sync <STYPE>"
2719 *mipsII:
2720 *mipsIII:
2721 *mipsIV:
2722 *mipsV:
2723 *vr4100:
2724 *vr5000:
2725 *r3900:
2726 {
2727   SyncOperation (STYPE);
2728 }
2729
2730
2731 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2732 "syscall <CODE>"
2733 *mipsI:
2734 *mipsII:
2735 *mipsIII:
2736 *mipsIV:
2737 *mipsV:
2738 *vr4100:
2739 *vr5000:
2740 *r3900:
2741 {
2742   SignalException(SystemCall, instruction_0);
2743 }
2744
2745
2746 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2747 "teq r<RS>, r<RT>"
2748 *mipsII:
2749 *mipsIII:
2750 *mipsIV:
2751 *mipsV:
2752 *vr4100:
2753 *vr5000:
2754 {
2755   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2756     SignalException(Trap, instruction_0);
2757 }
2758
2759
2760 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2761 "teqi r<RS>, <IMMEDIATE>"
2762 *mipsII:
2763 *mipsIII:
2764 *mipsIV:
2765 *mipsV:
2766 *vr4100:
2767 *vr5000:
2768 {
2769   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2770     SignalException(Trap, instruction_0);
2771 }
2772
2773
2774 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2775 "tge r<RS>, r<RT>"
2776 *mipsII:
2777 *mipsIII:
2778 *mipsIV:
2779 *mipsV:
2780 *vr4100:
2781 *vr5000:
2782 {
2783   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2784     SignalException(Trap, instruction_0);
2785 }
2786
2787
2788 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2789 "tgei r<RS>, <IMMEDIATE>"
2790 *mipsII:
2791 *mipsIII:
2792 *mipsIV:
2793 *mipsV:
2794 *vr4100:
2795 *vr5000:
2796 {
2797   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2798     SignalException(Trap, instruction_0);
2799 }
2800
2801
2802 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2803 "tgeiu r<RS>, <IMMEDIATE>"
2804 *mipsII:
2805 *mipsIII:
2806 *mipsIV:
2807 *mipsV:
2808 *vr4100:
2809 *vr5000:
2810 {
2811   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2812     SignalException(Trap, instruction_0);
2813 }
2814
2815
2816 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2817 "tgeu r<RS>, r<RT>"
2818 *mipsII:
2819 *mipsIII:
2820 *mipsIV:
2821 *mipsV:
2822 *vr4100:
2823 *vr5000:
2824 {
2825   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2826     SignalException(Trap, instruction_0);
2827 }
2828
2829
2830 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2831 "tlt r<RS>, r<RT>"
2832 *mipsII:
2833 *mipsIII:
2834 *mipsIV:
2835 *mipsV:
2836 *vr4100:
2837 *vr5000:
2838 {
2839   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2840     SignalException(Trap, instruction_0);
2841 }
2842
2843
2844 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2845 "tlti r<RS>, <IMMEDIATE>"
2846 *mipsII:
2847 *mipsIII:
2848 *mipsIV:
2849 *mipsV:
2850 *vr4100:
2851 *vr5000:
2852 {
2853   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2854     SignalException(Trap, instruction_0);
2855 }
2856
2857
2858 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2859 "tltiu r<RS>, <IMMEDIATE>"
2860 *mipsII:
2861 *mipsIII:
2862 *mipsIV:
2863 *mipsV:
2864 *vr4100:
2865 *vr5000:
2866 {
2867   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2868     SignalException(Trap, instruction_0);
2869 }
2870
2871
2872 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2873 "tltu r<RS>, r<RT>"
2874 *mipsII:
2875 *mipsIII:
2876 *mipsIV:
2877 *mipsV:
2878 *vr4100:
2879 *vr5000:
2880 {
2881   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2882     SignalException(Trap, instruction_0);
2883 }
2884
2885
2886 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2887 "tne r<RS>, r<RT>"
2888 *mipsII:
2889 *mipsIII:
2890 *mipsIV:
2891 *mipsV:
2892 *vr4100:
2893 *vr5000:
2894 {
2895   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2896     SignalException(Trap, instruction_0);
2897 }
2898
2899
2900 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2901 "tne r<RS>, <IMMEDIATE>"
2902 *mipsII:
2903 *mipsIII:
2904 *mipsIV:
2905 *mipsV:
2906 *vr4100:
2907 *vr5000:
2908 {
2909   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2910     SignalException(Trap, instruction_0);
2911 }
2912
2913
2914 :function:::void:do_xor:int rs, int rt, int rd
2915 {
2916   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2917   GPR[rd] = GPR[rs] ^ GPR[rt];
2918   TRACE_ALU_RESULT (GPR[rd]);
2919 }
2920
2921 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
2922 "xor r<RD>, r<RS>, r<RT>"
2923 *mipsI:
2924 *mipsII:
2925 *mipsIII:
2926 *mipsIV:
2927 *mipsV:
2928 *vr4100:
2929 *vr5000:
2930 *r3900:
2931 {
2932   do_xor (SD_, RS, RT, RD);
2933 }
2934
2935
2936 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
2937 {
2938   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2939   GPR[rt] = GPR[rs] ^ immediate;
2940   TRACE_ALU_RESULT (GPR[rt]);
2941 }
2942
2943 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2944 "xori r<RT>, r<RS>, <IMMEDIATE>"
2945 *mipsI:
2946 *mipsII:
2947 *mipsIII:
2948 *mipsIV:
2949 *mipsV:
2950 *vr4100:
2951 *vr5000:
2952 *r3900:
2953 {
2954   do_xori (SD_, RS, RT, IMMEDIATE);
2955 }
2956
2957 \f
2958 //
2959 // MIPS Architecture:
2960 //
2961 //        FPU Instruction Set (COP1 & COP1X)
2962 //
2963
2964
2965 :%s::::FMT:int fmt
2966 {
2967   switch (fmt)
2968     {
2969     case fmt_single: return "s";
2970     case fmt_double: return "d";
2971     case fmt_word: return "w";
2972     case fmt_long: return "l";
2973     default: return "?";
2974     }
2975 }
2976
2977 :%s::::X:int x
2978 {
2979   switch (x)
2980     {
2981     case 0: return "f";
2982     case 1: return "t";
2983     default: return "?";
2984     }
2985 }
2986
2987 :%s::::TF:int tf
2988 {
2989   if (tf)
2990     return "t";
2991   else
2992     return "f";
2993 }
2994
2995 :%s::::ND:int nd
2996 {
2997   if (nd)
2998     return "l";
2999   else
3000     return "";
3001 }
3002
3003 :%s::::COND:int cond
3004 {
3005   switch (cond)
3006     {
3007     case 00: return "f";
3008     case 01: return "un";
3009     case 02: return "eq";
3010     case 03: return "ueq";
3011     case 04: return "olt";
3012     case 05: return "ult";
3013     case 06: return "ole";
3014     case 07: return "ule";
3015     case 010: return "sf";
3016     case 011: return "ngle";
3017     case 012: return "seq";
3018     case 013: return "ngl";
3019     case 014: return "lt";
3020     case 015: return "nge";
3021     case 016: return "le";
3022     case 017: return "ngt";
3023     default: return "?";
3024     }
3025 }
3026
3027 // Helper:
3028 //
3029 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3030 // exception if not.
3031 //
3032
3033 :function:::void:check_fpu:
3034 *mipsI:
3035 *mipsII:
3036 *mipsIII:
3037 *mipsIV:
3038 *mipsV:
3039 *vr4100:
3040 *vr5000:
3041 *r3900:
3042 {
3043 #if 0   /* XXX FIXME: For now, never treat the FPU as disabled.  */
3044   if (! COP_Usable (1))
3045     SignalExceptionCoProcessorUnusable (1);
3046 #endif
3047 }
3048
3049
3050 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3051 "abs.%s<FMT> f<FD>, f<FS>"
3052 *mipsI:
3053 *mipsII:
3054 *mipsIII:
3055 *mipsIV:
3056 *mipsV:
3057 *vr4100:
3058 *vr5000:
3059 *r3900:
3060 {
3061   unsigned32 instruction = instruction_0;
3062   int destreg = ((instruction >> 6) & 0x0000001F);
3063   int fs = ((instruction >> 11) & 0x0000001F);
3064   int format = ((instruction >> 21) & 0x00000007);
3065   check_fpu(SD_);
3066   {
3067     if ((format != fmt_single) && (format != fmt_double))
3068       SignalException(ReservedInstruction,instruction);
3069     else
3070       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3071   }
3072 }
3073
3074
3075
3076 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3077 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3078 *mipsI:
3079 *mipsII:
3080 *mipsIII:
3081 *mipsIV:
3082 *mipsV:
3083 *vr4100:
3084 *vr5000:
3085 *r3900:
3086 {
3087   unsigned32 instruction = instruction_0;
3088   int destreg = ((instruction >> 6) & 0x0000001F);
3089   int fs = ((instruction >> 11) & 0x0000001F);
3090   int ft = ((instruction >> 16) & 0x0000001F);
3091   int format = ((instruction >> 21) & 0x00000007);
3092   check_fpu(SD_);
3093   {
3094     if ((format != fmt_single) && (format != fmt_double))
3095       SignalException(ReservedInstruction, instruction);
3096     else
3097       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3098   }
3099 }
3100
3101
3102
3103 // BC1F
3104 // BC1FL
3105 // BC1T
3106 // BC1TL
3107
3108 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3109 "bc1%s<TF>%s<ND> <OFFSET>"
3110 *mipsI:
3111 *mipsII:
3112 *mipsIII:
3113 {
3114   check_fpu(SD_);
3115   check_branch_bug ();
3116   TRACE_BRANCH_INPUT (PREVCOC1());
3117   if (PREVCOC1() == TF)
3118     {
3119       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3120       TRACE_BRANCH_RESULT (dest);
3121       mark_branch_bug (dest);
3122       DELAY_SLOT (dest);
3123     }
3124   else if (ND)
3125     {
3126       TRACE_BRANCH_RESULT (0);
3127       NULLIFY_NEXT_INSTRUCTION ();
3128     }
3129   else
3130     {
3131       TRACE_BRANCH_RESULT (NIA);
3132     }
3133 }
3134
3135 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3136 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3137 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3138 *mipsIV:
3139 *mipsV:
3140 #*vr4100:
3141 *vr5000:
3142 *r3900:
3143 {
3144   check_fpu(SD_);
3145   check_branch_bug ();
3146   if (GETFCC(CC) == TF)
3147     {
3148       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3149       mark_branch_bug (dest);
3150       DELAY_SLOT (dest);
3151     }
3152   else if (ND)
3153     {
3154       NULLIFY_NEXT_INSTRUCTION ();
3155     }
3156 }
3157
3158
3159
3160
3161
3162
3163 // C.EQ.S
3164 // C.EQ.D
3165 // ...
3166
3167 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3168 {
3169   if ((fmt != fmt_single) && (fmt != fmt_double))
3170     SignalException (ReservedInstruction, insn);
3171   else
3172     {
3173       int less;
3174       int equal;
3175       int unordered;
3176       int condition;
3177       unsigned64 ofs = ValueFPR (fs, fmt);
3178       unsigned64 oft = ValueFPR (ft, fmt);
3179       if (NaN (ofs, fmt) || NaN (oft, fmt))
3180         {
3181           if (FCSR & FP_ENABLE (IO))
3182             {
3183               FCSR |= FP_CAUSE (IO);
3184               SignalExceptionFPE ();
3185             }
3186           less = 0;
3187           equal = 0;
3188           unordered = 1;
3189         }
3190       else
3191         {
3192           less = Less (ofs, oft, fmt);
3193           equal = Equal (ofs, oft, fmt);
3194           unordered = 0;
3195         }
3196       condition = (((cond & (1 << 2)) && less)
3197                    || ((cond & (1 << 1)) && equal)
3198                    || ((cond & (1 << 0)) && unordered));
3199       SETFCC (cc, condition);
3200     }
3201 }
3202
3203 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3204 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3205 *mipsI:
3206 *mipsII:
3207 *mipsIII:
3208 {
3209   check_fpu(SD_);
3210   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3211 }
3212
3213 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3214 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3215 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3216 *mipsIV:
3217 *mipsV:
3218 *vr4100:
3219 *vr5000:
3220 *r3900:
3221 {
3222   check_fpu(SD_);
3223   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3224 }
3225
3226
3227 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3228 "ceil.l.%s<FMT> f<FD>, f<FS>"
3229 *mipsIII:
3230 *mipsIV:
3231 *mipsV:
3232 *vr4100:
3233 *vr5000:
3234 *r3900:
3235 {
3236   unsigned32 instruction = instruction_0;
3237   int destreg = ((instruction >> 6) & 0x0000001F);
3238   int fs = ((instruction >> 11) & 0x0000001F);
3239   int format = ((instruction >> 21) & 0x00000007);
3240   check_fpu(SD_);
3241   {
3242     if ((format != fmt_single) && (format != fmt_double))
3243       SignalException(ReservedInstruction,instruction);
3244     else
3245       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
3246   }
3247 }
3248
3249
3250 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3251 *mipsII:
3252 *mipsIII:
3253 *mipsIV:
3254 *mipsV:
3255 *vr4100:
3256 *vr5000:
3257 *r3900:
3258 {
3259   unsigned32 instruction = instruction_0;
3260   int destreg = ((instruction >> 6) & 0x0000001F);
3261   int fs = ((instruction >> 11) & 0x0000001F);
3262   int format = ((instruction >> 21) & 0x00000007);
3263   check_fpu(SD_);
3264   {
3265   if ((format != fmt_single) && (format != fmt_double))
3266    SignalException(ReservedInstruction,instruction);
3267   else
3268    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
3269   }
3270 }
3271
3272
3273 // CFC1
3274 // CTC1
3275 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
3276 "c%s<X>c1 r<RT>, f<FS>"
3277 *mipsI:
3278 *mipsII:
3279 *mipsIII:
3280 {
3281   check_fpu(SD_);
3282   if (X)
3283     {
3284       if (FS == 0)
3285         PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
3286       else if (FS == 31)
3287         PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
3288       /* else NOP */
3289       PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
3290     }
3291   else
3292     { /* control from */
3293       if (FS == 0)
3294         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
3295       else if (FS == 31)
3296         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
3297       /* else NOP */
3298     }
3299 }
3300 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
3301 "c%s<X>c1 r<RT>, f<FS>"
3302 *mipsIV:
3303 *mipsV:
3304 *vr4100:
3305 *vr5000:
3306 *r3900:
3307 {
3308   check_fpu(SD_);
3309   if (X)
3310     {
3311       /* control to */
3312       TRACE_ALU_INPUT1 (GPR[RT]);
3313       if (FS == 0)
3314         {
3315           FCR0 = VL4_8(GPR[RT]);
3316           TRACE_ALU_RESULT (FCR0);
3317         }
3318       else if (FS == 31)
3319         {
3320           FCR31 = VL4_8(GPR[RT]);
3321           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3322           TRACE_ALU_RESULT (FCR31);
3323         }
3324       else
3325         {
3326           TRACE_ALU_RESULT0 ();
3327         }
3328       /* else NOP */
3329     }
3330   else
3331     { /* control from */
3332       if (FS == 0)
3333         {
3334           TRACE_ALU_INPUT1 (FCR0);
3335           GPR[RT] = SIGNEXTEND (FCR0, 32);
3336         }
3337       else if (FS == 31)
3338         {
3339           TRACE_ALU_INPUT1 (FCR31);
3340           GPR[RT] = SIGNEXTEND (FCR31, 32);
3341         }
3342       TRACE_ALU_RESULT (GPR[RT]);
3343       /* else NOP */
3344     }
3345 }
3346
3347
3348 //
3349 // FIXME: Does not correctly differentiate between mips*
3350 //
3351 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3352 "cvt.d.%s<FMT> f<FD>, f<FS>"
3353 *mipsI:
3354 *mipsII:
3355 *mipsIII:
3356 *mipsIV:
3357 *mipsV:
3358 *vr4100:
3359 *vr5000:
3360 *r3900:
3361 {
3362   unsigned32 instruction = instruction_0;
3363   int destreg = ((instruction >> 6) & 0x0000001F);
3364   int fs = ((instruction >> 11) & 0x0000001F);
3365   int format = ((instruction >> 21) & 0x00000007);
3366   check_fpu(SD_);
3367   {
3368     if ((format == fmt_double) | 0)
3369       SignalException(ReservedInstruction,instruction);
3370     else
3371       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
3372   }
3373 }
3374
3375
3376 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3377 "cvt.l.%s<FMT> f<FD>, f<FS>"
3378 *mipsIII:
3379 *mipsIV:
3380 *mipsV:
3381 *vr4100:
3382 *vr5000:
3383 *r3900:
3384 {
3385   unsigned32 instruction = instruction_0;
3386   int destreg = ((instruction >> 6) & 0x0000001F);
3387   int fs = ((instruction >> 11) & 0x0000001F);
3388   int format = ((instruction >> 21) & 0x00000007);
3389   check_fpu(SD_);
3390   {
3391     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
3392       SignalException(ReservedInstruction,instruction);
3393     else
3394       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
3395   }
3396 }
3397
3398
3399 //
3400 // FIXME: Does not correctly differentiate between mips*
3401 //
3402 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3403 "cvt.s.%s<FMT> f<FD>, f<FS>"
3404 *mipsI:
3405 *mipsII:
3406 *mipsIII:
3407 *mipsIV:
3408 *mipsV:
3409 *vr4100:
3410 *vr5000:
3411 *r3900:
3412 {
3413   unsigned32 instruction = instruction_0;
3414   int destreg = ((instruction >> 6) & 0x0000001F);
3415   int fs = ((instruction >> 11) & 0x0000001F);
3416   int format = ((instruction >> 21) & 0x00000007);
3417   check_fpu(SD_);
3418   {
3419     if ((format == fmt_single) | 0)
3420       SignalException(ReservedInstruction,instruction);
3421     else
3422       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
3423   }
3424 }
3425
3426
3427 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
3428 "cvt.w.%s<FMT> f<FD>, f<FS>"
3429 *mipsI:
3430 *mipsII:
3431 *mipsIII:
3432 *mipsIV:
3433 *mipsV:
3434 *vr4100:
3435 *vr5000:
3436 *r3900:
3437 {
3438   unsigned32 instruction = instruction_0;
3439   int destreg = ((instruction >> 6) & 0x0000001F);
3440   int fs = ((instruction >> 11) & 0x0000001F);
3441   int format = ((instruction >> 21) & 0x00000007);
3442   check_fpu(SD_);
3443   {
3444     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
3445       SignalException(ReservedInstruction,instruction);
3446     else
3447       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
3448   }
3449 }
3450
3451
3452 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
3453 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3454 *mipsI:
3455 *mipsII:
3456 *mipsIII:
3457 *mipsIV:
3458 *mipsV:
3459 *vr4100:
3460 *vr5000:
3461 *r3900:
3462 {
3463   unsigned32 instruction = instruction_0;
3464   int destreg = ((instruction >> 6) & 0x0000001F);
3465   int fs = ((instruction >> 11) & 0x0000001F);
3466   int ft = ((instruction >> 16) & 0x0000001F);
3467   int format = ((instruction >> 21) & 0x00000007);
3468   check_fpu(SD_);
3469   {
3470     if ((format != fmt_single) && (format != fmt_double))
3471       SignalException(ReservedInstruction,instruction);
3472     else
3473       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3474   }
3475 }
3476
3477
3478 // DMFC1
3479 // DMTC1
3480 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
3481 "dm%s<X>c1 r<RT>, f<FS>"
3482 *mipsIII:
3483 {
3484   check_fpu(SD_);
3485   check_u64 (SD_, instruction_0);
3486   if (X)
3487     {
3488       if (SizeFGR() == 64)
3489         PENDING_FILL((FS + FGRIDX),GPR[RT]);
3490       else if ((FS & 0x1) == 0)
3491         {
3492           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3493           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3494         }
3495     }
3496   else
3497     {
3498       if (SizeFGR() == 64)
3499         PENDING_FILL(RT,FGR[FS]);
3500       else if ((FS & 0x1) == 0)
3501         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3502       else
3503         {
3504           if (STATE_VERBOSE_P(SD))
3505             sim_io_eprintf (SD,
3506               "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
3507               (long) CIA);
3508           PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3509         }
3510     }
3511 }
3512 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
3513 "dm%s<X>c1 r<RT>, f<FS>"
3514 *mipsIV:
3515 *mipsV:
3516 *vr4100:
3517 *vr5000:
3518 *r3900:
3519 {
3520   check_fpu(SD_);
3521   check_u64 (SD_, instruction_0);
3522   if (X)
3523     {
3524       if (SizeFGR() == 64)
3525         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3526       else if ((FS & 0x1) == 0)
3527         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3528     }
3529   else
3530     {
3531       if (SizeFGR() == 64)
3532         GPR[RT] = FGR[FS];
3533       else if ((FS & 0x1) == 0)
3534         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3535       else
3536         {
3537           if (STATE_VERBOSE_P(SD))
3538             sim_io_eprintf (SD,
3539               "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
3540                             (long) CIA);
3541           GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3542         }
3543     }
3544 }
3545
3546
3547 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
3548 "floor.l.%s<FMT> f<FD>, f<FS>"
3549 *mipsIII:
3550 *mipsIV:
3551 *mipsV:
3552 *vr4100:
3553 *vr5000:
3554 *r3900:
3555 {
3556   unsigned32 instruction = instruction_0;
3557   int destreg = ((instruction >> 6) & 0x0000001F);
3558   int fs = ((instruction >> 11) & 0x0000001F);
3559   int format = ((instruction >> 21) & 0x00000007);
3560   check_fpu(SD_);
3561   {
3562     if ((format != fmt_single) && (format != fmt_double))
3563       SignalException(ReservedInstruction,instruction);
3564     else
3565       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3566   }
3567 }
3568
3569
3570 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
3571 "floor.w.%s<FMT> f<FD>, f<FS>"
3572 *mipsII:
3573 *mipsIII:
3574 *mipsIV:
3575 *mipsV:
3576 *vr4100:
3577 *vr5000:
3578 *r3900:
3579 {
3580   unsigned32 instruction = instruction_0;
3581   int destreg = ((instruction >> 6) & 0x0000001F);
3582   int fs = ((instruction >> 11) & 0x0000001F);
3583   int format = ((instruction >> 21) & 0x00000007);
3584   check_fpu(SD_);
3585   {
3586     if ((format != fmt_single) && (format != fmt_double))
3587       SignalException(ReservedInstruction,instruction);
3588     else
3589       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3590   }
3591 }
3592
3593
3594 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
3595 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
3596 *mipsII:
3597 *mipsIII:
3598 *mipsIV:
3599 *mipsV:
3600 *vr4100:
3601 *vr5000:
3602 *r3900:
3603 {
3604   check_fpu(SD_);
3605   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3606 }
3607
3608
3609 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
3610 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3611 *mipsIV:
3612 *mipsV:
3613 *vr5000:
3614 {
3615   check_fpu(SD_);
3616   check_u64 (SD_, instruction_0);
3617   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3618 }
3619
3620
3621
3622 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
3623 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
3624 *mipsI:
3625 *mipsII:
3626 *mipsIII:
3627 *mipsIV:
3628 *mipsV:
3629 *vr4100:
3630 *vr5000:
3631 *r3900:
3632 {
3633   check_fpu(SD_);
3634   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3635 }
3636
3637
3638 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
3639 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3640 *mipsIV:
3641 *mipsV:
3642 *vr5000:
3643 {
3644   check_fpu(SD_);
3645   check_u64 (SD_, instruction_0);
3646   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3647 }
3648
3649
3650
3651 //
3652 // FIXME: Not correct for mips*
3653 //
3654 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3655 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3656 *mipsIV:
3657 *mipsV:
3658 *vr5000:
3659 {
3660   unsigned32 instruction = instruction_0;
3661   int destreg = ((instruction >> 6) & 0x0000001F);
3662   int fs = ((instruction >> 11) & 0x0000001F);
3663   int ft = ((instruction >> 16) & 0x0000001F);
3664   int fr = ((instruction >> 21) & 0x0000001F);
3665   check_fpu(SD_);
3666   {
3667     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3668   }
3669 }
3670
3671
3672 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3673 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3674 *mipsIV:
3675 *mipsV:
3676 *vr5000:
3677 {
3678   unsigned32 instruction = instruction_0;
3679   int destreg = ((instruction >> 6) & 0x0000001F);
3680   int fs = ((instruction >> 11) & 0x0000001F);
3681   int ft = ((instruction >> 16) & 0x0000001F);
3682   int fr = ((instruction >> 21) & 0x0000001F);
3683   check_fpu(SD_);
3684   {
3685     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3686   }
3687 }
3688
3689
3690 // MFC1
3691 // MTC1
3692 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
3693 "m%s<X>c1 r<RT>, f<FS>"
3694 *mipsI:
3695 *mipsII:
3696 *mipsIII:
3697 {
3698   check_fpu(SD_);
3699   if (X)
3700     { /*MTC1*/
3701       if (SizeFGR() == 64)
3702         {
3703           if (STATE_VERBOSE_P(SD))
3704             sim_io_eprintf (SD,
3705                             "Warning:  PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
3706                             (long) CIA);
3707           PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3708         }
3709       else
3710         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3711     }
3712   else /*MFC1*/
3713     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
3714 }
3715 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
3716 "m%s<X>c1 r<RT>, f<FS>"
3717 *mipsIV:
3718 *mipsV:
3719 *vr4100:
3720 *vr5000:
3721 *r3900:
3722 {
3723   int fs = FS;
3724   check_fpu(SD_);
3725   if (X)
3726     /*MTC1*/
3727     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3728   else /*MFC1*/
3729     GPR[RT] = SIGNEXTEND(FGR[FS],32);
3730 }
3731
3732
3733 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
3734 "mov.%s<FMT> f<FD>, f<FS>"
3735 *mipsI:
3736 *mipsII:
3737 *mipsIII:
3738 *mipsIV:
3739 *mipsV:
3740 *vr4100:
3741 *vr5000:
3742 *r3900:
3743 {
3744   unsigned32 instruction = instruction_0;
3745   int destreg = ((instruction >> 6) & 0x0000001F);
3746   int fs = ((instruction >> 11) & 0x0000001F);
3747   int format = ((instruction >> 21) & 0x00000007);
3748   check_fpu(SD_);
3749   {
3750     StoreFPR(destreg,format,ValueFPR(fs,format));
3751   }
3752 }
3753
3754
3755 // MOVF
3756 // MOVT
3757 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
3758 "mov%s<TF> r<RD>, r<RS>, <CC>"
3759 *mipsIV:
3760 *mipsV:
3761 *vr5000:
3762 {
3763   check_fpu(SD_);
3764   if (GETFCC(CC) == TF)
3765     GPR[RD] = GPR[RS];
3766 }
3767
3768
3769 // MOVF.fmt
3770 // MOVT.fmt
3771 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
3772 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3773 *mipsIV:
3774 *mipsV:
3775 *vr5000:
3776 {
3777   unsigned32 instruction = instruction_0;
3778   int format = ((instruction >> 21) & 0x00000007);
3779   check_fpu(SD_);
3780   {
3781    if (GETFCC(CC) == TF)
3782      StoreFPR (FD, format, ValueFPR (FS, format));
3783    else
3784      StoreFPR (FD, format, ValueFPR (FD, format));
3785   }
3786 }
3787
3788
3789 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
3790 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
3791 *mipsIV:
3792 *mipsV:
3793 *vr5000:
3794 {
3795   check_fpu(SD_);
3796   if (GPR[RT] != 0)
3797     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3798   else
3799     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3800 }
3801
3802
3803 // MOVT see MOVtf
3804
3805
3806 // MOVT.fmt see MOVtf.fmt
3807
3808
3809
3810 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
3811 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3812 *mipsIV:
3813 *mipsV:
3814 *vr5000:
3815 {
3816   check_fpu(SD_);
3817   if (GPR[RT] == 0)
3818     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3819   else
3820     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3821 }
3822
3823
3824 // MSUB.fmt
3825 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
3826 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3827 *mipsIV:
3828 *mipsV:
3829 *vr5000:
3830 {
3831   unsigned32 instruction = instruction_0;
3832   int destreg = ((instruction >> 6) & 0x0000001F);
3833   int fs = ((instruction >> 11) & 0x0000001F);
3834   int ft = ((instruction >> 16) & 0x0000001F);
3835   int fr = ((instruction >> 21) & 0x0000001F);
3836   check_fpu(SD_);
3837   {
3838     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3839   }
3840 }
3841
3842
3843 // MSUB.fmt
3844 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
3845 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3846 *mipsIV:
3847 *mipsV:
3848 *vr5000:
3849 {
3850   unsigned32 instruction = instruction_0;
3851   int destreg = ((instruction >> 6) & 0x0000001F);
3852   int fs = ((instruction >> 11) & 0x0000001F);
3853   int ft = ((instruction >> 16) & 0x0000001F);
3854   int fr = ((instruction >> 21) & 0x0000001F);
3855   check_fpu(SD_);
3856   {
3857    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3858   }
3859 }
3860
3861
3862 // MTC1 see MxC1
3863
3864
3865 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
3866 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3867 *mipsI:
3868 *mipsII:
3869 *mipsIII:
3870 *mipsIV:
3871 *mipsV:
3872 *vr4100:
3873 *vr5000:
3874 *r3900:
3875 {
3876   unsigned32 instruction = instruction_0;
3877   int destreg = ((instruction >> 6) & 0x0000001F);
3878   int fs = ((instruction >> 11) & 0x0000001F);
3879   int ft = ((instruction >> 16) & 0x0000001F);
3880   int format = ((instruction >> 21) & 0x00000007);
3881   check_fpu(SD_);
3882   {
3883     if ((format != fmt_single) && (format != fmt_double))
3884       SignalException(ReservedInstruction,instruction);
3885     else
3886       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3887   }
3888 }
3889
3890
3891 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
3892 "neg.%s<FMT> f<FD>, f<FS>"
3893 *mipsI:
3894 *mipsII:
3895 *mipsIII:
3896 *mipsIV:
3897 *mipsV:
3898 *vr4100:
3899 *vr5000:
3900 *r3900:
3901 {
3902   unsigned32 instruction = instruction_0;
3903   int destreg = ((instruction >> 6) & 0x0000001F);
3904   int fs = ((instruction >> 11) & 0x0000001F);
3905   int format = ((instruction >> 21) & 0x00000007);
3906   check_fpu(SD_);
3907   {
3908     if ((format != fmt_single) && (format != fmt_double))
3909       SignalException(ReservedInstruction,instruction);
3910     else
3911       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3912   }
3913 }
3914
3915
3916 // NMADD.fmt
3917 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
3918 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3919 *mipsIV:
3920 *mipsV:
3921 *vr5000:
3922 {
3923   unsigned32 instruction = instruction_0;
3924   int destreg = ((instruction >> 6) & 0x0000001F);
3925   int fs = ((instruction >> 11) & 0x0000001F);
3926   int ft = ((instruction >> 16) & 0x0000001F);
3927   int fr = ((instruction >> 21) & 0x0000001F);
3928   check_fpu(SD_);
3929   {
3930    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3931   }
3932 }
3933
3934
3935 // NMADD.fmt
3936 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
3937 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3938 *mipsIV:
3939 *mipsV:
3940 *vr5000:
3941 {
3942   unsigned32 instruction = instruction_0;
3943   int destreg = ((instruction >> 6) & 0x0000001F);
3944   int fs = ((instruction >> 11) & 0x0000001F);
3945   int ft = ((instruction >> 16) & 0x0000001F);
3946   int fr = ((instruction >> 21) & 0x0000001F);
3947   check_fpu(SD_);
3948   {
3949    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3950   }
3951 }
3952
3953
3954 // NMSUB.fmt
3955 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
3956 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3957 *mipsIV:
3958 *mipsV:
3959 *vr5000:
3960 {
3961   unsigned32 instruction = instruction_0;
3962   int destreg = ((instruction >> 6) & 0x0000001F);
3963   int fs = ((instruction >> 11) & 0x0000001F);
3964   int ft = ((instruction >> 16) & 0x0000001F);
3965   int fr = ((instruction >> 21) & 0x0000001F);
3966   check_fpu(SD_);
3967   {
3968    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3969   }
3970 }
3971
3972
3973 // NMSUB.fmt
3974 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
3975 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3976 *mipsIV:
3977 *mipsV:
3978 *vr5000:
3979 {
3980   unsigned32 instruction = instruction_0;
3981   int destreg = ((instruction >> 6) & 0x0000001F);
3982   int fs = ((instruction >> 11) & 0x0000001F);
3983   int ft = ((instruction >> 16) & 0x0000001F);
3984   int fr = ((instruction >> 21) & 0x0000001F);
3985   check_fpu(SD_);
3986   {
3987     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3988   }
3989 }
3990
3991
3992 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
3993 "prefx <HINT>, r<INDEX>(r<BASE>)"
3994 *mipsIV:
3995 *mipsV:
3996 *vr5000:
3997 {
3998   unsigned32 instruction = instruction_0;
3999   int fs = ((instruction >> 11) & 0x0000001F);
4000   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4001   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4002   {
4003     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4004     address_word paddr;
4005     int uncached;
4006     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4007       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4008   }
4009 }
4010
4011 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4012 "recip.%s<FMT> f<FD>, f<FS>"
4013 *mipsIV:
4014 *mipsV:
4015 *vr5000:
4016 {
4017   unsigned32 instruction = instruction_0;
4018   int destreg = ((instruction >> 6) & 0x0000001F);
4019   int fs = ((instruction >> 11) & 0x0000001F);
4020   int format = ((instruction >> 21) & 0x00000007);
4021   check_fpu(SD_);
4022   {
4023   if ((format != fmt_single) && (format != fmt_double))
4024    SignalException(ReservedInstruction,instruction);
4025   else
4026    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
4027   }
4028 }
4029
4030
4031 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4032 "round.l.%s<FMT> f<FD>, f<FS>"
4033 *mipsIII:
4034 *mipsIV:
4035 *mipsV:
4036 *vr4100:
4037 *vr5000:
4038 *r3900:
4039 {
4040   unsigned32 instruction = instruction_0;
4041   int destreg = ((instruction >> 6) & 0x0000001F);
4042   int fs = ((instruction >> 11) & 0x0000001F);
4043   int format = ((instruction >> 21) & 0x00000007);
4044   check_fpu(SD_);
4045   {
4046     if ((format != fmt_single) && (format != fmt_double))
4047       SignalException(ReservedInstruction,instruction);
4048     else
4049       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
4050   }
4051 }
4052
4053
4054 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4055 "round.w.%s<FMT> f<FD>, f<FS>"
4056 *mipsII:
4057 *mipsIII:
4058 *mipsIV:
4059 *mipsV:
4060 *vr4100:
4061 *vr5000:
4062 *r3900:
4063 {
4064   unsigned32 instruction = instruction_0;
4065   int destreg = ((instruction >> 6) & 0x0000001F);
4066   int fs = ((instruction >> 11) & 0x0000001F);
4067   int format = ((instruction >> 21) & 0x00000007);
4068   check_fpu(SD_);
4069   {
4070   if ((format != fmt_single) && (format != fmt_double))
4071    SignalException(ReservedInstruction,instruction);
4072   else
4073    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
4074   }
4075 }
4076
4077
4078 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4079 *mipsIV:
4080 *mipsV:
4081 "rsqrt.%s<FMT> f<FD>, f<FS>"
4082 *vr5000:
4083 {
4084   unsigned32 instruction = instruction_0;
4085   int destreg = ((instruction >> 6) & 0x0000001F);
4086   int fs = ((instruction >> 11) & 0x0000001F);
4087   int format = ((instruction >> 21) & 0x00000007);
4088   check_fpu(SD_);
4089   {
4090   if ((format != fmt_single) && (format != fmt_double))
4091    SignalException(ReservedInstruction,instruction);
4092   else
4093    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
4094   }
4095 }
4096
4097
4098 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
4099 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4100 *mipsII:
4101 *mipsIII:
4102 *mipsIV:
4103 *mipsV:
4104 *vr4100:
4105 *vr5000:
4106 *r3900:
4107 {
4108   check_fpu(SD_);
4109   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4110 }
4111
4112
4113 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4114 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4115 *mipsIV:
4116 *mipsV:
4117 *vr5000:
4118 {
4119   check_fpu(SD_);
4120   check_u64 (SD_, instruction_0);
4121   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4122 }
4123
4124
4125 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4126 "sqrt.%s<FMT> f<FD>, f<FS>"
4127 *mipsII:
4128 *mipsIII:
4129 *mipsIV:
4130 *mipsV:
4131 *vr4100:
4132 *vr5000:
4133 *r3900:
4134 {
4135   unsigned32 instruction = instruction_0;
4136   int destreg = ((instruction >> 6) & 0x0000001F);
4137   int fs = ((instruction >> 11) & 0x0000001F);
4138   int format = ((instruction >> 21) & 0x00000007);
4139   check_fpu(SD_);
4140   {
4141     if ((format != fmt_single) && (format != fmt_double))
4142       SignalException(ReservedInstruction,instruction);
4143     else
4144       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
4145   }
4146 }
4147
4148
4149 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4150 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4151 *mipsI:
4152 *mipsII:
4153 *mipsIII:
4154 *mipsIV:
4155 *mipsV:
4156 *vr4100:
4157 *vr5000:
4158 *r3900:
4159 {
4160   unsigned32 instruction = instruction_0;
4161   int destreg = ((instruction >> 6) & 0x0000001F);
4162   int fs = ((instruction >> 11) & 0x0000001F);
4163   int ft = ((instruction >> 16) & 0x0000001F);
4164   int format = ((instruction >> 21) & 0x00000007);
4165   check_fpu(SD_);
4166   {
4167     if ((format != fmt_single) && (format != fmt_double))
4168       SignalException(ReservedInstruction,instruction);
4169     else
4170       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
4171   }
4172 }
4173
4174
4175
4176 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4177 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4178 *mipsI:
4179 *mipsII:
4180 *mipsIII:
4181 *mipsIV:
4182 *mipsV:
4183 *vr4100:
4184 *vr5000:
4185 *r3900:
4186 {
4187   unsigned32 instruction = instruction_0;
4188   signed_word offset = EXTEND16 (OFFSET);
4189   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4190   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4191   check_fpu(SD_);
4192   {
4193     address_word vaddr = ((uword64)op1 + offset);
4194     address_word paddr;
4195     int uncached;
4196     if ((vaddr & 3) != 0)
4197       {
4198         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4199       }
4200     else
4201       {
4202         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4203           {
4204             uword64 memval = 0;
4205             uword64 memval1 = 0;
4206             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4207             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4208             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4209             unsigned int byte;
4210             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4211             byte = ((vaddr & mask) ^ bigendiancpu);
4212             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
4213             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4214           }
4215       }
4216   }
4217 }
4218
4219
4220 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4221 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4222 *mipsIV:
4223 *mipsV:
4224 *vr5000:
4225 {
4226   unsigned32 instruction = instruction_0;
4227   int fs = ((instruction >> 11) & 0x0000001F);
4228   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4229   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4230   check_fpu(SD_);
4231   check_u64 (SD_, instruction_0);
4232   {
4233    address_word vaddr = ((unsigned64)op1 + op2);
4234    address_word paddr;
4235    int uncached;
4236    if ((vaddr & 3) != 0)
4237      {
4238        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4239      }
4240    else
4241    {
4242     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4243     {
4244      unsigned64 memval = 0;
4245      unsigned64 memval1 = 0;
4246      unsigned64 mask = 0x7;
4247      unsigned int byte;
4248      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4249      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4250      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
4251       {
4252        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4253       }
4254     }
4255    }
4256   }
4257 }
4258
4259
4260 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4261 "trunc.l.%s<FMT> f<FD>, f<FS>"
4262 *mipsIII:
4263 *mipsIV:
4264 *mipsV:
4265 *vr4100:
4266 *vr5000:
4267 *r3900:
4268 {
4269   unsigned32 instruction = instruction_0;
4270   int destreg = ((instruction >> 6) & 0x0000001F);
4271   int fs = ((instruction >> 11) & 0x0000001F);
4272   int format = ((instruction >> 21) & 0x00000007);
4273   check_fpu(SD_);
4274   {
4275   if ((format != fmt_single) && (format != fmt_double))
4276    SignalException(ReservedInstruction,instruction);
4277   else
4278    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
4279   }
4280 }
4281
4282
4283 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4284 "trunc.w.%s<FMT> f<FD>, f<FS>"
4285 *mipsII:
4286 *mipsIII:
4287 *mipsIV:
4288 *mipsV:
4289 *vr4100:
4290 *vr5000:
4291 *r3900:
4292 {
4293   unsigned32 instruction = instruction_0;
4294   int destreg = ((instruction >> 6) & 0x0000001F);
4295   int fs = ((instruction >> 11) & 0x0000001F);
4296   int format = ((instruction >> 21) & 0x00000007);
4297   check_fpu(SD_);
4298   {
4299   if ((format != fmt_single) && (format != fmt_double))
4300    SignalException(ReservedInstruction,instruction);
4301   else
4302    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
4303   }
4304 }
4305
4306 \f
4307 //
4308 // MIPS Architecture:
4309 //
4310 //        System Control Instruction Set (COP0)
4311 //
4312
4313
4314 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4315 "bc0f <OFFSET>"
4316 *mipsI:
4317 *mipsII:
4318 *mipsIII:
4319 *mipsIV:
4320 *mipsV:
4321 *vr4100:
4322 *vr5000:
4323
4324 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4325 "bc0f <OFFSET>"
4326 // stub needed for eCos as tx39 hardware bug workaround
4327 *r3900:
4328 {
4329   /* do nothing */
4330 }
4331
4332
4333 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4334 "bc0fl <OFFSET>"
4335 *mipsI:
4336 *mipsII:
4337 *mipsIII:
4338 *mipsIV:
4339 *mipsV:
4340 *vr4100:
4341 *vr5000:
4342
4343
4344 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4345 "bc0t <OFFSET>"
4346 *mipsI:
4347 *mipsII:
4348 *mipsIII:
4349 *mipsIV:
4350 *mipsV:
4351 *vr4100:
4352
4353
4354 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4355 "bc0tl <OFFSET>"
4356 *mipsI:
4357 *mipsII:
4358 *mipsIII:
4359 *mipsIV:
4360 *mipsV:
4361 *vr4100:
4362 *vr5000:
4363
4364
4365 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4366 "cache <OP>, <OFFSET>(r<BASE>)"
4367 *mipsIII:
4368 *mipsIV:
4369 *mipsV:
4370 *vr4100:
4371 *vr5000:
4372 *r3900:
4373 {
4374   unsigned32 instruction = instruction_0;
4375   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
4376   int hint = ((instruction >> 16) & 0x0000001F);
4377   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4378   {
4379     address_word vaddr = (op1 + offset);
4380     address_word paddr;
4381     int uncached;
4382     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4383       CacheOp(hint,vaddr,paddr,instruction);
4384   }
4385 }
4386
4387
4388 010000,1,0000000000000000000,111001:COP0:32::DI
4389 "di"
4390 *mipsI:
4391 *mipsII:
4392 *mipsIII:
4393 *mipsIV:
4394 *mipsV:
4395 *vr4100:
4396 *vr5000:
4397
4398
4399 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4400 "dmfc0 r<RT>, r<RD>"
4401 *mipsIII:
4402 *mipsIV:
4403 *mipsV:
4404 {
4405   check_u64 (SD_, instruction_0);
4406   DecodeCoproc (instruction_0);
4407 }
4408
4409
4410 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4411 "dmtc0 r<RT>, r<RD>"
4412 *mipsIII:
4413 *mipsIV:
4414 *mipsV:
4415 {
4416   check_u64 (SD_, instruction_0);
4417   DecodeCoproc (instruction_0);
4418 }
4419
4420
4421 010000,1,0000000000000000000,111000:COP0:32::EI
4422 "ei"
4423 *mipsI:
4424 *mipsII:
4425 *mipsIII:
4426 *mipsIV:
4427 *mipsV:
4428 *vr4100:
4429 *vr5000:
4430
4431
4432 010000,1,0000000000000000000,011000:COP0:32::ERET
4433 "eret"
4434 *mipsIII:
4435 *mipsIV:
4436 *mipsV:
4437 *vr4100:
4438 *vr5000:
4439 {
4440   if (SR & status_ERL)
4441     {
4442       /* Oops, not yet available */
4443       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4444       NIA = EPC;
4445       SR &= ~status_ERL;
4446     }
4447   else
4448     {
4449       NIA = EPC;
4450       SR &= ~status_EXL;
4451     }
4452 }
4453
4454
4455 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4456 "mfc0 r<RT>, r<RD> # <REGX>"
4457 *mipsI:
4458 *mipsII:
4459 *mipsIII:
4460 *mipsIV:
4461 *mipsV:
4462 *vr4100:
4463 *vr5000:
4464 *r3900:
4465 {
4466   TRACE_ALU_INPUT0 ();
4467   DecodeCoproc (instruction_0);
4468   TRACE_ALU_RESULT (GPR[RT]);
4469 }
4470
4471 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4472 "mtc0 r<RT>, r<RD> # <REGX>"
4473 *mipsI:
4474 *mipsII:
4475 *mipsIII:
4476 *mipsIV:
4477 *mipsV:
4478 *vr4100:
4479 *vr5000:
4480 *r3900:
4481 {
4482   DecodeCoproc (instruction_0);
4483 }
4484
4485
4486 010000,1,0000000000000000000,010000:COP0:32::RFE
4487 "rfe"
4488 *mipsI:
4489 *mipsII:
4490 *mipsIII:
4491 *mipsIV:
4492 *mipsV:
4493 *vr4100:
4494 *vr5000:
4495 *r3900:
4496 {
4497   DecodeCoproc (instruction_0);
4498 }
4499
4500
4501 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4502 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
4503 *mipsI:
4504 *mipsII:
4505 *mipsIII:
4506 *mipsIV:
4507 *mipsV:
4508 *vr4100:
4509 *r3900:
4510 {
4511   DecodeCoproc (instruction_0);
4512 }
4513
4514
4515
4516 010000,1,0000000000000000000,001000:COP0:32::TLBP
4517 "tlbp"
4518 *mipsI:
4519 *mipsII:
4520 *mipsIII:
4521 *mipsIV:
4522 *mipsV:
4523 *vr4100:
4524 *vr5000:
4525
4526
4527 010000,1,0000000000000000000,000001:COP0:32::TLBR
4528 "tlbr"
4529 *mipsI:
4530 *mipsII:
4531 *mipsIII:
4532 *mipsIV:
4533 *mipsV:
4534 *vr4100:
4535 *vr5000:
4536
4537
4538 010000,1,0000000000000000000,000010:COP0:32::TLBWI
4539 "tlbwi"
4540 *mipsI:
4541 *mipsII:
4542 *mipsIII:
4543 *mipsIV:
4544 *mipsV:
4545 *vr4100:
4546 *vr5000:
4547
4548
4549 010000,1,0000000000000000000,000110:COP0:32::TLBWR
4550 "tlbwr"
4551 *mipsI:
4552 *mipsII:
4553 *mipsIII:
4554 *mipsIV:
4555 *mipsV:
4556 *vr4100:
4557 *vr5000:
4558
4559 \f
4560 :include:::m16.igen
4561 :include:::tx.igen
4562 :include:::vr.igen
4563 \f