sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 // start-sanitize-vr4320
  47 :model:::vr4320:mips4320:
  48 // end-sanitize-vr4320
  49 // start-sanitize-vr5400
  50 :model:::vr5400:mips5400:
  51 :model:::mdmx:mdmx:
  52 // end-sanitize-vr5400
  53 :model:::vr5000:mips5000:
  54
  55
  56
  57 // Pseudo instructions known by IGEN
  58 :internal::::illegal:
  59 {
  60   SignalException (ReservedInstruction, 0);
  61 }
  62
  63
  64 // Pseudo instructions known by interp.c
  65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  67 "rsvd <OP>"
  68 {
  69   SignalException (ReservedInstruction, instruction_0);
  70 }
  71
  72
  73
  74 // Helper:
  75 //
  76 // Simulate a 32 bit delayslot instruction
  77 //
  78
  79 :function:::address_word:delayslot32:address_word target
  80 {
  81   instruction_word delay_insn;
  82   sim_events_slip (SD, 1);
  83   DSPC = CIA;
  84   CIA = CIA + 4; /* NOTE not mips16 */
  85   STATE |= simDELAYSLOT;
  86   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  87   idecode_issue (CPU_, delay_insn, (CIA));
  88   STATE &= ~simDELAYSLOT;
  89   return target;
  90 }
  91
  92 :function:::address_word:nullify_next_insn32:
  93 {
  94   sim_events_slip (SD, 1);
  95   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  96   return CIA + 8;
  97 }
  98
  99
 100
 101 // Helper:
 102 //
 103 // Check that an access to a HI/LO register meets timing requirements
 104 //
 105 // The following requirements exist:
 106 //
 107 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 108 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 109 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 110 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 111 //
 112
 113 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 114 {
 115   if (history->mf.timestamp + 3 > time)
 116     {
 117       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 118                         itable[MY_INDEX].name,
 119                         new, (long) CIA,
 120                         (long) history->mf.cia);
 121       return 0;
 122     }
 123   return 1;
 124 }
 125
 126 :function:::int:check_mt_hilo:hilo_history *history
 127 *mipsI,mipsII,mipsIII,mipsIV:
 128 *vr5000:
 129 // start-sanitize-vr4320
 130 *vr4320:
 131 // end-sanitize-vr4320
 132 // start-sanitize-vr5400
 133 *vr5400:
 134 // end-sanitize-vr5400
 135 {
 136   signed64 time = sim_events_time (SD);
 137   int ok = check_mf_cycles (SD_, history, time, "MT");
 138   history->mt.timestamp = time;
 139   history->mt.cia = CIA;
 140   return ok;
 141 }
 142
 143 :function:::int:check_mt_hilo:hilo_history *history
 144 *r3900:
 145 // start-sanitize-tx19
 146 *tx19:
 147 // end-sanitize-tx19
 148 // start-sanitize-r5900
 149 *r5900:
 150 // end-sanitize-r5900
 151 {
 152   signed64 time = sim_events_time (SD);
 153   history->mt.timestamp = time;
 154   history->mt.cia = CIA;
 155   return 1;
 156 }
 157
 158
 159 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 160 *mipsI,mipsII,mipsIII,mipsIV:
 161 *vr5000:
 162 // start-sanitize-vr4320
 163 *vr4320:
 164 // end-sanitize-vr4320
 165 // start-sanitize-vr5400
 166 *vr5400:
 167 // end-sanitize-vr5400
 168 *r3900:
 169 // start-sanitize-tx19
 170 *tx19:
 171 // end-sanitize-tx19
 172 {
 173   signed64 time = sim_events_time (SD);
 174   int ok = 1;
 175   if (peer != NULL
 176       && peer->mt.timestamp > history->op.timestamp
 177       && history->mf.timestamp < history->op.timestamp)
 178     {
 179       /* The peer has been written to since the last OP yet we have
 180          not */
 181       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 182                         itable[MY_INDEX].name,
 183                         (long) CIA,
 184                         (long) history->op.cia,
 185                         (long) peer->mt.cia);
 186       ok = 0;
 187     }
 188   history->mf.timestamp = time;
 189   history->mf.cia = CIA;
 190   return ok;
 191 }
 192
 193 // start-sanitize-r5900
 194 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
 195 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 196 // end-sanitize-r5900
 197 // start-sanitize-r5900
 198 *r5900:
 199 // end-sanitize-r5900
 200 // start-sanitize-r5900
 201 {
 202   /* FIXME: could record the fact that a stall occured if we want */
 203   signed64 time = sim_events_time (SD);
 204   history->mf.timestamp = time;
 205   history->mf.cia = CIA;
 206   return 1;
 207 }
 208 // end-sanitize-r5900
 209
 210
 211 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 212 *mipsI,mipsII,mipsIII,mipsIV:
 213 *vr5000:
 214 // start-sanitize-vr4320
 215 *vr4320:
 216 // end-sanitize-vr4320
 217 // start-sanitize-vr5400
 218 *vr5400:
 219 // end-sanitize-vr5400
 220 {
 221   signed64 time = sim_events_time (SD);
 222   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 223             && check_mf_cycles (SD_, lo, time, "OP"));
 224   hi->op.timestamp = time;
 225   lo->op.timestamp = time;
 226   hi->op.cia = CIA;
 227   lo->op.cia = CIA;
 228   return ok;
 229 }
 230
 231 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 232 // a mf{hi,lo}
 233 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 234 *r3900:
 235 // start-sanitize-tx19
 236 *tx19:
 237 // end-sanitize-tx19
 238 // start-sanitize-r5900
 239 *r5900:
 240 // end-sanitize-r5900
 241 {
 242   /* FIXME: could record the fact that a stall occured if we want */
 243   signed64 time = sim_events_time (SD);
 244   hi->op.timestamp = time;
 245   lo->op.timestamp = time;
 246   hi->op.cia = CIA;
 247   lo->op.cia = CIA;
 248   return 1;
 249 }
 250
 251
 252 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 253 *mipsI,mipsII,mipsIII,mipsIV:
 254 *vr5000:
 255 // start-sanitize-vr4320
 256 *vr4320:
 257 // end-sanitize-vr4320
 258 // start-sanitize-vr5400
 259 *vr5400:
 260 // end-sanitize-vr5400
 261 *r3900:
 262 // start-sanitize-tx19
 263 *tx19:
 264 // end-sanitize-tx19
 265 {
 266   signed64 time = sim_events_time (SD);
 267   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 268             && check_mf_cycles (SD_, lo, time, "OP"));
 269   hi->op.timestamp = time;
 270   lo->op.timestamp = time;
 271   hi->op.cia = CIA;
 272   lo->op.cia = CIA;
 273   return ok;
 274 }
 275
 276
 277 // start-sanitize-r5900
 278 // The r5900 div et.al insns _can_ be exectuted immediatly after
 279 // a mf{hi,lo}
 280 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 281 // end-sanitize-r5900
 282 // start-sanitize-r5900
 283 *r5900:
 284 // end-sanitize-r5900
 285 // start-sanitize-r5900
 286 {
 287   /* FIXME: could record the fact that a stall occured if we want */
 288   signed64 time = sim_events_time (SD);
 289   hi->op.timestamp = time;
 290   lo->op.timestamp = time;
 291   hi->op.cia = CIA;
 292   lo->op.cia = CIA;
 293   return 1;
 294 }
 295 // end-sanitize-r5900
 296
 297
 298
 299 //
 300 // Mips Architecture:
 301 //
 302 //        CPU Instruction Set (mipsI - mipsIV)
 303 //
 304
 305
 306
 307 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 308 "add r<RD>, r<RS>, r<RT>"
 309 *mipsI,mipsII,mipsIII,mipsIV:
 310 *vr5000:
 311 // start-sanitize-vr4320
 312 *vr4320:
 313 // end-sanitize-vr4320
 314 // start-sanitize-vr5400
 315 *vr5400:
 316 // end-sanitize-vr5400
 317 // start-sanitize-r5900
 318 *r5900:
 319 // end-sanitize-r5900
 320 *r3900:
 321 // start-sanitize-tx19
 322 *tx19:
 323 // end-sanitize-tx19
 324 {
 325   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 326   {
 327     ALU32_BEGIN (GPR[RS]);
 328     ALU32_ADD (GPR[RT]);
 329     ALU32_END (GPR[RD]);
 330   }
 331   TRACE_ALU_RESULT (GPR[RD]);
 332 }
 333
 334
 335
 336 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 337 "addi r<RT>, r<RS>, IMMEDIATE"
 338 *mipsI,mipsII,mipsIII,mipsIV:
 339 *vr5000:
 340 // start-sanitize-vr4320
 341 *vr4320:
 342 // end-sanitize-vr4320
 343 // start-sanitize-vr5400
 344 *vr5400:
 345 // end-sanitize-vr5400
 346 // start-sanitize-r5900
 347 *r5900:
 348 // end-sanitize-r5900
 349 *r3900:
 350 // start-sanitize-tx19
 351 *tx19:
 352 // end-sanitize-tx19
 353 {
 354   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 355   {
 356     ALU32_BEGIN (GPR[RS]);
 357     ALU32_ADD (EXTEND16 (IMMEDIATE));
 358     ALU32_END (GPR[RT]);
 359   }
 360   TRACE_ALU_RESULT (GPR[RT]);
 361 }
 362
 363
 364
 365 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 366 {
 367   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 368   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 369   TRACE_ALU_RESULT (GPR[rt]);
 370 }
 371
 372 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 373 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 374 *mipsI,mipsII,mipsIII,mipsIV:
 375 *vr5000:
 376 // start-sanitize-vr4320
 377 *vr4320:
 378 // end-sanitize-vr4320
 379 // start-sanitize-vr5400
 380 *vr5400:
 381 // end-sanitize-vr5400
 382 // start-sanitize-r5900
 383 *r5900:
 384 // end-sanitize-r5900
 385 *r3900:
 386 // start-sanitize-tx19
 387 *tx19:
 388 // end-sanitize-tx19
 389 {
 390   do_addiu (SD_, RS, RT, IMMEDIATE);
 391 }
 392
 393
 394
 395 :function:::void:do_addu:int rs, int rt, int rd
 396 {
 397   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 398   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 399   TRACE_ALU_RESULT (GPR[rd]);
 400 }
 401
 402 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 403 "addu r<RD>, r<RS>, r<RT>"
 404 *mipsI,mipsII,mipsIII,mipsIV:
 405 *vr5000:
 406 // start-sanitize-vr4320
 407 *vr4320:
 408 // end-sanitize-vr4320
 409 // start-sanitize-vr5400
 410 *vr5400:
 411 // end-sanitize-vr5400
 412 // start-sanitize-r5900
 413 *r5900:
 414 // end-sanitize-r5900
 415 *r3900:
 416 // start-sanitize-tx19
 417 *tx19:
 418 // end-sanitize-tx19
 419 {
 420   do_addu (SD_, RS, RT, RD);
 421 }
 422
 423
 424
 425 :function:::void:do_and:int rs, int rt, int rd
 426 {
 427   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 428   GPR[rd] = GPR[rs] & GPR[rt];
 429   TRACE_ALU_RESULT (GPR[rd]);
 430 }
 431
 432 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 433 "and r<RD>, r<RS>, r<RT>"
 434 *mipsI,mipsII,mipsIII,mipsIV:
 435 *vr5000:
 436 // start-sanitize-vr4320
 437 *vr4320:
 438 // end-sanitize-vr4320
 439 // start-sanitize-vr5400
 440 *vr5400:
 441 // end-sanitize-vr5400
 442 // start-sanitize-r5900
 443 *r5900:
 444 // end-sanitize-r5900
 445 *r3900:
 446 // start-sanitize-tx19
 447 *tx19:
 448 // end-sanitize-tx19
 449 {
 450   do_and (SD_, RS, RT, RD);
 451 }
 452
 453
 454
 455 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 456 "and r<RT>, r<RS>, <IMMEDIATE>"
 457 *mipsI,mipsII,mipsIII,mipsIV:
 458 *vr5000:
 459 // start-sanitize-vr4320
 460 *vr4320:
 461 // end-sanitize-vr4320
 462 // start-sanitize-vr5400
 463 *vr5400:
 464 // end-sanitize-vr5400
 465 // start-sanitize-r5900
 466 *r5900:
 467 // end-sanitize-r5900
 468 *r3900:
 469 // start-sanitize-tx19
 470 *tx19:
 471 // end-sanitize-tx19
 472 {
 473   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 474   GPR[RT] = GPR[RS] & IMMEDIATE;
 475   TRACE_ALU_RESULT (GPR[RT]);
 476 }
 477
 478
 479
 480 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 481 "beq r<RS>, r<RT>, <OFFSET>"
 482 *mipsI,mipsII,mipsIII,mipsIV:
 483 *vr5000:
 484 // start-sanitize-vr4320
 485 *vr4320:
 486 // end-sanitize-vr4320
 487 // start-sanitize-vr5400
 488 *vr5400:
 489 // end-sanitize-vr5400
 490 // start-sanitize-r5900
 491 *r5900:
 492 // end-sanitize-r5900
 493 *r3900:
 494 // start-sanitize-tx19
 495 *tx19:
 496 // end-sanitize-tx19
 497 {
 498   address_word offset = EXTEND16 (OFFSET) << 2;
 499   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 500     DELAY_SLOT (NIA + offset);
 501 }
 502
 503
 504
 505 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 506 "beql r<RS>, r<RT>, <OFFSET>"
 507 *mipsII:
 508 *mipsIII:
 509 *mipsIV:
 510 *vr5000:
 511 // start-sanitize-vr4320
 512 *vr4320:
 513 // end-sanitize-vr4320
 514 // start-sanitize-vr5400
 515 *vr5400:
 516 // end-sanitize-vr5400
 517 // start-sanitize-r5900
 518 *r5900:
 519 // end-sanitize-r5900
 520 *r3900:
 521 // start-sanitize-tx19
 522 *tx19:
 523 // end-sanitize-tx19
 524 {
 525   address_word offset = EXTEND16 (OFFSET) << 2;
 526   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 527     DELAY_SLOT (NIA + offset);
 528   else
 529     NULLIFY_NEXT_INSTRUCTION ();
 530 }
 531
 532
 533
 534 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 535 "bgez r<RS>, <OFFSET>"
 536 *mipsI,mipsII,mipsIII,mipsIV:
 537 *vr5000:
 538 // start-sanitize-vr4320
 539 *vr4320:
 540 // end-sanitize-vr4320
 541 // start-sanitize-vr5400
 542 *vr5400:
 543 // end-sanitize-vr5400
 544 // start-sanitize-r5900
 545 *r5900:
 546 // end-sanitize-r5900
 547 *r3900:
 548 // start-sanitize-tx19
 549 *tx19:
 550 // end-sanitize-tx19
 551 {
 552   address_word offset = EXTEND16 (OFFSET) << 2;
 553   if ((signed_word) GPR[RS] >= 0)
 554     DELAY_SLOT (NIA + offset);
 555 }
 556
 557
 558
 559 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 560 "bgezal r<RS>, <OFFSET>"
 561 *mipsI,mipsII,mipsIII,mipsIV:
 562 *vr5000:
 563 // start-sanitize-vr4320
 564 *vr4320:
 565 // end-sanitize-vr4320
 566 // start-sanitize-vr5400
 567 *vr5400:
 568 // end-sanitize-vr5400
 569 // start-sanitize-r5900
 570 *r5900:
 571 // end-sanitize-r5900
 572 *r3900:
 573 // start-sanitize-tx19
 574 *tx19:
 575 // end-sanitize-tx19
 576 {
 577   address_word offset = EXTEND16 (OFFSET) << 2;
 578   RA = (CIA + 8);
 579   if ((signed_word) GPR[RS] >= 0)
 580     DELAY_SLOT (NIA + offset);
 581 }
 582
 583
 584
 585 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 586 "bgezall r<RS>, <OFFSET>"
 587 *mipsII:
 588 *mipsIII:
 589 *mipsIV:
 590 *vr5000:
 591 // start-sanitize-vr4320
 592 *vr4320:
 593 // end-sanitize-vr4320
 594 // start-sanitize-vr5400
 595 *vr5400:
 596 // end-sanitize-vr5400
 597 // start-sanitize-r5900
 598 *r5900:
 599 // end-sanitize-r5900
 600 *r3900:
 601 // start-sanitize-tx19
 602 *tx19:
 603 // end-sanitize-tx19
 604 {
 605   address_word offset = EXTEND16 (OFFSET) << 2;
 606   RA = (CIA + 8);
 607   /* NOTE: The branch occurs AFTER the next instruction has been
 608      executed */
 609   if ((signed_word) GPR[RS] >= 0)
 610     DELAY_SLOT (NIA + offset);
 611   else
 612     NULLIFY_NEXT_INSTRUCTION ();
 613 }
 614
 615
 616
 617 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 618 "bgezl r<RS>, <OFFSET>"
 619 *mipsII:
 620 *mipsIII:
 621 *mipsIV:
 622 *vr5000:
 623 // start-sanitize-vr4320
 624 *vr4320:
 625 // end-sanitize-vr4320
 626 // start-sanitize-vr5400
 627 *vr5400:
 628 // end-sanitize-vr5400
 629 // start-sanitize-r5900
 630 *r5900:
 631 // end-sanitize-r5900
 632 *r3900:
 633 // start-sanitize-tx19
 634 *tx19:
 635 // end-sanitize-tx19
 636 {
 637   address_word offset = EXTEND16 (OFFSET) << 2;
 638   if ((signed_word) GPR[RS] >= 0)
 639     DELAY_SLOT (NIA + offset);
 640   else
 641     NULLIFY_NEXT_INSTRUCTION ();
 642 }
 643
 644
 645
 646 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 647 "bgtz r<RS>, <OFFSET>"
 648 *mipsI,mipsII,mipsIII,mipsIV:
 649 *vr5000:
 650 // start-sanitize-vr4320
 651 *vr4320:
 652 // end-sanitize-vr4320
 653 // start-sanitize-vr5400
 654 *vr5400:
 655 // end-sanitize-vr5400
 656 // start-sanitize-r5900
 657 *r5900:
 658 // end-sanitize-r5900
 659 *r3900:
 660 // start-sanitize-tx19
 661 *tx19:
 662 // end-sanitize-tx19
 663 {
 664   address_word offset = EXTEND16 (OFFSET) << 2;
 665   if ((signed_word) GPR[RS] > 0)
 666     DELAY_SLOT (NIA + offset);
 667 }
 668
 669
 670
 671 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 672 "bgtzl r<RS>, <OFFSET>"
 673 *mipsII:
 674 *mipsIII:
 675 *mipsIV:
 676 *vr5000:
 677 // start-sanitize-vr4320
 678 *vr4320:
 679 // end-sanitize-vr4320
 680 // start-sanitize-vr5400
 681 *vr5400:
 682 // end-sanitize-vr5400
 683 // start-sanitize-r5900
 684 *r5900:
 685 // end-sanitize-r5900
 686 *r3900:
 687 // start-sanitize-tx19
 688 *tx19:
 689 // end-sanitize-tx19
 690 {
 691   address_word offset = EXTEND16 (OFFSET) << 2;
 692   /* NOTE: The branch occurs AFTER the next instruction has been
 693      executed */
 694   if ((signed_word) GPR[RS] > 0)
 695     DELAY_SLOT (NIA + offset);
 696   else
 697     NULLIFY_NEXT_INSTRUCTION ();
 698 }
 699
 700
 701
 702 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 703 "blez r<RS>, <OFFSET>"
 704 *mipsI,mipsII,mipsIII,mipsIV:
 705 *vr5000:
 706 // start-sanitize-vr4320
 707 *vr4320:
 708 // end-sanitize-vr4320
 709 // start-sanitize-vr5400
 710 *vr5400:
 711 // end-sanitize-vr5400
 712 // start-sanitize-r5900
 713 *r5900:
 714 // end-sanitize-r5900
 715 *r3900:
 716 // start-sanitize-tx19
 717 *tx19:
 718 // end-sanitize-tx19
 719 {
 720   address_word offset = EXTEND16 (OFFSET) << 2;
 721   /* NOTE: The branch occurs AFTER the next instruction has been
 722      executed */
 723   if ((signed_word) GPR[RS] <= 0)
 724     DELAY_SLOT (NIA + offset);
 725 }
 726
 727
 728
 729 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 730 "bgezl r<RS>, <OFFSET>"
 731 *mipsII:
 732 *mipsIII:
 733 *mipsIV:
 734 *vr5000:
 735 // start-sanitize-vr4320
 736 *vr4320:
 737 // end-sanitize-vr4320
 738 // start-sanitize-vr5400
 739 *vr5400:
 740 // end-sanitize-vr5400
 741 // start-sanitize-r5900
 742 *r5900:
 743 // end-sanitize-r5900
 744 *r3900:
 745 // start-sanitize-tx19
 746 *tx19:
 747 // end-sanitize-tx19
 748 {
 749   address_word offset = EXTEND16 (OFFSET) << 2;
 750   if ((signed_word) GPR[RS] <= 0)
 751     DELAY_SLOT (NIA + offset);
 752   else
 753     NULLIFY_NEXT_INSTRUCTION ();
 754 }
 755
 756
 757
 758 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 759 "bltz r<RS>, <OFFSET>"
 760 *mipsI,mipsII,mipsIII,mipsIV:
 761 *vr5000:
 762 // start-sanitize-vr4320
 763 *vr4320:
 764 // end-sanitize-vr4320
 765 // start-sanitize-vr5400
 766 *vr5400:
 767 // end-sanitize-vr5400
 768 // start-sanitize-r5900
 769 *r5900:
 770 // end-sanitize-r5900
 771 *r3900:
 772 // start-sanitize-tx19
 773 *tx19:
 774 // end-sanitize-tx19
 775 {
 776   address_word offset = EXTEND16 (OFFSET) << 2;
 777   if ((signed_word) GPR[RS] < 0)
 778     DELAY_SLOT (NIA + offset);
 779 }
 780
 781
 782
 783 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 784 "bltzal r<RS>, <OFFSET>"
 785 *mipsI,mipsII,mipsIII,mipsIV:
 786 *vr5000:
 787 // start-sanitize-vr4320
 788 *vr4320:
 789 // end-sanitize-vr4320
 790 // start-sanitize-vr5400
 791 *vr5400:
 792 // end-sanitize-vr5400
 793 // start-sanitize-r5900
 794 *r5900:
 795 // end-sanitize-r5900
 796 *r3900:
 797 // start-sanitize-tx19
 798 *tx19:
 799 // end-sanitize-tx19
 800 {
 801   address_word offset = EXTEND16 (OFFSET) << 2;
 802   RA = (CIA + 8);
 803   /* NOTE: The branch occurs AFTER the next instruction has been
 804      executed */
 805   if ((signed_word) GPR[RS] < 0)
 806     DELAY_SLOT (NIA + offset);
 807 }
 808
 809
 810
 811 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 812 "bltzall r<RS>, <OFFSET>"
 813 *mipsII:
 814 *mipsIII:
 815 *mipsIV:
 816 *vr5000:
 817 // start-sanitize-vr4320
 818 *vr4320:
 819 // end-sanitize-vr4320
 820 // start-sanitize-vr5400
 821 *vr5400:
 822 // end-sanitize-vr5400
 823 // start-sanitize-r5900
 824 *r5900:
 825 // end-sanitize-r5900
 826 *r3900:
 827 // start-sanitize-tx19
 828 *tx19:
 829 // end-sanitize-tx19
 830 {
 831   address_word offset = EXTEND16 (OFFSET) << 2;
 832   RA = (CIA + 8);
 833   if ((signed_word) GPR[RS] < 0)
 834     DELAY_SLOT (NIA + offset);
 835   else
 836     NULLIFY_NEXT_INSTRUCTION ();
 837 }
 838
 839
 840
 841 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 842 "bltzl r<RS>, <OFFSET>"
 843 *mipsII:
 844 *mipsIII:
 845 *mipsIV:
 846 *vr5000:
 847 // start-sanitize-vr4320
 848 *vr4320:
 849 // end-sanitize-vr4320
 850 // start-sanitize-vr5400
 851 *vr5400:
 852 // end-sanitize-vr5400
 853 // start-sanitize-r5900
 854 *r5900:
 855 // end-sanitize-r5900
 856 *r3900:
 857 // start-sanitize-tx19
 858 *tx19:
 859 // end-sanitize-tx19
 860 {
 861   address_word offset = EXTEND16 (OFFSET) << 2;
 862   /* NOTE: The branch occurs AFTER the next instruction has been
 863      executed */
 864   if ((signed_word) GPR[RS] < 0)
 865     DELAY_SLOT (NIA + offset);
 866   else
 867     NULLIFY_NEXT_INSTRUCTION ();
 868 }
 869
 870
 871
 872 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 873 "bne r<RS>, r<RT>, <OFFSET>"
 874 *mipsI,mipsII,mipsIII,mipsIV:
 875 *vr5000:
 876 // start-sanitize-vr4320
 877 *vr4320:
 878 // end-sanitize-vr4320
 879 // start-sanitize-vr5400
 880 *vr5400:
 881 // end-sanitize-vr5400
 882 // start-sanitize-r5900
 883 *r5900:
 884 // end-sanitize-r5900
 885 *r3900:
 886 // start-sanitize-tx19
 887 *tx19:
 888 // end-sanitize-tx19
 889 {
 890   address_word offset = EXTEND16 (OFFSET) << 2;
 891   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 892     DELAY_SLOT (NIA + offset);
 893 }
 894
 895
 896
 897 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 898 "bnel r<RS>, r<RT>, <OFFSET>"
 899 *mipsII:
 900 *mipsIII:
 901 *mipsIV:
 902 *vr5000:
 903 // start-sanitize-vr4320
 904 *vr4320:
 905 // end-sanitize-vr4320
 906 // start-sanitize-vr5400
 907 *vr5400:
 908 // end-sanitize-vr5400
 909 // start-sanitize-r5900
 910 *r5900:
 911 // end-sanitize-r5900
 912 *r3900:
 913 // start-sanitize-tx19
 914 *tx19:
 915 // end-sanitize-tx19
 916 {
 917   address_word offset = EXTEND16 (OFFSET) << 2;
 918   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 919     DELAY_SLOT (NIA + offset);
 920   else
 921     NULLIFY_NEXT_INSTRUCTION ();
 922 }
 923
 924
 925
 926 000000,20.CODE,001101:SPECIAL:32::BREAK
 927 "break"
 928 *mipsI,mipsII,mipsIII,mipsIV:
 929 *vr5000:
 930 // start-sanitize-vr4320
 931 *vr4320:
 932 // end-sanitize-vr4320
 933 // start-sanitize-vr5400
 934 *vr5400:
 935 // end-sanitize-vr5400
 936 // start-sanitize-r5900
 937 *r5900:
 938 // end-sanitize-r5900
 939 *r3900:
 940 // start-sanitize-tx19
 941 *tx19:
 942 // end-sanitize-tx19
 943 {
 944   /* Check for some break instruction which are reserved for use by the simulator.  */
 945   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 946   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 947       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 948     {
 949       sim_engine_halt (SD, CPU, NULL, cia,
 950                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 951     }
 952   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 953            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 954     {
 955       if (STATE & simDELAYSLOT)
 956         PC = cia - 4; /* reference the branch instruction */
 957       else
 958         PC = cia;
 959       sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
 960     }
 961 // start-sanitize-sky
 962   else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
 963     {
 964       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
 965     }
 966   else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
 967     {
 968       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
 969     }
 970 // end-sanitize-sky
 971
 972   /* If we get this far, we're not an instruction reserved by the sim.  Raise
 973      the exception. */
 974   SignalException(BreakPoint, instruction_0);
 975 }
 976
 977
 978
 979
 980
 981
 982 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 983 "dadd r<RD>, r<RS>, r<RT>"
 984 *mipsIII:
 985 *mipsIV:
 986 *vr5000:
 987 // start-sanitize-vr4320
 988 *vr4320:
 989 // end-sanitize-vr4320
 990 // start-sanitize-vr5400
 991 *vr5400:
 992 // end-sanitize-vr5400
 993 // start-sanitize-r5900
 994 *r5900:
 995 // end-sanitize-r5900
 996 // start-sanitize-tx19
 997 *tx19:
 998 // end-sanitize-tx19
 999 {
1000   /* this check's for overflow */
1001   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1002   {
1003     ALU64_BEGIN (GPR[RS]);
1004     ALU64_ADD (GPR[RT]);
1005     ALU64_END (GPR[RD]);
1006   }
1007   TRACE_ALU_RESULT (GPR[RD]);
1008 }
1009
1010
1011
1012 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1013 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1014 *mipsIII:
1015 *mipsIV:
1016 *vr5000:
1017 // start-sanitize-vr4320
1018 *vr4320:
1019 // end-sanitize-vr4320
1020 // start-sanitize-vr5400
1021 *vr5400:
1022 // end-sanitize-vr5400
1023 // start-sanitize-r5900
1024 *r5900:
1025 // end-sanitize-r5900
1026 // start-sanitize-tx19
1027 *tx19:
1028 // end-sanitize-tx19
1029 {
1030   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1031   {
1032     ALU64_BEGIN (GPR[RS]);
1033     ALU64_ADD (EXTEND16 (IMMEDIATE));
1034     ALU64_END (GPR[RT]);
1035   }
1036   TRACE_ALU_RESULT (GPR[RT]);
1037 }
1038
1039
1040
1041 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1042 {
1043   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1044   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1045   TRACE_ALU_RESULT (GPR[rt]);
1046 }
1047
1048 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1049 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1050 *mipsIII:
1051 *mipsIV:
1052 *vr5000:
1053 // start-sanitize-vr4320
1054 *vr4320:
1055 // end-sanitize-vr4320
1056 // start-sanitize-vr5400
1057 *vr5400:
1058 // end-sanitize-vr5400
1059 // start-sanitize-r5900
1060 *r5900:
1061 // end-sanitize-r5900
1062 // start-sanitize-tx19
1063 *tx19:
1064 // end-sanitize-tx19
1065 {
1066   do_daddiu (SD_, RS, RT, IMMEDIATE);
1067 }
1068
1069
1070
1071 :function:::void:do_daddu:int rs, int rt, int rd
1072 {
1073   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1074   GPR[rd] = GPR[rs] + GPR[rt];
1075   TRACE_ALU_RESULT (GPR[rd]);
1076 }
1077
1078 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1079 "daddu r<RD>, r<RS>, r<RT>"
1080 *mipsIII:
1081 *mipsIV:
1082 *vr5000:
1083 // start-sanitize-vr4320
1084 *vr4320:
1085 // end-sanitize-vr4320
1086 // start-sanitize-vr5400
1087 *vr5400:
1088 // end-sanitize-vr5400
1089 // start-sanitize-r5900
1090 *r5900:
1091 // end-sanitize-r5900
1092 // start-sanitize-tx19
1093 *tx19:
1094 // end-sanitize-tx19
1095 {
1096   do_daddu (SD_, RS, RT, RD);
1097 }
1098
1099
1100
1101 :function:64::void:do_ddiv:int rs, int rt
1102 {
1103   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1104   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1105   {
1106     signed64 n = GPR[rs];
1107     signed64 d = GPR[rt];
1108     if (d == 0)
1109       {
1110         LO = SIGNED64 (0x8000000000000000);
1111         HI = 0;
1112       }
1113     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1114       {
1115         LO = SIGNED64 (0x8000000000000000);
1116         HI = 0;
1117       }
1118     else
1119       {
1120         LO = (n / d);
1121         HI = (n % d);
1122       }
1123   }
1124   TRACE_ALU_RESULT2 (HI, LO);
1125 }
1126
1127 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1128 "ddiv r<RS>, r<RT>"
1129 *mipsIII:
1130 *mipsIV:
1131 *vr5000:
1132 // start-sanitize-vr4320
1133 *vr4320:
1134 // end-sanitize-vr4320
1135 // start-sanitize-vr5400
1136 *vr5400:
1137 // end-sanitize-vr5400
1138 // start-sanitize-r5900
1139 *r5900:
1140 // end-sanitize-r5900
1141 // start-sanitize-tx19
1142 *tx19:
1143 // end-sanitize-tx19
1144 {
1145   do_ddiv (SD_, RS, RT);
1146 }
1147
1148
1149
1150 :function:64::void:do_ddivu:int rs, int rt
1151 {
1152   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1153   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1154   {
1155     unsigned64 n = GPR[rs];
1156     unsigned64 d = GPR[rt];
1157     if (d == 0)
1158       {
1159         LO = SIGNED64 (0x8000000000000000);
1160         HI = 0;
1161       }
1162     else
1163       {
1164         LO = (n / d);
1165         HI = (n % d);
1166       }
1167   }
1168   TRACE_ALU_RESULT2 (HI, LO);
1169 }
1170
1171 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1172 "ddivu r<RS>, r<RT>"
1173 *mipsIII:
1174 *mipsIV:
1175 *vr5000:
1176 // start-sanitize-vr4320
1177 *vr4320:
1178 // end-sanitize-vr4320
1179 // start-sanitize-vr5400
1180 *vr5400:
1181 // end-sanitize-vr5400
1182 // start-sanitize-tx19
1183 *tx19:
1184 // end-sanitize-tx19
1185 {
1186   do_ddivu (SD_, RS, RT);
1187 }
1188
1189
1190
1191 :function:::void:do_div:int rs, int rt
1192 {
1193   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1194   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1195   {
1196     signed32 n = GPR[rs];
1197     signed32 d = GPR[rt];
1198     if (d == 0)
1199       {
1200         LO = EXTEND32 (0x80000000);
1201         HI = EXTEND32 (0);
1202       }
1203     else if (n == SIGNED32 (0x80000000) && d == -1)
1204       {
1205         LO = EXTEND32 (0x80000000);
1206         HI = EXTEND32 (0);
1207       }
1208     else
1209       {
1210         LO = EXTEND32 (n / d);
1211         HI = EXTEND32 (n % d);
1212       }
1213   }
1214   TRACE_ALU_RESULT2 (HI, LO);
1215 }
1216
1217 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1218 "div r<RS>, r<RT>"
1219 *mipsI,mipsII,mipsIII,mipsIV:
1220 *vr5000:
1221 // start-sanitize-vr4320
1222 *vr4320:
1223 // end-sanitize-vr4320
1224 // start-sanitize-vr5400
1225 *vr5400:
1226 // end-sanitize-vr5400
1227 // start-sanitize-r5900
1228 *r5900:
1229 // end-sanitize-r5900
1230 *r3900:
1231 // start-sanitize-tx19
1232 *tx19:
1233 // end-sanitize-tx19
1234 {
1235   do_div (SD_, RS, RT);
1236 }
1237
1238
1239
1240 :function:::void:do_divu:int rs, int rt
1241 {
1242   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1243   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1244   {
1245     unsigned32 n = GPR[rs];
1246     unsigned32 d = GPR[rt];
1247     if (d == 0)
1248       {
1249         LO = EXTEND32 (0x80000000);
1250         HI = EXTEND32 (0);
1251       }
1252    else
1253      {
1254        LO = EXTEND32 (n / d);
1255        HI = EXTEND32 (n % d);
1256      }
1257   }
1258   TRACE_ALU_RESULT2 (HI, LO);
1259 }
1260
1261 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1262 "divu r<RS>, r<RT>"
1263 *mipsI,mipsII,mipsIII,mipsIV:
1264 *vr5000:
1265 // start-sanitize-vr4320
1266 *vr4320:
1267 // end-sanitize-vr4320
1268 // start-sanitize-vr5400
1269 *vr5400:
1270 // end-sanitize-vr5400
1271 // start-sanitize-r5900
1272 *r5900:
1273 // end-sanitize-r5900
1274 *r3900:
1275 // start-sanitize-tx19
1276 *tx19:
1277 // end-sanitize-tx19
1278 {
1279   do_divu (SD_, RS, RT);
1280 }
1281
1282
1283
1284 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1285 {
1286   unsigned64 lo;
1287   unsigned64 hi;
1288   unsigned64 m00;
1289   unsigned64 m01;
1290   unsigned64 m10;
1291   unsigned64 m11;
1292   unsigned64 mid;
1293   int sign;
1294   unsigned64 op1 = GPR[rs];
1295   unsigned64 op2 = GPR[rt];
1296   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1297   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1298   /* make signed multiply unsigned */
1299   sign = 0;
1300   if (signed_p)
1301     {
1302       if (op1 < 0)
1303         {
1304           op1 = - op1;
1305           ++sign;
1306         }
1307       if (op2 < 0)
1308         {
1309           op2 = - op2;
1310           ++sign;
1311         }
1312     }
1313   /* multuply out the 4 sub products */
1314   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1315   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1316   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1317   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1318   /* add the products */
1319   mid = ((unsigned64) VH4_8 (m00)
1320          + (unsigned64) VL4_8 (m10)
1321          + (unsigned64) VL4_8 (m01));
1322   lo = U8_4 (mid, m00);
1323   hi = (m11
1324         + (unsigned64) VH4_8 (mid)
1325         + (unsigned64) VH4_8 (m01)
1326         + (unsigned64) VH4_8 (m10));
1327   /* fix the sign */
1328   if (sign & 1)
1329     {
1330       lo = -lo;
1331       if (lo == 0)
1332         hi = -hi;
1333       else
1334         hi = -hi - 1;
1335     }
1336   /* save the result HI/LO (and a gpr) */
1337   LO = lo;
1338   HI = hi;
1339   if (rd != 0)
1340     GPR[rd] = lo;
1341   TRACE_ALU_RESULT2 (HI, LO);
1342 }
1343
1344 :function:::void:do_dmult:int rs, int rt, int rd
1345 {
1346   do_dmultx (SD_, rs, rt, rd, 1);
1347 }
1348
1349 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1350 "dmult r<RS>, r<RT>"
1351 *mipsIII,mipsIV:
1352 // start-sanitize-tx19
1353 *tx19:
1354 // end-sanitize-tx19
1355 // start-sanitize-vr4320
1356 *vr4320:
1357 // end-sanitize-vr4320
1358 {
1359   do_dmult (SD_, RS, RT, 0);
1360 }
1361
1362 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1363 "dmult r<RS>, r<RT>":RD == 0
1364 "dmult r<RD>, r<RS>, r<RT>"
1365 *vr5000:
1366 // start-sanitize-vr5400
1367 *vr5400:
1368 // end-sanitize-vr5400
1369 {
1370   do_dmult (SD_, RS, RT, RD);
1371 }
1372
1373
1374
1375 :function:::void:do_dmultu:int rs, int rt, int rd
1376 {
1377   do_dmultx (SD_, rs, rt, rd, 0);
1378 }
1379
1380 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1381 "dmultu r<RS>, r<RT>"
1382 *mipsIII,mipsIV:
1383 // start-sanitize-tx19
1384 *tx19:
1385 // end-sanitize-tx19
1386 // start-sanitize-vr4320
1387 *vr4320:
1388 // end-sanitize-vr4320
1389 {
1390   do_dmultu (SD_, RS, RT, 0);
1391 }
1392
1393 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1394 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1395 "dmultu r<RS>, r<RT>"
1396 *vr5000:
1397 // start-sanitize-vr5400
1398 *vr5400:
1399 // end-sanitize-vr5400
1400 {
1401   do_dmultu (SD_, RS, RT, RD);
1402 }
1403
1404
1405
1406 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1407 "dsll r<RD>, r<RT>, <SHIFT>"
1408 *mipsIII:
1409 *mipsIV:
1410 *vr5000:
1411 // start-sanitize-vr4320
1412 *vr4320:
1413 // end-sanitize-vr4320
1414 // start-sanitize-vr5400
1415 *vr5400:
1416 // end-sanitize-vr5400
1417 // start-sanitize-r5900
1418 *r5900:
1419 // end-sanitize-r5900
1420 // start-sanitize-tx19
1421 *tx19:
1422 // end-sanitize-tx19
1423 {
1424   int s = SHIFT;
1425   GPR[RD] = GPR[RT] << s;
1426 }
1427
1428
1429 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1430 "dsll32 r<RD>, r<RT>, <SHIFT>"
1431 *mipsIII:
1432 *mipsIV:
1433 *vr5000:
1434 // start-sanitize-vr4320
1435 *vr4320:
1436 // end-sanitize-vr4320
1437 // start-sanitize-vr5400
1438 *vr5400:
1439 // end-sanitize-vr5400
1440 // start-sanitize-r5900
1441 *r5900:
1442 // end-sanitize-r5900
1443 // start-sanitize-tx19
1444 *tx19:
1445 // end-sanitize-tx19
1446 {
1447   int s = 32 + SHIFT;
1448   GPR[RD] = GPR[RT] << s;
1449 }
1450
1451
1452
1453 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1454 "dsllv r<RD>, r<RT>, r<RS>"
1455 *mipsIII:
1456 *mipsIV:
1457 *vr5000:
1458 // start-sanitize-vr4320
1459 *vr4320:
1460 // end-sanitize-vr4320
1461 // start-sanitize-vr5400
1462 *vr5400:
1463 // end-sanitize-vr5400
1464 // start-sanitize-r5900
1465 *r5900:
1466 // end-sanitize-r5900
1467 // start-sanitize-tx19
1468 *tx19:
1469 // end-sanitize-tx19
1470 {
1471   int s = MASKED64 (GPR[RS], 5, 0);
1472   GPR[RD] = GPR[RT] << s;
1473 }
1474
1475
1476
1477 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1478 "dsra r<RD>, r<RT>, <SHIFT>"
1479 *mipsIII:
1480 *mipsIV:
1481 *vr5000:
1482 // start-sanitize-vr4320
1483 *vr4320:
1484 // end-sanitize-vr4320
1485 // start-sanitize-vr5400
1486 *vr5400:
1487 // end-sanitize-vr5400
1488 // start-sanitize-r5900
1489 *r5900:
1490 // end-sanitize-r5900
1491 // start-sanitize-tx19
1492 *tx19:
1493 // end-sanitize-tx19
1494 {
1495   int s = SHIFT;
1496   GPR[RD] = ((signed64) GPR[RT]) >> s;
1497 }
1498
1499
1500 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1501 "dsra32 r<RT>, r<RD>, <SHIFT>"
1502 *mipsIII:
1503 *mipsIV:
1504 *vr5000:
1505 // start-sanitize-vr4320
1506 *vr4320:
1507 // end-sanitize-vr4320
1508 // start-sanitize-vr5400
1509 *vr5400:
1510 // end-sanitize-vr5400
1511 // start-sanitize-r5900
1512 *r5900:
1513 // end-sanitize-r5900
1514 // start-sanitize-tx19
1515 *tx19:
1516 // end-sanitize-tx19
1517 {
1518   int s = 32 + SHIFT;
1519   GPR[RD] = ((signed64) GPR[RT]) >> s;
1520 }
1521
1522
1523 :function:::void:do_dsrav:int rs, int rt, int rd
1524 {
1525   int s = MASKED64 (GPR[rs], 5, 0);
1526   TRACE_ALU_INPUT2 (GPR[rt], s);
1527   GPR[rd] = ((signed64) GPR[rt]) >> s;
1528   TRACE_ALU_RESULT (GPR[rd]);
1529 }
1530
1531 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1532 "dsra32 r<RT>, r<RD>, r<RS>"
1533 *mipsIII:
1534 *mipsIV:
1535 *vr5000:
1536 // start-sanitize-vr4320
1537 *vr4320:
1538 // end-sanitize-vr4320
1539 // start-sanitize-vr5400
1540 *vr5400:
1541 // end-sanitize-vr5400
1542 // start-sanitize-r5900
1543 *r5900:
1544 // end-sanitize-r5900
1545 // start-sanitize-tx19
1546 *tx19:
1547 // end-sanitize-tx19
1548 {
1549   do_dsrav (SD_, RS, RT, RD);
1550 }
1551
1552
1553 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1554 "dsrl r<RD>, r<RT>, <SHIFT>"
1555 *mipsIII:
1556 *mipsIV:
1557 *vr5000:
1558 // start-sanitize-vr4320
1559 *vr4320:
1560 // end-sanitize-vr4320
1561 // start-sanitize-vr5400
1562 *vr5400:
1563 // end-sanitize-vr5400
1564 // start-sanitize-r5900
1565 *r5900:
1566 // end-sanitize-r5900
1567 // start-sanitize-tx19
1568 *tx19:
1569 // end-sanitize-tx19
1570 {
1571   int s = SHIFT;
1572   GPR[RD] = (unsigned64) GPR[RT] >> s;
1573 }
1574
1575
1576 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1577 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1578 *mipsIII:
1579 *mipsIV:
1580 *vr5000:
1581 // start-sanitize-vr4320
1582 *vr4320:
1583 // end-sanitize-vr4320
1584 // start-sanitize-vr5400
1585 *vr5400:
1586 // end-sanitize-vr5400
1587 // start-sanitize-r5900
1588 *r5900:
1589 // end-sanitize-r5900
1590 // start-sanitize-tx19
1591 *tx19:
1592 // end-sanitize-tx19
1593 {
1594   int s = 32 + SHIFT;
1595   GPR[RD] = (unsigned64) GPR[RT] >> s;
1596 }
1597
1598
1599 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1600 "dsrl32 r<RD>, r<RT>, r<RS>"
1601 *mipsIII:
1602 *mipsIV:
1603 *vr5000:
1604 // start-sanitize-vr4320
1605 *vr4320:
1606 // end-sanitize-vr4320
1607 // start-sanitize-vr5400
1608 *vr5400:
1609 // end-sanitize-vr5400
1610 // start-sanitize-r5900
1611 *r5900:
1612 // end-sanitize-r5900
1613 // start-sanitize-tx19
1614 *tx19:
1615 // end-sanitize-tx19
1616 {
1617   int s = MASKED64 (GPR[RS], 5, 0);
1618   GPR[RD] = (unsigned64) GPR[RT] >> s;
1619 }
1620
1621
1622 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1623 "dsub r<RD>, r<RS>, r<RT>"
1624 *mipsIII:
1625 *mipsIV:
1626 *vr5000:
1627 // start-sanitize-vr4320
1628 *vr4320:
1629 // end-sanitize-vr4320
1630 // start-sanitize-vr5400
1631 *vr5400:
1632 // end-sanitize-vr5400
1633 // start-sanitize-r5900
1634 *r5900:
1635 // end-sanitize-r5900
1636 // start-sanitize-tx19
1637 *tx19:
1638 // end-sanitize-tx19
1639 {
1640   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1641   {
1642     ALU64_BEGIN (GPR[RS]);
1643     ALU64_SUB (GPR[RT]);
1644     ALU64_END (GPR[RD]);
1645   }
1646   TRACE_ALU_RESULT (GPR[RD]);
1647 }
1648
1649
1650 :function:::void:do_dsubu:int rs, int rt, int rd
1651 {
1652   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1653   GPR[rd] = GPR[rs] - GPR[rt];
1654   TRACE_ALU_RESULT (GPR[rd]);
1655 }
1656
1657 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1658 "dsubu r<RD>, r<RS>, r<RT>"
1659 *mipsIII:
1660 *mipsIV:
1661 *vr5000:
1662 // start-sanitize-vr4320
1663 *vr4320:
1664 // end-sanitize-vr4320
1665 // start-sanitize-vr5400
1666 *vr5400:
1667 // end-sanitize-vr5400
1668 // start-sanitize-r5900
1669 *r5900:
1670 // end-sanitize-r5900
1671 // start-sanitize-tx19
1672 *tx19:
1673 // end-sanitize-tx19
1674 {
1675   do_dsubu (SD_, RS, RT, RD);
1676 }
1677
1678
1679 000010,26.INSTR_INDEX:NORMAL:32::J
1680 "j <INSTR_INDEX>"
1681 *mipsI,mipsII,mipsIII,mipsIV:
1682 *vr5000:
1683 // start-sanitize-vr4320
1684 *vr4320:
1685 // end-sanitize-vr4320
1686 // start-sanitize-vr5400
1687 *vr5400:
1688 // end-sanitize-vr5400
1689 // start-sanitize-r5900
1690 *r5900:
1691 // end-sanitize-r5900
1692 *r3900:
1693 // start-sanitize-tx19
1694 *tx19:
1695 // end-sanitize-tx19
1696 {
1697   /* NOTE: The region used is that of the delay slot NIA and NOT the
1698      current instruction */
1699   address_word region = (NIA & MASK (63, 28));
1700   DELAY_SLOT (region | (INSTR_INDEX << 2));
1701 }
1702
1703
1704 000011,26.INSTR_INDEX:NORMAL:32::JAL
1705 "jal <INSTR_INDEX>"
1706 *mipsI,mipsII,mipsIII,mipsIV:
1707 *vr5000:
1708 // start-sanitize-vr4320
1709 *vr4320:
1710 // end-sanitize-vr4320
1711 // start-sanitize-vr5400
1712 *vr5400:
1713 // end-sanitize-vr5400
1714 // start-sanitize-r5900
1715 *r5900:
1716 // end-sanitize-r5900
1717 *r3900:
1718 // start-sanitize-tx19
1719 *tx19:
1720 // end-sanitize-tx19
1721 {
1722   /* NOTE: The region used is that of the delay slot and NOT the
1723      current instruction */
1724   address_word region = (NIA & MASK (63, 28));
1725   GPR[31] = CIA + 8;
1726   DELAY_SLOT (region | (INSTR_INDEX << 2));
1727 }
1728
1729
1730 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1731 "jalr r<RS>":RD == 31
1732 "jalr r<RD>, r<RS>"
1733 *mipsI,mipsII,mipsIII,mipsIV:
1734 *vr5000:
1735 // start-sanitize-vr4320
1736 *vr4320:
1737 // end-sanitize-vr4320
1738 // start-sanitize-vr5400
1739 *vr5400:
1740 // end-sanitize-vr5400
1741 // start-sanitize-r5900
1742 *r5900:
1743 // end-sanitize-r5900
1744 *r3900:
1745 // start-sanitize-tx19
1746 *tx19:
1747 // end-sanitize-tx19
1748 {
1749   address_word temp = GPR[RS];
1750   GPR[RD] = CIA + 8;
1751   DELAY_SLOT (temp);
1752 }
1753
1754
1755 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1756 "jr r<RS>"
1757 *mipsI,mipsII,mipsIII,mipsIV:
1758 *vr5000:
1759 // start-sanitize-vr4320
1760 *vr4320:
1761 // end-sanitize-vr4320
1762 // start-sanitize-vr5400
1763 *vr5400:
1764 // end-sanitize-vr5400
1765 // start-sanitize-r5900
1766 *r5900:
1767 // end-sanitize-r5900
1768 *r3900:
1769 // start-sanitize-tx19
1770 *tx19:
1771 // end-sanitize-tx19
1772 {
1773   DELAY_SLOT (GPR[RS]);
1774 }
1775
1776
1777 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1778 {
1779   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1780   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1781   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1782   unsigned int byte;
1783   address_word paddr;
1784   int uncached;
1785   unsigned64 memval;
1786   address_word vaddr;
1787
1788   vaddr = base + offset;
1789   if ((vaddr & access) != 0)
1790     SignalExceptionAddressLoad ();
1791   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1792   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1793   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1794   byte = ((vaddr & mask) ^ bigendiancpu);
1795   return (memval >> (8 * byte));
1796 }
1797
1798
1799 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1800 "lb r<RT>, <OFFSET>(r<BASE>)"
1801 *mipsI,mipsII,mipsIII,mipsIV:
1802 *vr5000:
1803 // start-sanitize-vr4320
1804 *vr4320:
1805 // end-sanitize-vr4320
1806 // start-sanitize-vr5400
1807 *vr5400:
1808 // end-sanitize-vr5400
1809 // start-sanitize-r5900
1810 *r5900:
1811 // end-sanitize-r5900
1812 *r3900:
1813 // start-sanitize-tx19
1814 *tx19:
1815 // end-sanitize-tx19
1816 {
1817   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1818 }
1819
1820
1821 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1822 "lbu r<RT>, <OFFSET>(r<BASE>)"
1823 *mipsI,mipsII,mipsIII,mipsIV:
1824 *vr5000:
1825 // start-sanitize-vr4320
1826 *vr4320:
1827 // end-sanitize-vr4320
1828 // start-sanitize-vr5400
1829 *vr5400:
1830 // end-sanitize-vr5400
1831 // start-sanitize-r5900
1832 *r5900:
1833 // end-sanitize-r5900
1834 *r3900:
1835 // start-sanitize-tx19
1836 *tx19:
1837 // end-sanitize-tx19
1838 {
1839   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1840 }
1841
1842
1843 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1844 "ld r<RT>, <OFFSET>(r<BASE>)"
1845 *mipsIII:
1846 *mipsIV:
1847 *vr5000:
1848 // start-sanitize-vr4320
1849 *vr4320:
1850 // end-sanitize-vr4320
1851 // start-sanitize-vr5400
1852 *vr5400:
1853 // end-sanitize-vr5400
1854 // start-sanitize-r5900
1855 *r5900:
1856 // end-sanitize-r5900
1857 // start-sanitize-tx19
1858 *tx19:
1859 // end-sanitize-tx19
1860 {
1861   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1862 }
1863
1864
1865 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1866 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1867 *mipsII:
1868 *mipsIII:
1869 *mipsIV:
1870 *vr5000:
1871 // start-sanitize-vr4320
1872 *vr4320:
1873 // end-sanitize-vr4320
1874 // start-sanitize-vr5400
1875 *vr5400:
1876 // end-sanitize-vr5400
1877 *r3900:
1878 // start-sanitize-tx19
1879 *tx19:
1880 // end-sanitize-tx19
1881 {
1882   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1883 }
1884
1885
1886
1887
1888 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1889 "ldl r<RT>, <OFFSET>(r<BASE>)"
1890 *mipsIII:
1891 *mipsIV:
1892 *vr5000:
1893 // start-sanitize-vr4320
1894 *vr4320:
1895 // end-sanitize-vr4320
1896 // start-sanitize-vr5400
1897 *vr5400:
1898 // end-sanitize-vr5400
1899 // start-sanitize-r5900
1900 *r5900:
1901 // end-sanitize-r5900
1902 // start-sanitize-tx19
1903 *tx19:
1904 // end-sanitize-tx19
1905 {
1906   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1907 }
1908
1909
1910 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1911 "ldr r<RT>, <OFFSET>(r<BASE>)"
1912 *mipsIII:
1913 *mipsIV:
1914 *vr5000:
1915 // start-sanitize-vr4320
1916 *vr4320:
1917 // end-sanitize-vr4320
1918 // start-sanitize-vr5400
1919 *vr5400:
1920 // end-sanitize-vr5400
1921 // start-sanitize-r5900
1922 *r5900:
1923 // end-sanitize-r5900
1924 // start-sanitize-tx19
1925 *tx19:
1926 // end-sanitize-tx19
1927 {
1928   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1929 }
1930
1931
1932 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1933 "lh r<RT>, <OFFSET>(r<BASE>)"
1934 *mipsI,mipsII,mipsIII,mipsIV:
1935 *vr5000:
1936 // start-sanitize-vr4320
1937 *vr4320:
1938 // end-sanitize-vr4320
1939 // start-sanitize-vr5400
1940 *vr5400:
1941 // end-sanitize-vr5400
1942 // start-sanitize-r5900
1943 *r5900:
1944 // end-sanitize-r5900
1945 *r3900:
1946 // start-sanitize-tx19
1947 *tx19:
1948 // end-sanitize-tx19
1949 {
1950   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1951 }
1952
1953
1954 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1955 "lhu r<RT>, <OFFSET>(r<BASE>)"
1956 *mipsI,mipsII,mipsIII,mipsIV:
1957 *vr5000:
1958 // start-sanitize-vr4320
1959 *vr4320:
1960 // end-sanitize-vr4320
1961 // start-sanitize-vr5400
1962 *vr5400:
1963 // end-sanitize-vr5400
1964 // start-sanitize-r5900
1965 *r5900:
1966 // end-sanitize-r5900
1967 *r3900:
1968 // start-sanitize-tx19
1969 *tx19:
1970 // end-sanitize-tx19
1971 {
1972   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1973 }
1974
1975
1976 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1977 "ll r<RT>, <OFFSET>(r<BASE>)"
1978 *mipsII:
1979 *mipsIII:
1980 *mipsIV:
1981 *vr5000:
1982 // start-sanitize-vr4320
1983 *vr4320:
1984 // end-sanitize-vr4320
1985 // start-sanitize-vr5400
1986 *vr5400:
1987 // end-sanitize-vr5400
1988 // start-sanitize-r5900
1989 *r5900:
1990 // end-sanitize-r5900
1991 // start-sanitize-tx19
1992 *tx19:
1993 // end-sanitize-tx19
1994 {
1995   unsigned32 instruction = instruction_0;
1996   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1997   int destreg = ((instruction >> 16) & 0x0000001F);
1998   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1999   {
2000     address_word vaddr = ((unsigned64)op1 + offset);
2001     address_word paddr;
2002     int uncached;
2003     if ((vaddr & 3) != 0)
2004       SignalExceptionAddressLoad();
2005     else
2006       {
2007         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2008           {
2009             unsigned64 memval = 0;
2010             unsigned64 memval1 = 0;
2011             unsigned64 mask = 0x7;
2012             unsigned int shift = 2;
2013             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2014             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2015             unsigned int byte;
2016             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2017             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2018             byte = ((vaddr & mask) ^ (bigend << shift));
2019             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2020             LLBIT = 1;
2021           }
2022       }
2023   }
2024 }
2025
2026
2027 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2028 "lld r<RT>, <OFFSET>(r<BASE>)"
2029 *mipsIII:
2030 *mipsIV:
2031 *vr5000:
2032 // start-sanitize-vr4320
2033 *vr4320:
2034 // end-sanitize-vr4320
2035 // start-sanitize-vr5400
2036 *vr5400:
2037 // end-sanitize-vr5400
2038 // start-sanitize-r5900
2039 *r5900:
2040 // end-sanitize-r5900
2041 // start-sanitize-tx19
2042 *tx19:
2043 // end-sanitize-tx19
2044 {
2045   unsigned32 instruction = instruction_0;
2046   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2047   int destreg = ((instruction >> 16) & 0x0000001F);
2048   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2049   {
2050     address_word vaddr = ((unsigned64)op1 + offset);
2051     address_word paddr;
2052     int uncached;
2053     if ((vaddr & 7) != 0)
2054       SignalExceptionAddressLoad();
2055     else
2056       {
2057         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2058           {
2059             unsigned64 memval = 0;
2060             unsigned64 memval1 = 0;
2061             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2062             GPR[destreg] = memval;
2063             LLBIT = 1;
2064           }
2065       }
2066   }
2067 }
2068
2069
2070 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2071 "lui r<RT>, <IMMEDIATE>"
2072 *mipsI,mipsII,mipsIII,mipsIV:
2073 *vr5000:
2074 // start-sanitize-vr4320
2075 *vr4320:
2076 // end-sanitize-vr4320
2077 // start-sanitize-vr5400
2078 *vr5400:
2079 // end-sanitize-vr5400
2080 // start-sanitize-r5900
2081 *r5900:
2082 // end-sanitize-r5900
2083 *r3900:
2084 // start-sanitize-tx19
2085 *tx19:
2086 // end-sanitize-tx19
2087 {
2088   TRACE_ALU_INPUT1 (IMMEDIATE);
2089   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2090   TRACE_ALU_RESULT (GPR[RT]);
2091 }
2092
2093
2094 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2095 "lw r<RT>, <OFFSET>(r<BASE>)"
2096 *mipsI,mipsII,mipsIII,mipsIV:
2097 *vr5000:
2098 // start-sanitize-vr4320
2099 *vr4320:
2100 // end-sanitize-vr4320
2101 // start-sanitize-vr5400
2102 *vr5400:
2103 // end-sanitize-vr5400
2104 // start-sanitize-r5900
2105 *r5900:
2106 // end-sanitize-r5900
2107 *r3900:
2108 // start-sanitize-tx19
2109 *tx19:
2110 // end-sanitize-tx19
2111 {
2112   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2113 }
2114
2115
2116 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2117 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2118 *mipsI,mipsII,mipsIII,mipsIV:
2119 *vr5000:
2120 // start-sanitize-vr4320
2121 *vr4320:
2122 // end-sanitize-vr4320
2123 // start-sanitize-vr5400
2124 *vr5400:
2125 // end-sanitize-vr5400
2126 // start-sanitize-r5900
2127 *r5900:
2128 // end-sanitize-r5900
2129 *r3900:
2130 // start-sanitize-tx19
2131 *tx19:
2132 // end-sanitize-tx19
2133 {
2134   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2135 }
2136
2137
2138 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2139 {
2140   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2141   address_word reverseendian = (ReverseEndian ? -1 : 0);
2142   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2143   unsigned int byte;
2144   unsigned int word;
2145   address_word paddr;
2146   int uncached;
2147   unsigned64 memval;
2148   address_word vaddr;
2149   int nr_lhs_bits;
2150   int nr_rhs_bits;
2151   unsigned_word lhs_mask;
2152   unsigned_word temp;
2153
2154   vaddr = base + offset;
2155   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2156   paddr = (paddr ^ (reverseendian & mask));
2157   if (BigEndianMem == 0)
2158     paddr = paddr & ~access;
2159
2160   /* compute where within the word/mem we are */
2161   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2162   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2163   nr_lhs_bits = 8 * byte + 8;
2164   nr_rhs_bits = 8 * access - 8 * byte;
2165   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2166
2167   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2168            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2169            (long) ((unsigned64) paddr >> 32), (long) paddr,
2170            word, byte, nr_lhs_bits, nr_rhs_bits); */
2171
2172   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2173   if (word == 0)
2174     {
2175       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2176       temp = (memval << nr_rhs_bits);
2177     }
2178   else
2179     {
2180       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2181       temp = (memval >> nr_lhs_bits);
2182     }
2183   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2184   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2185
2186   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2187            (long) ((unsigned64) memval >> 32), (long) memval,
2188            (long) ((unsigned64) temp >> 32), (long) temp,
2189            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2190            (long) (rt >> 32), (long) rt); */
2191   return rt;
2192 }
2193
2194
2195 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2196 "lwl r<RT>, <OFFSET>(r<BASE>)"
2197 *mipsI,mipsII,mipsIII,mipsIV:
2198 *vr5000:
2199 // start-sanitize-vr4320
2200 *vr4320:
2201 // end-sanitize-vr4320
2202 // start-sanitize-vr5400
2203 *vr5400:
2204 // end-sanitize-vr5400
2205 // start-sanitize-r5900
2206 *r5900:
2207 // end-sanitize-r5900
2208 *r3900:
2209 // start-sanitize-tx19
2210 *tx19:
2211 // end-sanitize-tx19
2212 {
2213   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2214 }
2215
2216
2217 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2218 {
2219   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2220   address_word reverseendian = (ReverseEndian ? -1 : 0);
2221   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2222   unsigned int byte;
2223   address_word paddr;
2224   int uncached;
2225   unsigned64 memval;
2226   address_word vaddr;
2227
2228   vaddr = base + offset;
2229   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2230   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2231   paddr = (paddr ^ (reverseendian & mask));
2232   if (BigEndianMem != 0)
2233     paddr = paddr & ~access;
2234   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2235   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2236   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2237   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2238      (long) paddr, byte, (long) paddr, (long) memval); */
2239   {
2240     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2241     rt &= ~screen;
2242     rt |= (memval >> (8 * byte)) & screen;
2243   }
2244   return rt;
2245 }
2246
2247
2248 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2249 "lwr r<RT>, <OFFSET>(r<BASE>)"
2250 *mipsI,mipsII,mipsIII,mipsIV:
2251 *vr5000:
2252 // start-sanitize-vr4320
2253 *vr4320:
2254 // end-sanitize-vr4320
2255 // start-sanitize-vr5400
2256 *vr5400:
2257 // end-sanitize-vr5400
2258 // start-sanitize-r5900
2259 *r5900:
2260 // end-sanitize-r5900
2261 *r3900:
2262 // start-sanitize-tx19
2263 *tx19:
2264 // end-sanitize-tx19
2265 {
2266   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2267 }
2268
2269
2270 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2271 "lwu r<RT>, <OFFSET>(r<BASE>)"
2272 *mipsIII:
2273 *mipsIV:
2274 *vr5000:
2275 // start-sanitize-vr4320
2276 *vr4320:
2277 // end-sanitize-vr4320
2278 // start-sanitize-vr5400
2279 *vr5400:
2280 // end-sanitize-vr5400
2281 // start-sanitize-r5900
2282 *r5900:
2283 // end-sanitize-r5900
2284 // start-sanitize-tx19
2285 *tx19:
2286 // end-sanitize-tx19
2287 {
2288   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2289 }
2290
2291
2292 :function:::void:do_mfhi:int rd
2293 {
2294   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2295   TRACE_ALU_INPUT1 (HI);
2296   GPR[rd] = HI;
2297   TRACE_ALU_RESULT (GPR[rd]);
2298 }
2299
2300 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2301 "mfhi r<RD>"
2302 *mipsI,mipsII,mipsIII,mipsIV:
2303 *vr5000:
2304 // start-sanitize-vr4320
2305 *vr4320:
2306 // end-sanitize-vr4320
2307 // start-sanitize-vr5400
2308 *vr5400:
2309 // end-sanitize-vr5400
2310 // start-sanitize-r5900
2311 *r5900:
2312 // end-sanitize-r5900
2313 *r3900:
2314 // start-sanitize-tx19
2315 *tx19:
2316 // end-sanitize-tx19
2317 {
2318   do_mfhi (SD_, RD);
2319 }
2320
2321
2322
2323 :function:::void:do_mflo:int rd
2324 {
2325   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2326   TRACE_ALU_INPUT1 (LO);
2327   GPR[rd] = LO;
2328   TRACE_ALU_RESULT (GPR[rd]);
2329 }
2330
2331 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2332 "mflo r<RD>"
2333 *mipsI,mipsII,mipsIII,mipsIV:
2334 *vr5000:
2335 // start-sanitize-vr4320
2336 *vr4320:
2337 // end-sanitize-vr4320
2338 // start-sanitize-vr5400
2339 *vr5400:
2340 // end-sanitize-vr5400
2341 // start-sanitize-r5900
2342 *r5900:
2343 // end-sanitize-r5900
2344 *r3900:
2345 // start-sanitize-tx19
2346 *tx19:
2347 // end-sanitize-tx19
2348 {
2349   do_mflo (SD_, RD);
2350 }
2351
2352
2353
2354 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2355 "movn r<RD>, r<RS>, r<RT>"
2356 *mipsIV:
2357 *vr5000:
2358 // start-sanitize-vr4320
2359 *vr4320:
2360 // end-sanitize-vr4320
2361 // start-sanitize-vr5400
2362 *vr5400:
2363 // end-sanitize-vr5400
2364 // start-sanitize-r5900
2365 *r5900:
2366 // end-sanitize-r5900
2367 {
2368   if (GPR[RT] != 0)
2369     GPR[RD] = GPR[RS];
2370 }
2371
2372
2373
2374 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2375 "movz r<RD>, r<RS>, r<RT>"
2376 *mipsIV:
2377 *vr5000:
2378 // start-sanitize-vr4320
2379 *vr4320:
2380 // end-sanitize-vr4320
2381 // start-sanitize-vr5400
2382 *vr5400:
2383 // end-sanitize-vr5400
2384 // start-sanitize-r5900
2385 *r5900:
2386 // end-sanitize-r5900
2387 {
2388   if (GPR[RT] == 0)
2389     GPR[RD] = GPR[RS];
2390 }
2391
2392
2393
2394 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2395 "mthi r<RS>"
2396 *mipsI,mipsII,mipsIII,mipsIV:
2397 *vr5000:
2398 // start-sanitize-vr4320
2399 *vr4320:
2400 // end-sanitize-vr4320
2401 // start-sanitize-vr5400
2402 *vr5400:
2403 // end-sanitize-vr5400
2404 // start-sanitize-r5900
2405 *r5900:
2406 // end-sanitize-r5900
2407 *r3900:
2408 // start-sanitize-tx19
2409 *tx19:
2410 // end-sanitize-tx19
2411 {
2412   check_mt_hilo (SD_, HIHISTORY);
2413   HI = GPR[RS];
2414 }
2415
2416
2417
2418 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2419 "mtlo r<RS>"
2420 *mipsI,mipsII,mipsIII,mipsIV:
2421 *vr5000:
2422 // start-sanitize-vr4320
2423 *vr4320:
2424 // end-sanitize-vr4320
2425 // start-sanitize-vr5400
2426 *vr5400:
2427 // end-sanitize-vr5400
2428 // start-sanitize-r5900
2429 *r5900:
2430 // end-sanitize-r5900
2431 *r3900:
2432 // start-sanitize-tx19
2433 *tx19:
2434 // end-sanitize-tx19
2435 {
2436   check_mt_hilo (SD_, LOHISTORY);
2437   LO = GPR[RS];
2438 }
2439
2440
2441
2442 :function:::void:do_mult:int rs, int rt, int rd
2443 {
2444   signed64 prod;
2445   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2446   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2447   prod = (((signed64)(signed32) GPR[rs])
2448           * ((signed64)(signed32) GPR[rt]));
2449   LO = EXTEND32 (VL4_8 (prod));
2450   HI = EXTEND32 (VH4_8 (prod));
2451   if (rd != 0)
2452     GPR[rd] = LO;
2453   TRACE_ALU_RESULT2 (HI, LO);
2454 }
2455
2456 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2457 "mult r<RS>, r<RT>"
2458 *mipsI,mipsII,mipsIII,mipsIV:
2459 // start-sanitize-vr4320
2460 *vr4320:
2461 // end-sanitize-vr4320
2462 {
2463   do_mult (SD_, RS, RT, 0);
2464 }
2465
2466
2467 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2468 "mult r<RD>, r<RS>, r<RT>"
2469 *vr5000:
2470 // start-sanitize-vr5400
2471 *vr5400:
2472 // end-sanitize-vr5400
2473 // start-sanitize-r5900
2474 *r5900:
2475 // end-sanitize-r5900
2476 *r3900:
2477 // start-sanitize-tx19
2478 *tx19:
2479 // end-sanitize-tx19
2480 {
2481   do_mult (SD_, RS, RT, RD);
2482 }
2483
2484
2485 :function:::void:do_multu:int rs, int rt, int rd
2486 {
2487   unsigned64 prod;
2488   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2489   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2490   prod = (((unsigned64)(unsigned32) GPR[rs])
2491           * ((unsigned64)(unsigned32) GPR[rt]));
2492   LO = EXTEND32 (VL4_8 (prod));
2493   HI = EXTEND32 (VH4_8 (prod));
2494   if (rd != 0)
2495     GPR[rd] = LO;
2496   TRACE_ALU_RESULT2 (HI, LO);
2497 }
2498
2499 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2500 "multu r<RS>, r<RT>"
2501 *mipsI,mipsII,mipsIII,mipsIV:
2502 // start-sanitize-vr4320
2503 *vr4320:
2504 // end-sanitize-vr4320
2505 {
2506   do_multu (SD_, RS, RT, 0);
2507 }
2508
2509 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2510 "multu r<RD>, r<RS>, r<RT>"
2511 *vr5000:
2512 // start-sanitize-vr5400
2513 *vr5400:
2514 // end-sanitize-vr5400
2515 // start-sanitize-r5900
2516 *r5900:
2517 // end-sanitize-r5900
2518 *r3900:
2519 // start-sanitize-tx19
2520 *tx19:
2521 // end-sanitize-tx19
2522 {
2523   do_multu (SD_, RS, RT, 0);
2524 }
2525
2526
2527 :function:::void:do_nor:int rs, int rt, int rd
2528 {
2529   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2530   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2531   TRACE_ALU_RESULT (GPR[rd]);
2532 }
2533
2534 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2535 "nor r<RD>, r<RS>, r<RT>"
2536 *mipsI,mipsII,mipsIII,mipsIV:
2537 *vr5000:
2538 // start-sanitize-vr4320
2539 *vr4320:
2540 // end-sanitize-vr4320
2541 // start-sanitize-vr5400
2542 *vr5400:
2543 // end-sanitize-vr5400
2544 // start-sanitize-r5900
2545 *r5900:
2546 // end-sanitize-r5900
2547 *r3900:
2548 // start-sanitize-tx19
2549 *tx19:
2550 // end-sanitize-tx19
2551 {
2552   do_nor (SD_, RS, RT, RD);
2553 }
2554
2555
2556 :function:::void:do_or:int rs, int rt, int rd
2557 {
2558   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2559   GPR[rd] = (GPR[rs] | GPR[rt]);
2560   TRACE_ALU_RESULT (GPR[rd]);
2561 }
2562
2563 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2564 "or r<RD>, r<RS>, r<RT>"
2565 *mipsI,mipsII,mipsIII,mipsIV:
2566 *vr5000:
2567 // start-sanitize-vr4320
2568 *vr4320:
2569 // end-sanitize-vr4320
2570 // start-sanitize-vr5400
2571 *vr5400:
2572 // end-sanitize-vr5400
2573 // start-sanitize-r5900
2574 *r5900:
2575 // end-sanitize-r5900
2576 *r3900:
2577 // start-sanitize-tx19
2578 *tx19:
2579 // end-sanitize-tx19
2580 {
2581   do_or (SD_, RS, RT, RD);
2582 }
2583
2584
2585
2586 :function:::void:do_ori:int rs, int rt, unsigned immediate
2587 {
2588   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2589   GPR[rt] = (GPR[rs] | immediate);
2590   TRACE_ALU_RESULT (GPR[rt]);
2591 }
2592
2593 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2594 "ori r<RT>, r<RS>, <IMMEDIATE>"
2595 *mipsI,mipsII,mipsIII,mipsIV:
2596 *vr5000:
2597 // start-sanitize-vr4320
2598 *vr4320:
2599 // end-sanitize-vr4320
2600 // start-sanitize-vr5400
2601 *vr5400:
2602 // end-sanitize-vr5400
2603 // start-sanitize-r5900
2604 *r5900:
2605 // end-sanitize-r5900
2606 *r3900:
2607 // start-sanitize-tx19
2608 *tx19:
2609 // end-sanitize-tx19
2610 {
2611   do_ori (SD_, RS, RT, IMMEDIATE);
2612 }
2613
2614
2615 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2616 *mipsIV:
2617 *vr5000:
2618 // start-sanitize-vr4320
2619 *vr4320:
2620 // end-sanitize-vr4320
2621 // start-sanitize-vr5400
2622 *vr5400:
2623 // end-sanitize-vr5400
2624 // start-sanitize-r5900
2625 *r5900:
2626 // end-sanitize-r5900
2627 {
2628   unsigned32 instruction = instruction_0;
2629   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2630   int hint = ((instruction >> 16) & 0x0000001F);
2631   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2632   {
2633     address_word vaddr = ((unsigned64)op1 + offset);
2634     address_word paddr;
2635     int uncached;
2636     {
2637       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2638         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2639     }
2640   }
2641 }
2642
2643 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2644 {
2645   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2646   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2647   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2648   unsigned int byte;
2649   address_word paddr;
2650   int uncached;
2651   unsigned64 memval;
2652   address_word vaddr;
2653
2654   vaddr = base + offset;
2655   if ((vaddr & access) != 0)
2656     SignalExceptionAddressStore ();
2657   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2658   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2659   byte = ((vaddr & mask) ^ bigendiancpu);
2660   memval = (word << (8 * byte));
2661   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2662 }
2663
2664
2665 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2666 "sb r<RT>, <OFFSET>(r<BASE>)"
2667 *mipsI,mipsII,mipsIII,mipsIV:
2668 *vr5000:
2669 // start-sanitize-vr4320
2670 *vr4320:
2671 // end-sanitize-vr4320
2672 // start-sanitize-vr5400
2673 *vr5400:
2674 // end-sanitize-vr5400
2675 // start-sanitize-r5900
2676 *r5900:
2677 // end-sanitize-r5900
2678 *r3900:
2679 // start-sanitize-tx19
2680 *tx19:
2681 // end-sanitize-tx19
2682 {
2683   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2684 }
2685
2686
2687 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2688 "sc r<RT>, <OFFSET>(r<BASE>)"
2689 *mipsII:
2690 *mipsIII:
2691 *mipsIV:
2692 *vr5000:
2693 // start-sanitize-vr4320
2694 *vr4320:
2695 // end-sanitize-vr4320
2696 // start-sanitize-vr5400
2697 *vr5400:
2698 // end-sanitize-vr5400
2699 // start-sanitize-r5900
2700 *r5900:
2701 // end-sanitize-r5900
2702 // start-sanitize-tx19
2703 *tx19:
2704 // end-sanitize-tx19
2705 {
2706   unsigned32 instruction = instruction_0;
2707   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2708   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2709   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2710   {
2711     address_word vaddr = ((unsigned64)op1 + offset);
2712     address_word paddr;
2713     int uncached;
2714     if ((vaddr & 3) != 0)
2715       SignalExceptionAddressStore();
2716     else
2717       {
2718         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2719           {
2720             unsigned64 memval = 0;
2721             unsigned64 memval1 = 0;
2722             unsigned64 mask = 0x7;
2723             unsigned int byte;
2724             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2725             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2726             memval = ((unsigned64) op2 << (8 * byte));
2727             if (LLBIT)
2728               {
2729                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2730               }
2731             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2732           }
2733       }
2734   }
2735 }
2736
2737
2738 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2739 "scd r<RT>, <OFFSET>(r<BASE>)"
2740 *mipsIII:
2741 *mipsIV:
2742 *vr5000:
2743 // start-sanitize-vr4320
2744 *vr4320:
2745 // end-sanitize-vr4320
2746 // start-sanitize-vr5400
2747 *vr5400:
2748 // end-sanitize-vr5400
2749 // start-sanitize-r5900
2750 *r5900:
2751 // end-sanitize-r5900
2752 // start-sanitize-tx19
2753 *tx19:
2754 // end-sanitize-tx19
2755 {
2756   unsigned32 instruction = instruction_0;
2757   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2758   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2759   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2760   {
2761     address_word vaddr = ((unsigned64)op1 + offset);
2762     address_word paddr;
2763     int uncached;
2764     if ((vaddr & 7) != 0)
2765       SignalExceptionAddressStore();
2766     else
2767       {
2768         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2769           {
2770             unsigned64 memval = 0;
2771             unsigned64 memval1 = 0;
2772             memval = op2;
2773             if (LLBIT)
2774               {
2775                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2776               }
2777             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2778           }
2779       }
2780   }
2781 }
2782
2783
2784 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2785 "sd r<RT>, <OFFSET>(r<BASE>)"
2786 *mipsIII:
2787 *mipsIV:
2788 *vr5000:
2789 // start-sanitize-vr4320
2790 *vr4320:
2791 // end-sanitize-vr4320
2792 // start-sanitize-vr5400
2793 *vr5400:
2794 // end-sanitize-vr5400
2795 // start-sanitize-r5900
2796 *r5900:
2797 // end-sanitize-r5900
2798 // start-sanitize-tx19
2799 *tx19:
2800 // end-sanitize-tx19
2801 {
2802   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2803 }
2804
2805
2806 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2807 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2808 *mipsII:
2809 *mipsIII:
2810 *mipsIV:
2811 *vr5000:
2812 // start-sanitize-vr4320
2813 *vr4320:
2814 // end-sanitize-vr4320
2815 // start-sanitize-vr5400
2816 *vr5400:
2817 // end-sanitize-vr5400
2818 // start-sanitize-tx19
2819 *tx19:
2820 // end-sanitize-tx19
2821 {
2822   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2823 }
2824
2825
2826 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2827 "sdl r<RT>, <OFFSET>(r<BASE>)"
2828 *mipsIII:
2829 *mipsIV:
2830 *vr5000:
2831 // start-sanitize-vr4320
2832 *vr4320:
2833 // end-sanitize-vr4320
2834 // start-sanitize-vr5400
2835 *vr5400:
2836 // end-sanitize-vr5400
2837 // start-sanitize-r5900
2838 *r5900:
2839 // end-sanitize-r5900
2840 // start-sanitize-tx19
2841 *tx19:
2842 // end-sanitize-tx19
2843 {
2844   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2845 }
2846
2847
2848 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2849 "sdr r<RT>, <OFFSET>(r<BASE>)"
2850 *mipsIII:
2851 *mipsIV:
2852 *vr5000:
2853 // start-sanitize-vr4320
2854 *vr4320:
2855 // end-sanitize-vr4320
2856 // start-sanitize-vr5400
2857 *vr5400:
2858 // end-sanitize-vr5400
2859 // start-sanitize-r5900
2860 *r5900:
2861 // end-sanitize-r5900
2862 // start-sanitize-tx19
2863 *tx19:
2864 // end-sanitize-tx19
2865 {
2866   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2867 }
2868
2869
2870 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2871 "sh r<RT>, <OFFSET>(r<BASE>)"
2872 *mipsI,mipsII,mipsIII,mipsIV:
2873 *vr5000:
2874 // start-sanitize-vr4320
2875 *vr4320:
2876 // end-sanitize-vr4320
2877 // start-sanitize-vr5400
2878 *vr5400:
2879 // end-sanitize-vr5400
2880 // start-sanitize-r5900
2881 *r5900:
2882 // end-sanitize-r5900
2883 *r3900:
2884 // start-sanitize-tx19
2885 *tx19:
2886 // end-sanitize-tx19
2887 {
2888   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2889 }
2890
2891
2892 :function:::void:do_sll:int rt, int rd, int shift
2893 {
2894   unsigned32 temp = (GPR[rt] << shift);
2895   TRACE_ALU_INPUT2 (GPR[rt], shift);
2896   GPR[rd] = EXTEND32 (temp);
2897   TRACE_ALU_RESULT (GPR[rd]);
2898 }
2899
2900 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2901 "sll r<RD>, r<RT>, <SHIFT>"
2902 *mipsI,mipsII,mipsIII,mipsIV:
2903 *vr5000:
2904 // start-sanitize-vr4320
2905 *vr4320:
2906 // end-sanitize-vr4320
2907 // start-sanitize-vr5400
2908 *vr5400:
2909 // end-sanitize-vr5400
2910 // start-sanitize-r5900
2911 *r5900:
2912 // end-sanitize-r5900
2913 *r3900:
2914 // start-sanitize-tx19
2915 *tx19:
2916 // end-sanitize-tx19
2917 {
2918   do_sll (SD_, RT, RD, SHIFT);
2919 }
2920
2921
2922 :function:::void:do_sllv:int rs, int rt, int rd
2923 {
2924   int s = MASKED (GPR[rs], 4, 0);
2925   unsigned32 temp = (GPR[rt] << s);
2926   TRACE_ALU_INPUT2 (GPR[rt], s);
2927   GPR[rd] = EXTEND32 (temp);
2928   TRACE_ALU_RESULT (GPR[rd]);
2929 }
2930
2931 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2932 "sllv r<RD>, r<RT>, r<RS>"
2933 *mipsI,mipsII,mipsIII,mipsIV:
2934 *vr5000:
2935 // start-sanitize-vr4320
2936 *vr4320:
2937 // end-sanitize-vr4320
2938 // start-sanitize-vr5400
2939 *vr5400:
2940 // end-sanitize-vr5400
2941 // start-sanitize-r5900
2942 *r5900:
2943 // end-sanitize-r5900
2944 *r3900:
2945 // start-sanitize-tx19
2946 *tx19:
2947 // end-sanitize-tx19
2948 {
2949   do_sllv (SD_, RS, RT, RD);
2950 }
2951
2952
2953 :function:::void:do_slt:int rs, int rt, int rd
2954 {
2955   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2956   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2957   TRACE_ALU_RESULT (GPR[rd]);
2958 }
2959
2960 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2961 "slt r<RD>, r<RS>, r<RT>"
2962 *mipsI,mipsII,mipsIII,mipsIV:
2963 *vr5000:
2964 // start-sanitize-vr4320
2965 *vr4320:
2966 // end-sanitize-vr4320
2967 // start-sanitize-vr5400
2968 *vr5400:
2969 // end-sanitize-vr5400
2970 // start-sanitize-r5900
2971 *r5900:
2972 // end-sanitize-r5900
2973 *r3900:
2974 // start-sanitize-tx19
2975 *tx19:
2976 // end-sanitize-tx19
2977 {
2978   do_slt (SD_, RS, RT, RD);
2979 }
2980
2981
2982 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2983 {
2984   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2985   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2986   TRACE_ALU_RESULT (GPR[rt]);
2987 }
2988
2989 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2990 "slti r<RT>, r<RS>, <IMMEDIATE>"
2991 *mipsI,mipsII,mipsIII,mipsIV:
2992 *vr5000:
2993 // start-sanitize-vr4320
2994 *vr4320:
2995 // end-sanitize-vr4320
2996 // start-sanitize-vr5400
2997 *vr5400:
2998 // end-sanitize-vr5400
2999 // start-sanitize-r5900
3000 *r5900:
3001 // end-sanitize-r5900
3002 *r3900:
3003 // start-sanitize-tx19
3004 *tx19:
3005 // end-sanitize-tx19
3006 {
3007   do_slti (SD_, RS, RT, IMMEDIATE);
3008 }
3009
3010
3011 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3012 {
3013   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3014   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3015   TRACE_ALU_RESULT (GPR[rt]);
3016 }
3017
3018 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3019 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3020 *mipsI,mipsII,mipsIII,mipsIV:
3021 *vr5000:
3022 // start-sanitize-vr4320
3023 *vr4320:
3024 // end-sanitize-vr4320
3025 // start-sanitize-vr5400
3026 *vr5400:
3027 // end-sanitize-vr5400
3028 // start-sanitize-r5900
3029 *r5900:
3030 // end-sanitize-r5900
3031 *r3900:
3032 // start-sanitize-tx19
3033 *tx19:
3034 // end-sanitize-tx19
3035 {
3036   do_sltiu (SD_, RS, RT, IMMEDIATE);
3037 }
3038
3039
3040
3041 :function:::void:do_sltu:int rs, int rt, int rd
3042 {
3043   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3044   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3045   TRACE_ALU_RESULT (GPR[rd]);
3046 }
3047
3048 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3049 "sltu r<RD>, r<RS>, r<RT>"
3050 *mipsI,mipsII,mipsIII,mipsIV:
3051 *vr5000:
3052 // start-sanitize-vr4320
3053 *vr4320:
3054 // end-sanitize-vr4320
3055 // start-sanitize-vr5400
3056 *vr5400:
3057 // end-sanitize-vr5400
3058 // start-sanitize-r5900
3059 *r5900:
3060 // end-sanitize-r5900
3061 *r3900:
3062 // start-sanitize-tx19
3063 *tx19:
3064 // end-sanitize-tx19
3065 {
3066   do_sltu (SD_, RS, RT, RD);
3067 }
3068
3069
3070 :function:::void:do_sra:int rt, int rd, int shift
3071 {
3072   signed32 temp = (signed32) GPR[rt] >> shift;
3073   TRACE_ALU_INPUT2 (GPR[rt], shift);
3074   GPR[rd] = EXTEND32 (temp);
3075   TRACE_ALU_RESULT (GPR[rd]);
3076 }
3077
3078 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3079 "sra r<RD>, r<RT>, <SHIFT>"
3080 *mipsI,mipsII,mipsIII,mipsIV:
3081 *vr5000:
3082 // start-sanitize-vr4320
3083 *vr4320:
3084 // end-sanitize-vr4320
3085 // start-sanitize-vr5400
3086 *vr5400:
3087 // end-sanitize-vr5400
3088 // start-sanitize-r5900
3089 *r5900:
3090 // end-sanitize-r5900
3091 *r3900:
3092 // start-sanitize-tx19
3093 *tx19:
3094 // end-sanitize-tx19
3095 {
3096   do_sra (SD_, RT, RD, SHIFT);
3097 }
3098
3099
3100
3101 :function:::void:do_srav:int rs, int rt, int rd
3102 {
3103   int s = MASKED (GPR[rs], 4, 0);
3104   signed32 temp = (signed32) GPR[rt] >> s;
3105   TRACE_ALU_INPUT2 (GPR[rt], s);
3106   GPR[rd] = EXTEND32 (temp);
3107   TRACE_ALU_RESULT (GPR[rd]);
3108 }
3109
3110 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3111 "srav r<RD>, r<RT>, r<RS>"
3112 *mipsI,mipsII,mipsIII,mipsIV:
3113 *vr5000:
3114 // start-sanitize-vr4320
3115 *vr4320:
3116 // end-sanitize-vr4320
3117 // start-sanitize-vr5400
3118 *vr5400:
3119 // end-sanitize-vr5400
3120 // start-sanitize-r5900
3121 *r5900:
3122 // end-sanitize-r5900
3123 *r3900:
3124 // start-sanitize-tx19
3125 *tx19:
3126 // end-sanitize-tx19
3127 {
3128   do_srav (SD_, RS, RT, RD);
3129 }
3130
3131
3132
3133 :function:::void:do_srl:int rt, int rd, int shift
3134 {
3135   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3136   TRACE_ALU_INPUT2 (GPR[rt], shift);
3137   GPR[rd] = EXTEND32 (temp);
3138   TRACE_ALU_RESULT (GPR[rd]);
3139 }
3140
3141 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3142 "srl r<RD>, r<RT>, <SHIFT>"
3143 *mipsI,mipsII,mipsIII,mipsIV:
3144 *vr5000:
3145 // start-sanitize-vr4320
3146 *vr4320:
3147 // end-sanitize-vr4320
3148 // start-sanitize-vr5400
3149 *vr5400:
3150 // end-sanitize-vr5400
3151 // start-sanitize-r5900
3152 *r5900:
3153 // end-sanitize-r5900
3154 *r3900:
3155 // start-sanitize-tx19
3156 *tx19:
3157 // end-sanitize-tx19
3158 {
3159   do_srl (SD_, RT, RD, SHIFT);
3160 }
3161
3162
3163 :function:::void:do_srlv:int rs, int rt, int rd
3164 {
3165   int s = MASKED (GPR[rs], 4, 0);
3166   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3167   TRACE_ALU_INPUT2 (GPR[rt], s);
3168   GPR[rd] = EXTEND32 (temp);
3169   TRACE_ALU_RESULT (GPR[rd]);
3170 }
3171
3172 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3173 "srlv r<RD>, r<RT>, r<RS>"
3174 *mipsI,mipsII,mipsIII,mipsIV:
3175 *vr5000:
3176 // start-sanitize-vr4320
3177 *vr4320:
3178 // end-sanitize-vr4320
3179 // start-sanitize-vr5400
3180 *vr5400:
3181 // end-sanitize-vr5400
3182 // start-sanitize-r5900
3183 *r5900:
3184 // end-sanitize-r5900
3185 *r3900:
3186 // start-sanitize-tx19
3187 *tx19:
3188 // end-sanitize-tx19
3189 {
3190   do_srlv (SD_, RS, RT, RD);
3191 }
3192
3193
3194 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3195 "sub r<RD>, r<RS>, r<RT>"
3196 *mipsI,mipsII,mipsIII,mipsIV:
3197 *vr5000:
3198 // start-sanitize-vr4320
3199 *vr4320:
3200 // end-sanitize-vr4320
3201 // start-sanitize-vr5400
3202 *vr5400:
3203 // end-sanitize-vr5400
3204 // start-sanitize-r5900
3205 *r5900:
3206 // end-sanitize-r5900
3207 *r3900:
3208 // start-sanitize-tx19
3209 *tx19:
3210 // end-sanitize-tx19
3211 {
3212   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3213   {
3214     ALU32_BEGIN (GPR[RS]);
3215     ALU32_SUB (GPR[RT]);
3216     ALU32_END (GPR[RD]);
3217   }
3218   TRACE_ALU_RESULT (GPR[RD]);
3219 }
3220
3221
3222 :function:::void:do_subu:int rs, int rt, int rd
3223 {
3224   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3225   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3226   TRACE_ALU_RESULT (GPR[rd]);
3227 }
3228
3229 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3230 "subu r<RD>, r<RS>, r<RT>"
3231 *mipsI,mipsII,mipsIII,mipsIV:
3232 *vr5000:
3233 // start-sanitize-vr4320
3234 *vr4320:
3235 // end-sanitize-vr4320
3236 // start-sanitize-vr5400
3237 *vr5400:
3238 // end-sanitize-vr5400
3239 // start-sanitize-r5900
3240 *r5900:
3241 // end-sanitize-r5900
3242 *r3900:
3243 // start-sanitize-tx19
3244 *tx19:
3245 // end-sanitize-tx19
3246 {
3247   do_subu (SD_, RS, RT, RD);
3248 }
3249
3250
3251 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3252 "sw r<RT>, <OFFSET>(r<BASE>)"
3253 *mipsI,mipsII,mipsIII,mipsIV:
3254 // start-sanitize-tx19
3255 *tx19:
3256 // end-sanitize-tx19
3257 *r3900:
3258 // start-sanitize-vr4320
3259 *vr4320:
3260 // end-sanitize-vr4320
3261 *vr5000:
3262 // start-sanitize-vr5400
3263 *vr5400:
3264 // end-sanitize-vr5400
3265 // start-sanitize-r5900
3266 *r5900:
3267 // end-sanitize-r5900
3268 {
3269   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3270 }
3271
3272
3273 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3274 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3275 *mipsI,mipsII,mipsIII,mipsIV:
3276 *vr5000:
3277 // start-sanitize-vr4320
3278 *vr4320:
3279 // end-sanitize-vr4320
3280 // start-sanitize-vr5400
3281 *vr5400:
3282 // end-sanitize-vr5400
3283 *r3900:
3284 // start-sanitize-tx19
3285 *tx19:
3286 // end-sanitize-tx19
3287 {
3288   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3289 }
3290
3291
3292
3293 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3294 {
3295   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3296   address_word reverseendian = (ReverseEndian ? -1 : 0);
3297   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3298   unsigned int byte;
3299   unsigned int word;
3300   address_word paddr;
3301   int uncached;
3302   unsigned64 memval;
3303   address_word vaddr;
3304   int nr_lhs_bits;
3305   int nr_rhs_bits;
3306
3307   vaddr = base + offset;
3308   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3309   paddr = (paddr ^ (reverseendian & mask));
3310   if (BigEndianMem == 0)
3311     paddr = paddr & ~access;
3312
3313   /* compute where within the word/mem we are */
3314   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3315   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3316   nr_lhs_bits = 8 * byte + 8;
3317   nr_rhs_bits = 8 * access - 8 * byte;
3318   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3319   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3320            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3321            (long) ((unsigned64) paddr >> 32), (long) paddr,
3322            word, byte, nr_lhs_bits, nr_rhs_bits); */
3323
3324   if (word == 0)
3325     {
3326       memval = (rt >> nr_rhs_bits);
3327     }
3328   else
3329     {
3330       memval = (rt << nr_lhs_bits);
3331     }
3332   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3333            (long) ((unsigned64) rt >> 32), (long) rt,
3334            (long) ((unsigned64) memval >> 32), (long) memval); */
3335   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3336 }
3337
3338
3339 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3340 "swl r<RT>, <OFFSET>(r<BASE>)"
3341 *mipsI,mipsII,mipsIII,mipsIV:
3342 *vr5000:
3343 // start-sanitize-vr4320
3344 *vr4320:
3345 // end-sanitize-vr4320
3346 // start-sanitize-vr5400
3347 *vr5400:
3348 // end-sanitize-vr5400
3349 // start-sanitize-r5900
3350 *r5900:
3351 // end-sanitize-r5900
3352 *r3900:
3353 // start-sanitize-tx19
3354 *tx19:
3355 // end-sanitize-tx19
3356 {
3357   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3358 }
3359
3360
3361 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3362 {
3363   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3364   address_word reverseendian = (ReverseEndian ? -1 : 0);
3365   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3366   unsigned int byte;
3367   address_word paddr;
3368   int uncached;
3369   unsigned64 memval;
3370   address_word vaddr;
3371
3372   vaddr = base + offset;
3373   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3374   paddr = (paddr ^ (reverseendian & mask));
3375   if (BigEndianMem != 0)
3376     paddr &= ~access;
3377   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3378   memval = (rt << (byte * 8));
3379   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3380 }
3381
3382 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3383 "swr r<RT>, <OFFSET>(r<BASE>)"
3384 *mipsI,mipsII,mipsIII,mipsIV:
3385 *vr5000:
3386 // start-sanitize-vr4320
3387 *vr4320:
3388 // end-sanitize-vr4320
3389 // start-sanitize-vr5400
3390 *vr5400:
3391 // end-sanitize-vr5400
3392 // start-sanitize-r5900
3393 *r5900:
3394 // end-sanitize-r5900
3395 *r3900:
3396 // start-sanitize-tx19
3397 *tx19:
3398 // end-sanitize-tx19
3399 {
3400   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3401 }
3402
3403
3404 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3405 "sync":STYPE == 0
3406 "sync <STYPE>"
3407 *mipsII:
3408 *mipsIII:
3409 *mipsIV:
3410 *vr5000:
3411 // start-sanitize-vr4320
3412 *vr4320:
3413 // end-sanitize-vr4320
3414 // start-sanitize-vr5400
3415 *vr5400:
3416 // end-sanitize-vr5400
3417 // start-sanitize-r5900
3418 *r5900:
3419 // end-sanitize-r5900
3420 *r3900:
3421 // start-sanitize-tx19
3422 *tx19:
3423 // end-sanitize-tx19
3424 {
3425   SyncOperation (STYPE);
3426 }
3427
3428
3429 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3430 "syscall <CODE>"
3431 *mipsI,mipsII,mipsIII,mipsIV:
3432 *vr5000:
3433 // start-sanitize-vr4320
3434 *vr4320:
3435 // end-sanitize-vr4320
3436 // start-sanitize-vr5400
3437 *vr5400:
3438 // end-sanitize-vr5400
3439 // start-sanitize-r5900
3440 *r5900:
3441 // end-sanitize-r5900
3442 *r3900:
3443 // start-sanitize-tx19
3444 *tx19:
3445 // end-sanitize-tx19
3446 {
3447   SignalException(SystemCall, instruction_0);
3448 }
3449
3450
3451 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3452 "teq r<RS>, r<RT>"
3453 *mipsII:
3454 *mipsIII:
3455 *mipsIV:
3456 *vr5000:
3457 // start-sanitize-vr4320
3458 *vr4320:
3459 // end-sanitize-vr4320
3460 // start-sanitize-vr5400
3461 *vr5400:
3462 // end-sanitize-vr5400
3463 // start-sanitize-r5900
3464 *r5900:
3465 // end-sanitize-r5900
3466 // start-sanitize-tx19
3467 *tx19:
3468 // end-sanitize-tx19
3469 {
3470   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3471     SignalException(Trap, instruction_0);
3472 }
3473
3474
3475 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3476 "teqi r<RS>, <IMMEDIATE>"
3477 *mipsII:
3478 *mipsIII:
3479 *mipsIV:
3480 *vr5000:
3481 // start-sanitize-vr4320
3482 *vr4320:
3483 // end-sanitize-vr4320
3484 // start-sanitize-vr5400
3485 *vr5400:
3486 // end-sanitize-vr5400
3487 // start-sanitize-r5900
3488 *r5900:
3489 // end-sanitize-r5900
3490 // start-sanitize-tx19
3491 *tx19:
3492 // end-sanitize-tx19
3493 {
3494   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3495     SignalException(Trap, instruction_0);
3496 }
3497
3498
3499 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3500 "tge r<RS>, r<RT>"
3501 *mipsII:
3502 *mipsIII:
3503 *mipsIV:
3504 *vr5000:
3505 // start-sanitize-vr4320
3506 *vr4320:
3507 // end-sanitize-vr4320
3508 // start-sanitize-vr5400
3509 *vr5400:
3510 // end-sanitize-vr5400
3511 // start-sanitize-r5900
3512 *r5900:
3513 // end-sanitize-r5900
3514 // start-sanitize-tx19
3515 *tx19:
3516 // end-sanitize-tx19
3517 {
3518   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3519     SignalException(Trap, instruction_0);
3520 }
3521
3522
3523 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3524 "tgei r<RS>, <IMMEDIATE>"
3525 *mipsII:
3526 *mipsIII:
3527 *mipsIV:
3528 *vr5000:
3529 // start-sanitize-vr4320
3530 *vr4320:
3531 // end-sanitize-vr4320
3532 // start-sanitize-vr5400
3533 *vr5400:
3534 // end-sanitize-vr5400
3535 // start-sanitize-r5900
3536 *r5900:
3537 // end-sanitize-r5900
3538 // start-sanitize-tx19
3539 *tx19:
3540 // end-sanitize-tx19
3541 {
3542   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3543     SignalException(Trap, instruction_0);
3544 }
3545
3546
3547 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3548 "tgeiu r<RS>, <IMMEDIATE>"
3549 *mipsII:
3550 *mipsIII:
3551 *mipsIV:
3552 *vr5000:
3553 // start-sanitize-vr4320
3554 *vr4320:
3555 // end-sanitize-vr4320
3556 // start-sanitize-vr5400
3557 *vr5400:
3558 // end-sanitize-vr5400
3559 // start-sanitize-r5900
3560 *r5900:
3561 // end-sanitize-r5900
3562 // start-sanitize-tx19
3563 *tx19:
3564 // end-sanitize-tx19
3565 {
3566   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3567     SignalException(Trap, instruction_0);
3568 }
3569
3570
3571 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3572 "tgeu r<RS>, r<RT>"
3573 *mipsII:
3574 *mipsIII:
3575 *mipsIV:
3576 *vr5000:
3577 // start-sanitize-vr4320
3578 *vr4320:
3579 // end-sanitize-vr4320
3580 // start-sanitize-vr5400
3581 *vr5400:
3582 // end-sanitize-vr5400
3583 // start-sanitize-r5900
3584 *r5900:
3585 // end-sanitize-r5900
3586 // start-sanitize-tx19
3587 *tx19:
3588 // end-sanitize-tx19
3589 {
3590   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3591     SignalException(Trap, instruction_0);
3592 }
3593
3594
3595 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3596 "tlt r<RS>, r<RT>"
3597 *mipsII:
3598 *mipsIII:
3599 *mipsIV:
3600 *vr5000:
3601 // start-sanitize-vr4320
3602 *vr4320:
3603 // end-sanitize-vr4320
3604 // start-sanitize-vr5400
3605 *vr5400:
3606 // end-sanitize-vr5400
3607 // start-sanitize-r5900
3608 *r5900:
3609 // end-sanitize-r5900
3610 // start-sanitize-tx19
3611 *tx19:
3612 // end-sanitize-tx19
3613 {
3614   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3615     SignalException(Trap, instruction_0);
3616 }
3617
3618
3619 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3620 "tlti r<RS>, <IMMEDIATE>"
3621 *mipsII:
3622 *mipsIII:
3623 *mipsIV:
3624 *vr5000:
3625 // start-sanitize-vr4320
3626 *vr4320:
3627 // end-sanitize-vr4320
3628 // start-sanitize-vr5400
3629 *vr5400:
3630 // end-sanitize-vr5400
3631 // start-sanitize-r5900
3632 *r5900:
3633 // end-sanitize-r5900
3634 // start-sanitize-tx19
3635 *tx19:
3636 // end-sanitize-tx19
3637 {
3638   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3639     SignalException(Trap, instruction_0);
3640 }
3641
3642
3643 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3644 "tltiu r<RS>, <IMMEDIATE>"
3645 *mipsII:
3646 *mipsIII:
3647 *mipsIV:
3648 *vr5000:
3649 // start-sanitize-vr4320
3650 *vr4320:
3651 // end-sanitize-vr4320
3652 // start-sanitize-vr5400
3653 *vr5400:
3654 // end-sanitize-vr5400
3655 // start-sanitize-r5900
3656 *r5900:
3657 // end-sanitize-r5900
3658 // start-sanitize-tx19
3659 *tx19:
3660 // end-sanitize-tx19
3661 {
3662   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3663     SignalException(Trap, instruction_0);
3664 }
3665
3666
3667 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3668 "tltu r<RS>, r<RT>"
3669 *mipsII:
3670 *mipsIII:
3671 *mipsIV:
3672 *vr5000:
3673 // start-sanitize-vr4320
3674 *vr4320:
3675 // end-sanitize-vr4320
3676 // start-sanitize-vr5400
3677 *vr5400:
3678 // end-sanitize-vr5400
3679 // start-sanitize-r5900
3680 *r5900:
3681 // end-sanitize-r5900
3682 // start-sanitize-tx19
3683 *tx19:
3684 // end-sanitize-tx19
3685 {
3686   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3687     SignalException(Trap, instruction_0);
3688 }
3689
3690
3691 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3692 "tne r<RS>, r<RT>"
3693 *mipsII:
3694 *mipsIII:
3695 *mipsIV:
3696 *vr5000:
3697 // start-sanitize-vr4320
3698 *vr4320:
3699 // end-sanitize-vr4320
3700 // start-sanitize-vr5400
3701 *vr5400:
3702 // end-sanitize-vr5400
3703 // start-sanitize-r5900
3704 *r5900:
3705 // end-sanitize-r5900
3706 // start-sanitize-tx19
3707 *tx19:
3708 // end-sanitize-tx19
3709 {
3710   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3711     SignalException(Trap, instruction_0);
3712 }
3713
3714
3715 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3716 "tne r<RS>, <IMMEDIATE>"
3717 *mipsII:
3718 *mipsIII:
3719 *mipsIV:
3720 *vr5000:
3721 // start-sanitize-vr4320
3722 *vr4320:
3723 // end-sanitize-vr4320
3724 // start-sanitize-vr5400
3725 *vr5400:
3726 // end-sanitize-vr5400
3727 // start-sanitize-r5900
3728 *r5900:
3729 // end-sanitize-r5900
3730 // start-sanitize-tx19
3731 *tx19:
3732 // end-sanitize-tx19
3733 {
3734   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3735     SignalException(Trap, instruction_0);
3736 }
3737
3738
3739 :function:::void:do_xor:int rs, int rt, int rd
3740 {
3741   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3742   GPR[rd] = GPR[rs] ^ GPR[rt];
3743   TRACE_ALU_RESULT (GPR[rd]);
3744 }
3745
3746 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3747 "xor r<RD>, r<RS>, r<RT>"
3748 *mipsI,mipsII,mipsIII,mipsIV:
3749 *vr5000:
3750 // start-sanitize-vr4320
3751 *vr4320:
3752 // end-sanitize-vr4320
3753 // start-sanitize-vr5400
3754 *vr5400:
3755 // end-sanitize-vr5400
3756 // start-sanitize-r5900
3757 *r5900:
3758 // end-sanitize-r5900
3759 *r3900:
3760 // start-sanitize-tx19
3761 *tx19:
3762 // end-sanitize-tx19
3763 {
3764   do_xor (SD_, RS, RT, RD);
3765 }
3766
3767
3768 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3769 {
3770   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3771   GPR[rt] = GPR[rs] ^ immediate;
3772   TRACE_ALU_RESULT (GPR[rt]);
3773 }
3774
3775 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3776 "xori r<RT>, r<RS>, <IMMEDIATE>"
3777 *mipsI,mipsII,mipsIII,mipsIV:
3778 *vr5000:
3779 // start-sanitize-vr4320
3780 *vr4320:
3781 // end-sanitize-vr4320
3782 // start-sanitize-vr5400
3783 *vr5400:
3784 // end-sanitize-vr5400
3785 // start-sanitize-r5900
3786 *r5900:
3787 // end-sanitize-r5900
3788 *r3900:
3789 // start-sanitize-tx19
3790 *tx19:
3791 // end-sanitize-tx19
3792 {
3793   do_xori (SD_, RS, RT, IMMEDIATE);
3794 }
3795
3796 \f
3797 //
3798 // MIPS Architecture:
3799 //
3800 //        FPU Instruction Set (COP1 & COP1X)
3801 //
3802
3803
3804 :%s::::FMT:int fmt
3805 {
3806   switch (fmt)
3807     {
3808     case fmt_single: return "s";
3809     case fmt_double: return "d";
3810     case fmt_word: return "w";
3811     case fmt_long: return "l";
3812     default: return "?";
3813     }
3814 }
3815
3816 :%s::::X:int x
3817 {
3818   switch (x)
3819     {
3820     case 0: return "f";
3821     case 1: return "t";
3822     default: return "?";
3823     }
3824 }
3825
3826 :%s::::TF:int tf
3827 {
3828   if (tf)
3829     return "t";
3830   else
3831     return "f";
3832 }
3833
3834 :%s::::ND:int nd
3835 {
3836   if (nd)
3837     return "l";
3838   else
3839     return "";
3840 }
3841
3842 :%s::::COND:int cond
3843 {
3844   switch (cond)
3845     {
3846     case 00: return "f";
3847     case 01: return "un";
3848     case 02: return "eq";
3849     case 03: return "ueq";
3850     case 04: return "olt";
3851     case 05: return "ult";
3852     case 06: return "ole";
3853     case 07: return "ule";
3854     case 010: return "sf";
3855     case 011: return "ngle";
3856     case 012: return "seq";
3857     case 013: return "ngl";
3858     case 014: return "lt";
3859     case 015: return "nge";
3860     case 016: return "le";
3861     case 017: return "ngt";
3862     default: return "?";
3863     }
3864 }
3865
3866
3867 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3868 "abs.%s<FMT> f<FD>, f<FS>"
3869 *mipsI,mipsII,mipsIII,mipsIV:
3870 *vr5000:
3871 // start-sanitize-vr4320
3872 *vr4320:
3873 // end-sanitize-vr4320
3874 // start-sanitize-vr5400
3875 *vr5400:
3876 // end-sanitize-vr5400
3877 *r3900:
3878 // start-sanitize-tx19
3879 *tx19:
3880 // end-sanitize-tx19
3881 {
3882   unsigned32 instruction = instruction_0;
3883   int destreg = ((instruction >> 6) & 0x0000001F);
3884   int fs = ((instruction >> 11) & 0x0000001F);
3885   int format = ((instruction >> 21) & 0x00000007);
3886   {
3887     if ((format != fmt_single) && (format != fmt_double))
3888       SignalException(ReservedInstruction,instruction);
3889     else
3890       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3891   }
3892 }
3893
3894
3895
3896 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3897 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3898 *mipsI,mipsII,mipsIII,mipsIV:
3899 *vr5000:
3900 // start-sanitize-vr4320
3901 *vr4320:
3902 // end-sanitize-vr4320
3903 // start-sanitize-vr5400
3904 *vr5400:
3905 // end-sanitize-vr5400
3906 *r3900:
3907 // start-sanitize-tx19
3908 *tx19:
3909 // end-sanitize-tx19
3910 {
3911   unsigned32 instruction = instruction_0;
3912   int destreg = ((instruction >> 6) & 0x0000001F);
3913   int fs = ((instruction >> 11) & 0x0000001F);
3914   int ft = ((instruction >> 16) & 0x0000001F);
3915   int format = ((instruction >> 21) & 0x00000007);
3916   {
3917     if ((format != fmt_single) && (format != fmt_double))
3918       SignalException(ReservedInstruction, instruction);
3919     else
3920       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3921   }
3922 }
3923
3924
3925
3926 // BC1F
3927 // BC1FL
3928 // BC1T
3929 // BC1TL
3930
3931 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3932 "bc1%s<TF>%s<ND> <OFFSET>"
3933 *mipsI,mipsII,mipsIII:
3934 // start-sanitize-r5900
3935 *r5900:
3936 // end-sanitize-r5900
3937 {
3938   TRACE_BRANCH_INPUT (PREVCOC1());
3939   if (PREVCOC1() == TF)
3940     {
3941       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3942       TRACE_BRANCH_RESULT (dest);
3943       DELAY_SLOT (dest);
3944     }
3945   else if (ND)
3946     {
3947       TRACE_BRANCH_RESULT (0);
3948       NULLIFY_NEXT_INSTRUCTION ();
3949     }
3950   else
3951     {
3952       TRACE_BRANCH_RESULT (NIA);
3953     }
3954 }
3955
3956 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3957 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3958 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3959 *mipsIV:
3960 *vr5000:
3961 // start-sanitize-vr4320
3962 *vr4320:
3963 // end-sanitize-vr4320
3964 // start-sanitize-vr5400
3965 *vr5400:
3966 // end-sanitize-vr5400
3967 *r3900:
3968 // start-sanitize-tx19
3969 *tx19:
3970 // end-sanitize-tx19
3971 {
3972   if (GETFCC(CC) == TF)
3973     {
3974       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3975     }
3976   else if (ND)
3977     {
3978       NULLIFY_NEXT_INSTRUCTION ();
3979     }
3980 }
3981
3982
3983
3984
3985
3986
3987 // C.EQ.S
3988 // C.EQ.D
3989 // ...
3990
3991 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3992 {
3993   if ((fmt != fmt_single) && (fmt != fmt_double))
3994     SignalException (ReservedInstruction, insn);
3995   else
3996     {
3997       int less;
3998       int equal;
3999       int unordered;
4000       int condition;
4001       unsigned64 ofs = ValueFPR (fs, fmt);
4002       unsigned64 oft = ValueFPR (ft, fmt);
4003       if (NaN (ofs, fmt) || NaN (oft, fmt))
4004         {
4005           if (FCSR & FP_ENABLE (IO))
4006             {
4007               FCSR |= FP_CAUSE (IO);
4008               SignalExceptionFPE ();
4009             }
4010           less = 0;
4011           equal = 0;
4012           unordered = 1;
4013         }
4014       else
4015         {
4016           less = Less (ofs, oft, fmt);
4017           equal = Equal (ofs, oft, fmt);
4018           unordered = 0;
4019         }
4020       condition = (((cond & (1 << 2)) && less)
4021                    || ((cond & (1 << 1)) && equal)
4022                    || ((cond & (1 << 0)) && unordered));
4023       SETFCC (cc, condition);
4024     }
4025 }
4026
4027 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4028 *mipsI,mipsII,mipsIII:
4029 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
4030 {
4031   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4032 }
4033
4034 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4035 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4036 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4037 *mipsIV:
4038 *vr5000:
4039 // start-sanitize-vr4320
4040 *vr4320:
4041 // end-sanitize-vr4320
4042 // start-sanitize-vr5400
4043 *vr5400:
4044 // end-sanitize-vr5400
4045 *r3900:
4046 // start-sanitize-tx19
4047 *tx19:
4048 // end-sanitize-tx19
4049 {
4050   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4051 }
4052
4053
4054 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4055 "ceil.l.%s<FMT> f<FD>, f<FS>"
4056 *mipsIII:
4057 *mipsIV:
4058 *vr5000:
4059 // start-sanitize-vr4320
4060 *vr4320:
4061 // end-sanitize-vr4320
4062 // start-sanitize-vr5400
4063 *vr5400:
4064 // end-sanitize-vr5400
4065 // start-sanitize-r5900
4066 *r5900:
4067 // end-sanitize-r5900
4068 *r3900:
4069 // start-sanitize-tx19
4070 *tx19:
4071 // end-sanitize-tx19
4072 {
4073   unsigned32 instruction = instruction_0;
4074   int destreg = ((instruction >> 6) & 0x0000001F);
4075   int fs = ((instruction >> 11) & 0x0000001F);
4076   int format = ((instruction >> 21) & 0x00000007);
4077   {
4078     if ((format != fmt_single) && (format != fmt_double))
4079       SignalException(ReservedInstruction,instruction);
4080     else
4081       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4082   }
4083 }
4084
4085
4086 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4087 *mipsII:
4088 *mipsIII:
4089 *mipsIV:
4090 *vr5000:
4091 // start-sanitize-vr4320
4092 *vr4320:
4093 // end-sanitize-vr4320
4094 // start-sanitize-vr5400
4095 *vr5400:
4096 // end-sanitize-vr5400
4097 // start-sanitize-r5900
4098 *r5900:
4099 // end-sanitize-r5900
4100 *r3900:
4101 // start-sanitize-tx19
4102 *tx19:
4103 // end-sanitize-tx19
4104 {
4105   unsigned32 instruction = instruction_0;
4106   int destreg = ((instruction >> 6) & 0x0000001F);
4107   int fs = ((instruction >> 11) & 0x0000001F);
4108   int format = ((instruction >> 21) & 0x00000007);
4109   {
4110   if ((format != fmt_single) && (format != fmt_double))
4111    SignalException(ReservedInstruction,instruction);
4112   else
4113    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4114   }
4115 }
4116
4117
4118 // CFC1
4119 // CTC1
4120 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4121 "c%s<X>c1 r<RT>, f<FS>"
4122 *mipsI:
4123 *mipsII:
4124 *mipsIII:
4125 {
4126   if (X)
4127     {
4128       if (FS == 0)
4129         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4130       else if (FS == 31)
4131         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4132       /* else NOP */
4133       PENDING_FILL(COCIDX,0); /* special case */
4134     }
4135   else
4136     { /* control from */
4137       if (FS == 0)
4138         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4139       else if (FS == 31)
4140         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4141       /* else NOP */
4142     }
4143 }
4144 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4145 "c%s<X>c1 r<RT>, f<FS>"
4146 *mipsIV:
4147 *vr5000:
4148 // start-sanitize-vr4320
4149 *vr4320:
4150 // end-sanitize-vr4320
4151 // start-sanitize-vr5400
4152 *vr5400:
4153 // end-sanitize-vr5400
4154 *r3900:
4155 // start-sanitize-tx19
4156 *tx19:
4157 // end-sanitize-tx19
4158 {
4159   if (X)
4160     {
4161       /* control to */
4162       TRACE_ALU_INPUT1 (GPR[RT]);
4163       if (FS == 0)
4164         {
4165           FCR0 = VL4_8(GPR[RT]);
4166           TRACE_ALU_RESULT (FCR0);
4167         }
4168       else if (FS == 31)
4169         {
4170           FCR31 = VL4_8(GPR[RT]);
4171           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4172           TRACE_ALU_RESULT (FCR31);
4173         }
4174       else
4175         {
4176           TRACE_ALU_RESULT0 ();
4177         }
4178       /* else NOP */
4179     }
4180   else
4181     { /* control from */
4182       if (FS == 0)
4183         {
4184           TRACE_ALU_INPUT1 (FCR0);
4185           GPR[RT] = SIGNEXTEND (FCR0, 32);
4186         }
4187       else if (FS == 31)
4188         {
4189           TRACE_ALU_INPUT1 (FCR31);
4190           GPR[RT] = SIGNEXTEND (FCR31, 32);
4191         }
4192       TRACE_ALU_RESULT (GPR[RT]);
4193       /* else NOP */
4194     }
4195 }
4196
4197
4198 //
4199 // FIXME: Does not correctly differentiate between mips*
4200 //
4201 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4202 "cvt.d.%s<FMT> f<FD>, f<FS>"
4203 *mipsI,mipsII,mipsIII,mipsIV:
4204 *vr5000:
4205 // start-sanitize-vr4320
4206 *vr4320:
4207 // end-sanitize-vr4320
4208 // start-sanitize-vr5400
4209 *vr5400:
4210 // end-sanitize-vr5400
4211 *r3900:
4212 // start-sanitize-tx19
4213 *tx19:
4214 // end-sanitize-tx19
4215 {
4216   unsigned32 instruction = instruction_0;
4217   int destreg = ((instruction >> 6) & 0x0000001F);
4218   int fs = ((instruction >> 11) & 0x0000001F);
4219   int format = ((instruction >> 21) & 0x00000007);
4220   {
4221     if ((format == fmt_double) | 0)
4222       SignalException(ReservedInstruction,instruction);
4223     else
4224       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4225   }
4226 }
4227
4228
4229 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4230 "cvt.l.%s<FMT> f<FD>, f<FS>"
4231 *mipsIII:
4232 *mipsIV:
4233 *vr5000:
4234 // start-sanitize-vr4320
4235 *vr4320:
4236 // end-sanitize-vr4320
4237 // start-sanitize-vr5400
4238 *vr5400:
4239 // end-sanitize-vr5400
4240 *r3900:
4241 // start-sanitize-tx19
4242 *tx19:
4243 // end-sanitize-tx19
4244 {
4245   unsigned32 instruction = instruction_0;
4246   int destreg = ((instruction >> 6) & 0x0000001F);
4247   int fs = ((instruction >> 11) & 0x0000001F);
4248   int format = ((instruction >> 21) & 0x00000007);
4249   {
4250     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4251       SignalException(ReservedInstruction,instruction);
4252     else
4253       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4254   }
4255 }
4256
4257
4258 //
4259 // FIXME: Does not correctly differentiate between mips*
4260 //
4261 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4262 "cvt.s.%s<FMT> f<FD>, f<FS>"
4263 *mipsI,mipsII,mipsIII,mipsIV:
4264 *vr5000:
4265 // start-sanitize-vr4320
4266 *vr4320:
4267 // end-sanitize-vr4320
4268 // start-sanitize-vr5400
4269 *vr5400:
4270 // end-sanitize-vr5400
4271 *r3900:
4272 // start-sanitize-tx19
4273 *tx19:
4274 // end-sanitize-tx19
4275 {
4276   unsigned32 instruction = instruction_0;
4277   int destreg = ((instruction >> 6) & 0x0000001F);
4278   int fs = ((instruction >> 11) & 0x0000001F);
4279   int format = ((instruction >> 21) & 0x00000007);
4280   {
4281     if ((format == fmt_single) | 0)
4282       SignalException(ReservedInstruction,instruction);
4283     else
4284       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4285   }
4286 }
4287
4288
4289 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4290 "cvt.w.%s<FMT> f<FD>, f<FS>"
4291 *mipsI,mipsII,mipsIII,mipsIV:
4292 *vr5000:
4293 // start-sanitize-vr4320
4294 *vr4320:
4295 // end-sanitize-vr4320
4296 // start-sanitize-vr5400
4297 *vr5400:
4298 // end-sanitize-vr5400
4299 *r3900:
4300 // start-sanitize-tx19
4301 *tx19:
4302 // end-sanitize-tx19
4303 {
4304   unsigned32 instruction = instruction_0;
4305   int destreg = ((instruction >> 6) & 0x0000001F);
4306   int fs = ((instruction >> 11) & 0x0000001F);
4307   int format = ((instruction >> 21) & 0x00000007);
4308   {
4309     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4310       SignalException(ReservedInstruction,instruction);
4311     else
4312       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4313   }
4314 }
4315
4316
4317 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4318 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4319 *mipsI,mipsII,mipsIII,mipsIV:
4320 *vr5000:
4321 // start-sanitize-vr4320
4322 *vr4320:
4323 // end-sanitize-vr4320
4324 // start-sanitize-vr5400
4325 *vr5400:
4326 // end-sanitize-vr5400
4327 *r3900:
4328 // start-sanitize-tx19
4329 *tx19:
4330 // end-sanitize-tx19
4331 {
4332   unsigned32 instruction = instruction_0;
4333   int destreg = ((instruction >> 6) & 0x0000001F);
4334   int fs = ((instruction >> 11) & 0x0000001F);
4335   int ft = ((instruction >> 16) & 0x0000001F);
4336   int format = ((instruction >> 21) & 0x00000007);
4337   {
4338     if ((format != fmt_single) && (format != fmt_double))
4339       SignalException(ReservedInstruction,instruction);
4340     else
4341       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4342   }
4343 }
4344
4345
4346 // DMFC1
4347 // DMTC1
4348 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4349 "dm%s<X>c1 r<RT>, f<FS>"
4350 *mipsIII:
4351 {
4352   if (X)
4353     {
4354       if (SizeFGR() == 64)
4355         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4356       else if ((FS & 0x1) == 0)
4357         {
4358           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4359           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4360         }
4361     }
4362   else
4363     {
4364       if (SizeFGR() == 64)
4365         PENDING_FILL(RT,FGR[FS]);
4366       else if ((FS & 0x1) == 0)
4367         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4368       else
4369         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4370     }
4371 }
4372 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4373 "dm%s<X>c1 r<RT>, f<FS>"
4374 *mipsIV:
4375 *vr5000:
4376 // start-sanitize-vr4320
4377 *vr4320:
4378 // end-sanitize-vr4320
4379 // start-sanitize-vr5400
4380 *vr5400:
4381 // end-sanitize-vr5400
4382 // start-sanitize-r5900
4383 *r5900:
4384 // end-sanitize-r5900
4385 *r3900:
4386 // start-sanitize-tx19
4387 *tx19:
4388 // end-sanitize-tx19
4389 {
4390   if (X)
4391     {
4392       if (SizeFGR() == 64)
4393         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4394       else if ((FS & 0x1) == 0)
4395         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4396     }
4397   else
4398     {
4399       if (SizeFGR() == 64)
4400         GPR[RT] = FGR[FS];
4401       else if ((FS & 0x1) == 0)
4402         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4403       else
4404         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4405     }
4406 }
4407
4408
4409 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4410 "floor.l.%s<FMT> f<FD>, f<FS>"
4411 *mipsIII:
4412 *mipsIV:
4413 *vr5000:
4414 // start-sanitize-vr4320
4415 *vr4320:
4416 // end-sanitize-vr4320
4417 // start-sanitize-vr5400
4418 *vr5400:
4419 // end-sanitize-vr5400
4420 // start-sanitize-r5900
4421 *r5900:
4422 // end-sanitize-r5900
4423 *r3900:
4424 // start-sanitize-tx19
4425 *tx19:
4426 // end-sanitize-tx19
4427 {
4428   unsigned32 instruction = instruction_0;
4429   int destreg = ((instruction >> 6) & 0x0000001F);
4430   int fs = ((instruction >> 11) & 0x0000001F);
4431   int format = ((instruction >> 21) & 0x00000007);
4432   {
4433     if ((format != fmt_single) && (format != fmt_double))
4434       SignalException(ReservedInstruction,instruction);
4435     else
4436       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4437   }
4438 }
4439
4440
4441 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4442 "floor.w.%s<FMT> f<FD>, f<FS>"
4443 *mipsII:
4444 *mipsIII:
4445 *mipsIV:
4446 *vr5000:
4447 // start-sanitize-vr4320
4448 *vr4320:
4449 // end-sanitize-vr4320
4450 // start-sanitize-vr5400
4451 *vr5400:
4452 // end-sanitize-vr5400
4453 // start-sanitize-r5900
4454 *r5900:
4455 // end-sanitize-r5900
4456 *r3900:
4457 // start-sanitize-tx19
4458 *tx19:
4459 // end-sanitize-tx19
4460 {
4461   unsigned32 instruction = instruction_0;
4462   int destreg = ((instruction >> 6) & 0x0000001F);
4463   int fs = ((instruction >> 11) & 0x0000001F);
4464   int format = ((instruction >> 21) & 0x00000007);
4465   {
4466     if ((format != fmt_single) && (format != fmt_double))
4467       SignalException(ReservedInstruction,instruction);
4468     else
4469       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4470   }
4471 }
4472
4473
4474 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4475 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4476 *mipsII:
4477 *mipsIII:
4478 *mipsIV:
4479 *vr5000:
4480 // start-sanitize-vr4320
4481 *vr4320:
4482 // end-sanitize-vr4320
4483 // start-sanitize-vr5400
4484 *vr5400:
4485 // end-sanitize-vr5400
4486 *r3900:
4487 // start-sanitize-tx19
4488 *tx19:
4489 // end-sanitize-tx19
4490 {
4491   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4492 }
4493
4494
4495 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4496 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4497 *mipsIV:
4498 *vr5000:
4499 // start-sanitize-vr4320
4500 *vr4320:
4501 // end-sanitize-vr4320
4502 // start-sanitize-vr5400
4503 *vr5400:
4504 // end-sanitize-vr5400
4505 {
4506   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4507 }
4508
4509
4510
4511 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4512 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4513 *mipsI,mipsII,mipsIII,mipsIV:
4514 *vr5000:
4515 // start-sanitize-vr4320
4516 *vr4320:
4517 // end-sanitize-vr4320
4518 // start-sanitize-vr5400
4519 *vr5400:
4520 // end-sanitize-vr5400
4521 // start-sanitize-r5900
4522 *r5900:
4523 // end-sanitize-r5900
4524 *r3900:
4525 // start-sanitize-tx19
4526 *tx19:
4527 // end-sanitize-tx19
4528 {
4529   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4530 }
4531
4532
4533 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4534 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4535 *mipsIV:
4536 *vr5000:
4537 // start-sanitize-vr4320
4538 *vr4320:
4539 // end-sanitize-vr4320
4540 // start-sanitize-vr5400
4541 *vr5400:
4542 // end-sanitize-vr5400
4543 {
4544   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4545 }
4546
4547
4548
4549 //
4550 // FIXME: Not correct for mips*
4551 //
4552 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4553 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4554 *mipsIV:
4555 *vr5000:
4556 // start-sanitize-vr4320
4557 *vr4320:
4558 // end-sanitize-vr4320
4559 // start-sanitize-vr5400
4560 *vr5400:
4561 // end-sanitize-vr5400
4562 {
4563   unsigned32 instruction = instruction_0;
4564   int destreg = ((instruction >> 6) & 0x0000001F);
4565   int fs = ((instruction >> 11) & 0x0000001F);
4566   int ft = ((instruction >> 16) & 0x0000001F);
4567   int fr = ((instruction >> 21) & 0x0000001F);
4568   {
4569     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4570   }
4571 }
4572
4573
4574 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4575 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4576 *mipsIV:
4577 *vr5000:
4578 // start-sanitize-vr4320
4579 *vr4320:
4580 // end-sanitize-vr4320
4581 // start-sanitize-vr5400
4582 *vr5400:
4583 // end-sanitize-vr5400
4584 {
4585   unsigned32 instruction = instruction_0;
4586   int destreg = ((instruction >> 6) & 0x0000001F);
4587   int fs = ((instruction >> 11) & 0x0000001F);
4588   int ft = ((instruction >> 16) & 0x0000001F);
4589   int fr = ((instruction >> 21) & 0x0000001F);
4590   {
4591     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4592   }
4593 }
4594
4595
4596 // MFC1
4597 // MTC1
4598 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4599 "m%s<X>c1 r<RT>, f<FS>"
4600 *mipsI:
4601 *mipsII:
4602 *mipsIII:
4603 {
4604   if (X)
4605     { /*MTC1*/
4606       if (SizeFGR() == 64)
4607         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4608       else
4609         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4610     }
4611   else /*MFC1*/
4612     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4613 }
4614 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4615 "m%s<X>c1 r<RT>, f<FS>"
4616 *mipsIV:
4617 *vr5000:
4618 // start-sanitize-vr4320
4619 *vr4320:
4620 // end-sanitize-vr4320
4621 // start-sanitize-vr5400
4622 *vr5400:
4623 // end-sanitize-vr5400
4624 *r3900:
4625 // start-sanitize-tx19
4626 *tx19:
4627 // end-sanitize-tx19
4628 {
4629   if (X)
4630     /*MTC1*/
4631     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4632   else /*MFC1*/
4633     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4634 }
4635
4636
4637 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4638 "mov.%s<FMT> f<FD>, f<FS>"
4639 *mipsI,mipsII,mipsIII,mipsIV:
4640 *vr5000:
4641 // start-sanitize-vr4320
4642 *vr4320:
4643 // end-sanitize-vr4320
4644 // start-sanitize-vr5400
4645 *vr5400:
4646 // end-sanitize-vr5400
4647 *r3900:
4648 // start-sanitize-tx19
4649 *tx19:
4650 // end-sanitize-tx19
4651 {
4652   unsigned32 instruction = instruction_0;
4653   int destreg = ((instruction >> 6) & 0x0000001F);
4654   int fs = ((instruction >> 11) & 0x0000001F);
4655   int format = ((instruction >> 21) & 0x00000007);
4656   {
4657     StoreFPR(destreg,format,ValueFPR(fs,format));
4658   }
4659 }
4660
4661
4662 // MOVF
4663 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4664 "mov%s<TF> r<RD>, r<RS>, <CC>"
4665 *mipsIV:
4666 *vr5000:
4667 // start-sanitize-vr4320
4668 *vr4320:
4669 // end-sanitize-vr4320
4670 // start-sanitize-vr5400
4671 *vr5400:
4672 // end-sanitize-vr5400
4673 // start-sanitize-r5900
4674 *r5900:
4675 // end-sanitize-r5900
4676 {
4677   if (GETFCC(CC) == TF)
4678     GPR[RD] = GPR[RS];
4679 }
4680
4681
4682 // MOVF.fmt
4683 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4684 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4685 *mipsIV:
4686 *vr5000:
4687 // start-sanitize-vr4320
4688 *vr4320:
4689 // end-sanitize-vr4320
4690 // start-sanitize-vr5400
4691 *vr5400:
4692 // end-sanitize-vr5400
4693 // start-sanitize-r5900
4694 *r5900:
4695 // end-sanitize-r5900
4696 {
4697   unsigned32 instruction = instruction_0;
4698   int format = ((instruction >> 21) & 0x00000007);
4699   {
4700    if (GETFCC(CC) == TF)
4701      StoreFPR (FD, format, ValueFPR (FS, format));
4702    else
4703      StoreFPR (FD, format, ValueFPR (FD, format));
4704   }
4705 }
4706
4707
4708 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4709 *mipsIV:
4710 *vr5000:
4711 // start-sanitize-vr4320
4712 *vr4320:
4713 // end-sanitize-vr4320
4714 // start-sanitize-vr5400
4715 *vr5400:
4716 // end-sanitize-vr5400
4717 // start-sanitize-r5900
4718 *r5900:
4719 // end-sanitize-r5900
4720 {
4721   unsigned32 instruction = instruction_0;
4722   int destreg = ((instruction >> 6) & 0x0000001F);
4723   int fs = ((instruction >> 11) & 0x0000001F);
4724   int format = ((instruction >> 21) & 0x00000007);
4725   {
4726     StoreFPR(destreg,format,ValueFPR(fs,format));
4727   }
4728 }
4729
4730
4731 // MOVT see MOVtf
4732
4733
4734 // MOVT.fmt see MOVtf.fmt
4735
4736
4737
4738 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4739 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4740 *mipsIV:
4741 *vr5000:
4742 // start-sanitize-vr4320
4743 *vr4320:
4744 // end-sanitize-vr4320
4745 // start-sanitize-vr5400
4746 *vr5400:
4747 // end-sanitize-vr5400
4748 // start-sanitize-r5900
4749 *r5900:
4750 // end-sanitize-r5900
4751 {
4752   unsigned32 instruction = instruction_0;
4753   int destreg = ((instruction >> 6) & 0x0000001F);
4754   int fs = ((instruction >> 11) & 0x0000001F);
4755   int format = ((instruction >> 21) & 0x00000007);
4756   {
4757    StoreFPR(destreg,format,ValueFPR(fs,format));
4758   }
4759 }
4760
4761
4762 // MSUB.fmt
4763 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4764 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4765 *mipsIV:
4766 *vr5000:
4767 // start-sanitize-vr4320
4768 *vr4320:
4769 // end-sanitize-vr4320
4770 // start-sanitize-vr5400
4771 *vr5400:
4772 // end-sanitize-vr5400
4773 // start-sanitize-r5900
4774 *r5900:
4775 // end-sanitize-r5900
4776 {
4777   unsigned32 instruction = instruction_0;
4778   int destreg = ((instruction >> 6) & 0x0000001F);
4779   int fs = ((instruction >> 11) & 0x0000001F);
4780   int ft = ((instruction >> 16) & 0x0000001F);
4781   int fr = ((instruction >> 21) & 0x0000001F);
4782   {
4783     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4784   }
4785 }
4786
4787
4788 // MSUB.fmt
4789 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4790 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4791 *mipsIV:
4792 *vr5000:
4793 // start-sanitize-vr4320
4794 *vr4320:
4795 // end-sanitize-vr4320
4796 // start-sanitize-vr5400
4797 *vr5400:
4798 // end-sanitize-vr5400
4799 // start-sanitize-r5900
4800 *r5900:
4801 // end-sanitize-r5900
4802 {
4803   unsigned32 instruction = instruction_0;
4804   int destreg = ((instruction >> 6) & 0x0000001F);
4805   int fs = ((instruction >> 11) & 0x0000001F);
4806   int ft = ((instruction >> 16) & 0x0000001F);
4807   int fr = ((instruction >> 21) & 0x0000001F);
4808   {
4809    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4810   }
4811 }
4812
4813
4814 // MTC1 see MxC1
4815
4816
4817 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4818 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4819 *mipsI,mipsII,mipsIII,mipsIV:
4820 *vr5000:
4821 // start-sanitize-vr4320
4822 *vr4320:
4823 // end-sanitize-vr4320
4824 // start-sanitize-vr5400
4825 *vr5400:
4826 // end-sanitize-vr5400
4827 *r3900:
4828 // start-sanitize-tx19
4829 *tx19:
4830 // end-sanitize-tx19
4831 {
4832   unsigned32 instruction = instruction_0;
4833   int destreg = ((instruction >> 6) & 0x0000001F);
4834   int fs = ((instruction >> 11) & 0x0000001F);
4835   int ft = ((instruction >> 16) & 0x0000001F);
4836   int format = ((instruction >> 21) & 0x00000007);
4837   {
4838     if ((format != fmt_single) && (format != fmt_double))
4839       SignalException(ReservedInstruction,instruction);
4840     else
4841       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4842   }
4843 }
4844
4845
4846 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4847 "neg.%s<FMT> f<FD>, f<FS>"
4848 *mipsI,mipsII,mipsIII,mipsIV:
4849 *vr5000:
4850 // start-sanitize-vr4320
4851 *vr4320:
4852 // end-sanitize-vr4320
4853 // start-sanitize-vr5400
4854 *vr5400:
4855 // end-sanitize-vr5400
4856 *r3900:
4857 // start-sanitize-tx19
4858 *tx19:
4859 // end-sanitize-tx19
4860 {
4861   unsigned32 instruction = instruction_0;
4862   int destreg = ((instruction >> 6) & 0x0000001F);
4863   int fs = ((instruction >> 11) & 0x0000001F);
4864   int format = ((instruction >> 21) & 0x00000007);
4865   {
4866     if ((format != fmt_single) && (format != fmt_double))
4867       SignalException(ReservedInstruction,instruction);
4868     else
4869       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4870   }
4871 }
4872
4873
4874 // NMADD.fmt
4875 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4876 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4877 *mipsIV:
4878 *vr5000:
4879 // start-sanitize-vr4320
4880 *vr4320:
4881 // end-sanitize-vr4320
4882 // start-sanitize-vr5400
4883 *vr5400:
4884 // end-sanitize-vr5400
4885 {
4886   unsigned32 instruction = instruction_0;
4887   int destreg = ((instruction >> 6) & 0x0000001F);
4888   int fs = ((instruction >> 11) & 0x0000001F);
4889   int ft = ((instruction >> 16) & 0x0000001F);
4890   int fr = ((instruction >> 21) & 0x0000001F);
4891   {
4892    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4893   }
4894 }
4895
4896
4897 // NMADD.fmt
4898 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4899 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4900 *mipsIV:
4901 *vr5000:
4902 // start-sanitize-vr4320
4903 *vr4320:
4904 // end-sanitize-vr4320
4905 // start-sanitize-vr5400
4906 *vr5400:
4907 // end-sanitize-vr5400
4908 {
4909   unsigned32 instruction = instruction_0;
4910   int destreg = ((instruction >> 6) & 0x0000001F);
4911   int fs = ((instruction >> 11) & 0x0000001F);
4912   int ft = ((instruction >> 16) & 0x0000001F);
4913   int fr = ((instruction >> 21) & 0x0000001F);
4914   {
4915    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4916   }
4917 }
4918
4919
4920 // NMSUB.fmt
4921 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
4922 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4923 *mipsIV:
4924 *vr5000:
4925 // start-sanitize-vr4320
4926 *vr4320:
4927 // end-sanitize-vr4320
4928 // start-sanitize-vr5400
4929 *vr5400:
4930 // end-sanitize-vr5400
4931 {
4932   unsigned32 instruction = instruction_0;
4933   int destreg = ((instruction >> 6) & 0x0000001F);
4934   int fs = ((instruction >> 11) & 0x0000001F);
4935   int ft = ((instruction >> 16) & 0x0000001F);
4936   int fr = ((instruction >> 21) & 0x0000001F);
4937   {
4938    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4939   }
4940 }
4941
4942
4943 // NMSUB.fmt
4944 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
4945 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4946 *mipsIV:
4947 *vr5000:
4948 // start-sanitize-vr4320
4949 *vr4320:
4950 // end-sanitize-vr4320
4951 // start-sanitize-vr5400
4952 *vr5400:
4953 // end-sanitize-vr5400
4954 {
4955   unsigned32 instruction = instruction_0;
4956   int destreg = ((instruction >> 6) & 0x0000001F);
4957   int fs = ((instruction >> 11) & 0x0000001F);
4958   int ft = ((instruction >> 16) & 0x0000001F);
4959   int fr = ((instruction >> 21) & 0x0000001F);
4960   {
4961     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
4962   }
4963 }
4964
4965
4966 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
4967 "prefx <HINT>, r<INDEX>(r<BASE>)"
4968 *mipsIV:
4969 *vr5000:
4970 // start-sanitize-vr4320
4971 *vr4320:
4972 // end-sanitize-vr4320
4973 // start-sanitize-vr5400
4974 *vr5400:
4975 // end-sanitize-vr5400
4976 {
4977   unsigned32 instruction = instruction_0;
4978   int fs = ((instruction >> 11) & 0x0000001F);
4979   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4980   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4981   {
4982     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
4983     address_word paddr;
4984     int uncached;
4985     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4986       Prefetch(uncached,paddr,vaddr,isDATA,fs);
4987   }
4988 }
4989
4990 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
4991 *mipsIV:
4992 "recip.%s<FMT> f<FD>, f<FS>"
4993 *vr5000:
4994 // start-sanitize-vr4320
4995 *vr4320:
4996 // end-sanitize-vr4320
4997 // start-sanitize-vr5400
4998 *vr5400:
4999 // end-sanitize-vr5400
5000 {
5001   unsigned32 instruction = instruction_0;
5002   int destreg = ((instruction >> 6) & 0x0000001F);
5003   int fs = ((instruction >> 11) & 0x0000001F);
5004   int format = ((instruction >> 21) & 0x00000007);
5005   {
5006   if ((format != fmt_single) && (format != fmt_double))
5007    SignalException(ReservedInstruction,instruction);
5008   else
5009    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5010   }
5011 }
5012
5013
5014 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5015 "round.l.%s<FMT> f<FD>, f<FS>"
5016 *mipsIII:
5017 *mipsIV:
5018 *vr5000:
5019 // start-sanitize-vr4320
5020 *vr4320:
5021 // end-sanitize-vr4320
5022 // start-sanitize-vr5400
5023 *vr5400:
5024 // end-sanitize-vr5400
5025 // start-sanitize-r5900
5026 *r5900:
5027 // end-sanitize-r5900
5028 *r3900:
5029 // start-sanitize-tx19
5030 *tx19:
5031 // end-sanitize-tx19
5032 {
5033   unsigned32 instruction = instruction_0;
5034   int destreg = ((instruction >> 6) & 0x0000001F);
5035   int fs = ((instruction >> 11) & 0x0000001F);
5036   int format = ((instruction >> 21) & 0x00000007);
5037   {
5038     if ((format != fmt_single) && (format != fmt_double))
5039       SignalException(ReservedInstruction,instruction);
5040     else
5041       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5042   }
5043 }
5044
5045
5046 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5047 "round.w.%s<FMT> f<FD>, f<FS>"
5048 *mipsII:
5049 *mipsIII:
5050 *mipsIV:
5051 *vr5000:
5052 // start-sanitize-vr4320
5053 *vr4320:
5054 // end-sanitize-vr4320
5055 // start-sanitize-vr5400
5056 *vr5400:
5057 // end-sanitize-vr5400
5058 // start-sanitize-r5900
5059 *r5900:
5060 // end-sanitize-r5900
5061 *r3900:
5062 // start-sanitize-tx19
5063 *tx19:
5064 // end-sanitize-tx19
5065 {
5066   unsigned32 instruction = instruction_0;
5067   int destreg = ((instruction >> 6) & 0x0000001F);
5068   int fs = ((instruction >> 11) & 0x0000001F);
5069   int format = ((instruction >> 21) & 0x00000007);
5070   {
5071   if ((format != fmt_single) && (format != fmt_double))
5072    SignalException(ReservedInstruction,instruction);
5073   else
5074    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5075   }
5076 }
5077
5078
5079 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5080 *mipsIV:
5081 "rsqrt.%s<FMT> f<FD>, f<FS>"
5082 *vr5000:
5083 // start-sanitize-vr4320
5084 *vr4320:
5085 // end-sanitize-vr4320
5086 // start-sanitize-vr5400
5087 *vr5400:
5088 // end-sanitize-vr5400
5089 {
5090   unsigned32 instruction = instruction_0;
5091   int destreg = ((instruction >> 6) & 0x0000001F);
5092   int fs = ((instruction >> 11) & 0x0000001F);
5093   int format = ((instruction >> 21) & 0x00000007);
5094   {
5095   if ((format != fmt_single) && (format != fmt_double))
5096    SignalException(ReservedInstruction,instruction);
5097   else
5098    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5099   }
5100 }
5101
5102
5103 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5104 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5105 *mipsII:
5106 *mipsIII:
5107 *mipsIV:
5108 *vr5000:
5109 // start-sanitize-vr4320
5110 *vr4320:
5111 // end-sanitize-vr4320
5112 // start-sanitize-vr5400
5113 *vr5400:
5114 // end-sanitize-vr5400
5115 *r3900:
5116 // start-sanitize-tx19
5117 *tx19:
5118 // end-sanitize-tx19
5119 {
5120   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5121 }
5122
5123
5124 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5125 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5126 *mipsIV:
5127 *vr5000:
5128 // start-sanitize-vr4320
5129 *vr4320:
5130 // end-sanitize-vr4320
5131 // start-sanitize-vr5400
5132 *vr5400:
5133 // end-sanitize-vr5400
5134 {
5135   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5136 }
5137
5138
5139 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5140 "sqrt.%s<FMT> f<FD>, f<FS>"
5141 *mipsII:
5142 *mipsIII:
5143 *mipsIV:
5144 *vr5000:
5145 // start-sanitize-vr4320
5146 *vr4320:
5147 // end-sanitize-vr4320
5148 // start-sanitize-vr5400
5149 *vr5400:
5150 // end-sanitize-vr5400
5151 *r3900:
5152 // start-sanitize-tx19
5153 *tx19:
5154 // end-sanitize-tx19
5155 {
5156   unsigned32 instruction = instruction_0;
5157   int destreg = ((instruction >> 6) & 0x0000001F);
5158   int fs = ((instruction >> 11) & 0x0000001F);
5159   int format = ((instruction >> 21) & 0x00000007);
5160   {
5161     if ((format != fmt_single) && (format != fmt_double))
5162       SignalException(ReservedInstruction,instruction);
5163     else
5164       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5165   }
5166 }
5167
5168
5169 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5170 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5171 *mipsI,mipsII,mipsIII,mipsIV:
5172 *vr5000:
5173 // start-sanitize-vr4320
5174 *vr4320:
5175 // end-sanitize-vr4320
5176 // start-sanitize-vr5400
5177 *vr5400:
5178 // end-sanitize-vr5400
5179 *r3900:
5180 // start-sanitize-tx19
5181 *tx19:
5182 // end-sanitize-tx19
5183 {
5184   unsigned32 instruction = instruction_0;
5185   int destreg = ((instruction >> 6) & 0x0000001F);
5186   int fs = ((instruction >> 11) & 0x0000001F);
5187   int ft = ((instruction >> 16) & 0x0000001F);
5188   int format = ((instruction >> 21) & 0x00000007);
5189   {
5190     if ((format != fmt_single) && (format != fmt_double))
5191       SignalException(ReservedInstruction,instruction);
5192     else
5193       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5194   }
5195 }
5196
5197
5198
5199 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5200 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5201 *mipsI,mipsII,mipsIII,mipsIV:
5202 *vr5000:
5203 // start-sanitize-vr4320
5204 *vr4320:
5205 // end-sanitize-vr4320
5206 // start-sanitize-vr5400
5207 *vr5400:
5208 // end-sanitize-vr5400
5209 // start-sanitize-r5900
5210 *r5900:
5211 // end-sanitize-r5900
5212 *r3900:
5213 // start-sanitize-tx19
5214 *tx19:
5215 // end-sanitize-tx19
5216 {
5217   unsigned32 instruction = instruction_0;
5218   signed_word offset = EXTEND16 (OFFSET);
5219   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5220   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5221   {
5222     address_word vaddr = ((uword64)op1 + offset);
5223     address_word paddr;
5224     int uncached;
5225     if ((vaddr & 3) != 0)
5226       SignalExceptionAddressStore();
5227     else
5228       {
5229         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5230           {
5231             uword64 memval = 0;
5232             uword64 memval1 = 0;
5233             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5234             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5235             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5236             unsigned int byte;
5237             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5238             byte = ((vaddr & mask) ^ bigendiancpu);
5239             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5240             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5241           }
5242       }
5243   }
5244 }
5245
5246
5247 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5248 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5249 *mipsIV:
5250 *vr5000:
5251 // start-sanitize-vr4320
5252 *vr4320:
5253 // end-sanitize-vr4320
5254 // start-sanitize-vr5400
5255 *vr5400:
5256 // end-sanitize-vr5400
5257 {
5258   unsigned32 instruction = instruction_0;
5259   int fs = ((instruction >> 11) & 0x0000001F);
5260   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5261   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5262   {
5263    address_word vaddr = ((unsigned64)op1 + op2);
5264    address_word paddr;
5265    int uncached;
5266    if ((vaddr & 3) != 0)
5267     SignalExceptionAddressStore();
5268    else
5269    {
5270     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5271     {
5272      unsigned64 memval = 0;
5273      unsigned64 memval1 = 0;
5274      unsigned64 mask = 0x7;
5275      unsigned int byte;
5276      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5277      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5278      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5279       {
5280        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5281       }
5282     }
5283    }
5284   }
5285 }
5286
5287
5288 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5289 "trunc.l.%s<FMT> f<FD>, f<FS>"
5290 *mipsIII:
5291 *mipsIV:
5292 *vr5000:
5293 // start-sanitize-vr4320
5294 *vr4320:
5295 // end-sanitize-vr4320
5296 // start-sanitize-vr5400
5297 *vr5400:
5298 // end-sanitize-vr5400
5299 // start-sanitize-r5900
5300 *r5900:
5301 // end-sanitize-r5900
5302 *r3900:
5303 // start-sanitize-tx19
5304 *tx19:
5305 // end-sanitize-tx19
5306 {
5307   unsigned32 instruction = instruction_0;
5308   int destreg = ((instruction >> 6) & 0x0000001F);
5309   int fs = ((instruction >> 11) & 0x0000001F);
5310   int format = ((instruction >> 21) & 0x00000007);
5311   {
5312   if ((format != fmt_single) && (format != fmt_double))
5313    SignalException(ReservedInstruction,instruction);
5314   else
5315    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5316   }
5317 }
5318
5319
5320 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5321 "trunc.w.%s<FMT> f<FD>, f<FS>"
5322 *mipsII:
5323 *mipsIII:
5324 *mipsIV:
5325 *vr5000:
5326 // start-sanitize-vr4320
5327 *vr4320:
5328 // end-sanitize-vr4320
5329 // start-sanitize-vr5400
5330 *vr5400:
5331 // end-sanitize-vr5400
5332 // start-sanitize-r5900
5333 *r5900:
5334 // end-sanitize-r5900
5335 *r3900:
5336 // start-sanitize-tx19
5337 *tx19:
5338 // end-sanitize-tx19
5339 {
5340   unsigned32 instruction = instruction_0;
5341   int destreg = ((instruction >> 6) & 0x0000001F);
5342   int fs = ((instruction >> 11) & 0x0000001F);
5343   int format = ((instruction >> 21) & 0x00000007);
5344   {
5345   if ((format != fmt_single) && (format != fmt_double))
5346    SignalException(ReservedInstruction,instruction);
5347   else
5348    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5349   }
5350 }
5351
5352 \f
5353 //
5354 // MIPS Architecture:
5355 //
5356 //        System Control Instruction Set (COP0)
5357 //
5358
5359
5360 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5361 "bc0f <OFFSET>"
5362 *mipsI,mipsII,mipsIII,mipsIV:
5363 *vr5000:
5364 // start-sanitize-vr4320
5365 *vr4320:
5366 // end-sanitize-vr4320
5367 // start-sanitize-vr5400
5368 *vr5400:
5369 // end-sanitize-vr5400
5370 // start-sanitize-r5900
5371 *r5900:
5372 // start-sanitize-sky
5373 {
5374 #ifdef TARGET_SKY
5375   extern int sky_cpcond0A;
5376   if (sky_cpcond0A == 0)
5377     {
5378       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
5379       TRACE_BRANCH_RESULT (dest);
5380       DELAY_SLOT (dest);
5381     }
5382   else
5383     {
5384       TRACE_BRANCH_RESULT (NIA);
5385     }
5386 #endif
5387 }
5388 // end-sanitize-sky
5389 // end-sanitize-r5900
5390
5391
5392 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5393 "bc0fl <OFFSET>"
5394 *mipsI,mipsII,mipsIII,mipsIV:
5395 *vr5000:
5396 // start-sanitize-vr4320
5397 *vr4320:
5398 // end-sanitize-vr4320
5399 // start-sanitize-vr5400
5400 *vr5400:
5401 // end-sanitize-vr5400
5402 // start-sanitize-r5900
5403 *r5900:
5404 // start-sanitize-sky
5405 {
5406 #ifdef TARGET_SKY
5407   extern int sky_cpcond0A;
5408   if (sky_cpcond0A == 0)
5409     {
5410       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
5411       TRACE_BRANCH_RESULT (dest);
5412       DELAY_SLOT (dest);
5413     }
5414   else
5415     {
5416       TRACE_BRANCH_RESULT (0);
5417       NULLIFY_NEXT_INSTRUCTION ();
5418     }
5419 #endif
5420 }
5421 // end-sanitize-sky
5422 // end-sanitize-r5900
5423
5424
5425 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5426 "bc0t <OFFSET>"
5427 *mipsI,mipsII,mipsIII,mipsIV:
5428 // start-sanitize-r5900
5429 *r5900:
5430 // start-sanitize-sky
5431 {
5432 #ifdef TARGET_SKY
5433   extern int sky_cpcond0A;
5434   if (sky_cpcond0A != 0)
5435     {
5436       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
5437       TRACE_BRANCH_RESULT (dest);
5438       DELAY_SLOT (dest);
5439     }
5440   else
5441     {
5442       TRACE_BRANCH_RESULT (NIA);
5443     }
5444 #endif
5445 }
5446 // end-sanitize-sky
5447 // end-sanitize-r5900
5448
5449
5450
5451 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5452 "bc0tl <OFFSET>"
5453 *mipsI,mipsII,mipsIII,mipsIV:
5454 *vr5000:
5455 // start-sanitize-vr4320
5456 *vr4320:
5457 // end-sanitize-vr4320
5458 // start-sanitize-vr5400
5459 *vr5400:
5460 // end-sanitize-vr5400
5461 // start-sanitize-r5900
5462 *r5900:
5463 // start-sanitize-sky
5464 {
5465 #ifdef TARGET_SKY
5466   extern int sky_cpcond0A;
5467   if (sky_cpcond0A != 0)
5468     {
5469       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
5470       TRACE_BRANCH_RESULT (dest);
5471       DELAY_SLOT (dest);
5472     }
5473   else
5474     {
5475       TRACE_BRANCH_RESULT (0);
5476       NULLIFY_NEXT_INSTRUCTION ();
5477     }
5478 #endif
5479 }
5480 // end-sanitize-sky
5481 // end-sanitize-r5900
5482
5483
5484 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5485 *mipsIII:
5486 *mipsIV:
5487 *vr5000:
5488 // start-sanitize-vr4320
5489 *vr4320:
5490 // end-sanitize-vr4320
5491 // start-sanitize-vr5400
5492 *vr5400:
5493 // end-sanitize-vr5400
5494 // start-sanitize-r5900
5495 *r5900:
5496 // end-sanitize-r5900
5497 *r3900:
5498 // start-sanitize-tx19
5499 *tx19:
5500 // end-sanitize-tx19
5501 {
5502   unsigned32 instruction = instruction_0;
5503   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5504   int hint = ((instruction >> 16) & 0x0000001F);
5505   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5506   {
5507     address_word vaddr = (op1 + offset);
5508     address_word paddr;
5509     int uncached;
5510     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5511       CacheOp(hint,vaddr,paddr,instruction);
5512   }
5513 }
5514
5515
5516 010000,10000,000000000000000,111001:COP0:32::DI
5517 "di"
5518 *mipsI,mipsII,mipsIII,mipsIV:
5519 *vr5000:
5520 // start-sanitize-vr4320
5521 *vr4320:
5522 // end-sanitize-vr4320
5523 // start-sanitize-vr5400
5524 *vr5400:
5525 // end-sanitize-vr5400
5526 // start-sanitize-r5900
5527 *r5900:
5528 // end-sanitize-r5900
5529
5530
5531 010000,10000,000000000000000,111000:COP0:32::EI
5532 "ei"
5533 *mipsI,mipsII,mipsIII,mipsIV:
5534 *vr5000:
5535 // start-sanitize-vr4320
5536 *vr4320:
5537 // end-sanitize-vr4320
5538 // start-sanitize-vr5400
5539 *vr5400:
5540 // end-sanitize-vr5400
5541 // start-sanitize-r5900
5542 *r5900:
5543 // end-sanitize-r5900
5544
5545
5546 010000,10000,000000000000000,011000:COP0:32::ERET
5547 "eret"
5548 *mipsIII:
5549 *mipsIV:
5550 *vr5000:
5551 // start-sanitize-vr4320
5552 *vr4320:
5553 // end-sanitize-vr4320
5554 // start-sanitize-vr5400
5555 *vr5400:
5556 // end-sanitize-vr5400
5557 // start-sanitize-r5900
5558 *r5900:
5559 // end-sanitize-r5900
5560 {
5561   if (SR & status_ERL)
5562     {
5563       /* Oops, not yet available */
5564       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5565       NIA = EPC;
5566       SR &= ~status_ERL;
5567     }
5568   else
5569     {
5570       NIA = EPC;
5571       SR &= ~status_EXL;
5572     }
5573 }
5574
5575
5576 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5577 "mfc0 r<RT>, r<RD> # <REGX>"
5578 *mipsI,mipsII,mipsIII,mipsIV:
5579 *r3900:
5580 *vr5000:
5581 // start-sanitize-vr4320
5582 *vr4320:
5583 // end-sanitize-vr4320
5584 // start-sanitize-vr5400
5585 *vr5400:
5586 // end-sanitize-vr5400
5587 // start-sanitize-r5900
5588 *r5900:
5589 // end-sanitize-r5900
5590 {
5591   TRACE_ALU_INPUT0 ();
5592   DecodeCoproc (instruction_0);
5593   TRACE_ALU_RESULT (GPR[RT]);
5594 }
5595
5596 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5597 "mtc0 r<RT>, r<RD> # <REGX>"
5598 *mipsI,mipsII,mipsIII,mipsIV:
5599 // start-sanitize-tx19
5600 *tx19:
5601 // end-sanitize-tx19
5602 *r3900:
5603 // start-sanitize-vr4320
5604 *vr4320:
5605 // end-sanitize-vr4320
5606 *vr5000:
5607 // start-sanitize-vr5400
5608 *vr5400:
5609 // end-sanitize-vr5400
5610 // start-sanitize-r5900
5611 *r5900:
5612 // end-sanitize-r5900
5613 {
5614   DecodeCoproc (instruction_0);
5615 }
5616
5617
5618 010000,10000,000000000000000,010000:COP0:32::RFE
5619 "rfe"
5620 *mipsI,mipsII,mipsIII,mipsIV:
5621 // start-sanitize-tx19
5622 *tx19:
5623 // end-sanitize-tx19
5624 *r3900:
5625 // start-sanitize-vr4320
5626 *vr4320:
5627 // end-sanitize-vr4320
5628 *vr5000:
5629 // start-sanitize-vr5400
5630 *vr5400:
5631 // end-sanitize-vr5400
5632 // start-sanitize-r5900
5633 *r5900:
5634 // end-sanitize-r5900
5635 {
5636   DecodeCoproc (instruction_0);
5637 }
5638
5639
5640 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5641 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5642 *mipsI,mipsII,mipsIII,mipsIV:
5643 // start-sanitize-r5900
5644 *r5900:
5645 // end-sanitize-r5900
5646 *r3900:
5647 // start-sanitize-tx19
5648 *tx19:
5649 // end-sanitize-tx19
5650 {
5651   DecodeCoproc (instruction_0);
5652 }
5653
5654
5655
5656 010000,10000,000000000000000,001000:COP0:32::TLBP
5657 "tlbp"
5658 *mipsI,mipsII,mipsIII,mipsIV:
5659 *vr5000:
5660 // start-sanitize-vr4320
5661 *vr4320:
5662 // end-sanitize-vr4320
5663 // start-sanitize-vr5400
5664 *vr5400:
5665 // end-sanitize-vr5400
5666 // start-sanitize-r5900
5667 *r5900:
5668 // end-sanitize-r5900
5669
5670
5671 010000,10000,000000000000000,000001:COP0:32::TLBR
5672 "tlbr"
5673 *mipsI,mipsII,mipsIII,mipsIV:
5674 *vr5000:
5675 // start-sanitize-vr4320
5676 *vr4320:
5677 // end-sanitize-vr4320
5678 // start-sanitize-vr5400
5679 *vr5400:
5680 // end-sanitize-vr5400
5681 // start-sanitize-r5900
5682 *r5900:
5683 // end-sanitize-r5900
5684
5685
5686 010000,10000,000000000000000,000010:COP0:32::TLBWI
5687 "tlbwi"
5688 *mipsI,mipsII,mipsIII,mipsIV:
5689 *vr5000:
5690 // start-sanitize-vr4320
5691 *vr4320:
5692 // end-sanitize-vr4320
5693 // start-sanitize-vr5400
5694 *vr5400:
5695 // end-sanitize-vr5400
5696 // start-sanitize-r5900
5697 *r5900:
5698 // end-sanitize-r5900
5699
5700
5701 010000,10000,000000000000000,000110:COP0:32::TLBWR
5702 "tlbwr"
5703 *mipsI,mipsII,mipsIII,mipsIV:
5704 *vr5000:
5705 // start-sanitize-vr4320
5706 *vr4320:
5707 // end-sanitize-vr4320
5708 // start-sanitize-vr5400
5709 *vr5400:
5710 // end-sanitize-vr5400
5711 // start-sanitize-r5900
5712 *r5900:
5713 // end-sanitize-r5900
5714
5715 \f
5716 :include:::m16.igen
5717 // start-sanitize-vr4320
5718 :include::vr4320:vr4320.igen
5719 // end-sanitize-vr4320
5720 // start-sanitize-vr5400
5721 :include::vr5400:vr5400.igen
5722 :include:64,f::mdmx.igen
5723 // end-sanitize-vr5400
5724 // start-sanitize-r5900
5725 :include::r5900:r5900.igen
5726 // end-sanitize-r5900
5727 :include:::tx.igen
5728 \f
5729 // start-sanitize-cygnus-never
5730
5731 // // FIXME FIXME FIXME What is this instruction?
5732 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5733 // *mipsI:
5734 // *mipsII:
5735 // *mipsIII:
5736 // *mipsIV:
5737 // // start-sanitize-r5900
5738 // *r5900:
5739 // // end-sanitize-r5900
5740 // *r3900:
5741 // // start-sanitize-tx19
5742 // *tx19:
5743 // // end-sanitize-tx19
5744 // {
5745 //   unsigned32 instruction = instruction_0;
5746 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5747 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5748 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5749 //   {
5750 //     if (CoProcPresent(3))
5751 //       SignalException(CoProcessorUnusable);
5752 //     else
5753 //       SignalException(ReservedInstruction,instruction);
5754 //   }
5755 // }
5756
5757 // end-sanitize-cygnus-never
5758 // start-sanitize-cygnus-never
5759
5760 // // FIXME FIXME FIXME What is this?
5761 // 11100,******,00001:RR:16::SDBBP
5762 // *mips16:
5763 // {
5764 //   unsigned32 instruction = instruction_0;
5765 //   if (have_extendval)
5766 //     SignalException (ReservedInstruction, instruction);
5767 //   {
5768 //     SignalException(DebugBreakPoint,instruction);
5769 //   }
5770 // }
5771
5772 // end-sanitize-cygnus-never
5773 // start-sanitize-cygnus-never
5774
5775 // // FIXME FIXME FIXME What is this?
5776 // 000000,********************,001110:SPECIAL:32::SDBBP
5777 // *r3900:
5778 // {
5779 //   unsigned32 instruction = instruction_0;
5780 //   {
5781 //     SignalException(DebugBreakPoint,instruction);
5782 //   }
5783 // }
5784
5785 // end-sanitize-cygnus-never
5786 // start-sanitize-cygnus-never
5787
5788 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5789 // // isn't yet reconized by this simulator.
5790 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5791 // *vr4100:
5792 // {
5793 //   unsigned32 instruction = instruction_0;
5794 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5795 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5796 //   {
5797 //     CHECKHILO("Multiply-Add");
5798 //     {
5799 //       unsigned64 temp = (op1 * op2);
5800 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5801 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5802 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5803 //     }
5804 //   }
5805 // }
5806
5807 // end-sanitize-cygnus-never
5808 // start-sanitize-cygnus-never
5809
5810 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5811 // // isn't yet reconized by this simulator.
5812 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5813 // *vr4100:
5814 // {
5815 //   unsigned32 instruction = instruction_0;
5816 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5817 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5818 //   {
5819 //     CHECKHILO("Multiply-Add");
5820 //     {
5821 //       unsigned64 temp = (op1 * op2);
5822 //       LO = LO + temp;
5823 //     }
5824 //   }
5825 // }
5826
5827 // end-sanitize-cygnus-never