sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator
  34 :model:::mipsI:mips3000:
  35 :model:::mipsII:mips6000:
  36 :model:::mipsIII:mips4000:
  37 :model:::mipsIV:mips8000:
  38 :model:::mips16:mips16:
  39 // start-sanitize-r5900
  40 :model:::r5900:mips5900:
  41 // end-sanitize-r5900
  42 :model:::r3900:mips3900:
  43 // start-sanitize-tx19
  44 :model:::tx19:tx19:
  45 // end-sanitize-tx19
  46 // start-sanitize-vr4320
  47 :model:::vr4320:mips4320:
  48 // end-sanitize-vr4320
  49 // start-sanitize-vr5400
  50 :model:::vr5400:mips5400:
  51 :model:::mdmx:mdmx:
  52 // end-sanitize-vr5400
  53 :model:::vr5000:mips5000:
  54
  55
  56
  57 // Pseudo instructions known by IGEN
  58 :internal::::illegal:
  59 {
  60   SignalException (ReservedInstruction, 0);
  61 }
  62
  63
  64 // Pseudo instructions known by interp.c
  65 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  66 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  67 "rsvd <OP>"
  68 {
  69   SignalException (ReservedInstruction, instruction_0);
  70 }
  71
  72
  73
  74 //
  75 // Mips Architecture:
  76 //
  77 //        CPU Instruction Set (mipsI - mipsIV)
  78 //
  79
  80
  81 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
  82 "add r<RD>, r<RS>, r<RT>"
  83 *mipsI,mipsII,mipsIII,mipsIV:
  84 *vr5000:
  85 // start-sanitize-vr4320
  86 *vr4320:
  87 // end-sanitize-vr4320
  88 // start-sanitize-vr5400
  89 *vr5400:
  90 // end-sanitize-vr5400
  91 // start-sanitize-r5900
  92 *r5900:
  93 // end-sanitize-r5900
  94 *r3900:
  95 // start-sanitize-tx19
  96 *tx19:
  97 // end-sanitize-tx19
  98 {
  99   ALU32_BEGIN (GPR[RS]);
 100   ALU32_ADD (GPR[RT]);
 101   ALU32_END (GPR[RD]);
 102 }
 103
 104
 105 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 106 "addi r<RT>, r<RS>, IMMEDIATE"
 107 *mipsI,mipsII,mipsIII,mipsIV:
 108 *vr5000:
 109 // start-sanitize-vr4320
 110 *vr4320:
 111 // end-sanitize-vr4320
 112 // start-sanitize-vr5400
 113 *vr5400:
 114 // end-sanitize-vr5400
 115 // start-sanitize-r5900
 116 *r5900:
 117 // end-sanitize-r5900
 118 *r3900:
 119 // start-sanitize-tx19
 120 *tx19:
 121 // end-sanitize-tx19
 122 {
 123   ALU32_BEGIN (GPR[RS]);
 124   ALU32_ADD (EXTEND16 (IMMEDIATE));
 125   ALU32_END (GPR[RT]);
 126 }
 127
 128
 129 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 130 "add r<RT>, r<RS>, <IMMEDIATE>"
 131 *mipsI,mipsII,mipsIII,mipsIV:
 132 *vr5000:
 133 // start-sanitize-vr4320
 134 *vr4320:
 135 // end-sanitize-vr4320
 136 // start-sanitize-vr5400
 137 *vr5400:
 138 // end-sanitize-vr5400
 139 // start-sanitize-r5900
 140 *r5900:
 141 // end-sanitize-r5900
 142 *r3900:
 143 // start-sanitize-tx19
 144 *tx19:
 145 // end-sanitize-tx19
 146 {
 147   signed32 temp = GPR[RS] + EXTEND16 (IMMEDIATE);
 148   GPR[RT] = EXTEND32 (temp);
 149 }
 150
 151
 152 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 153 *mipsI,mipsII,mipsIII,mipsIV:
 154 *vr5000:
 155 // start-sanitize-vr4320
 156 *vr4320:
 157 // end-sanitize-vr4320
 158 // start-sanitize-vr5400
 159 *vr5400:
 160 // end-sanitize-vr5400
 161 // start-sanitize-r5900
 162 *r5900:
 163 // end-sanitize-r5900
 164 *r3900:
 165 // start-sanitize-tx19
 166 *tx19:
 167 // end-sanitize-tx19
 168 {
 169   signed32 temp = GPR[RS] + GPR[RT];
 170   GPR[RD] = EXTEND32 (temp);
 171 }
 172
 173
 174 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 175 "and r<RD>, r<RS>, r<RT>"
 176 *mipsI,mipsII,mipsIII,mipsIV:
 177 *vr5000:
 178 // start-sanitize-vr4320
 179 *vr4320:
 180 // end-sanitize-vr4320
 181 // start-sanitize-vr5400
 182 *vr5400:
 183 // end-sanitize-vr5400
 184 // start-sanitize-r5900
 185 *r5900:
 186 // end-sanitize-r5900
 187 *r3900:
 188 // start-sanitize-tx19
 189 *tx19:
 190 // end-sanitize-tx19
 191 {
 192   GPR[RD] = GPR[RS] & GPR[RT];
 193 }
 194
 195
 196 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 197 "and r<RT>, r<RS>, <IMMEDIATE>"
 198 *mipsI,mipsII,mipsIII,mipsIV:
 199 *vr5000:
 200 // start-sanitize-vr4320
 201 *vr4320:
 202 // end-sanitize-vr4320
 203 // start-sanitize-vr5400
 204 *vr5400:
 205 // end-sanitize-vr5400
 206 // start-sanitize-r5900
 207 *r5900:
 208 // end-sanitize-r5900
 209 *r3900:
 210 // start-sanitize-tx19
 211 *tx19:
 212 // end-sanitize-tx19
 213 {
 214   GPR[RT] = GPR[RS] & IMMEDIATE;
 215 }
 216
 217
 218 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 219 "beq r<RS>, r<RT>, <OFFSET>"
 220 *mipsI,mipsII,mipsIII,mipsIV:
 221 *vr5000:
 222 // start-sanitize-vr4320
 223 *vr4320:
 224 // end-sanitize-vr4320
 225 // start-sanitize-vr5400
 226 *vr5400:
 227 // end-sanitize-vr5400
 228 // start-sanitize-r5900
 229 *r5900:
 230 // end-sanitize-r5900
 231 *r3900:
 232 // start-sanitize-tx19
 233 *tx19:
 234 // end-sanitize-tx19
 235 {
 236   address_word offset = EXTEND16 (OFFSET) << 2;
 237   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 238     DELAY_SLOT (NIA + offset);
 239 }
 240
 241
 242 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 243 "beql r<RS>, r<RT>, <OFFSET>"
 244 *mipsII:
 245 *mipsIII:
 246 *mipsIV:
 247 *vr5000:
 248 // start-sanitize-vr4320
 249 *vr4320:
 250 // end-sanitize-vr4320
 251 // start-sanitize-vr5400
 252 *vr5400:
 253 // end-sanitize-vr5400
 254 // start-sanitize-r5900
 255 *r5900:
 256 // end-sanitize-r5900
 257 *r3900:
 258 // start-sanitize-tx19
 259 *tx19:
 260 // end-sanitize-tx19
 261 {
 262   address_word offset = EXTEND16 (OFFSET) << 2;
 263   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 264     DELAY_SLOT (NIA + offset);
 265   else
 266     NULLIFY_NEXT_INSTRUCTION ();
 267 }
 268
 269
 270 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 271 "bgez r<RS>, <OFFSET>"
 272 *mipsI,mipsII,mipsIII,mipsIV:
 273 *vr5000:
 274 // start-sanitize-vr4320
 275 *vr4320:
 276 // end-sanitize-vr4320
 277 // start-sanitize-vr5400
 278 *vr5400:
 279 // end-sanitize-vr5400
 280 // start-sanitize-r5900
 281 *r5900:
 282 // end-sanitize-r5900
 283 *r3900:
 284 // start-sanitize-tx19
 285 *tx19:
 286 // end-sanitize-tx19
 287 {
 288   address_word offset = EXTEND16 (OFFSET) << 2;
 289   if ((signed_word) GPR[RS] >= 0)
 290     DELAY_SLOT (NIA + offset);
 291 }
 292
 293
 294 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 295 "bgezal r<RS>, <OFFSET>"
 296 *mipsI,mipsII,mipsIII,mipsIV:
 297 *vr5000:
 298 // start-sanitize-vr4320
 299 *vr4320:
 300 // end-sanitize-vr4320
 301 // start-sanitize-vr5400
 302 *vr5400:
 303 // end-sanitize-vr5400
 304 // start-sanitize-r5900
 305 *r5900:
 306 // end-sanitize-r5900
 307 *r3900:
 308 // start-sanitize-tx19
 309 *tx19:
 310 // end-sanitize-tx19
 311 {
 312   address_word offset = EXTEND16 (OFFSET) << 2;
 313   RA = (CIA + 8);
 314   if ((signed_word) GPR[RS] >= 0)
 315     DELAY_SLOT (NIA + offset);
 316 }
 317
 318
 319 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 320 "bgezall r<RS>, <OFFSET>"
 321 *mipsII:
 322 *mipsIII:
 323 *mipsIV:
 324 *vr5000:
 325 // start-sanitize-vr4320
 326 *vr4320:
 327 // end-sanitize-vr4320
 328 // start-sanitize-vr5400
 329 *vr5400:
 330 // end-sanitize-vr5400
 331 // start-sanitize-r5900
 332 *r5900:
 333 // end-sanitize-r5900
 334 *r3900:
 335 // start-sanitize-tx19
 336 *tx19:
 337 // end-sanitize-tx19
 338 {
 339   address_word offset = EXTEND16 (OFFSET) << 2;
 340   RA = (CIA + 8);
 341   /* NOTE: The branch occurs AFTER the next instruction has been
 342      executed */
 343   if ((signed_word) GPR[RS] >= 0)
 344     DELAY_SLOT (NIA + offset);
 345   else
 346     NULLIFY_NEXT_INSTRUCTION ();
 347 }
 348
 349
 350 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 351 "bgezl r<RS>, <OFFSET>"
 352 *mipsII:
 353 *mipsIII:
 354 *mipsIV:
 355 *vr5000:
 356 // start-sanitize-vr4320
 357 *vr4320:
 358 // end-sanitize-vr4320
 359 // start-sanitize-vr5400
 360 *vr5400:
 361 // end-sanitize-vr5400
 362 // start-sanitize-r5900
 363 *r5900:
 364 // end-sanitize-r5900
 365 *r3900:
 366 // start-sanitize-tx19
 367 *tx19:
 368 // end-sanitize-tx19
 369 {
 370   address_word offset = EXTEND16 (OFFSET) << 2;
 371   if ((signed_word) GPR[RS] >= 0)
 372     DELAY_SLOT (NIA + offset);
 373   else
 374     NULLIFY_NEXT_INSTRUCTION ();
 375 }
 376
 377
 378 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 379 "bgtz r<RS>, <OFFSET>"
 380 *mipsI,mipsII,mipsIII,mipsIV:
 381 *vr5000:
 382 // start-sanitize-vr4320
 383 *vr4320:
 384 // end-sanitize-vr4320
 385 // start-sanitize-vr5400
 386 *vr5400:
 387 // end-sanitize-vr5400
 388 // start-sanitize-r5900
 389 *r5900:
 390 // end-sanitize-r5900
 391 *r3900:
 392 // start-sanitize-tx19
 393 *tx19:
 394 // end-sanitize-tx19
 395 {
 396   address_word offset = EXTEND16 (OFFSET) << 2;
 397   if ((signed_word) GPR[RS] > 0)
 398     DELAY_SLOT (NIA + offset);
 399 }
 400
 401
 402 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 403 "bgtzl r<RS>, <OFFSET>"
 404 *mipsII:
 405 *mipsIII:
 406 *mipsIV:
 407 *vr5000:
 408 // start-sanitize-vr4320
 409 *vr4320:
 410 // end-sanitize-vr4320
 411 // start-sanitize-vr5400
 412 *vr5400:
 413 // end-sanitize-vr5400
 414 // start-sanitize-r5900
 415 *r5900:
 416 // end-sanitize-r5900
 417 *r3900:
 418 // start-sanitize-tx19
 419 *tx19:
 420 // end-sanitize-tx19
 421 {
 422   address_word offset = EXTEND16 (OFFSET) << 2;
 423   /* NOTE: The branch occurs AFTER the next instruction has been
 424      executed */
 425   if ((signed_word) GPR[RS] > 0)
 426     DELAY_SLOT (NIA + offset);
 427   else
 428     NULLIFY_NEXT_INSTRUCTION ();
 429 }
 430
 431
 432 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 433 "blez r<RS>, <OFFSET>"
 434 *mipsI,mipsII,mipsIII,mipsIV:
 435 *vr5000:
 436 // start-sanitize-vr4320
 437 *vr4320:
 438 // end-sanitize-vr4320
 439 // start-sanitize-vr5400
 440 *vr5400:
 441 // end-sanitize-vr5400
 442 // start-sanitize-r5900
 443 *r5900:
 444 // end-sanitize-r5900
 445 *r3900:
 446 // start-sanitize-tx19
 447 *tx19:
 448 // end-sanitize-tx19
 449 {
 450   address_word offset = EXTEND16 (OFFSET) << 2;
 451   /* NOTE: The branch occurs AFTER the next instruction has been
 452      executed */
 453   if ((signed_word) GPR[RS] <= 0)
 454     DELAY_SLOT (NIA + offset);
 455 }
 456
 457
 458 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 459 "bgezl r<RS>, <OFFSET>"
 460 *mipsII:
 461 *mipsIII:
 462 *mipsIV:
 463 *vr5000:
 464 // start-sanitize-vr4320
 465 *vr4320:
 466 // end-sanitize-vr4320
 467 // start-sanitize-vr5400
 468 *vr5400:
 469 // end-sanitize-vr5400
 470 // start-sanitize-r5900
 471 *r5900:
 472 // end-sanitize-r5900
 473 *r3900:
 474 // start-sanitize-tx19
 475 *tx19:
 476 // end-sanitize-tx19
 477 {
 478   address_word offset = EXTEND16 (OFFSET) << 2;
 479   if ((signed_word) GPR[RS] <= 0)
 480     DELAY_SLOT (NIA + offset);
 481   else
 482     NULLIFY_NEXT_INSTRUCTION ();
 483 }
 484
 485
 486 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 487 "bltz r<RS>, <OFFSET>"
 488 *mipsI,mipsII,mipsIII,mipsIV:
 489 *vr5000:
 490 // start-sanitize-vr4320
 491 *vr4320:
 492 // end-sanitize-vr4320
 493 // start-sanitize-vr5400
 494 *vr5400:
 495 // end-sanitize-vr5400
 496 // start-sanitize-r5900
 497 *r5900:
 498 // end-sanitize-r5900
 499 *r3900:
 500 // start-sanitize-tx19
 501 *tx19:
 502 // end-sanitize-tx19
 503 {
 504   address_word offset = EXTEND16 (OFFSET) << 2;
 505   if ((signed_word) GPR[RS] < 0)
 506     DELAY_SLOT (NIA + offset);
 507 }
 508
 509
 510 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 511 "bltzal r<RS>, <OFFSET>"
 512 *mipsI,mipsII,mipsIII,mipsIV:
 513 *vr5000:
 514 // start-sanitize-vr4320
 515 *vr4320:
 516 // end-sanitize-vr4320
 517 // start-sanitize-vr5400
 518 *vr5400:
 519 // end-sanitize-vr5400
 520 // start-sanitize-r5900
 521 *r5900:
 522 // end-sanitize-r5900
 523 *r3900:
 524 // start-sanitize-tx19
 525 *tx19:
 526 // end-sanitize-tx19
 527 {
 528   address_word offset = EXTEND16 (OFFSET) << 2;
 529   RA = (CIA + 8);
 530   /* NOTE: The branch occurs AFTER the next instruction has been
 531      executed */
 532   if ((signed_word) GPR[RS] < 0)
 533     DELAY_SLOT (NIA + offset);
 534 }
 535
 536
 537 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 538 "bltzall r<RS>, <OFFSET>"
 539 *mipsII:
 540 *mipsIII:
 541 *mipsIV:
 542 *vr5000:
 543 // start-sanitize-vr4320
 544 *vr4320:
 545 // end-sanitize-vr4320
 546 // start-sanitize-vr5400
 547 *vr5400:
 548 // end-sanitize-vr5400
 549 // start-sanitize-r5900
 550 *r5900:
 551 // end-sanitize-r5900
 552 *r3900:
 553 // start-sanitize-tx19
 554 *tx19:
 555 // end-sanitize-tx19
 556 {
 557   address_word offset = EXTEND16 (OFFSET) << 2;
 558   RA = (CIA + 8);
 559   if ((signed_word) GPR[RS] < 0)
 560     DELAY_SLOT (NIA + offset);
 561   else
 562     NULLIFY_NEXT_INSTRUCTION ();
 563 }
 564
 565
 566 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 567 "bltzl r<RS>, <OFFSET>"
 568 *mipsII:
 569 *mipsIII:
 570 *mipsIV:
 571 *vr5000:
 572 // start-sanitize-vr4320
 573 *vr4320:
 574 // end-sanitize-vr4320
 575 // start-sanitize-vr5400
 576 *vr5400:
 577 // end-sanitize-vr5400
 578 // start-sanitize-r5900
 579 *r5900:
 580 // end-sanitize-r5900
 581 *r3900:
 582 // start-sanitize-tx19
 583 *tx19:
 584 // end-sanitize-tx19
 585 {
 586   address_word offset = EXTEND16 (OFFSET) << 2;
 587   /* NOTE: The branch occurs AFTER the next instruction has been
 588      executed */
 589   if ((signed_word) GPR[RS] < 0)
 590     DELAY_SLOT (NIA + offset);
 591   else
 592     NULLIFY_NEXT_INSTRUCTION ();
 593 }
 594
 595
 596 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 597 "bne r<RS>, r<RT>, <OFFSET>"
 598 *mipsI,mipsII,mipsIII,mipsIV:
 599 *vr5000:
 600 // start-sanitize-vr4320
 601 *vr4320:
 602 // end-sanitize-vr4320
 603 // start-sanitize-vr5400
 604 *vr5400:
 605 // end-sanitize-vr5400
 606 // start-sanitize-r5900
 607 *r5900:
 608 // end-sanitize-r5900
 609 *r3900:
 610 // start-sanitize-tx19
 611 *tx19:
 612 // end-sanitize-tx19
 613 {
 614   address_word offset = EXTEND16 (OFFSET) << 2;
 615   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 616     DELAY_SLOT (NIA + offset);
 617 }
 618
 619
 620 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 621 "bnel r<RS>, r<RT>, <OFFSET>"
 622 *mipsII:
 623 *mipsIII:
 624 *mipsIV:
 625 *vr5000:
 626 // start-sanitize-vr4320
 627 *vr4320:
 628 // end-sanitize-vr4320
 629 // start-sanitize-vr5400
 630 *vr5400:
 631 // end-sanitize-vr5400
 632 // start-sanitize-r5900
 633 *r5900:
 634 // end-sanitize-r5900
 635 *r3900:
 636 // start-sanitize-tx19
 637 *tx19:
 638 // end-sanitize-tx19
 639 {
 640   address_word offset = EXTEND16 (OFFSET) << 2;
 641   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 642     DELAY_SLOT (NIA + offset);
 643   else
 644     NULLIFY_NEXT_INSTRUCTION ();
 645 }
 646
 647
 648 000000,20.CODE,001101:SPECIAL:32::BREAK
 649 "break"
 650 *mipsI,mipsII,mipsIII,mipsIV:
 651 *vr5000:
 652 // start-sanitize-vr4320
 653 *vr4320:
 654 // end-sanitize-vr4320
 655 // start-sanitize-vr5400
 656 *vr5400:
 657 // end-sanitize-vr5400
 658 // start-sanitize-r5900
 659 *r5900:
 660 // end-sanitize-r5900
 661 *r3900:
 662 // start-sanitize-tx19
 663 *tx19:
 664 // end-sanitize-tx19
 665 {
 666   SignalException(BreakPoint, instruction_0);
 667 }
 668
 669
 670 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 671 "cop<ZZ> <COP_FUN>"
 672 *mipsI,mipsII,mipsIII,mipsIV:
 673 // start-sanitize-r5900
 674 *r5900:
 675 // end-sanitize-r5900
 676 *r3900:
 677 // start-sanitize-tx19
 678 *tx19:
 679 // end-sanitize-tx19
 680 {
 681   DecodeCoproc (instruction_0);
 682 }
 683
 684
 685 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 686 "dadd r<RD>, r<RS>, r<RT>"
 687 *mipsIII:
 688 *mipsIV:
 689 *vr5000:
 690 // start-sanitize-vr4320
 691 *vr4320:
 692 // end-sanitize-vr4320
 693 // start-sanitize-vr5400
 694 *vr5400:
 695 // end-sanitize-vr5400
 696 // start-sanitize-r5900
 697 *r5900:
 698 // end-sanitize-r5900
 699 *r3900:
 700 // start-sanitize-tx19
 701 *tx19:
 702 // end-sanitize-tx19
 703 {
 704   /* this check's for overflow */
 705   ALU64_BEGIN (GPR[RS]);
 706   ALU64_ADD (GPR[RT]);
 707   ALU64_END (GPR[RD]);
 708 }
 709
 710
 711 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 712 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 713 *mipsIII:
 714 *mipsIV:
 715 *vr5000:
 716 // start-sanitize-vr4320
 717 *vr4320:
 718 // end-sanitize-vr4320
 719 // start-sanitize-vr5400
 720 *vr5400:
 721 // end-sanitize-vr5400
 722 // start-sanitize-r5900
 723 *r5900:
 724 // end-sanitize-r5900
 725 *r3900:
 726 // start-sanitize-tx19
 727 *tx19:
 728 // end-sanitize-tx19
 729 {
 730   ALU64_BEGIN (GPR[RS]);
 731   ALU64_ADD (EXTEND16 (IMMEDIATE));
 732   ALU64_END (GPR[RT]);
 733 }
 734
 735
 736 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 737 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 738 *mipsIII:
 739 *mipsIV:
 740 *vr5000:
 741 // start-sanitize-vr4320
 742 *vr4320:
 743 // end-sanitize-vr4320
 744 // start-sanitize-vr5400
 745 *vr5400:
 746 // end-sanitize-vr5400
 747 // start-sanitize-r5900
 748 *r5900:
 749 // end-sanitize-r5900
 750 *r3900:
 751 // start-sanitize-tx19
 752 *tx19:
 753 // end-sanitize-tx19
 754 {
 755   GPR[RT] = GPR[RS] + EXTEND16 (IMMEDIATE);
 756 }
 757
 758
 759 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 760 "daddu r<RD>, r<RS>, r<RT>"
 761 *mipsIII:
 762 *mipsIV:
 763 *vr5000:
 764 // start-sanitize-vr4320
 765 *vr4320:
 766 // end-sanitize-vr4320
 767 // start-sanitize-vr5400
 768 *vr5400:
 769 // end-sanitize-vr5400
 770 // start-sanitize-r5900
 771 *r5900:
 772 // end-sanitize-r5900
 773 *r3900:
 774 // start-sanitize-tx19
 775 *tx19:
 776 // end-sanitize-tx19
 777 {
 778   GPR[RD] = GPR[RS] + GPR[RT];
 779 }
 780
 781
 782 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 783 "ddiv r<RS>, r<RT>"
 784 *mipsIII:
 785 *mipsIV:
 786 *vr5000:
 787 // start-sanitize-vr4320
 788 *vr4320:
 789 // end-sanitize-vr4320
 790 // start-sanitize-vr5400
 791 *vr5400:
 792 // end-sanitize-vr5400
 793 // start-sanitize-r5900
 794 *r5900:
 795 // end-sanitize-r5900
 796 *r3900:
 797 // start-sanitize-tx19
 798 *tx19:
 799 // end-sanitize-tx19
 800 {
 801   CHECKHILO ("Division");
 802   {
 803     signed64 n = GPR[RS];
 804     signed64 d = GPR[RT];
 805     if (d == 0)
 806       {
 807         LO = SIGNED64 (0x8000000000000000);
 808         HI = 0;
 809       }
 810     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 811       {
 812         LO = SIGNED64 (0x8000000000000000);
 813         HI = 0;
 814       }
 815     else
 816       {
 817         LO = (n / d);
 818         HI = (n % d);
 819       }
 820   }
 821 }
 822
 823
 824
 825 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 826 "ddivu r<RS>, r<RT>"
 827 *mipsIII:
 828 *mipsIV:
 829 *r3900:
 830 *vr5000:
 831 // start-sanitize-vr4320
 832 *vr4320:
 833 // end-sanitize-vr4320
 834 // start-sanitize-vr5400
 835 *vr5400:
 836 // end-sanitize-vr5400
 837 // start-sanitize-tx19
 838 *tx19:
 839 // end-sanitize-tx19
 840 {
 841   CHECKHILO ("Division");
 842   {
 843     unsigned64 n = GPR[RS];
 844     unsigned64 d = GPR[RT];
 845     if (d == 0)
 846       {
 847         LO = SIGNED64 (0x8000000000000000);
 848         HI = 0;
 849       }
 850     else
 851       {
 852         LO = (n / d);
 853         HI = (n % d);
 854       }
 855   }
 856 }
 857
 858
 859 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 860 "div r<RS>, r<RT>"
 861 *mipsI,mipsII,mipsIII,mipsIV:
 862 *vr5000:
 863 // start-sanitize-vr4320
 864 *vr4320:
 865 // end-sanitize-vr4320
 866 // start-sanitize-vr5400
 867 *vr5400:
 868 // end-sanitize-vr5400
 869 // start-sanitize-r5900
 870 *r5900:
 871 // end-sanitize-r5900
 872 *r3900:
 873 // start-sanitize-tx19
 874 *tx19:
 875 // end-sanitize-tx19
 876 {
 877   CHECKHILO("Division");
 878   {
 879     signed32 n = GPR[RS];
 880     signed32 d = GPR[RT];
 881     if (d == 0)
 882       {
 883         LO = EXTEND32 (0x80000000);
 884         HI = EXTEND32 (0);
 885       }
 886     else if (n == SIGNED32 (0x80000000) && d == -1)
 887       {
 888         LO = EXTEND32 (0x80000000);
 889         HI = EXTEND32 (0);
 890       }
 891     else
 892       {
 893         LO = EXTEND32 (n / d);
 894         HI = EXTEND32 (n % d);
 895       }
 896   }
 897 }
 898
 899
 900 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 901 "divu r<RS>, r<RT>"
 902 *mipsI,mipsII,mipsIII,mipsIV:
 903 *vr5000:
 904 // start-sanitize-vr4320
 905 *vr4320:
 906 // end-sanitize-vr4320
 907 // start-sanitize-vr5400
 908 *vr5400:
 909 // end-sanitize-vr5400
 910 // start-sanitize-r5900
 911 *r5900:
 912 // end-sanitize-r5900
 913 *r3900:
 914 // start-sanitize-tx19
 915 *tx19:
 916 // end-sanitize-tx19
 917 {
 918   CHECKHILO ("Division");
 919   {
 920     unsigned32 n = GPR[RS];
 921     unsigned32 d = GPR[RT];
 922     if (d == 0)
 923       {
 924         LO = EXTEND32 (0x80000000);
 925         HI = EXTEND32 (0);
 926       }
 927    else
 928      {
 929        LO = EXTEND32 (n / d);
 930        HI = EXTEND32 (n % d);
 931      }
 932   }
 933 }
 934
 935
 936 :function:::void:do_dmult:int rs, int rt, int rd, int signed_p
 937 {
 938   unsigned64 lo;
 939   unsigned64 hi;
 940   unsigned64 m00;
 941   unsigned64 m01;
 942   unsigned64 m10;
 943   unsigned64 m11;
 944   unsigned64 mid;
 945   int sign;
 946   unsigned64 op1 = GPR[rs];
 947   unsigned64 op2 = GPR[rt];
 948   CHECKHILO ("Multiplication");
 949   /* make signed multiply unsigned */
 950   sign = 0;
 951   if (signed_p)
 952     {
 953       if (op1 < 0)
 954         {
 955           op1 = - op1;
 956           ++sign;
 957         }
 958       if (op2 < 0)
 959         {
 960           op2 = - op2;
 961           ++sign;
 962         }
 963     }
 964   /* multuply out the 4 sub products */
 965   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
 966   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
 967   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
 968   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
 969   /* add the products */
 970   mid = ((unsigned64) VH4_8 (m00)
 971          + (unsigned64) VL4_8 (m10)
 972          + (unsigned64) VL4_8 (m01));
 973   lo = U8_4 (mid, m00);
 974   hi = (m11
 975         + (unsigned64) VH4_8 (mid)
 976         + (unsigned64) VH4_8 (m01)
 977         + (unsigned64) VH4_8 (m10));
 978   /* fix the sign */
 979   if (sign & 1)
 980     {
 981       lo = -lo;
 982       if (lo == 0)
 983         hi = -hi;
 984       else
 985         hi = -hi - 1;
 986     }
 987   /* save the result HI/LO (and a gpr) */
 988   LO = lo;
 989   HI = hi;
 990   if (rd != 0)
 991     GPR[rd] = lo;
 992 }
 993
 994
 995 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 996 "dmult r<RS>, r<RT>"
 997 *mipsIII,mipsIV:
 998 *r3900:
 999 // start-sanitize-tx19
1000 *tx19:
1001 // end-sanitize-tx19
1002 // start-sanitize-vr4320
1003 *vr4320:
1004 // end-sanitize-vr4320
1005 {
1006   do_dmult (SD_, RS, RT, 0, 1);
1007 }
1008
1009 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1010 "dmult r<RS>, r<RT>":RD == 0
1011 "dmult r<RD>, r<RS>, r<RT>"
1012 *vr5000:
1013 // start-sanitize-vr5400
1014 *vr5400:
1015 // end-sanitize-vr5400
1016 {
1017   do_dmult (SD_, RS, RT, RD, 1);
1018 }
1019
1020
1021
1022 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1023 "dmultu r<RS>, r<RT>"
1024 *mipsIII,mipsIV:
1025 *r3900:
1026 // start-sanitize-tx19
1027 *tx19:
1028 // end-sanitize-tx19
1029 // start-sanitize-vr4320
1030 *vr4320:
1031 // end-sanitize-vr4320
1032 {
1033   do_dmult (SD_, RS, RT, 0, 0);
1034 }
1035
1036 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1037 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1038 "dmultu r<RS>, r<RT>"
1039 *vr5000:
1040 // start-sanitize-vr5400
1041 *vr5400:
1042 // end-sanitize-vr5400
1043 {
1044   do_dmult (SD_, RS, RT, RD, 0);
1045 }
1046
1047
1048
1049 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1050 "dsll r<RD>, r<RT>, <SHIFT>"
1051 *mipsIII:
1052 *mipsIV:
1053 *vr5000:
1054 // start-sanitize-vr4320
1055 *vr4320:
1056 // end-sanitize-vr4320
1057 // start-sanitize-vr5400
1058 *vr5400:
1059 // end-sanitize-vr5400
1060 // start-sanitize-r5900
1061 *r5900:
1062 // end-sanitize-r5900
1063 *r3900:
1064 // start-sanitize-tx19
1065 *tx19:
1066 // end-sanitize-tx19
1067 {
1068   int s = SHIFT;
1069   GPR[RD] = GPR[RT] << s;
1070 }
1071
1072
1073 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1074 "dsll32 r<RD>, r<RT>, <SHIFT>"
1075 *mipsIII:
1076 *mipsIV:
1077 *vr5000:
1078 // start-sanitize-vr4320
1079 *vr4320:
1080 // end-sanitize-vr4320
1081 // start-sanitize-vr5400
1082 *vr5400:
1083 // end-sanitize-vr5400
1084 // start-sanitize-r5900
1085 *r5900:
1086 // end-sanitize-r5900
1087 *r3900:
1088 // start-sanitize-tx19
1089 *tx19:
1090 // end-sanitize-tx19
1091 {
1092   int s = 32 + SHIFT;
1093   GPR[RD] = GPR[RT] << s;
1094 }
1095
1096
1097 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1098 "dsllv r<RD>, r<RT>, r<RS>"
1099 *mipsIII:
1100 *mipsIV:
1101 *vr5000:
1102 // start-sanitize-vr4320
1103 *vr4320:
1104 // end-sanitize-vr4320
1105 // start-sanitize-vr5400
1106 *vr5400:
1107 // end-sanitize-vr5400
1108 // start-sanitize-r5900
1109 *r5900:
1110 // end-sanitize-r5900
1111 *r3900:
1112 // start-sanitize-tx19
1113 *tx19:
1114 // end-sanitize-tx19
1115 {
1116   int s = MASKED64 (GPR[RS], 5, 0);
1117   GPR[RD] = GPR[RT] << s;
1118 }
1119
1120
1121 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1122 "dsra r<RD>, r<RT>, <SHIFT>"
1123 *mipsIII:
1124 *mipsIV:
1125 *vr5000:
1126 // start-sanitize-vr4320
1127 *vr4320:
1128 // end-sanitize-vr4320
1129 // start-sanitize-vr5400
1130 *vr5400:
1131 // end-sanitize-vr5400
1132 // start-sanitize-r5900
1133 *r5900:
1134 // end-sanitize-r5900
1135 *r3900:
1136 // start-sanitize-tx19
1137 *tx19:
1138 // end-sanitize-tx19
1139 {
1140   int s = SHIFT;
1141   GPR[RD] = ((signed64) GPR[RT]) >> s;
1142 }
1143
1144
1145 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1146 "dsra32 r<RT>, r<RD>, <SHIFT>"
1147 *mipsIII:
1148 *mipsIV:
1149 *vr5000:
1150 // start-sanitize-vr4320
1151 *vr4320:
1152 // end-sanitize-vr4320
1153 // start-sanitize-vr5400
1154 *vr5400:
1155 // end-sanitize-vr5400
1156 // start-sanitize-r5900
1157 *r5900:
1158 // end-sanitize-r5900
1159 *r3900:
1160 // start-sanitize-tx19
1161 *tx19:
1162 // end-sanitize-tx19
1163 {
1164   int s = 32 + SHIFT;
1165   GPR[RD] = ((signed64) GPR[RT]) >> s;
1166 }
1167
1168
1169 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1170 "dsra32 r<RT>, r<RD>, r<RS>"
1171 *mipsIII:
1172 *mipsIV:
1173 *vr5000:
1174 // start-sanitize-vr4320
1175 *vr4320:
1176 // end-sanitize-vr4320
1177 // start-sanitize-vr5400
1178 *vr5400:
1179 // end-sanitize-vr5400
1180 // start-sanitize-r5900
1181 *r5900:
1182 // end-sanitize-r5900
1183 *r3900:
1184 // start-sanitize-tx19
1185 *tx19:
1186 // end-sanitize-tx19
1187 {
1188   int s = MASKED64 (GPR[RS], 5, 0);
1189   GPR[RD] = ((signed64) GPR[RT]) >> s;
1190 }
1191
1192
1193 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1194 "dsrav r<RD>, r<RT>, <SHIFT>"
1195 *mipsIII:
1196 *mipsIV:
1197 *vr5000:
1198 // start-sanitize-vr4320
1199 *vr4320:
1200 // end-sanitize-vr4320
1201 // start-sanitize-vr5400
1202 *vr5400:
1203 // end-sanitize-vr5400
1204 // start-sanitize-r5900
1205 *r5900:
1206 // end-sanitize-r5900
1207 *r3900:
1208 // start-sanitize-tx19
1209 *tx19:
1210 // end-sanitize-tx19
1211 {
1212   int s = SHIFT;
1213   GPR[RD] = (unsigned64) GPR[RT] >> s;
1214 }
1215
1216
1217 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1218 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1219 *mipsIII:
1220 *mipsIV:
1221 *vr5000:
1222 // start-sanitize-vr4320
1223 *vr4320:
1224 // end-sanitize-vr4320
1225 // start-sanitize-vr5400
1226 *vr5400:
1227 // end-sanitize-vr5400
1228 // start-sanitize-r5900
1229 *r5900:
1230 // end-sanitize-r5900
1231 *r3900:
1232 // start-sanitize-tx19
1233 *tx19:
1234 // end-sanitize-tx19
1235 {
1236   int s = 32 + SHIFT;
1237   GPR[RD] = (unsigned64) GPR[RT] >> s;
1238 }
1239
1240
1241 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1242 "dsrl32 r<RD>, r<RT>, r<RS>"
1243 *mipsIII:
1244 *mipsIV:
1245 *vr5000:
1246 // start-sanitize-vr4320
1247 *vr4320:
1248 // end-sanitize-vr4320
1249 // start-sanitize-vr5400
1250 *vr5400:
1251 // end-sanitize-vr5400
1252 // start-sanitize-r5900
1253 *r5900:
1254 // end-sanitize-r5900
1255 *r3900:
1256 // start-sanitize-tx19
1257 *tx19:
1258 // end-sanitize-tx19
1259 {
1260   int s = MASKED64 (GPR[RS], 5, 0);
1261   GPR[RD] = (unsigned64) GPR[RT] >> s;
1262 }
1263
1264
1265 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1266 "dsub r<RD>, r<RS>, r<RT>"
1267 *mipsIII:
1268 *mipsIV:
1269 *vr5000:
1270 // start-sanitize-vr4320
1271 *vr4320:
1272 // end-sanitize-vr4320
1273 // start-sanitize-vr5400
1274 *vr5400:
1275 // end-sanitize-vr5400
1276 // start-sanitize-r5900
1277 *r5900:
1278 // end-sanitize-r5900
1279 *r3900:
1280 // start-sanitize-tx19
1281 *tx19:
1282 // end-sanitize-tx19
1283 {
1284   ALU64_BEGIN (GPR[RS]);
1285   ALU64_SUB (GPR[RT]);
1286   ALU64_END (GPR[RD]);
1287 }
1288
1289
1290 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1291 "dsubu r<RD>, r<RS>, r<RT>"
1292 *mipsIII:
1293 *mipsIV:
1294 *vr5000:
1295 // start-sanitize-vr4320
1296 *vr4320:
1297 // end-sanitize-vr4320
1298 // start-sanitize-vr5400
1299 *vr5400:
1300 // end-sanitize-vr5400
1301 // start-sanitize-r5900
1302 *r5900:
1303 // end-sanitize-r5900
1304 *r3900:
1305 // start-sanitize-tx19
1306 *tx19:
1307 // end-sanitize-tx19
1308 {
1309   GPR[RD] = GPR[RS] - GPR[RT];
1310 }
1311
1312
1313 000010,26.INSTR_INDEX:NORMAL:32::J
1314 "j <INSTR_INDEX>"
1315 *mipsI,mipsII,mipsIII,mipsIV:
1316 *vr5000:
1317 // start-sanitize-vr4320
1318 *vr4320:
1319 // end-sanitize-vr4320
1320 // start-sanitize-vr5400
1321 *vr5400:
1322 // end-sanitize-vr5400
1323 // start-sanitize-r5900
1324 *r5900:
1325 // end-sanitize-r5900
1326 *r3900:
1327 // start-sanitize-tx19
1328 *tx19:
1329 // end-sanitize-tx19
1330 {
1331   /* NOTE: The region used is that of the delay slot NIA and NOT the
1332      current instruction */
1333   address_word region = (NIA & MASK (63, 28));
1334   DELAY_SLOT (region | (INSTR_INDEX << 2));
1335 }
1336
1337
1338 000011,26.INSTR_INDEX:NORMAL:32::JAL
1339 "jal <INSTR_INDEX>"
1340 *mipsI,mipsII,mipsIII,mipsIV:
1341 *vr5000:
1342 // start-sanitize-vr4320
1343 *vr4320:
1344 // end-sanitize-vr4320
1345 // start-sanitize-vr5400
1346 *vr5400:
1347 // end-sanitize-vr5400
1348 // start-sanitize-r5900
1349 *r5900:
1350 // end-sanitize-r5900
1351 *r3900:
1352 // start-sanitize-tx19
1353 *tx19:
1354 // end-sanitize-tx19
1355 {
1356   /* NOTE: The region used is that of the delay slot and NOT the
1357      current instruction */
1358   address_word region = (NIA & MASK (63, 28));
1359   GPR[31] = CIA + 8;
1360   DELAY_SLOT (region | (INSTR_INDEX << 2));
1361 }
1362
1363
1364 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1365 "jalr r<RS>":RD == 31
1366 "jalr r<RD>, r<RS>"
1367 *mipsI,mipsII,mipsIII,mipsIV:
1368 *vr5000:
1369 // start-sanitize-vr4320
1370 *vr4320:
1371 // end-sanitize-vr4320
1372 // start-sanitize-vr5400
1373 *vr5400:
1374 // end-sanitize-vr5400
1375 // start-sanitize-r5900
1376 *r5900:
1377 // end-sanitize-r5900
1378 *r3900:
1379 // start-sanitize-tx19
1380 *tx19:
1381 // end-sanitize-tx19
1382 {
1383   address_word temp = GPR[RS];
1384   GPR[RD] = CIA + 8;
1385   DELAY_SLOT (temp);
1386 }
1387
1388
1389 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1390 "jr r<RS>"
1391 *mipsI,mipsII,mipsIII,mipsIV:
1392 *vr5000:
1393 // start-sanitize-vr4320
1394 *vr4320:
1395 // end-sanitize-vr4320
1396 // start-sanitize-vr5400
1397 *vr5400:
1398 // end-sanitize-vr5400
1399 // start-sanitize-r5900
1400 *r5900:
1401 // end-sanitize-r5900
1402 *r3900:
1403 // start-sanitize-tx19
1404 *tx19:
1405 // end-sanitize-tx19
1406 {
1407   DELAY_SLOT (GPR[RS]);
1408 }
1409
1410
1411 :function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset
1412 {
1413   address_word vaddr = offset + gpr_base;
1414   address_word paddr;
1415   int uncached;
1416   if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1417     {
1418       unsigned64 memval = 0;
1419       address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1420       unsigned int reverse = (ReverseEndian ? mask : 0);
1421       unsigned int bigend = (BigEndianCPU ? mask : 0);
1422       unsigned int byte;
1423       paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1424       LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL);
1425       byte = ((vaddr & mask) ^ bigend);
1426       GPR[rt] = EXTEND8 ((memval >> (8 * byte)));
1427     }
1428 }
1429
1430 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1431 "lb r<RT>, <OFFSET>(r<BASE>)"
1432 *mipsI,mipsII,mipsIII,mipsIV:
1433 *vr5000:
1434 // start-sanitize-vr4320
1435 *vr4320:
1436 // end-sanitize-vr4320
1437 // start-sanitize-vr5400
1438 *vr5400:
1439 // end-sanitize-vr5400
1440 // start-sanitize-r5900
1441 *r5900:
1442 // end-sanitize-r5900
1443 *r3900:
1444 // start-sanitize-tx19
1445 *tx19:
1446 // end-sanitize-tx19
1447 {
1448   do_load_byte (SD_, GPR[BASE], RT, OFFSET);
1449 #if 0
1450   unsigned32 instruction = instruction_0;
1451   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1452   int destreg = ((instruction >> 16) & 0x0000001F);
1453   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1454   {
1455     address_word vaddr = ((uword64)op1 + offset);
1456     address_word paddr;
1457     int uncached;
1458     {
1459       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1460         {
1461           uword64 memval = 0;
1462           uword64 memval1 = 0;
1463           uword64 mask = 0x7;
1464           unsigned int shift = 0;
1465           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1466           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1467           unsigned int byte;
1468           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1469           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1470           byte = ((vaddr & mask) ^ (bigend << shift));
1471           GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x000000FF),8));
1472         }
1473     }
1474   }
1475 #endif
1476 }
1477
1478
1479 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1480 "lbu r<RT>, <OFFSET>(r<BASE>)"
1481 *mipsI,mipsII,mipsIII,mipsIV:
1482 *vr5000:
1483 // start-sanitize-vr4320
1484 *vr4320:
1485 // end-sanitize-vr4320
1486 // start-sanitize-vr5400
1487 *vr5400:
1488 // end-sanitize-vr5400
1489 // start-sanitize-r5900
1490 *r5900:
1491 // end-sanitize-r5900
1492 *r3900:
1493 // start-sanitize-tx19
1494 *tx19:
1495 // end-sanitize-tx19
1496 {
1497   unsigned32 instruction = instruction_0;
1498   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1499   int destreg = ((instruction >> 16) & 0x0000001F);
1500   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1501   {
1502     address_word vaddr = ((unsigned64)op1 + offset);
1503     address_word paddr;
1504     int uncached;
1505     {
1506       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1507         {
1508           unsigned64 memval = 0;
1509           unsigned64 memval1 = 0;
1510           unsigned64 mask = 0x7;
1511           unsigned int shift = 0;
1512           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1513           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1514           unsigned int byte;
1515           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1516           LoadMemory(&memval,&memval1,uncached,AccessLength_BYTE,paddr,vaddr,isDATA,isREAL);
1517           byte = ((vaddr & mask) ^ (bigend << shift));
1518           GPR[destreg] = (((memval >> (8 * byte)) & 0x000000FF));
1519         }
1520     }
1521   }
1522 }
1523
1524
1525 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1526 "ld r<RT>, <OFFSET>(r<BASE>)"
1527 *mipsIII:
1528 *mipsIV:
1529 *vr5000:
1530 // start-sanitize-vr4320
1531 *vr4320:
1532 // end-sanitize-vr4320
1533 // start-sanitize-vr5400
1534 *vr5400:
1535 // end-sanitize-vr5400
1536 // start-sanitize-r5900
1537 *r5900:
1538 // end-sanitize-r5900
1539 *r3900:
1540 // start-sanitize-tx19
1541 *tx19:
1542 // end-sanitize-tx19
1543 {
1544   unsigned32 instruction = instruction_0;
1545   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1546   int destreg = ((instruction >> 16) & 0x0000001F);
1547   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1548   {
1549     address_word vaddr = ((unsigned64)op1 + offset);
1550     address_word paddr;
1551     int uncached;
1552     if ((vaddr & 7) != 0)
1553       SignalExceptionAddressLoad();
1554     else
1555       {
1556         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1557           {
1558             unsigned64 memval = 0;
1559             unsigned64 memval1 = 0;
1560             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1561             GPR[destreg] = memval;
1562           }
1563       }
1564   }
1565 }
1566
1567
1568 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1569 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1570 *mipsII:
1571 *mipsIII:
1572 *mipsIV:
1573 *vr5000:
1574 // start-sanitize-vr4320
1575 *vr4320:
1576 // end-sanitize-vr4320
1577 // start-sanitize-vr5400
1578 *vr5400:
1579 // end-sanitize-vr5400
1580 *r3900:
1581 // start-sanitize-tx19
1582 *tx19:
1583 // end-sanitize-tx19
1584 {
1585   unsigned32 instruction = instruction_0;
1586   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1587   int destreg = ((instruction >> 16) & 0x0000001F);
1588   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1589   {
1590     address_word vaddr = ((unsigned64)op1 + offset);
1591     address_word paddr;
1592     int uncached;
1593     if ((vaddr & 7) != 0)
1594       SignalExceptionAddressLoad();
1595     else
1596       {
1597         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1598           {
1599             unsigned64 memval = 0;
1600             unsigned64 memval1 = 0;
1601             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1602             COP_LD(((instruction >> 26) & 0x3),destreg,memval);;
1603           }
1604       }
1605   }
1606 }
1607
1608
1609 // start-sanitize-sky
1610 110110,5.BASE,5.RT,16.OFFSET:NORMAL:64::LQC2
1611 "lqc2 r<RT>, <OFFSET>(r<BASE>)"
1612 *r5900:
1613 {
1614 #ifdef TARGET_SKY
1615   unsigned32 instruction = instruction_0;
1616   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1617   int destreg = ((instruction >> 16) & 0x0000001F);
1618   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1619   {
1620     address_word vaddr = ((unsigned64)op1 + offset);
1621     address_word paddr;
1622     int uncached;
1623     if ((vaddr & 0x0f) != 0)
1624       SignalExceptionAddressLoad();
1625     else
1626       {
1627         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1628           {
1629             unsigned64 memval = 0;
1630             unsigned64 memval1 = 0;
1631             unsigned128 qw = U16_8(memval, memval1); /* XXX: check order */
1632             /* XXX: block on VU0 pipeline if necessary */
1633             LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
1634             COP_LQ(((instruction >> 26) & 0x3),destreg,qw);;
1635           }
1636       }
1637   }
1638 #endif /* TARGET_SKY */
1639 }
1640 // end-sanitize-sky
1641
1642
1643 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1644 "ldl r<RT>, <OFFSET>(r<BASE>)"
1645 *mipsIII:
1646 *mipsIV:
1647 *vr5000:
1648 // start-sanitize-vr4320
1649 *vr4320:
1650 // end-sanitize-vr4320
1651 // start-sanitize-vr5400
1652 *vr5400:
1653 // end-sanitize-vr5400
1654 // start-sanitize-r5900
1655 *r5900:
1656 // end-sanitize-r5900
1657 *r3900:
1658 // start-sanitize-tx19
1659 *tx19:
1660 // end-sanitize-tx19
1661 {
1662   unsigned32 instruction = instruction_0;
1663   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1664   int destreg = ((instruction >> 16) & 0x0000001F);
1665   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1666   {
1667     address_word vaddr = ((unsigned64)op1 + offset);
1668     address_word paddr;
1669     int uncached;
1670     {
1671       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1672         {
1673           unsigned64 memval = 0;
1674           unsigned64 memval1 = 0;
1675           unsigned64 mask = 7;
1676           unsigned int reverse = (ReverseEndian ? mask : 0);
1677           unsigned int bigend = (BigEndianCPU ? mask : 0);
1678           int byte;
1679           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1680           byte = ((vaddr & mask) ^ bigend);
1681           if (!BigEndianMem)
1682             paddr &= ~mask;
1683           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
1684           GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
1685         }
1686     }
1687   }
1688 }
1689
1690
1691 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1692 "ldr r<RT>, <OFFSET>(r<BASE>)"
1693 *mipsIII:
1694 *mipsIV:
1695 *vr5000:
1696 // start-sanitize-vr4320
1697 *vr4320:
1698 // end-sanitize-vr4320
1699 // start-sanitize-vr5400
1700 *vr5400:
1701 // end-sanitize-vr5400
1702 // start-sanitize-r5900
1703 *r5900:
1704 // end-sanitize-r5900
1705 *r3900:
1706 // start-sanitize-tx19
1707 *tx19:
1708 // end-sanitize-tx19
1709 {
1710   unsigned32 instruction = instruction_0;
1711   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1712   int destreg = ((instruction >> 16) & 0x0000001F);
1713   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1714   {
1715     address_word vaddr = ((unsigned64)op1 + offset);
1716     address_word paddr;
1717     int uncached;
1718     {
1719       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1720         {
1721           unsigned64 memval = 0;
1722           unsigned64 memval1 = 0;
1723           unsigned64 mask = 7;
1724           unsigned int reverse = (ReverseEndian ? mask : 0);
1725           unsigned int bigend = (BigEndianCPU ? mask : 0);
1726           int byte;
1727           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
1728           byte = ((vaddr & mask) ^ bigend);
1729           if (BigEndianMem)
1730             paddr &= ~mask;
1731           LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
1732           {
1733             unsigned64 srcmask;
1734             if (byte == 0)
1735               srcmask = 0;
1736             else
1737               srcmask = ((unsigned64)-1 << (8 * (8 - byte)));
1738             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
1739           }
1740         }
1741     }
1742   }
1743 }
1744
1745
1746 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1747 "lh r<RT>, <OFFSET>(r<BASE>)"
1748 *mipsI,mipsII,mipsIII,mipsIV:
1749 *vr5000:
1750 // start-sanitize-vr4320
1751 *vr4320:
1752 // end-sanitize-vr4320
1753 // start-sanitize-vr5400
1754 *vr5400:
1755 // end-sanitize-vr5400
1756 // start-sanitize-r5900
1757 *r5900:
1758 // end-sanitize-r5900
1759 *r3900:
1760 // start-sanitize-tx19
1761 *tx19:
1762 // end-sanitize-tx19
1763 {
1764   unsigned32 instruction = instruction_0;
1765   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1766   int destreg = ((instruction >> 16) & 0x0000001F);
1767   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1768   {
1769     address_word vaddr = ((unsigned64)op1 + offset);
1770     address_word paddr;
1771     int uncached;
1772     if ((vaddr & 1) != 0)
1773       SignalExceptionAddressLoad();
1774     else
1775       {
1776         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1777           {
1778             unsigned64 memval = 0;
1779             unsigned64 memval1 = 0;
1780             unsigned64 mask = 0x7;
1781             unsigned int shift = 1;
1782             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1783             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1784             unsigned int byte;
1785             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1786             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1787             byte = ((vaddr & mask) ^ (bigend << shift));
1788             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0x0000FFFF),16));
1789           }
1790       }
1791   }
1792 }
1793
1794
1795 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1796 "lhu r<RT>, <OFFSET>(r<BASE>)"
1797 *mipsI,mipsII,mipsIII,mipsIV:
1798 *vr5000:
1799 // start-sanitize-vr4320
1800 *vr4320:
1801 // end-sanitize-vr4320
1802 // start-sanitize-vr5400
1803 *vr5400:
1804 // end-sanitize-vr5400
1805 // start-sanitize-r5900
1806 *r5900:
1807 // end-sanitize-r5900
1808 *r3900:
1809 // start-sanitize-tx19
1810 *tx19:
1811 // end-sanitize-tx19
1812 {
1813   unsigned32 instruction = instruction_0;
1814   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1815   int destreg = ((instruction >> 16) & 0x0000001F);
1816   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1817   {
1818     address_word vaddr = ((unsigned64)op1 + offset);
1819     address_word paddr;
1820     int uncached;
1821     if ((vaddr & 1) != 0)
1822       SignalExceptionAddressLoad();
1823     else
1824       {
1825         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1826           {
1827             unsigned64 memval = 0;
1828             unsigned64 memval1 = 0;
1829             unsigned64 mask = 0x7;
1830             unsigned int shift = 1;
1831             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1832             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1833             unsigned int byte;
1834             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1835             LoadMemory(&memval,&memval1,uncached,AccessLength_HALFWORD,paddr,vaddr,isDATA,isREAL);
1836             byte = ((vaddr & mask) ^ (bigend << shift));
1837             GPR[destreg] = (((memval >> (8 * byte)) & 0x0000FFFF));
1838           }
1839       }
1840   }
1841 }
1842
1843
1844 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1845 "ll r<RT>, <OFFSET>(r<BASE>)"
1846 *mipsII:
1847 *mipsIII:
1848 *mipsIV:
1849 *vr5000:
1850 // start-sanitize-vr4320
1851 *vr4320:
1852 // end-sanitize-vr4320
1853 // start-sanitize-vr5400
1854 *vr5400:
1855 // end-sanitize-vr5400
1856 // start-sanitize-r5900
1857 *r5900:
1858 // end-sanitize-r5900
1859 *r3900:
1860 // start-sanitize-tx19
1861 *tx19:
1862 // end-sanitize-tx19
1863 {
1864   unsigned32 instruction = instruction_0;
1865   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1866   int destreg = ((instruction >> 16) & 0x0000001F);
1867   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1868   {
1869     address_word vaddr = ((unsigned64)op1 + offset);
1870     address_word paddr;
1871     int uncached;
1872     if ((vaddr & 3) != 0)
1873       SignalExceptionAddressLoad();
1874     else
1875       {
1876         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1877           {
1878             unsigned64 memval = 0;
1879             unsigned64 memval1 = 0;
1880             unsigned64 mask = 0x7;
1881             unsigned int shift = 2;
1882             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1883             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1884             unsigned int byte;
1885             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1886             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1887             byte = ((vaddr & mask) ^ (bigend << shift));
1888             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1889             LLBIT = 1;
1890           }
1891       }
1892   }
1893 }
1894
1895
1896 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1897 "lld r<RT>, <OFFSET>(r<BASE>)"
1898 *mipsIII:
1899 *mipsIV:
1900 *vr5000:
1901 // start-sanitize-vr4320
1902 *vr4320:
1903 // end-sanitize-vr4320
1904 // start-sanitize-vr5400
1905 *vr5400:
1906 // end-sanitize-vr5400
1907 // start-sanitize-r5900
1908 *r5900:
1909 // end-sanitize-r5900
1910 *r3900:
1911 // start-sanitize-tx19
1912 *tx19:
1913 // end-sanitize-tx19
1914 {
1915   unsigned32 instruction = instruction_0;
1916   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1917   int destreg = ((instruction >> 16) & 0x0000001F);
1918   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1919   {
1920     address_word vaddr = ((unsigned64)op1 + offset);
1921     address_word paddr;
1922     int uncached;
1923     if ((vaddr & 7) != 0)
1924       SignalExceptionAddressLoad();
1925     else
1926       {
1927         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1928           {
1929             unsigned64 memval = 0;
1930             unsigned64 memval1 = 0;
1931             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1932             GPR[destreg] = memval;
1933             LLBIT = 1;
1934           }
1935       }
1936   }
1937 }
1938
1939
1940 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1941 "lui r<RT>, <IMMEDIATE>"
1942 *mipsI,mipsII,mipsIII,mipsIV:
1943 *vr5000:
1944 // start-sanitize-vr4320
1945 *vr4320:
1946 // end-sanitize-vr4320
1947 // start-sanitize-vr5400
1948 *vr5400:
1949 // end-sanitize-vr5400
1950 // start-sanitize-r5900
1951 *r5900:
1952 // end-sanitize-r5900
1953 *r3900:
1954 // start-sanitize-tx19
1955 *tx19:
1956 // end-sanitize-tx19
1957 {
1958   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1959 }
1960
1961
1962 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1963 "lw r<RT>, <OFFSET>(r<BASE>)"
1964 *mipsI,mipsII,mipsIII,mipsIV:
1965 *vr5000:
1966 // start-sanitize-vr4320
1967 *vr4320:
1968 // end-sanitize-vr4320
1969 // start-sanitize-vr5400
1970 *vr5400:
1971 // end-sanitize-vr5400
1972 // start-sanitize-r5900
1973 *r5900:
1974 // end-sanitize-r5900
1975 *r3900:
1976 // start-sanitize-tx19
1977 *tx19:
1978 // end-sanitize-tx19
1979 {
1980   unsigned32 instruction = instruction_0;
1981   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1982   int destreg = ((instruction >> 16) & 0x0000001F);
1983   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1984   {
1985     address_word vaddr = ((unsigned64)op1 + offset);
1986     address_word paddr;
1987     int uncached;
1988     if ((vaddr & 3) != 0)
1989       SignalExceptionAddressLoad();
1990     else
1991       {
1992         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1993           {
1994             unsigned64 memval = 0;
1995             unsigned64 memval1 = 0;
1996             unsigned64 mask = 0x7;
1997             unsigned int shift = 2;
1998             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1999             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2000             unsigned int byte;
2001             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2002             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2003             byte = ((vaddr & mask) ^ (bigend << shift));
2004             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2005           }
2006       }
2007   }
2008 }
2009
2010
2011 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2012 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2013 *mipsI,mipsII,mipsIII,mipsIV:
2014 *vr5000:
2015 // start-sanitize-vr4320
2016 *vr4320:
2017 // end-sanitize-vr4320
2018 // start-sanitize-vr5400
2019 *vr5400:
2020 // end-sanitize-vr5400
2021 // start-sanitize-r5900
2022 *r5900:
2023 // end-sanitize-r5900
2024 *r3900:
2025 // start-sanitize-tx19
2026 *tx19:
2027 // end-sanitize-tx19
2028 {
2029   unsigned32 instruction = instruction_0;
2030   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2031   int destreg = ((instruction >> 16) & 0x0000001F);
2032   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2033   {
2034     address_word vaddr = ((unsigned64)op1 + offset);
2035     address_word paddr;
2036     int uncached;
2037     if ((vaddr & 3) != 0)
2038       SignalExceptionAddressLoad();
2039     else
2040       {
2041         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2042           {
2043             unsigned64 memval = 0;
2044             unsigned64 memval1 = 0;
2045             unsigned64 mask = 0x7;
2046             unsigned int shift = 2;
2047             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2048             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2049             unsigned int byte;
2050             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2051             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2052             byte = ((vaddr & mask) ^ (bigend << shift));
2053             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
2054           }
2055       }
2056   }
2057 }
2058
2059
2060 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2061 "lwl r<RT>, <OFFSET>(r<BASE>)"
2062 *mipsI,mipsII,mipsIII,mipsIV:
2063 *vr5000:
2064 // start-sanitize-vr4320
2065 *vr4320:
2066 // end-sanitize-vr4320
2067 // start-sanitize-vr5400
2068 *vr5400:
2069 // end-sanitize-vr5400
2070 // start-sanitize-r5900
2071 *r5900:
2072 // end-sanitize-r5900
2073 *r3900:
2074 // start-sanitize-tx19
2075 *tx19:
2076 // end-sanitize-tx19
2077 {
2078   unsigned32 instruction = instruction_0;
2079   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2080   int destreg = ((instruction >> 16) & 0x0000001F);
2081   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2082   {
2083     address_word vaddr = ((unsigned64)op1 + offset);
2084     address_word paddr;
2085     int uncached;
2086     {
2087       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2088         {
2089           unsigned64 memval = 0;
2090           unsigned64 memval1 = 0;
2091           unsigned64 mask = 3;
2092           unsigned int reverse = (ReverseEndian ? mask : 0);
2093           unsigned int bigend = (BigEndianCPU ? mask : 0);
2094           int byte;
2095           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2096           byte = ((vaddr & mask) ^ bigend);
2097           if (!BigEndianMem)
2098             paddr &= ~mask;
2099           LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
2100           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2101             memval >>= 32;
2102           }
2103           GPR[destreg] = ((memval << ((3 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((3 - byte) * 8)) - 1)));
2104           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
2105         }
2106     }
2107   }
2108 }
2109
2110
2111 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2112 "lwr r<RT>, <OFFSET>(r<BASE>)"
2113 *mipsI,mipsII,mipsIII,mipsIV:
2114 *vr5000:
2115 // start-sanitize-vr4320
2116 *vr4320:
2117 // end-sanitize-vr4320
2118 // start-sanitize-vr5400
2119 *vr5400:
2120 // end-sanitize-vr5400
2121 // start-sanitize-r5900
2122 *r5900:
2123 // end-sanitize-r5900
2124 *r3900:
2125 // start-sanitize-tx19
2126 *tx19:
2127 // end-sanitize-tx19
2128 {
2129   unsigned32 instruction = instruction_0;
2130   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2131   int destreg = ((instruction >> 16) & 0x0000001F);
2132   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2133   {
2134     address_word vaddr = ((unsigned64)op1 + offset);
2135     address_word paddr;
2136     int uncached;
2137     {
2138       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2139         {
2140           unsigned64 memval = 0;
2141           unsigned64 memval1 = 0;
2142           unsigned64 mask = 3;
2143           unsigned int reverse = (ReverseEndian ? mask : 0);
2144           unsigned int bigend = (BigEndianCPU ? mask : 0);
2145           int byte;
2146           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2147           byte = ((vaddr & mask) ^ bigend);
2148           if (BigEndianMem)
2149             paddr &= ~mask;
2150           LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
2151           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
2152             memval >>= 32;
2153           }
2154           {
2155             unsigned64 srcmask;
2156             if (byte == 0)
2157               srcmask = 0;
2158             else
2159               srcmask = ((unsigned64)-1 << (8 * (4 - byte)));
2160             GPR[destreg] = ((GPR[destreg] & srcmask) | (memval >> (8 * byte)));
2161           }
2162           GPR[destreg] = SIGNEXTEND(GPR[destreg],32);
2163         }
2164     }
2165   }
2166 }
2167
2168
2169 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2170 "lwu r<RT>, <OFFSET>(r<BASE>)"
2171 *mipsIII:
2172 *mipsIV:
2173 *vr5000:
2174 // start-sanitize-vr4320
2175 *vr4320:
2176 // end-sanitize-vr4320
2177 // start-sanitize-vr5400
2178 *vr5400:
2179 // end-sanitize-vr5400
2180 // start-sanitize-r5900
2181 *r5900:
2182 // end-sanitize-r5900
2183 *r3900:
2184 // start-sanitize-tx19
2185 *tx19:
2186 // end-sanitize-tx19
2187 {
2188   unsigned32 instruction = instruction_0;
2189   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2190   int destreg = ((instruction >> 16) & 0x0000001F);
2191   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2192   {
2193     address_word vaddr = ((unsigned64)op1 + offset);
2194     address_word paddr;
2195     int uncached;
2196     if ((vaddr & 3) != 0)
2197       SignalExceptionAddressLoad();
2198     else
2199       {
2200         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2201           {
2202             unsigned64 memval = 0;
2203             unsigned64 memval1 = 0;
2204             unsigned64 mask = 0x7;
2205             unsigned int shift = 2;
2206             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2207             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2208             unsigned int byte;
2209             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2210             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2211             byte = ((vaddr & mask) ^ (bigend << shift));
2212             GPR[destreg] = (((memval >> (8 * byte)) & 0xFFFFFFFF));
2213           }
2214       }
2215   }
2216 }
2217
2218
2219 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2220 "mfhi r<RD>"
2221 *mipsI,mipsII,mipsIII,mipsIV:
2222 *vr5000:
2223 // start-sanitize-vr4320
2224 *vr4320:
2225 // end-sanitize-vr4320
2226 // start-sanitize-vr5400
2227 *vr5400:
2228 // end-sanitize-vr5400
2229 // start-sanitize-r5900
2230 *r5900:
2231 // end-sanitize-r5900
2232 *r3900:
2233 // start-sanitize-tx19
2234 *tx19:
2235 // end-sanitize-tx19
2236 {
2237   GPR[RD] = HI;
2238 #if 0
2239   HIACCESS = 3;
2240 #endif
2241 }
2242
2243
2244 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2245 "mflo r<RD>"
2246 *mipsI,mipsII,mipsIII,mipsIV:
2247 *vr5000:
2248 // start-sanitize-vr4320
2249 *vr4320:
2250 // end-sanitize-vr4320
2251 // start-sanitize-vr5400
2252 *vr5400:
2253 // end-sanitize-vr5400
2254 // start-sanitize-r5900
2255 *r5900:
2256 // end-sanitize-r5900
2257 *r3900:
2258 // start-sanitize-tx19
2259 *tx19:
2260 // end-sanitize-tx19
2261 {
2262   GPR[RD] = LO;
2263 #if 0
2264   LOACCESS = 3; /* 3rd instruction will be safe */
2265 #endif
2266 }
2267
2268
2269 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2270 "movn r<RD>, r<RS>, r<RT>"
2271 *mipsIV:
2272 *vr5000:
2273 // start-sanitize-vr4320
2274 *vr4320:
2275 // end-sanitize-vr4320
2276 // start-sanitize-vr5400
2277 *vr5400:
2278 // end-sanitize-vr5400
2279 // start-sanitize-r5900
2280 *r5900:
2281 // end-sanitize-r5900
2282 {
2283   if (GPR[RT] != 0)
2284     GPR[RD] = GPR[RS];
2285 }
2286
2287
2288 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2289 "movz r<RD>, r<RS>, r<RT>"
2290 *mipsIV:
2291 *vr5000:
2292 // start-sanitize-vr4320
2293 *vr4320:
2294 // end-sanitize-vr4320
2295 // start-sanitize-vr5400
2296 *vr5400:
2297 // end-sanitize-vr5400
2298 // start-sanitize-r5900
2299 *r5900:
2300 // end-sanitize-r5900
2301 {
2302   if (GPR[RT] == 0)
2303     GPR[RD] = GPR[RS];
2304 }
2305
2306
2307 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2308 "mthi r<RS>"
2309 *mipsI,mipsII,mipsIII,mipsIV:
2310 *vr5000:
2311 // start-sanitize-vr4320
2312 *vr4320:
2313 // end-sanitize-vr4320
2314 // start-sanitize-vr5400
2315 *vr5400:
2316 // end-sanitize-vr5400
2317 // start-sanitize-r5900
2318 *r5900:
2319 // end-sanitize-r5900
2320 *r3900:
2321 // start-sanitize-tx19
2322 *tx19:
2323 // end-sanitize-tx19
2324 {
2325 #if 0
2326   if (HIACCESS != 0)
2327     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
2328 #endif
2329   HI = GPR[RS];
2330 #if 0
2331   HIACCESS = 3; /* 3rd instruction will be safe */
2332 #endif
2333 }
2334
2335
2336 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2337 "mtlo r<RS>"
2338 *mipsI,mipsII,mipsIII,mipsIV:
2339 *vr5000:
2340 // start-sanitize-vr4320
2341 *vr4320:
2342 // end-sanitize-vr4320
2343 // start-sanitize-vr5400
2344 *vr5400:
2345 // end-sanitize-vr5400
2346 // start-sanitize-r5900
2347 *r5900:
2348 // end-sanitize-r5900
2349 *r3900:
2350 // start-sanitize-tx19
2351 *tx19:
2352 // end-sanitize-tx19
2353 {
2354 #if 0
2355   if (LOACCESS != 0)
2356     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
2357 #endif
2358   LO = GPR[RS];
2359 #if 0
2360   LOACCESS = 3; /* 3rd instruction will be safe */
2361 #endif
2362 }
2363
2364
2365 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2366 "mult r<RS>, r<RT>"
2367 *mipsI,mipsII,mipsIII,mipsIV:
2368 // start-sanitize-vr4320
2369 *vr4320:
2370 // end-sanitize-vr4320
2371 {
2372   signed64 prod;
2373   CHECKHILO ("Multiplication");
2374   prod = (((signed64)(signed32) GPR[RS])
2375           * ((signed64)(signed32) GPR[RT]));
2376   LO = EXTEND32 (VL4_8 (prod));
2377   HI = EXTEND32 (VH4_8 (prod));
2378 }
2379
2380
2381 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2382 "mult r<RD>, r<RS>, r<RT>"
2383 *vr5000:
2384 // start-sanitize-vr5400
2385 *vr5400:
2386 // end-sanitize-vr5400
2387 // start-sanitize-r5900
2388 *r5900:
2389 // end-sanitize-r5900
2390 *r3900:
2391 // start-sanitize-tx19
2392 *tx19:
2393 // end-sanitize-tx19
2394 {
2395   signed64 prod;
2396   CHECKHILO ("Multiplication");
2397   prod = (((signed64)(signed32) GPR[RS])
2398           * ((signed64)(signed32) GPR[RT]));
2399   LO = EXTEND32 (VL4_8 (prod));
2400   HI = EXTEND32 (VH4_8 (prod));
2401   if (RD != 0)
2402     GPR[RD] = LO;
2403 }
2404
2405
2406 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2407 "multu r<RS>, r<RT>"
2408 *mipsI,mipsII,mipsIII,mipsIV:
2409 // start-sanitize-vr4320
2410 *vr4320:
2411 // end-sanitize-vr4320
2412 {
2413   unsigned64 prod;
2414   CHECKHILO ("Multiplication");
2415   prod = (((unsigned64)(unsigned32) GPR[RS])
2416           * ((unsigned64)(unsigned32) GPR[RT]));
2417   LO = EXTEND32 (VL4_8 (prod));
2418   HI = EXTEND32 (VH4_8 (prod));
2419 }
2420 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2421 "multu r<RD>, r<RS>, r<RT>"
2422 *vr5000:
2423 // start-sanitize-vr5400
2424 *vr5400:
2425 // end-sanitize-vr5400
2426 // start-sanitize-r5900
2427 *r5900:
2428 // end-sanitize-r5900
2429 *r3900:
2430 // start-sanitize-tx19
2431 *tx19:
2432 // end-sanitize-tx19
2433 {
2434   unsigned64 prod;
2435   CHECKHILO ("Multiplication");
2436   prod = (((unsigned64)(unsigned32) GPR[RS])
2437           * ((unsigned64)(unsigned32) GPR[RT]));
2438   LO = EXTEND32 (VL4_8 (prod));
2439   HI = EXTEND32 (VH4_8 (prod));
2440   if (RD != 0)
2441     GPR[RD] = LO;
2442 }
2443
2444
2445 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2446 "nor r<RD>, r<RS>, r<RT>"
2447 *mipsI,mipsII,mipsIII,mipsIV:
2448 *vr5000:
2449 // start-sanitize-vr4320
2450 *vr4320:
2451 // end-sanitize-vr4320
2452 // start-sanitize-vr5400
2453 *vr5400:
2454 // end-sanitize-vr5400
2455 // start-sanitize-r5900
2456 *r5900:
2457 // end-sanitize-r5900
2458 *r3900:
2459 // start-sanitize-tx19
2460 *tx19:
2461 // end-sanitize-tx19
2462 {
2463   GPR[RD] = ~ (GPR[RS] | GPR[RT]);
2464 }
2465
2466
2467 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2468 "or r<RD>, r<RS>, r<RT>"
2469 *mipsI,mipsII,mipsIII,mipsIV:
2470 *vr5000:
2471 // start-sanitize-vr4320
2472 *vr4320:
2473 // end-sanitize-vr4320
2474 // start-sanitize-vr5400
2475 *vr5400:
2476 // end-sanitize-vr5400
2477 // start-sanitize-r5900
2478 *r5900:
2479 // end-sanitize-r5900
2480 *r3900:
2481 // start-sanitize-tx19
2482 *tx19:
2483 // end-sanitize-tx19
2484 {
2485   GPR[RD] = (GPR[RS] | GPR[RT]);
2486 }
2487
2488
2489 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2490 "ori r<RT>, r<RS>, <IMMEDIATE>"
2491 *mipsI,mipsII,mipsIII,mipsIV:
2492 *vr5000:
2493 // start-sanitize-vr4320
2494 *vr4320:
2495 // end-sanitize-vr4320
2496 // start-sanitize-vr5400
2497 *vr5400:
2498 // end-sanitize-vr5400
2499 // start-sanitize-r5900
2500 *r5900:
2501 // end-sanitize-r5900
2502 *r3900:
2503 // start-sanitize-tx19
2504 *tx19:
2505 // end-sanitize-tx19
2506 {
2507   GPR[RT] = (GPR[RS] | IMMEDIATE);
2508 }
2509
2510
2511 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2512 *mipsIV:
2513 *vr5000:
2514 // start-sanitize-vr4320
2515 *vr4320:
2516 // end-sanitize-vr4320
2517 // start-sanitize-vr5400
2518 *vr5400:
2519 // end-sanitize-vr5400
2520 // start-sanitize-r5900
2521 *r5900:
2522 // end-sanitize-r5900
2523 {
2524   unsigned32 instruction = instruction_0;
2525   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2526   int hint = ((instruction >> 16) & 0x0000001F);
2527   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2528   {
2529     address_word vaddr = ((unsigned64)op1 + offset);
2530     address_word paddr;
2531     int uncached;
2532     {
2533       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2534         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2535     }
2536   }
2537 }
2538
2539 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2540 "sb r<RT>, <OFFSET>(r<BASE>)"
2541 *mipsI,mipsII,mipsIII,mipsIV:
2542 *vr5000:
2543 // start-sanitize-vr4320
2544 *vr4320:
2545 // end-sanitize-vr4320
2546 // start-sanitize-vr5400
2547 *vr5400:
2548 // end-sanitize-vr5400
2549 // start-sanitize-r5900
2550 *r5900:
2551 // end-sanitize-r5900
2552 *r3900:
2553 // start-sanitize-tx19
2554 *tx19:
2555 // end-sanitize-tx19
2556 {
2557   unsigned32 instruction = instruction_0;
2558   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2559   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2560   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2561   {
2562     address_word vaddr = ((unsigned64)op1 + offset);
2563     address_word paddr;
2564     int uncached;
2565     {
2566       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2567         {
2568           unsigned64 memval = 0;
2569           unsigned64 memval1 = 0;
2570           unsigned64 mask = 0x7;
2571           unsigned int shift = 0;
2572           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2573           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2574           unsigned int byte;
2575           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2576           byte = ((vaddr & mask) ^ (bigend << shift));
2577           memval = ((unsigned64) op2 << (8 * byte));
2578           {
2579             StoreMemory(uncached,AccessLength_BYTE,memval,memval1,paddr,vaddr,isREAL);
2580           }
2581         }
2582     }
2583   }
2584 }
2585
2586
2587 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2588 "sc r<RT>, <OFFSET>(r<BASE>)"
2589 *mipsII:
2590 *mipsIII:
2591 *mipsIV:
2592 *vr5000:
2593 // start-sanitize-vr4320
2594 *vr4320:
2595 // end-sanitize-vr4320
2596 // start-sanitize-vr5400
2597 *vr5400:
2598 // end-sanitize-vr5400
2599 // start-sanitize-r5900
2600 *r5900:
2601 // end-sanitize-r5900
2602 *r3900:
2603 // start-sanitize-tx19
2604 *tx19:
2605 // end-sanitize-tx19
2606 {
2607   unsigned32 instruction = instruction_0;
2608   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2609   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2610   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2611   {
2612     address_word vaddr = ((unsigned64)op1 + offset);
2613     address_word paddr;
2614     int uncached;
2615     if ((vaddr & 3) != 0)
2616       SignalExceptionAddressStore();
2617     else
2618       {
2619         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2620           {
2621             unsigned64 memval = 0;
2622             unsigned64 memval1 = 0;
2623             unsigned64 mask = 0x7;
2624             unsigned int byte;
2625             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2626             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2627             memval = ((unsigned64) op2 << (8 * byte));
2628             if (LLBIT)
2629               {
2630                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2631               }
2632             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2633           }
2634       }
2635   }
2636 }
2637
2638
2639 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2640 "scd r<RT>, <OFFSET>(r<BASE>)"
2641 *mipsIII:
2642 *mipsIV:
2643 *vr5000:
2644 // start-sanitize-vr4320
2645 *vr4320:
2646 // end-sanitize-vr4320
2647 // start-sanitize-vr5400
2648 *vr5400:
2649 // end-sanitize-vr5400
2650 // start-sanitize-r5900
2651 *r5900:
2652 // end-sanitize-r5900
2653 *r3900:
2654 // start-sanitize-tx19
2655 *tx19:
2656 // end-sanitize-tx19
2657 {
2658   unsigned32 instruction = instruction_0;
2659   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2660   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2661   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2662   {
2663     address_word vaddr = ((unsigned64)op1 + offset);
2664     address_word paddr;
2665     int uncached;
2666     if ((vaddr & 7) != 0)
2667       SignalExceptionAddressStore();
2668     else
2669       {
2670         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2671           {
2672             unsigned64 memval = 0;
2673             unsigned64 memval1 = 0;
2674             memval = op2;
2675             if (LLBIT)
2676               {
2677                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2678               }
2679             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2680           }
2681       }
2682   }
2683 }
2684
2685
2686 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2687 "sd r<RT>, <OFFSET>(r<BASE>)"
2688 *mipsIII:
2689 *mipsIV:
2690 *vr5000:
2691 // start-sanitize-vr4320
2692 *vr4320:
2693 // end-sanitize-vr4320
2694 // start-sanitize-vr5400
2695 *vr5400:
2696 // end-sanitize-vr5400
2697 // start-sanitize-r5900
2698 *r5900:
2699 // end-sanitize-r5900
2700 *r3900:
2701 // start-sanitize-tx19
2702 *tx19:
2703 // end-sanitize-tx19
2704 {
2705   unsigned32 instruction = instruction_0;
2706   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2707   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2708   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2709   {
2710     address_word vaddr = ((unsigned64)op1 + offset);
2711     address_word paddr;
2712     int uncached;
2713     if ((vaddr & 7) != 0)
2714       SignalExceptionAddressStore();
2715     else
2716       {
2717         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2718           {
2719             unsigned64 memval = 0;
2720             unsigned64 memval1 = 0;
2721             memval = op2;
2722             {
2723               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2724             }
2725           }
2726       }
2727   }
2728 }
2729
2730
2731 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2732 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2733 *mipsII:
2734 *mipsIII:
2735 *mipsIV:
2736 *vr5000:
2737 // start-sanitize-vr4320
2738 *vr4320:
2739 // end-sanitize-vr4320
2740 // start-sanitize-vr5400
2741 *vr5400:
2742 // end-sanitize-vr5400
2743 // start-sanitize-r5900
2744 *r5900:
2745 // end-sanitize-r5900
2746 *r3900:
2747 // start-sanitize-tx19
2748 *tx19:
2749 // end-sanitize-tx19
2750 {
2751   unsigned32 instruction = instruction_0;
2752   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2753   int destreg = ((instruction >> 16) & 0x0000001F);
2754   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2755   {
2756     address_word vaddr = ((unsigned64)op1 + offset);
2757     address_word paddr;
2758     int uncached;
2759     if ((vaddr & 7) != 0)
2760       SignalExceptionAddressStore();
2761     else
2762       {
2763         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2764           {
2765             unsigned64 memval = 0;
2766             unsigned64 memval1 = 0;
2767             memval = (unsigned64)COP_SD(((instruction >> 26) & 0x3),destreg);
2768             {
2769               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2770             }
2771           }
2772       }
2773   }
2774 }
2775
2776
2777 // start-sanitize-sky
2778 111010,5.BASE,5.RT,16.OFFSET:NORMAL:64::SQC2
2779 "sqc2 r<RT>, <OFFSET>(r<BASE>)"
2780 *r5900:
2781 {
2782 #ifdef TARGET_SKY
2783   unsigned32 instruction = instruction_0;
2784   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2785   int destreg = ((instruction >> 16) & 0x0000001F);
2786   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2787   {
2788     address_word vaddr = ((unsigned64)op1 + offset);
2789     address_word paddr;
2790     int uncached;
2791     if ((vaddr & 0x0f) != 0)
2792       SignalExceptionAddressStore();
2793     else
2794       {
2795         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2796           {
2797             unsigned128 qw;
2798             unsigned64 memval0 = 0;
2799             unsigned64 memval1 = 0;
2800             qw = COP_SQ(((instruction >> 26) & 0x3),destreg);
2801             memval0 = *A8_16(& qw, 0);
2802             memval1 = *A8_16(& qw, 1);
2803             {
2804               StoreMemory(uncached,AccessLength_WORD,memval0,memval1,paddr,vaddr,isREAL);
2805             }
2806           }
2807       }
2808   }
2809 #endif /* TARGET_SKY */
2810 }
2811 // end-sanitize-sky
2812
2813
2814
2815 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2816 "sdl r<RT>, <OFFSET>(r<BASE>)"
2817 *mipsIII:
2818 *mipsIV:
2819 *vr5000:
2820 // start-sanitize-vr4320
2821 *vr4320:
2822 // end-sanitize-vr4320
2823 // start-sanitize-vr5400
2824 *vr5400:
2825 // end-sanitize-vr5400
2826 // start-sanitize-r5900
2827 *r5900:
2828 // end-sanitize-r5900
2829 *r3900:
2830 // start-sanitize-tx19
2831 *tx19:
2832 // end-sanitize-tx19
2833 {
2834   unsigned32 instruction = instruction_0;
2835   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2836   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2837   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2838   {
2839     address_word vaddr = ((unsigned64)op1 + offset);
2840     address_word paddr;
2841     int uncached;
2842     {
2843       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2844         {
2845           unsigned64 memval = 0;
2846           unsigned64 memval1 = 0;
2847           unsigned64 mask = 7;
2848           unsigned int reverse = (ReverseEndian ? mask : 0);
2849           unsigned int bigend = (BigEndianCPU ? mask : 0);
2850           int byte;
2851           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2852           byte = ((vaddr & mask) ^ bigend);
2853           if (!BigEndianMem)
2854             paddr &= ~mask;
2855           memval = (op2 >> (8 * (7 - byte)));
2856           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
2857         }
2858     }
2859   }
2860 }
2861
2862
2863 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2864 "sdr r<RT>, <OFFSET>(r<BASE>)"
2865 *mipsIII:
2866 *mipsIV:
2867 *vr5000:
2868 // start-sanitize-vr4320
2869 *vr4320:
2870 // end-sanitize-vr4320
2871 // start-sanitize-vr5400
2872 *vr5400:
2873 // end-sanitize-vr5400
2874 // start-sanitize-r5900
2875 *r5900:
2876 // end-sanitize-r5900
2877 *r3900:
2878 // start-sanitize-tx19
2879 *tx19:
2880 // end-sanitize-tx19
2881 {
2882   address_word paddr;
2883   int uncached;
2884   unsigned64 memval;
2885   unsigned64 mask = 7;
2886   unsigned int reverse = (ReverseEndian ? mask : 0);
2887   unsigned int bigend = (BigEndianCPU ? mask : 0);
2888   int byte;
2889   address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
2890   AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
2891   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
2892   if (BigEndianMem)
2893     paddr &= ~mask;
2894   byte = ((vaddr & mask) ^ bigend);
2895   memval = (GPR[RT] << (byte * 8));
2896   StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,0,paddr,vaddr,isREAL);
2897 }
2898
2899
2900 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2901 "sh r<RT>, <OFFSET>(r<BASE>)"
2902 *mipsI,mipsII,mipsIII,mipsIV:
2903 *vr5000:
2904 // start-sanitize-vr4320
2905 *vr4320:
2906 // end-sanitize-vr4320
2907 // start-sanitize-vr5400
2908 *vr5400:
2909 // end-sanitize-vr5400
2910 // start-sanitize-r5900
2911 *r5900:
2912 // end-sanitize-r5900
2913 *r3900:
2914 // start-sanitize-tx19
2915 *tx19:
2916 // end-sanitize-tx19
2917 {
2918   unsigned32 instruction = instruction_0;
2919   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2920   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2921   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2922   {
2923     address_word vaddr = ((unsigned64)op1 + offset);
2924     address_word paddr;
2925     int uncached;
2926     if ((vaddr & 1) != 0)
2927       SignalExceptionAddressStore();
2928     else
2929       {
2930         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2931           {
2932             unsigned64 memval = 0;
2933             unsigned64 memval1 = 0;
2934             unsigned64 mask = 0x7;
2935             unsigned int shift = 1;
2936             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2937             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2938             unsigned int byte;
2939             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2940             byte = ((vaddr & mask) ^ (bigend << shift));
2941             memval = ((unsigned64) op2 << (8 * byte));
2942             {
2943               StoreMemory(uncached,AccessLength_HALFWORD,memval,memval1,paddr,vaddr,isREAL);
2944             }
2945           }
2946       }
2947   }
2948 }
2949
2950
2951 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2952 "sll r<RD>, r<RT>, <SHIFT>"
2953 *mipsI,mipsII,mipsIII,mipsIV:
2954 *vr5000:
2955 // start-sanitize-vr4320
2956 *vr4320:
2957 // end-sanitize-vr4320
2958 // start-sanitize-vr5400
2959 *vr5400:
2960 // end-sanitize-vr5400
2961 // start-sanitize-r5900
2962 *r5900:
2963 // end-sanitize-r5900
2964 *r3900:
2965 // start-sanitize-tx19
2966 *tx19:
2967 // end-sanitize-tx19
2968 {
2969   int s = SHIFT;
2970   unsigned32 temp = (GPR[RT] << s);
2971   GPR[RD] = EXTEND32 (temp);
2972 }
2973
2974
2975 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2976 "sllv r<RD>, r<RT>, r<RS>"
2977 *mipsI,mipsII,mipsIII,mipsIV:
2978 *vr5000:
2979 // start-sanitize-vr4320
2980 *vr4320:
2981 // end-sanitize-vr4320
2982 // start-sanitize-vr5400
2983 *vr5400:
2984 // end-sanitize-vr5400
2985 // start-sanitize-r5900
2986 *r5900:
2987 // end-sanitize-r5900
2988 *r3900:
2989 // start-sanitize-tx19
2990 *tx19:
2991 // end-sanitize-tx19
2992 {
2993   int s = MASKED (GPR[RS], 4, 0);
2994   unsigned32 temp = (GPR[RT] << s);
2995   GPR[RD] = EXTEND32 (temp);
2996 }
2997
2998
2999 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3000 "slt r<RD>, r<RS>, r<RT>"
3001 *mipsI,mipsII,mipsIII,mipsIV:
3002 *vr5000:
3003 // start-sanitize-vr4320
3004 *vr4320:
3005 // end-sanitize-vr4320
3006 // start-sanitize-vr5400
3007 *vr5400:
3008 // end-sanitize-vr5400
3009 // start-sanitize-r5900
3010 *r5900:
3011 // end-sanitize-r5900
3012 *r3900:
3013 // start-sanitize-tx19
3014 *tx19:
3015 // end-sanitize-tx19
3016 {
3017   GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
3018 }
3019
3020
3021 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3022 "slti r<RT>, r<RS>, <IMMEDIATE>"
3023 *mipsI,mipsII,mipsIII,mipsIV:
3024 *vr5000:
3025 // start-sanitize-vr4320
3026 *vr4320:
3027 // end-sanitize-vr4320
3028 // start-sanitize-vr5400
3029 *vr5400:
3030 // end-sanitize-vr5400
3031 // start-sanitize-r5900
3032 *r5900:
3033 // end-sanitize-r5900
3034 *r3900:
3035 // start-sanitize-tx19
3036 *tx19:
3037 // end-sanitize-tx19
3038 {
3039   GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
3040 }
3041
3042
3043 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3044 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3045 *mipsI,mipsII,mipsIII,mipsIV:
3046 *vr5000:
3047 // start-sanitize-vr4320
3048 *vr4320:
3049 // end-sanitize-vr4320
3050 // start-sanitize-vr5400
3051 *vr5400:
3052 // end-sanitize-vr5400
3053 // start-sanitize-r5900
3054 *r5900:
3055 // end-sanitize-r5900
3056 *r3900:
3057 // start-sanitize-tx19
3058 *tx19:
3059 // end-sanitize-tx19
3060 {
3061   GPR[RT] = ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE));
3062 }
3063
3064 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3065 "sltu r<RD>, r<RS>, r<RT>"
3066 *mipsI,mipsII,mipsIII,mipsIV:
3067 *vr5000:
3068 // start-sanitize-vr4320
3069 *vr4320:
3070 // end-sanitize-vr4320
3071 // start-sanitize-vr5400
3072 *vr5400:
3073 // end-sanitize-vr5400
3074 // start-sanitize-r5900
3075 *r5900:
3076 // end-sanitize-r5900
3077 *r3900:
3078 // start-sanitize-tx19
3079 *tx19:
3080 // end-sanitize-tx19
3081 {
3082   GPR[RD] = ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]);
3083 }
3084
3085
3086 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3087 "sra r<RD>, r<RT>, <SHIFT>"
3088 *mipsI,mipsII,mipsIII,mipsIV:
3089 *vr5000:
3090 // start-sanitize-vr4320
3091 *vr4320:
3092 // end-sanitize-vr4320
3093 // start-sanitize-vr5400
3094 *vr5400:
3095 // end-sanitize-vr5400
3096 // start-sanitize-r5900
3097 *r5900:
3098 // end-sanitize-r5900
3099 *r3900:
3100 // start-sanitize-tx19
3101 *tx19:
3102 // end-sanitize-tx19
3103 {
3104   int s = SHIFT;
3105   signed32 temp = (signed32) GPR[RT] >> s;
3106   GPR[RD] = EXTEND32 (temp);
3107 }
3108
3109
3110 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3111 "srav r<RD>, r<RT>, r<RS>"
3112 *mipsI,mipsII,mipsIII,mipsIV:
3113 *vr5000:
3114 // start-sanitize-vr4320
3115 *vr4320:
3116 // end-sanitize-vr4320
3117 // start-sanitize-vr5400
3118 *vr5400:
3119 // end-sanitize-vr5400
3120 // start-sanitize-r5900
3121 *r5900:
3122 // end-sanitize-r5900
3123 *r3900:
3124 // start-sanitize-tx19
3125 *tx19:
3126 // end-sanitize-tx19
3127 {
3128   int s = MASKED (GPR[RS], 4, 0);
3129   signed32 temp = (signed32) GPR[RT] >> s;
3130   GPR[RD] = EXTEND32 (temp);
3131 }
3132
3133
3134 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3135 "srl r<RD>, r<RT>, <SHIFT>"
3136 *mipsI,mipsII,mipsIII,mipsIV:
3137 *vr5000:
3138 // start-sanitize-vr4320
3139 *vr4320:
3140 // end-sanitize-vr4320
3141 // start-sanitize-vr5400
3142 *vr5400:
3143 // end-sanitize-vr5400
3144 // start-sanitize-r5900
3145 *r5900:
3146 // end-sanitize-r5900
3147 *r3900:
3148 // start-sanitize-tx19
3149 *tx19:
3150 // end-sanitize-tx19
3151 {
3152   int s = SHIFT;
3153   unsigned32 temp = (unsigned32) GPR[RT] >> s;
3154   GPR[RD] = EXTEND32 (temp);
3155 }
3156
3157
3158 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3159 "srlv r<RD>, r<RT>, r<RS>"
3160 *mipsI,mipsII,mipsIII,mipsIV:
3161 *vr5000:
3162 // start-sanitize-vr4320
3163 *vr4320:
3164 // end-sanitize-vr4320
3165 // start-sanitize-vr5400
3166 *vr5400:
3167 // end-sanitize-vr5400
3168 // start-sanitize-r5900
3169 *r5900:
3170 // end-sanitize-r5900
3171 *r3900:
3172 // start-sanitize-tx19
3173 *tx19:
3174 // end-sanitize-tx19
3175 {
3176   int s = MASKED (GPR[RS], 4, 0);
3177   unsigned32 temp = (unsigned32) GPR[RT] >> s;
3178   GPR[RD] = EXTEND32 (temp);
3179 }
3180
3181
3182 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3183 "sub r<RD>, r<RS>, r<RT>"
3184 *mipsI,mipsII,mipsIII,mipsIV:
3185 *vr5000:
3186 // start-sanitize-vr4320
3187 *vr4320:
3188 // end-sanitize-vr4320
3189 // start-sanitize-vr5400
3190 *vr5400:
3191 // end-sanitize-vr5400
3192 // start-sanitize-r5900
3193 *r5900:
3194 // end-sanitize-r5900
3195 *r3900:
3196 // start-sanitize-tx19
3197 *tx19:
3198 // end-sanitize-tx19
3199 {
3200   ALU32_BEGIN (GPR[RS]);
3201   ALU32_SUB (GPR[RT]);
3202   ALU32_END (GPR[RD]);
3203 }
3204
3205
3206 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3207 "subu r<RD>, r<RS>, r<RT>"
3208 *mipsI,mipsII,mipsIII,mipsIV:
3209 *vr5000:
3210 // start-sanitize-vr4320
3211 *vr4320:
3212 // end-sanitize-vr4320
3213 // start-sanitize-vr5400
3214 *vr5400:
3215 // end-sanitize-vr5400
3216 // start-sanitize-r5900
3217 *r5900:
3218 // end-sanitize-r5900
3219 *r3900:
3220 // start-sanitize-tx19
3221 *tx19:
3222 // end-sanitize-tx19
3223 {
3224   GPR[RD] = EXTEND32 (GPR[RS] - GPR[RT]);
3225 }
3226
3227
3228 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3229 "sw r<RT>, <OFFSET>(r<BASE>)"
3230 *mipsI,mipsII,mipsIII,mipsIV:
3231 *vr5000:
3232 // start-sanitize-vr4320
3233 *vr4320:
3234 // end-sanitize-vr4320
3235 // start-sanitize-vr5400
3236 *vr5400:
3237 // end-sanitize-vr5400
3238 // start-sanitize-r5900
3239 *r5900:
3240 // end-sanitize-r5900
3241 *r3900:
3242 // start-sanitize-tx19
3243 *tx19:
3244 // end-sanitize-tx19
3245 {
3246   unsigned32 instruction = instruction_0;
3247   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3248   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3249   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3250   {
3251     address_word vaddr = ((unsigned64)op1 + offset);
3252     address_word paddr;
3253     int uncached;
3254     if ((vaddr & 3) != 0)
3255       SignalExceptionAddressStore();
3256     else
3257       {
3258         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3259           {
3260             unsigned64 memval = 0;
3261             unsigned64 memval1 = 0;
3262             unsigned64 mask = 0x7;
3263             unsigned int byte;
3264             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3265             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3266             memval = ((unsigned64) op2 << (8 * byte));
3267             {
3268               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3269             }
3270           }
3271       }
3272   }
3273 }
3274
3275
3276 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3277 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3278 *mipsI,mipsII,mipsIII,mipsIV:
3279 *vr5000:
3280 // start-sanitize-vr4320
3281 *vr4320:
3282 // end-sanitize-vr4320
3283 // start-sanitize-vr5400
3284 *vr5400:
3285 // end-sanitize-vr5400
3286 *r3900:
3287 // start-sanitize-tx19
3288 *tx19:
3289 // end-sanitize-tx19
3290 {
3291   unsigned32 instruction = instruction_0;
3292   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3293   int destreg = ((instruction >> 16) & 0x0000001F);
3294   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3295   {
3296     address_word vaddr = ((unsigned64)op1 + offset);
3297     address_word paddr;
3298     int uncached;
3299     if ((vaddr & 3) != 0)
3300       SignalExceptionAddressStore();
3301     else
3302       {
3303         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3304           {
3305             unsigned64 memval = 0;
3306             unsigned64 memval1 = 0;
3307             unsigned64 mask = 0x7;
3308             unsigned int byte;
3309             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3310             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3311             memval = (((unsigned64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
3312             {
3313               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3314             }
3315           }
3316       }
3317   }
3318 }
3319
3320
3321 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3322 "swl r<RT>, <OFFSET>(r<BASE>)"
3323 *mipsI,mipsII,mipsIII,mipsIV:
3324 *vr5000:
3325 // start-sanitize-vr4320
3326 *vr4320:
3327 // end-sanitize-vr4320
3328 // start-sanitize-vr5400
3329 *vr5400:
3330 // end-sanitize-vr5400
3331 // start-sanitize-r5900
3332 *r5900:
3333 // end-sanitize-r5900
3334 *r3900:
3335 // start-sanitize-tx19
3336 *tx19:
3337 // end-sanitize-tx19
3338 {
3339   unsigned32 instruction = instruction_0;
3340   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3341   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3342   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3343   {
3344     address_word vaddr = ((unsigned64)op1 + offset);
3345     address_word paddr;
3346     int uncached;
3347     {
3348       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3349         {
3350           unsigned64 memval = 0;
3351           unsigned64 memval1 = 0;
3352           unsigned64 mask = 3;
3353           unsigned int reverse = (ReverseEndian ? mask : 0);
3354           unsigned int bigend = (BigEndianCPU ? mask : 0);
3355           int byte;
3356           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3357           byte = ((vaddr & mask) ^ bigend);
3358           if (!BigEndianMem)
3359             paddr &= ~mask;
3360           memval = (op2 >> (8 * (3 - byte)));
3361           if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
3362             memval <<= 32;
3363           }
3364           StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
3365         }
3366     }
3367   }
3368 }
3369
3370
3371 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3372 "swr r<RT>, <OFFSET>(r<BASE>)"
3373 *mipsI,mipsII,mipsIII,mipsIV:
3374 *vr5000:
3375 // start-sanitize-vr4320
3376 *vr4320:
3377 // end-sanitize-vr4320
3378 // start-sanitize-vr5400
3379 *vr5400:
3380 // end-sanitize-vr5400
3381 // start-sanitize-r5900
3382 *r5900:
3383 // end-sanitize-r5900
3384 *r3900:
3385 // start-sanitize-tx19
3386 *tx19:
3387 // end-sanitize-tx19
3388 {
3389   unsigned64 memval = 0;
3390   unsigned64 mask = 3;
3391   unsigned int reverse = (ReverseEndian ? mask : 0);
3392   unsigned int bigend = (BigEndianCPU ? mask : 0);
3393   int byte;
3394   address_word paddr;
3395   int uncached;
3396   address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
3397   AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
3398   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
3399   if (BigEndianMem)
3400     paddr &= ~mask;
3401   byte = ((vaddr & mask) ^ bigend);
3402   memval = (GPR[RT] << (byte * 8));
3403   if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2))
3404     memval <<= 32;
3405   StoreMemory(uncached,(AccessLength_WORD - byte),memval,0,paddr,vaddr,isREAL);
3406 }
3407
3408
3409 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3410 "sync":STYPE == 0
3411 "sync <STYPE>"
3412 *mipsII:
3413 *mipsIII:
3414 *mipsIV:
3415 *vr5000:
3416 // start-sanitize-vr4320
3417 *vr4320:
3418 // end-sanitize-vr4320
3419 // start-sanitize-vr5400
3420 *vr5400:
3421 // end-sanitize-vr5400
3422 // start-sanitize-r5900
3423 *r5900:
3424 // end-sanitize-r5900
3425 *r3900:
3426 // start-sanitize-tx19
3427 *tx19:
3428 // end-sanitize-tx19
3429 {
3430   SyncOperation (STYPE);
3431 }
3432
3433
3434 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3435 "syscall <CODE>"
3436 *mipsI,mipsII,mipsIII,mipsIV:
3437 *vr5000:
3438 // start-sanitize-vr4320
3439 *vr4320:
3440 // end-sanitize-vr4320
3441 // start-sanitize-vr5400
3442 *vr5400:
3443 // end-sanitize-vr5400
3444 // start-sanitize-r5900
3445 *r5900:
3446 // end-sanitize-r5900
3447 *r3900:
3448 // start-sanitize-tx19
3449 *tx19:
3450 // end-sanitize-tx19
3451 {
3452   SignalException(SystemCall, instruction_0);
3453 }
3454
3455
3456 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3457 "teq r<RS>, r<RT>"
3458 *mipsII:
3459 *mipsIII:
3460 *mipsIV:
3461 *vr5000:
3462 // start-sanitize-vr4320
3463 *vr4320:
3464 // end-sanitize-vr4320
3465 // start-sanitize-vr5400
3466 *vr5400:
3467 // end-sanitize-vr5400
3468 // start-sanitize-r5900
3469 *r5900:
3470 // end-sanitize-r5900
3471 *r3900:
3472 // start-sanitize-tx19
3473 *tx19:
3474 // end-sanitize-tx19
3475 {
3476   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3477     SignalException(Trap, instruction_0);
3478 }
3479
3480
3481 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3482 "teqi r<RS>, <IMMEDIATE>"
3483 *mipsII:
3484 *mipsIII:
3485 *mipsIV:
3486 *vr5000:
3487 // start-sanitize-vr4320
3488 *vr4320:
3489 // end-sanitize-vr4320
3490 // start-sanitize-vr5400
3491 *vr5400:
3492 // end-sanitize-vr5400
3493 // start-sanitize-r5900
3494 *r5900:
3495 // end-sanitize-r5900
3496 *r3900:
3497 // start-sanitize-tx19
3498 *tx19:
3499 // end-sanitize-tx19
3500 {
3501   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3502     SignalException(Trap, instruction_0);
3503 }
3504
3505
3506 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3507 "tge r<RS>, r<RT>"
3508 *mipsII:
3509 *mipsIII:
3510 *mipsIV:
3511 *vr5000:
3512 // start-sanitize-vr4320
3513 *vr4320:
3514 // end-sanitize-vr4320
3515 // start-sanitize-vr5400
3516 *vr5400:
3517 // end-sanitize-vr5400
3518 // start-sanitize-r5900
3519 *r5900:
3520 // end-sanitize-r5900
3521 *r3900:
3522 // start-sanitize-tx19
3523 *tx19:
3524 // end-sanitize-tx19
3525 {
3526   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3527     SignalException(Trap, instruction_0);
3528 }
3529
3530
3531 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3532 "tgei r<RS>, <IMMEDIATE>"
3533 *mipsII:
3534 *mipsIII:
3535 *mipsIV:
3536 *vr5000:
3537 // start-sanitize-vr4320
3538 *vr4320:
3539 // end-sanitize-vr4320
3540 // start-sanitize-vr5400
3541 *vr5400:
3542 // end-sanitize-vr5400
3543 // start-sanitize-r5900
3544 *r5900:
3545 // end-sanitize-r5900
3546 *r3900:
3547 // start-sanitize-tx19
3548 *tx19:
3549 // end-sanitize-tx19
3550 {
3551   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3552     SignalException(Trap, instruction_0);
3553 }
3554
3555
3556 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3557 "tgeiu r<RS>, <IMMEDIATE>"
3558 *mipsII:
3559 *mipsIII:
3560 *mipsIV:
3561 *vr5000:
3562 // start-sanitize-vr4320
3563 *vr4320:
3564 // end-sanitize-vr4320
3565 // start-sanitize-vr5400
3566 *vr5400:
3567 // end-sanitize-vr5400
3568 // start-sanitize-r5900
3569 *r5900:
3570 // end-sanitize-r5900
3571 *r3900:
3572 // start-sanitize-tx19
3573 *tx19:
3574 // end-sanitize-tx19
3575 {
3576   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3577     SignalException(Trap, instruction_0);
3578 }
3579
3580
3581 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3582 "tgeu r<RS>, r<RT>"
3583 *mipsII:
3584 *mipsIII:
3585 *mipsIV:
3586 *vr5000:
3587 // start-sanitize-vr4320
3588 *vr4320:
3589 // end-sanitize-vr4320
3590 // start-sanitize-vr5400
3591 *vr5400:
3592 // end-sanitize-vr5400
3593 // start-sanitize-r5900
3594 *r5900:
3595 // end-sanitize-r5900
3596 *r3900:
3597 // start-sanitize-tx19
3598 *tx19:
3599 // end-sanitize-tx19
3600 {
3601   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3602     SignalException(Trap, instruction_0);
3603 }
3604
3605
3606 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3607 "tlt r<RS>, r<RT>"
3608 *mipsII:
3609 *mipsIII:
3610 *mipsIV:
3611 *vr5000:
3612 // start-sanitize-vr4320
3613 *vr4320:
3614 // end-sanitize-vr4320
3615 // start-sanitize-vr5400
3616 *vr5400:
3617 // end-sanitize-vr5400
3618 // start-sanitize-r5900
3619 *r5900:
3620 // end-sanitize-r5900
3621 *r3900:
3622 // start-sanitize-tx19
3623 *tx19:
3624 // end-sanitize-tx19
3625 {
3626   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3627     SignalException(Trap, instruction_0);
3628 }
3629
3630
3631 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3632 "tlti r<RS>, <IMMEDIATE>"
3633 *mipsII:
3634 *mipsIII:
3635 *mipsIV:
3636 *vr5000:
3637 // start-sanitize-vr4320
3638 *vr4320:
3639 // end-sanitize-vr4320
3640 // start-sanitize-vr5400
3641 *vr5400:
3642 // end-sanitize-vr5400
3643 // start-sanitize-r5900
3644 *r5900:
3645 // end-sanitize-r5900
3646 *r3900:
3647 // start-sanitize-tx19
3648 *tx19:
3649 // end-sanitize-tx19
3650 {
3651   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3652     SignalException(Trap, instruction_0);
3653 }
3654
3655
3656 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3657 "tltiu r<RS>, <IMMEDIATE>"
3658 *mipsII:
3659 *mipsIII:
3660 *mipsIV:
3661 *vr5000:
3662 // start-sanitize-vr4320
3663 *vr4320:
3664 // end-sanitize-vr4320
3665 // start-sanitize-vr5400
3666 *vr5400:
3667 // end-sanitize-vr5400
3668 // start-sanitize-r5900
3669 *r5900:
3670 // end-sanitize-r5900
3671 *r3900:
3672 // start-sanitize-tx19
3673 *tx19:
3674 // end-sanitize-tx19
3675 {
3676   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3677     SignalException(Trap, instruction_0);
3678 }
3679
3680
3681 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3682 "tltu r<RS>, r<RT>"
3683 *mipsII:
3684 *mipsIII:
3685 *mipsIV:
3686 *vr5000:
3687 // start-sanitize-vr4320
3688 *vr4320:
3689 // end-sanitize-vr4320
3690 // start-sanitize-vr5400
3691 *vr5400:
3692 // end-sanitize-vr5400
3693 // start-sanitize-r5900
3694 *r5900:
3695 // end-sanitize-r5900
3696 *r3900:
3697 // start-sanitize-tx19
3698 *tx19:
3699 // end-sanitize-tx19
3700 {
3701   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3702     SignalException(Trap, instruction_0);
3703 }
3704
3705
3706 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3707 "tne r<RS>, r<RT>"
3708 *mipsII:
3709 *mipsIII:
3710 *mipsIV:
3711 *vr5000:
3712 // start-sanitize-vr4320
3713 *vr4320:
3714 // end-sanitize-vr4320
3715 // start-sanitize-vr5400
3716 *vr5400:
3717 // end-sanitize-vr5400
3718 // start-sanitize-r5900
3719 *r5900:
3720 // end-sanitize-r5900
3721 *r3900:
3722 // start-sanitize-tx19
3723 *tx19:
3724 // end-sanitize-tx19
3725 {
3726   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3727     SignalException(Trap, instruction_0);
3728 }
3729
3730
3731 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3732 "tne r<RS>, <IMMEDIATE>"
3733 *mipsII:
3734 *mipsIII:
3735 *mipsIV:
3736 *vr5000:
3737 // start-sanitize-vr4320
3738 *vr4320:
3739 // end-sanitize-vr4320
3740 // start-sanitize-vr5400
3741 *vr5400:
3742 // end-sanitize-vr5400
3743 // start-sanitize-r5900
3744 *r5900:
3745 // end-sanitize-r5900
3746 *r3900:
3747 // start-sanitize-tx19
3748 *tx19:
3749 // end-sanitize-tx19
3750 {
3751   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3752     SignalException(Trap, instruction_0);
3753 }
3754
3755
3756 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3757 "xor r<RD>, r<RS>, r<RT>"
3758 *mipsI,mipsII,mipsIII,mipsIV:
3759 *vr5000:
3760 // start-sanitize-vr4320
3761 *vr4320:
3762 // end-sanitize-vr4320
3763 // start-sanitize-vr5400
3764 *vr5400:
3765 // end-sanitize-vr5400
3766 // start-sanitize-r5900
3767 *r5900:
3768 // end-sanitize-r5900
3769 *r3900:
3770 // start-sanitize-tx19
3771 *tx19:
3772 // end-sanitize-tx19
3773 {
3774   GPR[RD] = GPR[RS] ^ GPR[RT];
3775 }
3776
3777
3778 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3779 "xori r<RT>, r<RS>, <IMMEDIATE>"
3780 *mipsI,mipsII,mipsIII,mipsIV:
3781 *vr5000:
3782 // start-sanitize-vr4320
3783 *vr4320:
3784 // end-sanitize-vr4320
3785 // start-sanitize-vr5400
3786 *vr5400:
3787 // end-sanitize-vr5400
3788 // start-sanitize-r5900
3789 *r5900:
3790 // end-sanitize-r5900
3791 *r3900:
3792 // start-sanitize-tx19
3793 *tx19:
3794 // end-sanitize-tx19
3795 {
3796   GPR[RT] = GPR[RS] ^ IMMEDIATE;
3797 }
3798
3799 \f
3800 //
3801 // MIPS Architecture:
3802 //
3803 //        FPU Instruction Set (COP1 & COP1X)
3804 //
3805
3806
3807 :%s::::FMT:int fmt
3808 {
3809   switch (fmt)
3810     {
3811     case fmt_single: return "s";
3812     case fmt_double: return "d";
3813     case fmt_word: return "w";
3814     case fmt_long: return "l";
3815     default: return "?";
3816     }
3817 }
3818
3819 :%s::::X:int x
3820 {
3821   switch (x)
3822     {
3823     case 0: return "f";
3824     case 1: return "t";
3825     default: return "?";
3826     }
3827 }
3828
3829 :%s::::TF:int tf
3830 {
3831   if (tf)
3832     return "t";
3833   else
3834     return "f";
3835 }
3836
3837 :%s::::ND:int nd
3838 {
3839   if (nd)
3840     return "l";
3841   else
3842     return "";
3843 }
3844
3845 :%s::::COND:int cond
3846 {
3847   switch (cond)
3848     {
3849     case 00: return "f";
3850     case 01: return "un";
3851     case 02: return "eq";
3852     case 03: return "ueq";
3853     case 04: return "olt";
3854     case 05: return "ult";
3855     case 06: return "ole";
3856     case 07: return "ule";
3857     case 010: return "sf";
3858     case 011: return "ngle";
3859     case 012: return "seq";
3860     case 013: return "ngl";
3861     case 014: return "lt";
3862     case 015: return "nge";
3863     case 016: return "le";
3864     case 017: return "ngt";
3865     default: return "?";
3866     }
3867 }
3868
3869
3870 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3871 "abs.%s<FMT> f<FD>, f<FS>"
3872 *mipsI,mipsII,mipsIII,mipsIV:
3873 *vr5000:
3874 // start-sanitize-vr4320
3875 *vr4320:
3876 // end-sanitize-vr4320
3877 // start-sanitize-vr5400
3878 *vr5400:
3879 // end-sanitize-vr5400
3880 *r3900:
3881 // start-sanitize-tx19
3882 *tx19:
3883 // end-sanitize-tx19
3884 {
3885   unsigned32 instruction = instruction_0;
3886   int destreg = ((instruction >> 6) & 0x0000001F);
3887   int fs = ((instruction >> 11) & 0x0000001F);
3888   int format = ((instruction >> 21) & 0x00000007);
3889   {
3890     if ((format != fmt_single) && (format != fmt_double))
3891       SignalException(ReservedInstruction,instruction);
3892     else
3893       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
3894   }
3895 }
3896
3897
3898
3899 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3900 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3901 *mipsI,mipsII,mipsIII,mipsIV:
3902 *vr5000:
3903 // start-sanitize-vr4320
3904 *vr4320:
3905 // end-sanitize-vr4320
3906 // start-sanitize-vr5400
3907 *vr5400:
3908 // end-sanitize-vr5400
3909 *r3900:
3910 // start-sanitize-tx19
3911 *tx19:
3912 // end-sanitize-tx19
3913 {
3914   unsigned32 instruction = instruction_0;
3915   int destreg = ((instruction >> 6) & 0x0000001F);
3916   int fs = ((instruction >> 11) & 0x0000001F);
3917   int ft = ((instruction >> 16) & 0x0000001F);
3918   int format = ((instruction >> 21) & 0x00000007);
3919   {
3920     if ((format != fmt_single) && (format != fmt_double))
3921       SignalException(ReservedInstruction, instruction);
3922     else
3923       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
3924   }
3925 }
3926
3927
3928
3929 // BC1F
3930 // BC1FL
3931 // BC1T
3932 // BC1TL
3933
3934 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3935 "bc1%s<TF>%s<ND> <OFFSET>"
3936 *mipsI,mipsII,mipsIII:
3937 // start-sanitize-r5900
3938 *r5900:
3939 // end-sanitize-r5900
3940 {
3941   TRACE_BRANCH_INPUT (PREVCOC1());
3942   if (PREVCOC1() == TF)
3943     {
3944       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3945       TRACE_BRANCH_RESULT (dest);
3946       DELAY_SLOT (dest);
3947     }
3948   else if (ND)
3949     {
3950       TRACE_BRANCH_RESULT (0);
3951       NULLIFY_NEXT_INSTRUCTION ();
3952     }
3953   else
3954     {
3955       TRACE_BRANCH_RESULT (NIA);
3956     }
3957 }
3958
3959 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
3960 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3961 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3962 *mipsIV:
3963 *vr5000:
3964 // start-sanitize-vr4320
3965 *vr4320:
3966 // end-sanitize-vr4320
3967 // start-sanitize-vr5400
3968 *vr5400:
3969 // end-sanitize-vr5400
3970 *r3900:
3971 // start-sanitize-tx19
3972 *tx19:
3973 // end-sanitize-tx19
3974 {
3975   if (GETFCC(CC) == TF)
3976     {
3977       DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
3978     }
3979   else if (ND)
3980     {
3981       NULLIFY_NEXT_INSTRUCTION ();
3982     }
3983 }
3984
3985
3986
3987 // C.EQ.S
3988 // C.EQ.D
3989 // ...
3990
3991 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3992 {
3993   if ((fmt != fmt_single) && (fmt != fmt_double))
3994     SignalException (ReservedInstruction, insn);
3995   else
3996     {
3997       int less;
3998       int equal;
3999       int unordered;
4000       int condition;
4001       unsigned64 ofs = ValueFPR (fs, fmt);
4002       unsigned64 oft = ValueFPR (ft, fmt);
4003       if (NaN (ofs, fmt) || NaN (oft, fmt))
4004         {
4005           if (FCSR & FP_ENABLE (IO))
4006             {
4007               FCSR |= FP_CAUSE (IO);
4008               SignalExceptionFPE ();
4009             }
4010           less = 0;
4011           equal = 0;
4012           unordered = 1;
4013         }
4014       else
4015         {
4016           less = Less (ofs, oft, fmt);
4017           equal = Equal (ofs, oft, fmt);
4018           unordered = 0;
4019         }
4020       condition = (((cond & (1 << 2)) && less)
4021                    || ((cond & (1 << 1)) && equal)
4022                    || ((cond & (1 << 0)) && unordered));
4023       SETFCC (cc, condition);
4024     }
4025 }
4026
4027 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4028 *mipsI,mipsII,mipsIII:
4029 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":
4030 {
4031   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4032 }
4033
4034 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4035 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4036 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4037 *mipsIV:
4038 *vr5000:
4039 // start-sanitize-vr4320
4040 *vr4320:
4041 // end-sanitize-vr4320
4042 // start-sanitize-vr5400
4043 *vr5400:
4044 // end-sanitize-vr5400
4045 *r3900:
4046 // start-sanitize-tx19
4047 *tx19:
4048 // end-sanitize-tx19
4049 {
4050   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4051 }
4052
4053
4054 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4055 "ceil.l.%s<FMT> f<FD>, f<FS>"
4056 *mipsIII:
4057 *mipsIV:
4058 *vr5000:
4059 // start-sanitize-vr4320
4060 *vr4320:
4061 // end-sanitize-vr4320
4062 // start-sanitize-vr5400
4063 *vr5400:
4064 // end-sanitize-vr5400
4065 // start-sanitize-r5900
4066 *r5900:
4067 // end-sanitize-r5900
4068 *r3900:
4069 // start-sanitize-tx19
4070 *tx19:
4071 // end-sanitize-tx19
4072 {
4073   unsigned32 instruction = instruction_0;
4074   int destreg = ((instruction >> 6) & 0x0000001F);
4075   int fs = ((instruction >> 11) & 0x0000001F);
4076   int format = ((instruction >> 21) & 0x00000007);
4077   {
4078     if ((format != fmt_single) && (format != fmt_double))
4079       SignalException(ReservedInstruction,instruction);
4080     else
4081       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4082   }
4083 }
4084
4085
4086 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4087 *mipsII:
4088 *mipsIII:
4089 *mipsIV:
4090 *vr5000:
4091 // start-sanitize-vr4320
4092 *vr4320:
4093 // end-sanitize-vr4320
4094 // start-sanitize-vr5400
4095 *vr5400:
4096 // end-sanitize-vr5400
4097 // start-sanitize-r5900
4098 *r5900:
4099 // end-sanitize-r5900
4100 *r3900:
4101 // start-sanitize-tx19
4102 *tx19:
4103 // end-sanitize-tx19
4104 {
4105   unsigned32 instruction = instruction_0;
4106   int destreg = ((instruction >> 6) & 0x0000001F);
4107   int fs = ((instruction >> 11) & 0x0000001F);
4108   int format = ((instruction >> 21) & 0x00000007);
4109   {
4110   if ((format != fmt_single) && (format != fmt_double))
4111    SignalException(ReservedInstruction,instruction);
4112   else
4113    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4114   }
4115 }
4116
4117
4118 // CFC1
4119 // CTC1
4120 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4121 "c%s<X>c1 r<RT>, f<FS>"
4122 *mipsI:
4123 *mipsII:
4124 *mipsIII:
4125 {
4126   if (X)
4127     {
4128       if (FS == 0)
4129         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4130       else if (FS == 31)
4131         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4132       /* else NOP */
4133       PENDING_FILL(COCIDX,0); /* special case */
4134     }
4135   else
4136     { /* control from */
4137       if (FS == 0)
4138         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4139       else if (FS == 31)
4140         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4141       /* else NOP */
4142     }
4143 }
4144 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4145 "c%s<X>c1 r<RT>, f<FS>"
4146 *mipsIV:
4147 *vr5000:
4148 // start-sanitize-vr4320
4149 *vr4320:
4150 // end-sanitize-vr4320
4151 // start-sanitize-vr5400
4152 *vr5400:
4153 // end-sanitize-vr5400
4154 // start-sanitize-r5900
4155 *r5900:
4156 // end-sanitize-r5900
4157 *r3900:
4158 // start-sanitize-tx19
4159 *tx19:
4160 // end-sanitize-tx19
4161 {
4162   if (X)
4163     {
4164       /* control to */
4165       TRACE_ALU_INPUT1 (GPR[RT]);
4166       if (FS == 0)
4167         {
4168           FCR0 = VL4_8(GPR[RT]);
4169           TRACE_ALU_RESULT (FCR0);
4170         }
4171       else if (FS == 31)
4172         {
4173           FCR31 = VL4_8(GPR[RT]);
4174           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4175           TRACE_ALU_RESULT (FCR31);
4176         }
4177       else
4178         {
4179           TRACE_ALU_RESULT0 ();
4180         }
4181       /* else NOP */
4182     }
4183   else
4184     { /* control from */
4185       if (FS == 0)
4186         {
4187           TRACE_ALU_INPUT1 (FCR0);
4188           GPR[RT] = SIGNEXTEND (FCR0, 32);
4189         }
4190       else if (FS == 31)
4191         {
4192           TRACE_ALU_INPUT1 (FCR31);
4193           GPR[RT] = SIGNEXTEND (FCR31, 32);
4194         }
4195       TRACE_ALU_RESULT (GPR[RT]);
4196       /* else NOP */
4197     }
4198 }
4199
4200
4201 //
4202 // FIXME: Does not correctly differentiate between mips*
4203 //
4204 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4205 "cvt.d.%s<FMT> f<FD>, f<FS>"
4206 *mipsI,mipsII,mipsIII,mipsIV:
4207 *vr5000:
4208 // start-sanitize-vr4320
4209 *vr4320:
4210 // end-sanitize-vr4320
4211 // start-sanitize-vr5400
4212 *vr5400:
4213 // end-sanitize-vr5400
4214 *r3900:
4215 // start-sanitize-tx19
4216 *tx19:
4217 // end-sanitize-tx19
4218 {
4219   unsigned32 instruction = instruction_0;
4220   int destreg = ((instruction >> 6) & 0x0000001F);
4221   int fs = ((instruction >> 11) & 0x0000001F);
4222   int format = ((instruction >> 21) & 0x00000007);
4223   {
4224     if ((format == fmt_double) | 0)
4225       SignalException(ReservedInstruction,instruction);
4226     else
4227       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4228   }
4229 }
4230
4231
4232 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4233 "cvt.l.%s<FMT> f<FD>, f<FS>"
4234 *mipsIII:
4235 *mipsIV:
4236 *vr5000:
4237 // start-sanitize-vr4320
4238 *vr4320:
4239 // end-sanitize-vr4320
4240 // start-sanitize-vr5400
4241 *vr5400:
4242 // end-sanitize-vr5400
4243 *r3900:
4244 // start-sanitize-tx19
4245 *tx19:
4246 // end-sanitize-tx19
4247 {
4248   unsigned32 instruction = instruction_0;
4249   int destreg = ((instruction >> 6) & 0x0000001F);
4250   int fs = ((instruction >> 11) & 0x0000001F);
4251   int format = ((instruction >> 21) & 0x00000007);
4252   {
4253     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4254       SignalException(ReservedInstruction,instruction);
4255     else
4256       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4257   }
4258 }
4259
4260
4261 //
4262 // FIXME: Does not correctly differentiate between mips*
4263 //
4264 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4265 "cvt.s.%s<FMT> f<FD>, f<FS>"
4266 *mipsI,mipsII,mipsIII,mipsIV:
4267 *vr5000:
4268 // start-sanitize-vr4320
4269 *vr4320:
4270 // end-sanitize-vr4320
4271 // start-sanitize-vr5400
4272 *vr5400:
4273 // end-sanitize-vr5400
4274 *r3900:
4275 // start-sanitize-tx19
4276 *tx19:
4277 // end-sanitize-tx19
4278 {
4279   unsigned32 instruction = instruction_0;
4280   int destreg = ((instruction >> 6) & 0x0000001F);
4281   int fs = ((instruction >> 11) & 0x0000001F);
4282   int format = ((instruction >> 21) & 0x00000007);
4283   {
4284     if ((format == fmt_single) | 0)
4285       SignalException(ReservedInstruction,instruction);
4286     else
4287       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4288   }
4289 }
4290
4291
4292 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4293 "cvt.w.%s<FMT> f<FD>, f<FS>"
4294 *mipsI,mipsII,mipsIII,mipsIV:
4295 *vr5000:
4296 // start-sanitize-vr4320
4297 *vr4320:
4298 // end-sanitize-vr4320
4299 // start-sanitize-vr5400
4300 *vr5400:
4301 // end-sanitize-vr5400
4302 *r3900:
4303 // start-sanitize-tx19
4304 *tx19:
4305 // end-sanitize-tx19
4306 {
4307   unsigned32 instruction = instruction_0;
4308   int destreg = ((instruction >> 6) & 0x0000001F);
4309   int fs = ((instruction >> 11) & 0x0000001F);
4310   int format = ((instruction >> 21) & 0x00000007);
4311   {
4312     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4313       SignalException(ReservedInstruction,instruction);
4314     else
4315       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4316   }
4317 }
4318
4319
4320 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4321 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4322 *mipsI,mipsII,mipsIII,mipsIV:
4323 *vr5000:
4324 // start-sanitize-vr4320
4325 *vr4320:
4326 // end-sanitize-vr4320
4327 // start-sanitize-vr5400
4328 *vr5400:
4329 // end-sanitize-vr5400
4330 *r3900:
4331 // start-sanitize-tx19
4332 *tx19:
4333 // end-sanitize-tx19
4334 {
4335   unsigned32 instruction = instruction_0;
4336   int destreg = ((instruction >> 6) & 0x0000001F);
4337   int fs = ((instruction >> 11) & 0x0000001F);
4338   int ft = ((instruction >> 16) & 0x0000001F);
4339   int format = ((instruction >> 21) & 0x00000007);
4340   {
4341     if ((format != fmt_single) && (format != fmt_double))
4342       SignalException(ReservedInstruction,instruction);
4343     else
4344       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4345   }
4346 }
4347
4348
4349 // DMFC1
4350 // DMTC1
4351 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4352 "dm%s<X>c1 r<RT>, f<FS>"
4353 *mipsIII:
4354 {
4355   if (X)
4356     {
4357       if (SizeFGR() == 64)
4358         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4359       else if ((FS & 0x1) == 0)
4360         {
4361           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4362           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4363         }
4364     }
4365   else
4366     {
4367       if (SizeFGR() == 64)
4368         PENDING_FILL(RT,FGR[FS]);
4369       else if ((FS & 0x1) == 0)
4370         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4371       else
4372         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4373     }
4374 }
4375 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4376 "dm%s<X>c1 r<RT>, f<FS>"
4377 *mipsIV:
4378 *vr5000:
4379 // start-sanitize-vr4320
4380 *vr4320:
4381 // end-sanitize-vr4320
4382 // start-sanitize-vr5400
4383 *vr5400:
4384 // end-sanitize-vr5400
4385 // start-sanitize-r5900
4386 *r5900:
4387 // end-sanitize-r5900
4388 *r3900:
4389 // start-sanitize-tx19
4390 *tx19:
4391 // end-sanitize-tx19
4392 {
4393   if (X)
4394     {
4395       if (SizeFGR() == 64)
4396         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4397       else if ((FS & 0x1) == 0)
4398         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4399     }
4400   else
4401     {
4402       if (SizeFGR() == 64)
4403         GPR[RT] = FGR[FS];
4404       else if ((FS & 0x1) == 0)
4405         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4406       else
4407         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4408     }
4409 }
4410
4411
4412 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4413 "floor.l.%s<FMT> f<FD>, f<FS>"
4414 *mipsIII:
4415 *mipsIV:
4416 *vr5000:
4417 // start-sanitize-vr4320
4418 *vr4320:
4419 // end-sanitize-vr4320
4420 // start-sanitize-vr5400
4421 *vr5400:
4422 // end-sanitize-vr5400
4423 // start-sanitize-r5900
4424 *r5900:
4425 // end-sanitize-r5900
4426 *r3900:
4427 // start-sanitize-tx19
4428 *tx19:
4429 // end-sanitize-tx19
4430 {
4431   unsigned32 instruction = instruction_0;
4432   int destreg = ((instruction >> 6) & 0x0000001F);
4433   int fs = ((instruction >> 11) & 0x0000001F);
4434   int format = ((instruction >> 21) & 0x00000007);
4435   {
4436     if ((format != fmt_single) && (format != fmt_double))
4437       SignalException(ReservedInstruction,instruction);
4438     else
4439       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4440   }
4441 }
4442
4443
4444 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4445 "floor.w.%s<FMT> f<FD>, f<FS>"
4446 *mipsII:
4447 *mipsIII:
4448 *mipsIV:
4449 *vr5000:
4450 // start-sanitize-vr4320
4451 *vr4320:
4452 // end-sanitize-vr4320
4453 // start-sanitize-vr5400
4454 *vr5400:
4455 // end-sanitize-vr5400
4456 // start-sanitize-r5900
4457 *r5900:
4458 // end-sanitize-r5900
4459 *r3900:
4460 // start-sanitize-tx19
4461 *tx19:
4462 // end-sanitize-tx19
4463 {
4464   unsigned32 instruction = instruction_0;
4465   int destreg = ((instruction >> 6) & 0x0000001F);
4466   int fs = ((instruction >> 11) & 0x0000001F);
4467   int format = ((instruction >> 21) & 0x00000007);
4468   {
4469     if ((format != fmt_single) && (format != fmt_double))
4470       SignalException(ReservedInstruction,instruction);
4471     else
4472       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4473   }
4474 }
4475
4476
4477 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4478 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4479 *mipsII:
4480 *mipsIII:
4481 *mipsIV:
4482 *vr5000:
4483 // start-sanitize-vr4320
4484 *vr4320:
4485 // end-sanitize-vr4320
4486 // start-sanitize-vr5400
4487 *vr5400:
4488 // end-sanitize-vr5400
4489 *r3900:
4490 // start-sanitize-tx19
4491 *tx19:
4492 // end-sanitize-tx19
4493 {
4494   address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
4495   address_word paddr;
4496   int uncached;
4497   if ((vaddr & 7) != 0)
4498     SignalExceptionAddressLoad();
4499   else
4500     {
4501       unsigned64 memval;
4502       AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
4503       LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4504       COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
4505     }
4506 }
4507
4508
4509 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4510 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4511 *mipsIV:
4512 *vr5000:
4513 // start-sanitize-vr4320
4514 *vr4320:
4515 // end-sanitize-vr4320
4516 // start-sanitize-vr5400
4517 *vr5400:
4518 // end-sanitize-vr5400
4519 {
4520   unsigned32 instruction = instruction_0;
4521   int destreg = ((instruction >> 6) & 0x0000001F);
4522   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4523   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4524   {
4525     address_word vaddr = ((unsigned64)op1 + op2);
4526     address_word paddr;
4527     int uncached;
4528     if ((vaddr & 7) != 0)
4529       SignalExceptionAddressLoad();
4530     else
4531       {
4532         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4533           {
4534             unsigned64 memval = 0;
4535             unsigned64 memval1 = 0;
4536             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
4537             COP_LD(1,destreg,memval);;
4538           }
4539       }
4540   }
4541 }
4542
4543
4544
4545 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4546 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4547 *mipsI,mipsII,mipsIII,mipsIV:
4548 *vr5000:
4549 // start-sanitize-vr4320
4550 *vr4320:
4551 // end-sanitize-vr4320
4552 // start-sanitize-vr5400
4553 *vr5400:
4554 // end-sanitize-vr5400
4555 // start-sanitize-r5900
4556 *r5900:
4557 // end-sanitize-r5900
4558 *r3900:
4559 // start-sanitize-tx19
4560 *tx19:
4561 // end-sanitize-tx19
4562 {
4563   unsigned32 instruction = instruction_0;
4564   signed_word offset = EXTEND16 (OFFSET);
4565   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
4566   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
4567   {
4568     address_word vaddr = ((uword64)op1 + offset);
4569     address_word paddr;
4570     int uncached;
4571     if ((vaddr & 3) != 0)
4572       SignalExceptionAddressLoad();
4573     else
4574       {
4575         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4576           {
4577             uword64 memval = 0;
4578             uword64 memval1 = 0;
4579             uword64 mask = 0x7;
4580             unsigned int shift = 2;
4581             unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
4582             unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
4583             unsigned int byte UNUSED;
4584             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4585             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4586             byte = ((vaddr & mask) ^ (bigend << shift));
4587             COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4588           }
4589       }
4590   }
4591 }
4592
4593
4594 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4595 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4596 *mipsIV:
4597 *vr5000:
4598 // start-sanitize-vr4320
4599 *vr4320:
4600 // end-sanitize-vr4320
4601 // start-sanitize-vr5400
4602 *vr5400:
4603 // end-sanitize-vr5400
4604 {
4605   unsigned32 instruction = instruction_0;
4606   int destreg = ((instruction >> 6) & 0x0000001F);
4607   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
4608   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
4609   {
4610    address_word vaddr = ((unsigned64)op1 + op2);
4611    address_word paddr;
4612    int uncached;
4613    if ((vaddr & 3) != 0)
4614     SignalExceptionAddressLoad();
4615    else
4616    {
4617     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4618     {
4619      unsigned64 memval = 0;
4620      unsigned64 memval1 = 0;
4621      unsigned64 mask = 0x7;
4622      unsigned int shift = 2;
4623      unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
4624      unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
4625      unsigned int byte;
4626      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
4627      LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
4628      byte = ((vaddr & mask) ^ (bigend << shift));
4629      COP_LW(1,destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
4630     }
4631    }
4632   }
4633 }
4634
4635
4636
4637 //
4638 // FIXME: Not correct for mips*
4639 //
4640 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4641 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4642 *mipsIV:
4643 *vr5000:
4644 // start-sanitize-vr4320
4645 *vr4320:
4646 // end-sanitize-vr4320
4647 // start-sanitize-vr5400
4648 *vr5400:
4649 // end-sanitize-vr5400
4650 {
4651   unsigned32 instruction = instruction_0;
4652   int destreg = ((instruction >> 6) & 0x0000001F);
4653   int fs = ((instruction >> 11) & 0x0000001F);
4654   int ft = ((instruction >> 16) & 0x0000001F);
4655   int fr = ((instruction >> 21) & 0x0000001F);
4656   {
4657     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4658   }
4659 }
4660
4661
4662 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4663 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4664 *mipsIV:
4665 *vr5000:
4666 // start-sanitize-vr4320
4667 *vr4320:
4668 // end-sanitize-vr4320
4669 // start-sanitize-vr5400
4670 *vr5400:
4671 // end-sanitize-vr5400
4672 {
4673   unsigned32 instruction = instruction_0;
4674   int destreg = ((instruction >> 6) & 0x0000001F);
4675   int fs = ((instruction >> 11) & 0x0000001F);
4676   int ft = ((instruction >> 16) & 0x0000001F);
4677   int fr = ((instruction >> 21) & 0x0000001F);
4678   {
4679     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4680   }
4681 }
4682
4683
4684 // MFC1
4685 // MTC1
4686 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4687 "m%s<X>c1 r<RT>, f<FS>"
4688 *mipsI:
4689 *mipsII:
4690 *mipsIII:
4691 {
4692   if (X)
4693     { /*MTC1*/
4694       if (SizeFGR() == 64)
4695         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4696       else
4697         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4698     }
4699   else /*MFC1*/
4700     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4701 }
4702 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4703 "m%s<X>c1 r<RT>, f<FS>"
4704 *mipsIV:
4705 *vr5000:
4706 // start-sanitize-vr4320
4707 *vr4320:
4708 // end-sanitize-vr4320
4709 // start-sanitize-vr5400
4710 *vr5400:
4711 // end-sanitize-vr5400
4712 *r3900:
4713 // start-sanitize-tx19
4714 *tx19:
4715 // end-sanitize-tx19
4716 {
4717   if (X)
4718     /*MTC1*/
4719     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4720   else /*MFC1*/
4721     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4722 }
4723
4724
4725 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4726 "mov.%s<FMT> f<FD>, f<FS>"
4727 *mipsI,mipsII,mipsIII,mipsIV:
4728 *vr5000:
4729 // start-sanitize-vr4320
4730 *vr4320:
4731 // end-sanitize-vr4320
4732 // start-sanitize-vr5400
4733 *vr5400:
4734 // end-sanitize-vr5400
4735 *r3900:
4736 // start-sanitize-tx19
4737 *tx19:
4738 // end-sanitize-tx19
4739 {
4740   unsigned32 instruction = instruction_0;
4741   int destreg = ((instruction >> 6) & 0x0000001F);
4742   int fs = ((instruction >> 11) & 0x0000001F);
4743   int format = ((instruction >> 21) & 0x00000007);
4744   {
4745     StoreFPR(destreg,format,ValueFPR(fs,format));
4746   }
4747 }
4748
4749
4750 // MOVF
4751 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4752 "mov%s<TF> r<RD>, r<RS>, <CC>"
4753 *mipsIV:
4754 *vr5000:
4755 // start-sanitize-vr4320
4756 *vr4320:
4757 // end-sanitize-vr4320
4758 // start-sanitize-vr5400
4759 *vr5400:
4760 // end-sanitize-vr5400
4761 // start-sanitize-r5900
4762 *r5900:
4763 // end-sanitize-r5900
4764 {
4765   if (GETFCC(CC) == TF)
4766     GPR[RD] = GPR[RS];
4767 }
4768
4769
4770 // MOVF.fmt
4771 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4772 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4773 *mipsIV:
4774 *vr5000:
4775 // start-sanitize-vr4320
4776 *vr4320:
4777 // end-sanitize-vr4320
4778 // start-sanitize-vr5400
4779 *vr5400:
4780 // end-sanitize-vr5400
4781 // start-sanitize-r5900
4782 *r5900:
4783 // end-sanitize-r5900
4784 {
4785   unsigned32 instruction = instruction_0;
4786   int format = ((instruction >> 21) & 0x00000007);
4787   {
4788    if (GETFCC(CC) == TF)
4789      StoreFPR (FD, format, ValueFPR (FS, format));
4790    else
4791      StoreFPR (FD, format, ValueFPR (FD, format));
4792   }
4793 }
4794
4795
4796 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4797 *mipsIV:
4798 *vr5000:
4799 // start-sanitize-vr4320
4800 *vr4320:
4801 // end-sanitize-vr4320
4802 // start-sanitize-vr5400
4803 *vr5400:
4804 // end-sanitize-vr5400
4805 // start-sanitize-r5900
4806 *r5900:
4807 // end-sanitize-r5900
4808 {
4809   unsigned32 instruction = instruction_0;
4810   int destreg = ((instruction >> 6) & 0x0000001F);
4811   int fs = ((instruction >> 11) & 0x0000001F);
4812   int format = ((instruction >> 21) & 0x00000007);
4813   {
4814     StoreFPR(destreg,format,ValueFPR(fs,format));
4815   }
4816 }
4817
4818
4819 // MOVT see MOVtf
4820
4821
4822 // MOVT.fmt see MOVtf.fmt
4823
4824
4825
4826 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
4827 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4828 *mipsIV:
4829 *vr5000:
4830 // start-sanitize-vr4320
4831 *vr4320:
4832 // end-sanitize-vr4320
4833 // start-sanitize-vr5400
4834 *vr5400:
4835 // end-sanitize-vr5400
4836 // start-sanitize-r5900
4837 *r5900:
4838 // end-sanitize-r5900
4839 {
4840   unsigned32 instruction = instruction_0;
4841   int destreg = ((instruction >> 6) & 0x0000001F);
4842   int fs = ((instruction >> 11) & 0x0000001F);
4843   int format = ((instruction >> 21) & 0x00000007);
4844   {
4845    StoreFPR(destreg,format,ValueFPR(fs,format));
4846   }
4847 }
4848
4849
4850 // MSUB.fmt
4851 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
4852 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4853 *mipsIV:
4854 *vr5000:
4855 // start-sanitize-vr4320
4856 *vr4320:
4857 // end-sanitize-vr4320
4858 // start-sanitize-vr5400
4859 *vr5400:
4860 // end-sanitize-vr5400
4861 // start-sanitize-r5900
4862 *r5900:
4863 // end-sanitize-r5900
4864 {
4865   unsigned32 instruction = instruction_0;
4866   int destreg = ((instruction >> 6) & 0x0000001F);
4867   int fs = ((instruction >> 11) & 0x0000001F);
4868   int ft = ((instruction >> 16) & 0x0000001F);
4869   int fr = ((instruction >> 21) & 0x0000001F);
4870   {
4871     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4872   }
4873 }
4874
4875
4876 // MSUB.fmt
4877 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
4878 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4879 *mipsIV:
4880 *vr5000:
4881 // start-sanitize-vr4320
4882 *vr4320:
4883 // end-sanitize-vr4320
4884 // start-sanitize-vr5400
4885 *vr5400:
4886 // end-sanitize-vr5400
4887 // start-sanitize-r5900
4888 *r5900:
4889 // end-sanitize-r5900
4890 {
4891   unsigned32 instruction = instruction_0;
4892   int destreg = ((instruction >> 6) & 0x0000001F);
4893   int fs = ((instruction >> 11) & 0x0000001F);
4894   int ft = ((instruction >> 16) & 0x0000001F);
4895   int fr = ((instruction >> 21) & 0x0000001F);
4896   {
4897    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4898   }
4899 }
4900
4901
4902 // MTC1 see MxC1
4903
4904
4905 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
4906 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4907 *mipsI,mipsII,mipsIII,mipsIV:
4908 *vr5000:
4909 // start-sanitize-vr4320
4910 *vr4320:
4911 // end-sanitize-vr4320
4912 // start-sanitize-vr5400
4913 *vr5400:
4914 // end-sanitize-vr5400
4915 *r3900:
4916 // start-sanitize-tx19
4917 *tx19:
4918 // end-sanitize-tx19
4919 {
4920   unsigned32 instruction = instruction_0;
4921   int destreg = ((instruction >> 6) & 0x0000001F);
4922   int fs = ((instruction >> 11) & 0x0000001F);
4923   int ft = ((instruction >> 16) & 0x0000001F);
4924   int format = ((instruction >> 21) & 0x00000007);
4925   {
4926     if ((format != fmt_single) && (format != fmt_double))
4927       SignalException(ReservedInstruction,instruction);
4928     else
4929       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
4930   }
4931 }
4932
4933
4934 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
4935 "neg.%s<FMT> f<FD>, f<FS>"
4936 *mipsI,mipsII,mipsIII,mipsIV:
4937 *vr5000:
4938 // start-sanitize-vr4320
4939 *vr4320:
4940 // end-sanitize-vr4320
4941 // start-sanitize-vr5400
4942 *vr5400:
4943 // end-sanitize-vr5400
4944 *r3900:
4945 // start-sanitize-tx19
4946 *tx19:
4947 // end-sanitize-tx19
4948 {
4949   unsigned32 instruction = instruction_0;
4950   int destreg = ((instruction >> 6) & 0x0000001F);
4951   int fs = ((instruction >> 11) & 0x0000001F);
4952   int format = ((instruction >> 21) & 0x00000007);
4953   {
4954     if ((format != fmt_single) && (format != fmt_double))
4955       SignalException(ReservedInstruction,instruction);
4956     else
4957       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
4958   }
4959 }
4960
4961
4962 // NMADD.fmt
4963 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
4964 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4965 *mipsIV:
4966 *vr5000:
4967 // start-sanitize-vr4320
4968 *vr4320:
4969 // end-sanitize-vr4320
4970 // start-sanitize-vr5400
4971 *vr5400:
4972 // end-sanitize-vr5400
4973 {
4974   unsigned32 instruction = instruction_0;
4975   int destreg = ((instruction >> 6) & 0x0000001F);
4976   int fs = ((instruction >> 11) & 0x0000001F);
4977   int ft = ((instruction >> 16) & 0x0000001F);
4978   int fr = ((instruction >> 21) & 0x0000001F);
4979   {
4980    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
4981   }
4982 }
4983
4984
4985 // NMADD.fmt
4986 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
4987 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4988 *mipsIV:
4989 *vr5000:
4990 // start-sanitize-vr4320
4991 *vr4320:
4992 // end-sanitize-vr4320
4993 // start-sanitize-vr5400
4994 *vr5400:
4995 // end-sanitize-vr5400
4996 {
4997   unsigned32 instruction = instruction_0;
4998   int destreg = ((instruction >> 6) & 0x0000001F);
4999   int fs = ((instruction >> 11) & 0x0000001F);
5000   int ft = ((instruction >> 16) & 0x0000001F);
5001   int fr = ((instruction >> 21) & 0x0000001F);
5002   {
5003    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5004   }
5005 }
5006
5007
5008 // NMSUB.fmt
5009 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5010 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5011 *mipsIV:
5012 *vr5000:
5013 // start-sanitize-vr4320
5014 *vr4320:
5015 // end-sanitize-vr4320
5016 // start-sanitize-vr5400
5017 *vr5400:
5018 // end-sanitize-vr5400
5019 {
5020   unsigned32 instruction = instruction_0;
5021   int destreg = ((instruction >> 6) & 0x0000001F);
5022   int fs = ((instruction >> 11) & 0x0000001F);
5023   int ft = ((instruction >> 16) & 0x0000001F);
5024   int fr = ((instruction >> 21) & 0x0000001F);
5025   {
5026    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5027   }
5028 }
5029
5030
5031 // NMSUB.fmt
5032 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5033 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5034 *mipsIV:
5035 *vr5000:
5036 // start-sanitize-vr4320
5037 *vr4320:
5038 // end-sanitize-vr4320
5039 // start-sanitize-vr5400
5040 *vr5400:
5041 // end-sanitize-vr5400
5042 {
5043   unsigned32 instruction = instruction_0;
5044   int destreg = ((instruction >> 6) & 0x0000001F);
5045   int fs = ((instruction >> 11) & 0x0000001F);
5046   int ft = ((instruction >> 16) & 0x0000001F);
5047   int fr = ((instruction >> 21) & 0x0000001F);
5048   {
5049     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5050   }
5051 }
5052
5053
5054 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5055 "prefx <HINT>, r<INDEX>(r<BASE>)"
5056 *mipsIV:
5057 *vr5000:
5058 // start-sanitize-vr4320
5059 *vr4320:
5060 // end-sanitize-vr4320
5061 // start-sanitize-vr5400
5062 *vr5400:
5063 // end-sanitize-vr5400
5064 {
5065   unsigned32 instruction = instruction_0;
5066   int fs = ((instruction >> 11) & 0x0000001F);
5067   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5068   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5069   {
5070     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5071     address_word paddr;
5072     int uncached;
5073     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5074       Prefetch(uncached,paddr,vaddr,isDATA,fs);
5075   }
5076 }
5077
5078 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5079 *mipsIV:
5080 "recip.%s<FMT> f<FD>, f<FS>"
5081 *vr5000:
5082 // start-sanitize-vr4320
5083 *vr4320:
5084 // end-sanitize-vr4320
5085 // start-sanitize-vr5400
5086 *vr5400:
5087 // end-sanitize-vr5400
5088 {
5089   unsigned32 instruction = instruction_0;
5090   int destreg = ((instruction >> 6) & 0x0000001F);
5091   int fs = ((instruction >> 11) & 0x0000001F);
5092   int format = ((instruction >> 21) & 0x00000007);
5093   {
5094   if ((format != fmt_single) && (format != fmt_double))
5095    SignalException(ReservedInstruction,instruction);
5096   else
5097    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5098   }
5099 }
5100
5101
5102 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5103 "round.l.%s<FMT> f<FD>, f<FS>"
5104 *mipsIII:
5105 *mipsIV:
5106 *vr5000:
5107 // start-sanitize-vr4320
5108 *vr4320:
5109 // end-sanitize-vr4320
5110 // start-sanitize-vr5400
5111 *vr5400:
5112 // end-sanitize-vr5400
5113 // start-sanitize-r5900
5114 *r5900:
5115 // end-sanitize-r5900
5116 *r3900:
5117 // start-sanitize-tx19
5118 *tx19:
5119 // end-sanitize-tx19
5120 {
5121   unsigned32 instruction = instruction_0;
5122   int destreg = ((instruction >> 6) & 0x0000001F);
5123   int fs = ((instruction >> 11) & 0x0000001F);
5124   int format = ((instruction >> 21) & 0x00000007);
5125   {
5126     if ((format != fmt_single) && (format != fmt_double))
5127       SignalException(ReservedInstruction,instruction);
5128     else
5129       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5130   }
5131 }
5132
5133
5134 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5135 "round.w.%s<FMT> f<FD>, f<FS>"
5136 *mipsII:
5137 *mipsIII:
5138 *mipsIV:
5139 *vr5000:
5140 // start-sanitize-vr4320
5141 *vr4320:
5142 // end-sanitize-vr4320
5143 // start-sanitize-vr5400
5144 *vr5400:
5145 // end-sanitize-vr5400
5146 // start-sanitize-r5900
5147 *r5900:
5148 // end-sanitize-r5900
5149 *r3900:
5150 // start-sanitize-tx19
5151 *tx19:
5152 // end-sanitize-tx19
5153 {
5154   unsigned32 instruction = instruction_0;
5155   int destreg = ((instruction >> 6) & 0x0000001F);
5156   int fs = ((instruction >> 11) & 0x0000001F);
5157   int format = ((instruction >> 21) & 0x00000007);
5158   {
5159   if ((format != fmt_single) && (format != fmt_double))
5160    SignalException(ReservedInstruction,instruction);
5161   else
5162    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5163   }
5164 }
5165
5166
5167 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5168 *mipsIV:
5169 "rsqrt.%s<FMT> f<FD>, f<FS>"
5170 *vr5000:
5171 // start-sanitize-vr4320
5172 *vr4320:
5173 // end-sanitize-vr4320
5174 // start-sanitize-vr5400
5175 *vr5400:
5176 // end-sanitize-vr5400
5177 {
5178   unsigned32 instruction = instruction_0;
5179   int destreg = ((instruction >> 6) & 0x0000001F);
5180   int fs = ((instruction >> 11) & 0x0000001F);
5181   int format = ((instruction >> 21) & 0x00000007);
5182   {
5183   if ((format != fmt_single) && (format != fmt_double))
5184    SignalException(ReservedInstruction,instruction);
5185   else
5186    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5187   }
5188 }
5189
5190
5191 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5192 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5193 *mipsII:
5194 *mipsIII:
5195 *mipsIV:
5196 *vr5000:
5197 // start-sanitize-vr4320
5198 *vr4320:
5199 // end-sanitize-vr4320
5200 // start-sanitize-vr5400
5201 *vr5400:
5202 // end-sanitize-vr5400
5203 *r3900:
5204 // start-sanitize-tx19
5205 *tx19:
5206 // end-sanitize-tx19
5207 {
5208   address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
5209   int uncached;
5210   if ((vaddr & 7) != 0)
5211     SignalExceptionAddressStore();
5212   else
5213     {
5214       address_word paddr;
5215       unsigned64 memval;
5216       AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
5217       memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
5218       StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
5219     }
5220 }
5221
5222
5223 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
5224 *mipsIV:
5225 *vr5000:
5226 // start-sanitize-vr4320
5227 *vr4320:
5228 // end-sanitize-vr4320
5229 // start-sanitize-vr5400
5230 *vr5400:
5231 // end-sanitize-vr5400
5232 {
5233   unsigned32 instruction = instruction_0;
5234   int fs = ((instruction >> 11) & 0x0000001F);
5235   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5236   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5237   {
5238     address_word vaddr = ((unsigned64)op1 + op2);
5239     address_word paddr;
5240     int uncached;
5241     if ((vaddr & 7) != 0)
5242       SignalExceptionAddressStore();
5243     else
5244       {
5245         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5246           {
5247             unsigned64 memval = 0;
5248             unsigned64 memval1 = 0;
5249             memval = (unsigned64)COP_SD(1,fs);
5250             {
5251               StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
5252             }
5253           }
5254       }
5255   }
5256 }
5257
5258
5259 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5260 "sqrt.%s<FMT> f<FD>, f<FS>"
5261 *mipsII:
5262 *mipsIII:
5263 *mipsIV:
5264 *vr5000:
5265 // start-sanitize-vr4320
5266 *vr4320:
5267 // end-sanitize-vr4320
5268 // start-sanitize-vr5400
5269 *vr5400:
5270 // end-sanitize-vr5400
5271 *r3900:
5272 // start-sanitize-tx19
5273 *tx19:
5274 // end-sanitize-tx19
5275 {
5276   unsigned32 instruction = instruction_0;
5277   int destreg = ((instruction >> 6) & 0x0000001F);
5278   int fs = ((instruction >> 11) & 0x0000001F);
5279   int format = ((instruction >> 21) & 0x00000007);
5280   {
5281     if ((format != fmt_single) && (format != fmt_double))
5282       SignalException(ReservedInstruction,instruction);
5283     else
5284       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5285   }
5286 }
5287
5288
5289 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5290 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5291 *mipsI,mipsII,mipsIII,mipsIV:
5292 *vr5000:
5293 // start-sanitize-vr4320
5294 *vr4320:
5295 // end-sanitize-vr4320
5296 // start-sanitize-vr5400
5297 *vr5400:
5298 // end-sanitize-vr5400
5299 *r3900:
5300 // start-sanitize-tx19
5301 *tx19:
5302 // end-sanitize-tx19
5303 {
5304   unsigned32 instruction = instruction_0;
5305   int destreg = ((instruction >> 6) & 0x0000001F);
5306   int fs = ((instruction >> 11) & 0x0000001F);
5307   int ft = ((instruction >> 16) & 0x0000001F);
5308   int format = ((instruction >> 21) & 0x00000007);
5309   {
5310     if ((format != fmt_single) && (format != fmt_double))
5311       SignalException(ReservedInstruction,instruction);
5312     else
5313       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5314   }
5315 }
5316
5317
5318
5319 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5320 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5321 *mipsI,mipsII,mipsIII,mipsIV:
5322 *vr5000:
5323 // start-sanitize-vr4320
5324 *vr4320:
5325 // end-sanitize-vr4320
5326 // start-sanitize-vr5400
5327 *vr5400:
5328 // end-sanitize-vr5400
5329 // start-sanitize-r5900
5330 *r5900:
5331 // end-sanitize-r5900
5332 *r3900:
5333 // start-sanitize-tx19
5334 *tx19:
5335 // end-sanitize-tx19
5336 {
5337   unsigned32 instruction = instruction_0;
5338   signed_word offset = EXTEND16 (OFFSET);
5339   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5340   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5341   {
5342     address_word vaddr = ((uword64)op1 + offset);
5343     address_word paddr;
5344     int uncached;
5345     if ((vaddr & 3) != 0)
5346       SignalExceptionAddressStore();
5347     else
5348       {
5349         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5350           {
5351             uword64 memval = 0;
5352             uword64 memval1 = 0;
5353             uword64 mask = 0x7;
5354             unsigned int byte;
5355             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5356             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5357             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5358             {
5359               StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5360             }
5361           }
5362       }
5363   }
5364 }
5365
5366
5367 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5368 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5369 *mipsIV:
5370 *vr5000:
5371 // start-sanitize-vr4320
5372 *vr4320:
5373 // end-sanitize-vr4320
5374 // start-sanitize-vr5400
5375 *vr5400:
5376 // end-sanitize-vr5400
5377 {
5378   unsigned32 instruction = instruction_0;
5379   int fs = ((instruction >> 11) & 0x0000001F);
5380   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5381   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5382   {
5383    address_word vaddr = ((unsigned64)op1 + op2);
5384    address_word paddr;
5385    int uncached;
5386    if ((vaddr & 3) != 0)
5387     SignalExceptionAddressStore();
5388    else
5389    {
5390     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5391     {
5392      unsigned64 memval = 0;
5393      unsigned64 memval1 = 0;
5394      unsigned64 mask = 0x7;
5395      unsigned int byte;
5396      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5397      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5398      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5399       {
5400        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5401       }
5402     }
5403    }
5404   }
5405 }
5406
5407
5408 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5409 "trunc.l.%s<FMT> f<FD>, f<FS>"
5410 *mipsIII:
5411 *mipsIV:
5412 *vr5000:
5413 // start-sanitize-vr4320
5414 *vr4320:
5415 // end-sanitize-vr4320
5416 // start-sanitize-vr5400
5417 *vr5400:
5418 // end-sanitize-vr5400
5419 // start-sanitize-r5900
5420 *r5900:
5421 // end-sanitize-r5900
5422 *r3900:
5423 // start-sanitize-tx19
5424 *tx19:
5425 // end-sanitize-tx19
5426 {
5427   unsigned32 instruction = instruction_0;
5428   int destreg = ((instruction >> 6) & 0x0000001F);
5429   int fs = ((instruction >> 11) & 0x0000001F);
5430   int format = ((instruction >> 21) & 0x00000007);
5431   {
5432   if ((format != fmt_single) && (format != fmt_double))
5433    SignalException(ReservedInstruction,instruction);
5434   else
5435    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5436   }
5437 }
5438
5439
5440 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5441 "trunc.w.%s<FMT> f<FD>, f<FS>"
5442 *mipsII:
5443 *mipsIII:
5444 *mipsIV:
5445 *vr5000:
5446 // start-sanitize-vr4320
5447 *vr4320:
5448 // end-sanitize-vr4320
5449 // start-sanitize-vr5400
5450 *vr5400:
5451 // end-sanitize-vr5400
5452 // start-sanitize-r5900
5453 *r5900:
5454 // end-sanitize-r5900
5455 *r3900:
5456 // start-sanitize-tx19
5457 *tx19:
5458 // end-sanitize-tx19
5459 {
5460   unsigned32 instruction = instruction_0;
5461   int destreg = ((instruction >> 6) & 0x0000001F);
5462   int fs = ((instruction >> 11) & 0x0000001F);
5463   int format = ((instruction >> 21) & 0x00000007);
5464   {
5465   if ((format != fmt_single) && (format != fmt_double))
5466    SignalException(ReservedInstruction,instruction);
5467   else
5468    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5469   }
5470 }
5471
5472 \f
5473 //
5474 // MIPS Architecture:
5475 //
5476 //        System Control Instruction Set (COP0)
5477 //
5478
5479
5480 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5481 "bc0f <OFFSET>"
5482 *mipsI,mipsII,mipsIII,mipsIV:
5483 *vr5000:
5484 // start-sanitize-vr4320
5485 *vr4320:
5486 // end-sanitize-vr4320
5487 // start-sanitize-vr5400
5488 *vr5400:
5489 // end-sanitize-vr5400
5490 // start-sanitize-r5900
5491 *r5900:
5492 // end-sanitize-r5900
5493
5494
5495 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5496 "bc0fl <OFFSET>"
5497 *mipsI,mipsII,mipsIII,mipsIV:
5498 *vr5000:
5499 // start-sanitize-vr4320
5500 *vr4320:
5501 // end-sanitize-vr4320
5502 // start-sanitize-vr5400
5503 *vr5400:
5504 // end-sanitize-vr5400
5505 // start-sanitize-r5900
5506 *r5900:
5507 // end-sanitize-r5900
5508
5509
5510 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5511 "bc0t <OFFSET>"
5512 *mipsI,mipsII,mipsIII,mipsIV:
5513 // start-sanitize-r5900
5514 *r5900:
5515 // end-sanitize-r5900
5516
5517
5518
5519 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5520 "bc0tl <OFFSET>"
5521 *mipsI,mipsII,mipsIII,mipsIV:
5522 *vr5000:
5523 // start-sanitize-vr4320
5524 *vr4320:
5525 // end-sanitize-vr4320
5526 // start-sanitize-vr5400
5527 *vr5400:
5528 // end-sanitize-vr5400
5529 // start-sanitize-r5900
5530 *r5900:
5531 // end-sanitize-r5900
5532
5533
5534 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5535 *mipsIII:
5536 *mipsIV:
5537 *vr5000:
5538 // start-sanitize-vr4320
5539 *vr4320:
5540 // end-sanitize-vr4320
5541 // start-sanitize-vr5400
5542 *vr5400:
5543 // end-sanitize-vr5400
5544 // start-sanitize-r5900
5545 *r5900:
5546 // end-sanitize-r5900
5547 *r3900:
5548 // start-sanitize-tx19
5549 *tx19:
5550 // end-sanitize-tx19
5551 {
5552   unsigned32 instruction = instruction_0;
5553   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5554   int hint = ((instruction >> 16) & 0x0000001F);
5555   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5556   {
5557     address_word vaddr = (op1 + offset);
5558     address_word paddr;
5559     int uncached;
5560     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5561       CacheOp(hint,vaddr,paddr,instruction);
5562   }
5563 }
5564
5565
5566 010000,10000,000000000000000,111001:COP0:32::DI
5567 "di"
5568 *mipsI,mipsII,mipsIII,mipsIV:
5569 *vr5000:
5570 // start-sanitize-vr4320
5571 *vr4320:
5572 // end-sanitize-vr4320
5573 // start-sanitize-vr5400
5574 *vr5400:
5575 // end-sanitize-vr5400
5576 // start-sanitize-r5900
5577 *r5900:
5578 // end-sanitize-r5900
5579
5580
5581 010000,10000,000000000000000,111000:COP0:32::EI
5582 "ei"
5583 *mipsI,mipsII,mipsIII,mipsIV:
5584 *vr5000:
5585 // start-sanitize-vr4320
5586 *vr4320:
5587 // end-sanitize-vr4320
5588 // start-sanitize-vr5400
5589 *vr5400:
5590 // end-sanitize-vr5400
5591 // start-sanitize-r5900
5592 *r5900:
5593 // end-sanitize-r5900
5594
5595
5596 010000,10000,000000000000000,011000:COP0:32::ERET
5597 "eret"
5598 *mipsIII:
5599 *mipsIV:
5600 *vr5000:
5601 // start-sanitize-vr4320
5602 *vr4320:
5603 // end-sanitize-vr4320
5604 // start-sanitize-vr5400
5605 *vr5400:
5606 // end-sanitize-vr5400
5607 // start-sanitize-r5900
5608 *r5900:
5609 // end-sanitize-r5900
5610
5611
5612 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5613 "mfc0 r<RT>, r<RD> # <REGX>"
5614 *mipsI,mipsII,mipsIII,mipsIV:
5615 *vr5000:
5616 // start-sanitize-vr4320
5617 *vr4320:
5618 // end-sanitize-vr4320
5619 // start-sanitize-vr5400
5620 *vr5400:
5621 // end-sanitize-vr5400
5622 // start-sanitize-r5900
5623 *r5900:
5624 // end-sanitize-r5900
5625 {
5626   DecodeCoproc (instruction_0);
5627 }
5628
5629 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5630 "mtc0 r<RT>, r<RD> # <REGX>"
5631 *mipsI,mipsII,mipsIII,mipsIV:
5632 *vr5000:
5633 // start-sanitize-vr4320
5634 *vr4320:
5635 // end-sanitize-vr4320
5636 // start-sanitize-vr5400
5637 *vr5400:
5638 // end-sanitize-vr5400
5639 // start-sanitize-r5900
5640 *r5900:
5641 // end-sanitize-r5900
5642 {
5643   DecodeCoproc (instruction_0);
5644 }
5645
5646
5647 010000,10000,000000000000000,001000:COP0:32::TLBP
5648 "tlbp"
5649 *mipsI,mipsII,mipsIII,mipsIV:
5650 *vr5000:
5651 // start-sanitize-vr4320
5652 *vr4320:
5653 // end-sanitize-vr4320
5654 // start-sanitize-vr5400
5655 *vr5400:
5656 // end-sanitize-vr5400
5657 // start-sanitize-r5900
5658 *r5900:
5659 // end-sanitize-r5900
5660
5661
5662 010000,10000,000000000000000,000001:COP0:32::TLBR
5663 "tlbr"
5664 *mipsI,mipsII,mipsIII,mipsIV:
5665 *vr5000:
5666 // start-sanitize-vr4320
5667 *vr4320:
5668 // end-sanitize-vr4320
5669 // start-sanitize-vr5400
5670 *vr5400:
5671 // end-sanitize-vr5400
5672 // start-sanitize-r5900
5673 *r5900:
5674 // end-sanitize-r5900
5675
5676
5677 010000,10000,000000000000000,000010:COP0:32::TLBWI
5678 "tlbwi"
5679 *mipsI,mipsII,mipsIII,mipsIV:
5680 *vr5000:
5681 // start-sanitize-vr4320
5682 *vr4320:
5683 // end-sanitize-vr4320
5684 // start-sanitize-vr5400
5685 *vr5400:
5686 // end-sanitize-vr5400
5687 // start-sanitize-r5900
5688 *r5900:
5689 // end-sanitize-r5900
5690
5691
5692 010000,10000,000000000000000,000110:COP0:32::TLBWR
5693 "tlbwr"
5694 *mipsI,mipsII,mipsIII,mipsIV:
5695 *vr5000:
5696 // start-sanitize-vr4320
5697 *vr4320:
5698 // end-sanitize-vr4320
5699 // start-sanitize-vr5400
5700 *vr5400:
5701 // end-sanitize-vr5400
5702 // start-sanitize-r5900
5703 *r5900:
5704 // end-sanitize-r5900
5705
5706 \f
5707 :include:16::m16.igen
5708 // start-sanitize-vr4320
5709 :include::vr4320:vr4320.igen
5710 // end-sanitize-vr4320
5711 // start-sanitize-vr5400
5712 :include::vr5400:vr5400.igen
5713 :include:64,f::mdmx.igen
5714 // end-sanitize-vr5400
5715 // start-sanitize-r5900
5716 :include::r5900:r5900.igen
5717 // end-sanitize-r5900
5718 \f
5719 // start-sanitize-cygnus-never
5720
5721 // // FIXME FIXME FIXME What is this instruction?
5722 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5723 // *mipsI:
5724 // *mipsII:
5725 // *mipsIII:
5726 // *mipsIV:
5727 // // start-sanitize-r5900
5728 // *r5900:
5729 // // end-sanitize-r5900
5730 // *r3900:
5731 // // start-sanitize-tx19
5732 // *tx19:
5733 // // end-sanitize-tx19
5734 // {
5735 //   unsigned32 instruction = instruction_0;
5736 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5737 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5738 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5739 //   {
5740 //     if (CoProcPresent(3))
5741 //       SignalException(CoProcessorUnusable);
5742 //     else
5743 //       SignalException(ReservedInstruction,instruction);
5744 //   }
5745 // }
5746
5747 // end-sanitize-cygnus-never
5748 // start-sanitize-cygnus-never
5749
5750 // // FIXME FIXME FIXME What is this?
5751 // 11100,******,00001:RR:16::SDBBP
5752 // *mips16:
5753 // {
5754 //   unsigned32 instruction = instruction_0;
5755 //   if (have_extendval)
5756 //     SignalException (ReservedInstruction, instruction);
5757 //   {
5758 //     SignalException(DebugBreakPoint,instruction);
5759 //   }
5760 // }
5761
5762 // end-sanitize-cygnus-never
5763 // start-sanitize-cygnus-never
5764
5765 // // FIXME FIXME FIXME What is this?
5766 // 000000,********************,001110:SPECIAL:32::SDBBP
5767 // *r3900:
5768 // {
5769 //   unsigned32 instruction = instruction_0;
5770 //   {
5771 //     SignalException(DebugBreakPoint,instruction);
5772 //   }
5773 // }
5774
5775 // end-sanitize-cygnus-never
5776 // start-sanitize-cygnus-never
5777
5778 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5779 // // isn't yet reconized by this simulator.
5780 // 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
5781 // *vr4100:
5782 // {
5783 //   unsigned32 instruction = instruction_0;
5784 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5785 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5786 //   {
5787 //     CHECKHILO("Multiply-Add");
5788 //     {
5789 //       unsigned64 temp = (op1 * op2);
5790 //       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
5791 //       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
5792 //       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
5793 //     }
5794 //   }
5795 // }
5796
5797 // end-sanitize-cygnus-never
5798 // start-sanitize-cygnus-never
5799
5800 // // FIXME FIXME FIXME This apparently belongs to the vr4100 which
5801 // // isn't yet reconized by this simulator.
5802 // 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
5803 // *vr4100:
5804 // {
5805 //   unsigned32 instruction = instruction_0;
5806 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5807 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5808 //   {
5809 //     CHECKHILO("Multiply-Add");
5810 //     {
5811 //       unsigned64 temp = (op1 * op2);
5812 //       LO = LO + temp;
5813 //     }
5814 //   }
5815 // }
5816
5817 // end-sanitize-cygnus-never