sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips64:mipsisa64:
  49
  50 //  Vendor ISAs:
  51 //
  52 //  Standard MIPS ISA instructions used for these models are listed here,
  53 //  as are functions needed by those standard instructions.  Instructions
  54 //  which are model-dependent and which are not in the standard MIPS ISAs
  55 //  (or which pre-date or use different encodings than the standard
  56 //  instructions) are (for the most part) in separate .igen files.
  57 :model:::vr4100:mips4100:               // vr.igen
  58 :model:::vr5000:mips5000:
  59 :model:::r3900:mips3900:                // tx.igen
  60
  61 //  MIPS Application Specific Extensions (ASEs)
  62 //
  63 //  Instructions for the ASEs are in separate .igen files.
  64 //  ASEs add instructions on to a base ISA.
  65 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  66 :model:::mdmx:mdmx:                     // mdmx.igen
  67
  68 //  Vendor Extensions
  69 //
  70 //  Instructions specific to these extensions are in separate .igen files.
  71 //  Extensions add instructions on to a base ISA.
  72 :model:::sb1:sb1:                       // sb1.igen
  73
  74
  75 // Pseudo instructions known by IGEN
  76 :internal::::illegal:
  77 {
  78   SignalException (ReservedInstruction, 0);
  79 }
  80
  81
  82 // Pseudo instructions known by interp.c
  83 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  84 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  85 "rsvd <OP>"
  86 {
  87   SignalException (ReservedInstruction, instruction_0);
  88 }
  89
  90
  91
  92 // Helper:
  93 //
  94 // Simulate a 32 bit delayslot instruction
  95 //
  96
  97 :function:::address_word:delayslot32:address_word target
  98 {
  99   instruction_word delay_insn;
 100   sim_events_slip (SD, 1);
 101   DSPC = CIA;
 102   CIA = CIA + 4; /* NOTE not mips16 */
 103   STATE |= simDELAYSLOT;
 104   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 105   ENGINE_ISSUE_PREFIX_HOOK();
 106   idecode_issue (CPU_, delay_insn, (CIA));
 107   STATE &= ~simDELAYSLOT;
 108   return target;
 109 }
 110
 111 :function:::address_word:nullify_next_insn32:
 112 {
 113   sim_events_slip (SD, 1);
 114   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 115   return CIA + 8;
 116 }
 117
 118
 119 // Helper:
 120 //
 121 // Calculate an effective address given a base and an offset.
 122 //
 123
 124 :function:::address_word:loadstore_ea:address_word base, address_word offset
 125 *mipsI:
 126 *mipsII:
 127 *mipsIII:
 128 *mipsIV:
 129 *mipsV:
 130 *mips32:
 131 *vr4100:
 132 *vr5000:
 133 *r3900:
 134 {
 135   return base + offset;
 136 }
 137
 138 :function:::address_word:loadstore_ea:address_word base, address_word offset
 139 *mips64:
 140 {
 141 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 142   /* If in user mode and UX is not set, use 32-bit compatibility effective
 143      address computations as defined in the MIPS64 Architecture for
 144      Programmers Volume III, Revision 0.95, section 4.9.  */
 145   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 146       == (ksu_user << status_KSU_shift))
 147     return (address_word)((signed32)base + (signed32)offset);
 148 #endif
 149   return base + offset;
 150 }
 151
 152
 153 // Helper:
 154 //
 155 // Check that a 32-bit register value is properly sign-extended.
 156 // (See NotWordValue in ISA spec.)
 157 //
 158
 159 :function:::int:not_word_value:unsigned_word value
 160 *mipsI:
 161 *mipsII:
 162 *mipsIII:
 163 *mipsIV:
 164 *mipsV:
 165 *vr4100:
 166 *vr5000:
 167 *r3900:
 168 {
 169   /* For historical simulator compatibility (until documentation is
 170      found that makes these operations unpredictable on some of these
 171      architectures), this check never returns true.  */
 172   return 0;
 173 }
 174
 175 :function:::int:not_word_value:unsigned_word value
 176 *mips32:
 177 {
 178   /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
 179   return 0;
 180 }
 181
 182 :function:::int:not_word_value:unsigned_word value
 183 *mips64:
 184 {
 185   return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
 186 }
 187
 188
 189 // Helper:
 190 //
 191 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 192 // theoretically portable code which invokes non-portable behaviour from
 193 // running with no indication of the portability issue.
 194 // (See definition of UNPREDICTABLE in ISA spec.)
 195 //
 196
 197 :function:::void:unpredictable:
 198 *mipsI:
 199 *mipsII:
 200 *mipsIII:
 201 *mipsIV:
 202 *mipsV:
 203 *vr4100:
 204 *vr5000:
 205 *r3900:
 206 {
 207 }
 208
 209 :function:::void:unpredictable:
 210 *mips32:
 211 *mips64:
 212 {
 213   unpredictable_action (CPU, CIA);
 214 }
 215
 216
 217 // Helper:
 218 //
 219 // Check that an access to a HI/LO register meets timing requirements
 220 //
 221 // The following requirements exist:
 222 //
 223 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 224 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 225 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 226 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 227 //
 228
 229 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 230 {
 231   if (history->mf.timestamp + 3 > time)
 232     {
 233       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 234                         itable[MY_INDEX].name,
 235                         new, (long) CIA,
 236                         (long) history->mf.cia);
 237       return 0;
 238     }
 239   return 1;
 240 }
 241
 242 :function:::int:check_mt_hilo:hilo_history *history
 243 *mipsI:
 244 *mipsII:
 245 *mipsIII:
 246 *mipsIV:
 247 *mipsV:
 248 *vr4100:
 249 *vr5000:
 250 {
 251   signed64 time = sim_events_time (SD);
 252   int ok = check_mf_cycles (SD_, history, time, "MT");
 253   history->mt.timestamp = time;
 254   history->mt.cia = CIA;
 255   return ok;
 256 }
 257
 258 :function:::int:check_mt_hilo:hilo_history *history
 259 *mips32:
 260 *mips64:
 261 *r3900:
 262 {
 263   signed64 time = sim_events_time (SD);
 264   history->mt.timestamp = time;
 265   history->mt.cia = CIA;
 266   return 1;
 267 }
 268
 269
 270 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 271 *mipsI:
 272 *mipsII:
 273 *mipsIII:
 274 *mipsIV:
 275 *mipsV:
 276 *mips32:
 277 *mips64:
 278 *vr4100:
 279 *vr5000:
 280 *r3900:
 281 {
 282   signed64 time = sim_events_time (SD);
 283   int ok = 1;
 284   if (peer != NULL
 285       && peer->mt.timestamp > history->op.timestamp
 286       && history->mt.timestamp < history->op.timestamp
 287       && ! (history->mf.timestamp > history->op.timestamp
 288             && history->mf.timestamp < peer->mt.timestamp)
 289       && ! (peer->mf.timestamp > history->op.timestamp
 290             && peer->mf.timestamp < peer->mt.timestamp))
 291     {
 292       /* The peer has been written to since the last OP yet we have
 293          not */
 294       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 295                         itable[MY_INDEX].name,
 296                         (long) CIA,
 297                         (long) history->op.cia,
 298                         (long) peer->mt.cia);
 299       ok = 0;
 300     }
 301   history->mf.timestamp = time;
 302   history->mf.cia = CIA;
 303   return ok;
 304 }
 305
 306
 307
 308 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 309 *mipsI:
 310 *mipsII:
 311 *mipsIII:
 312 *mipsIV:
 313 *mipsV:
 314 *vr4100:
 315 *vr5000:
 316 {
 317   signed64 time = sim_events_time (SD);
 318   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 319             && check_mf_cycles (SD_, lo, time, "OP"));
 320   hi->op.timestamp = time;
 321   lo->op.timestamp = time;
 322   hi->op.cia = CIA;
 323   lo->op.cia = CIA;
 324   return ok;
 325 }
 326
 327 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 328 // a mf{hi,lo}
 329 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 330 *mips32:
 331 *mips64:
 332 *r3900:
 333 {
 334   /* FIXME: could record the fact that a stall occured if we want */
 335   signed64 time = sim_events_time (SD);
 336   hi->op.timestamp = time;
 337   lo->op.timestamp = time;
 338   hi->op.cia = CIA;
 339   lo->op.cia = CIA;
 340   return 1;
 341 }
 342
 343
 344 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 345 *mipsI:
 346 *mipsII:
 347 *mipsIII:
 348 *mipsIV:
 349 *mipsV:
 350 *mips32:
 351 *mips64:
 352 *vr4100:
 353 *vr5000:
 354 *r3900:
 355 {
 356   signed64 time = sim_events_time (SD);
 357   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 358             && check_mf_cycles (SD_, lo, time, "OP"));
 359   hi->op.timestamp = time;
 360   lo->op.timestamp = time;
 361   hi->op.cia = CIA;
 362   lo->op.cia = CIA;
 363   return ok;
 364 }
 365
 366
 367 // Helper:
 368 //
 369 // Check that the 64-bit instruction can currently be used, and signal
 370 // a ReservedInstruction exception if not.
 371 //
 372
 373 :function:::void:check_u64:instruction_word insn
 374 *mipsIII:
 375 *mipsIV:
 376 *mipsV:
 377 *vr4100:
 378 *vr5000:
 379 {
 380   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 381 }
 382
 383 :function:::void:check_u64:instruction_word insn
 384 *mips64:
 385 {
 386 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 387   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 388     SignalException (ReservedInstruction, insn);
 389 #endif
 390 }
 391
 392
 393
 394 //
 395 // MIPS Architecture:
 396 //
 397 //        CPU Instruction Set (mipsI - mipsV, mips32, mips64)
 398 //
 399
 400
 401
 402 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 403 "add r<RD>, r<RS>, r<RT>"
 404 *mipsI:
 405 *mipsII:
 406 *mipsIII:
 407 *mipsIV:
 408 *mipsV:
 409 *mips32:
 410 *mips64:
 411 *vr4100:
 412 *vr5000:
 413 *r3900:
 414 {
 415   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 416     Unpredictable ();
 417   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 418   {
 419     ALU32_BEGIN (GPR[RS]);
 420     ALU32_ADD (GPR[RT]);
 421     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 422   }
 423   TRACE_ALU_RESULT (GPR[RD]);
 424 }
 425
 426
 427
 428 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 429 "addi r<RT>, r<RS>, <IMMEDIATE>"
 430 *mipsI:
 431 *mipsII:
 432 *mipsIII:
 433 *mipsIV:
 434 *mipsV:
 435 *mips32:
 436 *mips64:
 437 *vr4100:
 438 *vr5000:
 439 *r3900:
 440 {
 441   if (NotWordValue (GPR[RS]))
 442     Unpredictable ();
 443   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 444   {
 445     ALU32_BEGIN (GPR[RS]);
 446     ALU32_ADD (EXTEND16 (IMMEDIATE));
 447     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 448   }
 449   TRACE_ALU_RESULT (GPR[RT]);
 450 }
 451
 452
 453
 454 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 455 {
 456   if (NotWordValue (GPR[rs]))
 457     Unpredictable ();
 458   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 459   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 460   TRACE_ALU_RESULT (GPR[rt]);
 461 }
 462
 463 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 464 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 465 *mipsI:
 466 *mipsII:
 467 *mipsIII:
 468 *mipsIV:
 469 *mipsV:
 470 *mips32:
 471 *mips64:
 472 *vr4100:
 473 *vr5000:
 474 *r3900:
 475 {
 476   do_addiu (SD_, RS, RT, IMMEDIATE);
 477 }
 478
 479
 480
 481 :function:::void:do_addu:int rs, int rt, int rd
 482 {
 483   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 484     Unpredictable ();
 485   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 486   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 487   TRACE_ALU_RESULT (GPR[rd]);
 488 }
 489
 490 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 491 "addu r<RD>, r<RS>, r<RT>"
 492 *mipsI:
 493 *mipsII:
 494 *mipsIII:
 495 *mipsIV:
 496 *mipsV:
 497 *mips32:
 498 *mips64:
 499 *vr4100:
 500 *vr5000:
 501 *r3900:
 502 {
 503   do_addu (SD_, RS, RT, RD);
 504 }
 505
 506
 507
 508 :function:::void:do_and:int rs, int rt, int rd
 509 {
 510   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 511   GPR[rd] = GPR[rs] & GPR[rt];
 512   TRACE_ALU_RESULT (GPR[rd]);
 513 }
 514
 515 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 516 "and r<RD>, r<RS>, r<RT>"
 517 *mipsI:
 518 *mipsII:
 519 *mipsIII:
 520 *mipsIV:
 521 *mipsV:
 522 *mips32:
 523 *mips64:
 524 *vr4100:
 525 *vr5000:
 526 *r3900:
 527 {
 528   do_and (SD_, RS, RT, RD);
 529 }
 530
 531
 532
 533 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 534 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 535 *mipsI:
 536 *mipsII:
 537 *mipsIII:
 538 *mipsIV:
 539 *mipsV:
 540 *mips32:
 541 *mips64:
 542 *vr4100:
 543 *vr5000:
 544 *r3900:
 545 {
 546   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 547   GPR[RT] = GPR[RS] & IMMEDIATE;
 548   TRACE_ALU_RESULT (GPR[RT]);
 549 }
 550
 551
 552
 553 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 554 "beq r<RS>, r<RT>, <OFFSET>"
 555 *mipsI:
 556 *mipsII:
 557 *mipsIII:
 558 *mipsIV:
 559 *mipsV:
 560 *mips32:
 561 *mips64:
 562 *vr4100:
 563 *vr5000:
 564 *r3900:
 565 {
 566   address_word offset = EXTEND16 (OFFSET) << 2;
 567   check_branch_bug ();
 568   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 569     {
 570       mark_branch_bug (NIA+offset);
 571       DELAY_SLOT (NIA + offset);
 572     }
 573 }
 574
 575
 576
 577 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 578 "beql r<RS>, r<RT>, <OFFSET>"
 579 *mipsII:
 580 *mipsIII:
 581 *mipsIV:
 582 *mipsV:
 583 *mips32:
 584 *mips64:
 585 *vr4100:
 586 *vr5000:
 587 *r3900:
 588 {
 589   address_word offset = EXTEND16 (OFFSET) << 2;
 590   check_branch_bug ();
 591   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 592     {
 593       mark_branch_bug (NIA+offset);
 594       DELAY_SLOT (NIA + offset);
 595     }
 596   else
 597     NULLIFY_NEXT_INSTRUCTION ();
 598 }
 599
 600
 601
 602 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 603 "bgez r<RS>, <OFFSET>"
 604 *mipsI:
 605 *mipsII:
 606 *mipsIII:
 607 *mipsIV:
 608 *mipsV:
 609 *mips32:
 610 *mips64:
 611 *vr4100:
 612 *vr5000:
 613 *r3900:
 614 {
 615   address_word offset = EXTEND16 (OFFSET) << 2;
 616   check_branch_bug ();
 617   if ((signed_word) GPR[RS] >= 0)
 618     {
 619       mark_branch_bug (NIA+offset);
 620       DELAY_SLOT (NIA + offset);
 621     }
 622 }
 623
 624
 625
 626 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 627 "bgezal r<RS>, <OFFSET>"
 628 *mipsI:
 629 *mipsII:
 630 *mipsIII:
 631 *mipsIV:
 632 *mipsV:
 633 *mips32:
 634 *mips64:
 635 *vr4100:
 636 *vr5000:
 637 *r3900:
 638 {
 639   address_word offset = EXTEND16 (OFFSET) << 2;
 640   check_branch_bug ();
 641   if (RS == 31)
 642     Unpredictable ();
 643   RA = (CIA + 8);
 644   if ((signed_word) GPR[RS] >= 0)
 645     {
 646       mark_branch_bug (NIA+offset);
 647       DELAY_SLOT (NIA + offset);
 648     }
 649 }
 650
 651
 652
 653 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 654 "bgezall r<RS>, <OFFSET>"
 655 *mipsII:
 656 *mipsIII:
 657 *mipsIV:
 658 *mipsV:
 659 *mips32:
 660 *mips64:
 661 *vr4100:
 662 *vr5000:
 663 *r3900:
 664 {
 665   address_word offset = EXTEND16 (OFFSET) << 2;
 666   check_branch_bug ();
 667   if (RS == 31)
 668     Unpredictable ();
 669   RA = (CIA + 8);
 670   /* NOTE: The branch occurs AFTER the next instruction has been
 671      executed */
 672   if ((signed_word) GPR[RS] >= 0)
 673     {
 674       mark_branch_bug (NIA+offset);
 675       DELAY_SLOT (NIA + offset);
 676     }
 677   else
 678     NULLIFY_NEXT_INSTRUCTION ();
 679 }
 680
 681
 682
 683 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 684 "bgezl r<RS>, <OFFSET>"
 685 *mipsII:
 686 *mipsIII:
 687 *mipsIV:
 688 *mipsV:
 689 *mips32:
 690 *mips64:
 691 *vr4100:
 692 *vr5000:
 693 *r3900:
 694 {
 695   address_word offset = EXTEND16 (OFFSET) << 2;
 696   check_branch_bug ();
 697   if ((signed_word) GPR[RS] >= 0)
 698     {
 699       mark_branch_bug (NIA+offset);
 700       DELAY_SLOT (NIA + offset);
 701     }
 702   else
 703     NULLIFY_NEXT_INSTRUCTION ();
 704 }
 705
 706
 707
 708 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 709 "bgtz r<RS>, <OFFSET>"
 710 *mipsI:
 711 *mipsII:
 712 *mipsIII:
 713 *mipsIV:
 714 *mipsV:
 715 *mips32:
 716 *mips64:
 717 *vr4100:
 718 *vr5000:
 719 *r3900:
 720 {
 721   address_word offset = EXTEND16 (OFFSET) << 2;
 722   check_branch_bug ();
 723   if ((signed_word) GPR[RS] > 0)
 724     {
 725       mark_branch_bug (NIA+offset);
 726       DELAY_SLOT (NIA + offset);
 727     }
 728 }
 729
 730
 731
 732 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 733 "bgtzl r<RS>, <OFFSET>"
 734 *mipsII:
 735 *mipsIII:
 736 *mipsIV:
 737 *mipsV:
 738 *mips32:
 739 *mips64:
 740 *vr4100:
 741 *vr5000:
 742 *r3900:
 743 {
 744   address_word offset = EXTEND16 (OFFSET) << 2;
 745   check_branch_bug ();
 746   /* NOTE: The branch occurs AFTER the next instruction has been
 747      executed */
 748   if ((signed_word) GPR[RS] > 0)
 749     {
 750       mark_branch_bug (NIA+offset);
 751       DELAY_SLOT (NIA + offset);
 752     }
 753   else
 754     NULLIFY_NEXT_INSTRUCTION ();
 755 }
 756
 757
 758
 759 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 760 "blez r<RS>, <OFFSET>"
 761 *mipsI:
 762 *mipsII:
 763 *mipsIII:
 764 *mipsIV:
 765 *mipsV:
 766 *mips32:
 767 *mips64:
 768 *vr4100:
 769 *vr5000:
 770 *r3900:
 771 {
 772   address_word offset = EXTEND16 (OFFSET) << 2;
 773   check_branch_bug ();
 774   /* NOTE: The branch occurs AFTER the next instruction has been
 775      executed */
 776   if ((signed_word) GPR[RS] <= 0)
 777     {
 778       mark_branch_bug (NIA+offset);
 779       DELAY_SLOT (NIA + offset);
 780     }
 781 }
 782
 783
 784
 785 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 786 "bgezl r<RS>, <OFFSET>"
 787 *mipsII:
 788 *mipsIII:
 789 *mipsIV:
 790 *mipsV:
 791 *mips32:
 792 *mips64:
 793 *vr4100:
 794 *vr5000:
 795 *r3900:
 796 {
 797   address_word offset = EXTEND16 (OFFSET) << 2;
 798   check_branch_bug ();
 799   if ((signed_word) GPR[RS] <= 0)
 800     {
 801       mark_branch_bug (NIA+offset);
 802       DELAY_SLOT (NIA + offset);
 803     }
 804   else
 805     NULLIFY_NEXT_INSTRUCTION ();
 806 }
 807
 808
 809
 810 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 811 "bltz r<RS>, <OFFSET>"
 812 *mipsI:
 813 *mipsII:
 814 *mipsIII:
 815 *mipsIV:
 816 *mipsV:
 817 *mips32:
 818 *mips64:
 819 *vr4100:
 820 *vr5000:
 821 *r3900:
 822 {
 823   address_word offset = EXTEND16 (OFFSET) << 2;
 824   check_branch_bug ();
 825   if ((signed_word) GPR[RS] < 0)
 826     {
 827       mark_branch_bug (NIA+offset);
 828       DELAY_SLOT (NIA + offset);
 829     }
 830 }
 831
 832
 833
 834 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 835 "bltzal r<RS>, <OFFSET>"
 836 *mipsI:
 837 *mipsII:
 838 *mipsIII:
 839 *mipsIV:
 840 *mipsV:
 841 *mips32:
 842 *mips64:
 843 *vr4100:
 844 *vr5000:
 845 *r3900:
 846 {
 847   address_word offset = EXTEND16 (OFFSET) << 2;
 848   check_branch_bug ();
 849   if (RS == 31)
 850     Unpredictable ();
 851   RA = (CIA + 8);
 852   /* NOTE: The branch occurs AFTER the next instruction has been
 853      executed */
 854   if ((signed_word) GPR[RS] < 0)
 855     {
 856       mark_branch_bug (NIA+offset);
 857       DELAY_SLOT (NIA + offset);
 858     }
 859 }
 860
 861
 862
 863 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 864 "bltzall r<RS>, <OFFSET>"
 865 *mipsII:
 866 *mipsIII:
 867 *mipsIV:
 868 *mipsV:
 869 *mips32:
 870 *mips64:
 871 *vr4100:
 872 *vr5000:
 873 *r3900:
 874 {
 875   address_word offset = EXTEND16 (OFFSET) << 2;
 876   check_branch_bug ();
 877   if (RS == 31)
 878     Unpredictable ();
 879   RA = (CIA + 8);
 880   if ((signed_word) GPR[RS] < 0)
 881     {
 882       mark_branch_bug (NIA+offset);
 883       DELAY_SLOT (NIA + offset);
 884     }
 885   else
 886     NULLIFY_NEXT_INSTRUCTION ();
 887 }
 888
 889
 890
 891 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 892 "bltzl r<RS>, <OFFSET>"
 893 *mipsII:
 894 *mipsIII:
 895 *mipsIV:
 896 *mipsV:
 897 *mips32:
 898 *mips64:
 899 *vr4100:
 900 *vr5000:
 901 *r3900:
 902 {
 903   address_word offset = EXTEND16 (OFFSET) << 2;
 904   check_branch_bug ();
 905   /* NOTE: The branch occurs AFTER the next instruction has been
 906      executed */
 907   if ((signed_word) GPR[RS] < 0)
 908     {
 909       mark_branch_bug (NIA+offset);
 910       DELAY_SLOT (NIA + offset);
 911     }
 912   else
 913     NULLIFY_NEXT_INSTRUCTION ();
 914 }
 915
 916
 917
 918 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 919 "bne r<RS>, r<RT>, <OFFSET>"
 920 *mipsI:
 921 *mipsII:
 922 *mipsIII:
 923 *mipsIV:
 924 *mipsV:
 925 *mips32:
 926 *mips64:
 927 *vr4100:
 928 *vr5000:
 929 *r3900:
 930 {
 931   address_word offset = EXTEND16 (OFFSET) << 2;
 932   check_branch_bug ();
 933   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 934     {
 935       mark_branch_bug (NIA+offset);
 936       DELAY_SLOT (NIA + offset);
 937     }
 938 }
 939
 940
 941
 942 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 943 "bnel r<RS>, r<RT>, <OFFSET>"
 944 *mipsII:
 945 *mipsIII:
 946 *mipsIV:
 947 *mipsV:
 948 *mips32:
 949 *mips64:
 950 *vr4100:
 951 *vr5000:
 952 *r3900:
 953 {
 954   address_word offset = EXTEND16 (OFFSET) << 2;
 955   check_branch_bug ();
 956   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 957     {
 958       mark_branch_bug (NIA+offset);
 959       DELAY_SLOT (NIA + offset);
 960     }
 961   else
 962     NULLIFY_NEXT_INSTRUCTION ();
 963 }
 964
 965
 966
 967 000000,20.CODE,001101:SPECIAL:32::BREAK
 968 "break %#lx<CODE>"
 969 *mipsI:
 970 *mipsII:
 971 *mipsIII:
 972 *mipsIV:
 973 *mipsV:
 974 *mips32:
 975 *mips64:
 976 *vr4100:
 977 *vr5000:
 978 *r3900:
 979 {
 980   /* Check for some break instruction which are reserved for use by the simulator.  */
 981   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 982   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 983       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 984     {
 985       sim_engine_halt (SD, CPU, NULL, cia,
 986                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 987     }
 988   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 989            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 990     {
 991       if (STATE & simDELAYSLOT)
 992         PC = cia - 4; /* reference the branch instruction */
 993       else
 994         PC = cia;
 995       SignalException (BreakPoint, instruction_0);
 996     }
 997
 998   else
 999     {
1000       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1001          the exception. */
1002       SignalException (BreakPoint, instruction_0);
1003     }
1004 }
1005
1006
1007
1008 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1009 "clo r<RD>, r<RS>"
1010 *mips32:
1011 *mips64:
1012 {
1013   unsigned32 temp = GPR[RS];
1014   unsigned32 i, mask;
1015   if (RT != RD)
1016     Unpredictable ();
1017   if (NotWordValue (GPR[RS]))
1018     Unpredictable ();
1019   TRACE_ALU_INPUT1 (GPR[RS]);
1020   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1021     {
1022       if ((temp & mask) == 0)
1023         break;
1024       mask >>= 1;
1025     }
1026   GPR[RD] = EXTEND32 (i);
1027   TRACE_ALU_RESULT (GPR[RD]);
1028 }
1029
1030
1031
1032 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1033 "clz r<RD>, r<RS>"
1034 *mips32:
1035 *mips64:
1036 {
1037   unsigned32 temp = GPR[RS];
1038   unsigned32 i, mask;
1039   if (RT != RD)
1040     Unpredictable ();
1041   if (NotWordValue (GPR[RS]))
1042     Unpredictable ();
1043   TRACE_ALU_INPUT1 (GPR[RS]);
1044   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1045     {
1046       if ((temp & mask) != 0)
1047         break;
1048       mask >>= 1;
1049     }
1050   GPR[RD] = EXTEND32 (i);
1051   TRACE_ALU_RESULT (GPR[RD]);
1052 }
1053
1054
1055
1056 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1057 "dadd r<RD>, r<RS>, r<RT>"
1058 *mipsIII:
1059 *mipsIV:
1060 *mipsV:
1061 *mips64:
1062 *vr4100:
1063 *vr5000:
1064 {
1065   check_u64 (SD_, instruction_0);
1066   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1067   {
1068     ALU64_BEGIN (GPR[RS]);
1069     ALU64_ADD (GPR[RT]);
1070     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1071   }
1072   TRACE_ALU_RESULT (GPR[RD]);
1073 }
1074
1075
1076
1077 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1078 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1079 *mipsIII:
1080 *mipsIV:
1081 *mipsV:
1082 *mips64:
1083 *vr4100:
1084 *vr5000:
1085 {
1086   check_u64 (SD_, instruction_0);
1087   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1088   {
1089     ALU64_BEGIN (GPR[RS]);
1090     ALU64_ADD (EXTEND16 (IMMEDIATE));
1091     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1092   }
1093   TRACE_ALU_RESULT (GPR[RT]);
1094 }
1095
1096
1097
1098 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1099 {
1100   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1101   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1102   TRACE_ALU_RESULT (GPR[rt]);
1103 }
1104
1105 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1106 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1107 *mipsIII:
1108 *mipsIV:
1109 *mipsV:
1110 *mips64:
1111 *vr4100:
1112 *vr5000:
1113 {
1114   check_u64 (SD_, instruction_0);
1115   do_daddiu (SD_, RS, RT, IMMEDIATE);
1116 }
1117
1118
1119
1120 :function:::void:do_daddu:int rs, int rt, int rd
1121 {
1122   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1123   GPR[rd] = GPR[rs] + GPR[rt];
1124   TRACE_ALU_RESULT (GPR[rd]);
1125 }
1126
1127 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1128 "daddu r<RD>, r<RS>, r<RT>"
1129 *mipsIII:
1130 *mipsIV:
1131 *mipsV:
1132 *mips64:
1133 *vr4100:
1134 *vr5000:
1135 {
1136   check_u64 (SD_, instruction_0);
1137   do_daddu (SD_, RS, RT, RD);
1138 }
1139
1140
1141
1142 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1143 "dclo r<RD>, r<RS>"
1144 *mips64:
1145 {
1146   unsigned64 temp = GPR[RS];
1147   unsigned32 i;
1148   unsigned64 mask;
1149   check_u64 (SD_, instruction_0);
1150   if (RT != RD)
1151     Unpredictable ();
1152   TRACE_ALU_INPUT1 (GPR[RS]);
1153   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1154     {
1155       if ((temp & mask) == 0)
1156         break;
1157       mask >>= 1;
1158     }
1159   GPR[RD] = EXTEND32 (i);
1160   TRACE_ALU_RESULT (GPR[RD]);
1161 }
1162
1163
1164
1165 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1166 "dclz r<RD>, r<RS>"
1167 *mips64:
1168 {
1169   unsigned64 temp = GPR[RS];
1170   unsigned32 i;
1171   unsigned64 mask;
1172   check_u64 (SD_, instruction_0);
1173   if (RT != RD)
1174     Unpredictable ();
1175   TRACE_ALU_INPUT1 (GPR[RS]);
1176   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1177     {
1178       if ((temp & mask) != 0)
1179         break;
1180       mask >>= 1;
1181     }
1182   GPR[RD] = EXTEND32 (i);
1183   TRACE_ALU_RESULT (GPR[RD]);
1184 }
1185
1186
1187
1188 :function:::void:do_ddiv:int rs, int rt
1189 {
1190   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1191   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1192   {
1193     signed64 n = GPR[rs];
1194     signed64 d = GPR[rt];
1195     signed64 hi;
1196     signed64 lo;
1197     if (d == 0)
1198       {
1199         lo = SIGNED64 (0x8000000000000000);
1200         hi = 0;
1201       }
1202     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1203       {
1204         lo = SIGNED64 (0x8000000000000000);
1205         hi = 0;
1206       }
1207     else
1208       {
1209         lo = (n / d);
1210         hi = (n % d);
1211       }
1212     HI = hi;
1213     LO = lo;
1214   }
1215   TRACE_ALU_RESULT2 (HI, LO);
1216 }
1217
1218 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1219 "ddiv r<RS>, r<RT>"
1220 *mipsIII:
1221 *mipsIV:
1222 *mipsV:
1223 *mips64:
1224 *vr4100:
1225 *vr5000:
1226 {
1227   check_u64 (SD_, instruction_0);
1228   do_ddiv (SD_, RS, RT);
1229 }
1230
1231
1232
1233 :function:::void:do_ddivu:int rs, int rt
1234 {
1235   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1236   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1237   {
1238     unsigned64 n = GPR[rs];
1239     unsigned64 d = GPR[rt];
1240     unsigned64 hi;
1241     unsigned64 lo;
1242     if (d == 0)
1243       {
1244         lo = SIGNED64 (0x8000000000000000);
1245         hi = 0;
1246       }
1247     else
1248       {
1249         lo = (n / d);
1250         hi = (n % d);
1251       }
1252     HI = hi;
1253     LO = lo;
1254   }
1255   TRACE_ALU_RESULT2 (HI, LO);
1256 }
1257
1258 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1259 "ddivu r<RS>, r<RT>"
1260 *mipsIII:
1261 *mipsIV:
1262 *mipsV:
1263 *mips64:
1264 *vr4100:
1265 *vr5000:
1266 {
1267   check_u64 (SD_, instruction_0);
1268   do_ddivu (SD_, RS, RT);
1269 }
1270
1271
1272
1273 :function:::void:do_div:int rs, int rt
1274 {
1275   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1276   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1277   {
1278     signed32 n = GPR[rs];
1279     signed32 d = GPR[rt];
1280     if (d == 0)
1281       {
1282         LO = EXTEND32 (0x80000000);
1283         HI = EXTEND32 (0);
1284       }
1285     else if (n == SIGNED32 (0x80000000) && d == -1)
1286       {
1287         LO = EXTEND32 (0x80000000);
1288         HI = EXTEND32 (0);
1289       }
1290     else
1291       {
1292         LO = EXTEND32 (n / d);
1293         HI = EXTEND32 (n % d);
1294       }
1295   }
1296   TRACE_ALU_RESULT2 (HI, LO);
1297 }
1298
1299 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1300 "div r<RS>, r<RT>"
1301 *mipsI:
1302 *mipsII:
1303 *mipsIII:
1304 *mipsIV:
1305 *mipsV:
1306 *mips32:
1307 *mips64:
1308 *vr4100:
1309 *vr5000:
1310 *r3900:
1311 {
1312   do_div (SD_, RS, RT);
1313 }
1314
1315
1316
1317 :function:::void:do_divu:int rs, int rt
1318 {
1319   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1320   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1321   {
1322     unsigned32 n = GPR[rs];
1323     unsigned32 d = GPR[rt];
1324     if (d == 0)
1325       {
1326         LO = EXTEND32 (0x80000000);
1327         HI = EXTEND32 (0);
1328       }
1329     else
1330       {
1331         LO = EXTEND32 (n / d);
1332         HI = EXTEND32 (n % d);
1333       }
1334   }
1335   TRACE_ALU_RESULT2 (HI, LO);
1336 }
1337
1338 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1339 "divu r<RS>, r<RT>"
1340 *mipsI:
1341 *mipsII:
1342 *mipsIII:
1343 *mipsIV:
1344 *mipsV:
1345 *mips32:
1346 *mips64:
1347 *vr4100:
1348 *vr5000:
1349 *r3900:
1350 {
1351   do_divu (SD_, RS, RT);
1352 }
1353
1354
1355
1356 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1357 {
1358   unsigned64 lo;
1359   unsigned64 hi;
1360   unsigned64 m00;
1361   unsigned64 m01;
1362   unsigned64 m10;
1363   unsigned64 m11;
1364   unsigned64 mid;
1365   int sign;
1366   unsigned64 op1 = GPR[rs];
1367   unsigned64 op2 = GPR[rt];
1368   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1369   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1370   /* make signed multiply unsigned */
1371   sign = 0;
1372   if (signed_p)
1373     {
1374       if (op1 < 0)
1375         {
1376           op1 = - op1;
1377           ++sign;
1378         }
1379       if (op2 < 0)
1380         {
1381           op2 = - op2;
1382           ++sign;
1383         }
1384     }
1385   /* multiply out the 4 sub products */
1386   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1387   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1388   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1389   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1390   /* add the products */
1391   mid = ((unsigned64) VH4_8 (m00)
1392          + (unsigned64) VL4_8 (m10)
1393          + (unsigned64) VL4_8 (m01));
1394   lo = U8_4 (mid, m00);
1395   hi = (m11
1396         + (unsigned64) VH4_8 (mid)
1397         + (unsigned64) VH4_8 (m01)
1398         + (unsigned64) VH4_8 (m10));
1399   /* fix the sign */
1400   if (sign & 1)
1401     {
1402       lo = -lo;
1403       if (lo == 0)
1404         hi = -hi;
1405       else
1406         hi = -hi - 1;
1407     }
1408   /* save the result HI/LO (and a gpr) */
1409   LO = lo;
1410   HI = hi;
1411   if (rd != 0)
1412     GPR[rd] = lo;
1413   TRACE_ALU_RESULT2 (HI, LO);
1414 }
1415
1416 :function:::void:do_dmult:int rs, int rt, int rd
1417 {
1418   do_dmultx (SD_, rs, rt, rd, 1);
1419 }
1420
1421 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1422 "dmult r<RS>, r<RT>"
1423 *mipsIII:
1424 *mipsIV:
1425 *mipsV:
1426 *mips64:
1427 *vr4100:
1428 {
1429   check_u64 (SD_, instruction_0);
1430   do_dmult (SD_, RS, RT, 0);
1431 }
1432
1433 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1434 "dmult r<RS>, r<RT>":RD == 0
1435 "dmult r<RD>, r<RS>, r<RT>"
1436 *vr5000:
1437 {
1438   check_u64 (SD_, instruction_0);
1439   do_dmult (SD_, RS, RT, RD);
1440 }
1441
1442
1443
1444 :function:::void:do_dmultu:int rs, int rt, int rd
1445 {
1446   do_dmultx (SD_, rs, rt, rd, 0);
1447 }
1448
1449 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1450 "dmultu r<RS>, r<RT>"
1451 *mipsIII:
1452 *mipsIV:
1453 *mipsV:
1454 *mips64:
1455 *vr4100:
1456 {
1457   check_u64 (SD_, instruction_0);
1458   do_dmultu (SD_, RS, RT, 0);
1459 }
1460
1461 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1462 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1463 "dmultu r<RS>, r<RT>"
1464 *vr5000:
1465 {
1466   check_u64 (SD_, instruction_0);
1467   do_dmultu (SD_, RS, RT, RD);
1468 }
1469
1470 :function:::void:do_dsll:int rt, int rd, int shift
1471 {
1472   TRACE_ALU_INPUT2 (GPR[rt], shift);
1473   GPR[rd] = GPR[rt] << shift;
1474   TRACE_ALU_RESULT (GPR[rd]);
1475 }
1476
1477 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1478 "dsll r<RD>, r<RT>, <SHIFT>"
1479 *mipsIII:
1480 *mipsIV:
1481 *mipsV:
1482 *mips64:
1483 *vr4100:
1484 *vr5000:
1485 {
1486   check_u64 (SD_, instruction_0);
1487   do_dsll (SD_, RT, RD, SHIFT);
1488 }
1489
1490
1491 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1492 "dsll32 r<RD>, r<RT>, <SHIFT>"
1493 *mipsIII:
1494 *mipsIV:
1495 *mipsV:
1496 *mips64:
1497 *vr4100:
1498 *vr5000:
1499 {
1500   int s = 32 + SHIFT;
1501   check_u64 (SD_, instruction_0);
1502   TRACE_ALU_INPUT2 (GPR[RT], s);
1503   GPR[RD] = GPR[RT] << s;
1504   TRACE_ALU_RESULT (GPR[RD]);
1505 }
1506
1507 :function:::void:do_dsllv:int rs, int rt, int rd
1508 {
1509   int s = MASKED64 (GPR[rs], 5, 0);
1510   TRACE_ALU_INPUT2 (GPR[rt], s);
1511   GPR[rd] = GPR[rt] << s;
1512   TRACE_ALU_RESULT (GPR[rd]);
1513 }
1514
1515 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1516 "dsllv r<RD>, r<RT>, r<RS>"
1517 *mipsIII:
1518 *mipsIV:
1519 *mipsV:
1520 *mips64:
1521 *vr4100:
1522 *vr5000:
1523 {
1524   check_u64 (SD_, instruction_0);
1525   do_dsllv (SD_, RS, RT, RD);
1526 }
1527
1528 :function:::void:do_dsra:int rt, int rd, int shift
1529 {
1530   TRACE_ALU_INPUT2 (GPR[rt], shift);
1531   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1532   TRACE_ALU_RESULT (GPR[rd]);
1533 }
1534
1535
1536 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1537 "dsra r<RD>, r<RT>, <SHIFT>"
1538 *mipsIII:
1539 *mipsIV:
1540 *mipsV:
1541 *mips64:
1542 *vr4100:
1543 *vr5000:
1544 {
1545   check_u64 (SD_, instruction_0);
1546   do_dsra (SD_, RT, RD, SHIFT);
1547 }
1548
1549
1550 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1551 "dsra32 r<RD>, r<RT>, <SHIFT>"
1552 *mipsIII:
1553 *mipsIV:
1554 *mipsV:
1555 *mips64:
1556 *vr4100:
1557 *vr5000:
1558 {
1559   int s = 32 + SHIFT;
1560   check_u64 (SD_, instruction_0);
1561   TRACE_ALU_INPUT2 (GPR[RT], s);
1562   GPR[RD] = ((signed64) GPR[RT]) >> s;
1563   TRACE_ALU_RESULT (GPR[RD]);
1564 }
1565
1566
1567 :function:::void:do_dsrav:int rs, int rt, int rd
1568 {
1569   int s = MASKED64 (GPR[rs], 5, 0);
1570   TRACE_ALU_INPUT2 (GPR[rt], s);
1571   GPR[rd] = ((signed64) GPR[rt]) >> s;
1572   TRACE_ALU_RESULT (GPR[rd]);
1573 }
1574
1575 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1576 "dsrav r<RD>, r<RT>, r<RS>"
1577 *mipsIII:
1578 *mipsIV:
1579 *mipsV:
1580 *mips64:
1581 *vr4100:
1582 *vr5000:
1583 {
1584   check_u64 (SD_, instruction_0);
1585   do_dsrav (SD_, RS, RT, RD);
1586 }
1587
1588 :function:::void:do_dsrl:int rt, int rd, int shift
1589 {
1590   TRACE_ALU_INPUT2 (GPR[rt], shift);
1591   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1592   TRACE_ALU_RESULT (GPR[rd]);
1593 }
1594
1595
1596 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1597 "dsrl r<RD>, r<RT>, <SHIFT>"
1598 *mipsIII:
1599 *mipsIV:
1600 *mipsV:
1601 *mips64:
1602 *vr4100:
1603 *vr5000:
1604 {
1605   check_u64 (SD_, instruction_0);
1606   do_dsrl (SD_, RT, RD, SHIFT);
1607 }
1608
1609
1610 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1611 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1612 *mipsIII:
1613 *mipsIV:
1614 *mipsV:
1615 *mips64:
1616 *vr4100:
1617 *vr5000:
1618 {
1619   int s = 32 + SHIFT;
1620   check_u64 (SD_, instruction_0);
1621   TRACE_ALU_INPUT2 (GPR[RT], s);
1622   GPR[RD] = (unsigned64) GPR[RT] >> s;
1623   TRACE_ALU_RESULT (GPR[RD]);
1624 }
1625
1626
1627 :function:::void:do_dsrlv:int rs, int rt, int rd
1628 {
1629   int s = MASKED64 (GPR[rs], 5, 0);
1630   TRACE_ALU_INPUT2 (GPR[rt], s);
1631   GPR[rd] = (unsigned64) GPR[rt] >> s;
1632   TRACE_ALU_RESULT (GPR[rd]);
1633 }
1634
1635
1636
1637 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1638 "dsrlv r<RD>, r<RT>, r<RS>"
1639 *mipsIII:
1640 *mipsIV:
1641 *mipsV:
1642 *mips64:
1643 *vr4100:
1644 *vr5000:
1645 {
1646   check_u64 (SD_, instruction_0);
1647   do_dsrlv (SD_, RS, RT, RD);
1648 }
1649
1650
1651 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1652 "dsub r<RD>, r<RS>, r<RT>"
1653 *mipsIII:
1654 *mipsIV:
1655 *mipsV:
1656 *mips64:
1657 *vr4100:
1658 *vr5000:
1659 {
1660   check_u64 (SD_, instruction_0);
1661   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1662   {
1663     ALU64_BEGIN (GPR[RS]);
1664     ALU64_SUB (GPR[RT]);
1665     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1666   }
1667   TRACE_ALU_RESULT (GPR[RD]);
1668 }
1669
1670
1671 :function:::void:do_dsubu:int rs, int rt, int rd
1672 {
1673   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1674   GPR[rd] = GPR[rs] - GPR[rt];
1675   TRACE_ALU_RESULT (GPR[rd]);
1676 }
1677
1678 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1679 "dsubu r<RD>, r<RS>, r<RT>"
1680 *mipsIII:
1681 *mipsIV:
1682 *mipsV:
1683 *mips64:
1684 *vr4100:
1685 *vr5000:
1686 {
1687   check_u64 (SD_, instruction_0);
1688   do_dsubu (SD_, RS, RT, RD);
1689 }
1690
1691
1692 000010,26.INSTR_INDEX:NORMAL:32::J
1693 "j <INSTR_INDEX>"
1694 *mipsI:
1695 *mipsII:
1696 *mipsIII:
1697 *mipsIV:
1698 *mipsV:
1699 *mips32:
1700 *mips64:
1701 *vr4100:
1702 *vr5000:
1703 *r3900:
1704 {
1705   /* NOTE: The region used is that of the delay slot NIA and NOT the
1706      current instruction */
1707   address_word region = (NIA & MASK (63, 28));
1708   DELAY_SLOT (region | (INSTR_INDEX << 2));
1709 }
1710
1711
1712 000011,26.INSTR_INDEX:NORMAL:32::JAL
1713 "jal <INSTR_INDEX>"
1714 *mipsI:
1715 *mipsII:
1716 *mipsIII:
1717 *mipsIV:
1718 *mipsV:
1719 *mips32:
1720 *mips64:
1721 *vr4100:
1722 *vr5000:
1723 *r3900:
1724 {
1725   /* NOTE: The region used is that of the delay slot and NOT the
1726      current instruction */
1727   address_word region = (NIA & MASK (63, 28));
1728   GPR[31] = CIA + 8;
1729   DELAY_SLOT (region | (INSTR_INDEX << 2));
1730 }
1731
1732 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1733 "jalr r<RS>":RD == 31
1734 "jalr r<RD>, r<RS>"
1735 *mipsI:
1736 *mipsII:
1737 *mipsIII:
1738 *mipsIV:
1739 *mipsV:
1740 *mips32:
1741 *mips64:
1742 *vr4100:
1743 *vr5000:
1744 *r3900:
1745 {
1746   address_word temp = GPR[RS];
1747   GPR[RD] = CIA + 8;
1748   DELAY_SLOT (temp);
1749 }
1750
1751
1752 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1753 "jr r<RS>"
1754 *mipsI:
1755 *mipsII:
1756 *mipsIII:
1757 *mipsIV:
1758 *mipsV:
1759 *mips32:
1760 *mips64:
1761 *vr4100:
1762 *vr5000:
1763 *r3900:
1764 {
1765   DELAY_SLOT (GPR[RS]);
1766 }
1767
1768
1769 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1770 {
1771   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1772   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1773   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1774   unsigned int byte;
1775   address_word paddr;
1776   int uncached;
1777   unsigned64 memval;
1778   address_word vaddr;
1779
1780   vaddr = loadstore_ea (SD_, base, offset);
1781   if ((vaddr & access) != 0)
1782     {
1783       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1784     }
1785   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1786   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1787   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1788   byte = ((vaddr & mask) ^ bigendiancpu);
1789   return (memval >> (8 * byte));
1790 }
1791
1792 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1793 {
1794   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1795   address_word reverseendian = (ReverseEndian ? -1 : 0);
1796   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1797   unsigned int byte;
1798   unsigned int word;
1799   address_word paddr;
1800   int uncached;
1801   unsigned64 memval;
1802   address_word vaddr;
1803   int nr_lhs_bits;
1804   int nr_rhs_bits;
1805   unsigned_word lhs_mask;
1806   unsigned_word temp;
1807
1808   vaddr = loadstore_ea (SD_, base, offset);
1809   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1810   paddr = (paddr ^ (reverseendian & mask));
1811   if (BigEndianMem == 0)
1812     paddr = paddr & ~access;
1813
1814   /* compute where within the word/mem we are */
1815   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1816   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1817   nr_lhs_bits = 8 * byte + 8;
1818   nr_rhs_bits = 8 * access - 8 * byte;
1819   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1820
1821   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1822            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1823            (long) ((unsigned64) paddr >> 32), (long) paddr,
1824            word, byte, nr_lhs_bits, nr_rhs_bits); */
1825
1826   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1827   if (word == 0)
1828     {
1829       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1830       temp = (memval << nr_rhs_bits);
1831     }
1832   else
1833     {
1834       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1835       temp = (memval >> nr_lhs_bits);
1836     }
1837   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1838   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1839
1840   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1841            (long) ((unsigned64) memval >> 32), (long) memval,
1842            (long) ((unsigned64) temp >> 32), (long) temp,
1843            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1844            (long) (rt >> 32), (long) rt); */
1845   return rt;
1846 }
1847
1848 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1849 {
1850   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1851   address_word reverseendian = (ReverseEndian ? -1 : 0);
1852   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1853   unsigned int byte;
1854   address_word paddr;
1855   int uncached;
1856   unsigned64 memval;
1857   address_word vaddr;
1858
1859   vaddr = loadstore_ea (SD_, base, offset);
1860   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1861   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1862   paddr = (paddr ^ (reverseendian & mask));
1863   if (BigEndianMem != 0)
1864     paddr = paddr & ~access;
1865   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1866   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1867   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1868   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1869      (long) paddr, byte, (long) paddr, (long) memval); */
1870   {
1871     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1872     rt &= ~screen;
1873     rt |= (memval >> (8 * byte)) & screen;
1874   }
1875   return rt;
1876 }
1877
1878
1879 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1880 "lb r<RT>, <OFFSET>(r<BASE>)"
1881 *mipsI:
1882 *mipsII:
1883 *mipsIII:
1884 *mipsIV:
1885 *mipsV:
1886 *mips32:
1887 *mips64:
1888 *vr4100:
1889 *vr5000:
1890 *r3900:
1891 {
1892   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1893 }
1894
1895
1896 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1897 "lbu r<RT>, <OFFSET>(r<BASE>)"
1898 *mipsI:
1899 *mipsII:
1900 *mipsIII:
1901 *mipsIV:
1902 *mipsV:
1903 *mips32:
1904 *mips64:
1905 *vr4100:
1906 *vr5000:
1907 *r3900:
1908 {
1909   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1910 }
1911
1912
1913 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1914 "ld r<RT>, <OFFSET>(r<BASE>)"
1915 *mipsIII:
1916 *mipsIV:
1917 *mipsV:
1918 *mips64:
1919 *vr4100:
1920 *vr5000:
1921 {
1922   check_u64 (SD_, instruction_0);
1923   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1924 }
1925
1926
1927 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1928 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1929 *mipsII:
1930 *mipsIII:
1931 *mipsIV:
1932 *mipsV:
1933 *mips32:
1934 *mips64:
1935 *vr4100:
1936 *vr5000:
1937 *r3900:
1938 {
1939   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1940 }
1941
1942
1943
1944
1945 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1946 "ldl r<RT>, <OFFSET>(r<BASE>)"
1947 *mipsIII:
1948 *mipsIV:
1949 *mipsV:
1950 *mips64:
1951 *vr4100:
1952 *vr5000:
1953 {
1954   check_u64 (SD_, instruction_0);
1955   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1956 }
1957
1958
1959 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1960 "ldr r<RT>, <OFFSET>(r<BASE>)"
1961 *mipsIII:
1962 *mipsIV:
1963 *mipsV:
1964 *mips64:
1965 *vr4100:
1966 *vr5000:
1967 {
1968   check_u64 (SD_, instruction_0);
1969   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1970 }
1971
1972
1973 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1974 "lh r<RT>, <OFFSET>(r<BASE>)"
1975 *mipsI:
1976 *mipsII:
1977 *mipsIII:
1978 *mipsIV:
1979 *mipsV:
1980 *mips32:
1981 *mips64:
1982 *vr4100:
1983 *vr5000:
1984 *r3900:
1985 {
1986   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1987 }
1988
1989
1990 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1991 "lhu r<RT>, <OFFSET>(r<BASE>)"
1992 *mipsI:
1993 *mipsII:
1994 *mipsIII:
1995 *mipsIV:
1996 *mipsV:
1997 *mips32:
1998 *mips64:
1999 *vr4100:
2000 *vr5000:
2001 *r3900:
2002 {
2003   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2004 }
2005
2006
2007 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2008 "ll r<RT>, <OFFSET>(r<BASE>)"
2009 *mipsII:
2010 *mipsIII:
2011 *mipsIV:
2012 *mipsV:
2013 *mips32:
2014 *mips64:
2015 *vr4100:
2016 *vr5000:
2017 {
2018   address_word base = GPR[BASE];
2019   address_word offset = EXTEND16 (OFFSET);
2020   {
2021     address_word vaddr = loadstore_ea (SD_, base, offset);
2022     address_word paddr;
2023     int uncached;
2024     if ((vaddr & 3) != 0)
2025       {
2026         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2027       }
2028     else
2029       {
2030         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2031           {
2032             unsigned64 memval = 0;
2033             unsigned64 memval1 = 0;
2034             unsigned64 mask = 0x7;
2035             unsigned int shift = 2;
2036             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2037             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2038             unsigned int byte;
2039             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2040             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2041             byte = ((vaddr & mask) ^ (bigend << shift));
2042             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2043             LLBIT = 1;
2044           }
2045       }
2046   }
2047 }
2048
2049
2050 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2051 "lld r<RT>, <OFFSET>(r<BASE>)"
2052 *mipsIII:
2053 *mipsIV:
2054 *mipsV:
2055 *mips64:
2056 *vr4100:
2057 *vr5000:
2058 {
2059   address_word base = GPR[BASE];
2060   address_word offset = EXTEND16 (OFFSET);
2061   check_u64 (SD_, instruction_0);
2062   {
2063     address_word vaddr = loadstore_ea (SD_, base, offset);
2064     address_word paddr;
2065     int uncached;
2066     if ((vaddr & 7) != 0)
2067       {
2068         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2069       }
2070     else
2071       {
2072         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2073           {
2074             unsigned64 memval = 0;
2075             unsigned64 memval1 = 0;
2076             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2077             GPR[RT] = memval;
2078             LLBIT = 1;
2079           }
2080       }
2081   }
2082 }
2083
2084
2085 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2086 "lui r<RT>, %#lx<IMMEDIATE>"
2087 *mipsI:
2088 *mipsII:
2089 *mipsIII:
2090 *mipsIV:
2091 *mipsV:
2092 *mips32:
2093 *mips64:
2094 *vr4100:
2095 *vr5000:
2096 *r3900:
2097 {
2098   TRACE_ALU_INPUT1 (IMMEDIATE);
2099   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2100   TRACE_ALU_RESULT (GPR[RT]);
2101 }
2102
2103
2104 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2105 "lw r<RT>, <OFFSET>(r<BASE>)"
2106 *mipsI:
2107 *mipsII:
2108 *mipsIII:
2109 *mipsIV:
2110 *mipsV:
2111 *mips32:
2112 *mips64:
2113 *vr4100:
2114 *vr5000:
2115 *r3900:
2116 {
2117   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2118 }
2119
2120
2121 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2122 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2123 *mipsI:
2124 *mipsII:
2125 *mipsIII:
2126 *mipsIV:
2127 *mipsV:
2128 *mips32:
2129 *mips64:
2130 *vr4100:
2131 *vr5000:
2132 *r3900:
2133 {
2134   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2135 }
2136
2137
2138 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2139 "lwl r<RT>, <OFFSET>(r<BASE>)"
2140 *mipsI:
2141 *mipsII:
2142 *mipsIII:
2143 *mipsIV:
2144 *mipsV:
2145 *mips32:
2146 *mips64:
2147 *vr4100:
2148 *vr5000:
2149 *r3900:
2150 {
2151   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2152 }
2153
2154
2155 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2156 "lwr r<RT>, <OFFSET>(r<BASE>)"
2157 *mipsI:
2158 *mipsII:
2159 *mipsIII:
2160 *mipsIV:
2161 *mipsV:
2162 *mips32:
2163 *mips64:
2164 *vr4100:
2165 *vr5000:
2166 *r3900:
2167 {
2168   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2169 }
2170
2171
2172 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2173 "lwu r<RT>, <OFFSET>(r<BASE>)"
2174 *mipsIII:
2175 *mipsIV:
2176 *mipsV:
2177 *mips64:
2178 *vr4100:
2179 *vr5000:
2180 {
2181   check_u64 (SD_, instruction_0);
2182   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2183 }
2184
2185
2186
2187 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2188 "madd r<RS>, r<RT>"
2189 *mips32:
2190 *mips64:
2191 {
2192   signed64 temp;
2193   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2194   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2195     Unpredictable ();
2196   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2197   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2198           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2199   LO = EXTEND32 (temp);
2200   HI = EXTEND32 (VH4_8 (temp));
2201   TRACE_ALU_RESULT2 (HI, LO);
2202 }
2203
2204
2205
2206 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2207 "maddu r<RS>, r<RT>"
2208 *mips32:
2209 *mips64:
2210 {
2211   unsigned64 temp;
2212   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2213   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2214     Unpredictable ();
2215   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2216   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2217           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2218   LO = EXTEND32 (temp);
2219   HI = EXTEND32 (VH4_8 (temp));
2220   TRACE_ALU_RESULT2 (HI, LO);
2221 }
2222
2223
2224 :function:::void:do_mfhi:int rd
2225 {
2226   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2227   TRACE_ALU_INPUT1 (HI);
2228   GPR[rd] = HI;
2229   TRACE_ALU_RESULT (GPR[rd]);
2230 }
2231
2232 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2233 "mfhi r<RD>"
2234 *mipsI:
2235 *mipsII:
2236 *mipsIII:
2237 *mipsIV:
2238 *mipsV:
2239 *mips32:
2240 *mips64:
2241 *vr4100:
2242 *vr5000:
2243 *r3900:
2244 {
2245   do_mfhi (SD_, RD);
2246 }
2247
2248
2249
2250 :function:::void:do_mflo:int rd
2251 {
2252   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2253   TRACE_ALU_INPUT1 (LO);
2254   GPR[rd] = LO;
2255   TRACE_ALU_RESULT (GPR[rd]);
2256 }
2257
2258 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2259 "mflo r<RD>"
2260 *mipsI:
2261 *mipsII:
2262 *mipsIII:
2263 *mipsIV:
2264 *mipsV:
2265 *mips32:
2266 *mips64:
2267 *vr4100:
2268 *vr5000:
2269 *r3900:
2270 {
2271   do_mflo (SD_, RD);
2272 }
2273
2274
2275
2276 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2277 "movn r<RD>, r<RS>, r<RT>"
2278 *mipsIV:
2279 *mipsV:
2280 *mips32:
2281 *mips64:
2282 *vr5000:
2283 {
2284   if (GPR[RT] != 0)
2285     {
2286       GPR[RD] = GPR[RS];
2287       TRACE_ALU_RESULT (GPR[RD]);
2288     }
2289 }
2290
2291
2292
2293 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2294 "movz r<RD>, r<RS>, r<RT>"
2295 *mipsIV:
2296 *mipsV:
2297 *mips32:
2298 *mips64:
2299 *vr5000:
2300 {
2301   if (GPR[RT] == 0)
2302     {
2303       GPR[RD] = GPR[RS];
2304       TRACE_ALU_RESULT (GPR[RD]);
2305     }
2306 }
2307
2308
2309
2310 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2311 "msub r<RS>, r<RT>"
2312 *mips32:
2313 *mips64:
2314 {
2315   signed64 temp;
2316   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2317   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2318     Unpredictable ();
2319   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2320   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2321           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2322   LO = EXTEND32 (temp);
2323   HI = EXTEND32 (VH4_8 (temp));
2324   TRACE_ALU_RESULT2 (HI, LO);
2325 }
2326
2327
2328
2329 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2330 "msubu r<RS>, r<RT>"
2331 *mips32:
2332 *mips64:
2333 {
2334   unsigned64 temp;
2335   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2336   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2337     Unpredictable ();
2338   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2339   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2340           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2341   LO = EXTEND32 (temp);
2342   HI = EXTEND32 (VH4_8 (temp));
2343   TRACE_ALU_RESULT2 (HI, LO);
2344 }
2345
2346
2347
2348 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2349 "mthi r<RS>"
2350 *mipsI:
2351 *mipsII:
2352 *mipsIII:
2353 *mipsIV:
2354 *mipsV:
2355 *mips32:
2356 *mips64:
2357 *vr4100:
2358 *vr5000:
2359 *r3900:
2360 {
2361   check_mt_hilo (SD_, HIHISTORY);
2362   HI = GPR[RS];
2363 }
2364
2365
2366
2367 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2368 "mtlo r<RS>"
2369 *mipsI:
2370 *mipsII:
2371 *mipsIII:
2372 *mipsIV:
2373 *mipsV:
2374 *mips32:
2375 *mips64:
2376 *vr4100:
2377 *vr5000:
2378 *r3900:
2379 {
2380   check_mt_hilo (SD_, LOHISTORY);
2381   LO = GPR[RS];
2382 }
2383
2384
2385
2386 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2387 "mul r<RD>, r<RS>, r<RT>"
2388 *mips32:
2389 *mips64:
2390 {
2391   signed64 prod;
2392   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2393     Unpredictable ();
2394   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2395   prod = (((signed64)(signed32) GPR[RS])
2396           * ((signed64)(signed32) GPR[RT]));
2397   GPR[RD] = EXTEND32 (VL4_8 (prod));
2398   TRACE_ALU_RESULT (GPR[RD]);
2399 }
2400
2401
2402
2403 :function:::void:do_mult:int rs, int rt, int rd
2404 {
2405   signed64 prod;
2406   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2407   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2408     Unpredictable ();
2409   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2410   prod = (((signed64)(signed32) GPR[rs])
2411           * ((signed64)(signed32) GPR[rt]));
2412   LO = EXTEND32 (VL4_8 (prod));
2413   HI = EXTEND32 (VH4_8 (prod));
2414   if (rd != 0)
2415     GPR[rd] = LO;
2416   TRACE_ALU_RESULT2 (HI, LO);
2417 }
2418
2419 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2420 "mult r<RS>, r<RT>"
2421 *mipsI:
2422 *mipsII:
2423 *mipsIII:
2424 *mipsIV:
2425 *mipsV:
2426 *mips32:
2427 *mips64:
2428 *vr4100:
2429 {
2430   do_mult (SD_, RS, RT, 0);
2431 }
2432
2433
2434 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2435 "mult r<RS>, r<RT>":RD == 0
2436 "mult r<RD>, r<RS>, r<RT>"
2437 *vr5000:
2438 *r3900:
2439 {
2440   do_mult (SD_, RS, RT, RD);
2441 }
2442
2443
2444 :function:::void:do_multu:int rs, int rt, int rd
2445 {
2446   unsigned64 prod;
2447   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2448   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2449     Unpredictable ();
2450   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2451   prod = (((unsigned64)(unsigned32) GPR[rs])
2452           * ((unsigned64)(unsigned32) GPR[rt]));
2453   LO = EXTEND32 (VL4_8 (prod));
2454   HI = EXTEND32 (VH4_8 (prod));
2455   if (rd != 0)
2456     GPR[rd] = LO;
2457   TRACE_ALU_RESULT2 (HI, LO);
2458 }
2459
2460 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2461 "multu r<RS>, r<RT>"
2462 *mipsI:
2463 *mipsII:
2464 *mipsIII:
2465 *mipsIV:
2466 *mipsV:
2467 *mips32:
2468 *mips64:
2469 *vr4100:
2470 {
2471   do_multu (SD_, RS, RT, 0);
2472 }
2473
2474 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2475 "multu r<RS>, r<RT>":RD == 0
2476 "multu r<RD>, r<RS>, r<RT>"
2477 *vr5000:
2478 *r3900:
2479 {
2480   do_multu (SD_, RS, RT, RD);
2481 }
2482
2483
2484 :function:::void:do_nor:int rs, int rt, int rd
2485 {
2486   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2487   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2488   TRACE_ALU_RESULT (GPR[rd]);
2489 }
2490
2491 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2492 "nor r<RD>, r<RS>, r<RT>"
2493 *mipsI:
2494 *mipsII:
2495 *mipsIII:
2496 *mipsIV:
2497 *mipsV:
2498 *mips32:
2499 *mips64:
2500 *vr4100:
2501 *vr5000:
2502 *r3900:
2503 {
2504   do_nor (SD_, RS, RT, RD);
2505 }
2506
2507
2508 :function:::void:do_or:int rs, int rt, int rd
2509 {
2510   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2511   GPR[rd] = (GPR[rs] | GPR[rt]);
2512   TRACE_ALU_RESULT (GPR[rd]);
2513 }
2514
2515 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2516 "or r<RD>, r<RS>, r<RT>"
2517 *mipsI:
2518 *mipsII:
2519 *mipsIII:
2520 *mipsIV:
2521 *mipsV:
2522 *mips32:
2523 *mips64:
2524 *vr4100:
2525 *vr5000:
2526 *r3900:
2527 {
2528   do_or (SD_, RS, RT, RD);
2529 }
2530
2531
2532
2533 :function:::void:do_ori:int rs, int rt, unsigned immediate
2534 {
2535   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2536   GPR[rt] = (GPR[rs] | immediate);
2537   TRACE_ALU_RESULT (GPR[rt]);
2538 }
2539
2540 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2541 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2542 *mipsI:
2543 *mipsII:
2544 *mipsIII:
2545 *mipsIV:
2546 *mipsV:
2547 *mips32:
2548 *mips64:
2549 *vr4100:
2550 *vr5000:
2551 *r3900:
2552 {
2553   do_ori (SD_, RS, RT, IMMEDIATE);
2554 }
2555
2556
2557 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2558 "pref <HINT>, <OFFSET>(r<BASE>)"
2559 *mipsIV:
2560 *mipsV:
2561 *mips32:
2562 *mips64:
2563 *vr5000:
2564 {
2565   address_word base = GPR[BASE];
2566   address_word offset = EXTEND16 (OFFSET);
2567   {
2568     address_word vaddr = loadstore_ea (SD_, base, offset);
2569     address_word paddr;
2570     int uncached;
2571     {
2572       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2573         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2574     }
2575   }
2576 }
2577
2578
2579 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2580 {
2581   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2582   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2583   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2584   unsigned int byte;
2585   address_word paddr;
2586   int uncached;
2587   unsigned64 memval;
2588   address_word vaddr;
2589
2590   vaddr = loadstore_ea (SD_, base, offset);
2591   if ((vaddr & access) != 0)
2592     {
2593       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2594     }
2595   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2596   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2597   byte = ((vaddr & mask) ^ bigendiancpu);
2598   memval = (word << (8 * byte));
2599   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2600 }
2601
2602 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2603 {
2604   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2605   address_word reverseendian = (ReverseEndian ? -1 : 0);
2606   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2607   unsigned int byte;
2608   unsigned int word;
2609   address_word paddr;
2610   int uncached;
2611   unsigned64 memval;
2612   address_word vaddr;
2613   int nr_lhs_bits;
2614   int nr_rhs_bits;
2615
2616   vaddr = loadstore_ea (SD_, base, offset);
2617   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2618   paddr = (paddr ^ (reverseendian & mask));
2619   if (BigEndianMem == 0)
2620     paddr = paddr & ~access;
2621
2622   /* compute where within the word/mem we are */
2623   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2624   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2625   nr_lhs_bits = 8 * byte + 8;
2626   nr_rhs_bits = 8 * access - 8 * byte;
2627   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2628   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2629            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2630            (long) ((unsigned64) paddr >> 32), (long) paddr,
2631            word, byte, nr_lhs_bits, nr_rhs_bits); */
2632
2633   if (word == 0)
2634     {
2635       memval = (rt >> nr_rhs_bits);
2636     }
2637   else
2638     {
2639       memval = (rt << nr_lhs_bits);
2640     }
2641   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2642            (long) ((unsigned64) rt >> 32), (long) rt,
2643            (long) ((unsigned64) memval >> 32), (long) memval); */
2644   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2645 }
2646
2647 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2648 {
2649   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2650   address_word reverseendian = (ReverseEndian ? -1 : 0);
2651   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2652   unsigned int byte;
2653   address_word paddr;
2654   int uncached;
2655   unsigned64 memval;
2656   address_word vaddr;
2657
2658   vaddr = loadstore_ea (SD_, base, offset);
2659   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2660   paddr = (paddr ^ (reverseendian & mask));
2661   if (BigEndianMem != 0)
2662     paddr &= ~access;
2663   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2664   memval = (rt << (byte * 8));
2665   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2666 }
2667
2668
2669 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2670 "sb r<RT>, <OFFSET>(r<BASE>)"
2671 *mipsI:
2672 *mipsII:
2673 *mipsIII:
2674 *mipsIV:
2675 *mipsV:
2676 *mips32:
2677 *mips64:
2678 *vr4100:
2679 *vr5000:
2680 *r3900:
2681 {
2682   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2683 }
2684
2685
2686 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2687 "sc r<RT>, <OFFSET>(r<BASE>)"
2688 *mipsII:
2689 *mipsIII:
2690 *mipsIV:
2691 *mipsV:
2692 *mips32:
2693 *mips64:
2694 *vr4100:
2695 *vr5000:
2696 {
2697   unsigned32 instruction = instruction_0;
2698   address_word base = GPR[BASE];
2699   address_word offset = EXTEND16 (OFFSET);
2700   {
2701     address_word vaddr = loadstore_ea (SD_, base, offset);
2702     address_word paddr;
2703     int uncached;
2704     if ((vaddr & 3) != 0)
2705       {
2706         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2707       }
2708     else
2709       {
2710         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2711           {
2712             unsigned64 memval = 0;
2713             unsigned64 memval1 = 0;
2714             unsigned64 mask = 0x7;
2715             unsigned int byte;
2716             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2717             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2718             memval = ((unsigned64) GPR[RT] << (8 * byte));
2719             if (LLBIT)
2720               {
2721                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2722               }
2723             GPR[RT] = LLBIT;
2724           }
2725       }
2726   }
2727 }
2728
2729
2730 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2731 "scd r<RT>, <OFFSET>(r<BASE>)"
2732 *mipsIII:
2733 *mipsIV:
2734 *mipsV:
2735 *mips64:
2736 *vr4100:
2737 *vr5000:
2738 {
2739   address_word base = GPR[BASE];
2740   address_word offset = EXTEND16 (OFFSET);
2741   check_u64 (SD_, instruction_0);
2742   {
2743     address_word vaddr = loadstore_ea (SD_, base, offset);
2744     address_word paddr;
2745     int uncached;
2746     if ((vaddr & 7) != 0)
2747       {
2748         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2749       }
2750     else
2751       {
2752         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2753           {
2754             unsigned64 memval = 0;
2755             unsigned64 memval1 = 0;
2756             memval = GPR[RT];
2757             if (LLBIT)
2758               {
2759                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2760               }
2761             GPR[RT] = LLBIT;
2762           }
2763       }
2764   }
2765 }
2766
2767
2768 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2769 "sd r<RT>, <OFFSET>(r<BASE>)"
2770 *mipsIII:
2771 *mipsIV:
2772 *mipsV:
2773 *mips64:
2774 *vr4100:
2775 *vr5000:
2776 {
2777   check_u64 (SD_, instruction_0);
2778   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2779 }
2780
2781
2782 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2783 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2784 *mipsII:
2785 *mipsIII:
2786 *mipsIV:
2787 *mipsV:
2788 *mips32:
2789 *mips64:
2790 *vr4100:
2791 *vr5000:
2792 {
2793   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2794 }
2795
2796
2797 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2798 "sdl r<RT>, <OFFSET>(r<BASE>)"
2799 *mipsIII:
2800 *mipsIV:
2801 *mipsV:
2802 *mips64:
2803 *vr4100:
2804 *vr5000:
2805 {
2806   check_u64 (SD_, instruction_0);
2807   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2808 }
2809
2810
2811 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2812 "sdr r<RT>, <OFFSET>(r<BASE>)"
2813 *mipsIII:
2814 *mipsIV:
2815 *mipsV:
2816 *mips64:
2817 *vr4100:
2818 *vr5000:
2819 {
2820   check_u64 (SD_, instruction_0);
2821   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2822 }
2823
2824
2825 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2826 "sh r<RT>, <OFFSET>(r<BASE>)"
2827 *mipsI:
2828 *mipsII:
2829 *mipsIII:
2830 *mipsIV:
2831 *mipsV:
2832 *mips32:
2833 *mips64:
2834 *vr4100:
2835 *vr5000:
2836 *r3900:
2837 {
2838   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2839 }
2840
2841
2842 :function:::void:do_sll:int rt, int rd, int shift
2843 {
2844   unsigned32 temp = (GPR[rt] << shift);
2845   TRACE_ALU_INPUT2 (GPR[rt], shift);
2846   GPR[rd] = EXTEND32 (temp);
2847   TRACE_ALU_RESULT (GPR[rd]);
2848 }
2849
2850 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2851 "nop":RD == 0 && RT == 0 && SHIFT == 0
2852 "sll r<RD>, r<RT>, <SHIFT>"
2853 *mipsI:
2854 *mipsII:
2855 *mipsIII:
2856 *mipsIV:
2857 *mipsV:
2858 *vr4100:
2859 *vr5000:
2860 *r3900:
2861 {
2862   /* Skip shift for NOP, so that there won't be lots of extraneous
2863      trace output.  */
2864   if (RD != 0 || RT != 0 || SHIFT != 0)
2865     do_sll (SD_, RT, RD, SHIFT);
2866 }
2867
2868 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2869 "nop":RD == 0 && RT == 0 && SHIFT == 0
2870 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2871 "sll r<RD>, r<RT>, <SHIFT>"
2872 *mips32:
2873 *mips64:
2874 {
2875   /* Skip shift for NOP and SSNOP, so that there won't be lots of
2876      extraneous trace output.  */
2877   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2878     do_sll (SD_, RT, RD, SHIFT);
2879 }
2880
2881
2882 :function:::void:do_sllv:int rs, int rt, int rd
2883 {
2884   int s = MASKED (GPR[rs], 4, 0);
2885   unsigned32 temp = (GPR[rt] << s);
2886   TRACE_ALU_INPUT2 (GPR[rt], s);
2887   GPR[rd] = EXTEND32 (temp);
2888   TRACE_ALU_RESULT (GPR[rd]);
2889 }
2890
2891 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2892 "sllv r<RD>, r<RT>, r<RS>"
2893 *mipsI:
2894 *mipsII:
2895 *mipsIII:
2896 *mipsIV:
2897 *mipsV:
2898 *mips32:
2899 *mips64:
2900 *vr4100:
2901 *vr5000:
2902 *r3900:
2903 {
2904   do_sllv (SD_, RS, RT, RD);
2905 }
2906
2907
2908 :function:::void:do_slt:int rs, int rt, int rd
2909 {
2910   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2911   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2912   TRACE_ALU_RESULT (GPR[rd]);
2913 }
2914
2915 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2916 "slt r<RD>, r<RS>, r<RT>"
2917 *mipsI:
2918 *mipsII:
2919 *mipsIII:
2920 *mipsIV:
2921 *mipsV:
2922 *mips32:
2923 *mips64:
2924 *vr4100:
2925 *vr5000:
2926 *r3900:
2927 {
2928   do_slt (SD_, RS, RT, RD);
2929 }
2930
2931
2932 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2933 {
2934   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2935   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2936   TRACE_ALU_RESULT (GPR[rt]);
2937 }
2938
2939 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2940 "slti r<RT>, r<RS>, <IMMEDIATE>"
2941 *mipsI:
2942 *mipsII:
2943 *mipsIII:
2944 *mipsIV:
2945 *mipsV:
2946 *mips32:
2947 *mips64:
2948 *vr4100:
2949 *vr5000:
2950 *r3900:
2951 {
2952   do_slti (SD_, RS, RT, IMMEDIATE);
2953 }
2954
2955
2956 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2957 {
2958   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2959   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2960   TRACE_ALU_RESULT (GPR[rt]);
2961 }
2962
2963 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2964 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2965 *mipsI:
2966 *mipsII:
2967 *mipsIII:
2968 *mipsIV:
2969 *mipsV:
2970 *mips32:
2971 *mips64:
2972 *vr4100:
2973 *vr5000:
2974 *r3900:
2975 {
2976   do_sltiu (SD_, RS, RT, IMMEDIATE);
2977 }
2978
2979
2980
2981 :function:::void:do_sltu:int rs, int rt, int rd
2982 {
2983   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2984   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2985   TRACE_ALU_RESULT (GPR[rd]);
2986 }
2987
2988 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2989 "sltu r<RD>, r<RS>, r<RT>"
2990 *mipsI:
2991 *mipsII:
2992 *mipsIII:
2993 *mipsIV:
2994 *mipsV:
2995 *mips32:
2996 *mips64:
2997 *vr4100:
2998 *vr5000:
2999 *r3900:
3000 {
3001   do_sltu (SD_, RS, RT, RD);
3002 }
3003
3004
3005 :function:::void:do_sra:int rt, int rd, int shift
3006 {
3007   signed32 temp = (signed32) GPR[rt] >> shift;
3008   if (NotWordValue (GPR[rt]))
3009     Unpredictable ();
3010   TRACE_ALU_INPUT2 (GPR[rt], shift);
3011   GPR[rd] = EXTEND32 (temp);
3012   TRACE_ALU_RESULT (GPR[rd]);
3013 }
3014
3015 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3016 "sra r<RD>, r<RT>, <SHIFT>"
3017 *mipsI:
3018 *mipsII:
3019 *mipsIII:
3020 *mipsIV:
3021 *mipsV:
3022 *mips32:
3023 *mips64:
3024 *vr4100:
3025 *vr5000:
3026 *r3900:
3027 {
3028   do_sra (SD_, RT, RD, SHIFT);
3029 }
3030
3031
3032
3033 :function:::void:do_srav:int rs, int rt, int rd
3034 {
3035   int s = MASKED (GPR[rs], 4, 0);
3036   signed32 temp = (signed32) GPR[rt] >> s;
3037   if (NotWordValue (GPR[rt]))
3038     Unpredictable ();
3039   TRACE_ALU_INPUT2 (GPR[rt], s);
3040   GPR[rd] = EXTEND32 (temp);
3041   TRACE_ALU_RESULT (GPR[rd]);
3042 }
3043
3044 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3045 "srav r<RD>, r<RT>, r<RS>"
3046 *mipsI:
3047 *mipsII:
3048 *mipsIII:
3049 *mipsIV:
3050 *mipsV:
3051 *mips32:
3052 *mips64:
3053 *vr4100:
3054 *vr5000:
3055 *r3900:
3056 {
3057   do_srav (SD_, RS, RT, RD);
3058 }
3059
3060
3061
3062 :function:::void:do_srl:int rt, int rd, int shift
3063 {
3064   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3065   if (NotWordValue (GPR[rt]))
3066     Unpredictable ();
3067   TRACE_ALU_INPUT2 (GPR[rt], shift);
3068   GPR[rd] = EXTEND32 (temp);
3069   TRACE_ALU_RESULT (GPR[rd]);
3070 }
3071
3072 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3073 "srl r<RD>, r<RT>, <SHIFT>"
3074 *mipsI:
3075 *mipsII:
3076 *mipsIII:
3077 *mipsIV:
3078 *mipsV:
3079 *mips32:
3080 *mips64:
3081 *vr4100:
3082 *vr5000:
3083 *r3900:
3084 {
3085   do_srl (SD_, RT, RD, SHIFT);
3086 }
3087
3088
3089 :function:::void:do_srlv:int rs, int rt, int rd
3090 {
3091   int s = MASKED (GPR[rs], 4, 0);
3092   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3093   if (NotWordValue (GPR[rt]))
3094     Unpredictable ();
3095   TRACE_ALU_INPUT2 (GPR[rt], s);
3096   GPR[rd] = EXTEND32 (temp);
3097   TRACE_ALU_RESULT (GPR[rd]);
3098 }
3099
3100 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3101 "srlv r<RD>, r<RT>, r<RS>"
3102 *mipsI:
3103 *mipsII:
3104 *mipsIII:
3105 *mipsIV:
3106 *mipsV:
3107 *mips32:
3108 *mips64:
3109 *vr4100:
3110 *vr5000:
3111 *r3900:
3112 {
3113   do_srlv (SD_, RS, RT, RD);
3114 }
3115
3116
3117 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3118 "sub r<RD>, r<RS>, r<RT>"
3119 *mipsI:
3120 *mipsII:
3121 *mipsIII:
3122 *mipsIV:
3123 *mipsV:
3124 *mips32:
3125 *mips64:
3126 *vr4100:
3127 *vr5000:
3128 *r3900:
3129 {
3130   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3131     Unpredictable ();
3132   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3133   {
3134     ALU32_BEGIN (GPR[RS]);
3135     ALU32_SUB (GPR[RT]);
3136     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3137   }
3138   TRACE_ALU_RESULT (GPR[RD]);
3139 }
3140
3141
3142 :function:::void:do_subu:int rs, int rt, int rd
3143 {
3144   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3145     Unpredictable ();
3146   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3147   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3148   TRACE_ALU_RESULT (GPR[rd]);
3149 }
3150
3151 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3152 "subu r<RD>, r<RS>, r<RT>"
3153 *mipsI:
3154 *mipsII:
3155 *mipsIII:
3156 *mipsIV:
3157 *mipsV:
3158 *mips32:
3159 *mips64:
3160 *vr4100:
3161 *vr5000:
3162 *r3900:
3163 {
3164   do_subu (SD_, RS, RT, RD);
3165 }
3166
3167
3168 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3169 "sw r<RT>, <OFFSET>(r<BASE>)"
3170 *mipsI:
3171 *mipsII:
3172 *mipsIII:
3173 *mipsIV:
3174 *mipsV:
3175 *mips32:
3176 *mips64:
3177 *vr4100:
3178 *r3900:
3179 *vr5000:
3180 {
3181   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3182 }
3183
3184
3185 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3186 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3187 *mipsI:
3188 *mipsII:
3189 *mipsIII:
3190 *mipsIV:
3191 *mipsV:
3192 *mips32:
3193 *mips64:
3194 *vr4100:
3195 *vr5000:
3196 *r3900:
3197 {
3198   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3199 }
3200
3201
3202 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3203 "swl r<RT>, <OFFSET>(r<BASE>)"
3204 *mipsI:
3205 *mipsII:
3206 *mipsIII:
3207 *mipsIV:
3208 *mipsV:
3209 *mips32:
3210 *mips64:
3211 *vr4100:
3212 *vr5000:
3213 *r3900:
3214 {
3215   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3216 }
3217
3218
3219 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3220 "swr r<RT>, <OFFSET>(r<BASE>)"
3221 *mipsI:
3222 *mipsII:
3223 *mipsIII:
3224 *mipsIV:
3225 *mipsV:
3226 *mips32:
3227 *mips64:
3228 *vr4100:
3229 *vr5000:
3230 *r3900:
3231 {
3232   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3233 }
3234
3235
3236 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3237 "sync":STYPE == 0
3238 "sync <STYPE>"
3239 *mipsII:
3240 *mipsIII:
3241 *mipsIV:
3242 *mipsV:
3243 *mips32:
3244 *mips64:
3245 *vr4100:
3246 *vr5000:
3247 *r3900:
3248 {
3249   SyncOperation (STYPE);
3250 }
3251
3252
3253 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3254 "syscall %#lx<CODE>"
3255 *mipsI:
3256 *mipsII:
3257 *mipsIII:
3258 *mipsIV:
3259 *mipsV:
3260 *mips32:
3261 *mips64:
3262 *vr4100:
3263 *vr5000:
3264 *r3900:
3265 {
3266   SignalException (SystemCall, instruction_0);
3267 }
3268
3269
3270 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3271 "teq r<RS>, r<RT>"
3272 *mipsII:
3273 *mipsIII:
3274 *mipsIV:
3275 *mipsV:
3276 *mips32:
3277 *mips64:
3278 *vr4100:
3279 *vr5000:
3280 {
3281   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3282     SignalException (Trap, instruction_0);
3283 }
3284
3285
3286 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3287 "teqi r<RS>, <IMMEDIATE>"
3288 *mipsII:
3289 *mipsIII:
3290 *mipsIV:
3291 *mipsV:
3292 *mips32:
3293 *mips64:
3294 *vr4100:
3295 *vr5000:
3296 {
3297   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3298     SignalException (Trap, instruction_0);
3299 }
3300
3301
3302 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3303 "tge r<RS>, r<RT>"
3304 *mipsII:
3305 *mipsIII:
3306 *mipsIV:
3307 *mipsV:
3308 *mips32:
3309 *mips64:
3310 *vr4100:
3311 *vr5000:
3312 {
3313   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3314     SignalException (Trap, instruction_0);
3315 }
3316
3317
3318 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3319 "tgei r<RS>, <IMMEDIATE>"
3320 *mipsII:
3321 *mipsIII:
3322 *mipsIV:
3323 *mipsV:
3324 *mips32:
3325 *mips64:
3326 *vr4100:
3327 *vr5000:
3328 {
3329   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3330     SignalException (Trap, instruction_0);
3331 }
3332
3333
3334 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3335 "tgeiu r<RS>, <IMMEDIATE>"
3336 *mipsII:
3337 *mipsIII:
3338 *mipsIV:
3339 *mipsV:
3340 *mips32:
3341 *mips64:
3342 *vr4100:
3343 *vr5000:
3344 {
3345   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3346     SignalException (Trap, instruction_0);
3347 }
3348
3349
3350 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3351 "tgeu r<RS>, r<RT>"
3352 *mipsII:
3353 *mipsIII:
3354 *mipsIV:
3355 *mipsV:
3356 *mips32:
3357 *mips64:
3358 *vr4100:
3359 *vr5000:
3360 {
3361   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3362     SignalException (Trap, instruction_0);
3363 }
3364
3365
3366 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3367 "tlt r<RS>, r<RT>"
3368 *mipsII:
3369 *mipsIII:
3370 *mipsIV:
3371 *mipsV:
3372 *mips32:
3373 *mips64:
3374 *vr4100:
3375 *vr5000:
3376 {
3377   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3378     SignalException (Trap, instruction_0);
3379 }
3380
3381
3382 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3383 "tlti r<RS>, <IMMEDIATE>"
3384 *mipsII:
3385 *mipsIII:
3386 *mipsIV:
3387 *mipsV:
3388 *mips32:
3389 *mips64:
3390 *vr4100:
3391 *vr5000:
3392 {
3393   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3394     SignalException (Trap, instruction_0);
3395 }
3396
3397
3398 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3399 "tltiu r<RS>, <IMMEDIATE>"
3400 *mipsII:
3401 *mipsIII:
3402 *mipsIV:
3403 *mipsV:
3404 *mips32:
3405 *mips64:
3406 *vr4100:
3407 *vr5000:
3408 {
3409   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3410     SignalException (Trap, instruction_0);
3411 }
3412
3413
3414 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3415 "tltu r<RS>, r<RT>"
3416 *mipsII:
3417 *mipsIII:
3418 *mipsIV:
3419 *mipsV:
3420 *mips32:
3421 *mips64:
3422 *vr4100:
3423 *vr5000:
3424 {
3425   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3426     SignalException (Trap, instruction_0);
3427 }
3428
3429
3430 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3431 "tne r<RS>, r<RT>"
3432 *mipsII:
3433 *mipsIII:
3434 *mipsIV:
3435 *mipsV:
3436 *mips32:
3437 *mips64:
3438 *vr4100:
3439 *vr5000:
3440 {
3441   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3442     SignalException (Trap, instruction_0);
3443 }
3444
3445
3446 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3447 "tnei r<RS>, <IMMEDIATE>"
3448 *mipsII:
3449 *mipsIII:
3450 *mipsIV:
3451 *mipsV:
3452 *mips32:
3453 *mips64:
3454 *vr4100:
3455 *vr5000:
3456 {
3457   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3458     SignalException (Trap, instruction_0);
3459 }
3460
3461
3462 :function:::void:do_xor:int rs, int rt, int rd
3463 {
3464   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3465   GPR[rd] = GPR[rs] ^ GPR[rt];
3466   TRACE_ALU_RESULT (GPR[rd]);
3467 }
3468
3469 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3470 "xor r<RD>, r<RS>, r<RT>"
3471 *mipsI:
3472 *mipsII:
3473 *mipsIII:
3474 *mipsIV:
3475 *mipsV:
3476 *mips32:
3477 *mips64:
3478 *vr4100:
3479 *vr5000:
3480 *r3900:
3481 {
3482   do_xor (SD_, RS, RT, RD);
3483 }
3484
3485
3486 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3487 {
3488   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3489   GPR[rt] = GPR[rs] ^ immediate;
3490   TRACE_ALU_RESULT (GPR[rt]);
3491 }
3492
3493 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3494 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3495 *mipsI:
3496 *mipsII:
3497 *mipsIII:
3498 *mipsIV:
3499 *mipsV:
3500 *mips32:
3501 *mips64:
3502 *vr4100:
3503 *vr5000:
3504 *r3900:
3505 {
3506   do_xori (SD_, RS, RT, IMMEDIATE);
3507 }
3508
3509 \f
3510 //
3511 // MIPS Architecture:
3512 //
3513 //        FPU Instruction Set (COP1 & COP1X)
3514 //
3515
3516
3517 :%s::::FMT:int fmt
3518 {
3519   switch (fmt)
3520     {
3521     case fmt_single: return "s";
3522     case fmt_double: return "d";
3523     case fmt_word: return "w";
3524     case fmt_long: return "l";
3525     default: return "?";
3526     }
3527 }
3528
3529 :%s::::TF:int tf
3530 {
3531   if (tf)
3532     return "t";
3533   else
3534     return "f";
3535 }
3536
3537 :%s::::ND:int nd
3538 {
3539   if (nd)
3540     return "l";
3541   else
3542     return "";
3543 }
3544
3545 :%s::::COND:int cond
3546 {
3547   switch (cond)
3548     {
3549     case 00: return "f";
3550     case 01: return "un";
3551     case 02: return "eq";
3552     case 03: return "ueq";
3553     case 04: return "olt";
3554     case 05: return "ult";
3555     case 06: return "ole";
3556     case 07: return "ule";
3557     case 010: return "sf";
3558     case 011: return "ngle";
3559     case 012: return "seq";
3560     case 013: return "ngl";
3561     case 014: return "lt";
3562     case 015: return "nge";
3563     case 016: return "le";
3564     case 017: return "ngt";
3565     default: return "?";
3566     }
3567 }
3568
3569
3570 // Helpers:
3571 //
3572 // Check that the given FPU format is usable, and signal a
3573 // ReservedInstruction exception if not.
3574 //
3575
3576 // check_fmt checks that the format is single or double.
3577 :function:::void:check_fmt:int fmt, instruction_word insn
3578 *mipsI:
3579 *mipsII:
3580 *mipsIII:
3581 *mipsIV:
3582 *mipsV:
3583 *mips32:
3584 *mips64:
3585 *vr4100:
3586 *vr5000:
3587 *r3900:
3588 {
3589   if ((fmt != fmt_single) && (fmt != fmt_double))
3590     SignalException (ReservedInstruction, insn);
3591 }
3592
3593 // check_fmt_p checks that the format is single, double, or paired single.
3594 :function:::void:check_fmt_p:int fmt, instruction_word insn
3595 *mipsI:
3596 *mipsII:
3597 *mipsIII:
3598 *mipsIV:
3599 *mips32:
3600 *vr4100:
3601 *vr5000:
3602 *r3900:
3603 {
3604   /* None of these ISAs support Paired Single, so just fall back to
3605      the single/double check.  */
3606   check_fmt (SD_, fmt, insn);
3607 }
3608
3609 :function:::void:check_fmt_p:int fmt, instruction_word insn
3610 *mipsV:
3611 *mips64:
3612 {
3613 #if 0 /* XXX FIXME: FP code doesn't yet support paired single ops.  */
3614   if ((fmt != fmt_single) && (fmt != fmt_double)
3615       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3616     SignalException (ReservedInstruction, insn);
3617 #else
3618   check_fmt (SD_, fmt, insn);
3619 #endif
3620 }
3621
3622
3623 // Helper:
3624 //
3625 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3626 // exception if not.
3627 //
3628
3629 :function:::void:check_fpu:
3630 *mipsI:
3631 *mipsII:
3632 *mipsIII:
3633 *mipsIV:
3634 *mipsV:
3635 *mips32:
3636 *mips64:
3637 *vr4100:
3638 *vr5000:
3639 *r3900:
3640 {
3641   if (! COP_Usable (1))
3642     SignalExceptionCoProcessorUnusable (1);
3643 }
3644
3645
3646 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3647 "abs.%s<FMT> f<FD>, f<FS>"
3648 *mipsI:
3649 *mipsII:
3650 *mipsIII:
3651 *mipsIV:
3652 *mipsV:
3653 *mips32:
3654 *mips64:
3655 *vr4100:
3656 *vr5000:
3657 *r3900:
3658 {
3659   int fmt = FMT;
3660   check_fpu (SD_);
3661   check_fmt_p (SD_, fmt, instruction_0);
3662   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
3663 }
3664
3665
3666
3667 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3668 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3669 *mipsI:
3670 *mipsII:
3671 *mipsIII:
3672 *mipsIV:
3673 *mipsV:
3674 *mips32:
3675 *mips64:
3676 *vr4100:
3677 *vr5000:
3678 *r3900:
3679 {
3680   int fmt = FMT;
3681   check_fpu (SD_);
3682   check_fmt_p (SD_, fmt, instruction_0);
3683   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
3684 }
3685
3686
3687
3688 // BC1F
3689 // BC1FL
3690 // BC1T
3691 // BC1TL
3692
3693 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3694 "bc1%s<TF>%s<ND> <OFFSET>"
3695 *mipsI:
3696 *mipsII:
3697 *mipsIII:
3698 {
3699   check_fpu (SD_);
3700   check_branch_bug ();
3701   TRACE_BRANCH_INPUT (PREVCOC1());
3702   if (PREVCOC1() == TF)
3703     {
3704       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3705       TRACE_BRANCH_RESULT (dest);
3706       mark_branch_bug (dest);
3707       DELAY_SLOT (dest);
3708     }
3709   else if (ND)
3710     {
3711       TRACE_BRANCH_RESULT (0);
3712       NULLIFY_NEXT_INSTRUCTION ();
3713     }
3714   else
3715     {
3716       TRACE_BRANCH_RESULT (NIA);
3717     }
3718 }
3719
3720 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3721 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3722 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3723 *mipsIV:
3724 *mipsV:
3725 *mips32:
3726 *mips64:
3727 #*vr4100:
3728 *vr5000:
3729 *r3900:
3730 {
3731   check_fpu (SD_);
3732   check_branch_bug ();
3733   if (GETFCC(CC) == TF)
3734     {
3735       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3736       mark_branch_bug (dest);
3737       DELAY_SLOT (dest);
3738     }
3739   else if (ND)
3740     {
3741       NULLIFY_NEXT_INSTRUCTION ();
3742     }
3743 }
3744
3745
3746 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3747 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3748 *mipsI:
3749 *mipsII:
3750 *mipsIII:
3751 {
3752   int fmt = FMT;
3753   check_fpu (SD_);
3754   check_fmt_p (SD_, fmt, instruction_0);
3755   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
3756   TRACE_ALU_RESULT (ValueFCR (31));
3757 }
3758
3759 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3760 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3761 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3762 *mipsIV:
3763 *mipsV:
3764 *mips32:
3765 *mips64:
3766 *vr4100:
3767 *vr5000:
3768 *r3900:
3769 {
3770   int fmt = FMT;
3771   check_fpu (SD_);
3772   check_fmt_p (SD_, fmt, instruction_0);
3773   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
3774   TRACE_ALU_RESULT (ValueFCR (31));
3775 }
3776
3777
3778 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3779 "ceil.l.%s<FMT> f<FD>, f<FS>"
3780 *mipsIII:
3781 *mipsIV:
3782 *mipsV:
3783 *mips64:
3784 *vr4100:
3785 *vr5000:
3786 *r3900:
3787 {
3788   int fmt = FMT;
3789   check_fpu (SD_);
3790   check_fmt (SD_, fmt, instruction_0);
3791   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3792             fmt_long));
3793 }
3794
3795
3796 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3797 "ceil.w.%s<FMT> f<FD>, f<FS>"
3798 *mipsII:
3799 *mipsIII:
3800 *mipsIV:
3801 *mipsV:
3802 *mips32:
3803 *mips64:
3804 *vr4100:
3805 *vr5000:
3806 *r3900:
3807 {
3808   int fmt = FMT;
3809   check_fpu (SD_);
3810   check_fmt (SD_, fmt, instruction_0);
3811   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3812             fmt_word));
3813 }
3814
3815
3816 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
3817 "cfc1 r<RT>, f<FS>"
3818 *mipsI:
3819 *mipsII:
3820 *mipsIII:
3821 {
3822   check_fpu (SD_);
3823   if (FS == 0)
3824     PENDING_FILL (RT, EXTEND32 (FCR0));
3825   else if (FS == 31)
3826     PENDING_FILL (RT, EXTEND32 (FCR31));
3827   /* else NOP */
3828 }
3829
3830 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
3831 "cfc1 r<RT>, f<FS>"
3832 *mipsIV:
3833 *vr4100:
3834 *vr5000:
3835 *r3900:
3836 {
3837   check_fpu (SD_);
3838   if (FS == 0 || FS == 31)
3839     {
3840       unsigned_word  fcr = ValueFCR (FS);
3841       TRACE_ALU_INPUT1 (fcr);
3842       GPR[RT] = fcr;
3843     }
3844   /* else NOP */
3845   TRACE_ALU_RESULT (GPR[RT]);
3846 }
3847
3848 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
3849 "cfc1 r<RT>, f<FS>"
3850 *mipsV:
3851 *mips32:
3852 *mips64:
3853 {
3854   check_fpu (SD_);
3855   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
3856     {
3857       unsigned_word  fcr = ValueFCR (FS);
3858       TRACE_ALU_INPUT1 (fcr);
3859       GPR[RT] = fcr;
3860     }
3861   /* else NOP */
3862   TRACE_ALU_RESULT (GPR[RT]);
3863 }
3864
3865 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
3866 "ctc1 r<RT>, f<FS>"
3867 *mipsI:
3868 *mipsII:
3869 *mipsIII:
3870 {
3871   check_fpu (SD_);
3872   if (FS == 31)
3873     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
3874   /* else NOP */
3875 }
3876
3877 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
3878 "ctc1 r<RT>, f<FS>"
3879 *mipsIV:
3880 *vr4100:
3881 *vr5000:
3882 *r3900:
3883 {
3884   check_fpu (SD_);
3885   TRACE_ALU_INPUT1 (GPR[RT]);
3886   if (FS == 31)
3887     StoreFCR (FS, GPR[RT]);
3888   /* else NOP */
3889 }
3890
3891 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
3892 "ctc1 r<RT>, f<FS>"
3893 *mipsV:
3894 *mips32:
3895 *mips64:
3896 {
3897   check_fpu (SD_);
3898   TRACE_ALU_INPUT1 (GPR[RT]);
3899   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
3900       StoreFCR (FS, GPR[RT]);
3901   /* else NOP */
3902 }
3903
3904
3905 //
3906 // FIXME: Does not correctly differentiate between mips*
3907 //
3908 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3909 "cvt.d.%s<FMT> f<FD>, f<FS>"
3910 *mipsI:
3911 *mipsII:
3912 *mipsIII:
3913 *mipsIV:
3914 *mipsV:
3915 *mips32:
3916 *mips64:
3917 *vr4100:
3918 *vr5000:
3919 *r3900:
3920 {
3921   int fmt = FMT;
3922   check_fpu (SD_);
3923   if ((fmt == fmt_double) | 0)
3924     SignalException (ReservedInstruction, instruction_0);
3925   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
3926             fmt_double));
3927 }
3928
3929
3930 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3931 "cvt.l.%s<FMT> f<FD>, f<FS>"
3932 *mipsIII:
3933 *mipsIV:
3934 *mipsV:
3935 *mips64:
3936 *vr4100:
3937 *vr5000:
3938 *r3900:
3939 {
3940   int fmt = FMT;
3941   check_fpu (SD_);
3942   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3943     SignalException (ReservedInstruction, instruction_0);
3944   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
3945             fmt_long));
3946 }
3947
3948
3949 //
3950 // FIXME: Does not correctly differentiate between mips*
3951 //
3952 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3953 "cvt.s.%s<FMT> f<FD>, f<FS>"
3954 *mipsI:
3955 *mipsII:
3956 *mipsIII:
3957 *mipsIV:
3958 *mipsV:
3959 *mips32:
3960 *mips64:
3961 *vr4100:
3962 *vr5000:
3963 *r3900:
3964 {
3965   int fmt = FMT;
3966   check_fpu (SD_);
3967   if ((fmt == fmt_single) | 0)
3968     SignalException (ReservedInstruction, instruction_0);
3969   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
3970             fmt_single));
3971 }
3972
3973
3974 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
3975 "cvt.w.%s<FMT> f<FD>, f<FS>"
3976 *mipsI:
3977 *mipsII:
3978 *mipsIII:
3979 *mipsIV:
3980 *mipsV:
3981 *mips32:
3982 *mips64:
3983 *vr4100:
3984 *vr5000:
3985 *r3900:
3986 {
3987   int fmt = FMT;
3988   check_fpu (SD_);
3989   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
3990     SignalException (ReservedInstruction, instruction_0);
3991   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
3992             fmt_word));
3993 }
3994
3995
3996 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
3997 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3998 *mipsI:
3999 *mipsII:
4000 *mipsIII:
4001 *mipsIV:
4002 *mipsV:
4003 *mips32:
4004 *mips64:
4005 *vr4100:
4006 *vr5000:
4007 *r3900:
4008 {
4009   int fmt = FMT;
4010   check_fpu (SD_);
4011   check_fmt (SD_, fmt, instruction_0);
4012   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4013 }
4014
4015
4016 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4017 "dmfc1 r<RT>, f<FS>"
4018 *mipsIII:
4019 {
4020   unsigned64 v;
4021   check_fpu (SD_);
4022   check_u64 (SD_, instruction_0);
4023   if (SizeFGR () == 64)
4024     v = FGR[FS];
4025   else if ((FS & 0x1) == 0)
4026     v = SET64HI (FGR[FS+1]) | FGR[FS];
4027   else
4028     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4029   PENDING_FILL (RT, v);
4030   TRACE_ALU_RESULT (v);
4031 }
4032
4033 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4034 "dmfc1 r<RT>, f<FS>"
4035 *mipsIV:
4036 *mipsV:
4037 *mips64:
4038 *vr4100:
4039 *vr5000:
4040 *r3900:
4041 {
4042   check_fpu (SD_);
4043   check_u64 (SD_, instruction_0);
4044   if (SizeFGR () == 64)
4045     GPR[RT] = FGR[FS];
4046   else if ((FS & 0x1) == 0)
4047     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4048   else
4049     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4050   TRACE_ALU_RESULT (GPR[RT]);
4051 }
4052
4053
4054 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4055 "dmtc1 r<RT>, f<FS>"
4056 *mipsIII:
4057 {
4058   unsigned64 v;
4059   check_fpu (SD_);
4060   check_u64 (SD_, instruction_0);
4061   if (SizeFGR () == 64)
4062     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4063   else if ((FS & 0x1) == 0)
4064     {
4065       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4066       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4067     }
4068   else
4069     Unpredictable ();
4070   TRACE_FP_RESULT (GPR[RT]);
4071 }
4072
4073 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4074 "dmtc1 r<RT>, f<FS>"
4075 *mipsIV:
4076 *mipsV:
4077 *mips64:
4078 *vr4100:
4079 *vr5000:
4080 *r3900:
4081 {
4082   check_fpu (SD_);
4083   check_u64 (SD_, instruction_0);
4084   if (SizeFGR () == 64)
4085     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4086   else if ((FS & 0x1) == 0)
4087     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4088   else
4089     Unpredictable ();
4090 }
4091
4092
4093 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4094 "floor.l.%s<FMT> f<FD>, f<FS>"
4095 *mipsIII:
4096 *mipsIV:
4097 *mipsV:
4098 *mips64:
4099 *vr4100:
4100 *vr5000:
4101 *r3900:
4102 {
4103   int fmt = FMT;
4104   check_fpu (SD_);
4105   check_fmt (SD_, fmt, instruction_0);
4106   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4107             fmt_long));
4108 }
4109
4110
4111 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4112 "floor.w.%s<FMT> f<FD>, f<FS>"
4113 *mipsII:
4114 *mipsIII:
4115 *mipsIV:
4116 *mipsV:
4117 *mips32:
4118 *mips64:
4119 *vr4100:
4120 *vr5000:
4121 *r3900:
4122 {
4123   int fmt = FMT;
4124   check_fpu (SD_);
4125   check_fmt (SD_, fmt, instruction_0);
4126   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4127             fmt_word));
4128 }
4129
4130
4131 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
4132 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4133 *mipsII:
4134 *mipsIII:
4135 *mipsIV:
4136 *mipsV:
4137 *mips32:
4138 *mips64:
4139 *vr4100:
4140 *vr5000:
4141 *r3900:
4142 {
4143   check_fpu (SD_);
4144   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4145 }
4146
4147
4148 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4149 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4150 *mipsIV:
4151 *mipsV:
4152 *mips64:
4153 *vr5000:
4154 {
4155   check_fpu (SD_);
4156   check_u64 (SD_, instruction_0);
4157   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4158 }
4159
4160
4161
4162 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4163 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4164 *mipsI:
4165 *mipsII:
4166 *mipsIII:
4167 *mipsIV:
4168 *mipsV:
4169 *mips32:
4170 *mips64:
4171 *vr4100:
4172 *vr5000:
4173 *r3900:
4174 {
4175   check_fpu (SD_);
4176   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4177 }
4178
4179
4180 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4181 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4182 *mipsIV:
4183 *mipsV:
4184 *mips64:
4185 *vr5000:
4186 {
4187   check_fpu (SD_);
4188   check_u64 (SD_, instruction_0);
4189   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4190 }
4191
4192
4193
4194 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
4195 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4196 *mipsIV:
4197 *mipsV:
4198 *mips64:
4199 *vr5000:
4200 {
4201   int fmt = FMT;
4202   check_fpu (SD_);
4203   check_u64 (SD_, instruction_0);
4204   check_fmt_p (SD_, fmt, instruction_0);
4205   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4206                                   ValueFPR (FR, fmt), fmt));
4207 }
4208
4209
4210 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4211 "mfc1 r<RT>, f<FS>"
4212 *mipsI:
4213 *mipsII:
4214 *mipsIII:
4215 {
4216   unsigned64 v;
4217   check_fpu (SD_);
4218   v = EXTEND32 (FGR[FS]);
4219   PENDING_FILL (RT, v);
4220   TRACE_ALU_RESULT (v);
4221 }
4222
4223 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4224 "mfc1 r<RT>, f<FS>"
4225 *mipsIV:
4226 *mipsV:
4227 *mips32:
4228 *mips64:
4229 *vr4100:
4230 *vr5000:
4231 *r3900:
4232 {
4233   check_fpu (SD_);
4234   GPR[RT] = EXTEND32 (FGR[FS]);
4235   TRACE_ALU_RESULT (GPR[RT]);
4236 }
4237
4238
4239 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4240 "mov.%s<FMT> f<FD>, f<FS>"
4241 *mipsI:
4242 *mipsII:
4243 *mipsIII:
4244 *mipsIV:
4245 *mipsV:
4246 *mips32:
4247 *mips64:
4248 *vr4100:
4249 *vr5000:
4250 *r3900:
4251 {
4252   int fmt = FMT;
4253   check_fpu (SD_);
4254   check_fmt_p (SD_, fmt, instruction_0);
4255   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4256 }
4257
4258
4259 // MOVF
4260 // MOVT
4261 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4262 "mov%s<TF> r<RD>, r<RS>, <CC>"
4263 *mipsIV:
4264 *mipsV:
4265 *mips32:
4266 *mips64:
4267 *vr5000:
4268 {
4269   check_fpu (SD_);
4270   if (GETFCC(CC) == TF)
4271     GPR[RD] = GPR[RS];
4272 }
4273
4274
4275 // MOVF.fmt
4276 // MOVT.fmt
4277 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4278 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4279 *mipsIV:
4280 *mipsV:
4281 *mips32:
4282 *mips64:
4283 *vr5000:
4284 {
4285   int fmt = FMT;
4286   check_fpu (SD_);
4287   {
4288    if (GETFCC(CC) == TF)
4289      StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4290    else
4291      StoreFPR (FD, fmt, ValueFPR (FD, fmt));
4292   }
4293 }
4294
4295
4296 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4297 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4298 *mipsIV:
4299 *mipsV:
4300 *mips32:
4301 *mips64:
4302 *vr5000:
4303 {
4304   check_fpu (SD_);
4305   if (GPR[RT] != 0)
4306     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4307   else
4308     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4309 }
4310
4311
4312 // MOVT see MOVtf
4313
4314
4315 // MOVT.fmt see MOVtf.fmt
4316
4317
4318
4319 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4320 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4321 *mipsIV:
4322 *mipsV:
4323 *mips32:
4324 *mips64:
4325 *vr5000:
4326 {
4327   check_fpu (SD_);
4328   if (GPR[RT] == 0)
4329     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4330   else
4331     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4332 }
4333
4334
4335 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
4336 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4337 *mipsIV:
4338 *mipsV:
4339 *mips64:
4340 *vr5000:
4341 {
4342   int fmt = FMT;
4343   check_fpu (SD_);
4344   check_u64 (SD_, instruction_0);
4345   check_fmt_p (SD_, fmt, instruction_0);
4346   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4347                                   ValueFPR (FR, fmt), fmt));
4348 }
4349
4350
4351 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4352 "mtc1 r<RT>, f<FS>"
4353 *mipsI:
4354 *mipsII:
4355 *mipsIII:
4356 {
4357   check_fpu (SD_);
4358   if (SizeFGR () == 64)
4359     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4360   else
4361     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4362   TRACE_FP_RESULT (GPR[RT]);
4363 }
4364
4365 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4366 "mtc1 r<RT>, f<FS>"
4367 *mipsIV:
4368 *mipsV:
4369 *mips32:
4370 *mips64:
4371 *vr4100:
4372 *vr5000:
4373 *r3900:
4374 {
4375   check_fpu (SD_);
4376   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4377 }
4378
4379
4380 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4381 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4382 *mipsI:
4383 *mipsII:
4384 *mipsIII:
4385 *mipsIV:
4386 *mipsV:
4387 *mips32:
4388 *mips64:
4389 *vr4100:
4390 *vr5000:
4391 *r3900:
4392 {
4393   int fmt = FMT;
4394   check_fpu (SD_);
4395   check_fmt_p (SD_, fmt, instruction_0);
4396   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4397 }
4398
4399
4400 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4401 "neg.%s<FMT> f<FD>, f<FS>"
4402 *mipsI:
4403 *mipsII:
4404 *mipsIII:
4405 *mipsIV:
4406 *mipsV:
4407 *mips32:
4408 *mips64:
4409 *vr4100:
4410 *vr5000:
4411 *r3900:
4412 {
4413   int fmt = FMT;
4414   check_fpu (SD_);
4415   check_fmt_p (SD_, fmt, instruction_0);
4416   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4417 }
4418
4419
4420 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
4421 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4422 *mipsIV:
4423 *mipsV:
4424 *mips64:
4425 *vr5000:
4426 {
4427   int fmt = FMT;
4428   check_fpu (SD_);
4429   check_u64 (SD_, instruction_0);
4430   check_fmt_p (SD_, fmt, instruction_0);
4431   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4432                                      ValueFPR (FR, fmt), fmt));
4433 }
4434
4435
4436 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
4437 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4438 *mipsIV:
4439 *mipsV:
4440 *mips64:
4441 *vr5000:
4442 {
4443   int fmt = FMT;
4444   check_fpu (SD_);
4445   check_u64 (SD_, instruction_0);
4446   check_fmt_p (SD_, fmt, instruction_0);
4447   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4448                                      ValueFPR (FR, fmt), fmt));
4449 }
4450
4451
4452 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4453 "prefx <HINT>, r<INDEX>(r<BASE>)"
4454 *mipsIV:
4455 *mipsV:
4456 *mips64:
4457 *vr5000:
4458 {
4459   address_word base = GPR[BASE];
4460   address_word index = GPR[INDEX];
4461   {
4462     address_word vaddr = loadstore_ea (SD_, base, index);
4463     address_word paddr;
4464     int uncached;
4465     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4466       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4467   }
4468 }
4469
4470 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4471 "recip.%s<FMT> f<FD>, f<FS>"
4472 *mipsIV:
4473 *mipsV:
4474 *mips64:
4475 *vr5000:
4476 {
4477   int fmt = FMT;
4478   check_fpu (SD_);
4479   check_fmt (SD_, fmt, instruction_0);
4480   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
4481 }
4482
4483
4484 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4485 "round.l.%s<FMT> f<FD>, f<FS>"
4486 *mipsIII:
4487 *mipsIV:
4488 *mipsV:
4489 *mips64:
4490 *vr4100:
4491 *vr5000:
4492 *r3900:
4493 {
4494   int fmt = FMT;
4495   check_fpu (SD_);
4496   check_fmt (SD_, fmt, instruction_0);
4497   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4498             fmt_long));
4499 }
4500
4501
4502 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4503 "round.w.%s<FMT> f<FD>, f<FS>"
4504 *mipsII:
4505 *mipsIII:
4506 *mipsIV:
4507 *mipsV:
4508 *mips32:
4509 *mips64:
4510 *vr4100:
4511 *vr5000:
4512 *r3900:
4513 {
4514   int fmt = FMT;
4515   check_fpu (SD_);
4516   check_fmt (SD_, fmt, instruction_0);
4517   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4518             fmt_word));
4519 }
4520
4521
4522 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4523 "rsqrt.%s<FMT> f<FD>, f<FS>"
4524 *mipsIV:
4525 *mipsV:
4526 *mips64:
4527 *vr5000:
4528 {
4529   int fmt = FMT;
4530   check_fpu (SD_);
4531   check_fmt (SD_, fmt, instruction_0);
4532   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
4533 }
4534
4535
4536 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
4537 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4538 *mipsII:
4539 *mipsIII:
4540 *mipsIV:
4541 *mipsV:
4542 *mips32:
4543 *mips64:
4544 *vr4100:
4545 *vr5000:
4546 *r3900:
4547 {
4548   check_fpu (SD_);
4549   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4550 }
4551
4552
4553 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4554 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4555 *mipsIV:
4556 *mipsV:
4557 *mips64:
4558 *vr5000:
4559 {
4560   check_fpu (SD_);
4561   check_u64 (SD_, instruction_0);
4562   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4563 }
4564
4565
4566 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4567 "sqrt.%s<FMT> f<FD>, f<FS>"
4568 *mipsII:
4569 *mipsIII:
4570 *mipsIV:
4571 *mipsV:
4572 *mips32:
4573 *mips64:
4574 *vr4100:
4575 *vr5000:
4576 *r3900:
4577 {
4578   int fmt = FMT;
4579   check_fpu (SD_);
4580   check_fmt (SD_, fmt, instruction_0);
4581   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
4582 }
4583
4584
4585 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4586 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4587 *mipsI:
4588 *mipsII:
4589 *mipsIII:
4590 *mipsIV:
4591 *mipsV:
4592 *mips32:
4593 *mips64:
4594 *vr4100:
4595 *vr5000:
4596 *r3900:
4597 {
4598   int fmt = FMT;
4599   check_fpu (SD_);
4600   check_fmt_p (SD_, fmt, instruction_0);
4601   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4602 }
4603
4604
4605
4606 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4607 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4608 *mipsI:
4609 *mipsII:
4610 *mipsIII:
4611 *mipsIV:
4612 *mipsV:
4613 *mips32:
4614 *mips64:
4615 *vr4100:
4616 *vr5000:
4617 *r3900:
4618 {
4619   address_word base = GPR[BASE];
4620   address_word offset = EXTEND16 (OFFSET);
4621   check_fpu (SD_);
4622   {
4623     address_word vaddr = loadstore_ea (SD_, base, offset);
4624     address_word paddr;
4625     int uncached;
4626     if ((vaddr & 3) != 0)
4627       {
4628         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4629       }
4630     else
4631       {
4632         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4633           {
4634             uword64 memval = 0;
4635             uword64 memval1 = 0;
4636             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4637             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4638             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4639             unsigned int byte;
4640             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4641             byte = ((vaddr & mask) ^ bigendiancpu);
4642             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4643             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4644           }
4645       }
4646   }
4647 }
4648
4649
4650 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4651 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4652 *mipsIV:
4653 *mipsV:
4654 *mips64:
4655 *vr5000:
4656 {
4657
4658   address_word base = GPR[BASE];
4659   address_word index = GPR[INDEX];
4660   check_fpu (SD_);
4661   check_u64 (SD_, instruction_0);
4662   {
4663    address_word vaddr = loadstore_ea (SD_, base, index);
4664    address_word paddr;
4665    int uncached;
4666    if ((vaddr & 3) != 0)
4667      {
4668        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4669      }
4670    else
4671    {
4672     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4673     {
4674      unsigned64 memval = 0;
4675      unsigned64 memval1 = 0;
4676      unsigned64 mask = 0x7;
4677      unsigned int byte;
4678      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4679      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4680      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4681       {
4682        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4683       }
4684     }
4685    }
4686   }
4687 }
4688
4689
4690 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4691 "trunc.l.%s<FMT> f<FD>, f<FS>"
4692 *mipsIII:
4693 *mipsIV:
4694 *mipsV:
4695 *mips64:
4696 *vr4100:
4697 *vr5000:
4698 *r3900:
4699 {
4700   int fmt = FMT;
4701   check_fpu (SD_);
4702   check_fmt (SD_, fmt, instruction_0);
4703   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4704             fmt_long));
4705 }
4706
4707
4708 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4709 "trunc.w.%s<FMT> f<FD>, f<FS>"
4710 *mipsII:
4711 *mipsIII:
4712 *mipsIV:
4713 *mipsV:
4714 *mips32:
4715 *mips64:
4716 *vr4100:
4717 *vr5000:
4718 *r3900:
4719 {
4720   int fmt = FMT;
4721   check_fpu (SD_);
4722   check_fmt (SD_, fmt, instruction_0);
4723   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4724             fmt_word));
4725 }
4726
4727 \f
4728 //
4729 // MIPS Architecture:
4730 //
4731 //        System Control Instruction Set (COP0)
4732 //
4733
4734
4735 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4736 "bc0f <OFFSET>"
4737 *mipsI:
4738 *mipsII:
4739 *mipsIII:
4740 *mipsIV:
4741 *mipsV:
4742 *mips32:
4743 *mips64:
4744 *vr4100:
4745 *vr5000:
4746
4747 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4748 "bc0f <OFFSET>"
4749 // stub needed for eCos as tx39 hardware bug workaround
4750 *r3900:
4751 {
4752   /* do nothing */
4753 }
4754
4755
4756 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4757 "bc0fl <OFFSET>"
4758 *mipsI:
4759 *mipsII:
4760 *mipsIII:
4761 *mipsIV:
4762 *mipsV:
4763 *mips32:
4764 *mips64:
4765 *vr4100:
4766 *vr5000:
4767
4768
4769 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4770 "bc0t <OFFSET>"
4771 *mipsI:
4772 *mipsII:
4773 *mipsIII:
4774 *mipsIV:
4775 *mipsV:
4776 *mips32:
4777 *mips64:
4778 *vr4100:
4779
4780
4781 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4782 "bc0tl <OFFSET>"
4783 *mipsI:
4784 *mipsII:
4785 *mipsIII:
4786 *mipsIV:
4787 *mipsV:
4788 *mips32:
4789 *mips64:
4790 *vr4100:
4791 *vr5000:
4792
4793
4794 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4795 "cache <OP>, <OFFSET>(r<BASE>)"
4796 *mipsIII:
4797 *mipsIV:
4798 *mipsV:
4799 *mips32:
4800 *mips64:
4801 *vr4100:
4802 *vr5000:
4803 *r3900:
4804 {
4805   address_word base = GPR[BASE];
4806   address_word offset = EXTEND16 (OFFSET);
4807   {
4808     address_word vaddr = loadstore_ea (SD_, base, offset);
4809     address_word paddr;
4810     int uncached;
4811     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4812       CacheOp(OP,vaddr,paddr,instruction_0);
4813   }
4814 }
4815
4816
4817 010000,1,0000000000000000000,111001:COP0:32::DI
4818 "di"
4819 *mipsI:
4820 *mipsII:
4821 *mipsIII:
4822 *mipsIV:
4823 *mipsV:
4824 *vr4100:
4825 *vr5000:
4826
4827
4828 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4829 "dmfc0 r<RT>, r<RD>"
4830 *mipsIII:
4831 *mipsIV:
4832 *mipsV:
4833 *mips64:
4834 {
4835   check_u64 (SD_, instruction_0);
4836   DecodeCoproc (instruction_0);
4837 }
4838
4839
4840 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4841 "dmtc0 r<RT>, r<RD>"
4842 *mipsIII:
4843 *mipsIV:
4844 *mipsV:
4845 *mips64:
4846 {
4847   check_u64 (SD_, instruction_0);
4848   DecodeCoproc (instruction_0);
4849 }
4850
4851
4852 010000,1,0000000000000000000,111000:COP0:32::EI
4853 "ei"
4854 *mipsI:
4855 *mipsII:
4856 *mipsIII:
4857 *mipsIV:
4858 *mipsV:
4859 *mips64:
4860 *vr4100:
4861 *vr5000:
4862
4863
4864 010000,1,0000000000000000000,011000:COP0:32::ERET
4865 "eret"
4866 *mipsIII:
4867 *mipsIV:
4868 *mipsV:
4869 *mips32:
4870 *mips64:
4871 *vr4100:
4872 *vr5000:
4873 {
4874   if (SR & status_ERL)
4875     {
4876       /* Oops, not yet available */
4877       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4878       NIA = EPC;
4879       SR &= ~status_ERL;
4880     }
4881   else
4882     {
4883       NIA = EPC;
4884       SR &= ~status_EXL;
4885     }
4886 }
4887
4888
4889 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4890 "mfc0 r<RT>, r<RD> # <REGX>"
4891 *mipsI:
4892 *mipsII:
4893 *mipsIII:
4894 *mipsIV:
4895 *mipsV:
4896 *mips32:
4897 *mips64:
4898 *vr4100:
4899 *vr5000:
4900 *r3900:
4901 {
4902   TRACE_ALU_INPUT0 ();
4903   DecodeCoproc (instruction_0);
4904   TRACE_ALU_RESULT (GPR[RT]);
4905 }
4906
4907 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4908 "mtc0 r<RT>, r<RD> # <REGX>"
4909 *mipsI:
4910 *mipsII:
4911 *mipsIII:
4912 *mipsIV:
4913 *mipsV:
4914 *mips32:
4915 *mips64:
4916 *vr4100:
4917 *vr5000:
4918 *r3900:
4919 {
4920   DecodeCoproc (instruction_0);
4921 }
4922
4923
4924 010000,1,0000000000000000000,010000:COP0:32::RFE
4925 "rfe"
4926 *mipsI:
4927 *mipsII:
4928 *mipsIII:
4929 *mipsIV:
4930 *mipsV:
4931 *vr4100:
4932 *vr5000:
4933 *r3900:
4934 {
4935   DecodeCoproc (instruction_0);
4936 }
4937
4938
4939 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4940 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
4941 *mipsI:
4942 *mipsII:
4943 *mipsIII:
4944 *mipsIV:
4945 *mipsV:
4946 *mips32:
4947 *mips64:
4948 *vr4100:
4949 *r3900:
4950 {
4951   DecodeCoproc (instruction_0);
4952 }
4953
4954
4955
4956 010000,1,0000000000000000000,001000:COP0:32::TLBP
4957 "tlbp"
4958 *mipsI:
4959 *mipsII:
4960 *mipsIII:
4961 *mipsIV:
4962 *mipsV:
4963 *mips32:
4964 *mips64:
4965 *vr4100:
4966 *vr5000:
4967
4968
4969 010000,1,0000000000000000000,000001:COP0:32::TLBR
4970 "tlbr"
4971 *mipsI:
4972 *mipsII:
4973 *mipsIII:
4974 *mipsIV:
4975 *mipsV:
4976 *mips32:
4977 *mips64:
4978 *vr4100:
4979 *vr5000:
4980
4981
4982 010000,1,0000000000000000000,000010:COP0:32::TLBWI
4983 "tlbwi"
4984 *mipsI:
4985 *mipsII:
4986 *mipsIII:
4987 *mipsIV:
4988 *mipsV:
4989 *mips32:
4990 *mips64:
4991 *vr4100:
4992 *vr5000:
4993
4994
4995 010000,1,0000000000000000000,000110:COP0:32::TLBWR
4996 "tlbwr"
4997 *mipsI:
4998 *mipsII:
4999 *mipsIII:
5000 *mipsIV:
5001 *mipsV:
5002 *mips32:
5003 *mips64:
5004 *vr4100:
5005 *vr5000:
5006
5007 \f
5008 :include:::m16.igen
5009 :include:::mdmx.igen
5010 :include:::sb1.igen
5011 :include:::tx.igen
5012 :include:::vr.igen
5013 \f