4 // <insn-word> { "+" <insn-word> }
11 // { <insn-mnemonic> }
16 // IGEN config - mips16
17 // :option:16::insn-bit-size:16
18 // :option:16::hi-bit-nr:15
19 :option:16::insn-specifying-widths:true
20 :option:16::gen-delayed-branch:false
22 // IGEN config - mips32/64..
23 // :option:32::insn-bit-size:32
24 // :option:32::hi-bit-nr:31
25 :option:32::insn-specifying-widths:true
26 :option:32::gen-delayed-branch:false
29 // Generate separate simulators for each target
30 // :option:::multi-sim:true
33 // Models known by this simulator are defined below.
35 // When placing models in the instruction descriptions, please place
36 // them one per line, in the order given here.
40 // Instructions and related functions for these models are included in
42 :model:::mipsI:mips3000:
43 :model:::mipsII:mips6000:
44 :model:::mipsIII:mips4000:
45 :model:::mipsIV:mips8000:
46 :model:::mipsV:mipsisaV:
47 :model:::mips32:mipsisa32:
48 :model:::mips64:mipsisa64:
52 // Standard MIPS ISA instructions used for these models are listed here,
53 // as are functions needed by those standard instructions. Instructions
54 // which are model-dependent and which are not in the standard MIPS ISAs
55 // (or which pre-date or use different encodings than the standard
56 // instructions) are (for the most part) in separate .igen files.
57 :model:::vr4100:mips4100: // vr.igen
58 :model:::vr5000:mips5000:
59 :model:::r3900:mips3900: // tx.igen
61 // MIPS Application Specific Extensions (ASEs)
63 // Instructions for the ASEs are in separate .igen files.
64 // ASEs add instructions on to a base ISA.
65 :model:::mips16:mips16: // m16.igen (and m16.dc)
66 :model:::mdmx:mdmx: // mdmx.igen
70 // Instructions specific to these extensions are in separate .igen files.
71 // Extensions add instructions on to a base ISA.
72 :model:::sb1:sb1: // sb1.igen
75 // Pseudo instructions known by IGEN
78 SignalException (ReservedInstruction, 0);
82 // Pseudo instructions known by interp.c
83 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
84 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
87 SignalException (ReservedInstruction, instruction_0);
94 // Simulate a 32 bit delayslot instruction
97 :function:::address_word:delayslot32:address_word target
99 instruction_word delay_insn;
100 sim_events_slip (SD, 1);
102 CIA = CIA + 4; /* NOTE not mips16 */
103 STATE |= simDELAYSLOT;
104 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
105 ENGINE_ISSUE_PREFIX_HOOK();
106 idecode_issue (CPU_, delay_insn, (CIA));
107 STATE &= ~simDELAYSLOT;
111 :function:::address_word:nullify_next_insn32:
113 sim_events_slip (SD, 1);
114 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
121 // Calculate an effective address given a base and an offset.
124 :function:::address_word:loadstore_ea:address_word base, address_word offset
135 return base + offset;
138 :function:::address_word:loadstore_ea:address_word base, address_word offset
141 #if 0 /* XXX FIXME: enable this only after some additional testing. */
142 /* If in user mode and UX is not set, use 32-bit compatibility effective
143 address computations as defined in the MIPS64 Architecture for
144 Programmers Volume III, Revision 0.95, section 4.9. */
145 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
146 == (ksu_user << status_KSU_shift))
147 return (address_word)((signed32)base + (signed32)offset);
149 return base + offset;
155 // Check that a 32-bit register value is properly sign-extended.
156 // (See NotWordValue in ISA spec.)
159 :function:::int:not_word_value:unsigned_word value
169 /* For historical simulator compatibility (until documentation is
170 found that makes these operations unpredictable on some of these
171 architectures), this check never returns true. */
175 :function:::int:not_word_value:unsigned_word value
178 /* On MIPS32, since registers are 32-bits, there's no check to be done. */
182 :function:::int:not_word_value:unsigned_word value
185 return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
191 // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
192 // theoretically portable code which invokes non-portable behaviour from
193 // running with no indication of the portability issue.
194 // (See definition of UNPREDICTABLE in ISA spec.)
197 :function:::void:unpredictable:
209 :function:::void:unpredictable:
213 unpredictable_action (CPU, CIA);
219 // Check that an access to a HI/LO register meets timing requirements
221 // The following requirements exist:
223 // - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
224 // - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
225 // - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
226 // corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
229 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
231 if (history->mf.timestamp + 3 > time)
233 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
234 itable[MY_INDEX].name,
236 (long) history->mf.cia);
242 :function:::int:check_mt_hilo:hilo_history *history
251 signed64 time = sim_events_time (SD);
252 int ok = check_mf_cycles (SD_, history, time, "MT");
253 history->mt.timestamp = time;
254 history->mt.cia = CIA;
258 :function:::int:check_mt_hilo:hilo_history *history
263 signed64 time = sim_events_time (SD);
264 history->mt.timestamp = time;
265 history->mt.cia = CIA;
270 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
282 signed64 time = sim_events_time (SD);
285 && peer->mt.timestamp > history->op.timestamp
286 && history->mt.timestamp < history->op.timestamp
287 && ! (history->mf.timestamp > history->op.timestamp
288 && history->mf.timestamp < peer->mt.timestamp)
289 && ! (peer->mf.timestamp > history->op.timestamp
290 && peer->mf.timestamp < peer->mt.timestamp))
292 /* The peer has been written to since the last OP yet we have
294 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
295 itable[MY_INDEX].name,
297 (long) history->op.cia,
298 (long) peer->mt.cia);
301 history->mf.timestamp = time;
302 history->mf.cia = CIA;
308 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
317 signed64 time = sim_events_time (SD);
318 int ok = (check_mf_cycles (SD_, hi, time, "OP")
319 && check_mf_cycles (SD_, lo, time, "OP"));
320 hi->op.timestamp = time;
321 lo->op.timestamp = time;
327 // The r3900 mult and multu insns _can_ be exectuted immediatly after
329 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
334 /* FIXME: could record the fact that a stall occured if we want */
335 signed64 time = sim_events_time (SD);
336 hi->op.timestamp = time;
337 lo->op.timestamp = time;
344 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
356 signed64 time = sim_events_time (SD);
357 int ok = (check_mf_cycles (SD_, hi, time, "OP")
358 && check_mf_cycles (SD_, lo, time, "OP"));
359 hi->op.timestamp = time;
360 lo->op.timestamp = time;
369 // Check that the 64-bit instruction can currently be used, and signal
370 // a ReservedInstruction exception if not.
373 :function:::void:check_u64:instruction_word insn
380 // The check should be similar to mips64 for any with PX/UX bit equivalents.
383 :function:::void:check_u64:instruction_word insn
386 #if 0 /* XXX FIXME: enable this only after some additional testing. */
387 if (UserMode && (SR & (status_UX|status_PX)) == 0)
388 SignalException (ReservedInstruction, insn);
395 // MIPS Architecture:
397 // CPU Instruction Set (mipsI - mipsV, mips32, mips64)
402 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
403 "add r<RD>, r<RS>, r<RT>"
415 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
417 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
419 ALU32_BEGIN (GPR[RS]);
421 ALU32_END (GPR[RD]); /* This checks for overflow. */
423 TRACE_ALU_RESULT (GPR[RD]);
428 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
429 "addi r<RT>, r<RS>, <IMMEDIATE>"
441 if (NotWordValue (GPR[RS]))
443 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
445 ALU32_BEGIN (GPR[RS]);
446 ALU32_ADD (EXTEND16 (IMMEDIATE));
447 ALU32_END (GPR[RT]); /* This checks for overflow. */
449 TRACE_ALU_RESULT (GPR[RT]);
454 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
456 if (NotWordValue (GPR[rs]))
458 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
459 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
460 TRACE_ALU_RESULT (GPR[rt]);
463 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
464 "addiu r<RT>, r<RS>, <IMMEDIATE>"
476 do_addiu (SD_, RS, RT, IMMEDIATE);
481 :function:::void:do_addu:int rs, int rt, int rd
483 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
485 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
486 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
487 TRACE_ALU_RESULT (GPR[rd]);
490 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
491 "addu r<RD>, r<RS>, r<RT>"
503 do_addu (SD_, RS, RT, RD);
508 :function:::void:do_and:int rs, int rt, int rd
510 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
511 GPR[rd] = GPR[rs] & GPR[rt];
512 TRACE_ALU_RESULT (GPR[rd]);
515 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
516 "and r<RD>, r<RS>, r<RT>"
528 do_and (SD_, RS, RT, RD);
533 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
534 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
546 TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
547 GPR[RT] = GPR[RS] & IMMEDIATE;
548 TRACE_ALU_RESULT (GPR[RT]);
553 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
554 "beq r<RS>, r<RT>, <OFFSET>"
566 address_word offset = EXTEND16 (OFFSET) << 2;
568 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
570 mark_branch_bug (NIA+offset);
571 DELAY_SLOT (NIA + offset);
577 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
578 "beql r<RS>, r<RT>, <OFFSET>"
589 address_word offset = EXTEND16 (OFFSET) << 2;
591 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
593 mark_branch_bug (NIA+offset);
594 DELAY_SLOT (NIA + offset);
597 NULLIFY_NEXT_INSTRUCTION ();
602 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
603 "bgez r<RS>, <OFFSET>"
615 address_word offset = EXTEND16 (OFFSET) << 2;
617 if ((signed_word) GPR[RS] >= 0)
619 mark_branch_bug (NIA+offset);
620 DELAY_SLOT (NIA + offset);
626 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
627 "bgezal r<RS>, <OFFSET>"
639 address_word offset = EXTEND16 (OFFSET) << 2;
644 if ((signed_word) GPR[RS] >= 0)
646 mark_branch_bug (NIA+offset);
647 DELAY_SLOT (NIA + offset);
653 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
654 "bgezall r<RS>, <OFFSET>"
665 address_word offset = EXTEND16 (OFFSET) << 2;
670 /* NOTE: The branch occurs AFTER the next instruction has been
672 if ((signed_word) GPR[RS] >= 0)
674 mark_branch_bug (NIA+offset);
675 DELAY_SLOT (NIA + offset);
678 NULLIFY_NEXT_INSTRUCTION ();
683 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
684 "bgezl r<RS>, <OFFSET>"
695 address_word offset = EXTEND16 (OFFSET) << 2;
697 if ((signed_word) GPR[RS] >= 0)
699 mark_branch_bug (NIA+offset);
700 DELAY_SLOT (NIA + offset);
703 NULLIFY_NEXT_INSTRUCTION ();
708 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
709 "bgtz r<RS>, <OFFSET>"
721 address_word offset = EXTEND16 (OFFSET) << 2;
723 if ((signed_word) GPR[RS] > 0)
725 mark_branch_bug (NIA+offset);
726 DELAY_SLOT (NIA + offset);
732 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
733 "bgtzl r<RS>, <OFFSET>"
744 address_word offset = EXTEND16 (OFFSET) << 2;
746 /* NOTE: The branch occurs AFTER the next instruction has been
748 if ((signed_word) GPR[RS] > 0)
750 mark_branch_bug (NIA+offset);
751 DELAY_SLOT (NIA + offset);
754 NULLIFY_NEXT_INSTRUCTION ();
759 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
760 "blez r<RS>, <OFFSET>"
772 address_word offset = EXTEND16 (OFFSET) << 2;
774 /* NOTE: The branch occurs AFTER the next instruction has been
776 if ((signed_word) GPR[RS] <= 0)
778 mark_branch_bug (NIA+offset);
779 DELAY_SLOT (NIA + offset);
785 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
786 "bgezl r<RS>, <OFFSET>"
797 address_word offset = EXTEND16 (OFFSET) << 2;
799 if ((signed_word) GPR[RS] <= 0)
801 mark_branch_bug (NIA+offset);
802 DELAY_SLOT (NIA + offset);
805 NULLIFY_NEXT_INSTRUCTION ();
810 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
811 "bltz r<RS>, <OFFSET>"
823 address_word offset = EXTEND16 (OFFSET) << 2;
825 if ((signed_word) GPR[RS] < 0)
827 mark_branch_bug (NIA+offset);
828 DELAY_SLOT (NIA + offset);
834 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
835 "bltzal r<RS>, <OFFSET>"
847 address_word offset = EXTEND16 (OFFSET) << 2;
852 /* NOTE: The branch occurs AFTER the next instruction has been
854 if ((signed_word) GPR[RS] < 0)
856 mark_branch_bug (NIA+offset);
857 DELAY_SLOT (NIA + offset);
863 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
864 "bltzall r<RS>, <OFFSET>"
875 address_word offset = EXTEND16 (OFFSET) << 2;
880 if ((signed_word) GPR[RS] < 0)
882 mark_branch_bug (NIA+offset);
883 DELAY_SLOT (NIA + offset);
886 NULLIFY_NEXT_INSTRUCTION ();
891 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
892 "bltzl r<RS>, <OFFSET>"
903 address_word offset = EXTEND16 (OFFSET) << 2;
905 /* NOTE: The branch occurs AFTER the next instruction has been
907 if ((signed_word) GPR[RS] < 0)
909 mark_branch_bug (NIA+offset);
910 DELAY_SLOT (NIA + offset);
913 NULLIFY_NEXT_INSTRUCTION ();
918 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
919 "bne r<RS>, r<RT>, <OFFSET>"
931 address_word offset = EXTEND16 (OFFSET) << 2;
933 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
935 mark_branch_bug (NIA+offset);
936 DELAY_SLOT (NIA + offset);
942 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
943 "bnel r<RS>, r<RT>, <OFFSET>"
954 address_word offset = EXTEND16 (OFFSET) << 2;
956 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
958 mark_branch_bug (NIA+offset);
959 DELAY_SLOT (NIA + offset);
962 NULLIFY_NEXT_INSTRUCTION ();
967 000000,20.CODE,001101:SPECIAL:32::BREAK
980 /* Check for some break instruction which are reserved for use by the simulator. */
981 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
982 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
983 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
985 sim_engine_halt (SD, CPU, NULL, cia,
986 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
988 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
989 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
991 if (STATE & simDELAYSLOT)
992 PC = cia - 4; /* reference the branch instruction */
995 SignalException (BreakPoint, instruction_0);
1000 /* If we get this far, we're not an instruction reserved by the sim. Raise
1002 SignalException (BreakPoint, instruction_0);
1008 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1013 unsigned32 temp = GPR[RS];
1017 if (NotWordValue (GPR[RS]))
1019 TRACE_ALU_INPUT1 (GPR[RS]);
1020 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1022 if ((temp & mask) == 0)
1026 GPR[RD] = EXTEND32 (i);
1027 TRACE_ALU_RESULT (GPR[RD]);
1032 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1037 unsigned32 temp = GPR[RS];
1041 if (NotWordValue (GPR[RS]))
1043 TRACE_ALU_INPUT1 (GPR[RS]);
1044 for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1046 if ((temp & mask) != 0)
1050 GPR[RD] = EXTEND32 (i);
1051 TRACE_ALU_RESULT (GPR[RD]);
1056 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1057 "dadd r<RD>, r<RS>, r<RT>"
1065 check_u64 (SD_, instruction_0);
1066 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1068 ALU64_BEGIN (GPR[RS]);
1069 ALU64_ADD (GPR[RT]);
1070 ALU64_END (GPR[RD]); /* This checks for overflow. */
1072 TRACE_ALU_RESULT (GPR[RD]);
1077 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1078 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1086 check_u64 (SD_, instruction_0);
1087 TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1089 ALU64_BEGIN (GPR[RS]);
1090 ALU64_ADD (EXTEND16 (IMMEDIATE));
1091 ALU64_END (GPR[RT]); /* This checks for overflow. */
1093 TRACE_ALU_RESULT (GPR[RT]);
1098 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1100 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1101 GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1102 TRACE_ALU_RESULT (GPR[rt]);
1105 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1106 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1114 check_u64 (SD_, instruction_0);
1115 do_daddiu (SD_, RS, RT, IMMEDIATE);
1120 :function:::void:do_daddu:int rs, int rt, int rd
1122 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1123 GPR[rd] = GPR[rs] + GPR[rt];
1124 TRACE_ALU_RESULT (GPR[rd]);
1127 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1128 "daddu r<RD>, r<RS>, r<RT>"
1136 check_u64 (SD_, instruction_0);
1137 do_daddu (SD_, RS, RT, RD);
1142 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1146 unsigned64 temp = GPR[RS];
1149 check_u64 (SD_, instruction_0);
1152 TRACE_ALU_INPUT1 (GPR[RS]);
1153 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1155 if ((temp & mask) == 0)
1159 GPR[RD] = EXTEND32 (i);
1160 TRACE_ALU_RESULT (GPR[RD]);
1165 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1169 unsigned64 temp = GPR[RS];
1172 check_u64 (SD_, instruction_0);
1175 TRACE_ALU_INPUT1 (GPR[RS]);
1176 for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1178 if ((temp & mask) != 0)
1182 GPR[RD] = EXTEND32 (i);
1183 TRACE_ALU_RESULT (GPR[RD]);
1188 :function:::void:do_ddiv:int rs, int rt
1190 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1191 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1193 signed64 n = GPR[rs];
1194 signed64 d = GPR[rt];
1199 lo = SIGNED64 (0x8000000000000000);
1202 else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1204 lo = SIGNED64 (0x8000000000000000);
1215 TRACE_ALU_RESULT2 (HI, LO);
1218 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1227 check_u64 (SD_, instruction_0);
1228 do_ddiv (SD_, RS, RT);
1233 :function:::void:do_ddivu:int rs, int rt
1235 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1236 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1238 unsigned64 n = GPR[rs];
1239 unsigned64 d = GPR[rt];
1244 lo = SIGNED64 (0x8000000000000000);
1255 TRACE_ALU_RESULT2 (HI, LO);
1258 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1259 "ddivu r<RS>, r<RT>"
1267 check_u64 (SD_, instruction_0);
1268 do_ddivu (SD_, RS, RT);
1273 :function:::void:do_div:int rs, int rt
1275 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1276 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1278 signed32 n = GPR[rs];
1279 signed32 d = GPR[rt];
1282 LO = EXTEND32 (0x80000000);
1285 else if (n == SIGNED32 (0x80000000) && d == -1)
1287 LO = EXTEND32 (0x80000000);
1292 LO = EXTEND32 (n / d);
1293 HI = EXTEND32 (n % d);
1296 TRACE_ALU_RESULT2 (HI, LO);
1299 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1312 do_div (SD_, RS, RT);
1317 :function:::void:do_divu:int rs, int rt
1319 check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1320 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1322 unsigned32 n = GPR[rs];
1323 unsigned32 d = GPR[rt];
1326 LO = EXTEND32 (0x80000000);
1331 LO = EXTEND32 (n / d);
1332 HI = EXTEND32 (n % d);
1335 TRACE_ALU_RESULT2 (HI, LO);
1338 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1351 do_divu (SD_, RS, RT);
1356 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1366 unsigned64 op1 = GPR[rs];
1367 unsigned64 op2 = GPR[rt];
1368 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1369 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1370 /* make signed multiply unsigned */
1385 /* multiply out the 4 sub products */
1386 m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1387 m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1388 m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1389 m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1390 /* add the products */
1391 mid = ((unsigned64) VH4_8 (m00)
1392 + (unsigned64) VL4_8 (m10)
1393 + (unsigned64) VL4_8 (m01));
1394 lo = U8_4 (mid, m00);
1396 + (unsigned64) VH4_8 (mid)
1397 + (unsigned64) VH4_8 (m01)
1398 + (unsigned64) VH4_8 (m10));
1408 /* save the result HI/LO (and a gpr) */
1413 TRACE_ALU_RESULT2 (HI, LO);
1416 :function:::void:do_dmult:int rs, int rt, int rd
1418 do_dmultx (SD_, rs, rt, rd, 1);
1421 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1422 "dmult r<RS>, r<RT>"
1429 check_u64 (SD_, instruction_0);
1430 do_dmult (SD_, RS, RT, 0);
1433 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1434 "dmult r<RS>, r<RT>":RD == 0
1435 "dmult r<RD>, r<RS>, r<RT>"
1438 check_u64 (SD_, instruction_0);
1439 do_dmult (SD_, RS, RT, RD);
1444 :function:::void:do_dmultu:int rs, int rt, int rd
1446 do_dmultx (SD_, rs, rt, rd, 0);
1449 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1450 "dmultu r<RS>, r<RT>"
1457 check_u64 (SD_, instruction_0);
1458 do_dmultu (SD_, RS, RT, 0);
1461 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1462 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1463 "dmultu r<RS>, r<RT>"
1466 check_u64 (SD_, instruction_0);
1467 do_dmultu (SD_, RS, RT, RD);
1470 :function:::void:do_dsll:int rt, int rd, int shift
1472 TRACE_ALU_INPUT2 (GPR[rt], shift);
1473 GPR[rd] = GPR[rt] << shift;
1474 TRACE_ALU_RESULT (GPR[rd]);
1477 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1478 "dsll r<RD>, r<RT>, <SHIFT>"
1486 check_u64 (SD_, instruction_0);
1487 do_dsll (SD_, RT, RD, SHIFT);
1491 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1492 "dsll32 r<RD>, r<RT>, <SHIFT>"
1501 check_u64 (SD_, instruction_0);
1502 TRACE_ALU_INPUT2 (GPR[RT], s);
1503 GPR[RD] = GPR[RT] << s;
1504 TRACE_ALU_RESULT (GPR[RD]);
1507 :function:::void:do_dsllv:int rs, int rt, int rd
1509 int s = MASKED64 (GPR[rs], 5, 0);
1510 TRACE_ALU_INPUT2 (GPR[rt], s);
1511 GPR[rd] = GPR[rt] << s;
1512 TRACE_ALU_RESULT (GPR[rd]);
1515 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1516 "dsllv r<RD>, r<RT>, r<RS>"
1524 check_u64 (SD_, instruction_0);
1525 do_dsllv (SD_, RS, RT, RD);
1528 :function:::void:do_dsra:int rt, int rd, int shift
1530 TRACE_ALU_INPUT2 (GPR[rt], shift);
1531 GPR[rd] = ((signed64) GPR[rt]) >> shift;
1532 TRACE_ALU_RESULT (GPR[rd]);
1536 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1537 "dsra r<RD>, r<RT>, <SHIFT>"
1545 check_u64 (SD_, instruction_0);
1546 do_dsra (SD_, RT, RD, SHIFT);
1550 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1551 "dsra32 r<RD>, r<RT>, <SHIFT>"
1560 check_u64 (SD_, instruction_0);
1561 TRACE_ALU_INPUT2 (GPR[RT], s);
1562 GPR[RD] = ((signed64) GPR[RT]) >> s;
1563 TRACE_ALU_RESULT (GPR[RD]);
1567 :function:::void:do_dsrav:int rs, int rt, int rd
1569 int s = MASKED64 (GPR[rs], 5, 0);
1570 TRACE_ALU_INPUT2 (GPR[rt], s);
1571 GPR[rd] = ((signed64) GPR[rt]) >> s;
1572 TRACE_ALU_RESULT (GPR[rd]);
1575 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1576 "dsrav r<RD>, r<RT>, r<RS>"
1584 check_u64 (SD_, instruction_0);
1585 do_dsrav (SD_, RS, RT, RD);
1588 :function:::void:do_dsrl:int rt, int rd, int shift
1590 TRACE_ALU_INPUT2 (GPR[rt], shift);
1591 GPR[rd] = (unsigned64) GPR[rt] >> shift;
1592 TRACE_ALU_RESULT (GPR[rd]);
1596 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1597 "dsrl r<RD>, r<RT>, <SHIFT>"
1605 check_u64 (SD_, instruction_0);
1606 do_dsrl (SD_, RT, RD, SHIFT);
1610 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1611 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1620 check_u64 (SD_, instruction_0);
1621 TRACE_ALU_INPUT2 (GPR[RT], s);
1622 GPR[RD] = (unsigned64) GPR[RT] >> s;
1623 TRACE_ALU_RESULT (GPR[RD]);
1627 :function:::void:do_dsrlv:int rs, int rt, int rd
1629 int s = MASKED64 (GPR[rs], 5, 0);
1630 TRACE_ALU_INPUT2 (GPR[rt], s);
1631 GPR[rd] = (unsigned64) GPR[rt] >> s;
1632 TRACE_ALU_RESULT (GPR[rd]);
1637 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1638 "dsrlv r<RD>, r<RT>, r<RS>"
1646 check_u64 (SD_, instruction_0);
1647 do_dsrlv (SD_, RS, RT, RD);
1651 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1652 "dsub r<RD>, r<RS>, r<RT>"
1660 check_u64 (SD_, instruction_0);
1661 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1663 ALU64_BEGIN (GPR[RS]);
1664 ALU64_SUB (GPR[RT]);
1665 ALU64_END (GPR[RD]); /* This checks for overflow. */
1667 TRACE_ALU_RESULT (GPR[RD]);
1671 :function:::void:do_dsubu:int rs, int rt, int rd
1673 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1674 GPR[rd] = GPR[rs] - GPR[rt];
1675 TRACE_ALU_RESULT (GPR[rd]);
1678 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1679 "dsubu r<RD>, r<RS>, r<RT>"
1687 check_u64 (SD_, instruction_0);
1688 do_dsubu (SD_, RS, RT, RD);
1692 000010,26.INSTR_INDEX:NORMAL:32::J
1705 /* NOTE: The region used is that of the delay slot NIA and NOT the
1706 current instruction */
1707 address_word region = (NIA & MASK (63, 28));
1708 DELAY_SLOT (region | (INSTR_INDEX << 2));
1712 000011,26.INSTR_INDEX:NORMAL:32::JAL
1725 /* NOTE: The region used is that of the delay slot and NOT the
1726 current instruction */
1727 address_word region = (NIA & MASK (63, 28));
1729 DELAY_SLOT (region | (INSTR_INDEX << 2));
1732 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1733 "jalr r<RS>":RD == 31
1746 address_word temp = GPR[RS];
1752 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1765 DELAY_SLOT (GPR[RS]);
1769 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1771 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1772 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1773 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1780 vaddr = loadstore_ea (SD_, base, offset);
1781 if ((vaddr & access) != 0)
1783 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1785 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1786 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1787 LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1788 byte = ((vaddr & mask) ^ bigendiancpu);
1789 return (memval >> (8 * byte));
1792 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1794 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1795 address_word reverseendian = (ReverseEndian ? -1 : 0);
1796 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1805 unsigned_word lhs_mask;
1808 vaddr = loadstore_ea (SD_, base, offset);
1809 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1810 paddr = (paddr ^ (reverseendian & mask));
1811 if (BigEndianMem == 0)
1812 paddr = paddr & ~access;
1814 /* compute where within the word/mem we are */
1815 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1816 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1817 nr_lhs_bits = 8 * byte + 8;
1818 nr_rhs_bits = 8 * access - 8 * byte;
1819 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1821 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1822 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1823 (long) ((unsigned64) paddr >> 32), (long) paddr,
1824 word, byte, nr_lhs_bits, nr_rhs_bits); */
1826 LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1829 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1830 temp = (memval << nr_rhs_bits);
1834 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1835 temp = (memval >> nr_lhs_bits);
1837 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1838 rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1840 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1841 (long) ((unsigned64) memval >> 32), (long) memval,
1842 (long) ((unsigned64) temp >> 32), (long) temp,
1843 (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1844 (long) (rt >> 32), (long) rt); */
1848 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1850 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1851 address_word reverseendian = (ReverseEndian ? -1 : 0);
1852 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1859 vaddr = loadstore_ea (SD_, base, offset);
1860 AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1861 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1862 paddr = (paddr ^ (reverseendian & mask));
1863 if (BigEndianMem != 0)
1864 paddr = paddr & ~access;
1865 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1866 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
1867 LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1868 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1869 (long) paddr, byte, (long) paddr, (long) memval); */
1871 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1873 rt |= (memval >> (8 * byte)) & screen;
1879 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1880 "lb r<RT>, <OFFSET>(r<BASE>)"
1892 GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1896 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1897 "lbu r<RT>, <OFFSET>(r<BASE>)"
1909 GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1913 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1914 "ld r<RT>, <OFFSET>(r<BASE>)"
1922 check_u64 (SD_, instruction_0);
1923 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1927 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1928 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1939 COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1945 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1946 "ldl r<RT>, <OFFSET>(r<BASE>)"
1954 check_u64 (SD_, instruction_0);
1955 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1959 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1960 "ldr r<RT>, <OFFSET>(r<BASE>)"
1968 check_u64 (SD_, instruction_0);
1969 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1973 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1974 "lh r<RT>, <OFFSET>(r<BASE>)"
1986 GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1990 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1991 "lhu r<RT>, <OFFSET>(r<BASE>)"
2003 GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2007 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2008 "ll r<RT>, <OFFSET>(r<BASE>)"
2018 address_word base = GPR[BASE];
2019 address_word offset = EXTEND16 (OFFSET);
2021 address_word vaddr = loadstore_ea (SD_, base, offset);
2024 if ((vaddr & 3) != 0)
2026 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2030 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2032 unsigned64 memval = 0;
2033 unsigned64 memval1 = 0;
2034 unsigned64 mask = 0x7;
2035 unsigned int shift = 2;
2036 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2037 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2039 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2040 LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2041 byte = ((vaddr & mask) ^ (bigend << shift));
2042 GPR[RT] = EXTEND32 (memval >> (8 * byte));
2050 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2051 "lld r<RT>, <OFFSET>(r<BASE>)"
2059 address_word base = GPR[BASE];
2060 address_word offset = EXTEND16 (OFFSET);
2061 check_u64 (SD_, instruction_0);
2063 address_word vaddr = loadstore_ea (SD_, base, offset);
2066 if ((vaddr & 7) != 0)
2068 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2072 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2074 unsigned64 memval = 0;
2075 unsigned64 memval1 = 0;
2076 LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2085 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2086 "lui r<RT>, %#lx<IMMEDIATE>"
2098 TRACE_ALU_INPUT1 (IMMEDIATE);
2099 GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2100 TRACE_ALU_RESULT (GPR[RT]);
2104 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2105 "lw r<RT>, <OFFSET>(r<BASE>)"
2117 GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2121 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2122 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2134 COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2138 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2139 "lwl r<RT>, <OFFSET>(r<BASE>)"
2151 GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2155 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2156 "lwr r<RT>, <OFFSET>(r<BASE>)"
2168 GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2172 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2173 "lwu r<RT>, <OFFSET>(r<BASE>)"
2181 check_u64 (SD_, instruction_0);
2182 GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2187 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2193 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2194 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2196 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2197 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2198 + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2199 LO = EXTEND32 (temp);
2200 HI = EXTEND32 (VH4_8 (temp));
2201 TRACE_ALU_RESULT2 (HI, LO);
2206 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2207 "maddu r<RS>, r<RT>"
2212 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2213 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2215 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2216 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2217 + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2218 LO = EXTEND32 (temp);
2219 HI = EXTEND32 (VH4_8 (temp));
2220 TRACE_ALU_RESULT2 (HI, LO);
2224 :function:::void:do_mfhi:int rd
2226 check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2227 TRACE_ALU_INPUT1 (HI);
2229 TRACE_ALU_RESULT (GPR[rd]);
2232 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2250 :function:::void:do_mflo:int rd
2252 check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2253 TRACE_ALU_INPUT1 (LO);
2255 TRACE_ALU_RESULT (GPR[rd]);
2258 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2276 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2277 "movn r<RD>, r<RS>, r<RT>"
2290 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2291 "movz r<RD>, r<RS>, r<RT>"
2304 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2310 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2311 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2313 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2314 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2315 - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2316 LO = EXTEND32 (temp);
2317 HI = EXTEND32 (VH4_8 (temp));
2318 TRACE_ALU_RESULT2 (HI, LO);
2323 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2324 "msubu r<RS>, r<RT>"
2329 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2330 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2332 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2333 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2334 - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2335 LO = EXTEND32 (temp);
2336 HI = EXTEND32 (VH4_8 (temp));
2337 TRACE_ALU_RESULT2 (HI, LO);
2342 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2355 check_mt_hilo (SD_, HIHISTORY);
2361 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2374 check_mt_hilo (SD_, LOHISTORY);
2380 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2381 "mul r<RD>, r<RS>, r<RT>"
2386 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2388 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2389 prod = (((signed64)(signed32) GPR[RS])
2390 * ((signed64)(signed32) GPR[RT]));
2391 GPR[RD] = EXTEND32 (VL4_8 (prod));
2392 TRACE_ALU_RESULT (GPR[RD]);
2397 :function:::void:do_mult:int rs, int rt, int rd
2400 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2401 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2403 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2404 prod = (((signed64)(signed32) GPR[rs])
2405 * ((signed64)(signed32) GPR[rt]));
2406 LO = EXTEND32 (VL4_8 (prod));
2407 HI = EXTEND32 (VH4_8 (prod));
2410 TRACE_ALU_RESULT2 (HI, LO);
2413 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2424 do_mult (SD_, RS, RT, 0);
2428 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2429 "mult r<RS>, r<RT>":RD == 0
2430 "mult r<RD>, r<RS>, r<RT>"
2434 do_mult (SD_, RS, RT, RD);
2438 :function:::void:do_multu:int rs, int rt, int rd
2441 check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2442 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2444 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2445 prod = (((unsigned64)(unsigned32) GPR[rs])
2446 * ((unsigned64)(unsigned32) GPR[rt]));
2447 LO = EXTEND32 (VL4_8 (prod));
2448 HI = EXTEND32 (VH4_8 (prod));
2451 TRACE_ALU_RESULT2 (HI, LO);
2454 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2455 "multu r<RS>, r<RT>"
2465 do_multu (SD_, RS, RT, 0);
2468 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2469 "multu r<RS>, r<RT>":RD == 0
2470 "multu r<RD>, r<RS>, r<RT>"
2474 do_multu (SD_, RS, RT, RD);
2478 :function:::void:do_nor:int rs, int rt, int rd
2480 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2481 GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2482 TRACE_ALU_RESULT (GPR[rd]);
2485 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2486 "nor r<RD>, r<RS>, r<RT>"
2498 do_nor (SD_, RS, RT, RD);
2502 :function:::void:do_or:int rs, int rt, int rd
2504 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2505 GPR[rd] = (GPR[rs] | GPR[rt]);
2506 TRACE_ALU_RESULT (GPR[rd]);
2509 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2510 "or r<RD>, r<RS>, r<RT>"
2522 do_or (SD_, RS, RT, RD);
2527 :function:::void:do_ori:int rs, int rt, unsigned immediate
2529 TRACE_ALU_INPUT2 (GPR[rs], immediate);
2530 GPR[rt] = (GPR[rs] | immediate);
2531 TRACE_ALU_RESULT (GPR[rt]);
2534 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2535 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2547 do_ori (SD_, RS, RT, IMMEDIATE);
2551 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2552 "pref <HINT>, <OFFSET>(r<BASE>)"
2559 address_word base = GPR[BASE];
2560 address_word offset = EXTEND16 (OFFSET);
2562 address_word vaddr = loadstore_ea (SD_, base, offset);
2566 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2567 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2573 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2575 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2576 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2577 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2584 vaddr = loadstore_ea (SD_, base, offset);
2585 if ((vaddr & access) != 0)
2587 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2589 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2590 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2591 byte = ((vaddr & mask) ^ bigendiancpu);
2592 memval = (word << (8 * byte));
2593 StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2596 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2598 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2599 address_word reverseendian = (ReverseEndian ? -1 : 0);
2600 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2610 vaddr = loadstore_ea (SD_, base, offset);
2611 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2612 paddr = (paddr ^ (reverseendian & mask));
2613 if (BigEndianMem == 0)
2614 paddr = paddr & ~access;
2616 /* compute where within the word/mem we are */
2617 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2618 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2619 nr_lhs_bits = 8 * byte + 8;
2620 nr_rhs_bits = 8 * access - 8 * byte;
2621 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2622 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2623 (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2624 (long) ((unsigned64) paddr >> 32), (long) paddr,
2625 word, byte, nr_lhs_bits, nr_rhs_bits); */
2629 memval = (rt >> nr_rhs_bits);
2633 memval = (rt << nr_lhs_bits);
2635 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2636 (long) ((unsigned64) rt >> 32), (long) rt,
2637 (long) ((unsigned64) memval >> 32), (long) memval); */
2638 StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2641 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2643 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2644 address_word reverseendian = (ReverseEndian ? -1 : 0);
2645 address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2652 vaddr = loadstore_ea (SD_, base, offset);
2653 AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2654 paddr = (paddr ^ (reverseendian & mask));
2655 if (BigEndianMem != 0)
2657 byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2658 memval = (rt << (byte * 8));
2659 StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2663 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2664 "sb r<RT>, <OFFSET>(r<BASE>)"
2676 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2680 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2681 "sc r<RT>, <OFFSET>(r<BASE>)"
2691 unsigned32 instruction = instruction_0;
2692 address_word base = GPR[BASE];
2693 address_word offset = EXTEND16 (OFFSET);
2695 address_word vaddr = loadstore_ea (SD_, base, offset);
2698 if ((vaddr & 3) != 0)
2700 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2704 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2706 unsigned64 memval = 0;
2707 unsigned64 memval1 = 0;
2708 unsigned64 mask = 0x7;
2710 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2711 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2712 memval = ((unsigned64) GPR[RT] << (8 * byte));
2715 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2724 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2725 "scd r<RT>, <OFFSET>(r<BASE>)"
2733 address_word base = GPR[BASE];
2734 address_word offset = EXTEND16 (OFFSET);
2735 check_u64 (SD_, instruction_0);
2737 address_word vaddr = loadstore_ea (SD_, base, offset);
2740 if ((vaddr & 7) != 0)
2742 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2746 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2748 unsigned64 memval = 0;
2749 unsigned64 memval1 = 0;
2753 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2762 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2763 "sd r<RT>, <OFFSET>(r<BASE>)"
2771 check_u64 (SD_, instruction_0);
2772 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2776 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2777 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2787 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2791 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2792 "sdl r<RT>, <OFFSET>(r<BASE>)"
2800 check_u64 (SD_, instruction_0);
2801 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2805 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2806 "sdr r<RT>, <OFFSET>(r<BASE>)"
2814 check_u64 (SD_, instruction_0);
2815 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2819 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2820 "sh r<RT>, <OFFSET>(r<BASE>)"
2832 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2836 :function:::void:do_sll:int rt, int rd, int shift
2838 unsigned32 temp = (GPR[rt] << shift);
2839 TRACE_ALU_INPUT2 (GPR[rt], shift);
2840 GPR[rd] = EXTEND32 (temp);
2841 TRACE_ALU_RESULT (GPR[rd]);
2844 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2845 "nop":RD == 0 && RT == 0 && SHIFT == 0
2846 "sll r<RD>, r<RT>, <SHIFT>"
2856 /* Skip shift for NOP, so that there won't be lots of extraneous
2858 if (RD != 0 || RT != 0 || SHIFT != 0)
2859 do_sll (SD_, RT, RD, SHIFT);
2862 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2863 "nop":RD == 0 && RT == 0 && SHIFT == 0
2864 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2865 "sll r<RD>, r<RT>, <SHIFT>"
2869 /* Skip shift for NOP and SSNOP, so that there won't be lots of
2870 extraneous trace output. */
2871 if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2872 do_sll (SD_, RT, RD, SHIFT);
2876 :function:::void:do_sllv:int rs, int rt, int rd
2878 int s = MASKED (GPR[rs], 4, 0);
2879 unsigned32 temp = (GPR[rt] << s);
2880 TRACE_ALU_INPUT2 (GPR[rt], s);
2881 GPR[rd] = EXTEND32 (temp);
2882 TRACE_ALU_RESULT (GPR[rd]);
2885 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2886 "sllv r<RD>, r<RT>, r<RS>"
2898 do_sllv (SD_, RS, RT, RD);
2902 :function:::void:do_slt:int rs, int rt, int rd
2904 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2905 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2906 TRACE_ALU_RESULT (GPR[rd]);
2909 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2910 "slt r<RD>, r<RS>, r<RT>"
2922 do_slt (SD_, RS, RT, RD);
2926 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2928 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2929 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2930 TRACE_ALU_RESULT (GPR[rt]);
2933 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2934 "slti r<RT>, r<RS>, <IMMEDIATE>"
2946 do_slti (SD_, RS, RT, IMMEDIATE);
2950 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2952 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2953 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2954 TRACE_ALU_RESULT (GPR[rt]);
2957 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2958 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2970 do_sltiu (SD_, RS, RT, IMMEDIATE);
2975 :function:::void:do_sltu:int rs, int rt, int rd
2977 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2978 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2979 TRACE_ALU_RESULT (GPR[rd]);
2982 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2983 "sltu r<RD>, r<RS>, r<RT>"
2995 do_sltu (SD_, RS, RT, RD);
2999 :function:::void:do_sra:int rt, int rd, int shift
3001 signed32 temp = (signed32) GPR[rt] >> shift;
3002 if (NotWordValue (GPR[rt]))
3004 TRACE_ALU_INPUT2 (GPR[rt], shift);
3005 GPR[rd] = EXTEND32 (temp);
3006 TRACE_ALU_RESULT (GPR[rd]);
3009 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3010 "sra r<RD>, r<RT>, <SHIFT>"
3022 do_sra (SD_, RT, RD, SHIFT);
3027 :function:::void:do_srav:int rs, int rt, int rd
3029 int s = MASKED (GPR[rs], 4, 0);
3030 signed32 temp = (signed32) GPR[rt] >> s;
3031 if (NotWordValue (GPR[rt]))
3033 TRACE_ALU_INPUT2 (GPR[rt], s);
3034 GPR[rd] = EXTEND32 (temp);
3035 TRACE_ALU_RESULT (GPR[rd]);
3038 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3039 "srav r<RD>, r<RT>, r<RS>"
3051 do_srav (SD_, RS, RT, RD);
3056 :function:::void:do_srl:int rt, int rd, int shift
3058 unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3059 if (NotWordValue (GPR[rt]))
3061 TRACE_ALU_INPUT2 (GPR[rt], shift);
3062 GPR[rd] = EXTEND32 (temp);
3063 TRACE_ALU_RESULT (GPR[rd]);
3066 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3067 "srl r<RD>, r<RT>, <SHIFT>"
3079 do_srl (SD_, RT, RD, SHIFT);
3083 :function:::void:do_srlv:int rs, int rt, int rd
3085 int s = MASKED (GPR[rs], 4, 0);
3086 unsigned32 temp = (unsigned32) GPR[rt] >> s;
3087 if (NotWordValue (GPR[rt]))
3089 TRACE_ALU_INPUT2 (GPR[rt], s);
3090 GPR[rd] = EXTEND32 (temp);
3091 TRACE_ALU_RESULT (GPR[rd]);
3094 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3095 "srlv r<RD>, r<RT>, r<RS>"
3107 do_srlv (SD_, RS, RT, RD);
3111 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3112 "sub r<RD>, r<RS>, r<RT>"
3124 if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3126 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3128 ALU32_BEGIN (GPR[RS]);
3129 ALU32_SUB (GPR[RT]);
3130 ALU32_END (GPR[RD]); /* This checks for overflow. */
3132 TRACE_ALU_RESULT (GPR[RD]);
3136 :function:::void:do_subu:int rs, int rt, int rd
3138 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3140 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3141 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3142 TRACE_ALU_RESULT (GPR[rd]);
3145 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3146 "subu r<RD>, r<RS>, r<RT>"
3158 do_subu (SD_, RS, RT, RD);
3162 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3163 "sw r<RT>, <OFFSET>(r<BASE>)"
3175 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3179 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3180 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3192 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3196 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3197 "swl r<RT>, <OFFSET>(r<BASE>)"
3209 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3213 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3214 "swr r<RT>, <OFFSET>(r<BASE>)"
3226 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3230 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3243 SyncOperation (STYPE);
3247 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3248 "syscall %#lx<CODE>"
3260 SignalException (SystemCall, instruction_0);
3264 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3275 if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3276 SignalException (Trap, instruction_0);
3280 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3281 "teqi r<RS>, <IMMEDIATE>"
3291 if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3292 SignalException (Trap, instruction_0);
3296 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3307 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3308 SignalException (Trap, instruction_0);
3312 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3313 "tgei r<RS>, <IMMEDIATE>"
3323 if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3324 SignalException (Trap, instruction_0);
3328 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3329 "tgeiu r<RS>, <IMMEDIATE>"
3339 if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3340 SignalException (Trap, instruction_0);
3344 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3355 if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3356 SignalException (Trap, instruction_0);
3360 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3371 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3372 SignalException (Trap, instruction_0);
3376 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3377 "tlti r<RS>, <IMMEDIATE>"
3387 if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3388 SignalException (Trap, instruction_0);
3392 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3393 "tltiu r<RS>, <IMMEDIATE>"
3403 if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3404 SignalException (Trap, instruction_0);
3408 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3419 if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3420 SignalException (Trap, instruction_0);
3424 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3435 if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3436 SignalException (Trap, instruction_0);
3440 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3441 "tne r<RS>, <IMMEDIATE>"
3451 if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3452 SignalException (Trap, instruction_0);
3456 :function:::void:do_xor:int rs, int rt, int rd
3458 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3459 GPR[rd] = GPR[rs] ^ GPR[rt];
3460 TRACE_ALU_RESULT (GPR[rd]);
3463 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3464 "xor r<RD>, r<RS>, r<RT>"
3476 do_xor (SD_, RS, RT, RD);
3480 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3482 TRACE_ALU_INPUT2 (GPR[rs], immediate);
3483 GPR[rt] = GPR[rs] ^ immediate;
3484 TRACE_ALU_RESULT (GPR[rt]);
3487 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3488 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3500 do_xori (SD_, RS, RT, IMMEDIATE);
3505 // MIPS Architecture:
3507 // FPU Instruction Set (COP1 & COP1X)
3515 case fmt_single: return "s";
3516 case fmt_double: return "d";
3517 case fmt_word: return "w";
3518 case fmt_long: return "l";
3519 default: return "?";
3529 default: return "?";
3549 :%s::::COND:int cond
3553 case 00: return "f";
3554 case 01: return "un";
3555 case 02: return "eq";
3556 case 03: return "ueq";
3557 case 04: return "olt";
3558 case 05: return "ult";
3559 case 06: return "ole";
3560 case 07: return "ule";
3561 case 010: return "sf";
3562 case 011: return "ngle";
3563 case 012: return "seq";
3564 case 013: return "ngl";
3565 case 014: return "lt";
3566 case 015: return "nge";
3567 case 016: return "le";
3568 case 017: return "ngt";
3569 default: return "?";
3576 // Check that the given FPU format is usable, and signal a
3577 // ReservedInstruction exception if not.
3580 // check_fmt checks that the format is single or double.
3581 :function:::void:check_fmt:int fmt, instruction_word insn
3593 if ((fmt != fmt_single) && (fmt != fmt_double))
3594 SignalException (ReservedInstruction, insn);
3597 // check_fmt_p checks that the format is single, double, or paired single.
3598 :function:::void:check_fmt_p:int fmt, instruction_word insn
3608 /* None of these ISAs support Paired Single, so just fall back to
3609 the single/double check. */
3610 check_fmt (SD_, fmt, insn);
3613 :function:::void:check_fmt_p:int fmt, instruction_word insn
3617 #if 0 /* XXX FIXME: FP code doesn't yet support paired single ops. */
3618 if ((fmt != fmt_single) && (fmt != fmt_double)
3619 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3620 SignalException (ReservedInstruction, insn);
3622 check_fmt (SD_, fmt, insn);
3629 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3630 // exception if not.
3633 :function:::void:check_fpu:
3645 if (! COP_Usable (1))
3646 SignalExceptionCoProcessorUnusable (1);
3650 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3651 "abs.%s<FMT> f<FD>, f<FS>"
3665 check_fmt_p (SD_, fmt, instruction_0);
3666 StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
3671 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3672 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3686 check_fmt_p (SD_, fmt, instruction_0);
3687 StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3697 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3698 "bc1%s<TF>%s<ND> <OFFSET>"
3704 check_branch_bug ();
3705 TRACE_BRANCH_INPUT (PREVCOC1());
3706 if (PREVCOC1() == TF)
3708 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3709 TRACE_BRANCH_RESULT (dest);
3710 mark_branch_bug (dest);
3715 TRACE_BRANCH_RESULT (0);
3716 NULLIFY_NEXT_INSTRUCTION ();
3720 TRACE_BRANCH_RESULT (NIA);
3724 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3725 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3726 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3736 check_branch_bug ();
3737 if (GETFCC(CC) == TF)
3739 address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3740 mark_branch_bug (dest);
3745 NULLIFY_NEXT_INSTRUCTION ();
3750 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3751 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3758 check_fmt_p (SD_, fmt, instruction_0);
3759 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
3760 TRACE_ALU_RESULT (ValueFCR (31));
3763 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3764 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3765 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3776 check_fmt_p (SD_, fmt, instruction_0);
3777 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
3778 TRACE_ALU_RESULT (ValueFCR (31));
3782 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3783 "ceil.l.%s<FMT> f<FD>, f<FS>"
3794 check_fmt (SD_, fmt, instruction_0);
3795 StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
3799 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3812 check_fmt (SD_, fmt, instruction_0);
3813 StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
3817 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
3825 PENDING_FILL (RT, EXTEND32 (FCR0));
3827 PENDING_FILL (RT, EXTEND32 (FCR31));
3831 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
3839 if (FS == 0 || FS == 31)
3841 unsigned_word fcr = ValueFCR (FS);
3842 TRACE_ALU_INPUT1 (fcr);
3846 TRACE_ALU_RESULT (GPR[RT]);
3849 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
3856 if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
3858 unsigned_word fcr = ValueFCR (FS);
3859 TRACE_ALU_INPUT1 (fcr);
3863 TRACE_ALU_RESULT (GPR[RT]);
3866 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
3874 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
3878 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
3886 TRACE_ALU_INPUT1 (GPR[RT]);
3888 StoreFCR (FS, GPR[RT]);
3892 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
3899 TRACE_ALU_INPUT1 (GPR[RT]);
3900 if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
3901 StoreFCR (FS, GPR[RT]);
3907 // FIXME: Does not correctly differentiate between mips*
3909 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3910 "cvt.d.%s<FMT> f<FD>, f<FS>"
3925 if ((fmt == fmt_double) | 0)
3926 SignalException (ReservedInstruction, instruction_0);
3928 StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
3933 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3934 "cvt.l.%s<FMT> f<FD>, f<FS>"
3946 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3947 SignalException (ReservedInstruction, instruction_0);
3949 StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
3955 // FIXME: Does not correctly differentiate between mips*
3957 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3958 "cvt.s.%s<FMT> f<FD>, f<FS>"
3973 if ((fmt == fmt_single) | 0)
3974 SignalException (ReservedInstruction, instruction_0);
3976 StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
3981 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
3982 "cvt.w.%s<FMT> f<FD>, f<FS>"
3997 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
3998 SignalException (ReservedInstruction, instruction_0);
4000 StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
4005 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4006 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4020 check_fmt (SD_, fmt, instruction_0);
4021 StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4025 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4026 "dmfc1 r<RT>, f<FS>"
4031 check_u64 (SD_, instruction_0);
4032 if (SizeFGR () == 64)
4034 else if ((FS & 0x1) == 0)
4035 v = SET64HI (FGR[FS+1]) | FGR[FS];
4037 v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4038 PENDING_FILL (RT, v);
4039 TRACE_ALU_RESULT (v);
4042 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4043 "dmfc1 r<RT>, f<FS>"
4052 check_u64 (SD_, instruction_0);
4053 if (SizeFGR () == 64)
4055 else if ((FS & 0x1) == 0)
4056 GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4058 GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4059 TRACE_ALU_RESULT (GPR[RT]);
4063 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4064 "dmtc1 r<RT>, f<FS>"
4069 check_u64 (SD_, instruction_0);
4070 if (SizeFGR () == 64)
4071 PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4072 else if ((FS & 0x1) == 0)
4074 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4075 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4079 TRACE_FP_RESULT (GPR[RT]);
4082 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4083 "dmtc1 r<RT>, f<FS>"
4092 check_u64 (SD_, instruction_0);
4093 if (SizeFGR () == 64)
4094 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4095 else if ((FS & 0x1) == 0)
4096 StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4102 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4103 "floor.l.%s<FMT> f<FD>, f<FS>"
4114 check_fmt (SD_, fmt, instruction_0);
4115 StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
4119 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4120 "floor.w.%s<FMT> f<FD>, f<FS>"
4133 check_fmt (SD_, fmt, instruction_0);
4134 StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
4138 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
4139 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4151 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4155 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4156 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4163 check_u64 (SD_, instruction_0);
4164 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4169 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4170 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4183 COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4187 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4188 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4195 check_u64 (SD_, instruction_0);
4196 COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4201 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
4202 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4210 check_u64 (SD_, instruction_0);
4211 check_fmt_p (SD_, fmt, instruction_0);
4212 StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4213 ValueFPR (FR, fmt), fmt));
4217 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4225 v = EXTEND32 (FGR[FS]);
4226 PENDING_FILL (RT, v);
4227 TRACE_ALU_RESULT (v);
4230 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4241 GPR[RT] = EXTEND32 (FGR[FS]);
4242 TRACE_ALU_RESULT (GPR[RT]);
4246 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4247 "mov.%s<FMT> f<FD>, f<FS>"
4261 check_fmt_p (SD_, fmt, instruction_0);
4262 StoreFPR(FD,fmt,ValueFPR(FS,fmt));
4268 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4269 "mov%s<TF> r<RD>, r<RS>, <CC>"
4277 if (GETFCC(CC) == TF)
4284 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4285 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4295 if (GETFCC(CC) == TF)
4296 StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4298 StoreFPR (FD, fmt, ValueFPR (FD, fmt));
4303 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4304 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4313 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4315 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4322 // MOVT.fmt see MOVtf.fmt
4326 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4327 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4336 StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4338 StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4342 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
4343 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4351 check_u64 (SD_, instruction_0);
4352 check_fmt_p (SD_, fmt, instruction_0);
4353 StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4354 ValueFPR (FR, fmt), fmt));
4358 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4365 if (SizeFGR () == 64)
4366 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4368 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4369 TRACE_FP_RESULT (GPR[RT]);
4372 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4383 StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4387 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4388 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4402 check_fmt_p (SD_, fmt, instruction_0);
4403 StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4407 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4408 "neg.%s<FMT> f<FD>, f<FS>"
4422 check_fmt_p (SD_, fmt, instruction_0);
4423 StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
4427 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
4428 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4436 check_u64 (SD_, instruction_0);
4437 check_fmt_p (SD_, fmt, instruction_0);
4438 StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4439 ValueFPR (FR, fmt), fmt));
4443 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
4444 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4452 check_u64 (SD_, instruction_0);
4453 check_fmt_p (SD_, fmt, instruction_0);
4454 StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4455 ValueFPR (FR, fmt), fmt));
4459 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4460 "prefx <HINT>, r<INDEX>(r<BASE>)"
4466 address_word base = GPR[BASE];
4467 address_word index = GPR[INDEX];
4469 address_word vaddr = loadstore_ea (SD_, base, index);
4472 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4473 Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4477 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4478 "recip.%s<FMT> f<FD>, f<FS>"
4486 check_fmt (SD_, fmt, instruction_0);
4487 StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
4491 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4492 "round.l.%s<FMT> f<FD>, f<FS>"
4503 check_fmt (SD_, fmt, instruction_0);
4504 StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
4508 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4509 "round.w.%s<FMT> f<FD>, f<FS>"
4522 check_fmt (SD_, fmt, instruction_0);
4523 StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
4527 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4531 "rsqrt.%s<FMT> f<FD>, f<FS>"
4536 check_fmt (SD_, fmt, instruction_0);
4537 StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
4541 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
4542 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4554 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4558 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4559 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4566 check_u64 (SD_, instruction_0);
4567 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4571 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4572 "sqrt.%s<FMT> f<FD>, f<FS>"
4585 check_fmt (SD_, fmt, instruction_0);
4586 StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
4590 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4591 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4605 check_fmt_p (SD_, fmt, instruction_0);
4606 StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4611 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4612 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4624 address_word base = GPR[BASE];
4625 address_word offset = EXTEND16 (OFFSET);
4628 address_word vaddr = loadstore_ea (SD_, base, offset);
4631 if ((vaddr & 3) != 0)
4633 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4637 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4640 uword64 memval1 = 0;
4641 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4642 address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4643 address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4645 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4646 byte = ((vaddr & mask) ^ bigendiancpu);
4647 memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4648 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4655 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4656 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4663 address_word base = GPR[BASE];
4664 address_word index = GPR[INDEX];
4666 check_u64 (SD_, instruction_0);
4668 address_word vaddr = loadstore_ea (SD_, base, index);
4671 if ((vaddr & 3) != 0)
4673 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4677 if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4679 unsigned64 memval = 0;
4680 unsigned64 memval1 = 0;
4681 unsigned64 mask = 0x7;
4683 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4684 byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4685 memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4687 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4695 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4696 "trunc.l.%s<FMT> f<FD>, f<FS>"
4707 check_fmt (SD_, fmt, instruction_0);
4708 StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
4712 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4713 "trunc.w.%s<FMT> f<FD>, f<FS>"
4726 check_fmt (SD_, fmt, instruction_0);
4727 StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
4732 // MIPS Architecture:
4734 // System Control Instruction Set (COP0)
4738 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4750 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4752 // stub needed for eCos as tx39 hardware bug workaround
4759 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4772 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4784 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4797 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4798 "cache <OP>, <OFFSET>(r<BASE>)"
4808 address_word base = GPR[BASE];
4809 address_word offset = EXTEND16 (OFFSET);
4811 address_word vaddr = loadstore_ea (SD_, base, offset);
4814 if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4815 CacheOp(OP,vaddr,paddr,instruction_0);
4820 010000,1,0000000000000000000,111001:COP0:32::DI
4831 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4832 "dmfc0 r<RT>, r<RD>"
4838 check_u64 (SD_, instruction_0);
4839 DecodeCoproc (instruction_0);
4843 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4844 "dmtc0 r<RT>, r<RD>"
4850 check_u64 (SD_, instruction_0);
4851 DecodeCoproc (instruction_0);
4855 010000,1,0000000000000000000,111000:COP0:32::EI
4867 010000,1,0000000000000000000,011000:COP0:32::ERET
4877 if (SR & status_ERL)
4879 /* Oops, not yet available */
4880 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4892 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4893 "mfc0 r<RT>, r<RD> # <REGX>"
4905 TRACE_ALU_INPUT0 ();
4906 DecodeCoproc (instruction_0);
4907 TRACE_ALU_RESULT (GPR[RT]);
4910 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4911 "mtc0 r<RT>, r<RD> # <REGX>"
4923 DecodeCoproc (instruction_0);
4927 010000,1,0000000000000000000,010000:COP0:32::RFE
4938 DecodeCoproc (instruction_0);
4942 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4943 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
4954 DecodeCoproc (instruction_0);
4959 010000,1,0000000000000000000,001000:COP0:32::TLBP
4972 010000,1,0000000000000000000,000001:COP0:32::TLBR
4985 010000,1,0000000000000000000,000010:COP0:32::TLBWI
4998 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5012 :include:::mdmx.igen