sim/mips/sb1.igen

   1 // -*- C -*-
   2
   3 // Simulator definition for the Broadcom SiByte SB-1 CPU extensions.
   4 // Copyright (C) 2002 Free Software Foundation, Inc.
   5 // Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
   6 // Corporation (SiByte).
   7 //
   8 // This file is part of GDB, the GNU debugger.
   9 //
  10 // This program is free software; you can redistribute it and/or modify
  11 // it under the terms of the GNU General Public License as published by
  12 // the Free Software Foundation; either version 2, or (at your option)
  13 // any later version.
  14 //
  15 // This program is distributed in the hope that it will be useful,
  16 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 // GNU General Public License for more details.
  19 //
  20 // You should have received a copy of the GNU General Public License along
  21 // with this program; if not, write to the Free Software Foundation, Inc.,
  22 // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23
  24
  25 //  MDMX ASE Instructions
  26 //  ---------------------
  27 //
  28 //  The SB-1 implements the format OB subset of MDMX
  29 //  and has three additions (pavg, pabsdiff, pabsdifc).
  30 //  In addition, there are a couple of partial-decoding
  31 //  issues for the read/write accumulator instructions.
  32 //
  33 //  This code is structured so that mdmx.igen can be used by
  34 //  selecting the allowed instructions either via model, or by
  35 //  using check_mdmx_fmtsel and check_mdmx_fmtop to cause an
  36 //  exception if the instruction is not allowed.
  37
  38
  39 :function:::void:check_mdmx:instruction_word insn
  40 *sb1:
  41 {
  42   if (!COP_Usable(1))
  43     SignalExceptionCoProcessorUnusable(1);
  44   if ((SR & status_MX) == 0)
  45     SignalExceptionMDMX();
  46   check_u64 (SD_, insn);
  47 }
  48
  49 :function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
  50 *sb1:
  51 {
  52   switch (fmtsel & 0x03)
  53     {
  54     case 0x00:     /* ob */
  55     case 0x02:
  56       return 1;
  57     case 0x01:     /* qh */
  58     case 0x03:     /* UNPREDICTABLE */
  59       SignalException (ReservedInstruction, insn);
  60       return 0;
  61     }
  62   return 0;
  63 }
  64
  65 :function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
  66 *sb1:
  67 {
  68   switch (fmtop & 0x01)
  69     {
  70     case 0x00:     /* ob */
  71       return 1;
  72     case 0x01:     /* qh */
  73       SignalException (ReservedInstruction, insn);
  74       return 0;
  75     }
  76   return 0;
  77 }
  78
  79
  80 011110,10,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.sb1.fmt
  81 "rach.?<X>.%s<FMTOP> v<VD>"
  82 *sb1:
  83 {
  84   check_mdmx (SD_, instruction_0);
  85   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
  86   /* No op.  */
  87 }
  88
  89
  90 011110,00,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.sb1.fmt
  91 "racl.?<X>.%s<FMTOP> v<VD>"
  92 *sb1:
  93 {
  94   check_mdmx (SD_, instruction_0);
  95   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
  96   /* No op.  */
  97 }
  98
  99
 100 011110,01,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.sb1.fmt
 101 "racm.?<X>.%s<FMTOP> v<VD>"
 102 *sb1:
 103 {
 104   check_mdmx (SD_, instruction_0);
 105   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 106   /* No op.  */
 107 }
 108
 109
 110 011110,2.X1!0!1!2,2.X2,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RAC.sb1.fmt
 111 "rac?<X1>.?<X2> v<VD>"
 112 *sb1:
 113 {
 114   check_mdmx (SD_, instruction_0);
 115   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 116   /* No op.  */
 117 }
 118
 119
 120 011110,10,2.X!0,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.sb1.fmt
 121 "wach.?<X>.%s<FMTOP> v<VS>"
 122 *sb1:
 123 {
 124   check_mdmx (SD_, instruction_0);
 125   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 126   /* No op.  */
 127 }
 128
 129
 130 011110,00,2.X!0,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.sb1.fmt
 131 "wacl.?<X>.%s<FMTOP> v<VS>,v<VT>"
 132 *sb1:
 133 {
 134   check_mdmx (SD_, instruction_0);
 135   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 136   /* No op.  */
 137 }
 138
 139
 140 011110,2.X1!0!2,2.X2,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WAC.sb1.fmt
 141 "wacl?<X1>.?<X2>.%s<FMTOP> v<VS>,v<VT>"
 142 *sb1:
 143 {
 144   check_mdmx (SD_, instruction_0);
 145   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 146   /* No op.  */
 147 }
 148
 149
 150 011110,5.FMTSEL,5.VT,5.VS,5.VD,001001:MDMX:64::PABSDIFF.fmt
 151 "pabsdiff.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
 152 *sb1:
 153 {
 154   check_mdmx (SD_, instruction_0);
 155   if (SR & status_SBX)
 156     {
 157       check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
 158       StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
 159     }
 160   else
 161     SignalException(ReservedInstruction, instruction_0);
 162 }
 163
 164
 165 011110,5.FMTSEL,5.VT,5.VS,00000,110101:MDMX:64::PABSDIFC.fmt
 166 "pabsdifc.%<FMTSEL> v<VS>,v<VT>"
 167 *sb1:
 168 {
 169   check_mdmx (SD_, instruction_0);
 170   if (SR & status_SBX)
 171     {
 172       check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
 173       MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
 174     }
 175   else
 176     SignalException(ReservedInstruction, instruction_0);
 177 }
 178
 179
 180 011110,5.FMTSEL,5.VT,5.VS,5.VD,001000:MDMX:64::PAVG.fmt
 181 "pavg.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
 182 *sb1:
 183 {
 184   check_mdmx (SD_, instruction_0);
 185   if (SR & status_SBX)
 186     {
 187       check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
 188       StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
 189     }
 190   else
 191     SignalException(ReservedInstruction, instruction_0);
 192 }