sim/mips/sb1.igen

   1 // -*- C -*-
   2
   3 // Simulator definition for the Broadcom SiByte SB-1 CPU extensions.
   4 // Copyright (C) 2002 Free Software Foundation, Inc.
   5 // Contributed by Broadcom Corporation (SiByte).
   6 //
   7 // This file is part of GDB, the GNU debugger.
   8 //
   9 // This program is free software; you can redistribute it and/or modify
  10 // it under the terms of the GNU General Public License as published by
  11 // the Free Software Foundation; either version 2, or (at your option)
  12 // any later version.
  13 //
  14 // This program is distributed in the hope that it will be useful,
  15 // but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 // GNU General Public License for more details.
  18 //
  19 // You should have received a copy of the GNU General Public License along
  20 // with this program; if not, write to the Free Software Foundation, Inc.,
  21 // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23
  24 //  MDMX ASE Instructions
  25 //  ---------------------
  26 //
  27 //  The SB-1 implements the format OB subset of MDMX
  28 //  and has three additions (pavg, pabsdiff, pabsdifc).
  29 //  In addition, there are a couple of partial-decoding
  30 //  issues for the read/write accumulator instructions.
  31 //
  32 //  This code is structured so that mdmx.igen can be used by
  33 //  selecting the allowed instructions either via model, or by
  34 //  using check_mdmx_fmtsel and check_mdmx_fmtop to cause an
  35 //  exception if the instruction is not allowed.
  36
  37
  38 :function:::void:check_mdmx:instruction_word insn
  39 *sb1:
  40 {
  41   if (!COP_Usable(1))
  42     SignalExceptionCoProcessorUnusable(1);
  43   if ((SR & status_MX) == 0)
  44     SignalExceptionMDMX();
  45   check_u64 (SD_, insn);
  46 }
  47
  48 :function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
  49 *sb1:
  50 {
  51   switch (fmtsel & 0x03)
  52     {
  53     case 0x00:     /* ob */
  54     case 0x02:
  55       return 1;
  56     case 0x01:     /* qh */
  57     case 0x03:     /* UNPREDICTABLE */
  58       SignalException (ReservedInstruction, insn);
  59       return 0;
  60     }
  61   return 0;
  62 }
  63
  64 :function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
  65 *sb1:
  66 {
  67   switch (fmtop & 0x01)
  68     {
  69     case 0x00:     /* ob */
  70       return 1;
  71     case 0x01:     /* qh */
  72       SignalException (ReservedInstruction, insn);
  73       return 0;
  74     }
  75   return 0;
  76 }
  77
  78
  79 011110,10,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.sb1.fmt
  80 "rach.?<X>.%s<FMTOP> v<VD>"
  81 *sb1:
  82 {
  83   check_mdmx (SD_, instruction_0);
  84   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
  85   /* No op.  */
  86 }
  87
  88
  89 011110,00,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.sb1.fmt
  90 "racl.?<X>.%s<FMTOP> v<VD>"
  91 *sb1:
  92 {
  93   check_mdmx (SD_, instruction_0);
  94   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
  95   /* No op.  */
  96 }
  97
  98
  99 011110,01,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.sb1.fmt
 100 "racm.?<X>.%s<FMTOP> v<VD>"
 101 *sb1:
 102 {
 103   check_mdmx (SD_, instruction_0);
 104   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 105   /* No op.  */
 106 }
 107
 108
 109 011110,2.X1!0!1!2,2.X2,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RAC.sb1.fmt
 110 "rac?<X1>.?<X2> v<VD>"
 111 *sb1:
 112 {
 113   check_mdmx (SD_, instruction_0);
 114   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 115   /* No op.  */
 116 }
 117
 118
 119 011110,10,2.X!0,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.sb1.fmt
 120 "wach.?<X>.%s<FMTOP> v<VS>"
 121 *sb1:
 122 {
 123   check_mdmx (SD_, instruction_0);
 124   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 125   /* No op.  */
 126 }
 127
 128
 129 011110,00,2.X!0,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.sb1.fmt
 130 "wacl.?<X>.%s<FMTOP> v<VS>,v<VT>"
 131 *sb1:
 132 {
 133   check_mdmx (SD_, instruction_0);
 134   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 135   /* No op.  */
 136 }
 137
 138
 139 011110,2.X1!0!2,2.X2,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WAC.sb1.fmt
 140 "wacl?<X1>.?<X2>.%s<FMTOP> v<VS>,v<VT>"
 141 *sb1:
 142 {
 143   check_mdmx (SD_, instruction_0);
 144   check_mdmx_fmtop (SD_, instruction_0, FMTOP);
 145   /* No op.  */
 146 }
 147
 148
 149 011110,5.FMTSEL,5.VT,5.VS,5.VD,001001:MDMX:64::PABSDIFF.fmt
 150 "pabsdiff.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
 151 *sb1:
 152 {
 153   check_mdmx (SD_, instruction_0);
 154   if (SR & status_SBX)
 155     {
 156       check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
 157       StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
 158     }
 159   else
 160     SignalException(ReservedInstruction, instruction_0);
 161 }
 162
 163
 164 011110,5.FMTSEL,5.VT,5.VS,00000,110101:MDMX:64::PABSDIFC.fmt
 165 "pabsdifc.%<FMTSEL> v<VS>,v<VT>"
 166 *sb1:
 167 {
 168   check_mdmx (SD_, instruction_0);
 169   if (SR & status_SBX)
 170     {
 171       check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
 172       MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
 173     }
 174   else
 175     SignalException(ReservedInstruction, instruction_0);
 176 }
 177
 178
 179 011110,5.FMTSEL,5.VT,5.VS,5.VD,001000:MDMX:64::PAVG.fmt
 180 "pavg.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
 181 *sb1:
 182 {
 183   check_mdmx (SD_, instruction_0);
 184   if (SR & status_SBX)
 185     {
 186       check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
 187       StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
 188     }
 189   else
 190     SignalException(ReservedInstruction, instruction_0);
 191 }