sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35
  36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  38
  39 #include "sim-basics.h"
  40
  41 typedef address_word sim_cia;
  42
  43 #include "sim-base.h"
  44
  45
  46 /* Deprecated macros and types for manipulating 64bit values.  Use
  47    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  48
  49 typedef signed64 word64;
  50 typedef unsigned64 uword64;
  51
  52 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  53 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  54 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  55 #define SET64HI(t)      (((uword64)(t))<<32)
  56 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  57 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  58
  59 /* Check if a value will fit within a halfword: */
  60 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  61
  62
  63
  64 /* Floating-point operations: */
  65
  66 #include "sim-fpu.h"
  67
  68 /* FPU registers must be one of the following types. All other values
  69    are reserved (and undefined). */
  70 typedef enum {
  71  fmt_single  = 0,
  72  fmt_double  = 1,
  73  fmt_word    = 4,
  74  fmt_long    = 5,
  75  /* The following are well outside the normal acceptable format
  76     range, and are used in the register status vector. */
  77  fmt_unknown       = 0x10000000,
  78  fmt_uninterpreted = 0x20000000,
  79  fmt_uninterpreted_32 = 0x40000000,
  80  fmt_uninterpreted_64 = 0x80000000U,
  81 } FP_formats;
  82
  83 /* Macro to update FPSR condition-code field. This is complicated by
  84    the fact that there is a hole in the index range of the bits within
  85    the FCSR register. Also, the number of bits visible depends on the
  86    MIPS ISA version being supported. */
  87
  88 #define SETFCC(cc,v) {\
  89   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
  90   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
  91 }
  92 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
  93
  94 /* This should be the COC1 value at the start of the preceding
  95    instruction: */
  96 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
  97
  98 #ifdef TARGET_ENABLE_FR
  99 /* FIXME: this should be enabled for all targets, but needs testing first. */
 100 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
 101    ? ((SR & status_FR) ? 64 : 32) \
 102    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
 103 #else
 104 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 105 #endif
 106
 107 /* Standard FCRS bits: */
 108 #define IR (0) /* Inexact Result */
 109 #define UF (1) /* UnderFlow */
 110 #define OF (2) /* OverFlow */
 111 #define DZ (3) /* Division by Zero */
 112 #define IO (4) /* Invalid Operation */
 113 #define UO (5) /* Unimplemented Operation */
 114
 115 /* Get masks for individual flags: */
 116 #if 1 /* SAFE version */
 117 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 118 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 119 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 120 #else
 121 #define FP_FLAGS(b)  (1 << ((b) + 2))
 122 #define FP_ENABLE(b) (1 << ((b) + 7))
 123 #define FP_CAUSE(b)  (1 << ((b) + 12))
 124 #endif
 125
 126 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 127
 128 #define FP_MASK_RM    (0x3)
 129 #define FP_SH_RM      (0)
 130 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 131 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 132 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 133 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 134 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 135
 136
 137
 138
 139
 140
 141 /* HI/LO register accesses */
 142
 143 /* For some MIPS targets, the HI/LO registers have certain timing
 144    restrictions in that, for instance, a read of a HI register must be
 145    separated by at least three instructions from a preceeding read.
 146
 147    The struct below is used to record the last access by each of A MT,
 148    MF or other OP instruction to a HI/LO register.  See mips.igen for
 149    more details. */
 150
 151 typedef struct _hilo_access {
 152   signed64 timestamp;
 153   address_word cia;
 154 } hilo_access;
 155
 156 typedef struct _hilo_history {
 157   hilo_access mt;
 158   hilo_access mf;
 159   hilo_access op;
 160 } hilo_history;
 161
 162
 163
 164
 165 /* Integer ALU operations: */
 166
 167 #include "sim-alu.h"
 168
 169 #define ALU32_END(ANS) \
 170   if (ALU32_HAD_OVERFLOW) \
 171     SignalExceptionIntegerOverflow (); \
 172   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 173
 174
 175 #define ALU64_END(ANS) \
 176   if (ALU64_HAD_OVERFLOW) \
 177     SignalExceptionIntegerOverflow (); \
 178   (ANS) = ALU64_OVERFLOW_RESULT;
 179
 180
 181
 182
 183
 184 /* The following is probably not used for MIPS IV onwards: */
 185 /* Slots for delayed register updates. For the moment we just have a
 186    fixed number of slots (rather than a more generic, dynamic
 187    system). This keeps the simulator fast. However, we only allow
 188    for the register update to be delayed for a single instruction
 189    cycle. */
 190 #define PSLOTS (8) /* Maximum number of instruction cycles */
 191
 192 typedef struct _pending_write_queue {
 193   int in;
 194   int out;
 195   int total;
 196   int slot_delay[PSLOTS];
 197   int slot_size[PSLOTS];
 198   int slot_bit[PSLOTS];
 199   void *slot_dest[PSLOTS];
 200   unsigned64 slot_value[PSLOTS];
 201 } pending_write_queue;
 202
 203 #ifndef PENDING_TRACE
 204 #define PENDING_TRACE 0
 205 #endif
 206 #define PENDING_IN ((CPU)->pending.in)
 207 #define PENDING_OUT ((CPU)->pending.out)
 208 #define PENDING_TOTAL ((CPU)->pending.total)
 209 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 210 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 211 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 212 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 213 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 214
 215 /* Invalidate the pending write queue, all pending writes are
 216    discarded. */
 217
 218 #define PENDING_INVALIDATE() \
 219 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 220
 221 /* Schedule a write to DEST for N cycles time.  For 64 bit
 222    destinations, schedule two writes.  For floating point registers,
 223    the caller should schedule a write to both the dest register and
 224    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 225    is updated. */
 226
 227 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 228   do {                                                                  \
 229     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 230       sim_engine_abort (SD, CPU, cia,                                   \
 231                         "PENDING_SCHED - buffer overflow\n");           \
 232     if (PENDING_TRACE)                                                  \
 233       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 234                       (unsigned long) cia, (unsigned long) &(DEST),     \
 235                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 236                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 237     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 238     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 239     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 240     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 241     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 242     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 243     PENDING_TOTAL += 1;                                                 \
 244   } while (0)
 245
 246 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 247 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 248
 249 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 250
 251 #define PENDING_FLUSH() abort () /* think about this one */
 252 #define PENDING_FP() abort () /* think about this one */
 253
 254 /* For backward compatibility */
 255 #define PENDING_FILL(R,VAL)                                             \
 256 do {                                                                    \
 257   if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR)                       \
 258     {                                                                   \
 259       PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1);                   \
 260       PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
 261     }                                                                   \
 262   else                                                                  \
 263     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 264 } while (0)
 265
 266
 267 enum float_operation
 268   {
 269     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 270     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 271     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 272   };
 273
 274
 275 /* The internal representation of an MDMX accumulator.
 276    Note that 24 and 48 bit accumulator elements are represented in
 277    32 or 64 bits.  Since the accumulators are 2's complement with
 278    overflow suppressed, high-order bits can be ignored in most contexts.  */
 279
 280 typedef signed32 signed24;
 281 typedef signed64 signed48;
 282
 283 typedef union {
 284   signed24  ob[8];
 285   signed48  qh[4];
 286 } MDMX_accumulator;
 287
 288
 289 /* Conventional system arguments.  */
 290 #define SIM_STATE  sim_cpu *cpu, address_word cia
 291 #define SIM_ARGS   CPU, cia
 292
 293 struct _sim_cpu {
 294
 295
 296   /* The following are internal simulator state variables: */
 297 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 298 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 299   address_word dspc;  /* delay-slot PC */
 300 #define DSPC ((CPU)->dspc)
 301
 302 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 303 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 304
 305
 306   /* State of the simulator */
 307   unsigned int state;
 308   unsigned int dsstate;
 309 #define STATE ((CPU)->state)
 310 #define DSSTATE ((CPU)->dsstate)
 311
 312 /* Flags in the "state" variable: */
 313 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 314 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 315 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 316 #define simPCOC0        (1 << 17) /* COC[1] from current */
 317 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 318 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 319 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 320 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 321 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 322
 323 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 324 #define ENGINE_ISSUE_PREFIX_HOOK() \
 325   { \
 326     /* Perform any pending writes */ \
 327     PENDING_TICK(); \
 328     /* Set previous flag, depending on current: */ \
 329     if (STATE & simPCOC0) \
 330      STATE |= simPCOC1; \
 331     else \
 332      STATE &= ~simPCOC1; \
 333     /* and update the current value: */ \
 334     if (GETFCC(0)) \
 335      STATE |= simPCOC0; \
 336     else \
 337      STATE &= ~simPCOC0; \
 338   }
 339 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 340
 341
 342 /* This is nasty, since we have to rely on matching the register
 343    numbers used by GDB. Unfortunately, depending on the MIPS target
 344    GDB uses different register numbers. We cannot just include the
 345    relevant "gdb/tm.h" link, since GDB may not be configured before
 346    the sim world, and also the GDB header file requires too much other
 347    state. */
 348
 349 #ifndef TM_MIPS_H
 350 #define LAST_EMBED_REGNUM (89)
 351 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 352
 353 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 354 #define FCRCS_REGNUM 70         /* FP control/status */
 355 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 356 #endif
 357
 358
 359 /* To keep this default simulator simple, and fast, we use a direct
 360    vector of registers. The internal simulator engine then uses
 361    manifests to access the correct slot. */
 362
 363   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 364
 365   int register_widths[NUM_REGS];
 366 #define REGISTERS       ((CPU)->registers)
 367
 368 #define GPR     (&REGISTERS[0])
 369 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 370
 371 #define LO      (REGISTERS[33])
 372 #define HI      (REGISTERS[34])
 373 #define PCIDX   37
 374 #define PC      (REGISTERS[PCIDX])
 375 #define CAUSE   (REGISTERS[36])
 376 #define SRIDX   (32)
 377 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 378 #define FCR0IDX  (71)
 379 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 380 #define FCR31IDX (70)
 381 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 382 #define FCSR    (FCR31)
 383 #define Debug   (REGISTERS[86])
 384 #define DEPC    (REGISTERS[87])
 385 #define EPC     (REGISTERS[88])
 386
 387   /* All internal state modified by signal_exception() that may need to be
 388      rolled back for passing moment-of-exception image back to gdb. */
 389   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 390   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 391   int exc_suspended;
 392
 393 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 394 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 395 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 396
 397   unsigned_word c0_config_reg;
 398 #define C0_CONFIG ((CPU)->c0_config_reg)
 399
 400 /* The following are pseudonyms for standard registers */
 401 #define ZERO    (REGISTERS[0])
 402 #define V0      (REGISTERS[2])
 403 #define A0      (REGISTERS[4])
 404 #define A1      (REGISTERS[5])
 405 #define A2      (REGISTERS[6])
 406 #define A3      (REGISTERS[7])
 407 #define T8IDX   24
 408 #define T8      (REGISTERS[T8IDX])
 409 #define SPIDX   29
 410 #define SP      (REGISTERS[SPIDX])
 411 #define RAIDX   31
 412 #define RA      (REGISTERS[RAIDX])
 413
 414   /* While space is allocated in the main registers arrray for some of
 415      the COP0 registers, that space isn't sufficient.  Unknown COP0
 416      registers overflow into the array below */
 417
 418 #define NR_COP0_GPR     32
 419   unsigned_word cop0_gpr[NR_COP0_GPR];
 420 #define COP0_GPR        ((CPU)->cop0_gpr)
 421 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 422
 423   /* While space is allocated for the floating point registers in the
 424      main registers array, they are stored separatly.  This is because
 425      their size may not necessarily match the size of either the
 426      general-purpose or system specific registers.  */
 427 #define NR_FGR    (32)
 428 #define FGR_BASE  FP0_REGNUM
 429   fp_word fgr[NR_FGR];
 430 #define FGR       ((CPU)->fgr)
 431
 432   /* Keep the current format state for each register: */
 433   FP_formats fpr_state[32];
 434 #define FPR_STATE ((CPU)->fpr_state)
 435
 436   pending_write_queue pending;
 437
 438   /* The MDMX accumulator (used only for MDMX ASE).  */
 439   MDMX_accumulator acc;
 440 #define ACC             ((CPU)->acc)
 441
 442   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 443      read-write instructions. It is set when a linked load occurs. It
 444      is tested and cleared by the conditional store. It is cleared
 445      (during other CPU operations) when a store to the location would
 446      no longer be atomic. In particular, it is cleared by exception
 447      return instructions. */
 448   int llbit;
 449 #define LLBIT ((CPU)->llbit)
 450
 451
 452 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 453    corruptions caused by using the HI or LO register too close to a
 454    following operation is spotted. See mips.igen for more details. */
 455
 456   hilo_history hi_history;
 457 #define HIHISTORY (&(CPU)->hi_history)
 458   hilo_history lo_history;
 459 #define LOHISTORY (&(CPU)->lo_history)
 460
 461 #define check_branch_bug()
 462 #define mark_branch_bug(TARGET)
 463
 464
 465
 466   sim_cpu_base base;
 467 };
 468
 469
 470 /* MIPS specific simulator watch config */
 471
 472 void watch_options_install PARAMS ((SIM_DESC sd));
 473
 474 struct swatch {
 475   sim_event *pc;
 476   sim_event *clock;
 477   sim_event *cycles;
 478 };
 479
 480
 481 /* FIXME: At present much of the simulator is still static */
 482 struct sim_state {
 483
 484   struct swatch watch;
 485
 486   sim_cpu cpu[MAX_NR_PROCESSORS];
 487 #if (WITH_SMP)
 488 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 489 #else
 490 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 491 #endif
 492
 493
 494   sim_state_base base;
 495 };
 496
 497
 498
 499 /* Status information: */
 500
 501 /* TODO : these should be the bitmasks for these bits within the
 502    status register. At the moment the following are VR4300
 503    bit-positions: */
 504 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 505 #define status_KSU_shift (3)            /* shift for field */
 506 #define ksu_kernel       (0x0)
 507 #define ksu_supervisor   (0x1)
 508 #define ksu_user         (0x2)
 509 #define ksu_unknown      (0x3)
 510
 511 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 512
 513 #define status_IE        (1 <<  0)      /* Interrupt enable */
 514 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 515 #define status_EXL       (1 <<  1)      /* Exception level */
 516 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 517 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 518 #define status_SR        (1 << 20)      /* soft reset or NMI */
 519 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 520 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 521 #define status_ERL       (1 <<  2)      /* Error level */
 522 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 523 #define status_RP        (1 << 27)      /* Reduced Power mode */
 524
 525 /* Specializations for TX39 family */
 526 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 527 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 528 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 529 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 530 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 531 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 532 #define status_IM_mask   (0xff)         /* Interrupt mask */
 533 #define status_IM_shift  (8)
 534 #define status_NMI       (1 << 20)      /* NMI */
 535 #define status_NMI       (1 << 20)      /* NMI */
 536
 537 /* Status bits used by MIPS32/MIPS64.  */
 538 #define status_UX        (1 <<  5)      /* 64-bit user addrs */
 539 #define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
 540 #define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
 541 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 542 #define status_PX        (1 << 23)      /* Enable 64 bit operations */
 543 #define status_MX        (1 << 24)      /* Enable MDMX resources */
 544 #define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
 545 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 546 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 547 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
 548 /* Bits reserved for implementations:  */
 549 #define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 550
 551 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 552 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 553 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 554 #define cause_CE_shift    28
 555 #define cause_EXC2_mask   0x00070000
 556 #define cause_EXC2_shift  16
 557 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 558 #define cause_SIOP        (1 << 12)     /* SIO pending */
 559 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 560 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 561
 562 #define cause_EXC_mask  (0x1c)          /* Exception code */
 563 #define cause_EXC_shift (2)
 564
 565 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 566 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 567 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 568 #define cause_IP_shift  (10)
 569
 570 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 571 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 572
 573
 574 /* NOTE: We keep the following status flags as bit values (1 for true,
 575    0 for false). This allows them to be used in binary boolean
 576    operations without worrying about what exactly the non-zero true
 577    value is. */
 578
 579 /* UserMode */
 580 #ifdef SUBTARGET_R3900
 581 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 582 #else
 583 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 584 #endif /* SUBTARGET_R3900 */
 585
 586 /* BigEndianMem */
 587 /* Hardware configuration. Affects endianness of LoadMemory and
 588    StoreMemory and the endianness of Kernel and Supervisor mode
 589    execution. The value is 0 for little-endian; 1 for big-endian. */
 590 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 591 /*(state & simBE) ? 1 : 0)*/
 592
 593 /* ReverseEndian */
 594 /* This mode is selected if in User mode with the RE bit being set in
 595    SR (Status Register). It reverses the endianness of load and store
 596    instructions. */
 597 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 598
 599 /* BigEndianCPU */
 600 /* The endianness for load and store instructions (0=little;1=big). In
 601    User mode this endianness may be switched by setting the state_RE
 602    bit in the SR register. Thus, BigEndianCPU may be computed as
 603    (BigEndianMem EOR ReverseEndian). */
 604 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 605
 606
 607
 608 /* Exceptions: */
 609
 610 /* NOTE: These numbers depend on the processor architecture being
 611    simulated: */
 612 enum ExceptionCause {
 613   Interrupt               = 0,
 614   TLBModification         = 1,
 615   TLBLoad                 = 2,
 616   TLBStore                = 3,
 617   AddressLoad             = 4,
 618   AddressStore            = 5,
 619   InstructionFetch        = 6,
 620   DataReference           = 7,
 621   SystemCall              = 8,
 622   BreakPoint              = 9,
 623   ReservedInstruction     = 10,
 624   CoProcessorUnusable     = 11,
 625   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 626   Trap                    = 13,
 627   FPE                     = 15,
 628   DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
 629   MDMX                    = 22,
 630   Watch                   = 23,
 631   MCheck                  = 24,
 632   CacheErr                = 30,
 633   NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
 634
 635
 636 /* The following exception code is actually private to the simulator
 637    world. It is *NOT* a processor feature, and is used to signal
 638    run-time errors in the simulator. */
 639   SimulatorFault          = 0xFFFFFFFF
 640 };
 641
 642 #define TLB_REFILL  (0)
 643 #define TLB_INVALID (1)
 644
 645
 646 /* The following break instructions are reserved for use by the
 647    simulator.  The first is used to halt the simulation.  The second
 648    is used by gdb for break-points.  NOTE: Care must be taken, since
 649    this value may be used in later revisions of the MIPS ISA. */
 650 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 651
 652 #define HALT_INSTRUCTION        (0x03ff000d)
 653 #define HALT_INSTRUCTION2       (0x0000ffcd)
 654
 655
 656 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 657 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 658
 659
 660
 661 void interrupt_event (SIM_DESC sd, void *data);
 662
 663 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 664 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 665 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 666 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 667 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 668 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 669 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 670 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 671 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 672 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 673 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
 674 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 675 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 676 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 677 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 678 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 679 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 680 #define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
 681 #define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
 682 #define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
 683 #define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
 684
 685 /* Co-processor accesses */
 686
 687 /* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
 688 #define COP_Usable(coproc_num)          (coproc_num == 1)
 689
 690 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 691 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 692 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 693 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 694
 695 #define COP_LW(coproc_num,coproc_reg,memword) \
 696 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 697 #define COP_LD(coproc_num,coproc_reg,memword) \
 698 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 699 #define COP_SW(coproc_num,coproc_reg) \
 700 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 701 #define COP_SD(coproc_num,coproc_reg) \
 702 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 703
 704
 705 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 706 #define DecodeCoproc(instruction) \
 707 decode_coproc (SD, CPU, cia, (instruction))
 708
 709 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 710
 711
 712 /* FPR access.  */
 713 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
 714 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
 715 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
 716 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
 717
 718
 719 /* FPU operations.  */
 720 int NaN (unsigned64 op, FP_formats fmt);
 721 int Less (unsigned64 op1, unsigned64 op2, FP_formats fmt);
 722 int Equal (unsigned64 op1, unsigned64 op2, FP_formats fmt);
 723 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
 724 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
 725 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
 726 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
 727 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 728 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
 729 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 730 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
 731 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 732 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
 733 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 734 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
 735 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
 736 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
 737 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 738 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
 739 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
 740 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
 741
 742
 743 /* MDMX access.  */
 744
 745 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 746 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
 747 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
 748
 749 #define fmt_mdmx fmt_uninterpreted
 750
 751 #define MX_VECT_AND  (0)
 752 #define MX_VECT_NOR  (1)
 753 #define MX_VECT_OR   (2)
 754 #define MX_VECT_XOR  (3)
 755 #define MX_VECT_SLL  (4)
 756 #define MX_VECT_SRL  (5)
 757 #define MX_VECT_ADD  (6)
 758 #define MX_VECT_SUB  (7)
 759 #define MX_VECT_MIN  (8)
 760 #define MX_VECT_MAX  (9)
 761 #define MX_VECT_MUL  (10)
 762 #define MX_VECT_MSGN (11)
 763 #define MX_VECT_SRA  (12)
 764 #define MX_VECT_ABSD (13)               /* SB-1 only.  */
 765 #define MX_VECT_AVG  (14)               /* SB-1 only.  */
 766
 767 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 768 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
 769 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
 770 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
 771 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
 772 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
 773 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
 774 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
 775 #define MX_Or(op1,vt,fmtsel)  mdmx_cpr_op(SIM_ARGS, MX_VECT_OR,  op1, vt, fmtsel)
 776 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
 777 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
 778 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
 779 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
 780 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
 781 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
 782 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
 783
 784 #define MX_C_EQ  0x1
 785 #define MX_C_LT  0x4
 786
 787 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 788 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
 789
 790 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 791 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
 792
 793 #define MX_VECT_ADDA  (0)
 794 #define MX_VECT_ADDL  (1)
 795 #define MX_VECT_MULA  (2)
 796 #define MX_VECT_MULL  (3)
 797 #define MX_VECT_MULS  (4)
 798 #define MX_VECT_MULSL (5)
 799 #define MX_VECT_SUBA  (6)
 800 #define MX_VECT_SUBL  (7)
 801 #define MX_VECT_ABSDA (8)               /* SB-1 only.  */
 802
 803 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 804 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
 805 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
 806 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
 807 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
 808 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
 809 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
 810 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
 811 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
 812 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
 813
 814 #define MX_FMT_OB   (0)
 815 #define MX_FMT_QH   (1)
 816
 817 /* The following codes chosen to indicate the units of shift.  */
 818 #define MX_RAC_L    (0)
 819 #define MX_RAC_M    (1)
 820 #define MX_RAC_H    (2)
 821
 822 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
 823 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
 824
 825 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
 826 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
 827 void mdmx_wach (SIM_STATE, int, unsigned64);
 828 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
 829
 830 #define MX_RND_AS   (0)
 831 #define MX_RND_AU   (1)
 832 #define MX_RND_ES   (2)
 833 #define MX_RND_EU   (3)
 834 #define MX_RND_ZS   (4)
 835 #define MX_RND_ZU   (5)
 836
 837 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
 838 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
 839 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
 840 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
 841 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
 842 #define MX_RZS(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
 843 #define MX_RZU(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
 844
 845 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
 846 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
 847
 848
 849
 850 /* Memory accesses */
 851
 852 /* The following are generic to all versions of the MIPS architecture
 853    to date: */
 854
 855 /* Memory Access Types (for CCA): */
 856 #define Uncached                (0)
 857 #define CachedNoncoherent       (1)
 858 #define CachedCoherent          (2)
 859 #define Cached                  (3)
 860
 861 #define isINSTRUCTION   (1 == 0) /* FALSE */
 862 #define isDATA          (1 == 1) /* TRUE */
 863 #define isLOAD          (1 == 0) /* FALSE */
 864 #define isSTORE         (1 == 1) /* TRUE */
 865 #define isREAL          (1 == 0) /* FALSE */
 866 #define isRAW           (1 == 1) /* TRUE */
 867 /* The parameter HOST (isTARGET / isHOST) is ignored */
 868 #define isTARGET        (1 == 0) /* FALSE */
 869 /* #define isHOST          (1 == 1) TRUE */
 870
 871 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 872    is the number of bytes minus 1. */
 873 #define AccessLength_BYTE       (0)
 874 #define AccessLength_HALFWORD   (1)
 875 #define AccessLength_TRIPLEBYTE (2)
 876 #define AccessLength_WORD       (3)
 877 #define AccessLength_QUINTIBYTE (4)
 878 #define AccessLength_SEXTIBYTE  (5)
 879 #define AccessLength_SEPTIBYTE  (6)
 880 #define AccessLength_DOUBLEWORD (7)
 881 #define AccessLength_QUADWORD   (15)
 882
 883 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 884                     ? AccessLength_DOUBLEWORD /*7*/ \
 885                     : AccessLength_WORD /*3*/)
 886 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 887
 888
 889 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 890 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 891 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 892
 893 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 894 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 895 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 896
 897 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 898 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 899 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 900
 901 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 902 #define CacheOp(op,pAddr,vAddr,instruction) \
 903 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 904
 905 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 906 #define SyncOperation(stype) \
 907 sync_operation (SD, CPU, cia, (stype))
 908
 909 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 910 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 911 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 912
 913 void unpredictable_action (sim_cpu *cpu, address_word cia);
 914 #define NotWordValue(val)       not_word_value (SD_, (val))
 915 #define Unpredictable()         unpredictable (SD_)
 916 #define UnpredictableResult()   /* For now, do nothing.  */
 917
 918 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 919 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 920 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 921 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 922 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 923
 924 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 925 extern FILE *tracefh;
 926
 927 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 928 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 929
 930 char* pr_addr PARAMS ((SIM_ADDR addr));
 931 char* pr_uword64 PARAMS ((uword64 addr));
 932
 933
 934 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
 935
 936 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 937 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 938 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 939
 940
 941 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 942 #include "sim-main.c"
 943 #endif
 944
 945 #endif