sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75
  76
  77 /* Floating-point operations: */
  78
  79 #include "sim-fpu.h"
  80
  81 /* FPU registers must be one of the following types. All other values
  82    are reserved (and undefined). */
  83 typedef enum {
  84  fmt_single  = 0,
  85  fmt_double  = 1,
  86  fmt_word    = 4,
  87  fmt_long    = 5,
  88  /* The following are well outside the normal acceptable format
  89     range, and are used in the register status vector. */
  90  fmt_unknown       = 0x10000000,
  91  fmt_uninterpreted = 0x20000000,
  92  fmt_uninterpreted_32 = 0x40000000,
  93  fmt_uninterpreted_64 = 0x80000000,
  94 } FP_formats;
  95
  96 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  97 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  98
  99 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
 100 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
 101
 102 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 103 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 104 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 105 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 106 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 107 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 108 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 109 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 110 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 113 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 114 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 115 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 116 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 117 #define Convert(rm,op,from,to) \
 118 convert (SD, CPU, cia, rm, op, from, to)
 119
 120 /* Macro to update FPSR condition-code field. This is complicated by
 121    the fact that there is a hole in the index range of the bits within
 122    the FCSR register. Also, the number of bits visible depends on the
 123    MIPS ISA version being supported. */
 124
 125 #define SETFCC(cc,v) {\
 126   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 127   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 128 }
 129 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 130
 131 /* This should be the COC1 value at the start of the preceding
 132    instruction: */
 133 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 134
 135 #if 1
 136 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 137 #else
 138 /* They depend on the CPU being simulated */
 139 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 140 #endif
 141
 142 /* Standard FCRS bits: */
 143 #define IR (0) /* Inexact Result */
 144 #define UF (1) /* UnderFlow */
 145 #define OF (2) /* OverFlow */
 146 #define DZ (3) /* Division by Zero */
 147 #define IO (4) /* Invalid Operation */
 148 #define UO (5) /* Unimplemented Operation */
 149
 150 /* Get masks for individual flags: */
 151 #if 1 /* SAFE version */
 152 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 153 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 154 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 155 #else
 156 #define FP_FLAGS(b)  (1 << ((b) + 2))
 157 #define FP_ENABLE(b) (1 << ((b) + 7))
 158 #define FP_CAUSE(b)  (1 << ((b) + 12))
 159 #endif
 160
 161 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 162
 163 #define FP_MASK_RM    (0x3)
 164 #define FP_SH_RM      (0)
 165 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 166 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 167 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 168 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 169 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 170
 171 /* start-sanitize-sky */
 172 #ifdef TARGET_SKY
 173 #ifdef SKY_FUNIT
 174 #include <assert.h>
 175 #include "wf.h"
 176 #endif
 177 #endif
 178 /* end-sanitize-sky */
 179
 180
 181
 182
 183
 184 /* HI/LO register accesses */
 185
 186 /* For some MIPS targets, the HI/LO registers have certain timing
 187    restrictions in that, for instance, a read of a HI register must be
 188    separated by at least three instructions from a preceeding read.
 189
 190    The struct below is used to record the last access by each of A MT,
 191    MF or other OP instruction to a HI/LO register.  See mips.igen for
 192    more details. */
 193
 194 typedef struct _hilo_access {
 195   signed64 timestamp;
 196   address_word cia;
 197 } hilo_access;
 198
 199 typedef struct _hilo_history {
 200   hilo_access mt;
 201   hilo_access mf;
 202   hilo_access op;
 203 } hilo_history;
 204
 205
 206
 207
 208 /* Integer ALU operations: */
 209
 210 #include "sim-alu.h"
 211
 212 #define ALU32_END(ANS) \
 213   if (ALU32_HAD_OVERFLOW) \
 214     SignalExceptionIntegerOverflow (); \
 215   (ANS) = ALU32_OVERFLOW_RESULT
 216
 217
 218 #define ALU64_END(ANS) \
 219   if (ALU64_HAD_OVERFLOW) \
 220     SignalExceptionIntegerOverflow (); \
 221   (ANS) = ALU64_OVERFLOW_RESULT;
 222
 223
 224 /* start-sanitize-r5900 */
 225
 226 /* Figure 10-5 FPU Control/Status Register.
 227    Note: some of these bits are different to what is found in a
 228    standard MIPS manual. */
 229 enum {
 230   R5900_FCSR_C = BIT (23), /* OK */
 231   R5900_FCSR_I = BIT (17),
 232   R5900_FCSR_D = BIT (16),
 233   R5900_FCSR_O = BIT (15),
 234   R5900_FCSR_U = BIT (14),
 235   R5900_FCSR_CAUSE = MASK (16,14),
 236   R5900_FCSR_SI = BIT (6),
 237   R5900_FCSR_SD = BIT (5),
 238   R5900_FCSR_SO = BIT (4),
 239   R5900_FCSR_SU = BIT (3),
 240 };
 241
 242 /* Table 10-1 FP format values.
 243    Note: some of these bits are different to what is found in a
 244    standard MIPS manual. */
 245 enum {
 246   R5900_EXPMAX = 128,
 247   R5900_EXPMIN = -127,
 248   R5900_EXPBIAS = 127,
 249 };
 250
 251
 252
 253 typedef struct _sim_r5900_cpu {
 254
 255   /* The R5900 has 32 x 128bit general purpose registers.
 256      Fortunatly, the high 64 bits are only touched by multimedia (MMI)
 257      instructions.  The normal mips instructions just use the lower 64
 258      bits.  To avoid changing the older parts of the simulator to
 259      handle this weirdness, the high 64 bits of each register are kept
 260      in a separate array (registers1).  The high 64 bits of any
 261      register are by convention refered by adding a '1' to the end of
 262      the normal register's name.  So LO still refers to the low 64
 263      bits of the LO register, LO1 refers to the high 64 bits of that
 264      same register.  */
 265   signed_word gpr1[32];
 266 #define GPR1     ((CPU)->r5900.gpr1)
 267   signed_word lo1;
 268   signed_word hi1;
 269 #define LO1      ((CPU)->r5900.lo1)
 270 #define HI1      ((CPU)->r5900.hi1)
 271
 272   /* The R5900 defines a shift amount register, that controls the
 273      amount of certain shift instructions */
 274   unsigned_word sa;        /* the shift amount register */
 275 #define REGISTER_SA     (124) /* GET RID IF THIS! */
 276 #define SA ((CPU)->r5900.sa)
 277
 278   /* The R5900, in addition to the (almost) standard floating point
 279      registers, defines a 32 bit accumulator.  This is used in
 280      multiply/accumulate style instructions */
 281   fp_word acc; /* floating-point accumulator */
 282 #define ACC ((CPU)->r5900.acc)
 283
 284   /* See comments below about needing to count cycles between updating
 285      and setting HI/LO registers */
 286   hilo_history hi1_history;
 287 #define HI1HISTORY (&(CPU)->r5900.hi1_history)
 288   hilo_history lo1_history;
 289 #define LO1HISTORY (&(CPU)->r5900.lo1_history)
 290
 291 } sim_r5900_cpu;
 292
 293 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 294 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 295 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 296 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 297
 298 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 299 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 300 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 301 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 302
 303 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 304    T  - type of the sub part
 305    TC - # of T's in the mips part of the "register"
 306    I  - index (from 0) of desired sub part
 307    A  - low part of "register"
 308    A1 - high part of register
 309 */
 310 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 311 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 312    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 313       ? ((TC) - 1 - (I) % (TC)) \
 314       : ((I) % (TC)) \
 315       ) \
 316    ) \
 317  )
 318
 319 /*
 320 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 321             where <type> has two letters:
 322                   1 is S=signed or U=unsigned
 323                   2 is B=byte H=halfword W=word D=doubleword
 324 */
 325
 326 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 327 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 328 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 329 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 330
 331 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 332 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 333 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 334 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 335
 336 #define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
 337 #define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
 338 #define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
 339 #define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
 340
 341 #define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
 342 #define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
 343 #define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
 344 #define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
 345
 346
 347 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 348 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 349 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 350 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 351
 352 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 353 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 354 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 355 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 356
 357 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 358 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 359 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 360 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 361
 362 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 363 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 364 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 365 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 366
 367
 368
 369 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 370 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 371 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 372 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 373
 374 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 375 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 376 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 377 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 378
 379 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 380 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 381 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 382 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 383
 384 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 385 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 386 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 387 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 388
 389 /* end-sanitize-r5900 */
 390
 391
 392
 393 /* The following is probably not used for MIPS IV onwards: */
 394 /* Slots for delayed register updates. For the moment we just have a
 395    fixed number of slots (rather than a more generic, dynamic
 396    system). This keeps the simulator fast. However, we only allow
 397    for the register update to be delayed for a single instruction
 398    cycle. */
 399 #define PSLOTS (8) /* Maximum number of instruction cycles */
 400
 401 typedef struct _pending_write_queue {
 402   int in;
 403   int out;
 404   int total;
 405   int slot_delay[PSLOTS];
 406   int slot_size[PSLOTS];
 407   int slot_bit[PSLOTS];
 408   void *slot_dest[PSLOTS];
 409   unsigned64 slot_value[PSLOTS];
 410 } pending_write_queue;
 411
 412 #ifndef PENDING_TRACE
 413 #define PENDING_TRACE 0
 414 #endif
 415 #define PENDING_IN ((CPU)->pending.in)
 416 #define PENDING_OUT ((CPU)->pending.out)
 417 #define PENDING_TOTAL ((CPU)->pending.total)
 418 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 419 #define PENDING_SLOT_BIT ((CPU)->pending.slot_size)
 420 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 421 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 422 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 423
 424 /* Invalidate the pending write queue, all pending writes are
 425    discarded. */
 426
 427 #define PENDING_INVALIDATE() \
 428 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 429
 430 /* Schedule a write to DEST for N cycles time.  For 64 bit
 431    destinations, schedule two writes.  For floating point registers,
 432    the caller should schedule a write to both the dest register and
 433    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 434    is updated. */
 435
 436 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 437   do {                                                                  \
 438     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 439       sim_engine_abort (SD, CPU, cia,                                   \
 440                         "PENDING_SCHED - buffer overflow\n");           \
 441     if (PENDING_TRACE)                                                  \
 442       sim_io_printf (SD, "PENDING_SCHED - dest 0x%lx, val 0x%lx, pending_in %d, pending_out %d, pending_total %d\n", (unsigned long) (DEST), (unsigned long) (VAL), PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
 443     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 444     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 445     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 446     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 447     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 448   } while (0)
 449
 450 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 451 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 452
 453 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 454
 455 #define PENDING_FLUSH() abort () /* think about this one */
 456 #define PENDING_FP() abort () /* think about this one */
 457
 458 /* For backward compatibility */
 459 #define PENDING_FILL(R,VAL)                                             \
 460 {                                                                       \
 461   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 462     PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 2, -1);                       \
 463   else                                                                  \
 464     PENDING_SCHED(GPR[(R)], VAL, 2, -1);                                \
 465 }
 466
 467
 468
 469 struct _sim_cpu {
 470
 471
 472   /* The following are internal simulator state variables: */
 473 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 474 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 475   address_word dspc;  /* delay-slot PC */
 476 #define DSPC ((CPU)->dspc)
 477
 478 #if !WITH_IGEN
 479   /* Issue a delay slot instruction immediatly by re-calling
 480      idecode_issue */
 481 #define DELAY_SLOT(TARGET) \
 482   do { \
 483     address_word target = (TARGET); \
 484     instruction_word delay_insn; \
 485     sim_events_slip (SD, 1); \
 486     CIA = CIA + 4; /* NOTE not mips16 */ \
 487     STATE |= simDELAYSLOT; \
 488     delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ \
 489     idecode_issue (CPU_, delay_insn, (CIA)); \
 490     STATE &= ~simDELAYSLOT; \
 491     NIA = target; \
 492   } while (0)
 493 #define NULLIFY_NEXT_INSTRUCTION() \
 494   do { \
 495     sim_events_slip (SD, 1); \
 496     dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
 497     NIA = CIA + 8; \
 498   } while (0)
 499 #else
 500 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 501 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 502 #endif
 503
 504
 505   /* State of the simulator */
 506   unsigned int state;
 507   unsigned int dsstate;
 508 #define STATE ((CPU)->state)
 509 #define DSSTATE ((CPU)->dsstate)
 510
 511 /* Flags in the "state" variable: */
 512 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 513 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 514 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 515 #define simPCOC0        (1 << 17) /* COC[1] from current */
 516 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 517 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 518 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 519 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 520 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 521
 522 #define ENGINE_ISSUE_PREFIX_HOOK() \
 523   { \
 524     /* Perform any pending writes */ \
 525     PENDING_TICK(); \
 526     /* Set previous flag, depending on current: */ \
 527     if (STATE & simPCOC0) \
 528      STATE |= simPCOC1; \
 529     else \
 530      STATE &= ~simPCOC1; \
 531     /* and update the current value: */ \
 532     if (GETFCC(0)) \
 533      STATE |= simPCOC0; \
 534     else \
 535      STATE &= ~simPCOC0; \
 536   }
 537
 538
 539 /* This is nasty, since we have to rely on matching the register
 540    numbers used by GDB. Unfortunately, depending on the MIPS target
 541    GDB uses different register numbers. We cannot just include the
 542    relevant "gdb/tm.h" link, since GDB may not be configured before
 543    the sim world, and also the GDB header file requires too much other
 544    state. */
 545
 546 #ifndef TM_MIPS_H
 547 #define LAST_EMBED_REGNUM (89)
 548 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 549 /* start-sanitize-r5900 */
 550 #undef NUM_REGS
 551 #define NUM_REGS (128)
 552 /* end-sanitize-r5900 */
 553 #endif
 554
 555 /* start-sanitize-sky */
 556 #ifdef TARGET_SKY
 557 #ifndef TM_TXVU_H
 558
 559 /* Number of machine registers */
 560 #define NUM_VU_REGS     153
 561 #define NUM_VU_INTEGER_REGS 16
 562
 563 #define NUM_VIF_REGS    25
 564
 565 #define FIRST_VEC_REG   25
 566 #define NUM_R5900_REGS  128
 567
 568 #undef NUM_REGS
 569 #define NUM_REGS (NUM_R5900_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
 570 #endif /* no tm-txvu.h */
 571 #endif
 572
 573 enum float_operation
 574 /* start-sanitize-sky */
 575 /* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
 576 /* end-sanitize-sky */
 577   {
 578     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 579     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 580     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 581   };
 582
 583 /* To keep this default simulator simple, and fast, we use a direct
 584    vector of registers. The internal simulator engine then uses
 585    manifests to access the correct slot. */
 586
 587   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 588   int register_widths[NUM_REGS];
 589 #define REGISTERS       ((CPU)->registers)
 590
 591 #define GPR     (&REGISTERS[0])
 592 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 593
 594   /* While space is allocated for the floating point registers in the
 595      main registers array, they are stored separatly.  This is because
 596      their size may not necessarily match the size of either the
 597      general-purpose or system specific registers */
 598 #define NR_FGR  (32)
 599 #define FGRIDX  (38)
 600   fp_word fgr[NR_FGR];
 601 #define FGR     ((CPU)->fgr)
 602
 603 #define LO      (REGISTERS[33])
 604 #define HI      (REGISTERS[34])
 605 #define PCIDX   37
 606 #define PC      (REGISTERS[PCIDX])
 607 #define CAUSE   (REGISTERS[36])
 608 #define SRIDX   (32)
 609 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 610 #define FCR0IDX  (71)
 611 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 612 #define FCR31IDX (70)
 613 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 614 #define FCSR    (FCR31)
 615 #define Debug   (REGISTERS[86])
 616 #define DEPC    (REGISTERS[87])
 617 #define EPC     (REGISTERS[88])
 618 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 619
 620   unsigned_word c0_config_reg;
 621 #define C0_CONFIG ((CPU)->c0_config_reg)
 622
 623 /* The following are pseudonyms for standard registers */
 624 #define ZERO    (REGISTERS[0])
 625 #define V0      (REGISTERS[2])
 626 #define A0      (REGISTERS[4])
 627 #define A1      (REGISTERS[5])
 628 #define A2      (REGISTERS[6])
 629 #define A3      (REGISTERS[7])
 630 #define T8IDX   24
 631 #define T8      (REGISTERS[T8IDX])
 632 #define SPIDX   29
 633 #define SP      (REGISTERS[SPIDX])
 634 #define RAIDX   31
 635 #define RA      (REGISTERS[RAIDX])
 636
 637   /* Keep the current format state for each register: */
 638   FP_formats fpr_state[32];
 639 #define FPR_STATE ((CPU)->fpr_state)
 640
 641   pending_write_queue pending;
 642
 643   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 644      read-write instructions. It is set when a linked load occurs. It
 645      is tested and cleared by the conditional store. It is cleared
 646      (during other CPU operations) when a store to the location would
 647      no longer be atomic. In particular, it is cleared by exception
 648      return instructions. */
 649   int llbit;
 650 #define LLBIT ((CPU)->llbit)
 651
 652
 653 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 654    corruptions caused by using the HI or LO register too close to a
 655    following operation is spotted. See mips.igen for more details. */
 656
 657   hilo_history hi_history;
 658 #define HIHISTORY (&(CPU)->hi_history)
 659   hilo_history lo_history;
 660 #define LOHISTORY (&(CPU)->lo_history)
 661
 662
 663   /* start-sanitize-r5900 */
 664   sim_r5900_cpu r5900;
 665
 666   /* end-sanitize-r5900 */
 667   /* start-sanitize-vr5400 */
 668
 669   /* The MDMX ISA has a very very large accumulator */
 670   unsigned8 acc[3 * 8];
 671   /* end-sanitize-vr5400 */
 672
 673   sim_cpu_base base;
 674 };
 675
 676
 677 /* MIPS specific simulator watch config */
 678
 679 void watch_options_install PARAMS ((SIM_DESC sd));
 680
 681 struct swatch {
 682   sim_event *pc;
 683   sim_event *clock;
 684   sim_event *cycles;
 685 };
 686
 687
 688 /* FIXME: At present much of the simulator is still static */
 689 struct sim_state {
 690
 691   struct swatch watch;
 692
 693   sim_cpu cpu[MAX_NR_PROCESSORS];
 694 #if (WITH_SMP)
 695 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 696 #else
 697 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 698 #endif
 699
 700 /* start-sanitize-sky */
 701 #ifdef TARGET_SKY
 702 #ifdef SKY_FUNIT
 703   /* Record of option for floating point implementation type. */
 704   int fp_type_opt;
 705 #define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
 706 #define STATE_FP_TYPE_OPT_TARGET 0x80000000
 707 #endif
 708 #endif
 709 /* end-sanitize-sky */
 710
 711   sim_state_base base;
 712 };
 713
 714
 715
 716 /* Status information: */
 717
 718 /* TODO : these should be the bitmasks for these bits within the
 719    status register. At the moment the following are VR4300
 720    bit-positions: */
 721 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 722 #define status_KSU_shift (3)            /* shift for field */
 723 #define ksu_kernel       (0x0)
 724 #define ksu_supervisor   (0x1)
 725 #define ksu_user         (0x2)
 726 #define ksu_unknown      (0x3)
 727
 728 #define status_IE        (1 <<  0)      /* Interrupt enable */
 729 #define status_EXL       (1 <<  1)      /* Exception level */
 730 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 731 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 732 #define status_SR        (1 << 20)      /* soft reset or NMI */
 733 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 734 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 735 #define status_ERL       (1 <<  2)      /* Error level */
 736 #define status_RP        (1 << 27)      /* Reduced Power mode */
 737 /* start-sanitize-r5900 */
 738 #define status_CU0       (1 << 28)      /* COP0 usable */
 739 #define status_CU1       (1 << 29)      /* COP1 usable */
 740 #define status_CU2       (1 << 30)      /* COP2 usable */
 741 /* end-sanitize-r5900 */
 742
 743 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 744
 745 /* NOTE: We keep the following status flags as bit values (1 for true,
 746    0 for false). This allows them to be used in binary boolean
 747    operations without worrying about what exactly the non-zero true
 748    value is. */
 749
 750 /* UserMode */
 751 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 752
 753 /* BigEndianMem */
 754 /* Hardware configuration. Affects endianness of LoadMemory and
 755    StoreMemory and the endianness of Kernel and Supervisor mode
 756    execution. The value is 0 for little-endian; 1 for big-endian. */
 757 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 758 /*(state & simBE) ? 1 : 0)*/
 759
 760 /* ReverseEndian */
 761 /* This mode is selected if in User mode with the RE bit being set in
 762    SR (Status Register). It reverses the endianness of load and store
 763    instructions. */
 764 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 765
 766 /* BigEndianCPU */
 767 /* The endianness for load and store instructions (0=little;1=big). In
 768    User mode this endianness may be switched by setting the state_RE
 769    bit in the SR register. Thus, BigEndianCPU may be computed as
 770    (BigEndianMem EOR ReverseEndian). */
 771 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 772
 773
 774
 775 /* Exceptions: */
 776
 777 /* NOTE: These numbers depend on the processor architecture being
 778    simulated: */
 779 #define Interrupt               (0)
 780 #define TLBModification         (1)
 781 #define TLBLoad                 (2)
 782 #define TLBStore                (3)
 783 #define AddressLoad             (4)
 784 #define AddressStore            (5)
 785 #define InstructionFetch        (6)
 786 #define DataReference           (7)
 787 #define SystemCall              (8)
 788 #define BreakPoint              (9)
 789 #define ReservedInstruction     (10)
 790 #define CoProcessorUnusable     (11)
 791 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 792 #define Trap                    (13)
 793 #define FPE                     (15)
 794 #define DebugBreakPoint         (16)
 795 #define Watch                   (23)
 796
 797 /* The following exception code is actually private to the simulator
 798    world. It is *NOT* a processor feature, and is used to signal
 799    run-time errors in the simulator. */
 800 #define SimulatorFault      (0xFFFFFFFF)
 801
 802 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 803 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 804 #define SignalExceptionInterrupt()           signal_exception (SD, CPU, NULL_CIA, Interrupt)
 805 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 806 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 807 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 808 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 809 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 810 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 811 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
 812
 813
 814 /* Co-processor accesses */
 815
 816 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 817 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 818 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 819 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 820
 821 #define COP_LW(coproc_num,coproc_reg,memword) \
 822 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 823 #define COP_LD(coproc_num,coproc_reg,memword) \
 824 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 825 #define COP_SW(coproc_num,coproc_reg) \
 826 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 827 #define COP_SD(coproc_num,coproc_reg) \
 828 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 829
 830 /* start-sanitize-sky */
 831 #ifdef TARGET_SKY
 832 void cop_lq  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
 833                       int coproc_num, int coproc_reg, unsigned128 memword));
 834 unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
 835                             int coproc_num, int coproc_reg));
 836 #define COP_LQ(coproc_num,coproc_reg,memword) \
 837 cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
 838 #define COP_SQ(coproc_num,coproc_reg) \
 839 cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
 840 #endif /* TARGET_SKY */
 841 /* end-sanitize-sky */
 842
 843 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 844 #define DecodeCoproc(instruction) \
 845 decode_coproc (SD, CPU, cia, (instruction))
 846
 847
 848
 849 /* Memory accesses */
 850
 851 /* The following are generic to all versions of the MIPS architecture
 852    to date: */
 853
 854 /* Memory Access Types (for CCA): */
 855 #define Uncached                (0)
 856 #define CachedNoncoherent       (1)
 857 #define CachedCoherent          (2)
 858 #define Cached                  (3)
 859
 860 #define isINSTRUCTION   (1 == 0) /* FALSE */
 861 #define isDATA          (1 == 1) /* TRUE */
 862 #define isLOAD          (1 == 0) /* FALSE */
 863 #define isSTORE         (1 == 1) /* TRUE */
 864 #define isREAL          (1 == 0) /* FALSE */
 865 #define isRAW           (1 == 1) /* TRUE */
 866 /* The parameter HOST (isTARGET / isHOST) is ignored */
 867 #define isTARGET        (1 == 0) /* FALSE */
 868 /* #define isHOST          (1 == 1) TRUE */
 869
 870 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 871    is the number of bytes minus 1. */
 872 #define AccessLength_BYTE       (0)
 873 #define AccessLength_HALFWORD   (1)
 874 #define AccessLength_TRIPLEBYTE (2)
 875 #define AccessLength_WORD       (3)
 876 #define AccessLength_QUINTIBYTE (4)
 877 #define AccessLength_SEXTIBYTE  (5)
 878 #define AccessLength_SEPTIBYTE  (6)
 879 #define AccessLength_DOUBLEWORD (7)
 880 #define AccessLength_QUADWORD   (15)
 881
 882 #if (WITH_IGEN)
 883 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 884                     ? AccessLength_DOUBLEWORD /*7*/ \
 885                     : AccessLength_WORD /*3*/)
 886 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 887 #endif
 888
 889
 890 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 891 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 892 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 893
 894 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 895 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 896 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 897
 898 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 899 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 900 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 901
 902 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 903 #define CacheOp(op,pAddr,vAddr,instruction) \
 904 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 905
 906 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 907 #define SyncOperation(stype) \
 908 sync_operation (SD, CPU, cia, (stype))
 909
 910 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 911 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 912 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 913
 914 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 915 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 916 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 917 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 918 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 919
 920 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 921 FILE *tracefh;
 922
 923 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 924
 925 char* pr_addr PARAMS ((SIM_ADDR addr));
 926 char* pr_uword64 PARAMS ((uword64 addr));
 927
 928
 929 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 930 #include "sim-main.c"
 931 #endif
 932
 933 #endif