1 /* MIPS Simulator definition.
2 Copyright (C) 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* This simulator doesn't cache the Current Instruction Address */
25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
28 #define SIM_HAVE_BIENDIAN
31 /* hobble some common features for moment */
32 #define WITH_WATCHPOINTS 1
33 #define WITH_MODULO_MEMORY 1
35 #include "sim-basics.h"
37 typedef address_word sim_cia
;
42 /* Depreciated macros and types for manipulating 64bit values. Use
43 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
45 typedef signed64 word64
;
46 typedef unsigned64 uword64
;
48 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
49 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
50 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
51 #define SET64HI(t) (((uword64)(t))<<32)
52 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
53 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
55 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
56 assume the HI32bits of the operand are zero, so we must perform a
57 mask to ensure we can use the simple subtraction to sign-extend. */
58 #define SIGNEXTEND(e,b) \
60 (((e) & ((uword64) 1 << ((b) - 1))) \
61 ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
62 : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
64 /* Check if a value will fit within a halfword: */
65 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
69 /* Floating-point operations: */
73 /* FPU registers must be one of the following types. All other values
74 are reserved (and undefined). */
80 /* The following are well outside the normal acceptable format
81 range, and are used in the register status vector. */
82 fmt_unknown
= 0x10000000,
83 fmt_uninterpreted
= 0x20000000,
84 fmt_uninterpreted_32
= 0x40000000,
85 fmt_uninterpreted_64
= 0x80000000U
,
88 unsigned64 value_fpr
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int fpr
, FP_formats
));
89 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
91 void store_fpr
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int fpr
, FP_formats fmt
, unsigned64 value
));
92 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
94 int NaN
PARAMS ((unsigned64 op
, FP_formats fmt
));
95 int Infinity
PARAMS ((unsigned64 op
, FP_formats fmt
));
96 int Less
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
97 int Equal
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
98 unsigned64 AbsoluteValue
PARAMS ((unsigned64 op
, FP_formats fmt
));
99 unsigned64 Negate
PARAMS ((unsigned64 op
, FP_formats fmt
));
100 unsigned64 Add
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
101 unsigned64 Sub
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
102 unsigned64 Multiply
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
103 unsigned64 Divide
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
104 unsigned64 Recip
PARAMS ((unsigned64 op
, FP_formats fmt
));
105 unsigned64 SquareRoot
PARAMS ((unsigned64 op
, FP_formats fmt
));
106 unsigned64 Max
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
107 unsigned64 Min
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
108 unsigned64 convert
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int rm
, unsigned64 op
, FP_formats from
, FP_formats to
));
109 #define Convert(rm,op,from,to) \
110 convert (SD, CPU, cia, rm, op, from, to)
112 /* Macro to update FPSR condition-code field. This is complicated by
113 the fact that there is a hole in the index range of the bits within
114 the FCSR register. Also, the number of bits visible depends on the
115 MIPS ISA version being supported. */
117 #define SETFCC(cc,v) {\
118 int bit = ((cc == 0) ? 23 : (24 + (cc)));\
119 FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
121 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
123 /* This should be the COC1 value at the start of the preceding
125 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
128 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
130 /* They depend on the CPU being simulated */
131 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
134 /* Standard FCRS bits: */
135 #define IR (0) /* Inexact Result */
136 #define UF (1) /* UnderFlow */
137 #define OF (2) /* OverFlow */
138 #define DZ (3) /* Division by Zero */
139 #define IO (4) /* Invalid Operation */
140 #define UO (5) /* Unimplemented Operation */
142 /* Get masks for individual flags: */
143 #if 1 /* SAFE version */
144 #define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
145 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
146 #define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
148 #define FP_FLAGS(b) (1 << ((b) + 2))
149 #define FP_ENABLE(b) (1 << ((b) + 7))
150 #define FP_CAUSE(b) (1 << ((b) + 12))
153 #define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
155 #define FP_MASK_RM (0x3)
157 #define FP_RM_NEAREST (0) /* Round to nearest (Round) */
158 #define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
159 #define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
160 #define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
161 #define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
163 /* start-sanitize-sky */
170 /* end-sanitize-sky */
176 /* HI/LO register accesses */
178 /* For some MIPS targets, the HI/LO registers have certain timing
179 restrictions in that, for instance, a read of a HI register must be
180 separated by at least three instructions from a preceeding read.
182 The struct below is used to record the last access by each of A MT,
183 MF or other OP instruction to a HI/LO register. See mips.igen for
186 typedef struct _hilo_access
{
191 typedef struct _hilo_history
{
200 /* Integer ALU operations: */
204 #define ALU32_END(ANS) \
205 if (ALU32_HAD_OVERFLOW) \
206 SignalExceptionIntegerOverflow (); \
207 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
210 #define ALU64_END(ANS) \
211 if (ALU64_HAD_OVERFLOW) \
212 SignalExceptionIntegerOverflow (); \
213 (ANS) = ALU64_OVERFLOW_RESULT;
216 /* start-sanitize-r5900 */
218 /* Figure 10-5 FPU Control/Status Register.
219 Note: some of these bits are different to what is found in a
220 standard MIPS manual. */
222 R5900_FCSR_C
= BIT (23), /* OK */
223 R5900_FCSR_I
= BIT (17),
224 R5900_FCSR_D
= BIT (16),
225 R5900_FCSR_O
= BIT (15),
226 R5900_FCSR_U
= BIT (14),
227 R5900_FCSR_CAUSE
= MASK (16,14),
228 R5900_FCSR_SI
= BIT (6),
229 R5900_FCSR_SD
= BIT (5),
230 R5900_FCSR_SO
= BIT (4),
231 R5900_FCSR_SU
= BIT (3),
234 /* Table 10-1 FP format values.
235 Note: some of these bits are different to what is found in a
236 standard MIPS manual. */
243 /* MAX and MIN FP values */
245 R5900_FPMAX
= LSMASK32 (30, 0),
246 R5900_FPMIN
= LSMASK32 (31, 0),
249 typedef struct _r4000_tlb_entry
{
256 #define TLB_MASK_MASK_MASK 0x01ffe000
257 #define TLB_HI_VPN2_MASK 0xffffe000
258 #define TLB_HI_G_MASK 0x00001000
259 #define TLB_HI_ASID_MASK 0x000000ff
261 #define TLB_LO_S_MASK 0x80000000
262 #define TLB_LO_PFN_MASK 0x03ffffc0
263 #define TLB_LO_C_MASK 0x00000038
264 #define TLB_LO_D_MASK 0x00000004
265 #define TLB_LO_V_MASK 0x00000002
269 typedef struct _sim_r5900_cpu
{
271 /* The R5900 has 32 x 128bit general purpose registers.
272 Fortunatly, the high 64 bits are only touched by multimedia (MMI)
273 instructions. The normal mips instructions just use the lower 64
274 bits. To avoid changing the older parts of the simulator to
275 handle this weirdness, the high 64 bits of each register are kept
276 in a separate array (registers1). The high 64 bits of any
277 register are by convention refered by adding a '1' to the end of
278 the normal register's name. So LO still refers to the low 64
279 bits of the LO register, LO1 refers to the high 64 bits of that
281 signed_word gpr1
[32];
282 #define GPR1 ((CPU)->r5900.gpr1)
283 #define GPR1_SET(N,VAL) (GPR1[(N]) = (VAL))
286 #define LO1 ((CPU)->r5900.lo1)
287 #define HI1 ((CPU)->r5900.hi1)
289 /* The R5900 defines a shift amount register, that controls the
290 amount of certain shift instructions */
291 unsigned_word sa
; /* the shift amount register */
292 #define REGISTER_SA (124) /* GET RID IF THIS! */
293 #define SA ((CPU)->r5900.sa)
295 /* The R5900, in addition to the (almost) standard floating point
296 registers, defines a 32 bit accumulator. This is used in
297 multiply/accumulate style instructions */
298 fp_word acc
; /* floating-point accumulator */
299 #define ACC ((CPU)->r5900.acc)
301 /* See comments below about needing to count cycles between updating
302 and setting HI/LO registers */
303 hilo_history hi1_history
;
304 #define HI1HISTORY (&(CPU)->r5900.hi1_history)
305 hilo_history lo1_history
;
306 #define LO1HISTORY (&(CPU)->r5900.lo1_history)
308 r4000_tlb_entry_t tlb
[TLB_SIZE
];
309 #define TLB ((CPU)->r5900.tlb)
313 #define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
314 #define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
315 #define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
316 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
318 #define BYTES_IN_MIPS_REGS (sizeof(signed_word))
319 #define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
320 #define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
321 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
323 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
324 T - type of the sub part
325 TC - # of T's in the mips part of the "register"
326 I - index (from 0) of desired sub part
327 A - low part of "register"
328 A1 - high part of register
330 #define SUB_REG_FETCH(T,TC,A,A1,I) \
331 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
332 + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
333 ? ((TC) - 1 - (I) % (TC)) \
340 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
341 where <type> has two letters:
342 1 is S=signed or U=unsigned
343 2 is B=byte H=halfword W=word D=doubleword
346 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
347 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
348 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
349 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
351 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
352 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
353 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
354 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
356 #define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
357 #define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
358 #define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
359 #define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
361 #define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
362 #define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
363 #define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
364 #define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
366 #define TMP_DCL unsigned64 tmp_reg, tmp_reg1
368 #define TMP_SB(I) SUB_REG_SB(&tmp_reg, &tmp_reg1, I)
369 #define TMP_SH(I) SUB_REG_SH(&tmp_reg, &tmp_reg1, I)
370 #define TMP_SW(I) SUB_REG_SW(&tmp_reg, &tmp_reg1, I)
371 #define TMP_SD(I) SUB_REG_SD(&tmp_reg, &tmp_reg1, I)
373 #define TMP_UB(I) SUB_REG_UB(&tmp_reg, &tmp_reg1, I)
374 #define TMP_UH(I) SUB_REG_UH(&tmp_reg, &tmp_reg1, I)
375 #define TMP_UW(I) SUB_REG_UW(&tmp_reg, &tmp_reg1, I)
376 #define TMP_UD(I) SUB_REG_UD(&tmp_reg, &tmp_reg1, I)
378 #define TMP_WRT(R) do { GPR[R] = tmp_reg; GPR1[R] = tmp_reg1; } while(0)
380 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
381 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
382 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
383 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
385 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
386 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
387 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
388 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
390 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
391 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
392 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
393 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
395 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
396 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
397 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
398 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
402 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
403 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
404 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
405 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
407 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
408 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
409 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
410 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
412 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
413 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
414 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
415 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
417 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
418 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
419 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
420 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
422 /* end-sanitize-r5900 */
426 /* The following is probably not used for MIPS IV onwards: */
427 /* Slots for delayed register updates. For the moment we just have a
428 fixed number of slots (rather than a more generic, dynamic
429 system). This keeps the simulator fast. However, we only allow
430 for the register update to be delayed for a single instruction
432 #define PSLOTS (8) /* Maximum number of instruction cycles */
434 typedef struct _pending_write_queue
{
438 int slot_delay
[PSLOTS
];
439 int slot_size
[PSLOTS
];
440 int slot_bit
[PSLOTS
];
441 void *slot_dest
[PSLOTS
];
442 unsigned64 slot_value
[PSLOTS
];
443 } pending_write_queue
;
445 #ifndef PENDING_TRACE
446 #define PENDING_TRACE 0
448 #define PENDING_IN ((CPU)->pending.in)
449 #define PENDING_OUT ((CPU)->pending.out)
450 #define PENDING_TOTAL ((CPU)->pending.total)
451 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
452 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
453 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
454 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
455 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
457 /* Invalidate the pending write queue, all pending writes are
460 #define PENDING_INVALIDATE() \
461 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
463 /* Schedule a write to DEST for N cycles time. For 64 bit
464 destinations, schedule two writes. For floating point registers,
465 the caller should schedule a write to both the dest register and
466 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
469 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
471 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
472 sim_engine_abort (SD, CPU, cia, \
473 "PENDING_SCHED - buffer overflow\n"); \
475 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
476 (unsigned long) cia, (unsigned long) &(DEST), \
477 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
478 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
479 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
480 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
481 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
482 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
483 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
484 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
485 PENDING_TOTAL += 1; \
488 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
489 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
491 #define PENDING_TICK() pending_tick (SD, CPU, cia)
493 #define PENDING_FLUSH() abort () /* think about this one */
494 #define PENDING_FP() abort () /* think about this one */
496 /* For backward compatibility */
497 #define PENDING_FILL(R,VAL) \
499 if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR) \
501 PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1); \
502 PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
505 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
513 /* The following are internal simulator state variables: */
514 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
515 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
516 address_word dspc
; /* delay-slot PC */
517 #define DSPC ((CPU)->dspc)
520 /* Issue a delay slot instruction immediatly by re-calling
522 #define DELAY_SLOT(TARGET) \
524 address_word target = (TARGET); \
525 instruction_word delay_insn; \
526 sim_events_slip (SD, 1); \
527 CIA = CIA + 4; /* NOTE not mips16 */ \
528 STATE |= simDELAYSLOT; \
529 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ \
530 idecode_issue (CPU_, delay_insn, (CIA)); \
531 STATE &= ~simDELAYSLOT; \
534 #define NULLIFY_NEXT_INSTRUCTION() \
536 sim_events_slip (SD, 1); \
537 dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
541 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
542 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
546 /* State of the simulator */
548 unsigned int dsstate
;
549 #define STATE ((CPU)->state)
550 #define DSSTATE ((CPU)->dsstate)
552 /* Flags in the "state" variable: */
553 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
554 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
555 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
556 #define simPCOC0 (1 << 17) /* COC[1] from current */
557 #define simPCOC1 (1 << 18) /* COC[1] from previous */
558 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
559 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
560 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
561 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
563 #define ENGINE_ISSUE_PREFIX_HOOK() \
565 /* Perform any pending writes */ \
567 /* Set previous flag, depending on current: */ \
568 if (STATE & simPCOC0) \
571 STATE &= ~simPCOC1; \
572 /* and update the current value: */ \
576 STATE &= ~simPCOC0; \
580 /* This is nasty, since we have to rely on matching the register
581 numbers used by GDB. Unfortunately, depending on the MIPS target
582 GDB uses different register numbers. We cannot just include the
583 relevant "gdb/tm.h" link, since GDB may not be configured before
584 the sim world, and also the GDB header file requires too much other
588 #define LAST_EMBED_REGNUM (89)
589 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
591 /* start-sanitize-r5900 */
592 #define FIRST_COP0_REG 128
593 #define NUM_COP0_REGS 22
595 #define NUM_REGS (150)
596 /* end-sanitize-r5900 */
600 /* start-sanitize-sky */
603 /* Number of machine registers */
604 #define NUM_VU_REGS 160
606 #define NUM_VU_INTEGER_REGS 16
607 #define FIRST_VEC_REG 32
609 #define NUM_VIF_REGS 26
611 #define NUM_CORE_REGS 150
614 #define NUM_REGS (NUM_CORE_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
615 #endif /* no tm-txvu.h */
616 #endif /* TARGET_SKY */
617 /* end-sanitize-sky */
620 /* start-sanitize-sky */
621 /* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
622 /* end-sanitize-sky */
624 FLOP_ADD
, FLOP_SUB
, FLOP_MUL
, FLOP_MADD
,
625 FLOP_MSUB
, FLOP_MAX
=10, FLOP_MIN
, FLOP_ABS
,
626 FLOP_ITOF0
=14, FLOP_FTOI0
=18, FLOP_NEG
=23
629 /* To keep this default simulator simple, and fast, we use a direct
630 vector of registers. The internal simulator engine then uses
631 manifests to access the correct slot. */
633 unsigned_word registers
[LAST_EMBED_REGNUM
+ 1];
634 int register_widths
[NUM_REGS
];
635 #define REGISTERS ((CPU)->registers)
637 #define GPR (®ISTERS[0])
638 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
640 /* While space is allocated for the floating point registers in the
641 main registers array, they are stored separatly. This is because
642 their size may not necessarily match the size of either the
643 general-purpose or system specific registers */
647 #define FGR ((CPU)->fgr)
649 #define LO (REGISTERS[33])
650 #define HI (REGISTERS[34])
652 #define PC (REGISTERS[PCIDX])
653 #define CAUSE (REGISTERS[36])
655 #define SR (REGISTERS[SRIDX]) /* CPU status register */
657 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
658 #define FCR31IDX (70)
659 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
661 #define Debug (REGISTERS[86])
662 #define DEPC (REGISTERS[87])
663 #define EPC (REGISTERS[88])
664 #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
666 unsigned_word c0_config_reg
;
667 #define C0_CONFIG ((CPU)->c0_config_reg)
669 /* The following are pseudonyms for standard registers */
670 #define ZERO (REGISTERS[0])
671 #define V0 (REGISTERS[2])
672 #define A0 (REGISTERS[4])
673 #define A1 (REGISTERS[5])
674 #define A2 (REGISTERS[6])
675 #define A3 (REGISTERS[7])
677 #define T8 (REGISTERS[T8IDX])
679 #define SP (REGISTERS[SPIDX])
681 #define RA (REGISTERS[RAIDX])
683 /* While space is allocated in the main registers arrray for some of
684 the COP0 registers, that space isn't sufficient. Unknown COP0
685 registers overflow into the array below */
687 #define NR_COP0_GPR 32
688 unsigned_word cop0_gpr
[NR_COP0_GPR
];
689 #define COP0_GPR ((CPU)->cop0_gpr)
690 /* start-sanitize-r5900 */
692 unsigned_word cop0_bp
[NR_COP0_BP
];
693 #define COP0_BP ((CPU)->cop0_bp)
695 unsigned_word cop0_p
[NR_COP0_P
];
697 #define COP0_P ((CPU)->cop0_p)
698 #define COP0_INDEX ((unsigned32)(COP0_GPR[0]))
699 #define COP0_RANDOM ((unsigned32)(COP0_GPR[1]))
700 #define COP0_ENTRYLO0 ((unsigned32)(COP0_GPR[2]))
701 #define COP0_ENTRYLO1 ((unsigned32)(COP0_GPR[3]))
702 #define COP0_CONTEXT ((unsigned32)(COP0_GPR[4]))
703 #define COP0_PAGEMASK ((unsigned32)(COP0_GPR[5]))
704 #define COP0_WIRED ((unsigned32)(COP0_GPR[6]))
705 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
706 #define COP0_COUNT ((unsigned32)(COP0_GPR[9]))
707 #define COP0_ENTRYHI ((unsigned32)(COP0_GPR[10]))
708 #define COP0_COMPARE ((unsigned32)(COP0_GPR[11]))
709 #define COP0_EPC ((unsigned32)(EPC)) /* 14 */
710 #define COP0_PRID ((unsigned32)(COP0_GPR[15]))
711 #define COP0_CONFIG ((unsigned32)(C0_CONFIG)) /* 16 */
712 #define COP0_TAGLO ((unsigned32)(COP0_GPR[28]))
713 #define COP0_TAGHI ((unsigned32)(COP0_GPR[29]))
714 #define COP0_ERROREPC ((unsigned32)(COP0_GPR[30]))
716 #define COP0_CONTEXT_BADVPN2_MASK 0x007ffff0
718 #define COP0_CONTEXT_set_BADVPN2(x) \
719 (COP0_CONTEXT = ((COP0_CONTEXT & 0xff100000) | ((x << 4) & 0x007ffff0)))
720 /* end-sanitize-r5900 */
722 /* Keep the current format state for each register: */
723 FP_formats fpr_state
[32];
724 #define FPR_STATE ((CPU)->fpr_state)
726 pending_write_queue pending
;
728 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
729 read-write instructions. It is set when a linked load occurs. It
730 is tested and cleared by the conditional store. It is cleared
731 (during other CPU operations) when a store to the location would
732 no longer be atomic. In particular, it is cleared by exception
733 return instructions. */
735 #define LLBIT ((CPU)->llbit)
738 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
739 corruptions caused by using the HI or LO register too close to a
740 following operation is spotted. See mips.igen for more details. */
742 hilo_history hi_history
;
743 #define HIHISTORY (&(CPU)->hi_history)
744 hilo_history lo_history
;
745 #define LOHISTORY (&(CPU)->lo_history)
747 /* start-sanitize-branchbug4011 */
749 int branchbug4011_option
;
750 #define BRANCHBUG4011_OPTION ((CPU)->branchbug4011_option)
751 address_word branchbug4011_last_target
;
752 #define BRANCHBUG4011_LAST_TARGET ((CPU)->branchbug4011_last_target)
753 address_word branchbug4011_last_cia
;
754 #define BRANCHBUG4011_LAST_CIA ((CPU)->branchbug4011_last_cia)
756 #define check_branch_bug() (check_4011_branch_bug (_SD))
757 #define mark_branch_bug(TARGET) (mark_4011_branch_bug (_SD,TARGET))
759 /* end-sanitize-branchbug4011 */
760 #define check_branch_bug()
761 #define mark_branch_bug(TARGET)
762 /* start-sanitize-branchbug4011 */
764 /* end-sanitize-branchbug4011 */
765 /* start-sanitize-r5900 */
767 /* end-sanitize-r5900 */
769 /* start-sanitize-cygnus */
770 /* The MDMX ISA has a very very large accumulator */
771 unsigned8 acc
[3 * 8];
772 /* end-sanitize-cygnus */
774 /* start-sanitize-sky */
776 /* Device on which instruction issue last occured. */
779 /* end-sanitize-sky */
785 /* MIPS specific simulator watch config */
787 void watch_options_install
PARAMS ((SIM_DESC sd
));
796 /* FIXME: At present much of the simulator is still static */
801 sim_cpu cpu
[MAX_NR_PROCESSORS
];
803 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
805 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
808 /* start-sanitize-sky */
811 /* Record of option for floating point implementation type. */
813 #define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
814 #define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
817 /* end-sanitize-sky */
824 /* Status information: */
826 /* TODO : these should be the bitmasks for these bits within the
827 status register. At the moment the following are VR4300
829 #define status_KSU_mask (0x18) /* mask for KSU bits */
830 #define status_KSU_shift (3) /* shift for field */
831 #define ksu_kernel (0x0)
832 #define ksu_supervisor (0x1)
833 #define ksu_user (0x2)
834 #define ksu_unknown (0x3)
836 #define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
838 #define status_IE (1 << 0) /* Interrupt enable */
839 #define status_EIE (1 << 16) /* Enable Interrupt Enable */
840 #define status_EXL (1 << 1) /* Exception level */
841 #define status_RE (1 << 25) /* Reverse Endian in user mode */
842 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
843 #define status_SR (1 << 20) /* soft reset or NMI */
844 #define status_BEV (1 << 22) /* Location of general exception vectors */
845 #define status_TS (1 << 21) /* TLB shutdown has occurred */
846 #define status_ERL (1 << 2) /* Error level */
847 #define status_IM7 (1 << 15) /* Timer Interrupt Mask */
848 #define status_RP (1 << 27) /* Reduced Power mode */
849 /* start-sanitize-r5900 */
850 #define status_CU0 (1 << 28) /* COP0 usable */
851 #define status_CU1 (1 << 29) /* COP1 usable */
852 #define status_CU2 (1 << 30) /* COP2 usable */
853 /* end-sanitize-r5900 */
855 /* Specializations for TX39 family */
856 #define status_IEc (1 << 0) /* Interrupt enable (current) */
857 #define status_KUc (1 << 1) /* Kernel/User mode */
858 #define status_IEp (1 << 2) /* Interrupt enable (previous) */
859 #define status_KUp (1 << 3) /* Kernel/User mode */
860 #define status_IEo (1 << 4) /* Interrupt enable (old) */
861 #define status_KUo (1 << 5) /* Kernel/User mode */
862 #define status_IM_mask (0xff) /* Interrupt mask */
863 #define status_IM_shift (8)
864 #define status_NMI (1 << 20) /* NMI */
865 #define status_NMI (1 << 20) /* NMI */
867 #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
868 #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
869 #define cause_CE_mask 0x30000000 /* Coprocessor exception */
870 #define cause_CE_shift 28
871 #define cause_EXC2_mask 0x00070000
872 #define cause_EXC2_shift 16
873 #define cause_IP7 (1 << 15) /* Interrupt pending */
874 #define cause_SIOP (1 << 12) /* SIO pending */
875 #define cause_IP3 (1 << 11) /* Int 0 pending */
876 #define cause_IP2 (1 << 10) /* Int 1 pending */
878 /* start-sanitize-sky */
880 #define cause_EXC_mask (0x7c) /* Exception code */
882 /* end-sanitize-sky */
883 #define cause_EXC_mask (0x1c) /* Exception code */
884 /* start-sanitize-sky */
886 /* end-sanitize-sky */
887 #define cause_EXC_shift (2)
889 #define cause_SW0 (1 << 8) /* Software interrupt 0 */
890 #define cause_SW1 (1 << 9) /* Software interrupt 1 */
891 #define cause_IP_mask (0x3f) /* Interrupt pending field */
892 #define cause_IP_shift (10)
894 #define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
895 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
898 /* NOTE: We keep the following status flags as bit values (1 for true,
899 0 for false). This allows them to be used in binary boolean
900 operations without worrying about what exactly the non-zero true
904 #ifdef SUBTARGET_R3900
905 #define UserMode ((SR & status_KUc) ? 1 : 0)
907 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
908 #endif /* SUBTARGET_R3900 */
911 /* Hardware configuration. Affects endianness of LoadMemory and
912 StoreMemory and the endianness of Kernel and Supervisor mode
913 execution. The value is 0 for little-endian; 1 for big-endian. */
914 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
915 /*(state & simBE) ? 1 : 0)*/
918 /* This mode is selected if in User mode with the RE bit being set in
919 SR (Status Register). It reverses the endianness of load and store
921 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
924 /* The endianness for load and store instructions (0=little;1=big). In
925 User mode this endianness may be switched by setting the state_RE
926 bit in the SR register. Thus, BigEndianCPU may be computed as
927 (BigEndianMem EOR ReverseEndian). */
928 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
934 /* NOTE: These numbers depend on the processor architecture being
936 enum ExceptionCause
{
943 InstructionFetch
= 6,
947 ReservedInstruction
= 10,
948 CoProcessorUnusable
= 11,
949 IntegerOverflow
= 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
952 DebugBreakPoint
= 16,
957 /* The following exception code is actually private to the simulator
958 world. It is *NOT* a processor feature, and is used to signal
959 run-time errors in the simulator. */
960 SimulatorFault
= 0xFFFFFFFF
963 #define TLB_REFILL (0)
964 #define TLB_INVALID (1)
966 /* start-sanitize-r5900 */
967 /* For the 5900, we have level 1 and level 2 exceptions. The level 2 exceptions
968 are ColdReset, NMI, Counter, and Debug/SIO. Of these, we support only
969 the NMIReset exception. */
971 #define is5900Level2Exception(x) (x == NMIReset)
972 /* end-sanitize-r5900 */
974 /* The following break instructions are reserved for use by the
975 simulator. The first is used to halt the simulation. The second
976 is used by gdb for break-points. NOTE: Care must be taken, since
977 this value may be used in later revisions of the MIPS ISA. */
978 #define HALT_INSTRUCTION_MASK (0x03FFFFC0)
980 #define HALT_INSTRUCTION (0x03ff000d)
981 #define HALT_INSTRUCTION2 (0x0000ffcd)
983 /* start-sanitize-sky */
984 #define HALT_INSTRUCTION_PASS (0x03fffc0d) /* break 0xffff0 */
985 #define HALT_INSTRUCTION_FAIL (0x03ffffcd) /* break 0xfffff */
986 /* end-sanitize-sky */
988 #define BREAKPOINT_INSTRUCTION (0x0005000d)
989 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
991 /* start-sanitize-sky */
992 #define LOAD_INSTRUCTION (0x03fffc4d) /* break 0xffff1 */
993 #define PRINTF_INSTRUCTION (0x03fffc8d) /* break 0xffff2 */
994 /* end-sanitize-sky */
997 void interrupt_event (SIM_DESC sd
, void *data
);
999 void signal_exception (SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int exception
, ...);
1000 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
1001 #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
1002 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
1003 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
1004 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
1005 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
1006 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
1007 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
1008 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
1009 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
1010 #define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
1011 #define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
1012 #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
1013 #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
1014 #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
1016 /* Co-processor accesses */
1018 void cop_lw
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int coproc_num
, int coproc_reg
, unsigned int memword
));
1019 void cop_ld
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int coproc_num
, int coproc_reg
, uword64 memword
));
1020 unsigned int cop_sw
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int coproc_num
, int coproc_reg
));
1021 uword64 cop_sd
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int coproc_num
, int coproc_reg
));
1023 #define COP_LW(coproc_num,coproc_reg,memword) \
1024 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
1025 #define COP_LD(coproc_num,coproc_reg,memword) \
1026 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
1027 #define COP_SW(coproc_num,coproc_reg) \
1028 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
1029 #define COP_SD(coproc_num,coproc_reg) \
1030 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
1032 /* start-sanitize-sky */
1034 void cop_lq
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
,
1035 int coproc_num
, int coproc_reg
, unsigned128 memword
));
1036 unsigned128 cop_sq
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
,
1037 int coproc_num
, int coproc_reg
));
1038 #define COP_LQ(coproc_num,coproc_reg,memword) \
1039 cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
1040 #define COP_SQ(coproc_num,coproc_reg) \
1041 cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
1042 #endif /* TARGET_SKY */
1043 /* end-sanitize-sky */
1045 void decode_coproc
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, unsigned int instruction
));
1046 #define DecodeCoproc(instruction) \
1047 decode_coproc (SD, CPU, cia, (instruction))
1051 /* Memory accesses */
1053 /* The following are generic to all versions of the MIPS architecture
1056 /* Memory Access Types (for CCA): */
1057 #define Uncached (0)
1058 #define CachedNoncoherent (1)
1059 #define CachedCoherent (2)
1062 #define isINSTRUCTION (1 == 0) /* FALSE */
1063 #define isDATA (1 == 1) /* TRUE */
1064 #define isLOAD (1 == 0) /* FALSE */
1065 #define isSTORE (1 == 1) /* TRUE */
1066 #define isREAL (1 == 0) /* FALSE */
1067 #define isRAW (1 == 1) /* TRUE */
1068 /* The parameter HOST (isTARGET / isHOST) is ignored */
1069 #define isTARGET (1 == 0) /* FALSE */
1070 /* #define isHOST (1 == 1) TRUE */
1072 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
1073 is the number of bytes minus 1. */
1074 #define AccessLength_BYTE (0)
1075 #define AccessLength_HALFWORD (1)
1076 #define AccessLength_TRIPLEBYTE (2)
1077 #define AccessLength_WORD (3)
1078 #define AccessLength_QUINTIBYTE (4)
1079 #define AccessLength_SEXTIBYTE (5)
1080 #define AccessLength_SEPTIBYTE (6)
1081 #define AccessLength_DOUBLEWORD (7)
1082 #define AccessLength_QUADWORD (15)
1085 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
1086 ? AccessLength_DOUBLEWORD /*7*/ \
1087 : AccessLength_WORD /*3*/)
1088 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
1092 INLINE_SIM_MAIN (int) address_translation
PARAMS ((SIM_DESC sd
, sim_cpu
*, address_word cia
, address_word vAddr
, int IorD
, int LorS
, address_word
*pAddr
, int *CCA
, int raw
));
1093 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
1094 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
1096 INLINE_SIM_MAIN (void) load_memory
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, uword64
* memvalp
, uword64
* memval1p
, int CCA
, unsigned int AccessLength
, address_word pAddr
, address_word vAddr
, int IorD
));
1097 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
1098 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
1100 INLINE_SIM_MAIN (void) store_memory
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int CCA
, unsigned int AccessLength
, uword64 MemElem
, uword64 MemElem1
, address_word pAddr
, address_word vAddr
));
1101 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
1102 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
1104 INLINE_SIM_MAIN (void) cache_op
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int op
, address_word pAddr
, address_word vAddr
, unsigned int instruction
));
1105 #define CacheOp(op,pAddr,vAddr,instruction) \
1106 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
1108 INLINE_SIM_MAIN (void) sync_operation
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int stype
));
1109 #define SyncOperation(stype) \
1110 sync_operation (SD, CPU, cia, (stype))
1112 INLINE_SIM_MAIN (void) prefetch
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, int CCA
, address_word pAddr
, address_word vAddr
, int DATA
, int hint
));
1113 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
1114 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
1116 INLINE_SIM_MAIN (unsigned32
) ifetch32
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, address_word vaddr
));
1117 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
1118 INLINE_SIM_MAIN (unsigned16
) ifetch16
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, address_word vaddr
));
1119 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
1120 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
1122 void dotrace
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, FILE *tracefh
, int type
, SIM_ADDR address
, int width
, char *comment
, ...));
1123 extern FILE *tracefh
;
1125 INLINE_SIM_MAIN (void) pending_tick
PARAMS ((SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
));
1127 char* pr_addr
PARAMS ((SIM_ADDR addr
));
1128 char* pr_uword64
PARAMS ((uword64 addr
));
1130 /* start-sanitize-sky */
1133 #ifdef SIM_ENGINE_HALT_HOOK
1134 #undef SIM_ENGINE_HALT_HOOK
1137 void sky_sim_engine_halt
PARAMS ((SIM_DESC sd
, sim_cpu
*last
, sim_cia cia
));
1138 #define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia)
1140 #ifdef SIM_ENGINE_RESTART_HOOK
1141 #undef SIM_ENGINE_RESTART_HOOK
1144 void sky_sim_engine_restart
PARAMS ((SIM_DESC sd
, sim_cpu
*last
, sim_cia cia
));
1145 #define SIM_ENGINE_RESTART_HOOK(sd, L, pc) sky_sim_engine_restart(sd, L, pc)
1147 /* for resume/suspend modules */
1148 SIM_RC sky_sim_module_install
PARAMS ((SIM_DESC sd
));
1150 #define MODULE_LIST sky_sim_module_install,
1152 void sim_monitor (SIM_DESC sd
, sim_cpu
*cpu
, address_word cia
, unsigned int arg
);
1154 #ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
1155 enum txvu_cpu_context
1157 TXVU_CPU_AUTO
= -1, /* context-sensitive context */
1158 TXVU_CPU_MASTER
= 0, /* R5900 core */
1159 TXVU_CPU_VU0
= 1, /* Vector units */
1161 TXVU_CPU_VIF0
= 3, /* Vector interface units */
1163 TXVU_CPU_LAST
/* Count of context types */
1166 /* memory segment for communication with GDB */
1167 #define VIO_BASE 0xa0000000
1168 #define GDB_COMM_AREA 0x19810000 /* Random choice */
1169 #define GDB_COMM_SIZE 0x4000
1171 /* Memory address containing last device to execute */
1172 #define LAST_DEVICE GDB_COMM_AREA
1174 /* The FIFO breakpoint count and table */
1175 #define FIFO_BPT_CNT (GDB_COMM_AREA + 4)
1176 #define FIFO_BPT_TBL (GDB_COMM_AREA + 8)
1178 /* Each element of the breakpoint table is three four-byte integers. */
1179 #define BPT_ELEM_SZ 4*3
1181 #define TXVU_VU_BRK_MASK 0x02 /* Breakpoint bit is #57 for VU insns */
1182 #define TXVU_VIF_BRK_MASK 0x80 /* Use interrupt bit for VIF insns */
1184 #endif /* !TM_TXVU_H */
1185 #endif /* TARGET_SKY */
1186 /* end-sanitize-sky */
1188 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1189 #include "sim-main.c"