sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35
  36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  38
  39 #include "sim-basics.h"
  40
  41 typedef address_word sim_cia;
  42
  43 #include "sim-base.h"
  44
  45
  46 /* Depreciated macros and types for manipulating 64bit values.  Use
  47    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  48
  49 typedef signed64 word64;
  50 typedef unsigned64 uword64;
  51
  52 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  53 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  54 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  55 #define SET64HI(t)      (((uword64)(t))<<32)
  56 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  57 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  58
  59 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  60    assume the HI32bits of the operand are zero, so we must perform a
  61    mask to ensure we can use the simple subtraction to sign-extend. */
  62 #define SIGNEXTEND(e,b) \
  63  ((unsigned_word) \
  64   (((e) & ((uword64) 1 << ((b) - 1))) \
  65    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  66    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  67
  68 /* Check if a value will fit within a halfword: */
  69 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  70
  71
  72
  73 /* Floating-point operations: */
  74
  75 #include "sim-fpu.h"
  76
  77 /* FPU registers must be one of the following types. All other values
  78    are reserved (and undefined). */
  79 typedef enum {
  80  fmt_single  = 0,
  81  fmt_double  = 1,
  82  fmt_word    = 4,
  83  fmt_long    = 5,
  84  /* The following are well outside the normal acceptable format
  85     range, and are used in the register status vector. */
  86  fmt_unknown       = 0x10000000,
  87  fmt_uninterpreted = 0x20000000,
  88  fmt_uninterpreted_32 = 0x40000000,
  89  fmt_uninterpreted_64 = 0x80000000U,
  90 } FP_formats;
  91
  92 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  93 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  94
  95 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
  96 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
  97
  98 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
  99 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 100 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 101 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 102 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 103 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 104 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 105 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 106 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 107 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 108 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 109 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 110 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 113 #define Convert(rm,op,from,to) \
 114 convert (SD, CPU, cia, rm, op, from, to)
 115
 116 /* Macro to update FPSR condition-code field. This is complicated by
 117    the fact that there is a hole in the index range of the bits within
 118    the FCSR register. Also, the number of bits visible depends on the
 119    MIPS ISA version being supported. */
 120
 121 #define SETFCC(cc,v) {\
 122   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 123   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 124 }
 125 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 126
 127 /* This should be the COC1 value at the start of the preceding
 128    instruction: */
 129 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 130
 131 #ifdef TARGET_ENABLE_FR
 132 /* FIXME: this should be enabled for all targets, but needs testing first. */
 133 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
 134    ? ((SR & status_FR) ? 64 : 32) \
 135    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
 136 #else
 137 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 138 #endif
 139
 140 /* Standard FCRS bits: */
 141 #define IR (0) /* Inexact Result */
 142 #define UF (1) /* UnderFlow */
 143 #define OF (2) /* OverFlow */
 144 #define DZ (3) /* Division by Zero */
 145 #define IO (4) /* Invalid Operation */
 146 #define UO (5) /* Unimplemented Operation */
 147
 148 /* Get masks for individual flags: */
 149 #if 1 /* SAFE version */
 150 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 151 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 152 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 153 #else
 154 #define FP_FLAGS(b)  (1 << ((b) + 2))
 155 #define FP_ENABLE(b) (1 << ((b) + 7))
 156 #define FP_CAUSE(b)  (1 << ((b) + 12))
 157 #endif
 158
 159 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 160
 161 #define FP_MASK_RM    (0x3)
 162 #define FP_SH_RM      (0)
 163 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 164 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 165 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 166 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 167 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 168
 169
 170
 171
 172
 173
 174 /* HI/LO register accesses */
 175
 176 /* For some MIPS targets, the HI/LO registers have certain timing
 177    restrictions in that, for instance, a read of a HI register must be
 178    separated by at least three instructions from a preceeding read.
 179
 180    The struct below is used to record the last access by each of A MT,
 181    MF or other OP instruction to a HI/LO register.  See mips.igen for
 182    more details. */
 183
 184 typedef struct _hilo_access {
 185   signed64 timestamp;
 186   address_word cia;
 187 } hilo_access;
 188
 189 typedef struct _hilo_history {
 190   hilo_access mt;
 191   hilo_access mf;
 192   hilo_access op;
 193 } hilo_history;
 194
 195
 196
 197
 198 /* Integer ALU operations: */
 199
 200 #include "sim-alu.h"
 201
 202 #define ALU32_END(ANS) \
 203   if (ALU32_HAD_OVERFLOW) \
 204     SignalExceptionIntegerOverflow (); \
 205   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 206
 207
 208 #define ALU64_END(ANS) \
 209   if (ALU64_HAD_OVERFLOW) \
 210     SignalExceptionIntegerOverflow (); \
 211   (ANS) = ALU64_OVERFLOW_RESULT;
 212
 213
 214
 215
 216
 217 /* The following is probably not used for MIPS IV onwards: */
 218 /* Slots for delayed register updates. For the moment we just have a
 219    fixed number of slots (rather than a more generic, dynamic
 220    system). This keeps the simulator fast. However, we only allow
 221    for the register update to be delayed for a single instruction
 222    cycle. */
 223 #define PSLOTS (8) /* Maximum number of instruction cycles */
 224
 225 typedef struct _pending_write_queue {
 226   int in;
 227   int out;
 228   int total;
 229   int slot_delay[PSLOTS];
 230   int slot_size[PSLOTS];
 231   int slot_bit[PSLOTS];
 232   void *slot_dest[PSLOTS];
 233   unsigned64 slot_value[PSLOTS];
 234 } pending_write_queue;
 235
 236 #ifndef PENDING_TRACE
 237 #define PENDING_TRACE 0
 238 #endif
 239 #define PENDING_IN ((CPU)->pending.in)
 240 #define PENDING_OUT ((CPU)->pending.out)
 241 #define PENDING_TOTAL ((CPU)->pending.total)
 242 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 243 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 244 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 245 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 246 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 247
 248 /* Invalidate the pending write queue, all pending writes are
 249    discarded. */
 250
 251 #define PENDING_INVALIDATE() \
 252 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 253
 254 /* Schedule a write to DEST for N cycles time.  For 64 bit
 255    destinations, schedule two writes.  For floating point registers,
 256    the caller should schedule a write to both the dest register and
 257    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 258    is updated. */
 259
 260 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 261   do {                                                                  \
 262     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 263       sim_engine_abort (SD, CPU, cia,                                   \
 264                         "PENDING_SCHED - buffer overflow\n");           \
 265     if (PENDING_TRACE)                                                  \
 266       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 267                       (unsigned long) cia, (unsigned long) &(DEST),     \
 268                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 269                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 270     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 271     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 272     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 273     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 274     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 275     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 276     PENDING_TOTAL += 1;                                                 \
 277   } while (0)
 278
 279 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 280 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 281
 282 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 283
 284 #define PENDING_FLUSH() abort () /* think about this one */
 285 #define PENDING_FP() abort () /* think about this one */
 286
 287 /* For backward compatibility */
 288 #define PENDING_FILL(R,VAL)                                             \
 289 do {                                                                    \
 290   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 291     {                                                                   \
 292       PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1);                     \
 293       PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
 294     }                                                                   \
 295   else                                                                  \
 296     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 297 } while (0)
 298
 299
 300
 301 struct _sim_cpu {
 302
 303
 304   /* The following are internal simulator state variables: */
 305 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 306 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 307   address_word dspc;  /* delay-slot PC */
 308 #define DSPC ((CPU)->dspc)
 309
 310 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 311 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 312
 313
 314   /* State of the simulator */
 315   unsigned int state;
 316   unsigned int dsstate;
 317 #define STATE ((CPU)->state)
 318 #define DSSTATE ((CPU)->dsstate)
 319
 320 /* Flags in the "state" variable: */
 321 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 322 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 323 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 324 #define simPCOC0        (1 << 17) /* COC[1] from current */
 325 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 326 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 327 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 328 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 329 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 330
 331 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 332 #define ENGINE_ISSUE_PREFIX_HOOK() \
 333   { \
 334     /* Perform any pending writes */ \
 335     PENDING_TICK(); \
 336     /* Set previous flag, depending on current: */ \
 337     if (STATE & simPCOC0) \
 338      STATE |= simPCOC1; \
 339     else \
 340      STATE &= ~simPCOC1; \
 341     /* and update the current value: */ \
 342     if (GETFCC(0)) \
 343      STATE |= simPCOC0; \
 344     else \
 345      STATE &= ~simPCOC0; \
 346   }
 347 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 348
 349
 350 /* This is nasty, since we have to rely on matching the register
 351    numbers used by GDB. Unfortunately, depending on the MIPS target
 352    GDB uses different register numbers. We cannot just include the
 353    relevant "gdb/tm.h" link, since GDB may not be configured before
 354    the sim world, and also the GDB header file requires too much other
 355    state. */
 356
 357 #ifndef TM_MIPS_H
 358 #define LAST_EMBED_REGNUM (89)
 359 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 360
 361
 362 #endif
 363
 364
 365 enum float_operation
 366   {
 367     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 368     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 369     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 370   };
 371
 372 /* To keep this default simulator simple, and fast, we use a direct
 373    vector of registers. The internal simulator engine then uses
 374    manifests to access the correct slot. */
 375
 376   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 377
 378   int register_widths[NUM_REGS];
 379 #define REGISTERS       ((CPU)->registers)
 380
 381 #define GPR     (&REGISTERS[0])
 382 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 383
 384   /* While space is allocated for the floating point registers in the
 385      main registers array, they are stored separatly.  This is because
 386      their size may not necessarily match the size of either the
 387      general-purpose or system specific registers */
 388 #define NR_FGR  (32)
 389 #define FGRIDX  (38)
 390   fp_word fgr[NR_FGR];
 391 #define FGR     ((CPU)->fgr)
 392
 393 #define LO      (REGISTERS[33])
 394 #define HI      (REGISTERS[34])
 395 #define PCIDX   37
 396 #define PC      (REGISTERS[PCIDX])
 397 #define CAUSE   (REGISTERS[36])
 398 #define SRIDX   (32)
 399 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 400 #define FCR0IDX  (71)
 401 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 402 #define FCR31IDX (70)
 403 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 404 #define FCSR    (FCR31)
 405 #define Debug   (REGISTERS[86])
 406 #define DEPC    (REGISTERS[87])
 407 #define EPC     (REGISTERS[88])
 408 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 409
 410   /* All internal state modified by signal_exception() that may need to be
 411      rolled back for passing moment-of-exception image back to gdb. */
 412   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 413   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 414   int exc_suspended;
 415
 416 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 417 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 418 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 419
 420   unsigned_word c0_config_reg;
 421 #define C0_CONFIG ((CPU)->c0_config_reg)
 422
 423 /* The following are pseudonyms for standard registers */
 424 #define ZERO    (REGISTERS[0])
 425 #define V0      (REGISTERS[2])
 426 #define A0      (REGISTERS[4])
 427 #define A1      (REGISTERS[5])
 428 #define A2      (REGISTERS[6])
 429 #define A3      (REGISTERS[7])
 430 #define T8IDX   24
 431 #define T8      (REGISTERS[T8IDX])
 432 #define SPIDX   29
 433 #define SP      (REGISTERS[SPIDX])
 434 #define RAIDX   31
 435 #define RA      (REGISTERS[RAIDX])
 436
 437   /* While space is allocated in the main registers arrray for some of
 438      the COP0 registers, that space isn't sufficient.  Unknown COP0
 439      registers overflow into the array below */
 440
 441 #define NR_COP0_GPR     32
 442   unsigned_word cop0_gpr[NR_COP0_GPR];
 443 #define COP0_GPR        ((CPU)->cop0_gpr)
 444 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 445
 446   /* Keep the current format state for each register: */
 447   FP_formats fpr_state[32];
 448 #define FPR_STATE ((CPU)->fpr_state)
 449
 450   pending_write_queue pending;
 451
 452   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 453      read-write instructions. It is set when a linked load occurs. It
 454      is tested and cleared by the conditional store. It is cleared
 455      (during other CPU operations) when a store to the location would
 456      no longer be atomic. In particular, it is cleared by exception
 457      return instructions. */
 458   int llbit;
 459 #define LLBIT ((CPU)->llbit)
 460
 461
 462 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 463    corruptions caused by using the HI or LO register too close to a
 464    following operation is spotted. See mips.igen for more details. */
 465
 466   hilo_history hi_history;
 467 #define HIHISTORY (&(CPU)->hi_history)
 468   hilo_history lo_history;
 469 #define LOHISTORY (&(CPU)->lo_history)
 470
 471 #define check_branch_bug()
 472 #define mark_branch_bug(TARGET)
 473
 474
 475
 476   sim_cpu_base base;
 477 };
 478
 479
 480 /* MIPS specific simulator watch config */
 481
 482 void watch_options_install PARAMS ((SIM_DESC sd));
 483
 484 struct swatch {
 485   sim_event *pc;
 486   sim_event *clock;
 487   sim_event *cycles;
 488 };
 489
 490
 491 /* FIXME: At present much of the simulator is still static */
 492 struct sim_state {
 493
 494   struct swatch watch;
 495
 496   sim_cpu cpu[MAX_NR_PROCESSORS];
 497 #if (WITH_SMP)
 498 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 499 #else
 500 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 501 #endif
 502
 503
 504   sim_state_base base;
 505 };
 506
 507
 508
 509 /* Status information: */
 510
 511 /* TODO : these should be the bitmasks for these bits within the
 512    status register. At the moment the following are VR4300
 513    bit-positions: */
 514 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 515 #define status_KSU_shift (3)            /* shift for field */
 516 #define ksu_kernel       (0x0)
 517 #define ksu_supervisor   (0x1)
 518 #define ksu_user         (0x2)
 519 #define ksu_unknown      (0x3)
 520
 521 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 522
 523 #define status_IE        (1 <<  0)      /* Interrupt enable */
 524 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 525 #define status_EXL       (1 <<  1)      /* Exception level */
 526 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 527 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 528 #define status_SR        (1 << 20)      /* soft reset or NMI */
 529 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 530 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 531 #define status_ERL       (1 <<  2)      /* Error level */
 532 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 533 #define status_RP        (1 << 27)      /* Reduced Power mode */
 534
 535 /* Specializations for TX39 family */
 536 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 537 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 538 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 539 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 540 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 541 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 542 #define status_IM_mask   (0xff)         /* Interrupt mask */
 543 #define status_IM_shift  (8)
 544 #define status_NMI       (1 << 20)      /* NMI */
 545 #define status_NMI       (1 << 20)      /* NMI */
 546
 547 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 548 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 549 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 550 #define cause_CE_shift    28
 551 #define cause_EXC2_mask   0x00070000
 552 #define cause_EXC2_shift  16
 553 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 554 #define cause_SIOP        (1 << 12)     /* SIO pending */
 555 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 556 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 557
 558 #define cause_EXC_mask  (0x1c)          /* Exception code */
 559 #define cause_EXC_shift (2)
 560
 561 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 562 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 563 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 564 #define cause_IP_shift  (10)
 565
 566 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 567 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 568
 569
 570 /* NOTE: We keep the following status flags as bit values (1 for true,
 571    0 for false). This allows them to be used in binary boolean
 572    operations without worrying about what exactly the non-zero true
 573    value is. */
 574
 575 /* UserMode */
 576 #ifdef SUBTARGET_R3900
 577 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 578 #else
 579 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 580 #endif /* SUBTARGET_R3900 */
 581
 582 /* BigEndianMem */
 583 /* Hardware configuration. Affects endianness of LoadMemory and
 584    StoreMemory and the endianness of Kernel and Supervisor mode
 585    execution. The value is 0 for little-endian; 1 for big-endian. */
 586 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 587 /*(state & simBE) ? 1 : 0)*/
 588
 589 /* ReverseEndian */
 590 /* This mode is selected if in User mode with the RE bit being set in
 591    SR (Status Register). It reverses the endianness of load and store
 592    instructions. */
 593 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 594
 595 /* BigEndianCPU */
 596 /* The endianness for load and store instructions (0=little;1=big). In
 597    User mode this endianness may be switched by setting the state_RE
 598    bit in the SR register. Thus, BigEndianCPU may be computed as
 599    (BigEndianMem EOR ReverseEndian). */
 600 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 601
 602
 603
 604 /* Exceptions: */
 605
 606 /* NOTE: These numbers depend on the processor architecture being
 607    simulated: */
 608 enum ExceptionCause {
 609   Interrupt               = 0,
 610   TLBModification         = 1,
 611   TLBLoad                 = 2,
 612   TLBStore                = 3,
 613   AddressLoad             = 4,
 614   AddressStore            = 5,
 615   InstructionFetch        = 6,
 616   DataReference           = 7,
 617   SystemCall              = 8,
 618   BreakPoint              = 9,
 619   ReservedInstruction     = 10,
 620   CoProcessorUnusable     = 11,
 621   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 622   Trap                    = 13,
 623   FPE                     = 15,
 624   DebugBreakPoint         = 16,
 625   Watch                   = 23,
 626   NMIReset                = 31,
 627
 628
 629 /* The following exception code is actually private to the simulator
 630    world. It is *NOT* a processor feature, and is used to signal
 631    run-time errors in the simulator. */
 632   SimulatorFault          = 0xFFFFFFFF
 633 };
 634
 635 #define TLB_REFILL  (0)
 636 #define TLB_INVALID (1)
 637
 638
 639 /* The following break instructions are reserved for use by the
 640    simulator.  The first is used to halt the simulation.  The second
 641    is used by gdb for break-points.  NOTE: Care must be taken, since
 642    this value may be used in later revisions of the MIPS ISA. */
 643 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 644
 645 #define HALT_INSTRUCTION        (0x03ff000d)
 646 #define HALT_INSTRUCTION2       (0x0000ffcd)
 647
 648
 649 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 650 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 651
 652
 653
 654 void interrupt_event (SIM_DESC sd, void *data);
 655
 656 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 657 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 658 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 659 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 660 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 661 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 662 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 663 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 664 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 665 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 666 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
 667 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 668 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 669 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 670 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 671 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 672 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 673
 674 /* Co-processor accesses */
 675
 676 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 677 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 678 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 679 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 680
 681 #define COP_LW(coproc_num,coproc_reg,memword) \
 682 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 683 #define COP_LD(coproc_num,coproc_reg,memword) \
 684 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 685 #define COP_SW(coproc_num,coproc_reg) \
 686 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 687 #define COP_SD(coproc_num,coproc_reg) \
 688 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 689
 690
 691 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 692 #define DecodeCoproc(instruction) \
 693 decode_coproc (SD, CPU, cia, (instruction))
 694
 695 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 696
 697
 698
 699 /* Memory accesses */
 700
 701 /* The following are generic to all versions of the MIPS architecture
 702    to date: */
 703
 704 /* Memory Access Types (for CCA): */
 705 #define Uncached                (0)
 706 #define CachedNoncoherent       (1)
 707 #define CachedCoherent          (2)
 708 #define Cached                  (3)
 709
 710 #define isINSTRUCTION   (1 == 0) /* FALSE */
 711 #define isDATA          (1 == 1) /* TRUE */
 712 #define isLOAD          (1 == 0) /* FALSE */
 713 #define isSTORE         (1 == 1) /* TRUE */
 714 #define isREAL          (1 == 0) /* FALSE */
 715 #define isRAW           (1 == 1) /* TRUE */
 716 /* The parameter HOST (isTARGET / isHOST) is ignored */
 717 #define isTARGET        (1 == 0) /* FALSE */
 718 /* #define isHOST          (1 == 1) TRUE */
 719
 720 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 721    is the number of bytes minus 1. */
 722 #define AccessLength_BYTE       (0)
 723 #define AccessLength_HALFWORD   (1)
 724 #define AccessLength_TRIPLEBYTE (2)
 725 #define AccessLength_WORD       (3)
 726 #define AccessLength_QUINTIBYTE (4)
 727 #define AccessLength_SEXTIBYTE  (5)
 728 #define AccessLength_SEPTIBYTE  (6)
 729 #define AccessLength_DOUBLEWORD (7)
 730 #define AccessLength_QUADWORD   (15)
 731
 732 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 733                     ? AccessLength_DOUBLEWORD /*7*/ \
 734                     : AccessLength_WORD /*3*/)
 735 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 736
 737
 738 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 739 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 740 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 741
 742 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 743 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 744 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 745
 746 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 747 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 748 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 749
 750 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 751 #define CacheOp(op,pAddr,vAddr,instruction) \
 752 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 753
 754 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 755 #define SyncOperation(stype) \
 756 sync_operation (SD, CPU, cia, (stype))
 757
 758 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 759 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 760 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 761
 762 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 763 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 764 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 765 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 766 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 767
 768 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 769 extern FILE *tracefh;
 770
 771 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 772 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 773
 774 char* pr_addr PARAMS ((SIM_ADDR addr));
 775 char* pr_uword64 PARAMS ((uword64 addr));
 776
 777
 778 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
 779
 780 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 781 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 782 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 783
 784
 785 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 786 #include "sim-main.c"
 787 #endif
 788
 789 #endif