sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75 /* windows always looses */
  76 #include <signal.h>
  77 #ifndef SIGBUS
  78 #define SIGBUS SIGSEGV
  79 #endif
  80 #ifdef _WIN32
  81 #define SIGTRAP 5
  82 #define SIGQUIT 3
  83 #endif
  84
  85
  86
  87 /* Floating-point operations: */
  88
  89 /* FPU registers must be one of the following types. All other values
  90    are reserved (and undefined). */
  91 typedef enum {
  92  fmt_single  = 0,
  93  fmt_double  = 1,
  94  fmt_word    = 4,
  95  fmt_long    = 5,
  96  /* The following are well outside the normal acceptable format
  97     range, and are used in the register status vector. */
  98  fmt_unknown       = 0x10000000,
  99  fmt_uninterpreted = 0x20000000,
 100 } FP_formats;
 101
 102 unsigned64 value_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats));
 103 #define ValueFPR(FPR,FMT) value_fpr (sd, cia, (FPR), (FMT))
 104
 105 void store_fpr PARAMS ((SIM_DESC sd, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
 106 #define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, cia, (FPR), (FMT), (VALUE))
 107
 108 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 109 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 110 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 113 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 114 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 115 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 116 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 117 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 118 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 119 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 120 unsigned64 convert PARAMS ((SIM_DESC sd, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 121 #define Convert(rm,op,from,to) convert(sd,cia,rm,op,from,to)
 122
 123 /* Macro to update FPSR condition-code field. This is complicated by
 124    the fact that there is a hole in the index range of the bits within
 125    the FCSR register. Also, the number of bits visible depends on the
 126    MIPS ISA version being supported. */
 127
 128 #define SETFCC(cc,v) {\
 129   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 130   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 131 }
 132 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
 133
 134 /* This should be the COC1 value at the start of the preceding
 135    instruction: */
 136 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 137
 138 #if 1
 139 #define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
 140 #else
 141 /* They depend on the CPU being simulated */
 142 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 143 #endif
 144
 145 /* Standard FCRS bits: */
 146 #define IR (0) /* Inexact Result */
 147 #define UF (1) /* UnderFlow */
 148 #define OF (2) /* OverFlow */
 149 #define DZ (3) /* Division by Zero */
 150 #define IO (4) /* Invalid Operation */
 151 #define UO (5) /* Unimplemented Operation */
 152
 153 /* Get masks for individual flags: */
 154 #if 1 /* SAFE version */
 155 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 156 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 157 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 158 #else
 159 #define FP_FLAGS(b)  (1 << ((b) + 2))
 160 #define FP_ENABLE(b) (1 << ((b) + 7))
 161 #define FP_CAUSE(b)  (1 << ((b) + 12))
 162 #endif
 163
 164 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 165
 166 #define FP_MASK_RM    (0x3)
 167 #define FP_SH_RM      (0)
 168 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 169 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 170 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 171 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 172 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 173
 174
 175
 176 /* Integer ALU operations: */
 177
 178 #include "sim-alu.h"
 179
 180 #define ALU32_END(ANS) \
 181   if (ALU32_HAD_OVERFLOW) \
 182     SignalExceptionIntegerOverflow (); \
 183   (ANS) = ALU32_OVERFLOW_RESULT
 184
 185
 186 #define ALU64_END(ANS) \
 187   if (ALU64_HAD_OVERFLOW) \
 188     SignalExceptionIntegerOverflow (); \
 189   (ANS) = ALU64_OVERFLOW_RESULT;
 190
 191 /* start-sanitize-r5900 */
 192
 193 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 194 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 195 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 196 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 197
 198 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 199 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 200 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 201 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 202
 203 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 204    T  - type of the sub part
 205    TC - # of T's in the mips part of the "register"
 206    I  - index (from 0) of desired sub part
 207    A  - low part of "register"
 208    A1 - high part of register
 209 */
 210 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 211 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 212    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 213       ? ((TC) - 1 - (I) % (TC)) \
 214       : ((I) % (TC)) \
 215       ) \
 216    ) \
 217  )
 218
 219 /*
 220 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 221             where <type> has two letters:
 222                   1 is S=signed or U=unsigned
 223                   2 is B=byte H=halfword W=word D=doubleword
 224 */
 225
 226 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 227 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 228 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 229 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 230
 231 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 232 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 233 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 234 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 235
 236 #define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I)
 237 #define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I)
 238 #define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I)
 239 #define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I)
 240
 241 #define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I)
 242 #define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I)
 243 #define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I)
 244 #define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I)
 245
 246
 247 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 248 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 249 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 250 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 251
 252 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 253 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 254 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 255 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 256
 257 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 258 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 259 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 260 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 261
 262 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 263 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 264 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 265 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 266
 267
 268
 269 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 270 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 271 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 272 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 273
 274 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 275 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 276 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 277 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 278
 279 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 280 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 281 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 282 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 283
 284 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 285 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 286 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 287 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 288
 289 /* end-sanitize-r5900 */
 290
 291
 292
 293
 294 struct _sim_cpu {
 295
 296
 297   /* The following are internal simulator state variables: */
 298 #define CPU_CIA(CPU) (PC)
 299   address_word dspc;  /* delay-slot PC */
 300 #define DSPC ((STATE_CPU (sd,0))->dspc)
 301
 302   /* Issue a delay slot instruction immediatly by re-calling
 303      idecode_issue */
 304 #define DELAY_SLOT(TARGET) \
 305   do { \
 306     address_word target = (TARGET); \
 307     instruction_word delay_insn; \
 308     sim_events_slip (sd, 1); \
 309     CIA = CIA + 4; \
 310     STATE |= simDELAYSLOT; \
 311     delay_insn = IMEM (CIA); \
 312     idecode_issue (sd, delay_insn, (CIA)); \
 313     STATE &= ~simDELAYSLOT; \
 314     NIA = target; \
 315   } while (0)
 316 #define NULLIFY_NEXT_INSTRUCTION() \
 317   do { \
 318     sim_events_slip (sd, 1); \
 319     dotrace (sd, tracefh, 2, NIA, 4, "load instruction"); \
 320     NIA = CIA + 8; \
 321   } while (0)
 322
 323
 324
 325   /* State of the simulator */
 326   unsigned int state;
 327   unsigned int dsstate;
 328 #define STATE ((STATE_CPU (sd,0))->state)
 329 #define DSSTATE ((STATE_CPU (sd,0))->dsstate)
 330
 331 /* Flags in the "state" variable: */
 332 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 333 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 334 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 335 #define simPCOC0        (1 << 17) /* COC[1] from current */
 336 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 337 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 338 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 339 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 340 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 341
 342
 343
 344
 345 /* This is nasty, since we have to rely on matching the register
 346    numbers used by GDB. Unfortunately, depending on the MIPS target
 347    GDB uses different register numbers. We cannot just include the
 348    relevant "gdb/tm.h" link, since GDB may not be configured before
 349    the sim world, and also the GDB header file requires too much other
 350    state. */
 351
 352 #ifndef TM_MIPS_H
 353 #define LAST_EMBED_REGNUM (89)
 354 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 355 /* start-sanitize-r5900 */
 356 #undef NUM_REGS
 357 #define NUM_REGS (128)
 358 /* end-sanitize-r5900 */
 359 #endif
 360
 361 /* To keep this default simulator simple, and fast, we use a direct
 362    vector of registers. The internal simulator engine then uses
 363    manifests to access the correct slot. */
 364
 365   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 366   int register_widths[NUM_REGS];
 367 #define REGISTERS       ((STATE_CPU (sd,0))->registers)
 368
 369 #define GPR     (&REGISTERS[0])
 370 #define FGRIDX  (38)
 371 #define FGR     (&REGISTERS[FGRIDX])
 372 #define LO      (REGISTERS[33])
 373 #define HI      (REGISTERS[34])
 374 #define PC      (REGISTERS[37])
 375 #define CAUSE   (REGISTERS[36])
 376 #define SRIDX   (32)
 377 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 378 #define FCR0IDX  (71)
 379 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 380 #define FCR31IDX (70)
 381 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 382 #define FCSR    (FCR31)
 383 #define Debug   (REGISTERS[86])
 384 #define DEPC    (REGISTERS[87])
 385 #define EPC     (REGISTERS[88])
 386 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 387
 388 /* The following are pseudonyms for standard registers */
 389 #define ZERO    (REGISTERS[0])
 390 #define V0      (REGISTERS[2])
 391 #define A0      (REGISTERS[4])
 392 #define A1      (REGISTERS[5])
 393 #define A2      (REGISTERS[6])
 394 #define A3      (REGISTERS[7])
 395 #define SP      (REGISTERS[29])
 396 #define RA      (REGISTERS[31])
 397
 398   /* Keep the current format state for each register: */
 399   FP_formats fpr_state[32];
 400 #define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
 401
 402
 403   /* Slots for delayed register updates. For the moment we just have a
 404      fixed number of slots (rather than a more generic, dynamic
 405      system). This keeps the simulator fast. However, we only allow
 406      for the register update to be delayed for a single instruction
 407      cycle. */
 408 #define PSLOTS (5) /* Maximum number of instruction cycles */
 409   int pending_in;
 410   int pending_out;
 411   int pending_total;
 412   int pending_slot_count[PSLOTS];
 413   int pending_slot_reg[PSLOTS];
 414   unsigned_word pending_slot_value[PSLOTS];
 415 #define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
 416 #define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
 417 #define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
 418 #define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
 419 #define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
 420 #define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
 421
 422   /* The following are not used for MIPS IV onwards: */
 423 #define PENDING_FILL(r,v) {\
 424 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
 425                             if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
 426                              sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
 427                             PENDING_SLOT_COUNT[PENDING_IN] = 2;\
 428                             PENDING_SLOT_REG[PENDING_IN] = (r);\
 429                             PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
 430 /*printf("DBG: FILL        reg %d value = 0x%s\n",(r),pr_addr(v));*/\
 431                             PENDING_TOTAL++;\
 432                             PENDING_IN++;\
 433                             if (PENDING_IN == PSLOTS)\
 434                              PENDING_IN = 0;\
 435 /*printf("DBG: FILL AFTER  pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
 436                           }
 437
 438
 439   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 440      read-write instructions. It is set when a linked load occurs. It
 441      is tested and cleared by the conditional store. It is cleared
 442      (during other CPU operations) when a store to the location would
 443      no longer be atomic. In particular, it is cleared by exception
 444      return instructions. */
 445   int llbit;
 446 #define LLBIT ((STATE_CPU (sd, 0))->llbit)
 447
 448
 449 /* The HIACCESS and LOACCESS counts are used to ensure that
 450    corruptions caused by using the HI or LO register to close to a
 451    following operation are spotted. */
 452
 453   int hiaccess;
 454   int loaccess;
 455 #define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
 456 #define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
 457   /* start-sanitize-r5900 */
 458   int hi1access;
 459   int lo1access;
 460 #define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
 461 #define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
 462   /* end-sanitize-r5900 */
 463 #if 1
 464   /* The 4300 and a few other processors have interlocks on hi/lo
 465      register reads, and hence do not have this problem.  To avoid
 466      spurious warnings, we just disable this always.  */
 467 #define CHECKHILO(s)
 468 #else
 469   unsigned_word HLPC;
 470   /* If either of the preceding two instructions have accessed the HI
 471      or LO registers, then the values they see should be
 472      undefined. However, to keep the simulator world simple, we just
 473      let them use the value read and raise a warning to notify the
 474      user: */
 475 #define CHECKHILO(s) {\
 476   if ((HIACCESS != 0) || (LOACCESS != 0)) \
 477     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 478 }
 479   /* start-sanitize-r5900 */
 480 #undef CHECKHILO
 481 #define CHECKHILO(s) {\
 482   if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
 483     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 484 }
 485   /* end-sanitize-r5900 */
 486 #endif
 487
 488
 489   /* start-sanitize-r5900 */
 490   /* The R5900 has 128 bit registers, but the hi 64 bits are only
 491      touched by multimedia (MMI) instructions.  The normal mips
 492      instructions just use the lower 64 bits.  To avoid changing the
 493      older parts of the simulator to handle this weirdness, the high
 494      64 bits of each register are kept in a separate array
 495      (registers1).  The high 64 bits of any register are by convention
 496      refered by adding a '1' to the end of the normal register's name.
 497      So LO still refers to the low 64 bits of the LO register, LO1
 498      refers to the high 64 bits of that same register.  */
 499
 500   signed_word registers1[LAST_EMBED_REGNUM + 1];
 501 #define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
 502 #define GPR1     (&REGISTERS1[0])
 503 #define LO1      (REGISTERS1[32])
 504 #define HI1      (REGISTERS1[33])
 505 #define REGISTER_SA     (124)
 506
 507   unsigned_word sa;        /* the shift amount register */
 508 #define SA ((STATE_CPU (sd, 0))->sa)
 509
 510   /* end-sanitize-r5900 */
 511   /* start-sanitize-vr5400 */
 512
 513   /* end-sanitize-vr5400 */
 514
 515
 516
 517   sim_cpu_base base;
 518 };
 519
 520
 521 /* MIPS specific simulator watch config */
 522
 523 void watch_options_install PARAMS ((SIM_DESC sd));
 524
 525 struct swatch {
 526   sim_event *pc;
 527   sim_event *clock;
 528   sim_event *cycles;
 529 };
 530
 531
 532 /* FIXME: At present much of the simulator is still static */
 533 struct sim_state {
 534
 535   struct swatch watch;
 536
 537   sim_cpu cpu[1];
 538 #if (WITH_SMP)
 539 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 540 #else
 541 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 542 #endif
 543
 544   sim_state_base base;
 545 };
 546
 547
 548
 549 /* Status information: */
 550
 551 /* TODO : these should be the bitmasks for these bits within the
 552    status register. At the moment the following are VR4300
 553    bit-positions: */
 554 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 555 #define status_KSU_shift (3)            /* shift for field */
 556 #define ksu_kernel       (0x0)
 557 #define ksu_supervisor   (0x1)
 558 #define ksu_user         (0x2)
 559 #define ksu_unknown      (0x3)
 560
 561 #define status_IE        (1 <<  0)      /* Interrupt enable */
 562 #define status_EXL       (1 <<  1)      /* Exception level */
 563 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 564 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 565 #define status_SR        (1 << 20)      /* soft reset or NMI */
 566 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 567 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 568 #define status_ERL       (1 <<  2)      /* Error level */
 569 #define status_RP        (1 << 27)      /* Reduced Power mode */
 570
 571 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 572
 573 /* NOTE: We keep the following status flags as bit values (1 for true,
 574    0 for false). This allows them to be used in binary boolean
 575    operations without worrying about what exactly the non-zero true
 576    value is. */
 577
 578 /* UserMode */
 579 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 580
 581 /* BigEndianMem */
 582 /* Hardware configuration. Affects endianness of LoadMemory and
 583    StoreMemory and the endianness of Kernel and Supervisor mode
 584    execution. The value is 0 for little-endian; 1 for big-endian. */
 585 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 586 /*(state & simBE) ? 1 : 0)*/
 587
 588 /* ReverseEndian */
 589 /* This mode is selected if in User mode with the RE bit being set in
 590    SR (Status Register). It reverses the endianness of load and store
 591    instructions. */
 592 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 593
 594 /* BigEndianCPU */
 595 /* The endianness for load and store instructions (0=little;1=big). In
 596    User mode this endianness may be switched by setting the state_RE
 597    bit in the SR register. Thus, BigEndianCPU may be computed as
 598    (BigEndianMem EOR ReverseEndian). */
 599 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 600
 601
 602
 603 /* Exceptions: */
 604
 605 /* NOTE: These numbers depend on the processor architecture being
 606    simulated: */
 607 #define Interrupt               (0)
 608 #define TLBModification         (1)
 609 #define TLBLoad                 (2)
 610 #define TLBStore                (3)
 611 #define AddressLoad             (4)
 612 #define AddressStore            (5)
 613 #define InstructionFetch        (6)
 614 #define DataReference           (7)
 615 #define SystemCall              (8)
 616 #define BreakPoint              (9)
 617 #define ReservedInstruction     (10)
 618 #define CoProcessorUnusable     (11)
 619 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 620 #define Trap                    (13)
 621 #define FPE                     (15)
 622 #define DebugBreakPoint         (16)
 623 #define Watch                   (23)
 624
 625 /* The following exception code is actually private to the simulator
 626    world. It is *NOT* a processor feature, and is used to signal
 627    run-time errors in the simulator. */
 628 #define SimulatorFault      (0xFFFFFFFF)
 629
 630 void signal_exception (SIM_DESC sd, address_word cia, int exception, ...);
 631 #define SignalException(exc,instruction)     signal_exception (sd, cia, (exc), (instruction))
 632 #define SignalExceptionInterrupt()           signal_exception (sd, NULL_CIA, Interrupt)
 633 #define SignalExceptionInstructionFetch()    signal_exception (sd, cia, InstructionFetch)
 634 #define SignalExceptionAddressStore()        signal_exception (sd, cia, AddressStore)
 635 #define SignalExceptionAddressLoad()         signal_exception (sd, cia, AddressLoad)
 636 #define SignalExceptionSimulatorFault(buf)   signal_exception (sd, cia, SimulatorFault, buf)
 637 #define SignalExceptionFPE()                 signal_exception (sd, cia, FPE)
 638 #define SignalExceptionIntegerOverflow()     signal_exception (sd, cia, IntegerOverflow)
 639 #define SignalExceptionCoProcessorUnusable() signal_exception (sd, cia, CoProcessorUnusable)
 640
 641
 642 /* Co-processor accesses */
 643
 644 void cop_lw  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 645 void cop_ld  PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 646 unsigned int cop_sw PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 647 uword64 cop_sd PARAMS ((SIM_DESC sd, address_word cia, int coproc_num, int coproc_reg));
 648
 649 #define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,cia,coproc_num,coproc_reg,memword)
 650 #define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,cia,coproc_num,coproc_reg,memword)
 651 #define COP_SW(coproc_num,coproc_reg) cop_sw(sd,cia,coproc_num,coproc_reg)
 652 #define COP_SD(coproc_num,coproc_reg) cop_sd(sd,cia,coproc_num,coproc_reg)
 653
 654 void decode_coproc PARAMS ((SIM_DESC sd, address_word cia, unsigned int instruction));
 655 #define DecodeCoproc(instruction) decode_coproc(sd, cia, (instruction))
 656
 657
 658
 659 /* Memory accesses */
 660
 661 /* The following are generic to all versions of the MIPS architecture
 662    to date: */
 663
 664 /* Memory Access Types (for CCA): */
 665 #define Uncached                (0)
 666 #define CachedNoncoherent       (1)
 667 #define CachedCoherent          (2)
 668 #define Cached                  (3)
 669
 670 #define isINSTRUCTION   (1 == 0) /* FALSE */
 671 #define isDATA          (1 == 1) /* TRUE */
 672 #define isLOAD          (1 == 0) /* FALSE */
 673 #define isSTORE         (1 == 1) /* TRUE */
 674 #define isREAL          (1 == 0) /* FALSE */
 675 #define isRAW           (1 == 1) /* TRUE */
 676 /* The parameter HOST (isTARGET / isHOST) is ignored */
 677 #define isTARGET        (1 == 0) /* FALSE */
 678 /* #define isHOST          (1 == 1) TRUE */
 679
 680 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 681    is the number of bytes minus 1. */
 682 #define AccessLength_BYTE       (0)
 683 #define AccessLength_HALFWORD   (1)
 684 #define AccessLength_TRIPLEBYTE (2)
 685 #define AccessLength_WORD       (3)
 686 #define AccessLength_QUINTIBYTE (4)
 687 #define AccessLength_SEXTIBYTE  (5)
 688 #define AccessLength_SEPTIBYTE  (6)
 689 #define AccessLength_DOUBLEWORD (7)
 690 #define AccessLength_QUADWORD   (15)
 691
 692 int address_translation PARAMS ((SIM_DESC sd, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 693 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 694 address_translation(sd,cia,vAddr,IorD,LorS,pAddr,CCA,raw)
 695
 696 void load_memory PARAMS ((SIM_DESC sd, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 697 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 698 load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
 699
 700 void store_memory PARAMS ((SIM_DESC sd, address_word cia, int CCA, int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 701 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 702 store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
 703
 704 void cache_op PARAMS ((SIM_DESC sd, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 705 #define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,cia,op,pAddr,vAddr,instruction)
 706
 707 void sync_operation PARAMS ((SIM_DESC sd, address_word cia, int stype));
 708 #define SyncOperation(stype) sync_operation (sd, cia, (stype))
 709
 710 void prefetch PARAMS ((SIM_DESC sd, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 711 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,cia,CCA,pAddr,vAddr,DATA,hint)
 712
 713 unsigned32 ifetch32 PARAMS ((SIM_DESC sd, address_word cia, address_word vaddr));
 714 #define IMEM(CIA) ifetch32 (SD, (CIA), (CIA))
 715
 716 void dotrace PARAMS ((SIM_DESC sd, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 717 FILE *tracefh;
 718
 719 #endif