1 /* MIPS Simulator definition.
2 Copyright (C) 1997 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* This simulator doesn't cache the Current Instruction Address */
25 #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA)
26 #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA)
28 #define SIM_HAVE_BIENDIAN
29 #define SIM_HAVE_FLATMEM
32 /* hobble some common features for moment */
34 #define WITH_WATCHPOINTS 1
36 #include "sim-basics.h"
38 typedef address_word sim_cia
;
43 /* Depreciated macros and types for manipulating 64bit values. Use
44 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
46 typedef signed64 word64
;
47 typedef unsigned64 uword64
;
49 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
50 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
51 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
52 #define SET64HI(t) (((uword64)(t))<<32)
53 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
54 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
56 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
57 assume the HI32bits of the operand are zero, so we must perform a
58 mask to ensure we can use the simple subtraction to sign-extend. */
59 #define SIGNEXTEND(e,b) \
61 (((e) & ((uword64) 1 << ((b) - 1))) \
62 ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
63 : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
65 /* Check if a value will fit within a halfword: */
66 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
68 /* windows always looses */
71 #define SIGBUS SIGSEGV
80 /* Floating-point operations: */
82 /* FPU registers must be one of the following types. All other values
83 are reserved (and undefined). */
89 /* The following are well outside the normal acceptable format
90 range, and are used in the register status vector. */
91 fmt_unknown
= 0x10000000,
92 fmt_uninterpreted
= 0x20000000,
95 unsigned64 value_fpr
PARAMS ((SIM_DESC sd
, int fpr
, FP_formats
));
96 #define ValueFPR(FPR,FMT) value_fpr (sd, (FPR), (FMT))
98 void store_fpr
PARAMS ((SIM_DESC sd
, int fpr
, FP_formats fmt
, unsigned64 value
));
99 #define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, (FPR), (FMT), (VALUE))
101 int NaN
PARAMS ((unsigned64 op
, FP_formats fmt
));
102 int Infinity
PARAMS ((unsigned64 op
, FP_formats fmt
));
103 int Less
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
104 int Equal
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
105 unsigned64 AbsoluteValue
PARAMS ((unsigned64 op
, FP_formats fmt
));
106 unsigned64 Negate
PARAMS ((unsigned64 op
, FP_formats fmt
));
107 unsigned64 Add
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
108 unsigned64 Sub
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
109 unsigned64 Multiply
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
110 unsigned64 Divide
PARAMS ((unsigned64 op1
, unsigned64 op2
, FP_formats fmt
));
111 unsigned64 Recip
PARAMS ((unsigned64 op
, FP_formats fmt
));
112 unsigned64 SquareRoot
PARAMS ((unsigned64 op
, FP_formats fmt
));
113 unsigned64 convert
PARAMS ((SIM_DESC sd
, int rm
, unsigned64 op
, FP_formats from
, FP_formats to
));
114 #define Convert(rm,op,from,to) convert(sd,rm,op,from,to)
116 /* Macro to update FPSR condition-code field. This is complicated by
117 the fact that there is a hole in the index range of the bits within
118 the FCSR register. Also, the number of bits visible depends on the
119 MIPS ISA version being supported. */
121 #define SETFCC(cc,v) {\
122 int bit = ((cc == 0) ? 23 : (24 + (cc)));\
123 FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
125 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
127 /* This should be the COC1 value at the start of the preceding
129 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
132 #define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
134 /* They depend on the CPU being simulated */
135 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
138 /* Standard FCRS bits: */
139 #define IR (0) /* Inexact Result */
140 #define UF (1) /* UnderFlow */
141 #define OF (2) /* OverFlow */
142 #define DZ (3) /* Division by Zero */
143 #define IO (4) /* Invalid Operation */
144 #define UO (5) /* Unimplemented Operation */
146 /* Get masks for individual flags: */
147 #if 1 /* SAFE version */
148 #define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
149 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
150 #define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
152 #define FP_FLAGS(b) (1 << ((b) + 2))
153 #define FP_ENABLE(b) (1 << ((b) + 7))
154 #define FP_CAUSE(b) (1 << ((b) + 12))
157 #define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
159 #define FP_MASK_RM (0x3)
161 #define FP_RM_NEAREST (0) /* Round to nearest (Round) */
162 #define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
163 #define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
164 #define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
165 #define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
169 /* Integer ALU operations: */
173 #define ALU32_END(ANS) \
174 if (ALU32_HAD_OVERFLOW) \
175 SignalExceptionIntegerOverflow (); \
176 (ANS) = ALU32_OVERFLOW_RESULT
179 #define ALU64_END(ANS) \
180 if (ALU64_HAD_OVERFLOW) \
181 SignalExceptionIntegerOverflow (); \
182 (ANS) = ALU64_OVERFLOW_RESULT;
184 /* start-sanitize-r5900 */
186 #define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word))
187 #define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2)
188 #define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4)
189 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
191 #define BYTES_IN_MIPS_REGS (sizeof(signed_word))
192 #define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2)
193 #define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4)
194 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
196 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
197 T - type of the sub part
198 TC - # of T's in the mips part of the "register"
199 I - index (from 0) of desired sub part
200 A - low part of "register"
201 A1 - high part of register
203 #define SUB_REG_FETCH(T,TC,A,A1,I) \
204 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
205 + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
206 ? ((TC) - 1 - (I) % (TC)) \
213 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
214 where <type> has two letters:
215 1 is S=signed or U=unsigned
216 2 is B=byte H=halfword W=word D=doubleword
219 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
220 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
221 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
222 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
224 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
225 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
226 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
227 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
229 #define GPR_SB(R,I) SUB_REG_SB(®ISTERS[R], ®ISTERS1[R], I)
230 #define GPR_SH(R,I) SUB_REG_SH(®ISTERS[R], ®ISTERS1[R], I)
231 #define GPR_SW(R,I) SUB_REG_SW(®ISTERS[R], ®ISTERS1[R], I)
232 #define GPR_SD(R,I) SUB_REG_SD(®ISTERS[R], ®ISTERS1[R], I)
234 #define GPR_UB(R,I) SUB_REG_UB(®ISTERS[R], ®ISTERS1[R], I)
235 #define GPR_UH(R,I) SUB_REG_UH(®ISTERS[R], ®ISTERS1[R], I)
236 #define GPR_UW(R,I) SUB_REG_UW(®ISTERS[R], ®ISTERS1[R], I)
237 #define GPR_UD(R,I) SUB_REG_UD(®ISTERS[R], ®ISTERS1[R], I)
240 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
241 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
242 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
243 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
245 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
246 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
247 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
248 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
250 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
251 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
252 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
253 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
255 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
256 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
257 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
258 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
262 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
263 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
264 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
265 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
267 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
268 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
269 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
270 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
272 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
273 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
274 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
275 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
277 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
278 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
279 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
280 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
282 /* end-sanitize-r5900 */
290 /* The following are internal simulator state variables: */
292 #define CPU_CIA(CPU) (PC)
293 address_word ipc
; /* internal Instruction PC */
294 address_word dspc
; /* delay-slot PC */
295 #define IPC ((STATE_CPU (sd,0))->ipc)
296 #define DSPC ((STATE_CPU (sd,0))->dspc)
298 /* Issue a delay slot instruction immediatly by re-calling
300 #define DELAY_SLOT(TARGET) \
302 address_word target = (TARGET); \
303 instruction_word delay_insn; \
304 sim_events_slip (sd, 1); \
306 STATE |= simDELAYSLOT; \
307 delay_insn = IMEM (PC); \
308 idecode_issue (sd, delay_insn, (PC)); \
309 STATE &= !simDELAYSLOT; \
312 #define NULLIFY_NEXT_INSTRUCTION() \
314 sim_events_slip (sd, 1); \
320 /* State of the simulator */
322 unsigned int dsstate
;
323 #define STATE ((STATE_CPU (sd,0))->state)
324 #define DSSTATE ((STATE_CPU (sd,0))->dsstate)
326 /* Flags in the "state" variable: */
327 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
328 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
329 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
330 #define simPCOC0 (1 << 17) /* COC[1] from current */
331 #define simPCOC1 (1 << 18) /* COC[1] from previous */
332 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
333 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
334 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
335 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
340 /* This is nasty, since we have to rely on matching the register
341 numbers used by GDB. Unfortunately, depending on the MIPS target
342 GDB uses different register numbers. We cannot just include the
343 relevant "gdb/tm.h" link, since GDB may not be configured before
344 the sim world, and also the GDB header file requires too much other
348 #define LAST_EMBED_REGNUM (89)
349 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
350 /* start-sanitize-r5900 */
352 #define NUM_REGS (128)
353 /* end-sanitize-r5900 */
356 /* To keep this default simulator simple, and fast, we use a direct
357 vector of registers. The internal simulator engine then uses
358 manifests to access the correct slot. */
360 unsigned_word registers
[LAST_EMBED_REGNUM
+ 1];
361 int register_widths
[NUM_REGS
];
362 #define REGISTERS ((STATE_CPU (sd,0))->registers)
364 #define GPR (®ISTERS[0])
366 #define FGR (®ISTERS[FGRIDX])
367 #define LO (REGISTERS[33])
368 #define HI (REGISTERS[34])
369 #define PC (REGISTERS[37])
370 #define CAUSE (REGISTERS[36])
372 #define SR (REGISTERS[SRIDX]) /* CPU status register */
374 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
375 #define FCR31IDX (70)
376 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
378 #define Debug (REGISTERS[86])
379 #define DEPC (REGISTERS[87])
380 #define EPC (REGISTERS[88])
381 #define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
383 /* The following are pseudonyms for standard registers */
384 #define ZERO (REGISTERS[0])
385 #define V0 (REGISTERS[2])
386 #define A0 (REGISTERS[4])
387 #define A1 (REGISTERS[5])
388 #define A2 (REGISTERS[6])
389 #define A3 (REGISTERS[7])
390 #define SP (REGISTERS[29])
391 #define RA (REGISTERS[31])
393 /* Keep the current format state for each register: */
394 FP_formats fpr_state
[32];
395 #define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
398 /* Slots for delayed register updates. For the moment we just have a
399 fixed number of slots (rather than a more generic, dynamic
400 system). This keeps the simulator fast. However, we only allow
401 for the register update to be delayed for a single instruction
403 #define PSLOTS (5) /* Maximum number of instruction cycles */
407 int pending_slot_count
[PSLOTS
];
408 int pending_slot_reg
[PSLOTS
];
409 unsigned_word pending_slot_value
[PSLOTS
];
410 #define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
411 #define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
412 #define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
413 #define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
414 #define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
415 #define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
417 /* The following are not used for MIPS IV onwards: */
418 #define PENDING_FILL(r,v) {\
419 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
420 if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
421 sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
422 PENDING_SLOT_COUNT[PENDING_IN] = 2;\
423 PENDING_SLOT_REG[PENDING_IN] = (r);\
424 PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
425 /*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\
428 if (PENDING_IN == PSLOTS)\
430 /*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
434 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
435 read-write instructions. It is set when a linked load occurs. It
436 is tested and cleared by the conditional store. It is cleared
437 (during other CPU operations) when a store to the location would
438 no longer be atomic. In particular, it is cleared by exception
439 return instructions. */
441 #define LLBIT ((STATE_CPU (sd, 0))->llbit)
444 /* The HIACCESS and LOACCESS counts are used to ensure that
445 corruptions caused by using the HI or LO register to close to a
446 following operation are spotted. */
450 #define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
451 #define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
452 /* start-sanitize-r5900 */
455 #define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
456 #define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
457 /* end-sanitize-r5900 */
459 /* The 4300 and a few other processors have interlocks on hi/lo
460 register reads, and hence do not have this problem. To avoid
461 spurious warnings, we just disable this always. */
465 /* If either of the preceding two instructions have accessed the HI
466 or LO registers, then the values they see should be
467 undefined. However, to keep the simulator world simple, we just
468 let them use the value read and raise a warning to notify the
470 #define CHECKHILO(s) {\
471 if ((HIACCESS != 0) || (LOACCESS != 0)) \
472 sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
474 /* start-sanitize-r5900 */
476 #define CHECKHILO(s) {\
477 if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
478 sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
480 /* end-sanitize-r5900 */
484 /* start-sanitize-r5900 */
485 /* The R5900 has 128 bit registers, but the hi 64 bits are only
486 touched by multimedia (MMI) instructions. The normal mips
487 instructions just use the lower 64 bits. To avoid changing the
488 older parts of the simulator to handle this weirdness, the high
489 64 bits of each register are kept in a separate array
490 (registers1). The high 64 bits of any register are by convention
491 refered by adding a '1' to the end of the normal register's name.
492 So LO still refers to the low 64 bits of the LO register, LO1
493 refers to the high 64 bits of that same register. */
495 signed_word registers1
[LAST_EMBED_REGNUM
+ 1];
496 #define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
497 #define GPR1 (®ISTERS1[0])
498 #define LO1 (REGISTERS1[32])
499 #define HI1 (REGISTERS1[33])
500 #define REGISTER_SA (124)
502 unsigned_word sa
; /* the shift amount register */
503 #define SA ((STATE_CPU (sd, 0))->sa)
505 /* end-sanitize-r5900 */
506 /* start-sanitize-vr5400 */
508 /* end-sanitize-vr5400 */
516 /* MIPS specific simulator watch config */
518 void watch_options_install
PARAMS ((SIM_DESC sd
));
527 /* FIXME: At present much of the simulator is still static */
534 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
536 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
544 /* Status information: */
546 /* TODO : these should be the bitmasks for these bits within the
547 status register. At the moment the following are VR4300
549 #define status_KSU_mask (0x3) /* mask for KSU bits */
550 #define status_KSU_shift (3) /* shift for field */
551 #define ksu_kernel (0x0)
552 #define ksu_supervisor (0x1)
553 #define ksu_user (0x2)
554 #define ksu_unknown (0x3)
556 #define status_IE (1 << 0) /* Interrupt enable */
557 #define status_EXL (1 << 1) /* Exception level */
558 #define status_RE (1 << 25) /* Reverse Endian in user mode */
559 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
560 #define status_SR (1 << 20) /* soft reset or NMI */
561 #define status_BEV (1 << 22) /* Location of general exception vectors */
562 #define status_TS (1 << 21) /* TLB shutdown has occurred */
563 #define status_ERL (1 << 2) /* Error level */
564 #define status_RP (1 << 27) /* Reduced Power mode */
566 #define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
568 /* NOTE: We keep the following status flags as bit values (1 for true,
569 0 for false). This allows them to be used in binary boolean
570 operations without worrying about what exactly the non-zero true
574 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
577 /* Hardware configuration. Affects endianness of LoadMemory and
578 StoreMemory and the endianness of Kernel and Supervisor mode
579 execution. The value is 0 for little-endian; 1 for big-endian. */
580 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
581 /*(state & simBE) ? 1 : 0)*/
584 /* This is true if the host and target have different endianness. */
585 #define ByteSwapMem (CURRENT_TARGET_BYTE_ORDER != CURRENT_HOST_BYTE_ORDER)
588 /* This mode is selected if in User mode with the RE bit being set in
589 SR (Status Register). It reverses the endianness of load and store
591 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
594 /* The endianness for load and store instructions (0=little;1=big). In
595 User mode this endianness may be switched by setting the state_RE
596 bit in the SR register. Thus, BigEndianCPU may be computed as
597 (BigEndianMem EOR ReverseEndian). */
598 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
604 /* NOTE: These numbers depend on the processor architecture being
606 #define Interrupt (0)
607 #define TLBModification (1)
610 #define AddressLoad (4)
611 #define AddressStore (5)
612 #define InstructionFetch (6)
613 #define DataReference (7)
614 #define SystemCall (8)
615 #define BreakPoint (9)
616 #define ReservedInstruction (10)
617 #define CoProcessorUnusable (11)
618 #define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
621 #define DebugBreakPoint (16)
624 /* The following exception code is actually private to the simulator
625 world. It is *NOT* a processor feature, and is used to signal
626 run-time errors in the simulator. */
627 #define SimulatorFault (0xFFFFFFFF)
629 void signal_exception (SIM_DESC sd
, int exception
, ...);
630 #define SignalException(exc,instruction) signal_exception (sd, (exc), (instruction))
631 #define SignalExceptionInterrupt() signal_exception (sd, Interrupt)
632 #define SignalExceptionInstructionFetch() signal_exception (sd, InstructionFetch)
633 #define SignalExceptionAddressStore() signal_exception (sd, AddressStore)
634 #define SignalExceptionAddressLoad() signal_exception (sd, AddressLoad)
635 #define SignalExceptionSimulatorFault(buf) signal_exception (sd, SimulatorFault, buf)
636 #define SignalExceptionFPE() signal_exception (sd, FPE)
637 #define SignalExceptionIntegerOverflow() signal_exception (sd, IntegerOverflow)
638 #define SignalExceptionCoProcessorUnusable() signal_exception (sd, CoProcessorUnusable)
641 /* Co-processor accesses */
643 void cop_lw
PARAMS ((SIM_DESC sd
, int coproc_num
, int coproc_reg
, unsigned int memword
));
644 void cop_ld
PARAMS ((SIM_DESC sd
, int coproc_num
, int coproc_reg
, uword64 memword
));
645 unsigned int cop_sw
PARAMS ((SIM_DESC sd
, int coproc_num
, int coproc_reg
));
646 uword64 cop_sd
PARAMS ((SIM_DESC sd
, int coproc_num
, int coproc_reg
));
648 #define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,coproc_num,coproc_reg,memword)
649 #define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,coproc_num,coproc_reg,memword)
650 #define COP_SW(coproc_num,coproc_reg) cop_sw(sd,coproc_num,coproc_reg)
651 #define COP_SD(coproc_num,coproc_reg) cop_sd(sd,coproc_num,coproc_reg)
653 void decode_coproc
PARAMS ((SIM_DESC sd
,unsigned int instruction
));
654 #define DecodeCoproc(instruction) decode_coproc(sd, (instruction))
658 /* Memory accesses */
660 /* The following are generic to all versions of the MIPS architecture
663 /* Memory Access Types (for CCA): */
665 #define CachedNoncoherent (1)
666 #define CachedCoherent (2)
669 #define isINSTRUCTION (1 == 0) /* FALSE */
670 #define isDATA (1 == 1) /* TRUE */
671 #define isLOAD (1 == 0) /* FALSE */
672 #define isSTORE (1 == 1) /* TRUE */
673 #define isREAL (1 == 0) /* FALSE */
674 #define isRAW (1 == 1) /* TRUE */
675 #define isTARGET (1 == 0) /* FALSE */
676 #define isHOST (1 == 1) /* TRUE */
678 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
679 is the number of bytes minus 1. */
680 #define AccessLength_BYTE (0)
681 #define AccessLength_HALFWORD (1)
682 #define AccessLength_TRIPLEBYTE (2)
683 #define AccessLength_WORD (3)
684 #define AccessLength_QUINTIBYTE (4)
685 #define AccessLength_SEXTIBYTE (5)
686 #define AccessLength_SEPTIBYTE (6)
687 #define AccessLength_DOUBLEWORD (7)
688 #define AccessLength_QUADWORD (15)
690 int address_translation
PARAMS ((SIM_DESC sd
, address_word vAddr
, int IorD
, int LorS
, address_word
*pAddr
, int *CCA
, int host
, int raw
));
691 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
692 address_translation(sd, vAddr,IorD,LorS,pAddr,CCA,host,raw)
694 void load_memory
PARAMS ((SIM_DESC sd
, uword64
* memvalp
, uword64
* memval1p
, int CCA
, int AccessLength
, address_word pAddr
, address_word vAddr
, int IorD
, int raw
));
695 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
696 load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw)
698 void store_memory
PARAMS ((SIM_DESC sd
, int CCA
, int AccessLength
, uword64 MemElem
, uword64 MemElem1
, address_word pAddr
, address_word vAddr
, int raw
));
699 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
700 store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
702 void cache_op
PARAMS ((SIM_DESC sd
, int op
, address_word pAddr
, address_word vAddr
, unsigned int instruction
));
703 #define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,op,pAddr,vAddr,instruction)
705 void sync_operation
PARAMS ((SIM_DESC sd
, int stype
));
706 #define SyncOperation(stype) sync_operation (sd, (stype))
708 void prefetch
PARAMS ((SIM_DESC sd
, int CCA
, address_word pAddr
, address_word vAddr
, int DATA
, int hint
));
709 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,CCA,pAddr,vAddr,DATA,hint)
711 unsigned32 ifetch32
PARAMS ((SIM_DESC sd
, address_word cia
));
712 #define IMEM(CIA) ifetch32 (SD, (CIA))