sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA)
  26 #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA)
  27
  28 #define SIM_HAVE_BIENDIAN
  29 #define SIM_HAVE_FLATMEM
  30
  31
  32 /* hobble some common features for moment */
  33 #define WITH_PROFILE 0
  34 #define WITH_TRACE 0
  35 #define WITH_WATCHPOINTS 1
  36
  37 #include "sim-basics.h"
  38
  39
  40 #if 0
  41 /* These are generated files.  */
  42 #include "itable.h"
  43 #include "idecode.h"
  44 #include "idecode.h"
  45
  46 /* dummy - not used */
  47 typedef instruction_address sim_cia;
  48 static const sim_cia null_cia = {0}; /* dummy */
  49 #define NULL_CIA null_cia
  50 #else
  51 typedef int sim_cia;
  52 #endif
  53
  54
  55 #include "sim-base.h"
  56
  57
  58 /* Depreciated macros and types for manipulating 64bit values.  Use
  59    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  60
  61 typedef signed64 word64;
  62 typedef unsigned64 uword64;
  63
  64 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  65 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  66 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  67 #define SET64HI(t)      (((uword64)(t))<<32)
  68 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  69 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  70
  71 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  72    assume the HI32bits of the operand are zero, so we must perform a
  73    mask to ensure we can use the simple subtraction to sign-extend. */
  74 #define SIGNEXTEND(e,b) \
  75   (((e) & ((uword64) 1 << ((b) - 1))) \
  76    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  77    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1)))
  78
  79 /* Check if a value will fit within a halfword: */
  80 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  81
  82 /* windows always looses */
  83 #include <signal.h>
  84 #ifndef SIGBUS
  85 #define SIGBUS SIGSEGV
  86 #endif
  87 #ifdef _WIN32
  88 #define SIGTRAP 5
  89 #define SIGQUIT 3
  90 #endif
  91
  92
  93
  94 /* Floating-point operations: */
  95
  96 /* FPU registers must be one of the following types. All other values
  97    are reserved (and undefined). */
  98 typedef enum {
  99  fmt_single  = 0,
 100  fmt_double  = 1,
 101  fmt_word    = 4,
 102  fmt_long    = 5,
 103  /* The following are well outside the normal acceptable format
 104     range, and are used in the register status vector. */
 105  fmt_unknown       = 0x10000000,
 106  fmt_uninterpreted = 0x20000000,
 107 } FP_formats;
 108
 109 unsigned64 value_fpr PARAMS ((SIM_DESC sd, int fpr, FP_formats));
 110 #define ValueFPR(FPR,FMT) value_fpr (sd, (FPR), (FMT))
 111
 112 void store_fpr PARAMS ((SIM_DESC sd, int fpr, FP_formats fmt, unsigned64 value));
 113 #define StoreFPR(FPR,FMT,VALUE) store_fpr (sd, (FPR), (FMT), (VALUE))
 114
 115 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 116 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 117 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 118 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 119 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 120 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 121 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 122 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 123 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 124 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 125 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 126 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 127 unsigned64 convert PARAMS ((SIM_DESC sd, int rm, unsigned64 op, FP_formats from, FP_formats to));
 128 #define Convert(rm,op,from,to) convert(sd,rm,op,from,to)
 129
 130 /* Macro to update FPSR condition-code field. This is complicated by
 131    the fact that there is a hole in the index range of the bits within
 132    the FCSR register. Also, the number of bits visible depends on the
 133    MIPS ISA version being supported. */
 134
 135 #define SETFCC(cc,v) {\
 136   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 137   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 138 }
 139 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
 140
 141 /* This should be the COC1 value at the start of the preceding
 142    instruction: */
 143 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 144
 145 #if 1
 146 #define SizeFGR() (WITH_TARGET_WORD_BITSIZE)
 147 #else
 148 /* They depend on the CPU being simulated */
 149 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 150 #endif
 151
 152 /* Standard FCRS bits: */
 153 #define IR (0) /* Inexact Result */
 154 #define UF (1) /* UnderFlow */
 155 #define OF (2) /* OverFlow */
 156 #define DZ (3) /* Division by Zero */
 157 #define IO (4) /* Invalid Operation */
 158 #define UO (5) /* Unimplemented Operation */
 159
 160 /* Get masks for individual flags: */
 161 #if 1 /* SAFE version */
 162 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 163 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 164 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 165 #else
 166 #define FP_FLAGS(b)  (1 << ((b) + 2))
 167 #define FP_ENABLE(b) (1 << ((b) + 7))
 168 #define FP_CAUSE(b)  (1 << ((b) + 12))
 169 #endif
 170
 171 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 172
 173 #define FP_MASK_RM    (0x3)
 174 #define FP_SH_RM      (0)
 175 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 176 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 177 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 178 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 179 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 180
 181
 182
 183 /* Integer ALU operations: */
 184
 185 #include "sim-alu.h"
 186
 187 #define ALU32_END(ANS) \
 188   if (ALU32_HAD_OVERFLOW) \
 189     SignalExceptionIntegerOverflow (); \
 190   (ANS) = alu_overflow_val;
 191
 192
 193 #define ALU64_END(ANS) \
 194   if (ALU64_HAD_OVERFLOW) \
 195     SignalExceptionIntegerOverflow (); \
 196   (ANS) = alu_val;
 197
 198 /* start-sanitize-r5900 */
 199
 200 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 201 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 202 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 203 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 204
 205 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 206 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 207 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 208 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 209
 210 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 211    T  - type of the sub part
 212    TC - # of T's in the mips part of the "register"
 213    I  - index (from 0) of desired sub part
 214    A  - low part of "register"
 215    A1 - high part of register
 216 */
 217 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 218 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 219    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 220       ? ((TC) - 1 - (I) % (TC)) \
 221       : ((I) % (TC)) \
 222       ) \
 223    ) \
 224  )
 225
 226 /*
 227 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 228             where <type> has two letters:
 229                   1 is S=signed or U=unsigned
 230                   2 is B=byte H=halfword W=word D=doubleword
 231 */
 232
 233 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 234 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 235 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 236 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 237
 238 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 239 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 240 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 241 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 242
 243 #define GPR_SB(R,I) SUB_REG_SB(&REGISTERS[R], &REGISTERS1[R], I)
 244 #define GPR_SH(R,I) SUB_REG_SH(&REGISTERS[R], &REGISTERS1[R], I)
 245 #define GPR_SW(R,I) SUB_REG_SW(&REGISTERS[R], &REGISTERS1[R], I)
 246 #define GPR_SD(R,I) SUB_REG_SD(&REGISTERS[R], &REGISTERS1[R], I)
 247
 248 #define GPR_UB(R,I) SUB_REG_UB(&REGISTERS[R], &REGISTERS1[R], I)
 249 #define GPR_UH(R,I) SUB_REG_UH(&REGISTERS[R], &REGISTERS1[R], I)
 250 #define GPR_UW(R,I) SUB_REG_UW(&REGISTERS[R], &REGISTERS1[R], I)
 251 #define GPR_UD(R,I) SUB_REG_UD(&REGISTERS[R], &REGISTERS1[R], I)
 252
 253
 254 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 255 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 256 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 257 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 258
 259 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 260 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 261 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 262 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 263
 264 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 265 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 266 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 267 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 268
 269 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 270 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 271 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 272 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 273
 274
 275
 276 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 277 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 278 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 279 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 280
 281 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 282 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 283 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 284 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 285
 286 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 287 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 288 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 289 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 290
 291 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 292 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 293 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 294 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 295
 296 /* end-sanitize-r5900 */
 297
 298
 299
 300
 301 struct _sim_cpu {
 302
 303
 304   /* The following are internal simulator state variables: */
 305   sim_cia cia;
 306 #define CPU_CIA(CPU) ((CPU)->cia)
 307   address_word ipc; /* internal Instruction PC */
 308   address_word dspc;  /* delay-slot PC */
 309 #define IPC ((STATE_CPU (sd,0))->ipc)
 310 #define DSPC ((STATE_CPU (sd,0))->dspc)
 311
 312 #define NULLIFY_NIA() { nia.ip = cia.dp + 4; nia.dp = nia.ip += 4; }
 313
 314
 315
 316   /* State of the simulator */
 317   unsigned int state;
 318   unsigned int dsstate;
 319 #define STATE ((STATE_CPU (sd,0))->state)
 320 #define DSSTATE ((STATE_CPU (sd,0))->dsstate)
 321
 322 /* Flags in the "state" variable: */
 323 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 324 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 325 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 326 #define simPROFILE      (1 << 9)  /* 0 = do nothing; 1 = gather profiling samples */
 327 #define simPCOC0        (1 << 17) /* COC[1] from current */
 328 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 329 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 330 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 331 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 332 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 333
 334
 335
 336
 337 /* This is nasty, since we have to rely on matching the register
 338    numbers used by GDB. Unfortunately, depending on the MIPS target
 339    GDB uses different register numbers. We cannot just include the
 340    relevant "gdb/tm.h" link, since GDB may not be configured before
 341    the sim world, and also the GDB header file requires too much other
 342    state. */
 343
 344 #ifndef TM_MIPS_H
 345 #define LAST_EMBED_REGNUM (89)
 346 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 347 /* start-sanitize-r5900 */
 348 #undef NUM_REGS
 349 #define NUM_REGS (128)
 350 /* end-sanitize-r5900 */
 351 #endif
 352
 353 /* To keep this default simulator simple, and fast, we use a direct
 354    vector of registers. The internal simulator engine then uses
 355    manifests to access the correct slot. */
 356
 357   signed_word registers[LAST_EMBED_REGNUM + 1];
 358   int register_widths[NUM_REGS];
 359 #define REGISTERS       ((STATE_CPU (sd,0))->registers)
 360
 361 #define GPR     (&REGISTERS[0])
 362 #define FGRIDX  (38)
 363 #define FGR     (&REGISTERS[FGRIDX])
 364 #define LO      (REGISTERS[33])
 365 #define HI      (REGISTERS[34])
 366 #define PC      (REGISTERS[37])
 367 #define CAUSE   (REGISTERS[36])
 368 #define SRIDX   (32)
 369 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 370 #define FCR0IDX  (71)
 371 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 372 #define FCR31IDX (70)
 373 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 374 #define FCSR    (FCR31)
 375 #define Debug   (REGISTERS[86])
 376 #define DEPC    (REGISTERS[87])
 377 #define EPC     (REGISTERS[88])
 378 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 379
 380 /* The following are pseudonyms for standard registers */
 381 #define ZERO    (REGISTERS[0])
 382 #define V0      (REGISTERS[2])
 383 #define A0      (REGISTERS[4])
 384 #define A1      (REGISTERS[5])
 385 #define A2      (REGISTERS[6])
 386 #define A3      (REGISTERS[7])
 387 #define SP      (REGISTERS[29])
 388 #define RA      (REGISTERS[31])
 389
 390   /* Keep the current format state for each register: */
 391   FP_formats fpr_state[32];
 392 #define FPR_STATE ((STATE_CPU (sd, 0))->fpr_state)
 393
 394
 395   /* Slots for delayed register updates. For the moment we just have a
 396      fixed number of slots (rather than a more generic, dynamic
 397      system). This keeps the simulator fast. However, we only allow
 398      for the register update to be delayed for a single instruction
 399      cycle. */
 400 #define PSLOTS (5) /* Maximum number of instruction cycles */
 401   int pending_in;
 402   int pending_out;
 403   int pending_total;
 404   int pending_slot_count[PSLOTS];
 405   int pending_slot_reg[PSLOTS];
 406   unsigned_word pending_slot_value[PSLOTS];
 407 #define PENDING_IN ((STATE_CPU (sd, 0))->pending_in)
 408 #define PENDING_OUT ((STATE_CPU (sd, 0))->pending_out)
 409 #define PENDING_TOTAL ((STATE_CPU (sd, 0))->pending_total)
 410 #define PENDING_SLOT_COUNT ((STATE_CPU (sd, 0))->pending_slot_count)
 411 #define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg)
 412 #define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value)
 413
 414   /* The following are not used for MIPS IV onwards: */
 415 #define PENDING_FILL(r,v) {\
 416 /* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\
 417                             if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\
 418                              sim_io_eprintf(sd,"Attempt to over-write pending value\n");\
 419                             PENDING_SLOT_COUNT[PENDING_IN] = 2;\
 420                             PENDING_SLOT_REG[PENDING_IN] = (r);\
 421                             PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\
 422 /*printf("DBG: FILL        reg %d value = 0x%s\n",(r),pr_addr(v));*/\
 423                             PENDING_TOTAL++;\
 424                             PENDING_IN++;\
 425                             if (PENDING_IN == PSLOTS)\
 426                              PENDING_IN = 0;\
 427 /*printf("DBG: FILL AFTER  pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\
 428                           }
 429
 430
 431   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 432      read-write instructions. It is set when a linked load occurs. It
 433      is tested and cleared by the conditional store. It is cleared
 434      (during other CPU operations) when a store to the location would
 435      no longer be atomic. In particular, it is cleared by exception
 436      return instructions. */
 437   int llbit;
 438 #define LLBIT ((STATE_CPU (sd, 0))->llbit)
 439
 440
 441 /* The HIACCESS and LOACCESS counts are used to ensure that
 442    corruptions caused by using the HI or LO register to close to a
 443    following operation are spotted. */
 444
 445   int hiaccess;
 446   int loaccess;
 447 #define HIACCESS ((STATE_CPU (sd, 0))->hiaccess)
 448 #define LOACCESS ((STATE_CPU (sd, 0))->loaccess)
 449   /* start-sanitize-r5900 */
 450   int hi1access;
 451   int lo1access;
 452 #define HI1ACCESS ((STATE_CPU (sd, 0))->hi1access)
 453 #define LO1ACCESS ((STATE_CPU (sd, 0))->lo1access)
 454   /* end-sanitize-r5900 */
 455 #if 1
 456   /* The 4300 and a few other processors have interlocks on hi/lo
 457      register reads, and hence do not have this problem.  To avoid
 458      spurious warnings, we just disable this always.  */
 459 #define CHECKHILO(s)
 460 #else
 461   unsigned_word HLPC;
 462   /* If either of the preceding two instructions have accessed the HI
 463      or LO registers, then the values they see should be
 464      undefined. However, to keep the simulator world simple, we just
 465      let them use the value read and raise a warning to notify the
 466      user: */
 467 #define CHECKHILO(s) {\
 468   if ((HIACCESS != 0) || (LOACCESS != 0)) \
 469     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 470 }
 471   /* end-sanitize-r5900 */
 472 #undef CHECKHILO
 473 #define CHECKHILO(s) {\
 474   if ((HIACCESS != 0) || (LOACCESS != 0) || (HI1ACCESS != 0) || (LO1ACCESS != 0))\
 475     sim_io_eprintf(sd,"%s over-writing HI and LO registers values (PC = 0x%s HLPC = 0x%s)\n",(s),pr_addr(PC),pr_addr(HLPC));\
 476 }
 477   /* end-sanitize-r5900 */
 478 #endif
 479
 480
 481   /* start-sanitize-r5900 */
 482   /* The R5900 has 128 bit registers, but the hi 64 bits are only
 483      touched by multimedia (MMI) instructions.  The normal mips
 484      instructions just use the lower 64 bits.  To avoid changing the
 485      older parts of the simulator to handle this weirdness, the high
 486      64 bits of each register are kept in a separate array
 487      (registers1).  The high 64 bits of any register are by convention
 488      refered by adding a '1' to the end of the normal register's name.
 489      So LO still refers to the low 64 bits of the LO register, LO1
 490      refers to the high 64 bits of that same register.  */
 491
 492   signed_word registers1[LAST_EMBED_REGNUM + 1];
 493 #define REGISTERS1 ((STATE_CPU (sd, 0))->registers1)
 494 #define GPR1     (&REGISTERS1[0])
 495 #define LO1      (REGISTERS1[32])
 496 #define HI1      (REGISTERS1[33])
 497 #define REGISTER_SA     (124)
 498
 499   unsigned_word sa;        /* the shift amount register */
 500 #define SA ((STATE_CPU (sd, 0))->sa)
 501
 502   /* end-sanitize-r5900 */
 503
 504
 505
 506   sim_cpu_base base;
 507 };
 508
 509
 510 /* MIPS specific simulator watch config */
 511
 512 void watch_options_install PARAMS ((SIM_DESC sd));
 513
 514 struct swatch {
 515   sim_event *pc;
 516   sim_event *clock;
 517   sim_event *cycles;
 518 };
 519
 520
 521 /* FIXME: At present much of the simulator is still static */
 522 struct sim_state {
 523
 524   struct swatch watch;
 525
 526   sim_cpu cpu[1];
 527 #if (WITH_SMP)
 528 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 529 #else
 530 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 531 #endif
 532
 533   sim_state_base base;
 534 };
 535
 536
 537
 538 /* Status information: */
 539
 540 /* TODO : these should be the bitmasks for these bits within the
 541    status register. At the moment the following are VR4300
 542    bit-positions: */
 543 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 544 #define status_KSU_shift (3)            /* shift for field */
 545 #define ksu_kernel       (0x0)
 546 #define ksu_supervisor   (0x1)
 547 #define ksu_user         (0x2)
 548 #define ksu_unknown      (0x3)
 549
 550 #define status_IE        (1 <<  0)      /* Interrupt enable */
 551 #define status_EXL       (1 <<  1)      /* Exception level */
 552 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 553 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 554 #define status_SR        (1 << 20)      /* soft reset or NMI */
 555 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 556 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 557 #define status_ERL       (1 <<  2)      /* Error level */
 558 #define status_RP        (1 << 27)      /* Reduced Power mode */
 559
 560 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 561
 562 /* NOTE: We keep the following status flags as bit values (1 for true,
 563    0 for false). This allows them to be used in binary boolean
 564    operations without worrying about what exactly the non-zero true
 565    value is. */
 566
 567 /* UserMode */
 568 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 569
 570 /* BigEndianMem */
 571 /* Hardware configuration. Affects endianness of LoadMemory and
 572    StoreMemory and the endianness of Kernel and Supervisor mode
 573    execution. The value is 0 for little-endian; 1 for big-endian. */
 574 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 575 /*(state & simBE) ? 1 : 0)*/
 576
 577 /* ByteSwapMem */
 578 /* This is true if the host and target have different endianness.  */
 579 #define ByteSwapMem (CURRENT_TARGET_BYTE_ORDER != CURRENT_HOST_BYTE_ORDER)
 580
 581 /* ReverseEndian */
 582 /* This mode is selected if in User mode with the RE bit being set in
 583    SR (Status Register). It reverses the endianness of load and store
 584    instructions. */
 585 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 586
 587 /* BigEndianCPU */
 588 /* The endianness for load and store instructions (0=little;1=big). In
 589    User mode this endianness may be switched by setting the state_RE
 590    bit in the SR register. Thus, BigEndianCPU may be computed as
 591    (BigEndianMem EOR ReverseEndian). */
 592 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 593
 594
 595
 596 /* Exceptions: */
 597
 598 /* NOTE: These numbers depend on the processor architecture being
 599    simulated: */
 600 #define Interrupt               (0)
 601 #define TLBModification         (1)
 602 #define TLBLoad                 (2)
 603 #define TLBStore                (3)
 604 #define AddressLoad             (4)
 605 #define AddressStore            (5)
 606 #define InstructionFetch        (6)
 607 #define DataReference           (7)
 608 #define SystemCall              (8)
 609 #define BreakPoint              (9)
 610 #define ReservedInstruction     (10)
 611 #define CoProcessorUnusable     (11)
 612 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 613 #define Trap                    (13)
 614 #define FPE                     (15)
 615 #define DebugBreakPoint         (16)
 616 #define Watch                   (23)
 617
 618 /* The following exception code is actually private to the simulator
 619    world. It is *NOT* a processor feature, and is used to signal
 620    run-time errors in the simulator. */
 621 #define SimulatorFault      (0xFFFFFFFF)
 622
 623 void signal_exception (SIM_DESC sd, int exception, ...);
 624 #define SignalException(exc,instruction) signal_exception (sd, (exc), (instruction))
 625 #define SignalExceptionInterrupt() signal_exception (sd, Interrupt)
 626 #define SignalExceptionInstructionFetch() signal_exception (sd, InstructionFetch)
 627 #define SignalExceptionAddressStore() signal_exception (sd, AddressStore)
 628 #define SignalExceptionAddressLoad() signal_exception (sd, AddressLoad)
 629 #define SignalExceptionSimulatorFault(buf) signal_exception (sd, SimulatorFault, buf)
 630 #define SignalExceptionFPE() signal_exception (sd, FPE)
 631 #define SignalExceptionIntegerOverflow() signal_exception (sd, IntegerOverflow)
 632 #define SignalExceptionCoProcessorUnusable() signal_exception (sd, CoProcessorUnusable)
 633
 634
 635 /* Co-processor accesses */
 636
 637 void cop_lw  PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg, unsigned int memword));
 638 void cop_ld  PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg, uword64 memword));
 639 unsigned int cop_sw PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg));
 640 uword64 cop_sd PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg));
 641
 642 #define COP_LW(coproc_num,coproc_reg,memword) cop_lw(sd,coproc_num,coproc_reg,memword)
 643 #define COP_LD(coproc_num,coproc_reg,memword) cop_ld(sd,coproc_num,coproc_reg,memword)
 644 #define COP_SW(coproc_num,coproc_reg) cop_sw(sd,coproc_num,coproc_reg)
 645 #define COP_SD(coproc_num,coproc_reg) cop_sd(sd,coproc_num,coproc_reg)
 646
 647 void decode_coproc PARAMS ((SIM_DESC sd,unsigned int instruction));
 648 #define DecodeCoproc(instruction) decode_coproc(sd, (instruction))
 649
 650
 651
 652 /* Memory accesses */
 653
 654 /* The following are generic to all versions of the MIPS architecture
 655    to date: */
 656
 657 /* Memory Access Types (for CCA): */
 658 #define Uncached                (0)
 659 #define CachedNoncoherent       (1)
 660 #define CachedCoherent          (2)
 661 #define Cached                  (3)
 662
 663 #define isINSTRUCTION   (1 == 0) /* FALSE */
 664 #define isDATA          (1 == 1) /* TRUE */
 665 #define isLOAD          (1 == 0) /* FALSE */
 666 #define isSTORE         (1 == 1) /* TRUE */
 667 #define isREAL          (1 == 0) /* FALSE */
 668 #define isRAW           (1 == 1) /* TRUE */
 669 #define isTARGET        (1 == 0) /* FALSE */
 670 #define isHOST          (1 == 1) /* TRUE */
 671
 672 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 673    is the number of bytes minus 1. */
 674 #define AccessLength_BYTE       (0)
 675 #define AccessLength_HALFWORD   (1)
 676 #define AccessLength_TRIPLEBYTE (2)
 677 #define AccessLength_WORD       (3)
 678 #define AccessLength_QUINTIBYTE (4)
 679 #define AccessLength_SEXTIBYTE  (5)
 680 #define AccessLength_SEPTIBYTE  (6)
 681 #define AccessLength_DOUBLEWORD (7)
 682 #define AccessLength_QUADWORD   (15)
 683
 684 int address_translation PARAMS ((SIM_DESC sd, uword64 vAddr, int IorD, int LorS, uword64 *pAddr, int *CCA, int host, int raw));
 685 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 686 address_translation(sd, vAddr,IorD,LorS,pAddr,CCA,host,raw)
 687
 688 void load_memory PARAMS ((SIM_DESC sd, uword64* memvalp, uword64* memval1p, int CCA, int AccessLength, uword64 pAddr, uword64 vAddr, int IorD, int raw));
 689 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 690 load_memory(sd,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw)
 691
 692 void store_memory PARAMS ((SIM_DESC sd, int CCA, int AccessLength, uword64 MemElem,     uword64 MemElem1, uword64 pAddr, uword64 vAddr, int raw));
 693 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 694 store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw)
 695
 696 void cache_op PARAMS ((SIM_DESC sd, int op, uword64 pAddr, uword64 vAddr, unsigned int instruction));
 697 #define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,op,pAddr,vAddr,instruction)
 698
 699 void sync_operation PARAMS ((SIM_DESC sd, int stype));
 700 #define SyncOperation(stype) sync_operation (sd, (stype))
 701
 702 void prefetch PARAMS ((SIM_DESC sd, int CCA, uword64 pAddr, uword64 vAddr, int DATA, int hint));
 703 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,CCA,pAddr,vAddr,DATA,hint)
 704
 705 #define IMEM(CIA) 0 /* FIXME */
 706
 707
 708 #endif