sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35
  36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  38
  39 #include "sim-basics.h"
  40
  41 typedef address_word sim_cia;
  42
  43 #include "sim-base.h"
  44
  45
  46 /* Depreciated macros and types for manipulating 64bit values.  Use
  47    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  48
  49 typedef signed64 word64;
  50 typedef unsigned64 uword64;
  51
  52 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  53 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  54 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  55 #define SET64HI(t)      (((uword64)(t))<<32)
  56 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  57 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  58
  59 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  60    assume the HI32bits of the operand are zero, so we must perform a
  61    mask to ensure we can use the simple subtraction to sign-extend. */
  62 #define SIGNEXTEND(e,b) \
  63  ((unsigned_word) \
  64   (((e) & ((uword64) 1 << ((b) - 1))) \
  65    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  66    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  67
  68 /* Check if a value will fit within a halfword: */
  69 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  70
  71
  72
  73 /* Floating-point operations: */
  74
  75 #include "sim-fpu.h"
  76
  77 /* FPU registers must be one of the following types. All other values
  78    are reserved (and undefined). */
  79 typedef enum {
  80  fmt_single  = 0,
  81  fmt_double  = 1,
  82  fmt_word    = 4,
  83  fmt_long    = 5,
  84  /* The following are well outside the normal acceptable format
  85     range, and are used in the register status vector. */
  86  fmt_unknown       = 0x10000000,
  87  fmt_uninterpreted = 0x20000000,
  88  fmt_uninterpreted_32 = 0x40000000,
  89  fmt_uninterpreted_64 = 0x80000000U,
  90 } FP_formats;
  91
  92 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  93 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  94
  95 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
  96 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
  97
  98 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
  99 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 100 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 101 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 102 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 103 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 104 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 105 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 106 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 107 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 108 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 109 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 110 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 113 #define Convert(rm,op,from,to) \
 114 convert (SD, CPU, cia, rm, op, from, to)
 115
 116 /* Macro to update FPSR condition-code field. This is complicated by
 117    the fact that there is a hole in the index range of the bits within
 118    the FCSR register. Also, the number of bits visible depends on the
 119    MIPS ISA version being supported. */
 120
 121 #define SETFCC(cc,v) {\
 122   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 123   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 124 }
 125 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 126
 127 /* This should be the COC1 value at the start of the preceding
 128    instruction: */
 129 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 130
 131 #ifdef TARGET_ENABLE_FR
 132 /* FIXME: this should be enabled for all targets, but needs testing first. */
 133 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
 134    ? ((SR & status_FR) ? 64 : 32) \
 135    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
 136 #else
 137 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 138 #endif
 139
 140 /* Standard FCRS bits: */
 141 #define IR (0) /* Inexact Result */
 142 #define UF (1) /* UnderFlow */
 143 #define OF (2) /* OverFlow */
 144 #define DZ (3) /* Division by Zero */
 145 #define IO (4) /* Invalid Operation */
 146 #define UO (5) /* Unimplemented Operation */
 147
 148 /* Get masks for individual flags: */
 149 #if 1 /* SAFE version */
 150 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 151 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 152 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 153 #else
 154 #define FP_FLAGS(b)  (1 << ((b) + 2))
 155 #define FP_ENABLE(b) (1 << ((b) + 7))
 156 #define FP_CAUSE(b)  (1 << ((b) + 12))
 157 #endif
 158
 159 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 160
 161 #define FP_MASK_RM    (0x3)
 162 #define FP_SH_RM      (0)
 163 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 164 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 165 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 166 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 167 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 168
 169 /* start-sanitize-sky */
 170 #ifdef TARGET_SKY
 171 #ifdef SKY_FUNIT
 172 #include <assert.h>
 173 #include "wf.h"
 174 #endif
 175 #endif
 176 /* end-sanitize-sky */
 177
 178
 179
 180
 181
 182 /* HI/LO register accesses */
 183
 184 /* For some MIPS targets, the HI/LO registers have certain timing
 185    restrictions in that, for instance, a read of a HI register must be
 186    separated by at least three instructions from a preceeding read.
 187
 188    The struct below is used to record the last access by each of A MT,
 189    MF or other OP instruction to a HI/LO register.  See mips.igen for
 190    more details. */
 191
 192 typedef struct _hilo_access {
 193   signed64 timestamp;
 194   address_word cia;
 195 } hilo_access;
 196
 197 typedef struct _hilo_history {
 198   hilo_access mt;
 199   hilo_access mf;
 200   hilo_access op;
 201 } hilo_history;
 202
 203
 204
 205
 206 /* Integer ALU operations: */
 207
 208 #include "sim-alu.h"
 209
 210 #define ALU32_END(ANS) \
 211   if (ALU32_HAD_OVERFLOW) \
 212     SignalExceptionIntegerOverflow (); \
 213   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 214
 215
 216 #define ALU64_END(ANS) \
 217   if (ALU64_HAD_OVERFLOW) \
 218     SignalExceptionIntegerOverflow (); \
 219   (ANS) = ALU64_OVERFLOW_RESULT;
 220
 221
 222 /* start-sanitize-r5900 */
 223
 224 /* Figure 10-5 FPU Control/Status Register.
 225    Note: some of these bits are different to what is found in a
 226    standard MIPS manual. */
 227 enum {
 228   R5900_FCSR_C = BIT (23), /* OK */
 229   R5900_FCSR_I = BIT (17),
 230   R5900_FCSR_D = BIT (16),
 231   R5900_FCSR_O = BIT (15),
 232   R5900_FCSR_U = BIT (14),
 233   R5900_FCSR_CAUSE = MASK (16,14),
 234   R5900_FCSR_SI = BIT (6),
 235   R5900_FCSR_SD = BIT (5),
 236   R5900_FCSR_SO = BIT (4),
 237   R5900_FCSR_SU = BIT (3),
 238 };
 239
 240 /* Table 10-1 FP format values.
 241    Note: some of these bits are different to what is found in a
 242    standard MIPS manual. */
 243 enum {
 244   R5900_EXPMAX = 128,
 245   R5900_EXPMIN = -127,
 246   R5900_EXPBIAS = 127,
 247 };
 248
 249 /* MAX and MIN FP values */
 250 enum {
 251   R5900_FPMAX = LSMASK32 (30, 0),
 252   R5900_FPMIN = LSMASK32 (31, 0),
 253 };
 254
 255 typedef struct _r4000_tlb_entry {
 256   unsigned32 mask;
 257   unsigned32 hi;
 258   unsigned32 lo0;
 259   unsigned32 lo1;
 260 } r4000_tlb_entry_t;
 261
 262 #define TLB_MASK_MASK_MASK 0x01ffe000
 263 #define TLB_HI_VPN2_MASK   0xffffe000
 264 #define TLB_HI_G_MASK      0x00001000
 265 #define TLB_HI_ASID_MASK   0x000000ff
 266
 267 #define TLB_LO_S_MASK      0x80000000
 268 #define TLB_LO_PFN_MASK    0x03ffffc0
 269 #define TLB_LO_C_MASK      0x00000038
 270 #define TLB_LO_D_MASK      0x00000004
 271 #define TLB_LO_V_MASK      0x00000002
 272
 273 #define TLB_SIZE 48
 274
 275 typedef struct _sim_r5900_cpu {
 276
 277   /* The R5900 has 32 x 128bit general purpose registers.
 278      Fortunatly, the high 64 bits are only touched by multimedia (MMI)
 279      instructions.  The normal mips instructions just use the lower 64
 280      bits.  To avoid changing the older parts of the simulator to
 281      handle this weirdness, the high 64 bits of each register are kept
 282      in a separate array (registers1).  The high 64 bits of any
 283      register are by convention refered by adding a '1' to the end of
 284      the normal register's name.  So LO still refers to the low 64
 285      bits of the LO register, LO1 refers to the high 64 bits of that
 286      same register.  */
 287   signed_word gpr1[32];
 288 #define GPR1     ((CPU)->r5900.gpr1)
 289 #define GPR1_SET(N,VAL) (GPR1[(N]) = (VAL))
 290   signed_word lo1;
 291   signed_word hi1;
 292 #define LO1      ((CPU)->r5900.lo1)
 293 #define HI1      ((CPU)->r5900.hi1)
 294
 295   /* The R5900 defines a shift amount register, that controls the
 296      amount of certain shift instructions */
 297   unsigned_word sa;        /* the shift amount register */
 298 #define REGISTER_SA     (124) /* GET RID IF THIS! */
 299 #define SA ((CPU)->r5900.sa)
 300
 301   /* The R5900, in addition to the (almost) standard floating point
 302      registers, defines a 32 bit accumulator.  This is used in
 303      multiply/accumulate style instructions */
 304   fp_word acc; /* floating-point accumulator */
 305 #define ACC ((CPU)->r5900.acc)
 306
 307   /* See comments below about needing to count cycles between updating
 308      and setting HI/LO registers */
 309   hilo_history hi1_history;
 310 #define HI1HISTORY (&(CPU)->r5900.hi1_history)
 311   hilo_history lo1_history;
 312 #define LO1HISTORY (&(CPU)->r5900.lo1_history)
 313
 314   r4000_tlb_entry_t tlb[TLB_SIZE];
 315 #define TLB ((CPU)->r5900.tlb)
 316
 317 } sim_r5900_cpu;
 318
 319 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 320 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 321 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 322 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 323
 324 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 325 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 326 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 327 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 328
 329 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 330    T  - type of the sub part
 331    TC - # of T's in the mips part of the "register"
 332    I  - index (from 0) of desired sub part
 333    A  - low part of "register"
 334    A1 - high part of register
 335 */
 336 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 337 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 338    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 339       ? ((TC) - 1 - (I) % (TC)) \
 340       : ((I) % (TC)) \
 341       ) \
 342    ) \
 343  )
 344
 345 /*
 346 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 347             where <type> has two letters:
 348                   1 is S=signed or U=unsigned
 349                   2 is B=byte H=halfword W=word D=doubleword
 350 */
 351
 352 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 353 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 354 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 355 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 356
 357 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 358 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 359 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 360 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 361
 362 #define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
 363 #define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
 364 #define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
 365 #define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
 366
 367 #define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
 368 #define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
 369 #define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
 370 #define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
 371
 372 #define TMP_DCL unsigned64 tmp_reg, tmp_reg1
 373
 374 #define TMP_SB(I) SUB_REG_SB(&tmp_reg, &tmp_reg1, I)
 375 #define TMP_SH(I) SUB_REG_SH(&tmp_reg, &tmp_reg1, I)
 376 #define TMP_SW(I) SUB_REG_SW(&tmp_reg, &tmp_reg1, I)
 377 #define TMP_SD(I) SUB_REG_SD(&tmp_reg, &tmp_reg1, I)
 378
 379 #define TMP_UB(I) SUB_REG_UB(&tmp_reg, &tmp_reg1, I)
 380 #define TMP_UH(I) SUB_REG_UH(&tmp_reg, &tmp_reg1, I)
 381 #define TMP_UW(I) SUB_REG_UW(&tmp_reg, &tmp_reg1, I)
 382 #define TMP_UD(I) SUB_REG_UD(&tmp_reg, &tmp_reg1, I)
 383
 384 #define TMP_WRT(R) do { GPR[R] = tmp_reg; GPR1[R] = tmp_reg1; } while(0)
 385
 386 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 387 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 388 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 389 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 390
 391 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 392 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 393 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 394 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 395
 396 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 397 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 398 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 399 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 400
 401 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 402 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 403 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 404 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 405
 406
 407
 408 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 409 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 410 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 411 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 412
 413 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 414 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 415 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 416 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 417
 418 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 419 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 420 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 421 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 422
 423 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 424 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 425 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 426 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 427
 428 /* end-sanitize-r5900 */
 429
 430
 431
 432 /* The following is probably not used for MIPS IV onwards: */
 433 /* Slots for delayed register updates. For the moment we just have a
 434    fixed number of slots (rather than a more generic, dynamic
 435    system). This keeps the simulator fast. However, we only allow
 436    for the register update to be delayed for a single instruction
 437    cycle. */
 438 #define PSLOTS (8) /* Maximum number of instruction cycles */
 439
 440 typedef struct _pending_write_queue {
 441   int in;
 442   int out;
 443   int total;
 444   int slot_delay[PSLOTS];
 445   int slot_size[PSLOTS];
 446   int slot_bit[PSLOTS];
 447   void *slot_dest[PSLOTS];
 448   unsigned64 slot_value[PSLOTS];
 449 } pending_write_queue;
 450
 451 #ifndef PENDING_TRACE
 452 #define PENDING_TRACE 0
 453 #endif
 454 #define PENDING_IN ((CPU)->pending.in)
 455 #define PENDING_OUT ((CPU)->pending.out)
 456 #define PENDING_TOTAL ((CPU)->pending.total)
 457 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 458 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 459 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 460 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 461 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 462
 463 /* Invalidate the pending write queue, all pending writes are
 464    discarded. */
 465
 466 #define PENDING_INVALIDATE() \
 467 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 468
 469 /* Schedule a write to DEST for N cycles time.  For 64 bit
 470    destinations, schedule two writes.  For floating point registers,
 471    the caller should schedule a write to both the dest register and
 472    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 473    is updated. */
 474
 475 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 476   do {                                                                  \
 477     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 478       sim_engine_abort (SD, CPU, cia,                                   \
 479                         "PENDING_SCHED - buffer overflow\n");           \
 480     if (PENDING_TRACE)                                                  \
 481       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 482                       (unsigned long) cia, (unsigned long) &(DEST),     \
 483                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 484                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 485     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 486     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 487     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 488     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 489     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 490     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 491     PENDING_TOTAL += 1;                                                 \
 492   } while (0)
 493
 494 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 495 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 496
 497 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 498
 499 #define PENDING_FLUSH() abort () /* think about this one */
 500 #define PENDING_FP() abort () /* think about this one */
 501
 502 /* For backward compatibility */
 503 #define PENDING_FILL(R,VAL)                                             \
 504 do {                                                                    \
 505   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 506     {                                                                   \
 507       PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1);                     \
 508       PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
 509     }                                                                   \
 510   else                                                                  \
 511     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 512 } while (0)
 513
 514
 515
 516 struct _sim_cpu {
 517
 518
 519   /* The following are internal simulator state variables: */
 520 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 521 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 522   address_word dspc;  /* delay-slot PC */
 523 #define DSPC ((CPU)->dspc)
 524
 525 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 526 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 527
 528
 529   /* State of the simulator */
 530   unsigned int state;
 531   unsigned int dsstate;
 532 #define STATE ((CPU)->state)
 533 #define DSSTATE ((CPU)->dsstate)
 534
 535 /* Flags in the "state" variable: */
 536 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 537 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 538 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 539 #define simPCOC0        (1 << 17) /* COC[1] from current */
 540 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 541 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 542 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 543 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 544 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 545
 546 #define ENGINE_ISSUE_PREFIX_HOOK() \
 547   { \
 548     /* Perform any pending writes */ \
 549     PENDING_TICK(); \
 550     /* Set previous flag, depending on current: */ \
 551     if (STATE & simPCOC0) \
 552      STATE |= simPCOC1; \
 553     else \
 554      STATE &= ~simPCOC1; \
 555     /* and update the current value: */ \
 556     if (GETFCC(0)) \
 557      STATE |= simPCOC0; \
 558     else \
 559      STATE &= ~simPCOC0; \
 560   }
 561
 562
 563 /* This is nasty, since we have to rely on matching the register
 564    numbers used by GDB. Unfortunately, depending on the MIPS target
 565    GDB uses different register numbers. We cannot just include the
 566    relevant "gdb/tm.h" link, since GDB may not be configured before
 567    the sim world, and also the GDB header file requires too much other
 568    state. */
 569
 570 #ifndef TM_MIPS_H
 571 #define LAST_EMBED_REGNUM (89)
 572 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 573
 574 /* start-sanitize-r5900 */
 575 #define FIRST_COP0_REG 128
 576 #define NUM_COP0_REGS 22
 577 #undef NUM_REGS
 578 #define NUM_REGS (150)
 579 /* end-sanitize-r5900 */
 580
 581 #endif
 582
 583 /* start-sanitize-sky */
 584 #ifdef TARGET_SKY
 585 #ifndef TM_TXVU_H
 586 /* Number of machine registers */
 587 #define NUM_VU_REGS     160
 588
 589 #define NUM_VU_INTEGER_REGS 16
 590 #define FIRST_VEC_REG   32
 591
 592 #define NUM_VIF_REGS    26
 593
 594 #define NUM_CORE_REGS   150
 595
 596 #undef NUM_REGS
 597 #define NUM_REGS (NUM_CORE_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
 598 #endif /* no tm-txvu.h */
 599 #endif /* TARGET_SKY */
 600 /* end-sanitize-sky */
 601
 602 enum float_operation
 603 /* start-sanitize-sky */
 604 /* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
 605 /* end-sanitize-sky */
 606   {
 607     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 608     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 609     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 610   };
 611
 612 /* To keep this default simulator simple, and fast, we use a direct
 613    vector of registers. The internal simulator engine then uses
 614    manifests to access the correct slot. */
 615
 616   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 617
 618   int register_widths[NUM_REGS];
 619 #define REGISTERS       ((CPU)->registers)
 620
 621 #define GPR     (&REGISTERS[0])
 622 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 623
 624   /* While space is allocated for the floating point registers in the
 625      main registers array, they are stored separatly.  This is because
 626      their size may not necessarily match the size of either the
 627      general-purpose or system specific registers */
 628 #define NR_FGR  (32)
 629 #define FGRIDX  (38)
 630   fp_word fgr[NR_FGR];
 631 #define FGR     ((CPU)->fgr)
 632
 633 #define LO      (REGISTERS[33])
 634 #define HI      (REGISTERS[34])
 635 #define PCIDX   37
 636 #define PC      (REGISTERS[PCIDX])
 637 #define CAUSE   (REGISTERS[36])
 638 #define SRIDX   (32)
 639 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 640 #define FCR0IDX  (71)
 641 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 642 #define FCR31IDX (70)
 643 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 644 #define FCSR    (FCR31)
 645 #define Debug   (REGISTERS[86])
 646 #define DEPC    (REGISTERS[87])
 647 #define EPC     (REGISTERS[88])
 648 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 649
 650   /* All internal state modified by signal_exception() that may need to be
 651      rolled back for passing moment-of-exception image back to gdb. */
 652   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 653   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 654   int exc_suspended;
 655
 656 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 657 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 658 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 659
 660   unsigned_word c0_config_reg;
 661 #define C0_CONFIG ((CPU)->c0_config_reg)
 662
 663 /* The following are pseudonyms for standard registers */
 664 #define ZERO    (REGISTERS[0])
 665 #define V0      (REGISTERS[2])
 666 #define A0      (REGISTERS[4])
 667 #define A1      (REGISTERS[5])
 668 #define A2      (REGISTERS[6])
 669 #define A3      (REGISTERS[7])
 670 #define T8IDX   24
 671 #define T8      (REGISTERS[T8IDX])
 672 #define SPIDX   29
 673 #define SP      (REGISTERS[SPIDX])
 674 #define RAIDX   31
 675 #define RA      (REGISTERS[RAIDX])
 676
 677   /* While space is allocated in the main registers arrray for some of
 678      the COP0 registers, that space isn't sufficient.  Unknown COP0
 679      registers overflow into the array below */
 680
 681 #define NR_COP0_GPR     32
 682   unsigned_word cop0_gpr[NR_COP0_GPR];
 683 #define COP0_GPR        ((CPU)->cop0_gpr)
 684   /* start-sanitize-r5900 */
 685 #define NR_COP0_BP      8
 686   unsigned_word cop0_bp[NR_COP0_BP];
 687 #define COP0_BP ((CPU)->cop0_bp)
 688 #define NR_COP0_P 64
 689   unsigned_word cop0_p[NR_COP0_P];
 690
 691 #define COP0_P  ((CPU)->cop0_p)
 692 #define COP0_INDEX    ((unsigned32)(COP0_GPR[0]))
 693 #define COP0_RANDOM   ((unsigned32)(COP0_GPR[1]))
 694 #define COP0_ENTRYLO0 ((unsigned32)(COP0_GPR[2]))
 695 #define COP0_ENTRYLO1 ((unsigned32)(COP0_GPR[3]))
 696 #define COP0_CONTEXT  ((unsigned32)(COP0_GPR[4]))
 697 #define COP0_PAGEMASK ((unsigned32)(COP0_GPR[5]))
 698 #define COP0_WIRED    ((unsigned32)(COP0_GPR[6]))
 699   /* end-sanitize-r5900 */
 700 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 701   /* start-sanitize-r5900 */
 702 #define COP0_COUNT    ((unsigned32)(COP0_GPR[9]))
 703 #define COP0_ENTRYHI  ((unsigned32)(COP0_GPR[10]))
 704 #define COP0_COMPARE  ((unsigned32)(COP0_GPR[11]))
 705 #define COP0_EPC      ((unsigned32)(EPC))       /* 14 */
 706 #define COP0_PRID     ((unsigned32)(COP0_GPR[15]))
 707 #define COP0_CONFIG   ((unsigned32)(C0_CONFIG)) /* 16 */
 708 #define COP0_TAGLO    ((unsigned32)(COP0_GPR[28]))
 709 #define COP0_TAGHI    ((unsigned32)(COP0_GPR[29]))
 710 #define COP0_ERROREPC ((unsigned32)(COP0_GPR[30]))
 711
 712 #define COP0_CONTEXT_BADVPN2_MASK 0x007ffff0
 713
 714 #define COP0_CONTEXT_set_BADVPN2(x) \
 715         (COP0_CONTEXT = ((COP0_CONTEXT & 0xff100000) | ((x << 4) & 0x007ffff0)))
 716   /* end-sanitize-r5900 */
 717
 718   /* Keep the current format state for each register: */
 719   FP_formats fpr_state[32];
 720 #define FPR_STATE ((CPU)->fpr_state)
 721
 722   pending_write_queue pending;
 723
 724   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 725      read-write instructions. It is set when a linked load occurs. It
 726      is tested and cleared by the conditional store. It is cleared
 727      (during other CPU operations) when a store to the location would
 728      no longer be atomic. In particular, it is cleared by exception
 729      return instructions. */
 730   int llbit;
 731 #define LLBIT ((CPU)->llbit)
 732
 733
 734 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 735    corruptions caused by using the HI or LO register too close to a
 736    following operation is spotted. See mips.igen for more details. */
 737
 738   hilo_history hi_history;
 739 #define HIHISTORY (&(CPU)->hi_history)
 740   hilo_history lo_history;
 741 #define LOHISTORY (&(CPU)->lo_history)
 742
 743   /* start-sanitize-branchbug4011 */
 744 #if 1
 745   int branchbug4011_option;
 746 #define BRANCHBUG4011_OPTION ((CPU)->branchbug4011_option)
 747   address_word branchbug4011_last_target;
 748 #define BRANCHBUG4011_LAST_TARGET ((CPU)->branchbug4011_last_target)
 749   address_word branchbug4011_last_cia;
 750 #define BRANCHBUG4011_LAST_CIA ((CPU)->branchbug4011_last_cia)
 751
 752 #define check_branch_bug() (check_4011_branch_bug (_SD))
 753 #define mark_branch_bug(TARGET) (mark_4011_branch_bug (_SD,TARGET))
 754 #else
 755   /* end-sanitize-branchbug4011 */
 756 #define check_branch_bug()
 757 #define mark_branch_bug(TARGET)
 758   /* start-sanitize-branchbug4011 */
 759 #endif
 760   /* end-sanitize-branchbug4011 */
 761   /* start-sanitize-r5900 */
 762   sim_r5900_cpu r5900;
 763   /* end-sanitize-r5900 */
 764
 765   /* start-sanitize-cygnus */
 766   /* The MDMX ISA has a very very large accumulator */
 767   unsigned8 acc[3 * 8];
 768   /* end-sanitize-cygnus */
 769
 770   /* start-sanitize-sky */
 771 #ifdef TARGET_SKY
 772   /* Device on which instruction issue last occured.  */
 773   char cur_device;
 774 #endif
 775   /* end-sanitize-sky */
 776
 777   sim_cpu_base base;
 778 };
 779
 780
 781 /* MIPS specific simulator watch config */
 782
 783 void watch_options_install PARAMS ((SIM_DESC sd));
 784
 785 struct swatch {
 786   sim_event *pc;
 787   sim_event *clock;
 788   sim_event *cycles;
 789 };
 790
 791
 792 /* FIXME: At present much of the simulator is still static */
 793 struct sim_state {
 794
 795   struct swatch watch;
 796
 797   sim_cpu cpu[MAX_NR_PROCESSORS];
 798 #if (WITH_SMP)
 799 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 800 #else
 801 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 802 #endif
 803
 804 /* start-sanitize-sky */
 805 #ifdef TARGET_SKY
 806
 807 #ifdef SKY_FUNIT
 808   /* Record of option for floating point implementation type. */
 809   int fp_type_opt;
 810 #define STATE_FP_TYPE_OPT(sd) ((sd)->fp_type_opt)
 811 #define STATE_FP_TYPE_OPT_ACCURATE 0x80000000
 812 #endif
 813
 814   /* Index of next unused name slot for multi-phase load list. */
 815   int next_mload_count;
 816 #define STATE_MLOAD_COUNT(sd) ((sd)->next_mload_count)
 817
 818 #define MAX_MLOAD_COUNT 2 /* limit for next_load_count and load_index */
 819
 820   /* Program names for multi-phase load. */
 821   char *next_mload_name[MAX_MLOAD_COUNT];
 822 #define STATE_MLOAD_NAME(sd) ((sd)->next_mload_name)
 823
 824   /* Index of next program for multi-phase load. */
 825   int mload_index;
 826 #define STATE_MLOAD_INDEX(sd) ((sd)->mload_index)
 827
 828 #endif
 829 /* end-sanitize-sky */
 830
 831   sim_state_base base;
 832 };
 833
 834
 835
 836 /* Status information: */
 837
 838 /* TODO : these should be the bitmasks for these bits within the
 839    status register. At the moment the following are VR4300
 840    bit-positions: */
 841 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 842 #define status_KSU_shift (3)            /* shift for field */
 843 #define ksu_kernel       (0x0)
 844 #define ksu_supervisor   (0x1)
 845 #define ksu_user         (0x2)
 846 #define ksu_unknown      (0x3)
 847
 848 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 849
 850 #define status_IE        (1 <<  0)      /* Interrupt enable */
 851 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 852 #define status_EXL       (1 <<  1)      /* Exception level */
 853 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 854 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 855 #define status_SR        (1 << 20)      /* soft reset or NMI */
 856 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 857 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 858 #define status_ERL       (1 <<  2)      /* Error level */
 859 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 860 #define status_RP        (1 << 27)      /* Reduced Power mode */
 861 /* start-sanitize-r5900 */
 862 #define status_CU0       (1 << 28)      /* COP0 usable */
 863 #define status_CU1       (1 << 29)      /* COP1 usable */
 864 #define status_CU2       (1 << 30)      /* COP2 usable */
 865 /* end-sanitize-r5900 */
 866
 867 /* Specializations for TX39 family */
 868 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 869 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 870 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 871 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 872 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 873 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 874 #define status_IM_mask   (0xff)         /* Interrupt mask */
 875 #define status_IM_shift  (8)
 876 #define status_NMI       (1 << 20)      /* NMI */
 877 #define status_NMI       (1 << 20)      /* NMI */
 878
 879 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 880 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 881 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 882 #define cause_CE_shift    28
 883 #define cause_EXC2_mask   0x00070000
 884 #define cause_EXC2_shift  16
 885 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 886 #define cause_SIOP        (1 << 12)     /* SIO pending */
 887 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 888 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 889
 890 /* start-sanitize-sky */
 891 #ifdef TARGET_SKY
 892 #define cause_EXC_mask  (0x7c)          /* Exception code */
 893 #else
 894 /* end-sanitize-sky */
 895 #define cause_EXC_mask  (0x1c)          /* Exception code */
 896 /* start-sanitize-sky */
 897 #endif
 898 /* end-sanitize-sky */
 899 #define cause_EXC_shift (2)
 900
 901 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 902 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 903 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 904 #define cause_IP_shift  (10)
 905
 906 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 907 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 908
 909
 910 /* NOTE: We keep the following status flags as bit values (1 for true,
 911    0 for false). This allows them to be used in binary boolean
 912    operations without worrying about what exactly the non-zero true
 913    value is. */
 914
 915 /* UserMode */
 916 #ifdef SUBTARGET_R3900
 917 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 918 #else
 919 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 920 #endif /* SUBTARGET_R3900 */
 921
 922 /* BigEndianMem */
 923 /* Hardware configuration. Affects endianness of LoadMemory and
 924    StoreMemory and the endianness of Kernel and Supervisor mode
 925    execution. The value is 0 for little-endian; 1 for big-endian. */
 926 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 927 /*(state & simBE) ? 1 : 0)*/
 928
 929 /* ReverseEndian */
 930 /* This mode is selected if in User mode with the RE bit being set in
 931    SR (Status Register). It reverses the endianness of load and store
 932    instructions. */
 933 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 934
 935 /* BigEndianCPU */
 936 /* The endianness for load and store instructions (0=little;1=big). In
 937    User mode this endianness may be switched by setting the state_RE
 938    bit in the SR register. Thus, BigEndianCPU may be computed as
 939    (BigEndianMem EOR ReverseEndian). */
 940 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 941
 942
 943
 944 /* Exceptions: */
 945
 946 /* NOTE: These numbers depend on the processor architecture being
 947    simulated: */
 948 enum ExceptionCause {
 949   Interrupt               = 0,
 950   TLBModification         = 1,
 951   TLBLoad                 = 2,
 952   TLBStore                = 3,
 953   AddressLoad             = 4,
 954   AddressStore            = 5,
 955   InstructionFetch        = 6,
 956   DataReference           = 7,
 957   SystemCall              = 8,
 958   BreakPoint              = 9,
 959   ReservedInstruction     = 10,
 960   CoProcessorUnusable     = 11,
 961   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 962   Trap                    = 13,
 963   FPE                     = 15,
 964   DebugBreakPoint         = 16,
 965   Watch                   = 23,
 966   NMIReset                = 31,
 967
 968
 969 /* The following exception code is actually private to the simulator
 970    world. It is *NOT* a processor feature, and is used to signal
 971    run-time errors in the simulator. */
 972   SimulatorFault          = 0xFFFFFFFF
 973 };
 974
 975 #define TLB_REFILL  (0)
 976 #define TLB_INVALID (1)
 977
 978 /* start-sanitize-r5900 */
 979 /* For the 5900, we have level 1 and level 2 exceptions.  The level 2 exceptions
 980    are ColdReset, NMI, Counter, and Debug/SIO.  Of these, we support only
 981    the NMIReset exception. */
 982
 983 #define is5900Level2Exception(x) (x == NMIReset)
 984 /* end-sanitize-r5900 */
 985
 986 /* The following break instructions are reserved for use by the
 987    simulator.  The first is used to halt the simulation.  The second
 988    is used by gdb for break-points.  NOTE: Care must be taken, since
 989    this value may be used in later revisions of the MIPS ISA. */
 990 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 991
 992 #define HALT_INSTRUCTION        (0x03ff000d)
 993 #define HALT_INSTRUCTION2       (0x0000ffcd)
 994
 995 /* start-sanitize-sky */
 996 #define HALT_INSTRUCTION_PASS   (0x03fffc0d)    /* break 0xffff0 */
 997 #define HALT_INSTRUCTION_FAIL   (0x03ffffcd)    /* break 0xfffff */
 998 /* end-sanitize-sky */
 999
1000 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
1001 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
1002
1003 /* start-sanitize-sky */
1004 #define LOAD_INSTRUCTION        (0x03fffc4d)    /* break 0xffff1 */
1005 #define PRINTF_INSTRUCTION      (0x03fffc8d)    /* break 0xffff2 */
1006 /* end-sanitize-sky */
1007
1008
1009 void interrupt_event (SIM_DESC sd, void *data);
1010
1011 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
1012 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
1013 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
1014 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
1015 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
1016 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
1017 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
1018 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
1019 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
1020 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
1021 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
1022 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
1023 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
1024 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
1025 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
1026 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
1027 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
1028
1029 /* Co-processor accesses */
1030
1031 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
1032 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
1033 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
1034 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
1035
1036 #define COP_LW(coproc_num,coproc_reg,memword) \
1037 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
1038 #define COP_LD(coproc_num,coproc_reg,memword) \
1039 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
1040 #define COP_SW(coproc_num,coproc_reg) \
1041 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
1042 #define COP_SD(coproc_num,coproc_reg) \
1043 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
1044
1045 /* start-sanitize-sky */
1046 #ifdef TARGET_SKY
1047 void cop_lq  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
1048                       int coproc_num, int coproc_reg, unsigned128 memword));
1049 unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
1050                             int coproc_num, int coproc_reg));
1051 #define COP_LQ(coproc_num,coproc_reg,memword) \
1052 cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
1053 #define COP_SQ(coproc_num,coproc_reg) \
1054 cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
1055 #endif /* TARGET_SKY */
1056 /* end-sanitize-sky */
1057
1058 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
1059 #define DecodeCoproc(instruction) \
1060 decode_coproc (SD, CPU, cia, (instruction))
1061
1062 void sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
1063
1064
1065
1066 /* Memory accesses */
1067
1068 /* The following are generic to all versions of the MIPS architecture
1069    to date: */
1070
1071 /* Memory Access Types (for CCA): */
1072 #define Uncached                (0)
1073 #define CachedNoncoherent       (1)
1074 #define CachedCoherent          (2)
1075 #define Cached                  (3)
1076
1077 #define isINSTRUCTION   (1 == 0) /* FALSE */
1078 #define isDATA          (1 == 1) /* TRUE */
1079 #define isLOAD          (1 == 0) /* FALSE */
1080 #define isSTORE         (1 == 1) /* TRUE */
1081 #define isREAL          (1 == 0) /* FALSE */
1082 #define isRAW           (1 == 1) /* TRUE */
1083 /* The parameter HOST (isTARGET / isHOST) is ignored */
1084 #define isTARGET        (1 == 0) /* FALSE */
1085 /* #define isHOST          (1 == 1) TRUE */
1086
1087 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
1088    is the number of bytes minus 1. */
1089 #define AccessLength_BYTE       (0)
1090 #define AccessLength_HALFWORD   (1)
1091 #define AccessLength_TRIPLEBYTE (2)
1092 #define AccessLength_WORD       (3)
1093 #define AccessLength_QUINTIBYTE (4)
1094 #define AccessLength_SEXTIBYTE  (5)
1095 #define AccessLength_SEPTIBYTE  (6)
1096 #define AccessLength_DOUBLEWORD (7)
1097 #define AccessLength_QUADWORD   (15)
1098
1099 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
1100                     ? AccessLength_DOUBLEWORD /*7*/ \
1101                     : AccessLength_WORD /*3*/)
1102 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
1103
1104
1105 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
1106 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
1107 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
1108
1109 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
1110 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
1111 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
1112
1113 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
1114 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
1115 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
1116
1117 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
1118 #define CacheOp(op,pAddr,vAddr,instruction) \
1119 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
1120
1121 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
1122 #define SyncOperation(stype) \
1123 sync_operation (SD, CPU, cia, (stype))
1124
1125 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
1126 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
1127 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
1128
1129 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
1130 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
1131 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
1132 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
1133 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
1134
1135 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
1136 extern FILE *tracefh;
1137
1138 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
1139 extern SIM_CORE_SIGNAL_FN mips_core_signal;
1140
1141 char* pr_addr PARAMS ((SIM_ADDR addr));
1142 char* pr_uword64 PARAMS ((uword64 addr));
1143
1144 /* start-sanitize-sky */
1145 #ifdef TARGET_SKY
1146
1147 #ifdef SIM_ENGINE_HALT_HOOK
1148 #undef SIM_ENGINE_HALT_HOOK
1149 #endif
1150
1151 void sky_sim_engine_halt PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
1152 #define SIM_ENGINE_HALT_HOOK(sd, last, cia) sky_sim_engine_halt(sd, last, cia)
1153
1154 #ifdef SIM_ENGINE_RESTART_HOOK
1155 #undef SIM_ENGINE_RESTART_HOOK
1156 #endif
1157
1158 void sky_sim_engine_restart PARAMS ((SIM_DESC sd, sim_cpu *last, sim_cia cia));
1159 #define SIM_ENGINE_RESTART_HOOK(sd, L, pc) sky_sim_engine_restart(sd, L, pc)
1160
1161 /* for resume/suspend modules */
1162 SIM_RC sky_sim_module_install PARAMS ((SIM_DESC sd));
1163
1164 #define MODULE_LIST     sky_sim_module_install,
1165
1166 #ifndef TM_TXVU_H /* In case GDB hasn't been configured yet */
1167 enum txvu_cpu_context
1168 {
1169   TXVU_CPU_AUTO         = -1,   /* context-sensitive context */
1170   TXVU_CPU_MASTER       = 0,    /* R5900 core */
1171   TXVU_CPU_VU0          = 1,    /* Vector units */
1172   TXVU_CPU_VU1          = 2,
1173   TXVU_CPU_VIF0         = 3,    /* Vector interface units */
1174   TXVU_CPU_VIF1         = 4,
1175   TXVU_CPU_LAST                 /* Count of context types */
1176 };
1177
1178 /* memory segment for communication with GDB */
1179 #define VIO_BASE        0xa0000000
1180 #define GDB_COMM_AREA   0x19810000      /* Random choice */
1181 #define GDB_COMM_SIZE   0x4000
1182
1183 /* Memory address containing last device to execute */
1184 #define LAST_DEVICE     GDB_COMM_AREA
1185
1186 /* The FIFO breakpoint count and table */
1187 #define FIFO_BPT_CNT    (GDB_COMM_AREA + 4)
1188 #define FIFO_BPT_TBL    (GDB_COMM_AREA + 8)
1189
1190 /* Each element of the breakpoint table is three four-byte integers. */
1191 #define BPT_ELEM_SZ     4*3
1192
1193 #define TXVU_VU_BRK_MASK 0x02   /* Breakpoint bit is #57 for VU insns */
1194 #define TXVU_VIF_BRK_MASK 0x80  /* Use interrupt bit for VIF insns */
1195
1196 #endif /* !TM_TXVU_H */
1197 #endif /* TARGET_SKY */
1198 /* end-sanitize-sky */
1199
1200 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
1201 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
1202 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
1203
1204
1205 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1206 #include "sim-main.c"
1207 #endif
1208
1209 #endif