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[deliverable/binutils-gdb.git] / sim / mips / sim-main.h
1 /* MIPS Simulator definition.
2 Copyright (C) 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21 #ifndef SIM_MAIN_H
22 #define SIM_MAIN_H
23
24 /* This simulator doesn't cache the Current Instruction Address */
25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
27
28 #define SIM_HAVE_BIENDIAN
29
30
31 /* hobble some common features for moment */
32 #define WITH_WATCHPOINTS 1
33 #define WITH_MODULO_MEMORY 1
34
35
36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
38
39 #include "sim-basics.h"
40
41 typedef address_word sim_cia;
42
43 #include "sim-base.h"
44
45
46 /* Deprecated macros and types for manipulating 64bit values. Use
47 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
48
49 typedef signed64 word64;
50 typedef unsigned64 uword64;
51
52 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
53 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
54 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
55 #define SET64HI(t) (((uword64)(t))<<32)
56 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
57 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
58
59 /* Check if a value will fit within a halfword: */
60 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
61
62
63
64 /* Floating-point operations: */
65
66 #include "sim-fpu.h"
67 #include "cp1.h"
68
69 /* FPU registers must be one of the following types. All other values
70 are reserved (and undefined). */
71 typedef enum {
72 fmt_single = 0,
73 fmt_double = 1,
74 fmt_word = 4,
75 fmt_long = 5,
76 fmt_ps = 6,
77 /* The following are well outside the normal acceptable format
78 range, and are used in the register status vector. */
79 fmt_unknown = 0x10000000,
80 fmt_uninterpreted = 0x20000000,
81 fmt_uninterpreted_32 = 0x40000000,
82 fmt_uninterpreted_64 = 0x80000000U,
83 } FP_formats;
84
85 /* This should be the COC1 value at the start of the preceding
86 instruction: */
87 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
88
89 #ifdef TARGET_ENABLE_FR
90 /* FIXME: this should be enabled for all targets, but needs testing first. */
91 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
92 ? ((SR & status_FR) ? 64 : 32) \
93 : (WITH_TARGET_FLOATING_POINT_BITSIZE))
94 #else
95 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
96 #endif
97
98
99
100
101
102 /* HI/LO register accesses */
103
104 /* For some MIPS targets, the HI/LO registers have certain timing
105 restrictions in that, for instance, a read of a HI register must be
106 separated by at least three instructions from a preceeding read.
107
108 The struct below is used to record the last access by each of A MT,
109 MF or other OP instruction to a HI/LO register. See mips.igen for
110 more details. */
111
112 typedef struct _hilo_access {
113 signed64 timestamp;
114 address_word cia;
115 } hilo_access;
116
117 typedef struct _hilo_history {
118 hilo_access mt;
119 hilo_access mf;
120 hilo_access op;
121 } hilo_history;
122
123
124
125
126 /* Integer ALU operations: */
127
128 #include "sim-alu.h"
129
130 #define ALU32_END(ANS) \
131 if (ALU32_HAD_OVERFLOW) \
132 SignalExceptionIntegerOverflow (); \
133 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
134
135
136 #define ALU64_END(ANS) \
137 if (ALU64_HAD_OVERFLOW) \
138 SignalExceptionIntegerOverflow (); \
139 (ANS) = ALU64_OVERFLOW_RESULT;
140
141
142
143
144
145 /* The following is probably not used for MIPS IV onwards: */
146 /* Slots for delayed register updates. For the moment we just have a
147 fixed number of slots (rather than a more generic, dynamic
148 system). This keeps the simulator fast. However, we only allow
149 for the register update to be delayed for a single instruction
150 cycle. */
151 #define PSLOTS (8) /* Maximum number of instruction cycles */
152
153 typedef struct _pending_write_queue {
154 int in;
155 int out;
156 int total;
157 int slot_delay[PSLOTS];
158 int slot_size[PSLOTS];
159 int slot_bit[PSLOTS];
160 void *slot_dest[PSLOTS];
161 unsigned64 slot_value[PSLOTS];
162 } pending_write_queue;
163
164 #ifndef PENDING_TRACE
165 #define PENDING_TRACE 0
166 #endif
167 #define PENDING_IN ((CPU)->pending.in)
168 #define PENDING_OUT ((CPU)->pending.out)
169 #define PENDING_TOTAL ((CPU)->pending.total)
170 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
171 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
172 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
173 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
174 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
175
176 /* Invalidate the pending write queue, all pending writes are
177 discarded. */
178
179 #define PENDING_INVALIDATE() \
180 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
181
182 /* Schedule a write to DEST for N cycles time. For 64 bit
183 destinations, schedule two writes. For floating point registers,
184 the caller should schedule a write to both the dest register and
185 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
186 is updated. */
187
188 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
189 do { \
190 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
191 sim_engine_abort (SD, CPU, cia, \
192 "PENDING_SCHED - buffer overflow\n"); \
193 if (PENDING_TRACE) \
194 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
195 (unsigned long) cia, (unsigned long) &(DEST), \
196 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
197 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
198 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
199 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
200 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
201 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
202 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
203 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
204 PENDING_TOTAL += 1; \
205 } while (0)
206
207 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
208 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
209
210 #define PENDING_TICK() pending_tick (SD, CPU, cia)
211
212 #define PENDING_FLUSH() abort () /* think about this one */
213 #define PENDING_FP() abort () /* think about this one */
214
215 /* For backward compatibility */
216 #define PENDING_FILL(R,VAL) \
217 do { \
218 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \
219 { \
220 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
221 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
222 } \
223 else \
224 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
225 } while (0)
226
227
228 enum float_operation
229 {
230 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
231 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
232 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
233 };
234
235
236 /* The internal representation of an MDMX accumulator.
237 Note that 24 and 48 bit accumulator elements are represented in
238 32 or 64 bits. Since the accumulators are 2's complement with
239 overflow suppressed, high-order bits can be ignored in most contexts. */
240
241 typedef signed32 signed24;
242 typedef signed64 signed48;
243
244 typedef union {
245 signed24 ob[8];
246 signed48 qh[4];
247 } MDMX_accumulator;
248
249
250 /* Conventional system arguments. */
251 #define SIM_STATE sim_cpu *cpu, address_word cia
252 #define SIM_ARGS CPU, cia
253
254 struct _sim_cpu {
255
256
257 /* The following are internal simulator state variables: */
258 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
259 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
260 address_word dspc; /* delay-slot PC */
261 #define DSPC ((CPU)->dspc)
262
263 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
264 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
265
266
267 /* State of the simulator */
268 unsigned int state;
269 unsigned int dsstate;
270 #define STATE ((CPU)->state)
271 #define DSSTATE ((CPU)->dsstate)
272
273 /* Flags in the "state" variable: */
274 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
275 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
276 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
277 #define simPCOC0 (1 << 17) /* COC[1] from current */
278 #define simPCOC1 (1 << 18) /* COC[1] from previous */
279 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
280 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
281 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
282 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
283
284 #ifndef ENGINE_ISSUE_PREFIX_HOOK
285 #define ENGINE_ISSUE_PREFIX_HOOK() \
286 { \
287 /* Perform any pending writes */ \
288 PENDING_TICK(); \
289 /* Set previous flag, depending on current: */ \
290 if (STATE & simPCOC0) \
291 STATE |= simPCOC1; \
292 else \
293 STATE &= ~simPCOC1; \
294 /* and update the current value: */ \
295 if (GETFCC(0)) \
296 STATE |= simPCOC0; \
297 else \
298 STATE &= ~simPCOC0; \
299 }
300 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
301
302
303 /* This is nasty, since we have to rely on matching the register
304 numbers used by GDB. Unfortunately, depending on the MIPS target
305 GDB uses different register numbers. We cannot just include the
306 relevant "gdb/tm.h" link, since GDB may not be configured before
307 the sim world, and also the GDB header file requires too much other
308 state. */
309
310 #ifndef TM_MIPS_H
311 #define LAST_EMBED_REGNUM (89)
312 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
313
314 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */
315 #define FCRCS_REGNUM 70 /* FP control/status */
316 #define FCRIR_REGNUM 71 /* FP implementation/revision */
317 #endif
318
319
320 /* To keep this default simulator simple, and fast, we use a direct
321 vector of registers. The internal simulator engine then uses
322 manifests to access the correct slot. */
323
324 unsigned_word registers[LAST_EMBED_REGNUM + 1];
325
326 int register_widths[NUM_REGS];
327 #define REGISTERS ((CPU)->registers)
328
329 #define GPR (&REGISTERS[0])
330 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
331
332 #define LO (REGISTERS[33])
333 #define HI (REGISTERS[34])
334 #define PCIDX 37
335 #define PC (REGISTERS[PCIDX])
336 #define CAUSE (REGISTERS[36])
337 #define SRIDX (32)
338 #define SR (REGISTERS[SRIDX]) /* CPU status register */
339 #define FCR0IDX (71)
340 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
341 #define FCR31IDX (70)
342 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
343 #define FCSR (FCR31)
344 #define Debug (REGISTERS[86])
345 #define DEPC (REGISTERS[87])
346 #define EPC (REGISTERS[88])
347
348 /* All internal state modified by signal_exception() that may need to be
349 rolled back for passing moment-of-exception image back to gdb. */
350 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
351 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
352 int exc_suspended;
353
354 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
355 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
356 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
357
358 unsigned_word c0_config_reg;
359 #define C0_CONFIG ((CPU)->c0_config_reg)
360
361 /* The following are pseudonyms for standard registers */
362 #define ZERO (REGISTERS[0])
363 #define V0 (REGISTERS[2])
364 #define A0 (REGISTERS[4])
365 #define A1 (REGISTERS[5])
366 #define A2 (REGISTERS[6])
367 #define A3 (REGISTERS[7])
368 #define T8IDX 24
369 #define T8 (REGISTERS[T8IDX])
370 #define SPIDX 29
371 #define SP (REGISTERS[SPIDX])
372 #define RAIDX 31
373 #define RA (REGISTERS[RAIDX])
374
375 /* While space is allocated in the main registers arrray for some of
376 the COP0 registers, that space isn't sufficient. Unknown COP0
377 registers overflow into the array below */
378
379 #define NR_COP0_GPR 32
380 unsigned_word cop0_gpr[NR_COP0_GPR];
381 #define COP0_GPR ((CPU)->cop0_gpr)
382 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
383
384 /* While space is allocated for the floating point registers in the
385 main registers array, they are stored separatly. This is because
386 their size may not necessarily match the size of either the
387 general-purpose or system specific registers. */
388 #define NR_FGR (32)
389 #define FGR_BASE FP0_REGNUM
390 fp_word fgr[NR_FGR];
391 #define FGR ((CPU)->fgr)
392
393 /* Keep the current format state for each register: */
394 FP_formats fpr_state[32];
395 #define FPR_STATE ((CPU)->fpr_state)
396
397 pending_write_queue pending;
398
399 /* The MDMX accumulator (used only for MDMX ASE). */
400 MDMX_accumulator acc;
401 #define ACC ((CPU)->acc)
402
403 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
404 read-write instructions. It is set when a linked load occurs. It
405 is tested and cleared by the conditional store. It is cleared
406 (during other CPU operations) when a store to the location would
407 no longer be atomic. In particular, it is cleared by exception
408 return instructions. */
409 int llbit;
410 #define LLBIT ((CPU)->llbit)
411
412
413 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
414 corruptions caused by using the HI or LO register too close to a
415 following operation is spotted. See mips.igen for more details. */
416
417 hilo_history hi_history;
418 #define HIHISTORY (&(CPU)->hi_history)
419 hilo_history lo_history;
420 #define LOHISTORY (&(CPU)->lo_history)
421
422 #define check_branch_bug()
423 #define mark_branch_bug(TARGET)
424
425
426
427 sim_cpu_base base;
428 };
429
430
431 /* MIPS specific simulator watch config */
432
433 void watch_options_install PARAMS ((SIM_DESC sd));
434
435 struct swatch {
436 sim_event *pc;
437 sim_event *clock;
438 sim_event *cycles;
439 };
440
441
442 /* FIXME: At present much of the simulator is still static */
443 struct sim_state {
444
445 struct swatch watch;
446
447 sim_cpu cpu[MAX_NR_PROCESSORS];
448 #if (WITH_SMP)
449 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
450 #else
451 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
452 #endif
453
454
455 sim_state_base base;
456 };
457
458
459
460 /* Status information: */
461
462 /* TODO : these should be the bitmasks for these bits within the
463 status register. At the moment the following are VR4300
464 bit-positions: */
465 #define status_KSU_mask (0x18) /* mask for KSU bits */
466 #define status_KSU_shift (3) /* shift for field */
467 #define ksu_kernel (0x0)
468 #define ksu_supervisor (0x1)
469 #define ksu_user (0x2)
470 #define ksu_unknown (0x3)
471
472 #define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
473
474 #define status_IE (1 << 0) /* Interrupt enable */
475 #define status_EIE (1 << 16) /* Enable Interrupt Enable */
476 #define status_EXL (1 << 1) /* Exception level */
477 #define status_RE (1 << 25) /* Reverse Endian in user mode */
478 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
479 #define status_SR (1 << 20) /* soft reset or NMI */
480 #define status_BEV (1 << 22) /* Location of general exception vectors */
481 #define status_TS (1 << 21) /* TLB shutdown has occurred */
482 #define status_ERL (1 << 2) /* Error level */
483 #define status_IM7 (1 << 15) /* Timer Interrupt Mask */
484 #define status_RP (1 << 27) /* Reduced Power mode */
485
486 /* Specializations for TX39 family */
487 #define status_IEc (1 << 0) /* Interrupt enable (current) */
488 #define status_KUc (1 << 1) /* Kernel/User mode */
489 #define status_IEp (1 << 2) /* Interrupt enable (previous) */
490 #define status_KUp (1 << 3) /* Kernel/User mode */
491 #define status_IEo (1 << 4) /* Interrupt enable (old) */
492 #define status_KUo (1 << 5) /* Kernel/User mode */
493 #define status_IM_mask (0xff) /* Interrupt mask */
494 #define status_IM_shift (8)
495 #define status_NMI (1 << 20) /* NMI */
496 #define status_NMI (1 << 20) /* NMI */
497
498 /* Status bits used by MIPS32/MIPS64. */
499 #define status_UX (1 << 5) /* 64-bit user addrs */
500 #define status_SX (1 << 6) /* 64-bit supervisor addrs */
501 #define status_KX (1 << 7) /* 64-bit kernel addrs */
502 #define status_TS (1 << 21) /* TLB shutdown has occurred */
503 #define status_PX (1 << 23) /* Enable 64 bit operations */
504 #define status_MX (1 << 24) /* Enable MDMX resources */
505 #define status_CU0 (1 << 28) /* Coprocessor 0 usable */
506 #define status_CU1 (1 << 29) /* Coprocessor 1 usable */
507 #define status_CU2 (1 << 30) /* Coprocessor 2 usable */
508 #define status_CU3 (1 << 31) /* Coprocessor 3 usable */
509 /* Bits reserved for implementations: */
510 #define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
511
512 #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
513 #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
514 #define cause_CE_mask 0x30000000 /* Coprocessor exception */
515 #define cause_CE_shift 28
516 #define cause_EXC2_mask 0x00070000
517 #define cause_EXC2_shift 16
518 #define cause_IP7 (1 << 15) /* Interrupt pending */
519 #define cause_SIOP (1 << 12) /* SIO pending */
520 #define cause_IP3 (1 << 11) /* Int 0 pending */
521 #define cause_IP2 (1 << 10) /* Int 1 pending */
522
523 #define cause_EXC_mask (0x1c) /* Exception code */
524 #define cause_EXC_shift (2)
525
526 #define cause_SW0 (1 << 8) /* Software interrupt 0 */
527 #define cause_SW1 (1 << 9) /* Software interrupt 1 */
528 #define cause_IP_mask (0x3f) /* Interrupt pending field */
529 #define cause_IP_shift (10)
530
531 #define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
532 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
533
534
535 /* NOTE: We keep the following status flags as bit values (1 for true,
536 0 for false). This allows them to be used in binary boolean
537 operations without worrying about what exactly the non-zero true
538 value is. */
539
540 /* UserMode */
541 #ifdef SUBTARGET_R3900
542 #define UserMode ((SR & status_KUc) ? 1 : 0)
543 #else
544 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
545 #endif /* SUBTARGET_R3900 */
546
547 /* BigEndianMem */
548 /* Hardware configuration. Affects endianness of LoadMemory and
549 StoreMemory and the endianness of Kernel and Supervisor mode
550 execution. The value is 0 for little-endian; 1 for big-endian. */
551 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
552 /*(state & simBE) ? 1 : 0)*/
553
554 /* ReverseEndian */
555 /* This mode is selected if in User mode with the RE bit being set in
556 SR (Status Register). It reverses the endianness of load and store
557 instructions. */
558 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
559
560 /* BigEndianCPU */
561 /* The endianness for load and store instructions (0=little;1=big). In
562 User mode this endianness may be switched by setting the state_RE
563 bit in the SR register. Thus, BigEndianCPU may be computed as
564 (BigEndianMem EOR ReverseEndian). */
565 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
566
567
568
569 /* Exceptions: */
570
571 /* NOTE: These numbers depend on the processor architecture being
572 simulated: */
573 enum ExceptionCause {
574 Interrupt = 0,
575 TLBModification = 1,
576 TLBLoad = 2,
577 TLBStore = 3,
578 AddressLoad = 4,
579 AddressStore = 5,
580 InstructionFetch = 6,
581 DataReference = 7,
582 SystemCall = 8,
583 BreakPoint = 9,
584 ReservedInstruction = 10,
585 CoProcessorUnusable = 11,
586 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
587 Trap = 13,
588 FPE = 15,
589 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
590 MDMX = 22,
591 Watch = 23,
592 MCheck = 24,
593 CacheErr = 30,
594 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
595
596
597 /* The following exception code is actually private to the simulator
598 world. It is *NOT* a processor feature, and is used to signal
599 run-time errors in the simulator. */
600 SimulatorFault = 0xFFFFFFFF
601 };
602
603 #define TLB_REFILL (0)
604 #define TLB_INVALID (1)
605
606
607 /* The following break instructions are reserved for use by the
608 simulator. The first is used to halt the simulation. The second
609 is used by gdb for break-points. NOTE: Care must be taken, since
610 this value may be used in later revisions of the MIPS ISA. */
611 #define HALT_INSTRUCTION_MASK (0x03FFFFC0)
612
613 #define HALT_INSTRUCTION (0x03ff000d)
614 #define HALT_INSTRUCTION2 (0x0000ffcd)
615
616
617 #define BREAKPOINT_INSTRUCTION (0x0005000d)
618 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
619
620
621
622 void interrupt_event (SIM_DESC sd, void *data);
623
624 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
625 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
626 #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
627 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
628 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
629 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
630 #define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
631 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
632 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
633 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
634 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
635 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
636 #define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
637 #define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
638 #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
639 #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
640 #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
641 #define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
642 #define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
643 #define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
644 #define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
645
646 /* Co-processor accesses */
647
648 /* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
649 #define COP_Usable(coproc_num) (coproc_num == 1)
650
651 void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
652 void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
653 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
654 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
655
656 #define COP_LW(coproc_num,coproc_reg,memword) \
657 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
658 #define COP_LD(coproc_num,coproc_reg,memword) \
659 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
660 #define COP_SW(coproc_num,coproc_reg) \
661 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
662 #define COP_SD(coproc_num,coproc_reg) \
663 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
664
665
666 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
667 #define DecodeCoproc(instruction) \
668 decode_coproc (SD, CPU, cia, (instruction))
669
670 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
671
672
673 /* FPR access. */
674 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
675 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
676 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
677 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
678 unsigned64 ps_lower (SIM_STATE, unsigned64 op);
679 #define PSLower(op) ps_lower (SIM_ARGS, op)
680 unsigned64 ps_upper (SIM_STATE, unsigned64 op);
681 #define PSUpper(op) ps_upper (SIM_ARGS, op)
682 unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
683 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
684
685
686 /* FCR access. */
687 unsigned_word value_fcr (SIM_STATE, int fcr);
688 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
689 void store_fcr (SIM_STATE, int fcr, unsigned_word value);
690 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
691 void test_fcsr (SIM_STATE);
692 #define TestFCSR() test_fcsr (SIM_ARGS)
693
694
695 /* FPU operations. */
696 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
697 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
698 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
699 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
700 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
701 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
702 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
703 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
704 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
705 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
706 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
707 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
708 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
709 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
710 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
711 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
712 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
713 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
714 unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
715 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
716 unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
717 unsigned64 op3, FP_formats fmt);
718 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
719 unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
720 unsigned64 op3, FP_formats fmt);
721 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
722 unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
723 unsigned64 op3, FP_formats fmt);
724 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
725 unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
726 unsigned64 op3, FP_formats fmt);
727 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
728 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
729 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
730 unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
731 FP_formats to);
732 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
733
734
735 /* MDMX access. */
736
737 typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
738 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
739 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
740
741 #define fmt_mdmx fmt_uninterpreted
742
743 #define MX_VECT_AND (0)
744 #define MX_VECT_NOR (1)
745 #define MX_VECT_OR (2)
746 #define MX_VECT_XOR (3)
747 #define MX_VECT_SLL (4)
748 #define MX_VECT_SRL (5)
749 #define MX_VECT_ADD (6)
750 #define MX_VECT_SUB (7)
751 #define MX_VECT_MIN (8)
752 #define MX_VECT_MAX (9)
753 #define MX_VECT_MUL (10)
754 #define MX_VECT_MSGN (11)
755 #define MX_VECT_SRA (12)
756 #define MX_VECT_ABSD (13) /* SB-1 only. */
757 #define MX_VECT_AVG (14) /* SB-1 only. */
758
759 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
760 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
761 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
762 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
763 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
764 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
765 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
766 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
767 #define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
768 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
769 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
770 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
771 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
772 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
773 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
774 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
775
776 #define MX_C_EQ 0x1
777 #define MX_C_LT 0x4
778
779 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
780 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
781
782 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
783 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
784
785 #define MX_VECT_ADDA (0)
786 #define MX_VECT_ADDL (1)
787 #define MX_VECT_MULA (2)
788 #define MX_VECT_MULL (3)
789 #define MX_VECT_MULS (4)
790 #define MX_VECT_MULSL (5)
791 #define MX_VECT_SUBA (6)
792 #define MX_VECT_SUBL (7)
793 #define MX_VECT_ABSDA (8) /* SB-1 only. */
794
795 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
796 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
797 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
798 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
799 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
800 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
801 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
802 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
803 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
804 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
805
806 #define MX_FMT_OB (0)
807 #define MX_FMT_QH (1)
808
809 /* The following codes chosen to indicate the units of shift. */
810 #define MX_RAC_L (0)
811 #define MX_RAC_M (1)
812 #define MX_RAC_H (2)
813
814 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
815 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
816
817 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
818 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
819 void mdmx_wach (SIM_STATE, int, unsigned64);
820 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
821
822 #define MX_RND_AS (0)
823 #define MX_RND_AU (1)
824 #define MX_RND_ES (2)
825 #define MX_RND_EU (3)
826 #define MX_RND_ZS (4)
827 #define MX_RND_ZU (5)
828
829 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
830 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
831 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
832 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
833 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
834 #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
835 #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
836
837 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
838 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
839
840
841
842 /* Memory accesses */
843
844 /* The following are generic to all versions of the MIPS architecture
845 to date: */
846
847 /* Memory Access Types (for CCA): */
848 #define Uncached (0)
849 #define CachedNoncoherent (1)
850 #define CachedCoherent (2)
851 #define Cached (3)
852
853 #define isINSTRUCTION (1 == 0) /* FALSE */
854 #define isDATA (1 == 1) /* TRUE */
855 #define isLOAD (1 == 0) /* FALSE */
856 #define isSTORE (1 == 1) /* TRUE */
857 #define isREAL (1 == 0) /* FALSE */
858 #define isRAW (1 == 1) /* TRUE */
859 /* The parameter HOST (isTARGET / isHOST) is ignored */
860 #define isTARGET (1 == 0) /* FALSE */
861 /* #define isHOST (1 == 1) TRUE */
862
863 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
864 is the number of bytes minus 1. */
865 #define AccessLength_BYTE (0)
866 #define AccessLength_HALFWORD (1)
867 #define AccessLength_TRIPLEBYTE (2)
868 #define AccessLength_WORD (3)
869 #define AccessLength_QUINTIBYTE (4)
870 #define AccessLength_SEXTIBYTE (5)
871 #define AccessLength_SEPTIBYTE (6)
872 #define AccessLength_DOUBLEWORD (7)
873 #define AccessLength_QUADWORD (15)
874
875 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
876 ? AccessLength_DOUBLEWORD /*7*/ \
877 : AccessLength_WORD /*3*/)
878 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
879
880
881 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
882 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
883 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
884
885 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
886 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
887 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
888
889 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
890 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
891 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
892
893 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
894 #define CacheOp(op,pAddr,vAddr,instruction) \
895 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
896
897 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
898 #define SyncOperation(stype) \
899 sync_operation (SD, CPU, cia, (stype))
900
901 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
902 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
903 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
904
905 void unpredictable_action (sim_cpu *cpu, address_word cia);
906 #define NotWordValue(val) not_word_value (SD_, (val))
907 #define Unpredictable() unpredictable (SD_)
908 #define UnpredictableResult() /* For now, do nothing. */
909
910 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
911 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
912 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
913 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
914 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
915
916 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
917 extern FILE *tracefh;
918
919 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
920 extern SIM_CORE_SIGNAL_FN mips_core_signal;
921
922 char* pr_addr PARAMS ((SIM_ADDR addr));
923 char* pr_uword64 PARAMS ((uword64 addr));
924
925
926 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
927
928 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
929 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
930 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
931
932
933 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
934 #include "sim-main.c"
935 #endif
936
937 #endif
GDB Binutils - Deliverables
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