sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997-2015 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef SIM_MAIN_H
  21 #define SIM_MAIN_H
  22
  23 /* This simulator doesn't cache the Current Instruction Address */
  24 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  25 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  26
  27 /* hobble some common features for moment */
  28 #define WITH_WATCHPOINTS 1
  29 #define WITH_MODULO_MEMORY 1
  30
  31
  32 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  33 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 typedef struct _sim_cpu SIM_CPU;
  40
  41 #include "sim-base.h"
  42 #include "bfd.h"
  43
  44 /* Deprecated macros and types for manipulating 64bit values.  Use
  45    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  46
  47 typedef signed64 word64;
  48 typedef unsigned64 uword64;
  49
  50 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  51 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  52 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  53 #define SET64HI(t)      (((uword64)(t))<<32)
  54 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  55 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  56
  57 /* Check if a value will fit within a halfword: */
  58 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  59
  60
  61
  62 /* Floating-point operations: */
  63
  64 #include "sim-fpu.h"
  65 #include "cp1.h"
  66
  67 /* FPU registers must be one of the following types. All other values
  68    are reserved (and undefined). */
  69 typedef enum {
  70  fmt_single  = 0,
  71  fmt_double  = 1,
  72  fmt_word    = 4,
  73  fmt_long    = 5,
  74  fmt_ps      = 6,
  75  /* The following are well outside the normal acceptable format
  76     range, and are used in the register status vector. */
  77  fmt_unknown       = 0x10000000,
  78  fmt_uninterpreted = 0x20000000,
  79  fmt_uninterpreted_32 = 0x40000000,
  80  fmt_uninterpreted_64 = 0x80000000U,
  81 } FP_formats;
  82
  83 /* For paired word (pw) operations, the opcode representation is fmt_word,
  84    but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long.  */
  85 #define fmt_pw fmt_long
  86
  87 /* This should be the COC1 value at the start of the preceding
  88    instruction: */
  89 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
  90
  91 #ifdef TARGET_ENABLE_FR
  92 /* FIXME: this should be enabled for all targets, but needs testing first. */
  93 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
  94    ? ((SR & status_FR) ? 64 : 32) \
  95    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
  96 #else
  97 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
  98 #endif
  99
 100
 101
 102
 103
 104 /* HI/LO register accesses */
 105
 106 /* For some MIPS targets, the HI/LO registers have certain timing
 107    restrictions in that, for instance, a read of a HI register must be
 108    separated by at least three instructions from a preceeding read.
 109
 110    The struct below is used to record the last access by each of A MT,
 111    MF or other OP instruction to a HI/LO register.  See mips.igen for
 112    more details. */
 113
 114 typedef struct _hilo_access {
 115   signed64 timestamp;
 116   address_word cia;
 117 } hilo_access;
 118
 119 typedef struct _hilo_history {
 120   hilo_access mt;
 121   hilo_access mf;
 122   hilo_access op;
 123 } hilo_history;
 124
 125
 126
 127
 128 /* Integer ALU operations: */
 129
 130 #include "sim-alu.h"
 131
 132 #define ALU32_END(ANS) \
 133   if (ALU32_HAD_OVERFLOW) \
 134     SignalExceptionIntegerOverflow (); \
 135   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 136
 137
 138 #define ALU64_END(ANS) \
 139   if (ALU64_HAD_OVERFLOW) \
 140     SignalExceptionIntegerOverflow (); \
 141   (ANS) = ALU64_OVERFLOW_RESULT;
 142
 143
 144
 145
 146
 147 /* The following is probably not used for MIPS IV onwards: */
 148 /* Slots for delayed register updates. For the moment we just have a
 149    fixed number of slots (rather than a more generic, dynamic
 150    system). This keeps the simulator fast. However, we only allow
 151    for the register update to be delayed for a single instruction
 152    cycle. */
 153 #define PSLOTS (8) /* Maximum number of instruction cycles */
 154
 155 typedef struct _pending_write_queue {
 156   int in;
 157   int out;
 158   int total;
 159   int slot_delay[PSLOTS];
 160   int slot_size[PSLOTS];
 161   int slot_bit[PSLOTS];
 162   void *slot_dest[PSLOTS];
 163   unsigned64 slot_value[PSLOTS];
 164 } pending_write_queue;
 165
 166 #ifndef PENDING_TRACE
 167 #define PENDING_TRACE 0
 168 #endif
 169 #define PENDING_IN ((CPU)->pending.in)
 170 #define PENDING_OUT ((CPU)->pending.out)
 171 #define PENDING_TOTAL ((CPU)->pending.total)
 172 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 173 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 174 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 175 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 176 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 177
 178 /* Invalidate the pending write queue, all pending writes are
 179    discarded. */
 180
 181 #define PENDING_INVALIDATE() \
 182 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 183
 184 /* Schedule a write to DEST for N cycles time.  For 64 bit
 185    destinations, schedule two writes.  For floating point registers,
 186    the caller should schedule a write to both the dest register and
 187    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 188    is updated. */
 189
 190 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 191   do {                                                                  \
 192     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 193       sim_engine_abort (SD, CPU, cia,                                   \
 194                         "PENDING_SCHED - buffer overflow\n");           \
 195     if (PENDING_TRACE)                                                  \
 196       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 197                       (unsigned long) cia, (unsigned long) &(DEST),     \
 198                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 199                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 200     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 201     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 202     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 203     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 204     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 205     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 206     PENDING_TOTAL += 1;                                                 \
 207   } while (0)
 208
 209 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 210 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 211
 212 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 213
 214 #define PENDING_FLUSH() abort () /* think about this one */
 215 #define PENDING_FP() abort () /* think about this one */
 216
 217 /* For backward compatibility */
 218 #define PENDING_FILL(R,VAL)                                             \
 219 do {                                                                    \
 220   if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR)                       \
 221     {                                                                   \
 222       PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1);                   \
 223       PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
 224     }                                                                   \
 225   else                                                                  \
 226     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 227 } while (0)
 228
 229
 230 enum float_operation
 231   {
 232     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 233     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 234     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 235   };
 236
 237
 238 /* The internal representation of an MDMX accumulator.
 239    Note that 24 and 48 bit accumulator elements are represented in
 240    32 or 64 bits.  Since the accumulators are 2's complement with
 241    overflow suppressed, high-order bits can be ignored in most contexts.  */
 242
 243 typedef signed32 signed24;
 244 typedef signed64 signed48;
 245
 246 typedef union {
 247   signed24  ob[8];
 248   signed48  qh[4];
 249 } MDMX_accumulator;
 250
 251
 252 /* Conventional system arguments.  */
 253 #define SIM_STATE  sim_cpu *cpu, address_word cia
 254 #define SIM_ARGS   CPU, cia
 255
 256 struct _sim_cpu {
 257
 258
 259   /* The following are internal simulator state variables: */
 260 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 261 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 262   address_word dspc;  /* delay-slot PC */
 263 #define DSPC ((CPU)->dspc)
 264
 265 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 266 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 267
 268
 269   /* State of the simulator */
 270   unsigned int state;
 271   unsigned int dsstate;
 272 #define STATE ((CPU)->state)
 273 #define DSSTATE ((CPU)->dsstate)
 274
 275 /* Flags in the "state" variable: */
 276 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 277 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 278 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 279 #define simPCOC0        (1 << 17) /* COC[1] from current */
 280 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 281 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 282 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 283 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 284 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 285
 286 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 287 #define ENGINE_ISSUE_PREFIX_HOOK() \
 288   { \
 289     /* Perform any pending writes */ \
 290     PENDING_TICK(); \
 291     /* Set previous flag, depending on current: */ \
 292     if (STATE & simPCOC0) \
 293      STATE |= simPCOC1; \
 294     else \
 295      STATE &= ~simPCOC1; \
 296     /* and update the current value: */ \
 297     if (GETFCC(0)) \
 298      STATE |= simPCOC0; \
 299     else \
 300      STATE &= ~simPCOC0; \
 301   }
 302 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 303
 304
 305 /* This is nasty, since we have to rely on matching the register
 306    numbers used by GDB. Unfortunately, depending on the MIPS target
 307    GDB uses different register numbers. We cannot just include the
 308    relevant "gdb/tm.h" link, since GDB may not be configured before
 309    the sim world, and also the GDB header file requires too much other
 310    state. */
 311
 312 #ifndef TM_MIPS_H
 313 #define LAST_EMBED_REGNUM (96)
 314 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 315
 316 #define FP0_REGNUM 38           /* Floating point register 0 (single float) */
 317 #define FCRCS_REGNUM 70         /* FP control/status */
 318 #define FCRIR_REGNUM 71         /* FP implementation/revision */
 319 #endif
 320
 321
 322 /* To keep this default simulator simple, and fast, we use a direct
 323    vector of registers. The internal simulator engine then uses
 324    manifests to access the correct slot. */
 325
 326   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 327
 328   int register_widths[NUM_REGS];
 329 #define REGISTERS       ((CPU)->registers)
 330
 331 #define GPR     (&REGISTERS[0])
 332 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 333
 334 #define LO      (REGISTERS[33])
 335 #define HI      (REGISTERS[34])
 336 #define PCIDX   37
 337 #define PC      (REGISTERS[PCIDX])
 338 #define CAUSE   (REGISTERS[36])
 339 #define SRIDX   (32)
 340 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 341 #define FCR0IDX  (71)
 342 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 343 #define FCR31IDX (70)
 344 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 345 #define FCSR    (FCR31)
 346 #define Debug   (REGISTERS[86])
 347 #define DEPC    (REGISTERS[87])
 348 #define EPC     (REGISTERS[88])
 349 #define ACX     (REGISTERS[89])
 350
 351 #define AC0LOIDX        (33)    /* Must be the same register as LO */
 352 #define AC0HIIDX        (34)    /* Must be the same register as HI */
 353 #define AC1LOIDX        (90)
 354 #define AC1HIIDX        (91)
 355 #define AC2LOIDX        (92)
 356 #define AC2HIIDX        (93)
 357 #define AC3LOIDX        (94)
 358 #define AC3HIIDX        (95)
 359
 360 #define DSPLO(N)        (REGISTERS[DSPLO_REGNUM[N]])
 361 #define DSPHI(N)        (REGISTERS[DSPHI_REGNUM[N]])
 362
 363 #define DSPCRIDX        (96)    /* DSP control register */
 364 #define DSPCR           (REGISTERS[DSPCRIDX])
 365
 366 #define DSPCR_POS_SHIFT         (0)
 367 #define DSPCR_POS_MASK          (0x3f)
 368 #define DSPCR_POS_SMASK         (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
 369
 370 #define DSPCR_SCOUNT_SHIFT      (7)
 371 #define DSPCR_SCOUNT_MASK       (0x3f)
 372 #define DSPCR_SCOUNT_SMASK      (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
 373
 374 #define DSPCR_CARRY_SHIFT       (13)
 375 #define DSPCR_CARRY_MASK        (1)
 376 #define DSPCR_CARRY_SMASK       (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
 377 #define DSPCR_CARRY             (1 << DSPCR_CARRY_SHIFT)
 378
 379 #define DSPCR_EFI_SHIFT         (14)
 380 #define DSPCR_EFI_MASK          (1)
 381 #define DSPCR_EFI_SMASK         (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
 382 #define DSPCR_EFI               (1 << DSPCR_EFI_MASK)
 383
 384 #define DSPCR_OUFLAG_SHIFT      (16)
 385 #define DSPCR_OUFLAG_MASK       (0xff)
 386 #define DSPCR_OUFLAG_SMASK      (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
 387 #define DSPCR_OUFLAG4           (1 << (DSPCR_OUFLAG_SHIFT + 4))
 388 #define DSPCR_OUFLAG5           (1 << (DSPCR_OUFLAG_SHIFT + 5))
 389 #define DSPCR_OUFLAG6           (1 << (DSPCR_OUFLAG_SHIFT + 6))
 390 #define DSPCR_OUFLAG7           (1 << (DSPCR_OUFLAG_SHIFT + 7))
 391
 392 #define DSPCR_CCOND_SHIFT       (24)
 393 #define DSPCR_CCOND_MASK        (0xf)
 394 #define DSPCR_CCOND_SMASK       (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
 395
 396   /* All internal state modified by signal_exception() that may need to be
 397      rolled back for passing moment-of-exception image back to gdb. */
 398   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 399   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 400   int exc_suspended;
 401
 402 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 403 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 404 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 405
 406   unsigned_word c0_config_reg;
 407 #define C0_CONFIG ((CPU)->c0_config_reg)
 408
 409 /* The following are pseudonyms for standard registers */
 410 #define ZERO    (REGISTERS[0])
 411 #define V0      (REGISTERS[2])
 412 #define A0      (REGISTERS[4])
 413 #define A1      (REGISTERS[5])
 414 #define A2      (REGISTERS[6])
 415 #define A3      (REGISTERS[7])
 416 #define T8IDX   24
 417 #define T8      (REGISTERS[T8IDX])
 418 #define SPIDX   29
 419 #define SP      (REGISTERS[SPIDX])
 420 #define RAIDX   31
 421 #define RA      (REGISTERS[RAIDX])
 422
 423   /* While space is allocated in the main registers arrray for some of
 424      the COP0 registers, that space isn't sufficient.  Unknown COP0
 425      registers overflow into the array below */
 426
 427 #define NR_COP0_GPR     32
 428   unsigned_word cop0_gpr[NR_COP0_GPR];
 429 #define COP0_GPR        ((CPU)->cop0_gpr)
 430 #define COP0_BADVADDR   (COP0_GPR[8])
 431
 432   /* While space is allocated for the floating point registers in the
 433      main registers array, they are stored separatly.  This is because
 434      their size may not necessarily match the size of either the
 435      general-purpose or system specific registers.  */
 436 #define NR_FGR    (32)
 437 #define FGR_BASE  FP0_REGNUM
 438   fp_word fgr[NR_FGR];
 439 #define FGR       ((CPU)->fgr)
 440
 441   /* Keep the current format state for each register: */
 442   FP_formats fpr_state[32];
 443 #define FPR_STATE ((CPU)->fpr_state)
 444
 445   pending_write_queue pending;
 446
 447   /* The MDMX accumulator (used only for MDMX ASE).  */
 448   MDMX_accumulator acc;
 449 #define ACC             ((CPU)->acc)
 450
 451   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 452      read-write instructions. It is set when a linked load occurs. It
 453      is tested and cleared by the conditional store. It is cleared
 454      (during other CPU operations) when a store to the location would
 455      no longer be atomic. In particular, it is cleared by exception
 456      return instructions. */
 457   int llbit;
 458 #define LLBIT ((CPU)->llbit)
 459
 460
 461 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 462    corruptions caused by using the HI or LO register too close to a
 463    following operation is spotted. See mips.igen for more details. */
 464
 465   hilo_history hi_history;
 466 #define HIHISTORY (&(CPU)->hi_history)
 467   hilo_history lo_history;
 468 #define LOHISTORY (&(CPU)->lo_history)
 469
 470
 471   sim_cpu_base base;
 472 };
 473
 474
 475 /* MIPS specific simulator watch config */
 476
 477 void watch_options_install (SIM_DESC sd);
 478
 479 struct swatch {
 480   sim_event *pc;
 481   sim_event *clock;
 482   sim_event *cycles;
 483 };
 484
 485
 486 /* FIXME: At present much of the simulator is still static */
 487 struct sim_state {
 488
 489   struct swatch watch;
 490
 491   sim_cpu *cpu[MAX_NR_PROCESSORS];
 492
 493   sim_state_base base;
 494 };
 495
 496
 497
 498 /* Status information: */
 499
 500 /* TODO : these should be the bitmasks for these bits within the
 501    status register. At the moment the following are VR4300
 502    bit-positions: */
 503 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 504 #define status_KSU_shift (3)            /* shift for field */
 505 #define ksu_kernel       (0x0)
 506 #define ksu_supervisor   (0x1)
 507 #define ksu_user         (0x2)
 508 #define ksu_unknown      (0x3)
 509
 510 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 511
 512 #define status_IE        (1 <<  0)      /* Interrupt enable */
 513 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 514 #define status_EXL       (1 <<  1)      /* Exception level */
 515 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 516 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 517 #define status_SR        (1 << 20)      /* soft reset or NMI */
 518 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 519 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 520 #define status_ERL       (1 <<  2)      /* Error level */
 521 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 522 #define status_RP        (1 << 27)      /* Reduced Power mode */
 523
 524 /* Specializations for TX39 family */
 525 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 526 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 527 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 528 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 529 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 530 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 531 #define status_IM_mask   (0xff)         /* Interrupt mask */
 532 #define status_IM_shift  (8)
 533 #define status_NMI       (1 << 20)      /* NMI */
 534 #define status_NMI       (1 << 20)      /* NMI */
 535
 536 /* Status bits used by MIPS32/MIPS64.  */
 537 #define status_UX        (1 <<  5)      /* 64-bit user addrs */
 538 #define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
 539 #define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
 540 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 541 #define status_PX        (1 << 23)      /* Enable 64 bit operations */
 542 #define status_MX        (1 << 24)      /* Enable MDMX resources */
 543 #define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
 544 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 545 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 546 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
 547 /* Bits reserved for implementations:  */
 548 #define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 549
 550 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 551 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 552 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 553 #define cause_CE_shift    28
 554 #define cause_EXC2_mask   0x00070000
 555 #define cause_EXC2_shift  16
 556 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 557 #define cause_SIOP        (1 << 12)     /* SIO pending */
 558 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 559 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 560
 561 #define cause_EXC_mask  (0x1c)          /* Exception code */
 562 #define cause_EXC_shift (2)
 563
 564 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 565 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 566 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 567 #define cause_IP_shift  (10)
 568
 569 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 570 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 571
 572
 573 /* NOTE: We keep the following status flags as bit values (1 for true,
 574    0 for false). This allows them to be used in binary boolean
 575    operations without worrying about what exactly the non-zero true
 576    value is. */
 577
 578 /* UserMode */
 579 #ifdef SUBTARGET_R3900
 580 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 581 #else
 582 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 583 #endif /* SUBTARGET_R3900 */
 584
 585 /* BigEndianMem */
 586 /* Hardware configuration. Affects endianness of LoadMemory and
 587    StoreMemory and the endianness of Kernel and Supervisor mode
 588    execution. The value is 0 for little-endian; 1 for big-endian. */
 589 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 590 /*(state & simBE) ? 1 : 0)*/
 591
 592 /* ReverseEndian */
 593 /* This mode is selected if in User mode with the RE bit being set in
 594    SR (Status Register). It reverses the endianness of load and store
 595    instructions. */
 596 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 597
 598 /* BigEndianCPU */
 599 /* The endianness for load and store instructions (0=little;1=big). In
 600    User mode this endianness may be switched by setting the state_RE
 601    bit in the SR register. Thus, BigEndianCPU may be computed as
 602    (BigEndianMem EOR ReverseEndian). */
 603 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 604
 605
 606
 607 /* Exceptions: */
 608
 609 /* NOTE: These numbers depend on the processor architecture being
 610    simulated: */
 611 enum ExceptionCause {
 612   Interrupt               = 0,
 613   TLBModification         = 1,
 614   TLBLoad                 = 2,
 615   TLBStore                = 3,
 616   AddressLoad             = 4,
 617   AddressStore            = 5,
 618   InstructionFetch        = 6,
 619   DataReference           = 7,
 620   SystemCall              = 8,
 621   BreakPoint              = 9,
 622   ReservedInstruction     = 10,
 623   CoProcessorUnusable     = 11,
 624   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 625   Trap                    = 13,
 626   FPE                     = 15,
 627   DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
 628   MDMX                    = 22,
 629   Watch                   = 23,
 630   MCheck                  = 24,
 631   CacheErr                = 30,
 632   NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
 633
 634
 635 /* The following exception code is actually private to the simulator
 636    world. It is *NOT* a processor feature, and is used to signal
 637    run-time errors in the simulator. */
 638   SimulatorFault          = 0xFFFFFFFF
 639 };
 640
 641 #define TLB_REFILL  (0)
 642 #define TLB_INVALID (1)
 643
 644
 645 /* The following break instructions are reserved for use by the
 646    simulator.  The first is used to halt the simulation.  The second
 647    is used by gdb for break-points.  NOTE: Care must be taken, since
 648    this value may be used in later revisions of the MIPS ISA. */
 649 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 650
 651 #define HALT_INSTRUCTION        (0x03ff000d)
 652 #define HALT_INSTRUCTION2       (0x0000ffcd)
 653
 654
 655 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 656 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 657
 658
 659
 660 void interrupt_event (SIM_DESC sd, void *data);
 661
 662 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 663 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 664 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 665 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 666 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 667 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 668 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 669 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 670 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 671 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 672 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
 673 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 674 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 675 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 676 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 677 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 678 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 679 #define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
 680 #define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
 681 #define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
 682 #define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
 683
 684 /* Co-processor accesses */
 685
 686 /* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
 687 #define COP_Usable(coproc_num)          (coproc_num == 1)
 688
 689 void cop_lw  (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
 690 void cop_ld  (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
 691 unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
 692 uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
 693
 694 #define COP_LW(coproc_num,coproc_reg,memword) \
 695 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 696 #define COP_LD(coproc_num,coproc_reg,memword) \
 697 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 698 #define COP_SW(coproc_num,coproc_reg) \
 699 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 700 #define COP_SD(coproc_num,coproc_reg) \
 701 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 702
 703
 704 void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction);
 705 #define DecodeCoproc(instruction) \
 706 decode_coproc (SD, CPU, cia, (instruction))
 707
 708 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 709
 710
 711 /* FPR access.  */
 712 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
 713 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
 714 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
 715 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
 716 unsigned64 ps_lower (SIM_STATE, unsigned64 op);
 717 #define PSLower(op) ps_lower (SIM_ARGS, op)
 718 unsigned64 ps_upper (SIM_STATE, unsigned64 op);
 719 #define PSUpper(op) ps_upper (SIM_ARGS, op)
 720 unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
 721 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
 722
 723
 724 /* FCR access.  */
 725 unsigned_word value_fcr (SIM_STATE, int fcr);
 726 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
 727 void store_fcr (SIM_STATE, int fcr, unsigned_word value);
 728 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
 729 void test_fcsr (SIM_STATE);
 730 #define TestFCSR() test_fcsr (SIM_ARGS)
 731
 732
 733 /* FPU operations.  */
 734 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
 735 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
 736 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
 737 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
 738 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
 739 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
 740 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 741 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
 742 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 743 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
 744 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 745 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
 746 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 747 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
 748 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
 749 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
 750 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 751 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
 752 unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
 753 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
 754 unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
 755                     unsigned64 op3, FP_formats fmt);
 756 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
 757 unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
 758                     unsigned64 op3, FP_formats fmt);
 759 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
 760 unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
 761                      unsigned64 op3, FP_formats fmt);
 762 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
 763 unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
 764                      unsigned64 op3, FP_formats fmt);
 765 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
 766 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
 767 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
 768 unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
 769                        FP_formats to);
 770 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
 771
 772
 773 /* MIPS-3D ASE operations.  */
 774 #define CompareAbs(op1,op2,fmt,cond,cc) \
 775 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
 776 unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 777 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
 778 unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 779 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
 780 unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
 781 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
 782 unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 783 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
 784 unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
 785 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
 786 unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
 787 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
 788
 789
 790 /* MDMX access.  */
 791
 792 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 793 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
 794 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
 795
 796 #define fmt_mdmx fmt_uninterpreted
 797
 798 #define MX_VECT_AND  (0)
 799 #define MX_VECT_NOR  (1)
 800 #define MX_VECT_OR   (2)
 801 #define MX_VECT_XOR  (3)
 802 #define MX_VECT_SLL  (4)
 803 #define MX_VECT_SRL  (5)
 804 #define MX_VECT_ADD  (6)
 805 #define MX_VECT_SUB  (7)
 806 #define MX_VECT_MIN  (8)
 807 #define MX_VECT_MAX  (9)
 808 #define MX_VECT_MUL  (10)
 809 #define MX_VECT_MSGN (11)
 810 #define MX_VECT_SRA  (12)
 811 #define MX_VECT_ABSD (13)               /* SB-1 only.  */
 812 #define MX_VECT_AVG  (14)               /* SB-1 only.  */
 813
 814 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 815 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
 816 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
 817 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
 818 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
 819 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
 820 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
 821 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
 822 #define MX_Or(op1,vt,fmtsel)  mdmx_cpr_op(SIM_ARGS, MX_VECT_OR,  op1, vt, fmtsel)
 823 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
 824 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
 825 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
 826 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
 827 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
 828 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
 829 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
 830
 831 #define MX_C_EQ  0x1
 832 #define MX_C_LT  0x4
 833
 834 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 835 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
 836
 837 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 838 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
 839
 840 #define MX_VECT_ADDA  (0)
 841 #define MX_VECT_ADDL  (1)
 842 #define MX_VECT_MULA  (2)
 843 #define MX_VECT_MULL  (3)
 844 #define MX_VECT_MULS  (4)
 845 #define MX_VECT_MULSL (5)
 846 #define MX_VECT_SUBA  (6)
 847 #define MX_VECT_SUBL  (7)
 848 #define MX_VECT_ABSDA (8)               /* SB-1 only.  */
 849
 850 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 851 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
 852 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
 853 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
 854 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
 855 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
 856 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
 857 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
 858 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
 859 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
 860
 861 #define MX_FMT_OB   (0)
 862 #define MX_FMT_QH   (1)
 863
 864 /* The following codes chosen to indicate the units of shift.  */
 865 #define MX_RAC_L    (0)
 866 #define MX_RAC_M    (1)
 867 #define MX_RAC_H    (2)
 868
 869 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
 870 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
 871
 872 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
 873 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
 874 void mdmx_wach (SIM_STATE, int, unsigned64);
 875 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
 876
 877 #define MX_RND_AS   (0)
 878 #define MX_RND_AU   (1)
 879 #define MX_RND_ES   (2)
 880 #define MX_RND_EU   (3)
 881 #define MX_RND_ZS   (4)
 882 #define MX_RND_ZU   (5)
 883
 884 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
 885 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
 886 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
 887 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
 888 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
 889 #define MX_RZS(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
 890 #define MX_RZU(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
 891
 892 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
 893 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
 894
 895
 896
 897 /* Memory accesses */
 898
 899 /* The following are generic to all versions of the MIPS architecture
 900    to date: */
 901
 902 /* Memory Access Types (for CCA): */
 903 #define Uncached                (0)
 904 #define CachedNoncoherent       (1)
 905 #define CachedCoherent          (2)
 906 #define Cached                  (3)
 907
 908 #define isINSTRUCTION   (1 == 0) /* FALSE */
 909 #define isDATA          (1 == 1) /* TRUE */
 910 #define isLOAD          (1 == 0) /* FALSE */
 911 #define isSTORE         (1 == 1) /* TRUE */
 912 #define isREAL          (1 == 0) /* FALSE */
 913 #define isRAW           (1 == 1) /* TRUE */
 914 /* The parameter HOST (isTARGET / isHOST) is ignored */
 915 #define isTARGET        (1 == 0) /* FALSE */
 916 /* #define isHOST          (1 == 1) TRUE */
 917
 918 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 919    is the number of bytes minus 1. */
 920 #define AccessLength_BYTE       (0)
 921 #define AccessLength_HALFWORD   (1)
 922 #define AccessLength_TRIPLEBYTE (2)
 923 #define AccessLength_WORD       (3)
 924 #define AccessLength_QUINTIBYTE (4)
 925 #define AccessLength_SEXTIBYTE  (5)
 926 #define AccessLength_SEPTIBYTE  (6)
 927 #define AccessLength_DOUBLEWORD (7)
 928 #define AccessLength_QUADWORD   (15)
 929
 930 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 931                     ? AccessLength_DOUBLEWORD /*7*/ \
 932                     : AccessLength_WORD /*3*/)
 933 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 934
 935
 936 INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
 937 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 938 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 939
 940 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
 941 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 942 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 943
 944 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
 945 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 946 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 947
 948 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
 949 #define CacheOp(op,pAddr,vAddr,instruction) \
 950 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 951
 952 INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
 953 #define SyncOperation(stype) \
 954 sync_operation (SD, CPU, cia, (stype))
 955
 956 INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
 957 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 958 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 959
 960 void unpredictable_action (sim_cpu *cpu, address_word cia);
 961 #define NotWordValue(val)       not_word_value (SD_, (val))
 962 #define Unpredictable()         unpredictable (SD_)
 963 #define UnpredictableResult()   /* For now, do nothing.  */
 964
 965 INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
 966 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 967 INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
 968 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 969 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 970
 971 void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...);
 972 extern FILE *tracefh;
 973
 974 extern int DSPLO_REGNUM[4];
 975 extern int DSPHI_REGNUM[4];
 976
 977 INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
 978 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 979
 980 char* pr_addr (SIM_ADDR addr);
 981 char* pr_uword64 (uword64 addr);
 982
 983
 984 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
 985
 986 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 987 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 988 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 989
 990 #ifdef MIPS_MACH_MULTI
 991 extern int mips_mach_multi(SIM_DESC sd);
 992 #define MIPS_MACH(SD)   mips_mach_multi(SD)
 993 #else
 994 #define MIPS_MACH(SD)   MIPS_MACH_DEFAULT
 995 #endif
 996
 997 /* Macros for determining whether a MIPS IV or MIPS V part is subject
 998    to the hi/lo restrictions described in mips.igen.  */
 999
1000 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
1001   (MIPS_MACH (SD) != bfd_mach_mips5500)
1002
1003 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
1004   (MIPS_MACH (SD) != bfd_mach_mips5500)
1005
1006 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
1007   (MIPS_MACH (SD) != bfd_mach_mips5500)
1008
1009 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1010 #include "sim-main.c"
1011 #endif
1012
1013 #endif